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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.20 96.89 91.99 97.67 100.00 98.28 97.45 98.14


Total test records in report: 468
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T296 /workspace/coverage/default/45.rom_ctrl_smoke.2476003094 Jul 02 08:02:32 AM PDT 24 Jul 02 08:02:58 AM PDT 24 268472408 ps
T297 /workspace/coverage/default/0.rom_ctrl_smoke.1890914770 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:03 AM PDT 24 750573340 ps
T298 /workspace/coverage/default/36.rom_ctrl_alert_test.4246537888 Jul 02 08:02:14 AM PDT 24 Jul 02 08:02:42 AM PDT 24 1559511110 ps
T299 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3080898976 Jul 02 08:01:52 AM PDT 24 Jul 02 08:02:32 AM PDT 24 9863471620 ps
T300 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.556831818 Jul 02 08:02:10 AM PDT 24 Jul 02 08:02:38 AM PDT 24 7735837674 ps
T301 /workspace/coverage/default/14.rom_ctrl_stress_all.2628991800 Jul 02 08:01:57 AM PDT 24 Jul 02 08:03:18 AM PDT 24 26910338262 ps
T302 /workspace/coverage/default/7.rom_ctrl_smoke.2828445196 Jul 02 08:02:05 AM PDT 24 Jul 02 08:02:57 AM PDT 24 3459701363 ps
T303 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1408215090 Jul 02 08:02:00 AM PDT 24 Jul 02 08:02:27 AM PDT 24 5463466926 ps
T304 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.403053071 Jul 02 08:02:15 AM PDT 24 Jul 02 08:04:35 AM PDT 24 2312982107 ps
T305 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2834084682 Jul 02 08:02:06 AM PDT 24 Jul 02 08:02:32 AM PDT 24 5283060967 ps
T306 /workspace/coverage/default/35.rom_ctrl_smoke.2750002744 Jul 02 08:02:25 AM PDT 24 Jul 02 08:02:51 AM PDT 24 716637725 ps
T307 /workspace/coverage/default/17.rom_ctrl_smoke.777151175 Jul 02 08:02:11 AM PDT 24 Jul 02 08:03:04 AM PDT 24 18254558818 ps
T308 /workspace/coverage/default/42.rom_ctrl_stress_all.3642049614 Jul 02 08:02:33 AM PDT 24 Jul 02 08:03:08 AM PDT 24 3510855603 ps
T309 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1992700883 Jul 02 08:01:43 AM PDT 24 Jul 02 08:02:09 AM PDT 24 471457361 ps
T310 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4097854128 Jul 02 08:02:04 AM PDT 24 Jul 02 08:05:23 AM PDT 24 38314122359 ps
T25 /workspace/coverage/default/1.rom_ctrl_sec_cm.4033405177 Jul 02 08:01:50 AM PDT 24 Jul 02 08:02:57 AM PDT 24 285068138 ps
T311 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3306039276 Jul 02 08:02:03 AM PDT 24 Jul 02 08:02:49 AM PDT 24 7670195822 ps
T312 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1917634855 Jul 02 08:02:10 AM PDT 24 Jul 02 08:02:31 AM PDT 24 100419665 ps
T313 /workspace/coverage/default/10.rom_ctrl_smoke.214369632 Jul 02 08:02:01 AM PDT 24 Jul 02 08:02:54 AM PDT 24 17438721739 ps
T314 /workspace/coverage/default/19.rom_ctrl_smoke.4255993336 Jul 02 08:02:06 AM PDT 24 Jul 02 08:02:32 AM PDT 24 188275261 ps
T315 /workspace/coverage/default/6.rom_ctrl_stress_all.32197025 Jul 02 08:01:49 AM PDT 24 Jul 02 08:03:09 AM PDT 24 25637346703 ps
T316 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3513509281 Jul 02 08:02:15 AM PDT 24 Jul 02 08:02:35 AM PDT 24 99830886 ps
T317 /workspace/coverage/default/27.rom_ctrl_smoke.4114645056 Jul 02 08:02:11 AM PDT 24 Jul 02 08:02:51 AM PDT 24 4220079659 ps
T318 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1005735890 Jul 02 08:02:33 AM PDT 24 Jul 02 08:06:36 AM PDT 24 75670691164 ps
T319 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3514200460 Jul 02 08:02:11 AM PDT 24 Jul 02 08:02:42 AM PDT 24 12370708856 ps
T320 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1431114631 Jul 02 08:02:29 AM PDT 24 Jul 02 08:03:01 AM PDT 24 17706571698 ps
T321 /workspace/coverage/default/37.rom_ctrl_alert_test.2117134732 Jul 02 08:02:15 AM PDT 24 Jul 02 08:02:42 AM PDT 24 1930053843 ps
T322 /workspace/coverage/default/49.rom_ctrl_alert_test.3843128063 Jul 02 08:02:44 AM PDT 24 Jul 02 08:03:08 AM PDT 24 2058789262 ps
T323 /workspace/coverage/default/39.rom_ctrl_smoke.1964632990 Jul 02 08:02:28 AM PDT 24 Jul 02 08:03:18 AM PDT 24 14147308356 ps
T324 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2308839862 Jul 02 08:02:15 AM PDT 24 Jul 02 08:02:38 AM PDT 24 831084575 ps
T325 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.901246211 Jul 02 08:02:04 AM PDT 24 Jul 02 08:04:18 AM PDT 24 2683036618 ps
T326 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4211424426 Jul 02 08:02:05 AM PDT 24 Jul 02 08:04:14 AM PDT 24 3678498324 ps
T327 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1078281982 Jul 02 08:02:06 AM PDT 24 Jul 02 08:05:32 AM PDT 24 20006996379 ps
T328 /workspace/coverage/default/22.rom_ctrl_alert_test.3210754309 Jul 02 08:01:59 AM PDT 24 Jul 02 08:02:26 AM PDT 24 13138763254 ps
T329 /workspace/coverage/default/24.rom_ctrl_alert_test.3798100221 Jul 02 08:02:18 AM PDT 24 Jul 02 08:02:41 AM PDT 24 1245618411 ps
T330 /workspace/coverage/default/35.rom_ctrl_alert_test.4269141334 Jul 02 08:02:23 AM PDT 24 Jul 02 08:02:48 AM PDT 24 943035959 ps
T331 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1904690598 Jul 02 08:02:15 AM PDT 24 Jul 02 08:08:24 AM PDT 24 63404982819 ps
T332 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1876285655 Jul 02 08:02:21 AM PDT 24 Jul 02 08:03:03 AM PDT 24 6365698007 ps
T333 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.695592633 Jul 02 08:02:17 AM PDT 24 Jul 02 08:02:42 AM PDT 24 371420352 ps
T334 /workspace/coverage/default/30.rom_ctrl_smoke.784577457 Jul 02 08:02:11 AM PDT 24 Jul 02 08:02:36 AM PDT 24 192349507 ps
T335 /workspace/coverage/default/44.rom_ctrl_stress_all.1251360099 Jul 02 08:02:22 AM PDT 24 Jul 02 08:03:32 AM PDT 24 13267588313 ps
T336 /workspace/coverage/default/22.rom_ctrl_stress_all.3345583604 Jul 02 08:02:16 AM PDT 24 Jul 02 08:03:35 AM PDT 24 5659953502 ps
T337 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2403697738 Jul 02 08:02:08 AM PDT 24 Jul 02 08:02:30 AM PDT 24 1236546128 ps
T338 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.199204245 Jul 02 08:02:11 AM PDT 24 Jul 02 08:02:40 AM PDT 24 1610682409 ps
T339 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.817543441 Jul 02 08:01:30 AM PDT 24 Jul 02 08:08:25 AM PDT 24 36614488111 ps
T340 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1802208577 Jul 02 08:02:22 AM PDT 24 Jul 02 08:05:22 AM PDT 24 11988373220 ps
T341 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1483740407 Jul 02 08:01:58 AM PDT 24 Jul 02 08:02:22 AM PDT 24 2593984218 ps
T342 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3777770719 Jul 02 08:02:06 AM PDT 24 Jul 02 08:06:12 AM PDT 24 12019474601 ps
T343 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2352522465 Jul 02 08:02:37 AM PDT 24 Jul 02 08:03:03 AM PDT 24 243142735 ps
T344 /workspace/coverage/default/38.rom_ctrl_stress_all.1702593738 Jul 02 08:02:26 AM PDT 24 Jul 02 08:03:38 AM PDT 24 5333066460 ps
T345 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2831413182 Jul 02 08:02:04 AM PDT 24 Jul 02 08:02:44 AM PDT 24 4082322054 ps
T346 /workspace/coverage/default/29.rom_ctrl_smoke.2851924790 Jul 02 08:02:14 AM PDT 24 Jul 02 08:02:49 AM PDT 24 1842152223 ps
T347 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3707784083 Jul 02 08:02:13 AM PDT 24 Jul 02 08:26:13 AM PDT 24 71960731748 ps
T348 /workspace/coverage/default/1.rom_ctrl_stress_all.4185960268 Jul 02 08:01:40 AM PDT 24 Jul 02 08:02:38 AM PDT 24 8424535273 ps
T349 /workspace/coverage/default/49.rom_ctrl_smoke.4093797275 Jul 02 08:02:28 AM PDT 24 Jul 02 08:03:06 AM PDT 24 2027739117 ps
T350 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2901891132 Jul 02 08:02:14 AM PDT 24 Jul 02 08:02:56 AM PDT 24 3250898211 ps
T351 /workspace/coverage/default/0.rom_ctrl_alert_test.3670903885 Jul 02 08:01:51 AM PDT 24 Jul 02 08:02:23 AM PDT 24 8372400855 ps
T352 /workspace/coverage/default/20.rom_ctrl_stress_all.3387601267 Jul 02 08:02:13 AM PDT 24 Jul 02 08:03:00 AM PDT 24 7979942487 ps
T353 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2790750711 Jul 02 08:02:11 AM PDT 24 Jul 02 08:31:05 AM PDT 24 94416551046 ps
T354 /workspace/coverage/default/9.rom_ctrl_stress_all.2161461648 Jul 02 08:02:01 AM PDT 24 Jul 02 08:02:41 AM PDT 24 11866565910 ps
T355 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1398528150 Jul 02 08:01:54 AM PDT 24 Jul 02 08:06:59 AM PDT 24 166331343503 ps
T356 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1335370333 Jul 02 08:02:15 AM PDT 24 Jul 02 08:02:41 AM PDT 24 4313701925 ps
T357 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3859523980 Jul 02 08:02:08 AM PDT 24 Jul 02 08:02:37 AM PDT 24 1649564490 ps
T358 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.754510019 Jul 02 08:02:27 AM PDT 24 Jul 02 08:02:50 AM PDT 24 307820087 ps
T359 /workspace/coverage/default/12.rom_ctrl_smoke.3204891982 Jul 02 08:02:11 AM PDT 24 Jul 02 08:02:57 AM PDT 24 15717346535 ps
T360 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1653460156 Jul 02 08:02:08 AM PDT 24 Jul 02 08:05:52 AM PDT 24 21086888617 ps
T361 /workspace/coverage/default/11.rom_ctrl_stress_all.2497884107 Jul 02 08:01:56 AM PDT 24 Jul 02 08:02:47 AM PDT 24 2471250270 ps
T362 /workspace/coverage/default/20.rom_ctrl_alert_test.365631537 Jul 02 08:02:08 AM PDT 24 Jul 02 08:02:32 AM PDT 24 866423943 ps
T363 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.753625834 Jul 02 08:02:12 AM PDT 24 Jul 02 08:02:43 AM PDT 24 1077026598 ps
T364 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.875089923 Jul 02 08:02:04 AM PDT 24 Jul 02 08:02:42 AM PDT 24 2623818230 ps
T365 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3054909883 Jul 02 08:02:00 AM PDT 24 Jul 02 08:02:20 AM PDT 24 517079009 ps
T366 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2388159129 Jul 02 08:02:16 AM PDT 24 Jul 02 08:02:46 AM PDT 24 6362278296 ps
T367 /workspace/coverage/default/24.rom_ctrl_smoke.1542852544 Jul 02 08:02:06 AM PDT 24 Jul 02 08:02:50 AM PDT 24 3002603797 ps
T47 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.385785354 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:03 AM PDT 24 1066446974 ps
T48 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1930383493 Jul 02 08:01:37 AM PDT 24 Jul 02 08:02:12 AM PDT 24 38493051993 ps
T49 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1630131576 Jul 02 08:01:47 AM PDT 24 Jul 02 08:02:12 AM PDT 24 2972230843 ps
T53 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1803929188 Jul 02 08:01:39 AM PDT 24 Jul 02 08:02:11 AM PDT 24 6238656107 ps
T92 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1877075337 Jul 02 08:01:28 AM PDT 24 Jul 02 08:02:00 AM PDT 24 1547495510 ps
T54 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2648439721 Jul 02 08:01:39 AM PDT 24 Jul 02 08:02:41 AM PDT 24 16996957924 ps
T44 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2560994672 Jul 02 08:01:34 AM PDT 24 Jul 02 08:03:11 AM PDT 24 18334112455 ps
T45 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2578313248 Jul 02 08:01:41 AM PDT 24 Jul 02 08:03:08 AM PDT 24 245199549 ps
T55 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4043474460 Jul 02 08:01:24 AM PDT 24 Jul 02 08:01:50 AM PDT 24 221333355 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1269310597 Jul 02 08:01:16 AM PDT 24 Jul 02 08:01:44 AM PDT 24 255256725 ps
T369 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1958532197 Jul 02 08:01:37 AM PDT 24 Jul 02 08:02:16 AM PDT 24 18746954321 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3742118588 Jul 02 08:01:45 AM PDT 24 Jul 02 08:02:14 AM PDT 24 6093211820 ps
T56 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3237521887 Jul 02 08:01:35 AM PDT 24 Jul 02 08:03:00 AM PDT 24 7169586703 ps
T57 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3924633765 Jul 02 08:01:16 AM PDT 24 Jul 02 08:01:53 AM PDT 24 1482045012 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3274476859 Jul 02 08:01:19 AM PDT 24 Jul 02 08:01:51 AM PDT 24 1286931837 ps
T96 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1784038457 Jul 02 08:01:36 AM PDT 24 Jul 02 08:02:47 AM PDT 24 3998274387 ps
T46 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1529170496 Jul 02 08:01:47 AM PDT 24 Jul 02 08:03:20 AM PDT 24 1656235820 ps
T89 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2550180029 Jul 02 08:01:45 AM PDT 24 Jul 02 08:02:07 AM PDT 24 261875370 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1731464535 Jul 02 08:01:52 AM PDT 24 Jul 02 08:02:14 AM PDT 24 85538008 ps
T101 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1733733184 Jul 02 08:01:34 AM PDT 24 Jul 02 08:02:34 AM PDT 24 1016795133 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.335356208 Jul 02 08:01:21 AM PDT 24 Jul 02 08:02:24 AM PDT 24 2279449137 ps
T58 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3232925738 Jul 02 08:01:30 AM PDT 24 Jul 02 08:02:02 AM PDT 24 2850040598 ps
T59 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1014902100 Jul 02 08:01:33 AM PDT 24 Jul 02 08:01:56 AM PDT 24 88084705 ps
T60 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3725572602 Jul 02 08:01:31 AM PDT 24 Jul 02 08:02:17 AM PDT 24 2149010732 ps
T67 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1190461147 Jul 02 08:01:31 AM PDT 24 Jul 02 08:02:08 AM PDT 24 1833095368 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.82479742 Jul 02 08:01:20 AM PDT 24 Jul 02 08:01:52 AM PDT 24 8012533926 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.517402007 Jul 02 08:01:34 AM PDT 24 Jul 02 08:02:01 AM PDT 24 1273838056 ps
T90 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1334777737 Jul 02 08:01:51 AM PDT 24 Jul 02 08:02:19 AM PDT 24 6106697572 ps
T103 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2033510862 Jul 02 08:01:35 AM PDT 24 Jul 02 08:03:08 AM PDT 24 1977762148 ps
T68 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.14713858 Jul 02 08:01:49 AM PDT 24 Jul 02 08:02:29 AM PDT 24 1267464273 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3729230219 Jul 02 08:01:37 AM PDT 24 Jul 02 08:02:08 AM PDT 24 1051177468 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1809121272 Jul 02 08:01:45 AM PDT 24 Jul 02 08:02:06 AM PDT 24 347907325 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1800634966 Jul 02 08:01:30 AM PDT 24 Jul 02 08:01:54 AM PDT 24 85890112 ps
T376 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1134631423 Jul 02 08:01:39 AM PDT 24 Jul 02 08:02:11 AM PDT 24 5501789414 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1130684124 Jul 02 08:01:46 AM PDT 24 Jul 02 08:02:18 AM PDT 24 1845178551 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3492560582 Jul 02 08:01:19 AM PDT 24 Jul 02 08:01:44 AM PDT 24 88039362 ps
T91 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2702558612 Jul 02 08:01:37 AM PDT 24 Jul 02 08:01:59 AM PDT 24 89036963 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3381900466 Jul 02 08:01:38 AM PDT 24 Jul 02 08:02:04 AM PDT 24 534346382 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2631380589 Jul 02 08:01:19 AM PDT 24 Jul 02 08:01:50 AM PDT 24 986806752 ps
T381 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3995421175 Jul 02 08:01:28 AM PDT 24 Jul 02 08:01:51 AM PDT 24 1298093931 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1252151158 Jul 02 08:01:36 AM PDT 24 Jul 02 08:02:11 AM PDT 24 17742056294 ps
T383 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3301744421 Jul 02 08:01:43 AM PDT 24 Jul 02 08:02:13 AM PDT 24 6233957207 ps
T102 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2224022587 Jul 02 08:01:40 AM PDT 24 Jul 02 08:02:38 AM PDT 24 1831693691 ps
T69 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1544615696 Jul 02 08:01:32 AM PDT 24 Jul 02 08:02:56 AM PDT 24 25650447203 ps
T70 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1526221615 Jul 02 08:01:49 AM PDT 24 Jul 02 08:02:32 AM PDT 24 3160035242 ps
T384 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2981345097 Jul 02 08:01:39 AM PDT 24 Jul 02 08:02:14 AM PDT 24 4103938624 ps
T71 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2401273096 Jul 02 08:01:33 AM PDT 24 Jul 02 08:03:06 AM PDT 24 8155810493 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2867857231 Jul 02 08:01:27 AM PDT 24 Jul 02 08:01:58 AM PDT 24 23043600459 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.805956473 Jul 02 08:01:24 AM PDT 24 Jul 02 08:02:02 AM PDT 24 690471255 ps
T386 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2312593450 Jul 02 08:01:41 AM PDT 24 Jul 02 08:02:07 AM PDT 24 3085918145 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1168360358 Jul 02 08:01:36 AM PDT 24 Jul 02 08:02:09 AM PDT 24 976565757 ps
T104 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2351484208 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:40 AM PDT 24 11386628587 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4022171399 Jul 02 08:01:32 AM PDT 24 Jul 02 08:02:05 AM PDT 24 6361221225 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1527531915 Jul 02 08:01:29 AM PDT 24 Jul 02 08:02:03 AM PDT 24 8125951648 ps
T98 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.748373024 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:30 AM PDT 24 391341266 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2641304235 Jul 02 08:01:29 AM PDT 24 Jul 02 08:02:01 AM PDT 24 882301471 ps
T391 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.203189406 Jul 02 08:01:30 AM PDT 24 Jul 02 08:02:00 AM PDT 24 1460411160 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1307465608 Jul 02 08:01:17 AM PDT 24 Jul 02 08:01:46 AM PDT 24 2092545597 ps
T99 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3331562901 Jul 02 08:01:28 AM PDT 24 Jul 02 08:02:23 AM PDT 24 607142231 ps
T393 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3475313502 Jul 02 08:01:31 AM PDT 24 Jul 02 08:02:00 AM PDT 24 1150535922 ps
T394 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.989524373 Jul 02 08:01:33 AM PDT 24 Jul 02 08:02:28 AM PDT 24 1531613510 ps
T395 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.581445889 Jul 02 08:01:45 AM PDT 24 Jul 02 08:02:06 AM PDT 24 689603857 ps
T73 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1225024594 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:21 AM PDT 24 560341032 ps
T100 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.292726086 Jul 02 08:01:29 AM PDT 24 Jul 02 08:02:59 AM PDT 24 2424481685 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1321726550 Jul 02 08:01:19 AM PDT 24 Jul 02 08:01:49 AM PDT 24 867686679 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.651828331 Jul 02 08:01:32 AM PDT 24 Jul 02 08:02:05 AM PDT 24 1649901306 ps
T398 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4289344006 Jul 02 08:01:41 AM PDT 24 Jul 02 08:02:12 AM PDT 24 6330868132 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3222224959 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:02 AM PDT 24 691936837 ps
T400 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1008935457 Jul 02 08:01:38 AM PDT 24 Jul 02 08:02:03 AM PDT 24 190763832 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3076791283 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:11 AM PDT 24 3755847186 ps
T402 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2097766761 Jul 02 08:01:38 AM PDT 24 Jul 02 08:02:09 AM PDT 24 8976440617 ps
T403 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1917415641 Jul 02 08:01:42 AM PDT 24 Jul 02 08:02:14 AM PDT 24 1773506805 ps
T404 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1567091030 Jul 02 08:01:36 AM PDT 24 Jul 02 08:02:10 AM PDT 24 1485014287 ps
T405 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1384088142 Jul 02 08:01:41 AM PDT 24 Jul 02 08:02:09 AM PDT 24 5277820693 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.947596088 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:03 AM PDT 24 830666745 ps
T407 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3881131725 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:03 AM PDT 24 1032391958 ps
T408 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2387411864 Jul 02 08:01:41 AM PDT 24 Jul 02 08:02:07 AM PDT 24 513802280 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1729055933 Jul 02 08:01:34 AM PDT 24 Jul 02 08:02:00 AM PDT 24 3349245818 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.920742515 Jul 02 08:01:21 AM PDT 24 Jul 02 08:01:55 AM PDT 24 1630906493 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3084883226 Jul 02 08:01:27 AM PDT 24 Jul 02 08:02:00 AM PDT 24 11484458040 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3767321736 Jul 02 08:01:36 AM PDT 24 Jul 02 08:03:05 AM PDT 24 2310691049 ps
T74 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4257434365 Jul 02 08:01:17 AM PDT 24 Jul 02 08:01:52 AM PDT 24 5740816497 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3295561985 Jul 02 08:01:36 AM PDT 24 Jul 02 08:02:09 AM PDT 24 1746448077 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.894247158 Jul 02 08:01:22 AM PDT 24 Jul 02 08:01:50 AM PDT 24 12141787473 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1799610577 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:07 AM PDT 24 6625415891 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2562802847 Jul 02 08:01:21 AM PDT 24 Jul 02 08:02:22 AM PDT 24 3674171289 ps
T416 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1319273730 Jul 02 08:01:27 AM PDT 24 Jul 02 08:01:54 AM PDT 24 806240878 ps
T417 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.989311732 Jul 02 08:01:39 AM PDT 24 Jul 02 08:02:08 AM PDT 24 4341753087 ps
T108 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.778867101 Jul 02 08:01:37 AM PDT 24 Jul 02 08:02:41 AM PDT 24 3689501642 ps
T418 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1666105961 Jul 02 08:01:42 AM PDT 24 Jul 02 08:02:13 AM PDT 24 1790217113 ps
T419 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3094873458 Jul 02 08:01:40 AM PDT 24 Jul 02 08:02:15 AM PDT 24 1752814461 ps
T420 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.908341900 Jul 02 08:01:16 AM PDT 24 Jul 02 08:01:50 AM PDT 24 1949865413 ps
T421 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1934260206 Jul 02 08:01:19 AM PDT 24 Jul 02 08:01:52 AM PDT 24 1485945177 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4088460245 Jul 02 08:01:29 AM PDT 24 Jul 02 08:02:00 AM PDT 24 10081665561 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4134103031 Jul 02 08:01:49 AM PDT 24 Jul 02 08:03:12 AM PDT 24 388608536 ps
T423 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3038321184 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:02 AM PDT 24 2142543557 ps
T105 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3776793176 Jul 02 08:01:41 AM PDT 24 Jul 02 08:02:41 AM PDT 24 1628917279 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2254533812 Jul 02 08:01:37 AM PDT 24 Jul 02 08:02:13 AM PDT 24 1503021771 ps
T425 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.87992660 Jul 02 08:01:46 AM PDT 24 Jul 02 08:02:07 AM PDT 24 88234232 ps
T426 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3087162082 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:41 AM PDT 24 5130964412 ps
T75 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2402898470 Jul 02 08:01:18 AM PDT 24 Jul 02 08:01:50 AM PDT 24 1339372230 ps
T427 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2987963216 Jul 02 08:01:38 AM PDT 24 Jul 02 08:02:44 AM PDT 24 10176072481 ps
T428 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3035888181 Jul 02 08:01:19 AM PDT 24 Jul 02 08:01:56 AM PDT 24 2152865780 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2556429184 Jul 02 08:01:20 AM PDT 24 Jul 02 08:02:42 AM PDT 24 8377294001 ps
T430 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4169141338 Jul 02 08:01:46 AM PDT 24 Jul 02 08:02:14 AM PDT 24 4341127144 ps
T431 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2204284258 Jul 02 08:01:51 AM PDT 24 Jul 02 08:02:22 AM PDT 24 7392477816 ps
T432 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3444249898 Jul 02 08:01:47 AM PDT 24 Jul 02 08:03:38 AM PDT 24 53706332206 ps
T433 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2343659752 Jul 02 08:01:26 AM PDT 24 Jul 02 08:01:52 AM PDT 24 604584324 ps
T434 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.738452818 Jul 02 08:01:39 AM PDT 24 Jul 02 08:02:12 AM PDT 24 2992617946 ps
T435 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3889639606 Jul 02 08:01:25 AM PDT 24 Jul 02 08:01:50 AM PDT 24 423451316 ps
T436 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.669834821 Jul 02 08:01:51 AM PDT 24 Jul 02 08:02:23 AM PDT 24 2313925514 ps
T76 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4021090139 Jul 02 08:01:42 AM PDT 24 Jul 02 08:02:13 AM PDT 24 4660069556 ps
T437 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2040588790 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:03 AM PDT 24 1608149485 ps
T77 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3848989677 Jul 02 08:01:20 AM PDT 24 Jul 02 08:01:51 AM PDT 24 1209294496 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2629479247 Jul 02 08:01:15 AM PDT 24 Jul 02 08:01:40 AM PDT 24 88541726 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2353047364 Jul 02 08:01:20 AM PDT 24 Jul 02 08:02:23 AM PDT 24 1394764579 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.421916176 Jul 02 08:01:17 AM PDT 24 Jul 02 08:01:52 AM PDT 24 2121007724 ps
T441 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2470261022 Jul 02 08:01:18 AM PDT 24 Jul 02 08:02:20 AM PDT 24 5522554883 ps
T442 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2520462686 Jul 02 08:01:51 AM PDT 24 Jul 02 08:02:11 AM PDT 24 333205464 ps
T443 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2632722349 Jul 02 08:01:28 AM PDT 24 Jul 02 08:01:54 AM PDT 24 496907180 ps
T444 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1179945433 Jul 02 08:01:43 AM PDT 24 Jul 02 08:02:31 AM PDT 24 841321932 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2905284605 Jul 02 08:01:24 AM PDT 24 Jul 02 08:03:17 AM PDT 24 32376844454 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1069588648 Jul 02 08:01:50 AM PDT 24 Jul 02 08:02:17 AM PDT 24 898828867 ps
T447 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1845191601 Jul 02 08:01:35 AM PDT 24 Jul 02 08:02:09 AM PDT 24 5882751457 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1467188062 Jul 02 08:01:17 AM PDT 24 Jul 02 08:01:46 AM PDT 24 2140624493 ps
T449 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2346164198 Jul 02 08:01:48 AM PDT 24 Jul 02 08:02:11 AM PDT 24 96481984 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.785918563 Jul 02 08:01:43 AM PDT 24 Jul 02 08:02:16 AM PDT 24 7947393304 ps
T451 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2771969174 Jul 02 08:01:47 AM PDT 24 Jul 02 08:02:08 AM PDT 24 175276478 ps
T452 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1297108416 Jul 02 08:01:17 AM PDT 24 Jul 02 08:01:44 AM PDT 24 761403355 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3452732282 Jul 02 08:01:25 AM PDT 24 Jul 02 08:02:38 AM PDT 24 23623164861 ps
T454 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1661041199 Jul 02 08:01:32 AM PDT 24 Jul 02 08:02:50 AM PDT 24 29362596117 ps
T455 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2152517137 Jul 02 08:01:38 AM PDT 24 Jul 02 08:02:11 AM PDT 24 6989844216 ps
T456 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2595513826 Jul 02 08:01:21 AM PDT 24 Jul 02 08:01:47 AM PDT 24 556529627 ps
T457 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3892154747 Jul 02 08:01:27 AM PDT 24 Jul 02 08:01:56 AM PDT 24 1988224020 ps
T458 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2097697321 Jul 02 08:01:39 AM PDT 24 Jul 02 08:02:04 AM PDT 24 252153787 ps
T459 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.502492483 Jul 02 08:01:46 AM PDT 24 Jul 02 08:02:07 AM PDT 24 376676323 ps
T460 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1571733900 Jul 02 08:01:34 AM PDT 24 Jul 02 08:02:30 AM PDT 24 1983070747 ps
T461 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1356011524 Jul 02 08:01:19 AM PDT 24 Jul 02 08:01:43 AM PDT 24 99977080 ps
T462 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3520236033 Jul 02 08:01:37 AM PDT 24 Jul 02 08:02:06 AM PDT 24 1300466850 ps
T463 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2977234558 Jul 02 08:01:33 AM PDT 24 Jul 02 08:01:59 AM PDT 24 519767770 ps
T464 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.465226449 Jul 02 08:01:40 AM PDT 24 Jul 02 08:02:13 AM PDT 24 7644425650 ps
T465 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3782790628 Jul 02 08:01:45 AM PDT 24 Jul 02 08:02:12 AM PDT 24 1015531259 ps
T466 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1070743215 Jul 02 08:01:17 AM PDT 24 Jul 02 08:01:47 AM PDT 24 731496031 ps
T467 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1914976758 Jul 02 08:01:32 AM PDT 24 Jul 02 08:01:59 AM PDT 24 615696543 ps
T468 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1334291241 Jul 02 08:01:37 AM PDT 24 Jul 02 08:02:14 AM PDT 24 1844475056 ps

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.995890386
Short name T2
Test name
Test status
Simulation time 62214529218 ps
CPU time 213.87 seconds
Started Jul 02 08:02:29 AM PDT 24
Finished Jul 02 08:06:19 AM PDT 24
Peak memory 228648 kb
Host smart-948a01a6-fcfb-4b60-8ee2-ca30f9c4eb9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995890386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.995890386
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1369601930
Short name T12
Test name
Test status
Simulation time 216142281911 ps
CPU time 2159.33 seconds
Started Jul 02 08:02:05 AM PDT 24
Finished Jul 02 08:38:20 AM PDT 24
Peak memory 237192 kb
Host smart-be4b1db8-28cb-4160-a1cd-8f5878d864e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369601930 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1369601930
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3861200284
Short name T27
Test name
Test status
Simulation time 31027357110 ps
CPU time 148.08 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:04:55 AM PDT 24
Peak memory 213688 kb
Host smart-b4670ca0-e835-43eb-8c06-1e100385606f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861200284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3861200284
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2578313248
Short name T45
Test name
Test status
Simulation time 245199549 ps
CPU time 69.44 seconds
Started Jul 02 08:01:41 AM PDT 24
Finished Jul 02 08:03:08 AM PDT 24
Peak memory 212388 kb
Host smart-078d9663-50cd-48bc-8c2c-53ad10f34e58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578313248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2578313248
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.258169960
Short name T13
Test name
Test status
Simulation time 146459792033 ps
CPU time 628.27 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:12:51 AM PDT 24
Peak memory 230108 kb
Host smart-cf1fafa4-50f0-48d4-a416-bdb129dba7ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258169960 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.258169960
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.380391037
Short name T3
Test name
Test status
Simulation time 582295795 ps
CPU time 53.13 seconds
Started Jul 02 08:01:33 AM PDT 24
Finished Jul 02 08:02:45 AM PDT 24
Peak memory 236908 kb
Host smart-82a050c9-7f1c-47a1-a50f-2e62b1577f1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380391037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.380391037
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3237521887
Short name T56
Test name
Test status
Simulation time 7169586703 ps
CPU time 66.82 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:03:00 AM PDT 24
Peak memory 210816 kb
Host smart-92c12863-934e-48fa-af78-0c87fab9cd60
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237521887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3237521887
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1529170496
Short name T46
Test name
Test status
Simulation time 1656235820 ps
CPU time 75.73 seconds
Started Jul 02 08:01:47 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 212412 kb
Host smart-f111be83-8ffa-4b2c-ba9d-efcbe1894e69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529170496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1529170496
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3430061665
Short name T11
Test name
Test status
Simulation time 1581312682 ps
CPU time 26.05 seconds
Started Jul 02 08:02:16 AM PDT 24
Finished Jul 02 08:02:56 AM PDT 24
Peak memory 215660 kb
Host smart-f128314f-ed68-4cb0-96f0-8efa6ea34315
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430061665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3430061665
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2841777901
Short name T126
Test name
Test status
Simulation time 5119927332 ps
CPU time 12.13 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:37 AM PDT 24
Peak memory 211320 kb
Host smart-5c9b3e61-8cf3-451f-b3b7-21418c817608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841777901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2841777901
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4140788685
Short name T7
Test name
Test status
Simulation time 10430321348 ps
CPU time 26.3 seconds
Started Jul 02 08:01:38 AM PDT 24
Finished Jul 02 08:02:22 AM PDT 24
Peak memory 212336 kb
Host smart-4ee89ae6-0596-4824-af04-a1eb1b493ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140788685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4140788685
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.681617885
Short name T118
Test name
Test status
Simulation time 4423642796 ps
CPU time 28.84 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:02:25 AM PDT 24
Peak memory 212212 kb
Host smart-ecfb3eb7-7148-4dcd-b890-60c6e98e5322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681617885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.681617885
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3331562901
Short name T99
Test name
Test status
Simulation time 607142231 ps
CPU time 36.47 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:02:23 AM PDT 24
Peak memory 218968 kb
Host smart-987c9817-bf06-44c9-8a85-7c794be1b3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331562901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3331562901
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1784038457
Short name T96
Test name
Test status
Simulation time 3998274387 ps
CPU time 52.17 seconds
Started Jul 02 08:01:36 AM PDT 24
Finished Jul 02 08:02:47 AM PDT 24
Peak memory 210896 kb
Host smart-7f03fa6d-4426-4d40-813f-c7ed9ee1763f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784038457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1784038457
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2224022587
Short name T102
Test name
Test status
Simulation time 1831693691 ps
CPU time 40.16 seconds
Started Jul 02 08:01:40 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 211772 kb
Host smart-49e936fd-52ee-45e9-a6e8-dbf32ba9d074
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224022587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2224022587
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2351484208
Short name T104
Test name
Test status
Simulation time 11386628587 ps
CPU time 46.39 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:40 AM PDT 24
Peak memory 219020 kb
Host smart-18340edb-0e3b-4200-85af-e595cddfa310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351484208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2351484208
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4257434365
Short name T74
Test name
Test status
Simulation time 5740816497 ps
CPU time 15.9 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:52 AM PDT 24
Peak memory 210768 kb
Host smart-097e2c69-0325-4559-a32d-20b664c5e2b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257434365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4257434365
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1087595950
Short name T78
Test name
Test status
Simulation time 184060511 ps
CPU time 5.43 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:02:27 AM PDT 24
Peak memory 211400 kb
Host smart-651a93b6-9f1c-4772-a94c-32b40d6c4b5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087595950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1087595950
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.894247158
Short name T413
Test name
Test status
Simulation time 12141787473 ps
CPU time 8.68 seconds
Started Jul 02 08:01:22 AM PDT 24
Finished Jul 02 08:01:50 AM PDT 24
Peak memory 210772 kb
Host smart-ab57374a-8ecc-4873-bffb-736dff4be81c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894247158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.894247158
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2631380589
Short name T380
Test name
Test status
Simulation time 986806752 ps
CPU time 10.89 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:50 AM PDT 24
Peak memory 210712 kb
Host smart-2fd69098-4fb4-4876-ae8d-f0d04ad57cc3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631380589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2631380589
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2629479247
Short name T438
Test name
Test status
Simulation time 88541726 ps
CPU time 5.83 seconds
Started Jul 02 08:01:15 AM PDT 24
Finished Jul 02 08:01:40 AM PDT 24
Peak memory 210600 kb
Host smart-4780a2ef-9277-46a9-971a-80644eb15a23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629479247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2629479247
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.908341900
Short name T420
Test name
Test status
Simulation time 1949865413 ps
CPU time 15.04 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:50 AM PDT 24
Peak memory 219044 kb
Host smart-bebb18cc-c4ff-4059-83cb-85add0b4fffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908341900 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.908341900
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1877075337
Short name T92
Test name
Test status
Simulation time 1547495510 ps
CPU time 13.04 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:02:00 AM PDT 24
Peak memory 218036 kb
Host smart-25b04819-d1e3-4261-bb65-99ed5beb79a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877075337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1877075337
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1800634966
Short name T375
Test name
Test status
Simulation time 85890112 ps
CPU time 4.16 seconds
Started Jul 02 08:01:30 AM PDT 24
Finished Jul 02 08:01:54 AM PDT 24
Peak memory 210608 kb
Host smart-38aee722-4539-458e-a8ee-b11adebcff48
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800634966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1800634966
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1467188062
Short name T448
Test name
Test status
Simulation time 2140624493 ps
CPU time 10.43 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:46 AM PDT 24
Peak memory 210624 kb
Host smart-609d0072-3efa-4097-9f4e-bde5a38ccf33
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467188062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1467188062
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2556429184
Short name T429
Test name
Test status
Simulation time 8377294001 ps
CPU time 62.55 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:02:42 AM PDT 24
Peak memory 210824 kb
Host smart-bda3a281-659a-48ce-a899-03e512cca22e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556429184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2556429184
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1307465608
Short name T392
Test name
Test status
Simulation time 2092545597 ps
CPU time 9.76 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:46 AM PDT 24
Peak memory 210860 kb
Host smart-d869bccd-20c5-4ee0-b411-69688ac049ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307465608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1307465608
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1070743215
Short name T466
Test name
Test status
Simulation time 731496031 ps
CPU time 9.91 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:47 AM PDT 24
Peak memory 218948 kb
Host smart-73634d53-40d2-4971-9549-0ed3aa4e85c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070743215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1070743215
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.335356208
Short name T97
Test name
Test status
Simulation time 2279449137 ps
CPU time 38.43 seconds
Started Jul 02 08:01:21 AM PDT 24
Finished Jul 02 08:02:24 AM PDT 24
Peak memory 212264 kb
Host smart-aee4b03d-2c6f-49fd-be8a-d6823d780d69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335356208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.335356208
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1297108416
Short name T452
Test name
Test status
Simulation time 761403355 ps
CPU time 8.8 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:44 AM PDT 24
Peak memory 210752 kb
Host smart-696611b5-4343-41e4-940e-b7325b93a1bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297108416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1297108416
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.920742515
Short name T410
Test name
Test status
Simulation time 1630906493 ps
CPU time 13.5 seconds
Started Jul 02 08:01:21 AM PDT 24
Finished Jul 02 08:01:55 AM PDT 24
Peak memory 210664 kb
Host smart-9067e9be-a9c7-4c97-9ff7-0439d6438be7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920742515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.920742515
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.82479742
Short name T371
Test name
Test status
Simulation time 8012533926 ps
CPU time 12.4 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:01:52 AM PDT 24
Peak memory 219064 kb
Host smart-5f2ce443-0444-4740-8065-e3f2c6fd2d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82479742 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.82479742
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3520236033
Short name T462
Test name
Test status
Simulation time 1300466850 ps
CPU time 10.54 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:02:06 AM PDT 24
Peak memory 218000 kb
Host smart-34c1d641-7763-4df7-9b3e-7d65cfb052e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520236033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3520236033
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1319273730
Short name T416
Test name
Test status
Simulation time 806240878 ps
CPU time 8.67 seconds
Started Jul 02 08:01:27 AM PDT 24
Finished Jul 02 08:01:54 AM PDT 24
Peak memory 210652 kb
Host smart-6ead36c6-0ccf-448b-a7f8-9608aa891d18
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319273730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1319273730
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.421916176
Short name T440
Test name
Test status
Simulation time 2121007724 ps
CPU time 16.15 seconds
Started Jul 02 08:01:17 AM PDT 24
Finished Jul 02 08:01:52 AM PDT 24
Peak memory 210608 kb
Host smart-aa3de336-3a04-4cc4-bbd8-f3bc1acfab5a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421916176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
421916176
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3452732282
Short name T453
Test name
Test status
Simulation time 23623164861 ps
CPU time 53.25 seconds
Started Jul 02 08:01:25 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 217916 kb
Host smart-9ab4ce35-fe4a-4c92-9ed5-d710448c25cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452732282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3452732282
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1321726550
Short name T396
Test name
Test status
Simulation time 867686679 ps
CPU time 9.5 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:49 AM PDT 24
Peak memory 210840 kb
Host smart-276f7734-ba7a-47bc-ae67-5f0f698caeda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321726550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1321726550
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1269310597
Short name T368
Test name
Test status
Simulation time 255256725 ps
CPU time 9.13 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:44 AM PDT 24
Peak memory 218988 kb
Host smart-3879fad0-0a2f-4a69-adff-b9da2008f34a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269310597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1269310597
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2470261022
Short name T441
Test name
Test status
Simulation time 5522554883 ps
CPU time 42.24 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:02:20 AM PDT 24
Peak memory 219028 kb
Host smart-1e15e9fc-e392-405f-864a-8257a461510e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470261022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2470261022
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1799610577
Short name T414
Test name
Test status
Simulation time 6625415891 ps
CPU time 13.79 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:07 AM PDT 24
Peak memory 219084 kb
Host smart-ef94401b-ba8a-4650-b543-789718d2ef31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799610577 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1799610577
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3892154747
Short name T457
Test name
Test status
Simulation time 1988224020 ps
CPU time 10.17 seconds
Started Jul 02 08:01:27 AM PDT 24
Finished Jul 02 08:01:56 AM PDT 24
Peak memory 210744 kb
Host smart-88e2547e-09d3-4694-80ba-9ee8af062b1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892154747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3892154747
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1803929188
Short name T53
Test name
Test status
Simulation time 6238656107 ps
CPU time 14.98 seconds
Started Jul 02 08:01:39 AM PDT 24
Finished Jul 02 08:02:11 AM PDT 24
Peak memory 218972 kb
Host smart-55fd68e7-64c7-4027-a18a-88136b99b694
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803929188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1803929188
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1168360358
Short name T387
Test name
Test status
Simulation time 976565757 ps
CPU time 14.15 seconds
Started Jul 02 08:01:36 AM PDT 24
Finished Jul 02 08:02:09 AM PDT 24
Peak memory 218988 kb
Host smart-1f92c8cc-c6cf-446d-9b07-cec1bfe3f447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168360358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1168360358
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3995421175
Short name T381
Test name
Test status
Simulation time 1298093931 ps
CPU time 4.73 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:01:51 AM PDT 24
Peak memory 219016 kb
Host smart-157b4842-baad-4719-a6ea-3a1334b5ce8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995421175 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3995421175
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1384088142
Short name T405
Test name
Test status
Simulation time 5277820693 ps
CPU time 11.64 seconds
Started Jul 02 08:01:41 AM PDT 24
Finished Jul 02 08:02:09 AM PDT 24
Peak memory 210732 kb
Host smart-c7deb00a-861c-4d80-b520-2e04844237ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384088142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1384088142
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1179945433
Short name T444
Test name
Test status
Simulation time 841321932 ps
CPU time 31.36 seconds
Started Jul 02 08:01:43 AM PDT 24
Finished Jul 02 08:02:31 AM PDT 24
Peak memory 210732 kb
Host smart-fadc5556-9805-455a-8c31-ad7ed551c294
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179945433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1179945433
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2632722349
Short name T443
Test name
Test status
Simulation time 496907180 ps
CPU time 7.57 seconds
Started Jul 02 08:01:28 AM PDT 24
Finished Jul 02 08:01:54 AM PDT 24
Peak memory 218232 kb
Host smart-258e6d7a-05e2-4763-8f1f-94a9cb08fc19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632722349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2632722349
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2387411864
Short name T408
Test name
Test status
Simulation time 513802280 ps
CPU time 9.42 seconds
Started Jul 02 08:01:41 AM PDT 24
Finished Jul 02 08:02:07 AM PDT 24
Peak memory 218724 kb
Host smart-db02fb13-e74b-4027-9f8c-3d5349e1717d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387411864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2387411864
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1930383493
Short name T48
Test name
Test status
Simulation time 38493051993 ps
CPU time 16.94 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:02:12 AM PDT 24
Peak memory 219088 kb
Host smart-7a2e61a8-4e40-4c26-a24e-6dad8e238c01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930383493 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1930383493
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1190461147
Short name T67
Test name
Test status
Simulation time 1833095368 ps
CPU time 14.68 seconds
Started Jul 02 08:01:31 AM PDT 24
Finished Jul 02 08:02:08 AM PDT 24
Peak memory 218868 kb
Host smart-54db39a0-1fb4-4ef9-915b-163dc858522f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190461147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1190461147
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2401273096
Short name T71
Test name
Test status
Simulation time 8155810493 ps
CPU time 74.79 seconds
Started Jul 02 08:01:33 AM PDT 24
Finished Jul 02 08:03:06 AM PDT 24
Peak memory 210884 kb
Host smart-7b6825e6-1549-4a65-bcdc-8713fb2bea41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401273096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2401273096
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2771969174
Short name T451
Test name
Test status
Simulation time 175276478 ps
CPU time 4.25 seconds
Started Jul 02 08:01:47 AM PDT 24
Finished Jul 02 08:02:08 AM PDT 24
Peak memory 210840 kb
Host smart-97944840-3fc8-4ba2-9afa-f49cc3b02281
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771969174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2771969174
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3094873458
Short name T419
Test name
Test status
Simulation time 1752814461 ps
CPU time 16.77 seconds
Started Jul 02 08:01:40 AM PDT 24
Finished Jul 02 08:02:15 AM PDT 24
Peak memory 219000 kb
Host smart-0096f4eb-a301-4a97-89d6-485c03c4be07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094873458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3094873458
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4289344006
Short name T398
Test name
Test status
Simulation time 6330868132 ps
CPU time 13.66 seconds
Started Jul 02 08:01:41 AM PDT 24
Finished Jul 02 08:02:12 AM PDT 24
Peak memory 218812 kb
Host smart-c67626d9-31ef-4ecf-b9f6-d104a38c365b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289344006 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.4289344006
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3301744421
Short name T383
Test name
Test status
Simulation time 6233957207 ps
CPU time 12.06 seconds
Started Jul 02 08:01:43 AM PDT 24
Finished Jul 02 08:02:13 AM PDT 24
Peak memory 210868 kb
Host smart-b6cf4bfb-5224-4b64-9658-f0a4b8a5f4cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301744421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3301744421
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1225024594
Short name T73
Test name
Test status
Simulation time 560341032 ps
CPU time 27.78 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:21 AM PDT 24
Peak memory 210740 kb
Host smart-f368677a-0d66-4e31-bedb-430289251dbe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225024594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1225024594
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2702558612
Short name T91
Test name
Test status
Simulation time 89036963 ps
CPU time 4.57 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:01:59 AM PDT 24
Peak memory 210844 kb
Host smart-727c69f1-552c-4596-8d4e-03fb6ca2c23b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702558612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2702558612
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3881131725
Short name T407
Test name
Test status
Simulation time 1032391958 ps
CPU time 9.53 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:03 AM PDT 24
Peak memory 218984 kb
Host smart-de8da679-0439-4a4a-b1fa-51192d04dcb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881131725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3881131725
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1934260206
Short name T421
Test name
Test status
Simulation time 1485945177 ps
CPU time 13.04 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:52 AM PDT 24
Peak memory 219032 kb
Host smart-fb557815-a983-4ead-8af8-90c20a46fe7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934260206 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1934260206
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1917415641
Short name T403
Test name
Test status
Simulation time 1773506805 ps
CPU time 14.15 seconds
Started Jul 02 08:01:42 AM PDT 24
Finished Jul 02 08:02:14 AM PDT 24
Peak memory 218596 kb
Host smart-52db9ecc-8286-4ef6-ab48-cf73fd0b8d2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917415641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1917415641
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2648439721
Short name T54
Test name
Test status
Simulation time 16996957924 ps
CPU time 45.12 seconds
Started Jul 02 08:01:39 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 210836 kb
Host smart-b0cd257d-8a79-4a03-8d9f-d5945d413bb5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648439721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2648439721
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2152517137
Short name T455
Test name
Test status
Simulation time 6989844216 ps
CPU time 15.25 seconds
Started Jul 02 08:01:38 AM PDT 24
Finished Jul 02 08:02:11 AM PDT 24
Peak memory 210876 kb
Host smart-c8d534d6-33ba-4a0b-af35-b509423fac96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152517137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2152517137
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1958532197
Short name T369
Test name
Test status
Simulation time 18746954321 ps
CPU time 21.12 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:02:16 AM PDT 24
Peak memory 219040 kb
Host smart-0647884b-4f96-48f6-b419-7c5ef6b753db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958532197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1958532197
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4134103031
Short name T106
Test name
Test status
Simulation time 388608536 ps
CPU time 67.23 seconds
Started Jul 02 08:01:49 AM PDT 24
Finished Jul 02 08:03:12 AM PDT 24
Peak memory 218944 kb
Host smart-46f0851b-83f5-435f-bda4-210b52a67aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134103031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4134103031
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1008935457
Short name T400
Test name
Test status
Simulation time 190763832 ps
CPU time 6.61 seconds
Started Jul 02 08:01:38 AM PDT 24
Finished Jul 02 08:02:03 AM PDT 24
Peak memory 219052 kb
Host smart-69acae07-7cff-4340-ba6e-0c55aee08987
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008935457 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1008935457
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.87992660
Short name T425
Test name
Test status
Simulation time 88234232 ps
CPU time 4.16 seconds
Started Jul 02 08:01:46 AM PDT 24
Finished Jul 02 08:02:07 AM PDT 24
Peak memory 218032 kb
Host smart-b80870e0-8a70-43dc-a1ad-3ea10b43327e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87992660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.87992660
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1544615696
Short name T69
Test name
Test status
Simulation time 25650447203 ps
CPU time 64.58 seconds
Started Jul 02 08:01:32 AM PDT 24
Finished Jul 02 08:02:56 AM PDT 24
Peak memory 210740 kb
Host smart-5b201ca5-775c-4171-ab07-c11180940712
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544615696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1544615696
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2550180029
Short name T89
Test name
Test status
Simulation time 261875370 ps
CPU time 5.12 seconds
Started Jul 02 08:01:45 AM PDT 24
Finished Jul 02 08:02:07 AM PDT 24
Peak memory 210840 kb
Host smart-a6f590f2-0446-4c4e-9ea7-5c7cada18056
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550180029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2550180029
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3076791283
Short name T401
Test name
Test status
Simulation time 3755847186 ps
CPU time 17.31 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:11 AM PDT 24
Peak memory 219036 kb
Host smart-a57c46d3-b6f7-48c2-8519-49a93ef3a689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076791283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3076791283
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.989524373
Short name T394
Test name
Test status
Simulation time 1531613510 ps
CPU time 36.82 seconds
Started Jul 02 08:01:33 AM PDT 24
Finished Jul 02 08:02:28 AM PDT 24
Peak memory 211972 kb
Host smart-d6e918bb-d05c-417b-a589-fca374cfcf3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989524373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.989524373
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.989311732
Short name T417
Test name
Test status
Simulation time 4341753087 ps
CPU time 11.26 seconds
Started Jul 02 08:01:39 AM PDT 24
Finished Jul 02 08:02:08 AM PDT 24
Peak memory 219052 kb
Host smart-dd04224d-2ce3-45cb-b446-dadb539cc78c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989311732 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.989311732
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2520462686
Short name T442
Test name
Test status
Simulation time 333205464 ps
CPU time 4.2 seconds
Started Jul 02 08:01:51 AM PDT 24
Finished Jul 02 08:02:11 AM PDT 24
Peak memory 210748 kb
Host smart-9d30cfc3-8666-4716-b6d2-4d33b12266a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520462686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2520462686
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.14713858
Short name T68
Test name
Test status
Simulation time 1267464273 ps
CPU time 24.1 seconds
Started Jul 02 08:01:49 AM PDT 24
Finished Jul 02 08:02:29 AM PDT 24
Peak memory 210780 kb
Host smart-94b59c74-b89a-4985-9384-a6cd9aa6ffb9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14713858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pas
sthru_mem_tl_intg_err.14713858
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2346164198
Short name T449
Test name
Test status
Simulation time 96481984 ps
CPU time 5.92 seconds
Started Jul 02 08:01:48 AM PDT 24
Finished Jul 02 08:02:11 AM PDT 24
Peak memory 210800 kb
Host smart-44a544e1-07d0-47b0-8ff6-c13cb7a82cb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346164198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2346164198
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1069588648
Short name T446
Test name
Test status
Simulation time 898828867 ps
CPU time 11.59 seconds
Started Jul 02 08:01:50 AM PDT 24
Finished Jul 02 08:02:17 AM PDT 24
Peak memory 218948 kb
Host smart-0b721b8a-19ef-4e02-9324-34d08251ed36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069588648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1069588648
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1571733900
Short name T460
Test name
Test status
Simulation time 1983070747 ps
CPU time 38.84 seconds
Started Jul 02 08:01:34 AM PDT 24
Finished Jul 02 08:02:30 AM PDT 24
Peak memory 211140 kb
Host smart-dfaea35f-9796-401c-98c7-0ac4fb6fbe56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571733900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1571733900
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4169141338
Short name T430
Test name
Test status
Simulation time 4341127144 ps
CPU time 11.7 seconds
Started Jul 02 08:01:46 AM PDT 24
Finished Jul 02 08:02:14 AM PDT 24
Peak memory 219048 kb
Host smart-b2508c73-447e-49cf-9f40-5519baf7cd4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169141338 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4169141338
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2312593450
Short name T386
Test name
Test status
Simulation time 3085918145 ps
CPU time 8.91 seconds
Started Jul 02 08:01:41 AM PDT 24
Finished Jul 02 08:02:07 AM PDT 24
Peak memory 210968 kb
Host smart-9b663831-9800-4e5c-a87b-45e2341cba94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312593450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2312593450
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2987963216
Short name T427
Test name
Test status
Simulation time 10176072481 ps
CPU time 47.94 seconds
Started Jul 02 08:01:38 AM PDT 24
Finished Jul 02 08:02:44 AM PDT 24
Peak memory 210800 kb
Host smart-4facc5d4-4bfd-4181-a323-63045d730440
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987963216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2987963216
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1334777737
Short name T90
Test name
Test status
Simulation time 6106697572 ps
CPU time 11.99 seconds
Started Jul 02 08:01:51 AM PDT 24
Finished Jul 02 08:02:19 AM PDT 24
Peak memory 219004 kb
Host smart-2dfcf4a1-52d6-4d49-8b9f-730dbc9ef42b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334777737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1334777737
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1731464535
Short name T370
Test name
Test status
Simulation time 85538008 ps
CPU time 6.14 seconds
Started Jul 02 08:01:52 AM PDT 24
Finished Jul 02 08:02:14 AM PDT 24
Peak memory 218980 kb
Host smart-c147b600-4cbe-4168-adc0-b2f2236a3f8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731464535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1731464535
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.502492483
Short name T459
Test name
Test status
Simulation time 376676323 ps
CPU time 4.33 seconds
Started Jul 02 08:01:46 AM PDT 24
Finished Jul 02 08:02:07 AM PDT 24
Peak memory 211580 kb
Host smart-0cda5d6c-0484-4316-be60-41894f375c9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502492483 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.502492483
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2981345097
Short name T384
Test name
Test status
Simulation time 4103938624 ps
CPU time 16.35 seconds
Started Jul 02 08:01:39 AM PDT 24
Finished Jul 02 08:02:14 AM PDT 24
Peak memory 218720 kb
Host smart-a96f8dce-6c34-446e-9da3-92dc15eb7023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981345097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2981345097
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3087162082
Short name T426
Test name
Test status
Simulation time 5130964412 ps
CPU time 47.22 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 210832 kb
Host smart-19caf887-7ab9-4204-afa0-f25b0354300d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087162082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3087162082
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.785918563
Short name T450
Test name
Test status
Simulation time 7947393304 ps
CPU time 15.58 seconds
Started Jul 02 08:01:43 AM PDT 24
Finished Jul 02 08:02:16 AM PDT 24
Peak memory 211144 kb
Host smart-5d74a339-1396-4c6c-b835-ac2658492dbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785918563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.785918563
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.669834821
Short name T436
Test name
Test status
Simulation time 2313925514 ps
CPU time 15.99 seconds
Started Jul 02 08:01:51 AM PDT 24
Finished Jul 02 08:02:23 AM PDT 24
Peak memory 219048 kb
Host smart-93f57a91-568a-4ec4-b6f7-ec852db6b919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669834821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.669834821
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3776793176
Short name T105
Test name
Test status
Simulation time 1628917279 ps
CPU time 43.46 seconds
Started Jul 02 08:01:41 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 211824 kb
Host smart-e9d3eb2b-545c-4ef7-adea-82de97de28f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776793176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3776793176
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3782790628
Short name T465
Test name
Test status
Simulation time 1015531259 ps
CPU time 10.5 seconds
Started Jul 02 08:01:45 AM PDT 24
Finished Jul 02 08:02:12 AM PDT 24
Peak memory 219032 kb
Host smart-a5c76d8c-376d-42c2-a0d0-1b8030515ee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782790628 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3782790628
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1914976758
Short name T467
Test name
Test status
Simulation time 615696543 ps
CPU time 8.48 seconds
Started Jul 02 08:01:32 AM PDT 24
Finished Jul 02 08:01:59 AM PDT 24
Peak memory 218376 kb
Host smart-8ae9ddd1-b4be-400c-8600-7db1eb99b1d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914976758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1914976758
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1661041199
Short name T454
Test name
Test status
Simulation time 29362596117 ps
CPU time 59.88 seconds
Started Jul 02 08:01:32 AM PDT 24
Finished Jul 02 08:02:50 AM PDT 24
Peak memory 210840 kb
Host smart-ae20f9f6-1328-4e0e-9de8-9a9cc14b95b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661041199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1661041199
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3742118588
Short name T88
Test name
Test status
Simulation time 6093211820 ps
CPU time 12.5 seconds
Started Jul 02 08:01:45 AM PDT 24
Finished Jul 02 08:02:14 AM PDT 24
Peak memory 219200 kb
Host smart-15a784b3-d10d-4468-8a9c-c1d6b5e6bf72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742118588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3742118588
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1567091030
Short name T404
Test name
Test status
Simulation time 1485014287 ps
CPU time 15.35 seconds
Started Jul 02 08:01:36 AM PDT 24
Finished Jul 02 08:02:10 AM PDT 24
Peak memory 218968 kb
Host smart-2713c08f-1fe3-4a23-95d8-a2e6cf0a1b70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567091030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1567091030
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1733733184
Short name T101
Test name
Test status
Simulation time 1016795133 ps
CPU time 40.67 seconds
Started Jul 02 08:01:34 AM PDT 24
Finished Jul 02 08:02:34 AM PDT 24
Peak memory 212104 kb
Host smart-516adeec-db18-458a-87c0-a1185285ae13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733733184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1733733184
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2641304235
Short name T390
Test name
Test status
Simulation time 882301471 ps
CPU time 9.2 seconds
Started Jul 02 08:01:29 AM PDT 24
Finished Jul 02 08:02:01 AM PDT 24
Peak memory 210676 kb
Host smart-96f7cafa-e90d-4996-96e2-99e9f6b780c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641304235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2641304235
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3381900466
Short name T379
Test name
Test status
Simulation time 534346382 ps
CPU time 8.03 seconds
Started Jul 02 08:01:38 AM PDT 24
Finished Jul 02 08:02:04 AM PDT 24
Peak memory 210756 kb
Host smart-234418c0-c933-423d-9555-34dcf6f45ab4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381900466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3381900466
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4043474460
Short name T55
Test name
Test status
Simulation time 221333355 ps
CPU time 7.13 seconds
Started Jul 02 08:01:24 AM PDT 24
Finished Jul 02 08:01:50 AM PDT 24
Peak memory 218900 kb
Host smart-1dbb635a-7792-471d-848b-14af9bd929a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043474460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4043474460
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1527531915
Short name T389
Test name
Test status
Simulation time 8125951648 ps
CPU time 15.85 seconds
Started Jul 02 08:01:29 AM PDT 24
Finished Jul 02 08:02:03 AM PDT 24
Peak memory 219112 kb
Host smart-917d77fe-d807-4788-b2a5-da04e84518c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527531915 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1527531915
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3274476859
Short name T93
Test name
Test status
Simulation time 1286931837 ps
CPU time 11.59 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:51 AM PDT 24
Peak memory 210680 kb
Host smart-9a24cf72-8ac7-4ed0-b350-86d56f0d71d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274476859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3274476859
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3492560582
Short name T378
Test name
Test status
Simulation time 88039362 ps
CPU time 4.28 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:44 AM PDT 24
Peak memory 210592 kb
Host smart-e0b41de8-dbba-4433-a5fe-fd12190cb34c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492560582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3492560582
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1729055933
Short name T409
Test name
Test status
Simulation time 3349245818 ps
CPU time 7.99 seconds
Started Jul 02 08:01:34 AM PDT 24
Finished Jul 02 08:02:00 AM PDT 24
Peak memory 210672 kb
Host smart-a0250fe2-ee2f-4221-bdaa-95035a47791f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729055933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1729055933
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3924633765
Short name T57
Test name
Test status
Simulation time 1482045012 ps
CPU time 18.96 seconds
Started Jul 02 08:01:16 AM PDT 24
Finished Jul 02 08:01:53 AM PDT 24
Peak memory 210748 kb
Host smart-c3bb8bb0-1c70-4eb0-8289-b9971784fce1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924633765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3924633765
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1356011524
Short name T461
Test name
Test status
Simulation time 99977080 ps
CPU time 4.31 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:43 AM PDT 24
Peak memory 218236 kb
Host smart-84d6852b-3a58-4736-a26c-537a042cc163
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356011524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1356011524
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.517402007
Short name T372
Test name
Test status
Simulation time 1273838056 ps
CPU time 8.89 seconds
Started Jul 02 08:01:34 AM PDT 24
Finished Jul 02 08:02:01 AM PDT 24
Peak memory 219008 kb
Host smart-88f2f0c8-bcbc-46e2-a68e-45248fede2b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517402007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.517402007
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2353047364
Short name T439
Test name
Test status
Simulation time 1394764579 ps
CPU time 43.32 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:02:23 AM PDT 24
Peak memory 211836 kb
Host smart-6c4444d0-9d90-469b-95f3-f4dd476af0ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353047364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2353047364
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4022171399
Short name T388
Test name
Test status
Simulation time 6361221225 ps
CPU time 14.06 seconds
Started Jul 02 08:01:32 AM PDT 24
Finished Jul 02 08:02:05 AM PDT 24
Peak memory 218944 kb
Host smart-5a368dce-ff10-4fff-867f-d3e853d44f9e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022171399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4022171399
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1809121272
Short name T374
Test name
Test status
Simulation time 347907325 ps
CPU time 4.39 seconds
Started Jul 02 08:01:45 AM PDT 24
Finished Jul 02 08:02:06 AM PDT 24
Peak memory 217664 kb
Host smart-f3e7cbed-9d75-4470-b470-8f8a406ecb66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809121272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1809121272
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3084883226
Short name T411
Test name
Test status
Simulation time 11484458040 ps
CPU time 13.63 seconds
Started Jul 02 08:01:27 AM PDT 24
Finished Jul 02 08:02:00 AM PDT 24
Peak memory 218904 kb
Host smart-98a263b9-6dd2-4837-a345-06af8093b89c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084883226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3084883226
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3889639606
Short name T435
Test name
Test status
Simulation time 423451316 ps
CPU time 5.42 seconds
Started Jul 02 08:01:25 AM PDT 24
Finished Jul 02 08:01:50 AM PDT 24
Peak memory 219032 kb
Host smart-5a2cd07e-38c6-493f-b216-b24d5b4abb26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889639606 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3889639606
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.651828331
Short name T397
Test name
Test status
Simulation time 1649901306 ps
CPU time 13.9 seconds
Started Jul 02 08:01:32 AM PDT 24
Finished Jul 02 08:02:05 AM PDT 24
Peak memory 210776 kb
Host smart-257e0498-c8b4-466c-be35-83050c20d9d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651828331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.651828331
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2595513826
Short name T456
Test name
Test status
Simulation time 556529627 ps
CPU time 7.68 seconds
Started Jul 02 08:01:21 AM PDT 24
Finished Jul 02 08:01:47 AM PDT 24
Peak memory 210584 kb
Host smart-f418d3c5-08ce-4ae1-b199-ac6704dcb872
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595513826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2595513826
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3222224959
Short name T399
Test name
Test status
Simulation time 691936837 ps
CPU time 7.91 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:02 AM PDT 24
Peak memory 210580 kb
Host smart-4bcb373b-7f6a-4815-aacd-3c60573d3041
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222224959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3222224959
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2905284605
Short name T445
Test name
Test status
Simulation time 32376844454 ps
CPU time 93.8 seconds
Started Jul 02 08:01:24 AM PDT 24
Finished Jul 02 08:03:17 AM PDT 24
Peak memory 210844 kb
Host smart-b9eef9fd-4cf5-4a83-84bd-45c259c723d7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905284605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2905284605
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2204284258
Short name T431
Test name
Test status
Simulation time 7392477816 ps
CPU time 15.33 seconds
Started Jul 02 08:01:51 AM PDT 24
Finished Jul 02 08:02:22 AM PDT 24
Peak memory 219028 kb
Host smart-2da55d27-4de9-4140-ba28-4f60f7f153a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204284258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2204284258
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1252151158
Short name T382
Test name
Test status
Simulation time 17742056294 ps
CPU time 16.06 seconds
Started Jul 02 08:01:36 AM PDT 24
Finished Jul 02 08:02:11 AM PDT 24
Peak memory 218952 kb
Host smart-420af7d7-46f4-497b-88c1-58e4d4306fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252151158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1252151158
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2560994672
Short name T44
Test name
Test status
Simulation time 18334112455 ps
CPU time 77.89 seconds
Started Jul 02 08:01:34 AM PDT 24
Finished Jul 02 08:03:11 AM PDT 24
Peak memory 211396 kb
Host smart-8992a881-2ea0-444e-851a-5fa0b86ebb9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560994672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2560994672
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3848989677
Short name T77
Test name
Test status
Simulation time 1209294496 ps
CPU time 11.35 seconds
Started Jul 02 08:01:20 AM PDT 24
Finished Jul 02 08:01:51 AM PDT 24
Peak memory 210728 kb
Host smart-a3ae4676-3ee6-495e-8ce1-49acda92cba8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848989677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3848989677
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3295561985
Short name T412
Test name
Test status
Simulation time 1746448077 ps
CPU time 13.93 seconds
Started Jul 02 08:01:36 AM PDT 24
Finished Jul 02 08:02:09 AM PDT 24
Peak memory 210748 kb
Host smart-066634c2-17e9-4bfa-8020-a1179aa179d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295561985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3295561985
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4021090139
Short name T76
Test name
Test status
Simulation time 4660069556 ps
CPU time 13.8 seconds
Started Jul 02 08:01:42 AM PDT 24
Finished Jul 02 08:02:13 AM PDT 24
Peak memory 218884 kb
Host smart-830cb23c-5204-4826-abfd-5c19ab6e1832
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021090139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4021090139
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.947596088
Short name T406
Test name
Test status
Simulation time 830666745 ps
CPU time 9.8 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:03 AM PDT 24
Peak memory 219068 kb
Host smart-e6cb3a4e-f511-4c14-a68a-36f80b7ddd6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947596088 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.947596088
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1630131576
Short name T49
Test name
Test status
Simulation time 2972230843 ps
CPU time 8.55 seconds
Started Jul 02 08:01:47 AM PDT 24
Finished Jul 02 08:02:12 AM PDT 24
Peak memory 210824 kb
Host smart-4f16962e-5d09-4ae3-ae61-33f446310234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630131576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1630131576
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1130684124
Short name T377
Test name
Test status
Simulation time 1845178551 ps
CPU time 14.77 seconds
Started Jul 02 08:01:46 AM PDT 24
Finished Jul 02 08:02:18 AM PDT 24
Peak memory 210552 kb
Host smart-89ed110e-1a2c-4317-b902-8b454f8851a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130684124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1130684124
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2867857231
Short name T385
Test name
Test status
Simulation time 23043600459 ps
CPU time 12.66 seconds
Started Jul 02 08:01:27 AM PDT 24
Finished Jul 02 08:01:58 AM PDT 24
Peak memory 210636 kb
Host smart-13d8c8cf-6645-42ec-8739-4a215f0fd409
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867857231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2867857231
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.805956473
Short name T72
Test name
Test status
Simulation time 690471255 ps
CPU time 18.34 seconds
Started Jul 02 08:01:24 AM PDT 24
Finished Jul 02 08:02:02 AM PDT 24
Peak memory 210736 kb
Host smart-ccb312cf-227d-4258-9b16-913cee7189b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805956473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.805956473
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2097697321
Short name T458
Test name
Test status
Simulation time 252153787 ps
CPU time 8.08 seconds
Started Jul 02 08:01:39 AM PDT 24
Finished Jul 02 08:02:04 AM PDT 24
Peak memory 218920 kb
Host smart-ed35e8b9-ca14-4a1d-8cdc-f48f4f0b821a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097697321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2097697321
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.738452818
Short name T434
Test name
Test status
Simulation time 2992617946 ps
CPU time 15.57 seconds
Started Jul 02 08:01:39 AM PDT 24
Finished Jul 02 08:02:12 AM PDT 24
Peak memory 219036 kb
Host smart-a5e0cfe7-aa43-4121-8d1d-95a14aa7b530
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738452818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.738452818
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2562802847
Short name T415
Test name
Test status
Simulation time 3674171289 ps
CPU time 40.67 seconds
Started Jul 02 08:01:21 AM PDT 24
Finished Jul 02 08:02:22 AM PDT 24
Peak memory 218996 kb
Host smart-fbf4ed14-23ef-45b0-9e93-5740ebb66df0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562802847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2562802847
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.465226449
Short name T464
Test name
Test status
Simulation time 7644425650 ps
CPU time 15.05 seconds
Started Jul 02 08:01:40 AM PDT 24
Finished Jul 02 08:02:13 AM PDT 24
Peak memory 219124 kb
Host smart-c36803aa-bc0c-4fed-be9b-454cdedbfe20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465226449 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.465226449
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1845191601
Short name T447
Test name
Test status
Simulation time 5882751457 ps
CPU time 15.56 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:09 AM PDT 24
Peak memory 218840 kb
Host smart-52825311-59b6-4cba-a202-57d99fa1670e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845191601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1845191601
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3444249898
Short name T432
Test name
Test status
Simulation time 53706332206 ps
CPU time 95.15 seconds
Started Jul 02 08:01:47 AM PDT 24
Finished Jul 02 08:03:38 AM PDT 24
Peak memory 210784 kb
Host smart-8e77268d-8977-4ae2-a3c7-2b388dddfad8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444249898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3444249898
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1014902100
Short name T59
Test name
Test status
Simulation time 88084705 ps
CPU time 4.34 seconds
Started Jul 02 08:01:33 AM PDT 24
Finished Jul 02 08:01:56 AM PDT 24
Peak memory 210792 kb
Host smart-ffb30065-c69c-428d-bad4-2b1016869ce0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014902100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1014902100
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3729230219
Short name T373
Test name
Test status
Simulation time 1051177468 ps
CPU time 12.08 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:02:08 AM PDT 24
Peak memory 218972 kb
Host smart-ca25fdf1-835d-4609-b828-fb063e9ac093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729230219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3729230219
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.292726086
Short name T100
Test name
Test status
Simulation time 2424481685 ps
CPU time 72.22 seconds
Started Jul 02 08:01:29 AM PDT 24
Finished Jul 02 08:02:59 AM PDT 24
Peak memory 212464 kb
Host smart-d8fb9bb3-129c-4f95-9455-06c6fab7cd44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292726086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.292726086
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3475313502
Short name T393
Test name
Test status
Simulation time 1150535922 ps
CPU time 10.84 seconds
Started Jul 02 08:01:31 AM PDT 24
Finished Jul 02 08:02:00 AM PDT 24
Peak memory 219060 kb
Host smart-17f9e7f1-78d2-42a4-81ee-612ebaf166d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475313502 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3475313502
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3038321184
Short name T423
Test name
Test status
Simulation time 2142543557 ps
CPU time 8.95 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:02 AM PDT 24
Peak memory 217956 kb
Host smart-8ab834d6-2706-49a9-9a1d-62ef2de2d6f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038321184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3038321184
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3725572602
Short name T60
Test name
Test status
Simulation time 2149010732 ps
CPU time 27.41 seconds
Started Jul 02 08:01:31 AM PDT 24
Finished Jul 02 08:02:17 AM PDT 24
Peak memory 210800 kb
Host smart-b43ab283-ed9f-4afe-92b9-ed93ca37a460
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725572602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3725572602
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.385785354
Short name T47
Test name
Test status
Simulation time 1066446974 ps
CPU time 10.1 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:03 AM PDT 24
Peak memory 210672 kb
Host smart-54728cf8-e594-4e06-a9d3-a1036d6b6152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385785354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.385785354
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1334291241
Short name T468
Test name
Test status
Simulation time 1844475056 ps
CPU time 17.8 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:02:14 AM PDT 24
Peak memory 218964 kb
Host smart-777efa55-f7c3-4325-9f83-7d8bf6042454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334291241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1334291241
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.748373024
Short name T98
Test name
Test status
Simulation time 391341266 ps
CPU time 36.44 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:30 AM PDT 24
Peak memory 218848 kb
Host smart-cce77402-d273-4a93-9dbd-8ad2fca22e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748373024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.748373024
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2040588790
Short name T437
Test name
Test status
Simulation time 1608149485 ps
CPU time 9.5 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:03 AM PDT 24
Peak memory 218936 kb
Host smart-2447d5c2-bfb7-45ec-bb8f-96c029a7c355
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040588790 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2040588790
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3232925738
Short name T58
Test name
Test status
Simulation time 2850040598 ps
CPU time 12.54 seconds
Started Jul 02 08:01:30 AM PDT 24
Finished Jul 02 08:02:02 AM PDT 24
Peak memory 218596 kb
Host smart-349a6bd6-4311-466c-8777-be66f511cc73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232925738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3232925738
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2097766761
Short name T402
Test name
Test status
Simulation time 8976440617 ps
CPU time 13.41 seconds
Started Jul 02 08:01:38 AM PDT 24
Finished Jul 02 08:02:09 AM PDT 24
Peak memory 211088 kb
Host smart-7b58cbd5-aa50-4bf6-bdce-699fb4c659df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097766761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2097766761
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1666105961
Short name T418
Test name
Test status
Simulation time 1790217113 ps
CPU time 12.93 seconds
Started Jul 02 08:01:42 AM PDT 24
Finished Jul 02 08:02:13 AM PDT 24
Peak memory 218952 kb
Host smart-da9bd352-11d5-4342-9bd1-3443f89c4334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666105961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1666105961
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3767321736
Short name T107
Test name
Test status
Simulation time 2310691049 ps
CPU time 70.26 seconds
Started Jul 02 08:01:36 AM PDT 24
Finished Jul 02 08:03:05 AM PDT 24
Peak memory 219020 kb
Host smart-309399f6-f078-4efe-8c0f-f42347353ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767321736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3767321736
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2343659752
Short name T433
Test name
Test status
Simulation time 604584324 ps
CPU time 6.73 seconds
Started Jul 02 08:01:26 AM PDT 24
Finished Jul 02 08:01:52 AM PDT 24
Peak memory 219060 kb
Host smart-1084f407-f274-475e-ad16-38c2bce806d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343659752 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2343659752
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2402898470
Short name T75
Test name
Test status
Simulation time 1339372230 ps
CPU time 11.81 seconds
Started Jul 02 08:01:18 AM PDT 24
Finished Jul 02 08:01:50 AM PDT 24
Peak memory 218328 kb
Host smart-61118165-be53-41b7-94a9-b6f0619b7b8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402898470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2402898470
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2254533812
Short name T424
Test name
Test status
Simulation time 1503021771 ps
CPU time 18.06 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:02:13 AM PDT 24
Peak memory 210648 kb
Host smart-9b3132f2-353e-4a11-b5f5-d7ec1139747c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254533812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2254533812
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.581445889
Short name T395
Test name
Test status
Simulation time 689603857 ps
CPU time 4.34 seconds
Started Jul 02 08:01:45 AM PDT 24
Finished Jul 02 08:02:06 AM PDT 24
Peak memory 210812 kb
Host smart-5e0c385f-fc03-4486-8867-a96c0a9b5477
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581445889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.581445889
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.203189406
Short name T391
Test name
Test status
Simulation time 1460411160 ps
CPU time 10.82 seconds
Started Jul 02 08:01:30 AM PDT 24
Finished Jul 02 08:02:00 AM PDT 24
Peak memory 219012 kb
Host smart-8027cc13-ebae-449b-a6f6-95b8a081477d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203189406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.203189406
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2033510862
Short name T103
Test name
Test status
Simulation time 1977762148 ps
CPU time 74.4 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:03:08 AM PDT 24
Peak memory 218848 kb
Host smart-e5dc4bf2-4d1a-4c25-8987-eb33620cdb94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033510862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2033510862
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3035888181
Short name T428
Test name
Test status
Simulation time 2152865780 ps
CPU time 16.36 seconds
Started Jul 02 08:01:19 AM PDT 24
Finished Jul 02 08:01:56 AM PDT 24
Peak memory 219088 kb
Host smart-17780cb0-8dab-4bcb-ae28-67b0bc36ff6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035888181 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3035888181
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2977234558
Short name T463
Test name
Test status
Simulation time 519767770 ps
CPU time 7.56 seconds
Started Jul 02 08:01:33 AM PDT 24
Finished Jul 02 08:01:59 AM PDT 24
Peak memory 210736 kb
Host smart-02885e12-b150-4c31-8bb8-05b1e1eec47f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977234558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2977234558
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1526221615
Short name T70
Test name
Test status
Simulation time 3160035242 ps
CPU time 27.21 seconds
Started Jul 02 08:01:49 AM PDT 24
Finished Jul 02 08:02:32 AM PDT 24
Peak memory 210820 kb
Host smart-fc4e7e9f-b9d9-4013-a7fc-e3f8fbc6064c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526221615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1526221615
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4088460245
Short name T422
Test name
Test status
Simulation time 10081665561 ps
CPU time 11.26 seconds
Started Jul 02 08:01:29 AM PDT 24
Finished Jul 02 08:02:00 AM PDT 24
Peak memory 210860 kb
Host smart-66ab7465-00c2-4eae-99a4-102823c6526b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088460245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4088460245
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1134631423
Short name T376
Test name
Test status
Simulation time 5501789414 ps
CPU time 14.97 seconds
Started Jul 02 08:01:39 AM PDT 24
Finished Jul 02 08:02:11 AM PDT 24
Peak memory 219272 kb
Host smart-04d5e76e-32fe-4cb8-bd81-0823207d7b54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134631423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1134631423
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.778867101
Short name T108
Test name
Test status
Simulation time 3689501642 ps
CPU time 46.38 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 212088 kb
Host smart-4976de2a-cd2d-4625-8d89-5eac0c1f525e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778867101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.778867101
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3670903885
Short name T351
Test name
Test status
Simulation time 8372400855 ps
CPU time 16.15 seconds
Started Jul 02 08:01:51 AM PDT 24
Finished Jul 02 08:02:23 AM PDT 24
Peak memory 211400 kb
Host smart-6eafad78-a401-42c1-bdd0-4b26e6272fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670903885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3670903885
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.817543441
Short name T339
Test name
Test status
Simulation time 36614488111 ps
CPU time 396.35 seconds
Started Jul 02 08:01:30 AM PDT 24
Finished Jul 02 08:08:25 AM PDT 24
Peak memory 234760 kb
Host smart-2ea10561-a2ef-4434-a87b-52393e874503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817543441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.817543441
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.450750955
Short name T191
Test name
Test status
Simulation time 378715465 ps
CPU time 5.72 seconds
Started Jul 02 08:01:50 AM PDT 24
Finished Jul 02 08:02:12 AM PDT 24
Peak memory 211420 kb
Host smart-89b31aeb-33f3-4769-beed-4d83dafc6593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450750955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.450750955
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.638260378
Short name T24
Test name
Test status
Simulation time 1037564536 ps
CPU time 58.33 seconds
Started Jul 02 08:01:44 AM PDT 24
Finished Jul 02 08:03:00 AM PDT 24
Peak memory 235680 kb
Host smart-1c767a83-3246-4f01-bfe9-f5b88ae79405
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638260378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.638260378
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1890914770
Short name T297
Test name
Test status
Simulation time 750573340 ps
CPU time 9.99 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:03 AM PDT 24
Peak memory 213680 kb
Host smart-491cc4c0-193b-4f6e-99c5-72475a84c929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890914770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1890914770
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4196157406
Short name T63
Test name
Test status
Simulation time 6269081092 ps
CPU time 76.74 seconds
Started Jul 02 08:01:57 AM PDT 24
Finished Jul 02 08:03:28 AM PDT 24
Peak memory 219044 kb
Host smart-1dee600e-b8dd-41fc-96a2-cc3655f71752
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196157406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4196157406
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.225030350
Short name T271
Test name
Test status
Simulation time 2129992123 ps
CPU time 8 seconds
Started Jul 02 08:01:33 AM PDT 24
Finished Jul 02 08:02:00 AM PDT 24
Peak memory 211332 kb
Host smart-f188aea2-f7e7-4e86-9e29-c9ece6b7e1a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225030350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.225030350
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1398528150
Short name T355
Test name
Test status
Simulation time 166331343503 ps
CPU time 289.98 seconds
Started Jul 02 08:01:54 AM PDT 24
Finished Jul 02 08:06:59 AM PDT 24
Peak memory 237244 kb
Host smart-4dc52c76-f225-4749-a628-031a69dede53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398528150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1398528150
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2238646454
Short name T232
Test name
Test status
Simulation time 2209891756 ps
CPU time 12.14 seconds
Started Jul 02 08:01:35 AM PDT 24
Finished Jul 02 08:02:06 AM PDT 24
Peak memory 211368 kb
Host smart-3fe37a55-5905-4f02-a8b3-f723687b4c5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2238646454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2238646454
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4033405177
Short name T25
Test name
Test status
Simulation time 285068138 ps
CPU time 51.1 seconds
Started Jul 02 08:01:50 AM PDT 24
Finished Jul 02 08:02:57 AM PDT 24
Peak memory 237736 kb
Host smart-fb026a3a-34ef-4aa1-84f2-2aeaeef0331f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033405177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4033405177
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.461269547
Short name T86
Test name
Test status
Simulation time 3367536961 ps
CPU time 38.94 seconds
Started Jul 02 08:01:41 AM PDT 24
Finished Jul 02 08:02:37 AM PDT 24
Peak memory 213740 kb
Host smart-6e2d25b5-92d9-4846-abdb-4aac1c96cc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461269547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.461269547
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4185960268
Short name T348
Test name
Test status
Simulation time 8424535273 ps
CPU time 40.14 seconds
Started Jul 02 08:01:40 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 214716 kb
Host smart-040b1af0-051a-4e63-b2f9-3e9d696ec83f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185960268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4185960268
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4122785731
Short name T199
Test name
Test status
Simulation time 482892249590 ps
CPU time 1858.87 seconds
Started Jul 02 08:01:45 AM PDT 24
Finished Jul 02 08:33:01 AM PDT 24
Peak memory 235796 kb
Host smart-afb82115-40ef-436c-8994-1ba21c7a6c53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122785731 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.4122785731
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.683493356
Short name T133
Test name
Test status
Simulation time 8778906581 ps
CPU time 12.5 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:37 AM PDT 24
Peak memory 211340 kb
Host smart-250a026f-ff68-4796-aead-84535aaca18d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683493356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.683493356
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4211424426
Short name T326
Test name
Test status
Simulation time 3678498324 ps
CPU time 114.05 seconds
Started Jul 02 08:02:05 AM PDT 24
Finished Jul 02 08:04:14 AM PDT 24
Peak memory 235956 kb
Host smart-741aa031-192e-4fe7-85e1-d9eb110fc2ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211424426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4211424426
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1154866269
Short name T193
Test name
Test status
Simulation time 4294449647 ps
CPU time 33.39 seconds
Started Jul 02 08:01:57 AM PDT 24
Finished Jul 02 08:02:46 AM PDT 24
Peak memory 212044 kb
Host smart-9936d5a5-e156-430a-9ccf-df0a7ee5a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154866269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1154866269
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.977088499
Short name T43
Test name
Test status
Simulation time 6439365160 ps
CPU time 14.12 seconds
Started Jul 02 08:01:57 AM PDT 24
Finished Jul 02 08:02:26 AM PDT 24
Peak memory 211468 kb
Host smart-e4481100-eb88-4c14-9d40-0610688c73b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977088499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.977088499
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.214369632
Short name T313
Test name
Test status
Simulation time 17438721739 ps
CPU time 38.68 seconds
Started Jul 02 08:02:01 AM PDT 24
Finished Jul 02 08:02:54 AM PDT 24
Peak memory 213888 kb
Host smart-a72ca910-fadb-4f5c-9fa2-0ccec68c490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214369632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.214369632
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2943197546
Short name T61
Test name
Test status
Simulation time 6405049527 ps
CPU time 57.3 seconds
Started Jul 02 08:01:49 AM PDT 24
Finished Jul 02 08:03:02 AM PDT 24
Peak memory 216364 kb
Host smart-50a02e58-96eb-437b-a8cb-260e53226758
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943197546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2943197546
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3477151489
Short name T37
Test name
Test status
Simulation time 116211127014 ps
CPU time 1117.5 seconds
Started Jul 02 08:01:57 AM PDT 24
Finished Jul 02 08:20:50 AM PDT 24
Peak memory 235872 kb
Host smart-ba8cb7a8-c3a3-491c-a502-4c65b39a6bd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477151489 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3477151489
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2417170257
Short name T291
Test name
Test status
Simulation time 2735684625 ps
CPU time 6.64 seconds
Started Jul 02 08:02:09 AM PDT 24
Finished Jul 02 08:02:30 AM PDT 24
Peak memory 211428 kb
Host smart-2db980d1-f901-4ba6-b7ad-ffd1fc5b1d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417170257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2417170257
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1136469976
Short name T17
Test name
Test status
Simulation time 23951728109 ps
CPU time 227.53 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:06:18 AM PDT 24
Peak memory 237924 kb
Host smart-6b5e7b66-36f7-49cd-8bd6-089be6ca546a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136469976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1136469976
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1420076453
Short name T23
Test name
Test status
Simulation time 4289166168 ps
CPU time 22.11 seconds
Started Jul 02 08:02:02 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 212040 kb
Host smart-93825175-787c-4c39-97cf-66e904a6e7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420076453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1420076453
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2458528407
Short name T182
Test name
Test status
Simulation time 1533466117 ps
CPU time 14.17 seconds
Started Jul 02 08:01:54 AM PDT 24
Finished Jul 02 08:02:23 AM PDT 24
Peak memory 211400 kb
Host smart-2b204c1e-4214-4dcc-8375-c938ca9ec993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2458528407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2458528407
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2861800756
Short name T9
Test name
Test status
Simulation time 18731855795 ps
CPU time 30.66 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:03:00 AM PDT 24
Peak memory 214672 kb
Host smart-731b74e8-1d6c-4c0b-a034-9d179f90c38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861800756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2861800756
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2497884107
Short name T361
Test name
Test status
Simulation time 2471250270 ps
CPU time 35.19 seconds
Started Jul 02 08:01:56 AM PDT 24
Finished Jul 02 08:02:47 AM PDT 24
Peak memory 213548 kb
Host smart-89dd3479-3223-4af1-a73b-423d9d795484
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497884107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2497884107
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2940712306
Short name T1
Test name
Test status
Simulation time 1886920180 ps
CPU time 15.11 seconds
Started Jul 02 08:02:07 AM PDT 24
Finished Jul 02 08:02:37 AM PDT 24
Peak memory 211368 kb
Host smart-89c51228-4a08-4af2-a7f7-163e190131b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940712306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2940712306
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1905917444
Short name T277
Test name
Test status
Simulation time 30062110282 ps
CPU time 255.69 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:06:41 AM PDT 24
Peak memory 237936 kb
Host smart-b60a957f-c1f8-41f9-a1fb-6fea169ccd02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905917444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1905917444
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1093723035
Short name T170
Test name
Test status
Simulation time 175364163 ps
CPU time 9.28 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:02:31 AM PDT 24
Peak memory 211988 kb
Host smart-d9181e9b-d260-4a0e-a06a-283ba22d4c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093723035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1093723035
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2403697738
Short name T337
Test name
Test status
Simulation time 1236546128 ps
CPU time 7.54 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:02:30 AM PDT 24
Peak memory 211292 kb
Host smart-e622b40a-8b43-4c39-96fc-18e5d8679014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403697738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2403697738
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3204891982
Short name T359
Test name
Test status
Simulation time 15717346535 ps
CPU time 30.97 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:57 AM PDT 24
Peak memory 214284 kb
Host smart-53be8537-0215-448d-8381-be685d6b4034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204891982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3204891982
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2240764002
Short name T188
Test name
Test status
Simulation time 5822050404 ps
CPU time 50.11 seconds
Started Jul 02 08:02:03 AM PDT 24
Finished Jul 02 08:03:08 AM PDT 24
Peak memory 216380 kb
Host smart-c459565c-b42f-4370-9d9d-396233583ae4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240764002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2240764002
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3667494714
Short name T222
Test name
Test status
Simulation time 2205389780 ps
CPU time 16.26 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:02:39 AM PDT 24
Peak memory 211304 kb
Host smart-57c4d2fc-7003-423e-ad32-08ba1432377b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667494714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3667494714
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1078281982
Short name T327
Test name
Test status
Simulation time 20006996379 ps
CPU time 190.09 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:05:32 AM PDT 24
Peak memory 237860 kb
Host smart-22cf4cd7-c061-4abd-9887-f488452901c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078281982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1078281982
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3080898976
Short name T299
Test name
Test status
Simulation time 9863471620 ps
CPU time 24.5 seconds
Started Jul 02 08:01:52 AM PDT 24
Finished Jul 02 08:02:32 AM PDT 24
Peak memory 212268 kb
Host smart-0e6f4021-2b81-4dac-886a-3636eb950afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080898976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3080898976
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.556831818
Short name T300
Test name
Test status
Simulation time 7735837674 ps
CPU time 12.61 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 211476 kb
Host smart-2a2e6cd4-362f-4e19-ba5e-aaa69a4e7bf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556831818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.556831818
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1149675155
Short name T229
Test name
Test status
Simulation time 14148750969 ps
CPU time 32.98 seconds
Started Jul 02 08:02:17 AM PDT 24
Finished Jul 02 08:03:04 AM PDT 24
Peak memory 213604 kb
Host smart-e28423df-ea5d-4e4a-9993-0538e376d816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149675155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1149675155
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2172166694
Short name T140
Test name
Test status
Simulation time 47458951046 ps
CPU time 97.12 seconds
Started Jul 02 08:01:54 AM PDT 24
Finished Jul 02 08:03:46 AM PDT 24
Peak memory 219436 kb
Host smart-59ad13be-1761-47db-9359-29da9e9943c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172166694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2172166694
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.532314840
Short name T155
Test name
Test status
Simulation time 3154959968 ps
CPU time 13.26 seconds
Started Jul 02 08:02:00 AM PDT 24
Finished Jul 02 08:02:27 AM PDT 24
Peak memory 211412 kb
Host smart-d408e2fe-dfe2-40b9-a7d5-7c1eb0194117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532314840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.532314840
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.901246211
Short name T325
Test name
Test status
Simulation time 2683036618 ps
CPU time 119.26 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:04:18 AM PDT 24
Peak memory 237036 kb
Host smart-4dc19f52-3ec3-4748-b2de-7087aa11f9e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901246211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.901246211
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3974961079
Short name T219
Test name
Test status
Simulation time 3678870467 ps
CPU time 29.96 seconds
Started Jul 02 08:02:02 AM PDT 24
Finished Jul 02 08:02:46 AM PDT 24
Peak memory 211976 kb
Host smart-238cd9ac-dd31-4792-9ac0-c08f75259eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974961079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3974961079
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1766297679
Short name T147
Test name
Test status
Simulation time 2612234191 ps
CPU time 13.28 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:02:32 AM PDT 24
Peak memory 211456 kb
Host smart-70f307d1-4614-46c8-9e34-196c11614ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1766297679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1766297679
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3159840620
Short name T41
Test name
Test status
Simulation time 4274707856 ps
CPU time 33.32 seconds
Started Jul 02 08:01:54 AM PDT 24
Finished Jul 02 08:02:42 AM PDT 24
Peak memory 213308 kb
Host smart-2d6c97f8-db5a-421a-96b8-0b1bcef3f5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159840620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3159840620
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2628991800
Short name T301
Test name
Test status
Simulation time 26910338262 ps
CPU time 66.18 seconds
Started Jul 02 08:01:57 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 218892 kb
Host smart-643c5b61-4d91-4658-af20-39155b7fe996
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628991800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2628991800
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3103401907
Short name T290
Test name
Test status
Simulation time 449655782 ps
CPU time 7.37 seconds
Started Jul 02 08:02:01 AM PDT 24
Finished Jul 02 08:02:22 AM PDT 24
Peak memory 211368 kb
Host smart-02a6dcca-0d29-4bd9-8202-f8429e80b91e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103401907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3103401907
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3556575127
Short name T82
Test name
Test status
Simulation time 73414676258 ps
CPU time 247.93 seconds
Started Jul 02 08:01:55 AM PDT 24
Finished Jul 02 08:06:18 AM PDT 24
Peak memory 228572 kb
Host smart-f820b9e8-6651-4d1d-a8ce-149804fbd2d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556575127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3556575127
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2898408996
Short name T233
Test name
Test status
Simulation time 341539550 ps
CPU time 9.54 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:02:39 AM PDT 24
Peak memory 212408 kb
Host smart-3b532889-96e5-47b7-9e42-aef5be5f5a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898408996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2898408996
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3896723372
Short name T185
Test name
Test status
Simulation time 2443177770 ps
CPU time 11.93 seconds
Started Jul 02 08:02:02 AM PDT 24
Finished Jul 02 08:02:28 AM PDT 24
Peak memory 211380 kb
Host smart-312e1637-ae9e-4ff7-b846-9fed6a7a4e5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896723372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3896723372
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4136152716
Short name T190
Test name
Test status
Simulation time 10824498885 ps
CPU time 29.11 seconds
Started Jul 02 08:02:03 AM PDT 24
Finished Jul 02 08:02:47 AM PDT 24
Peak memory 214064 kb
Host smart-206f1ace-3c13-417b-9fc3-9097dca2cad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136152716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4136152716
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.535861405
Short name T119
Test name
Test status
Simulation time 20636549599 ps
CPU time 46.13 seconds
Started Jul 02 08:02:03 AM PDT 24
Finished Jul 02 08:03:03 AM PDT 24
Peak memory 219580 kb
Host smart-1c2ef34e-eee6-4836-a327-c4caaeca9df1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535861405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.535861405
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.576158145
Short name T38
Test name
Test status
Simulation time 51172459989 ps
CPU time 1972.54 seconds
Started Jul 02 08:02:00 AM PDT 24
Finished Jul 02 08:35:08 AM PDT 24
Peak memory 233332 kb
Host smart-9465431b-c8b2-4c1a-babf-25eca2fce9d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576158145 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.576158145
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1799308418
Short name T149
Test name
Test status
Simulation time 89292523 ps
CPU time 4.21 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:02:33 AM PDT 24
Peak memory 211276 kb
Host smart-cefbc758-6f3b-4c84-b180-2893a793a23b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799308418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1799308418
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1904690598
Short name T331
Test name
Test status
Simulation time 63404982819 ps
CPU time 354.64 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:08:24 AM PDT 24
Peak memory 224908 kb
Host smart-731b7e9b-7e42-4857-bfb4-d90eae9cfb87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904690598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1904690598
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.766208582
Short name T206
Test name
Test status
Simulation time 4014625011 ps
CPU time 31.75 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:56 AM PDT 24
Peak memory 212036 kb
Host smart-cb27bd44-8815-486f-bc84-74c686744c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766208582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.766208582
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1483740407
Short name T341
Test name
Test status
Simulation time 2593984218 ps
CPU time 9.53 seconds
Started Jul 02 08:01:58 AM PDT 24
Finished Jul 02 08:02:22 AM PDT 24
Peak memory 211380 kb
Host smart-04cb4215-58cc-453e-8c94-89fe7e552021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483740407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1483740407
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4205638186
Short name T244
Test name
Test status
Simulation time 264733711 ps
CPU time 12.36 seconds
Started Jul 02 08:02:03 AM PDT 24
Finished Jul 02 08:02:30 AM PDT 24
Peak memory 213880 kb
Host smart-cc942fb3-ce48-4615-81fa-857bf1183f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205638186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4205638186
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2970741292
Short name T224
Test name
Test status
Simulation time 1327601819 ps
CPU time 14.42 seconds
Started Jul 02 08:02:07 AM PDT 24
Finished Jul 02 08:02:36 AM PDT 24
Peak memory 212368 kb
Host smart-39f46934-3f5d-49d8-851a-f157ca04fed9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970741292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2970741292
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3134272075
Short name T259
Test name
Test status
Simulation time 1297161986 ps
CPU time 12.04 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 211336 kb
Host smart-fe00923c-8419-4417-88c0-4dc34ec9c127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134272075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3134272075
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1296501910
Short name T28
Test name
Test status
Simulation time 25853060442 ps
CPU time 134.65 seconds
Started Jul 02 08:02:00 AM PDT 24
Finished Jul 02 08:04:30 AM PDT 24
Peak memory 237888 kb
Host smart-a1835942-3102-4069-8b5f-01cd6782ffa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296501910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1296501910
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3306039276
Short name T311
Test name
Test status
Simulation time 7670195822 ps
CPU time 31.67 seconds
Started Jul 02 08:02:03 AM PDT 24
Finished Jul 02 08:02:49 AM PDT 24
Peak memory 212288 kb
Host smart-e3fc5161-a56c-4d4b-9895-a81a842d4452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306039276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3306039276
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2533094575
Short name T141
Test name
Test status
Simulation time 371711402 ps
CPU time 5.41 seconds
Started Jul 02 08:01:50 AM PDT 24
Finished Jul 02 08:02:11 AM PDT 24
Peak memory 211320 kb
Host smart-b6b17cc4-d12c-4191-8d99-d445b09f7a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533094575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2533094575
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.777151175
Short name T307
Test name
Test status
Simulation time 18254558818 ps
CPU time 38.33 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:03:04 AM PDT 24
Peak memory 213692 kb
Host smart-959547ab-8f42-4c27-8eea-c8165396afa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777151175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.777151175
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3228296869
Short name T62
Test name
Test status
Simulation time 1768684551 ps
CPU time 17.03 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:02:36 AM PDT 24
Peak memory 211936 kb
Host smart-e7f89d69-39d0-4952-b192-7bb78b902064
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228296869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3228296869
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1024903230
Short name T161
Test name
Test status
Simulation time 22257546773 ps
CPU time 114.53 seconds
Started Jul 02 08:02:12 AM PDT 24
Finished Jul 02 08:04:21 AM PDT 24
Peak memory 237428 kb
Host smart-bc06392e-133b-455d-92d0-738a61895190
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024903230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1024903230
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.412825607
Short name T212
Test name
Test status
Simulation time 10629910655 ps
CPU time 24.39 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:02:53 AM PDT 24
Peak memory 212380 kb
Host smart-4e6ff562-91f2-413d-bc10-8d99b29a3924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412825607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.412825607
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.625723136
Short name T138
Test name
Test status
Simulation time 3043914270 ps
CPU time 13.41 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 211492 kb
Host smart-4d24d393-f936-4053-860a-2c26181b297a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625723136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.625723136
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3780615886
Short name T95
Test name
Test status
Simulation time 186360824 ps
CPU time 10.17 seconds
Started Jul 02 08:02:07 AM PDT 24
Finished Jul 02 08:02:32 AM PDT 24
Peak memory 213416 kb
Host smart-1765d9f3-0b9a-463b-8095-69e389112016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780615886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3780615886
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.941428619
Short name T8
Test name
Test status
Simulation time 5154904838 ps
CPU time 54.23 seconds
Started Jul 02 08:02:16 AM PDT 24
Finished Jul 02 08:03:24 AM PDT 24
Peak memory 216308 kb
Host smart-c9a35ced-3c56-4fc6-8b9d-24d1c75ab471
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941428619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.941428619
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2424704121
Short name T227
Test name
Test status
Simulation time 53542716180 ps
CPU time 2043.19 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:36:29 AM PDT 24
Peak memory 234248 kb
Host smart-4572e201-c0cb-464f-ac5b-d3a8d32367a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424704121 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2424704121
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3405774658
Short name T202
Test name
Test status
Simulation time 5453149350 ps
CPU time 14.95 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:02:44 AM PDT 24
Peak memory 211428 kb
Host smart-047796d9-df34-4979-abe5-89f26ced4a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405774658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3405774658
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1957372475
Short name T256
Test name
Test status
Simulation time 41870222583 ps
CPU time 246.19 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:06:35 AM PDT 24
Peak memory 225140 kb
Host smart-792864fd-e1a5-41bf-81d2-95a66d592f01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957372475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1957372475
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2901891132
Short name T350
Test name
Test status
Simulation time 3250898211 ps
CPU time 27.24 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:02:56 AM PDT 24
Peak memory 212108 kb
Host smart-e348ca11-f8c2-43e0-a2ff-e98a6db85d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901891132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2901891132
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3513509281
Short name T316
Test name
Test status
Simulation time 99830886 ps
CPU time 5.37 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:02:35 AM PDT 24
Peak memory 210944 kb
Host smart-5224be9d-b78d-4a82-96a2-20c54bac8e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513509281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3513509281
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.4255993336
Short name T314
Test name
Test status
Simulation time 188275261 ps
CPU time 10.23 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:02:32 AM PDT 24
Peak memory 213244 kb
Host smart-fe5f0671-a67b-4baa-a359-1c794a899ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255993336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.4255993336
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.971298409
Short name T264
Test name
Test status
Simulation time 5021479603 ps
CPU time 13.65 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:02:43 AM PDT 24
Peak memory 211372 kb
Host smart-be99161c-1a5a-4364-8944-b76f41113f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971298409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.971298409
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1453176101
Short name T266
Test name
Test status
Simulation time 4931743349 ps
CPU time 14.69 seconds
Started Jul 02 08:02:01 AM PDT 24
Finished Jul 02 08:02:30 AM PDT 24
Peak memory 211392 kb
Host smart-07274060-0f3e-4442-9cdb-3e9a82122c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453176101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1453176101
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.311405261
Short name T276
Test name
Test status
Simulation time 9090540528 ps
CPU time 117.22 seconds
Started Jul 02 08:01:52 AM PDT 24
Finished Jul 02 08:04:05 AM PDT 24
Peak memory 228596 kb
Host smart-8d8e62bd-c5ca-43a1-9d36-f218dbfc44ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311405261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.311405261
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2545533867
Short name T32
Test name
Test status
Simulation time 10805624880 ps
CPU time 27.98 seconds
Started Jul 02 08:01:43 AM PDT 24
Finished Jul 02 08:02:29 AM PDT 24
Peak memory 212300 kb
Host smart-29af1849-d59c-4b49-a7ed-a219dbc08b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545533867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2545533867
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.821541975
Short name T176
Test name
Test status
Simulation time 1035770747 ps
CPU time 5.95 seconds
Started Jul 02 08:01:44 AM PDT 24
Finished Jul 02 08:02:07 AM PDT 24
Peak memory 211416 kb
Host smart-f50eba8e-d368-418c-aa41-a223926827c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821541975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.821541975
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1646963133
Short name T225
Test name
Test status
Simulation time 3206728117 ps
CPU time 27.35 seconds
Started Jul 02 08:01:45 AM PDT 24
Finished Jul 02 08:02:29 AM PDT 24
Peak memory 213232 kb
Host smart-ccaa7b57-b294-4a4a-b02a-9bfa9dae0b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646963133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1646963133
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.502672733
Short name T116
Test name
Test status
Simulation time 1986497323 ps
CPU time 18.38 seconds
Started Jul 02 08:01:37 AM PDT 24
Finished Jul 02 08:02:13 AM PDT 24
Peak memory 211280 kb
Host smart-1fa0fad9-6b90-4b3f-a0a9-6156ac3bbf7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502672733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.502672733
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.626008563
Short name T189
Test name
Test status
Simulation time 128534527862 ps
CPU time 1168.92 seconds
Started Jul 02 08:01:39 AM PDT 24
Finished Jul 02 08:21:25 AM PDT 24
Peak memory 236020 kb
Host smart-884e8d0c-3995-4f71-b88d-445cef3ed2c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626008563 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.626008563
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.365631537
Short name T362
Test name
Test status
Simulation time 866423943 ps
CPU time 9.41 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:02:32 AM PDT 24
Peak memory 211332 kb
Host smart-e8a4926a-4d9f-46c5-92a8-5085b309f8e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365631537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.365631537
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3081135946
Short name T218
Test name
Test status
Simulation time 28224936725 ps
CPU time 274.11 seconds
Started Jul 02 08:01:59 AM PDT 24
Finished Jul 02 08:06:48 AM PDT 24
Peak memory 228544 kb
Host smart-d7138dc5-8a2b-40e2-a5db-34f2bf613c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081135946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3081135946
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2831413182
Short name T345
Test name
Test status
Simulation time 4082322054 ps
CPU time 25.15 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:02:44 AM PDT 24
Peak memory 211936 kb
Host smart-522ebc70-fa94-4050-9b54-c7aedb53f920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831413182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2831413182
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4024457251
Short name T115
Test name
Test status
Simulation time 347902801 ps
CPU time 5.36 seconds
Started Jul 02 08:02:03 AM PDT 24
Finished Jul 02 08:02:23 AM PDT 24
Peak memory 211396 kb
Host smart-76931027-96e2-4c7b-937f-be73f06b1abd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024457251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4024457251
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1605889271
Short name T226
Test name
Test status
Simulation time 4430211482 ps
CPU time 38.51 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:03:07 AM PDT 24
Peak memory 212980 kb
Host smart-cbf4d407-e00c-45df-adf3-8662c804df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605889271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1605889271
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3387601267
Short name T352
Test name
Test status
Simulation time 7979942487 ps
CPU time 32.54 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:03:00 AM PDT 24
Peak memory 215448 kb
Host smart-5a24a9c0-f4f7-4c4f-9cba-0dc347e6d4c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387601267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3387601267
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2255955648
Short name T52
Test name
Test status
Simulation time 2596844385 ps
CPU time 12.08 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:02:39 AM PDT 24
Peak memory 211428 kb
Host smart-6d268800-36af-4f80-9884-1f59c4f38ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255955648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2255955648
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2467412003
Short name T128
Test name
Test status
Simulation time 1739153157 ps
CPU time 74.62 seconds
Started Jul 02 08:02:02 AM PDT 24
Finished Jul 02 08:03:31 AM PDT 24
Peak memory 236764 kb
Host smart-8c7c99cf-e35e-4cc0-9ba9-9bebb053e2e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467412003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2467412003
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.73461058
Short name T30
Test name
Test status
Simulation time 355428628 ps
CPU time 9.51 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:02:31 AM PDT 24
Peak memory 211924 kb
Host smart-60ea98d3-34dd-40ef-afa6-563122e9d8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73461058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.73461058
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3369982426
Short name T127
Test name
Test status
Simulation time 4839483116 ps
CPU time 12.73 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:37 AM PDT 24
Peak memory 211468 kb
Host smart-86e95524-0ce5-4762-8de5-3421b49bd60b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369982426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3369982426
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2816384136
Short name T272
Test name
Test status
Simulation time 3862679857 ps
CPU time 32.24 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:03:02 AM PDT 24
Peak memory 213584 kb
Host smart-679c31da-a5e5-40e9-ab64-8a1fc8e75498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816384136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2816384136
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4046592760
Short name T262
Test name
Test status
Simulation time 16340101734 ps
CPU time 52.72 seconds
Started Jul 02 08:02:09 AM PDT 24
Finished Jul 02 08:03:17 AM PDT 24
Peak memory 216176 kb
Host smart-a6b0fb05-1c79-45f2-b0fa-06d7e0c5f56e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046592760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4046592760
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3210754309
Short name T328
Test name
Test status
Simulation time 13138763254 ps
CPU time 12.14 seconds
Started Jul 02 08:01:59 AM PDT 24
Finished Jul 02 08:02:26 AM PDT 24
Peak memory 211392 kb
Host smart-eed433f2-f3ff-4d07-8754-21ec6c074eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210754309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3210754309
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2508066293
Short name T248
Test name
Test status
Simulation time 26087962829 ps
CPU time 231.41 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:06:14 AM PDT 24
Peak memory 213648 kb
Host smart-63141fa0-fda3-4069-a9a9-6c9195c7d02a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508066293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2508066293
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1837256112
Short name T150
Test name
Test status
Simulation time 4671031119 ps
CPU time 22.71 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:02:46 AM PDT 24
Peak memory 212340 kb
Host smart-78c61536-c3ba-4e1e-923c-8a9b024ac970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837256112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1837256112
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1356233880
Short name T292
Test name
Test status
Simulation time 6207408147 ps
CPU time 10.82 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:02:34 AM PDT 24
Peak memory 211488 kb
Host smart-7b621f5d-5fd7-440c-bac1-913276be54d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1356233880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1356233880
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1172648293
Short name T216
Test name
Test status
Simulation time 950264258 ps
CPU time 16.87 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:02:36 AM PDT 24
Peak memory 212064 kb
Host smart-84900ff3-9095-4bba-b171-d9888e6d29a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172648293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1172648293
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3345583604
Short name T336
Test name
Test status
Simulation time 5659953502 ps
CPU time 63.65 seconds
Started Jul 02 08:02:16 AM PDT 24
Finished Jul 02 08:03:35 AM PDT 24
Peak memory 219440 kb
Host smart-da988403-2976-4161-8153-706f85af84b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345583604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3345583604
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2225267224
Short name T152
Test name
Test status
Simulation time 4075736022 ps
CPU time 10.17 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:02:29 AM PDT 24
Peak memory 211360 kb
Host smart-764d873b-42d1-4f43-bc56-13341890e778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225267224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2225267224
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.491916869
Short name T5
Test name
Test status
Simulation time 59418353806 ps
CPU time 326.29 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:07:55 AM PDT 24
Peak memory 237844 kb
Host smart-7e08b473-85ff-4f84-89de-dccb60810c47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491916869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.491916869
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.834165845
Short name T157
Test name
Test status
Simulation time 694140732 ps
CPU time 9.35 seconds
Started Jul 02 08:02:27 AM PDT 24
Finished Jul 02 08:02:53 AM PDT 24
Peak memory 212056 kb
Host smart-db65e2eb-3570-4fc2-822a-d40f0c08c43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834165845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.834165845
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2834084682
Short name T305
Test name
Test status
Simulation time 5283060967 ps
CPU time 10.86 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:02:32 AM PDT 24
Peak memory 211472 kb
Host smart-c20aaf6f-be2e-4d18-8452-c83f07d14ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2834084682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2834084682
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1500935352
Short name T84
Test name
Test status
Simulation time 3332361211 ps
CPU time 28.33 seconds
Started Jul 02 08:02:02 AM PDT 24
Finished Jul 02 08:02:44 AM PDT 24
Peak memory 213080 kb
Host smart-4db6d02a-8e6a-492a-a2d5-1583c581d9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500935352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1500935352
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4291035178
Short name T160
Test name
Test status
Simulation time 2838085116 ps
CPU time 27.91 seconds
Started Jul 02 08:02:12 AM PDT 24
Finished Jul 02 08:02:54 AM PDT 24
Peak memory 213572 kb
Host smart-69db5aa6-46a5-4e2c-b3f2-6cc99ad36f4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291035178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4291035178
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3798100221
Short name T329
Test name
Test status
Simulation time 1245618411 ps
CPU time 8.34 seconds
Started Jul 02 08:02:18 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 211368 kb
Host smart-4f6a4def-888e-44e4-ac60-a487e1beb05e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798100221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3798100221
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1653460156
Short name T360
Test name
Test status
Simulation time 21086888617 ps
CPU time 208.86 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:05:52 AM PDT 24
Peak memory 237840 kb
Host smart-001aeb96-9849-4edf-937c-3d79729347b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653460156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1653460156
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3859523980
Short name T357
Test name
Test status
Simulation time 1649564490 ps
CPU time 15.09 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:02:37 AM PDT 24
Peak memory 211972 kb
Host smart-5141e719-eefb-41cf-904c-f3754948e868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859523980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3859523980
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4180450238
Short name T213
Test name
Test status
Simulation time 2649626058 ps
CPU time 11.17 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:37 AM PDT 24
Peak memory 211472 kb
Host smart-62fb7799-dc69-41a0-88f2-1c60662987dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180450238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.4180450238
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1542852544
Short name T367
Test name
Test status
Simulation time 3002603797 ps
CPU time 28.71 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:02:50 AM PDT 24
Peak memory 212340 kb
Host smart-57070494-19c0-4da4-8f1a-de08d6f4acac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542852544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1542852544
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4040842394
Short name T154
Test name
Test status
Simulation time 3241563769 ps
CPU time 28.71 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:54 AM PDT 24
Peak memory 215416 kb
Host smart-10d961b1-81b8-4c7b-b433-f7c5f6045a75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040842394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4040842394
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1981250635
Short name T280
Test name
Test status
Simulation time 334286648 ps
CPU time 4.13 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:28 AM PDT 24
Peak memory 211348 kb
Host smart-20b8ea79-89a8-46aa-b0d1-9024ed5e2ea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981250635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1981250635
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4153549485
Short name T245
Test name
Test status
Simulation time 118010931232 ps
CPU time 286.42 seconds
Started Jul 02 08:02:07 AM PDT 24
Finished Jul 02 08:07:08 AM PDT 24
Peak memory 212648 kb
Host smart-0eefc117-7982-4eed-a5c1-b2fd7369e2d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153549485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4153549485
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1225015077
Short name T153
Test name
Test status
Simulation time 3405793454 ps
CPU time 14.84 seconds
Started Jul 02 08:02:02 AM PDT 24
Finished Jul 02 08:02:31 AM PDT 24
Peak memory 212064 kb
Host smart-6cd0186e-626d-4894-ba57-e7f7f9e6037e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225015077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1225015077
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1295678577
Short name T137
Test name
Test status
Simulation time 591033169 ps
CPU time 5.67 seconds
Started Jul 02 08:02:07 AM PDT 24
Finished Jul 02 08:02:28 AM PDT 24
Peak memory 211344 kb
Host smart-5a7d5d8b-65e0-4997-bb4b-1520d3666633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295678577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1295678577
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3497431040
Short name T151
Test name
Test status
Simulation time 22009386365 ps
CPU time 31.57 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:02:53 AM PDT 24
Peak memory 214372 kb
Host smart-a007f0d8-4b5e-463c-b55d-8aade7b80612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497431040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3497431040
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.720104700
Short name T254
Test name
Test status
Simulation time 32480425991 ps
CPU time 36.93 seconds
Started Jul 02 08:02:07 AM PDT 24
Finished Jul 02 08:02:58 AM PDT 24
Peak memory 215712 kb
Host smart-e7e6c402-ec79-498c-add9-d3e512ced3ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720104700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.720104700
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.236292312
Short name T112
Test name
Test status
Simulation time 1153178911 ps
CPU time 11.41 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:02:31 AM PDT 24
Peak memory 211332 kb
Host smart-22c0c745-8aa7-44bb-bb8d-add9206c2f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236292312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.236292312
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1846448366
Short name T220
Test name
Test status
Simulation time 29807982229 ps
CPU time 358.18 seconds
Started Jul 02 08:02:00 AM PDT 24
Finished Jul 02 08:08:12 AM PDT 24
Peak memory 228436 kb
Host smart-51d01721-74c2-4be1-82bb-c881485df4b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846448366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1846448366
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.183252476
Short name T242
Test name
Test status
Simulation time 13142321750 ps
CPU time 26.53 seconds
Started Jul 02 08:02:03 AM PDT 24
Finished Jul 02 08:02:44 AM PDT 24
Peak memory 212304 kb
Host smart-51d228bb-2b13-442c-ae0f-b4c13a66221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183252476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.183252476
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3514200460
Short name T319
Test name
Test status
Simulation time 12370708856 ps
CPU time 15.99 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:42 AM PDT 24
Peak memory 211412 kb
Host smart-4c85754f-bf16-45cf-b64c-feb9e2956380
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3514200460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3514200460
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.723341747
Short name T241
Test name
Test status
Simulation time 3247634555 ps
CPU time 11.81 seconds
Started Jul 02 08:01:58 AM PDT 24
Finished Jul 02 08:02:24 AM PDT 24
Peak memory 213392 kb
Host smart-afa6ebb2-984d-4757-aac0-b8e0d5909027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723341747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.723341747
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3919437107
Short name T183
Test name
Test status
Simulation time 2503797840 ps
CPU time 13.59 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:39 AM PDT 24
Peak memory 212556 kb
Host smart-4f78a5c1-b678-4053-a3d8-8ae4da651c12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919437107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3919437107
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2780051229
Short name T192
Test name
Test status
Simulation time 19435026865 ps
CPU time 991.96 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:18:59 AM PDT 24
Peak memory 231712 kb
Host smart-94269455-d8eb-48dd-aa4f-63aea170a72d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780051229 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2780051229
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.260003420
Short name T169
Test name
Test status
Simulation time 4014239870 ps
CPU time 15.79 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 211360 kb
Host smart-c4e06054-d34e-4f1c-ae7c-538245ac5f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260003420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.260003420
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1802208577
Short name T340
Test name
Test status
Simulation time 11988373220 ps
CPU time 165.3 seconds
Started Jul 02 08:02:22 AM PDT 24
Finished Jul 02 08:05:22 AM PDT 24
Peak memory 234816 kb
Host smart-fd745a23-401f-4653-bbd5-aa3392a9b1df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802208577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1802208577
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.875089923
Short name T364
Test name
Test status
Simulation time 2623818230 ps
CPU time 22.41 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:02:42 AM PDT 24
Peak memory 212052 kb
Host smart-4b6ae46f-c9c8-4e70-85ab-ed39d8f44cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875089923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.875089923
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.139179670
Short name T288
Test name
Test status
Simulation time 8817894000 ps
CPU time 16.4 seconds
Started Jul 02 08:02:09 AM PDT 24
Finished Jul 02 08:02:39 AM PDT 24
Peak memory 211476 kb
Host smart-7b79bda0-8ca5-4382-bfd6-bdbe26d7d3b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139179670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.139179670
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.4114645056
Short name T317
Test name
Test status
Simulation time 4220079659 ps
CPU time 24.91 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:51 AM PDT 24
Peak memory 213496 kb
Host smart-6c3c287f-e640-47b3-83d9-65e975c004bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114645056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.4114645056
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3439353905
Short name T286
Test name
Test status
Simulation time 3954000461 ps
CPU time 26.49 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:02:57 AM PDT 24
Peak memory 213972 kb
Host smart-c9e59185-81a3-4098-904a-00876b26c0d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439353905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3439353905
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3411885405
Short name T166
Test name
Test status
Simulation time 2070823919 ps
CPU time 15.96 seconds
Started Jul 02 08:02:09 AM PDT 24
Finished Jul 02 08:02:39 AM PDT 24
Peak memory 211368 kb
Host smart-b313da9a-a1ce-4d0e-aa35-521a000f8b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411885405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3411885405
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.718097950
Short name T135
Test name
Test status
Simulation time 250682282179 ps
CPU time 208.72 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:05:50 AM PDT 24
Peak memory 226180 kb
Host smart-d1c94e54-85d5-43f3-8f34-0c83499367c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718097950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.718097950
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3355290227
Short name T131
Test name
Test status
Simulation time 7138802994 ps
CPU time 30.16 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:02:57 AM PDT 24
Peak memory 213088 kb
Host smart-edc384ce-952e-42db-9335-ef89c1eaa2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355290227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3355290227
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2816374591
Short name T120
Test name
Test status
Simulation time 5723003375 ps
CPU time 14.44 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:40 AM PDT 24
Peak memory 211412 kb
Host smart-c47c4d54-e975-45de-9d40-30c81c9e8996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2816374591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2816374591
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2684233762
Short name T281
Test name
Test status
Simulation time 181573540 ps
CPU time 10.12 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:02:37 AM PDT 24
Peak memory 213784 kb
Host smart-c4b61498-28b1-44a3-8966-8f6278ebeb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684233762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2684233762
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1220296722
Short name T260
Test name
Test status
Simulation time 8524928097 ps
CPU time 46.41 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:03:08 AM PDT 24
Peak memory 216092 kb
Host smart-27afddb1-578b-406c-83e9-b00e9e693868
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220296722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1220296722
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.441934107
Short name T50
Test name
Test status
Simulation time 1322279515 ps
CPU time 6.46 seconds
Started Jul 02 08:02:29 AM PDT 24
Finished Jul 02 08:02:52 AM PDT 24
Peak memory 211152 kb
Host smart-5474b193-1927-450d-a9da-9b46f58db8e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441934107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.441934107
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3945125718
Short name T117
Test name
Test status
Simulation time 1809873464 ps
CPU time 130.01 seconds
Started Jul 02 08:02:18 AM PDT 24
Finished Jul 02 08:04:43 AM PDT 24
Peak memory 237812 kb
Host smart-d0f8cf2d-f255-4f7b-aa9b-bff09b556532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945125718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3945125718
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1663495412
Short name T168
Test name
Test status
Simulation time 2922357600 ps
CPU time 18.6 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:44 AM PDT 24
Peak memory 211476 kb
Host smart-19b6cfa7-1599-4c3d-8b58-7adf7ac678d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663495412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1663495412
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4159525571
Short name T217
Test name
Test status
Simulation time 198085191 ps
CPU time 5.68 seconds
Started Jul 02 08:02:03 AM PDT 24
Finished Jul 02 08:02:23 AM PDT 24
Peak memory 211404 kb
Host smart-172f7576-681c-4b8d-a561-4a38088d7655
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159525571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4159525571
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2851924790
Short name T346
Test name
Test status
Simulation time 1842152223 ps
CPU time 20.44 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:02:49 AM PDT 24
Peak memory 213804 kb
Host smart-299fe131-4170-4bab-a2a5-54fbd175a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851924790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2851924790
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3093692000
Short name T240
Test name
Test status
Simulation time 400062465 ps
CPU time 13.69 seconds
Started Jul 02 08:02:19 AM PDT 24
Finished Jul 02 08:02:47 AM PDT 24
Peak memory 214676 kb
Host smart-65e50014-aa7f-4bba-80fa-445a3b560903
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093692000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3093692000
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.22490284
Short name T223
Test name
Test status
Simulation time 347781869 ps
CPU time 4.24 seconds
Started Jul 02 08:01:48 AM PDT 24
Finished Jul 02 08:02:09 AM PDT 24
Peak memory 211296 kb
Host smart-e67b66bf-1f26-4ea5-a09e-40ec758d268b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22490284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.22490284
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2250202817
Short name T252
Test name
Test status
Simulation time 121607694698 ps
CPU time 379.55 seconds
Started Jul 02 08:01:41 AM PDT 24
Finished Jul 02 08:08:18 AM PDT 24
Peak memory 237468 kb
Host smart-eddb1eef-864f-4a52-967a-efa40c3b87f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250202817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2250202817
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.741084359
Short name T179
Test name
Test status
Simulation time 3509713411 ps
CPU time 16.05 seconds
Started Jul 02 08:02:01 AM PDT 24
Finished Jul 02 08:02:31 AM PDT 24
Peak memory 212608 kb
Host smart-578cdea7-aa35-4700-a2f1-7c1a96364502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741084359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.741084359
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1992700883
Short name T309
Test name
Test status
Simulation time 471457361 ps
CPU time 8.18 seconds
Started Jul 02 08:01:43 AM PDT 24
Finished Jul 02 08:02:09 AM PDT 24
Peak memory 211416 kb
Host smart-d6456b2f-96bc-4c7f-89fc-566ed25c488c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992700883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1992700883
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1708451053
Short name T19
Test name
Test status
Simulation time 7041704025 ps
CPU time 110.49 seconds
Started Jul 02 08:01:51 AM PDT 24
Finished Jul 02 08:03:58 AM PDT 24
Peak memory 239492 kb
Host smart-2760b5d0-fc4f-4add-b87c-85b6ea819f98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708451053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1708451053
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4096947060
Short name T94
Test name
Test status
Simulation time 13031218512 ps
CPU time 28.79 seconds
Started Jul 02 08:01:44 AM PDT 24
Finished Jul 02 08:02:29 AM PDT 24
Peak memory 214464 kb
Host smart-6265c37d-6d36-440f-a4fd-d018f39e3c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096947060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4096947060
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.677299148
Short name T293
Test name
Test status
Simulation time 6260686164 ps
CPU time 36.27 seconds
Started Jul 02 08:01:43 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 219436 kb
Host smart-c268e1f0-b26b-40f2-a6e6-f36e9e5451ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677299148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.677299148
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3958884393
Short name T20
Test name
Test status
Simulation time 1028638949 ps
CPU time 7.73 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:32 AM PDT 24
Peak memory 211256 kb
Host smart-6c472312-1e25-4107-9b00-01ac886f6965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958884393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3958884393
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3348705546
Short name T258
Test name
Test status
Simulation time 94468863263 ps
CPU time 272.28 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:07:01 AM PDT 24
Peak memory 233356 kb
Host smart-d93b6187-3b37-4078-a16f-6d978f2a8e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348705546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3348705546
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2308839862
Short name T324
Test name
Test status
Simulation time 831084575 ps
CPU time 9.33 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 212120 kb
Host smart-f40cb926-dbfa-49ce-9f9d-228d52ac7a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308839862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2308839862
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.979290635
Short name T282
Test name
Test status
Simulation time 192751528 ps
CPU time 5.49 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:02:28 AM PDT 24
Peak memory 211372 kb
Host smart-85c5b129-f7d8-4147-a2e0-edf5723bcc9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979290635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.979290635
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.784577457
Short name T334
Test name
Test status
Simulation time 192349507 ps
CPU time 10.14 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:36 AM PDT 24
Peak memory 213828 kb
Host smart-f4374e6b-2e6c-44bd-8290-17903ea9c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784577457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.784577457
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3660294503
Short name T284
Test name
Test status
Simulation time 8977873314 ps
CPU time 21.13 seconds
Started Jul 02 08:02:17 AM PDT 24
Finished Jul 02 08:02:53 AM PDT 24
Peak memory 211496 kb
Host smart-887bb227-9989-4c94-b7ad-ed6d4f7e6723
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660294503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3660294503
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1492205050
Short name T40
Test name
Test status
Simulation time 33239240780 ps
CPU time 2652.38 seconds
Started Jul 02 08:02:18 AM PDT 24
Finished Jul 02 08:46:46 AM PDT 24
Peak memory 229296 kb
Host smart-d2eeb28e-0669-4ee6-8f1e-e57313878237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492205050 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1492205050
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.444232171
Short name T195
Test name
Test status
Simulation time 191060816 ps
CPU time 4.29 seconds
Started Jul 02 08:02:25 AM PDT 24
Finished Jul 02 08:02:44 AM PDT 24
Peak memory 211292 kb
Host smart-7131f886-ed5c-4752-9c5c-5684a6f3fb22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444232171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.444232171
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4133752184
Short name T122
Test name
Test status
Simulation time 1509846342 ps
CPU time 90.2 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:03:52 AM PDT 24
Peak memory 237728 kb
Host smart-091e4bae-6329-4558-8094-9a378a6868d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133752184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4133752184
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4207722921
Short name T275
Test name
Test status
Simulation time 2135560373 ps
CPU time 22.31 seconds
Started Jul 02 08:02:18 AM PDT 24
Finished Jul 02 08:02:55 AM PDT 24
Peak memory 211896 kb
Host smart-83121278-d565-4e6e-85b9-f336989224f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207722921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4207722921
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1476439189
Short name T221
Test name
Test status
Simulation time 181269498 ps
CPU time 6.6 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:33 AM PDT 24
Peak memory 211412 kb
Host smart-c72b207f-af8f-46e3-a945-04486a9e5bd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476439189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1476439189
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.266340486
Short name T136
Test name
Test status
Simulation time 1819930780 ps
CPU time 12.3 seconds
Started Jul 02 08:02:17 AM PDT 24
Finished Jul 02 08:02:45 AM PDT 24
Peak memory 214092 kb
Host smart-c307afe3-a191-4494-93f5-f0563a4aef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266340486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.266340486
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.457115228
Short name T251
Test name
Test status
Simulation time 65314856372 ps
CPU time 54.87 seconds
Started Jul 02 08:02:24 AM PDT 24
Finished Jul 02 08:03:35 AM PDT 24
Peak memory 216500 kb
Host smart-5b3b22a8-2d78-4bb3-94e1-9745c2de8344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457115228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.457115228
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2461995136
Short name T250
Test name
Test status
Simulation time 7412872300 ps
CPU time 15.49 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 211416 kb
Host smart-36f436a8-b94a-4d9d-adc2-ae1f2eed15a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461995136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2461995136
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1204754344
Short name T197
Test name
Test status
Simulation time 5376050186 ps
CPU time 10.24 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 211468 kb
Host smart-f5de53e2-9222-4efd-bf43-be6890c826cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204754344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1204754344
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4251738399
Short name T187
Test name
Test status
Simulation time 242350473 ps
CPU time 10.16 seconds
Started Jul 02 08:02:17 AM PDT 24
Finished Jul 02 08:02:42 AM PDT 24
Peak memory 213232 kb
Host smart-f0b926fb-7c0e-43c4-9e31-01da897ad49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251738399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4251738399
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2960872413
Short name T196
Test name
Test status
Simulation time 47152410211 ps
CPU time 38.14 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:03:05 AM PDT 24
Peak memory 216480 kb
Host smart-3c83f136-f481-42b7-ad98-82e74705af57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960872413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2960872413
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3707784083
Short name T347
Test name
Test status
Simulation time 71960731748 ps
CPU time 1425.38 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:26:13 AM PDT 24
Peak memory 235880 kb
Host smart-f22b291a-08af-4030-b0d3-9c5298de8c79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707784083 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3707784083
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.500562800
Short name T173
Test name
Test status
Simulation time 88877814 ps
CPU time 4.3 seconds
Started Jul 02 08:02:17 AM PDT 24
Finished Jul 02 08:02:36 AM PDT 24
Peak memory 211288 kb
Host smart-baa3c8fc-b41a-4a7b-8ea3-a3103c28cb9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500562800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.500562800
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3972931393
Short name T158
Test name
Test status
Simulation time 47437022521 ps
CPU time 258.07 seconds
Started Jul 02 08:02:19 AM PDT 24
Finished Jul 02 08:06:51 AM PDT 24
Peak memory 225876 kb
Host smart-ee4397ee-a60f-4231-8ec0-58a1a6ad067b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972931393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3972931393
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.753625834
Short name T363
Test name
Test status
Simulation time 1077026598 ps
CPU time 16.5 seconds
Started Jul 02 08:02:12 AM PDT 24
Finished Jul 02 08:02:43 AM PDT 24
Peak memory 211896 kb
Host smart-53f733f5-253a-4283-bf23-54cb3e26e573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753625834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.753625834
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1335370333
Short name T356
Test name
Test status
Simulation time 4313701925 ps
CPU time 12.31 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 211476 kb
Host smart-5734b0dc-b5de-4931-a111-2455e4b495f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335370333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1335370333
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3638741253
Short name T66
Test name
Test status
Simulation time 195383701 ps
CPU time 10.49 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:37 AM PDT 24
Peak memory 213508 kb
Host smart-c8e4e9ea-a31f-4579-9464-e0587e807be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638741253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3638741253
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.795459370
Short name T167
Test name
Test status
Simulation time 725080606 ps
CPU time 5.35 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:02:34 AM PDT 24
Peak memory 211352 kb
Host smart-988b4388-d722-40bc-80f1-afc20f73172a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795459370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.795459370
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4097854128
Short name T310
Test name
Test status
Simulation time 38314122359 ps
CPU time 183.88 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:05:23 AM PDT 24
Peak memory 234008 kb
Host smart-955d1bf9-11e6-4051-b9b6-7ed5efee8001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097854128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4097854128
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2775409057
Short name T249
Test name
Test status
Simulation time 2659037090 ps
CPU time 17.72 seconds
Started Jul 02 08:02:09 AM PDT 24
Finished Jul 02 08:02:42 AM PDT 24
Peak memory 211956 kb
Host smart-c205f8c0-27f6-44ed-b44a-e3aed285625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775409057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2775409057
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3799177695
Short name T145
Test name
Test status
Simulation time 2202536699 ps
CPU time 11.33 seconds
Started Jul 02 08:02:12 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 211380 kb
Host smart-49a3b624-8fd0-41e7-87ee-82e8eb3c4af6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3799177695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3799177695
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2076980
Short name T228
Test name
Test status
Simulation time 5037387448 ps
CPU time 18.26 seconds
Started Jul 02 08:02:09 AM PDT 24
Finished Jul 02 08:02:42 AM PDT 24
Peak memory 213768 kb
Host smart-62689492-8dd4-4935-a5a8-953bc9273729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2076980
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1416212808
Short name T265
Test name
Test status
Simulation time 30295668615 ps
CPU time 85.52 seconds
Started Jul 02 08:02:16 AM PDT 24
Finished Jul 02 08:03:56 AM PDT 24
Peak memory 219344 kb
Host smart-7a054a5c-1f94-42a6-bc69-1543ce32ff37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416212808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1416212808
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4269141334
Short name T330
Test name
Test status
Simulation time 943035959 ps
CPU time 9.57 seconds
Started Jul 02 08:02:23 AM PDT 24
Finished Jul 02 08:02:48 AM PDT 24
Peak memory 211292 kb
Host smart-b936d2f4-f261-4720-9178-9a8f74135310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269141334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4269141334
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3838214361
Short name T234
Test name
Test status
Simulation time 45247676774 ps
CPU time 279.54 seconds
Started Jul 02 08:02:17 AM PDT 24
Finished Jul 02 08:07:13 AM PDT 24
Peak memory 240052 kb
Host smart-3fd8ee20-4b52-45bf-9cba-65e3e41ad6ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838214361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3838214361
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.695592633
Short name T333
Test name
Test status
Simulation time 371420352 ps
CPU time 9.37 seconds
Started Jul 02 08:02:17 AM PDT 24
Finished Jul 02 08:02:42 AM PDT 24
Peak memory 211940 kb
Host smart-b20d196f-7a21-4595-b75d-66b1d001a497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695592633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.695592633
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1917634855
Short name T312
Test name
Test status
Simulation time 100419665 ps
CPU time 5.81 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:31 AM PDT 24
Peak memory 211412 kb
Host smart-2b206505-3ea6-428c-a017-2ce31046822a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1917634855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1917634855
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2750002744
Short name T306
Test name
Test status
Simulation time 716637725 ps
CPU time 9.81 seconds
Started Jul 02 08:02:25 AM PDT 24
Finished Jul 02 08:02:51 AM PDT 24
Peak memory 213392 kb
Host smart-23258945-29bc-4939-b5b3-4902b1c90a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750002744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2750002744
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3583918672
Short name T6
Test name
Test status
Simulation time 24788113499 ps
CPU time 69.15 seconds
Started Jul 02 08:02:23 AM PDT 24
Finished Jul 02 08:03:48 AM PDT 24
Peak memory 217860 kb
Host smart-d9ad07f0-2f82-41ea-bf88-7e82347e25ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583918672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3583918672
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3436179152
Short name T177
Test name
Test status
Simulation time 93706064390 ps
CPU time 3650.33 seconds
Started Jul 02 08:02:18 AM PDT 24
Finished Jul 02 09:03:24 AM PDT 24
Peak memory 252400 kb
Host smart-3ec8510c-2f54-48c1-8ad6-1e1a1e1dacdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436179152 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3436179152
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4246537888
Short name T298
Test name
Test status
Simulation time 1559511110 ps
CPU time 13.46 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:02:42 AM PDT 24
Peak memory 211308 kb
Host smart-619e63dc-0c23-4e04-a199-22a9f3ca38a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246537888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4246537888
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2034296340
Short name T33
Test name
Test status
Simulation time 31921068908 ps
CPU time 294.09 seconds
Started Jul 02 08:02:16 AM PDT 24
Finished Jul 02 08:07:25 AM PDT 24
Peak memory 236864 kb
Host smart-6dfea400-8de4-4e23-911f-7382a0c437e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034296340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2034296340
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2867056366
Short name T22
Test name
Test status
Simulation time 2040447543 ps
CPU time 22.13 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:02:49 AM PDT 24
Peak memory 211912 kb
Host smart-aafea5ce-42b0-42c2-beda-13e1875212f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867056366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2867056366
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1213622526
Short name T237
Test name
Test status
Simulation time 196765846 ps
CPU time 5.62 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:02:33 AM PDT 24
Peak memory 210832 kb
Host smart-bd1f0a5e-ec5a-4589-b762-427be42b57c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1213622526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1213622526
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.239556513
Short name T79
Test name
Test status
Simulation time 2702987000 ps
CPU time 17.91 seconds
Started Jul 02 08:02:24 AM PDT 24
Finished Jul 02 08:02:58 AM PDT 24
Peak memory 212680 kb
Host smart-a8287890-c0cd-4cfa-89b1-c670a58e5b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239556513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.239556513
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3473332993
Short name T15
Test name
Test status
Simulation time 19254716938 ps
CPU time 46.54 seconds
Started Jul 02 08:02:09 AM PDT 24
Finished Jul 02 08:03:10 AM PDT 24
Peak memory 214296 kb
Host smart-2289ef4d-d442-4ae0-bc2f-38599a5e6b98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473332993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3473332993
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2117134732
Short name T321
Test name
Test status
Simulation time 1930053843 ps
CPU time 13.14 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:02:42 AM PDT 24
Peak memory 211336 kb
Host smart-568907f3-69b0-4b6a-8d16-69df549d2bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117134732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2117134732
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2755447660
Short name T148
Test name
Test status
Simulation time 149484291802 ps
CPU time 279.85 seconds
Started Jul 02 08:02:27 AM PDT 24
Finished Jul 02 08:07:24 AM PDT 24
Peak memory 212612 kb
Host smart-57a42d98-b741-4d9b-9db2-821ce41ebf2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755447660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2755447660
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2134679208
Short name T178
Test name
Test status
Simulation time 7862575166 ps
CPU time 31.1 seconds
Started Jul 02 08:02:20 AM PDT 24
Finished Jul 02 08:03:06 AM PDT 24
Peak memory 212420 kb
Host smart-ee2cf934-efb6-4a2d-8e8c-86c9fc022f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134679208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2134679208
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3771352027
Short name T247
Test name
Test status
Simulation time 966048088 ps
CPU time 8.27 seconds
Started Jul 02 08:02:18 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 211412 kb
Host smart-3d5173d6-c514-4f35-84b7-e33d5006d52b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771352027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3771352027
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.141281051
Short name T156
Test name
Test status
Simulation time 1374800205 ps
CPU time 9.67 seconds
Started Jul 02 08:02:26 AM PDT 24
Finished Jul 02 08:02:51 AM PDT 24
Peak memory 213252 kb
Host smart-95f9e6cc-29da-4376-a898-d959ea42fd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141281051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.141281051
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1213736955
Short name T171
Test name
Test status
Simulation time 14649474377 ps
CPU time 25.94 seconds
Started Jul 02 08:02:30 AM PDT 24
Finished Jul 02 08:03:13 AM PDT 24
Peak memory 212896 kb
Host smart-58781c08-6980-44e1-b745-7de0ae2e8f47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213736955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1213736955
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2790750711
Short name T353
Test name
Test status
Simulation time 94416551046 ps
CPU time 1719.57 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:31:05 AM PDT 24
Peak memory 235832 kb
Host smart-31653c28-b1cd-4a1f-9b14-18afadba1238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790750711 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2790750711
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3134095196
Short name T214
Test name
Test status
Simulation time 1325000629 ps
CPU time 12.24 seconds
Started Jul 02 08:02:12 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 211344 kb
Host smart-5b565218-d071-41eb-b8da-adcc60d4e09c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134095196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3134095196
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1803885826
Short name T29
Test name
Test status
Simulation time 68380477668 ps
CPU time 316.77 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:07:43 AM PDT 24
Peak memory 237812 kb
Host smart-9d0fc5ef-9a2d-40f3-ad8d-da1f33718929
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803885826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1803885826
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1876285655
Short name T332
Test name
Test status
Simulation time 6365698007 ps
CPU time 28.01 seconds
Started Jul 02 08:02:21 AM PDT 24
Finished Jul 02 08:03:03 AM PDT 24
Peak memory 212268 kb
Host smart-5a699407-baf3-44ef-a727-fe586b4f988a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876285655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1876285655
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2133842167
Short name T124
Test name
Test status
Simulation time 399573773 ps
CPU time 8.11 seconds
Started Jul 02 08:02:42 AM PDT 24
Finished Jul 02 08:03:06 AM PDT 24
Peak memory 211408 kb
Host smart-b0885d8f-bc4e-45ff-9571-edc12ee2c354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133842167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2133842167
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2241531112
Short name T207
Test name
Test status
Simulation time 12474141323 ps
CPU time 29.48 seconds
Started Jul 02 08:02:35 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 213780 kb
Host smart-372042c7-aa47-47df-ac2e-eef02fb013b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241531112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2241531112
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1702593738
Short name T344
Test name
Test status
Simulation time 5333066460 ps
CPU time 56.49 seconds
Started Jul 02 08:02:26 AM PDT 24
Finished Jul 02 08:03:38 AM PDT 24
Peak memory 216996 kb
Host smart-9305c7c9-21a6-497c-ad1a-a6f3d320ebb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702593738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1702593738
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4060775978
Short name T39
Test name
Test status
Simulation time 22232065472 ps
CPU time 2013.94 seconds
Started Jul 02 08:02:08 AM PDT 24
Finished Jul 02 08:35:56 AM PDT 24
Peak memory 227652 kb
Host smart-cb76a3dd-8f77-4abc-a335-07eb48c03d40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060775978 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4060775978
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3937554512
Short name T85
Test name
Test status
Simulation time 7408543712 ps
CPU time 15.25 seconds
Started Jul 02 08:02:26 AM PDT 24
Finished Jul 02 08:02:57 AM PDT 24
Peak memory 211396 kb
Host smart-5d73f964-9fed-4ddd-b860-470d28ead918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937554512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3937554512
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3391586606
Short name T270
Test name
Test status
Simulation time 5626656218 ps
CPU time 57.79 seconds
Started Jul 02 08:02:09 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 237572 kb
Host smart-4eb20b8c-18df-40fa-ba0c-0743ca6a64c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391586606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3391586606
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3433919514
Short name T121
Test name
Test status
Simulation time 4958514426 ps
CPU time 23.54 seconds
Started Jul 02 08:02:12 AM PDT 24
Finished Jul 02 08:02:50 AM PDT 24
Peak memory 212260 kb
Host smart-79dd9e0b-03e6-4069-938b-2d396a296b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433919514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3433919514
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2459437077
Short name T110
Test name
Test status
Simulation time 4935716207 ps
CPU time 12.87 seconds
Started Jul 02 08:02:12 AM PDT 24
Finished Jul 02 08:02:40 AM PDT 24
Peak memory 211440 kb
Host smart-94edb54a-f276-4b5e-9228-ab26c867facd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459437077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2459437077
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1964632990
Short name T323
Test name
Test status
Simulation time 14147308356 ps
CPU time 33.82 seconds
Started Jul 02 08:02:28 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 214508 kb
Host smart-b5513bcb-2428-4899-9fbf-d92fd5873fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964632990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1964632990
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2045319207
Short name T268
Test name
Test status
Simulation time 468305554 ps
CPU time 25.99 seconds
Started Jul 02 08:02:17 AM PDT 24
Finished Jul 02 08:02:58 AM PDT 24
Peak memory 216468 kb
Host smart-ab1ee00d-a474-4a97-8152-f48e734c4e18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045319207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2045319207
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.450411968
Short name T14
Test name
Test status
Simulation time 41285385429 ps
CPU time 1647.84 seconds
Started Jul 02 08:02:16 AM PDT 24
Finished Jul 02 08:29:58 AM PDT 24
Peak memory 232684 kb
Host smart-8bbfa3f5-4499-477f-b613-def35cae6be5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450411968 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.450411968
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.376815656
Short name T164
Test name
Test status
Simulation time 9489219780 ps
CPU time 10.69 seconds
Started Jul 02 08:02:00 AM PDT 24
Finished Jul 02 08:02:25 AM PDT 24
Peak memory 211320 kb
Host smart-b8ac5ad4-1bfd-4dd1-9e56-35c2ae6a2fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376815656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.376815656
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.502459116
Short name T180
Test name
Test status
Simulation time 6106517022 ps
CPU time 120.55 seconds
Started Jul 02 08:01:43 AM PDT 24
Finished Jul 02 08:04:01 AM PDT 24
Peak memory 237664 kb
Host smart-70dedc84-e563-42f2-b5bc-56d806ca474f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502459116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.502459116
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1709993764
Short name T230
Test name
Test status
Simulation time 333720292 ps
CPU time 9.72 seconds
Started Jul 02 08:01:44 AM PDT 24
Finished Jul 02 08:02:10 AM PDT 24
Peak memory 211920 kb
Host smart-c5227519-cab1-4e21-8432-9895c3c3e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709993764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1709993764
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.468097622
Short name T123
Test name
Test status
Simulation time 869850479 ps
CPU time 7.28 seconds
Started Jul 02 08:01:46 AM PDT 24
Finished Jul 02 08:02:10 AM PDT 24
Peak memory 211400 kb
Host smart-d4867303-1e6a-418e-baf2-0919b9500668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468097622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.468097622
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1360106755
Short name T18
Test name
Test status
Simulation time 6216637787 ps
CPU time 106.86 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:04:06 AM PDT 24
Peak memory 236848 kb
Host smart-fc956e58-9453-4f4a-985b-0630e16cb0e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360106755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1360106755
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1904503910
Short name T257
Test name
Test status
Simulation time 1385906647 ps
CPU time 12.46 seconds
Started Jul 02 08:02:01 AM PDT 24
Finished Jul 02 08:02:27 AM PDT 24
Peak memory 213896 kb
Host smart-a7f216b6-e136-44e0-9e42-90edd1b62cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904503910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1904503910
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.838557771
Short name T203
Test name
Test status
Simulation time 10027792634 ps
CPU time 47.71 seconds
Started Jul 02 08:01:57 AM PDT 24
Finished Jul 02 08:02:59 AM PDT 24
Peak memory 215952 kb
Host smart-f96c6142-f390-49e1-84d0-b3c6cc2d7b8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838557771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.838557771
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3220109776
Short name T274
Test name
Test status
Simulation time 24001349795 ps
CPU time 252.58 seconds
Started Jul 02 08:01:42 AM PDT 24
Finished Jul 02 08:06:12 AM PDT 24
Peak memory 231356 kb
Host smart-d4e7db31-23c1-4cf9-b99d-27363c23cba2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220109776 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3220109776
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.59311921
Short name T243
Test name
Test status
Simulation time 175512109 ps
CPU time 4.19 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:28 AM PDT 24
Peak memory 211364 kb
Host smart-52dd2f36-c74f-4c92-81fb-751be5f8198b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59311921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.59311921
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4161858131
Short name T295
Test name
Test status
Simulation time 22298188737 ps
CPU time 83.72 seconds
Started Jul 02 08:02:21 AM PDT 24
Finished Jul 02 08:03:59 AM PDT 24
Peak memory 236236 kb
Host smart-58e39aa3-094c-4490-aee8-b950451c41a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161858131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4161858131
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3832679033
Short name T83
Test name
Test status
Simulation time 17499459911 ps
CPU time 33.99 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:03:00 AM PDT 24
Peak memory 211464 kb
Host smart-68b8aea9-09c4-4f3a-9201-097ec90ef58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832679033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3832679033
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.199204245
Short name T338
Test name
Test status
Simulation time 1610682409 ps
CPU time 14.58 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:40 AM PDT 24
Peak memory 211400 kb
Host smart-4c3082b9-ad3a-4e6f-9bec-39f4f98d9cf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199204245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.199204245
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.49889321
Short name T65
Test name
Test status
Simulation time 2282523964 ps
CPU time 21.25 seconds
Started Jul 02 08:02:26 AM PDT 24
Finished Jul 02 08:03:02 AM PDT 24
Peak memory 214016 kb
Host smart-57eae42b-c464-480f-93b2-35723eb9d4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49889321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.49889321
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1732426927
Short name T209
Test name
Test status
Simulation time 4361017150 ps
CPU time 40.49 seconds
Started Jul 02 08:02:26 AM PDT 24
Finished Jul 02 08:03:22 AM PDT 24
Peak memory 212128 kb
Host smart-b37dd87b-da04-4a08-b772-0842db059cc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732426927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1732426927
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3218894346
Short name T200
Test name
Test status
Simulation time 6500988688 ps
CPU time 11.51 seconds
Started Jul 02 08:02:23 AM PDT 24
Finished Jul 02 08:02:49 AM PDT 24
Peak memory 211404 kb
Host smart-ec0c1d35-9969-4550-aa82-db057628a54a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218894346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3218894346
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2320171990
Short name T201
Test name
Test status
Simulation time 1185889545 ps
CPU time 16.92 seconds
Started Jul 02 08:02:22 AM PDT 24
Finished Jul 02 08:02:53 AM PDT 24
Peak memory 211928 kb
Host smart-7090198b-f396-4c13-97af-96b27eb40346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320171990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2320171990
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2916108020
Short name T239
Test name
Test status
Simulation time 1896676837 ps
CPU time 16.36 seconds
Started Jul 02 08:02:23 AM PDT 24
Finished Jul 02 08:02:54 AM PDT 24
Peak memory 211400 kb
Host smart-acf15d3e-6299-482b-b1ff-b0ee38ea3256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916108020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2916108020
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2558266271
Short name T129
Test name
Test status
Simulation time 3883817018 ps
CPU time 35.65 seconds
Started Jul 02 08:02:29 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 213756 kb
Host smart-5f2227c6-cb79-45ad-b425-d8bc7b639b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558266271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2558266271
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.727500673
Short name T235
Test name
Test status
Simulation time 1724514234 ps
CPU time 39.25 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:03:05 AM PDT 24
Peak memory 216864 kb
Host smart-fd290653-12ff-4dd9-a676-dcff2562c47d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727500673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.727500673
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3093793779
Short name T255
Test name
Test status
Simulation time 1387962104 ps
CPU time 9.89 seconds
Started Jul 02 08:02:29 AM PDT 24
Finished Jul 02 08:03:01 AM PDT 24
Peak memory 211332 kb
Host smart-ea366ae2-aab7-4730-ae4f-bb3591b2db7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093793779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3093793779
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.530756507
Short name T215
Test name
Test status
Simulation time 56879862803 ps
CPU time 306 seconds
Started Jul 02 08:02:41 AM PDT 24
Finished Jul 02 08:08:04 AM PDT 24
Peak memory 233808 kb
Host smart-186498f4-c1bd-4c85-9756-c8d0259c5187
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530756507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.530756507
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3680365361
Short name T80
Test name
Test status
Simulation time 4587266059 ps
CPU time 17.39 seconds
Started Jul 02 08:02:32 AM PDT 24
Finished Jul 02 08:03:05 AM PDT 24
Peak memory 212292 kb
Host smart-3a2c9722-9702-495e-b806-cd327f856276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680365361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3680365361
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.754510019
Short name T358
Test name
Test status
Simulation time 307820087 ps
CPU time 7.15 seconds
Started Jul 02 08:02:27 AM PDT 24
Finished Jul 02 08:02:50 AM PDT 24
Peak memory 211356 kb
Host smart-5b0392e8-a090-4f66-9982-e9762fa14460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754510019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.754510019
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1280003414
Short name T287
Test name
Test status
Simulation time 8949163293 ps
CPU time 22.84 seconds
Started Jul 02 08:02:22 AM PDT 24
Finished Jul 02 08:02:59 AM PDT 24
Peak memory 214588 kb
Host smart-82352170-5fe1-45ba-928a-248a44dc2c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280003414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1280003414
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3642049614
Short name T308
Test name
Test status
Simulation time 3510855603 ps
CPU time 18.27 seconds
Started Jul 02 08:02:33 AM PDT 24
Finished Jul 02 08:03:08 AM PDT 24
Peak memory 211344 kb
Host smart-cb624d38-a421-4e49-8c7c-ca02841f29c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642049614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3642049614
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1010909468
Short name T21
Test name
Test status
Simulation time 5193461762 ps
CPU time 11.93 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:38 AM PDT 24
Peak memory 211412 kb
Host smart-469a5e36-bf05-4683-84b2-5b12286d1675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010909468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1010909468
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3621206223
Short name T4
Test name
Test status
Simulation time 68856260249 ps
CPU time 231.57 seconds
Started Jul 02 08:02:54 AM PDT 24
Finished Jul 02 08:07:04 AM PDT 24
Peak memory 237840 kb
Host smart-b7fdafce-0bf5-4e98-b692-b1dcea249d48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621206223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3621206223
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1374868169
Short name T285
Test name
Test status
Simulation time 7510526260 ps
CPU time 30.87 seconds
Started Jul 02 08:02:24 AM PDT 24
Finished Jul 02 08:03:11 AM PDT 24
Peak memory 212464 kb
Host smart-b60e6a18-53e3-4f06-8bfb-5b94bf9ef6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374868169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1374868169
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3840209804
Short name T125
Test name
Test status
Simulation time 1910399479 ps
CPU time 15.99 seconds
Started Jul 02 08:02:39 AM PDT 24
Finished Jul 02 08:03:12 AM PDT 24
Peak memory 211352 kb
Host smart-e9ba2a6b-bcb4-4b57-8c2a-5e9d8eb59bf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3840209804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3840209804
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3317256770
Short name T267
Test name
Test status
Simulation time 2821077359 ps
CPU time 29.27 seconds
Started Jul 02 08:02:35 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 213464 kb
Host smart-ca0966d1-491a-4ff4-9d17-6ea46e66c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317256770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3317256770
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1982651798
Short name T130
Test name
Test status
Simulation time 2287496475 ps
CPU time 27.41 seconds
Started Jul 02 08:02:13 AM PDT 24
Finished Jul 02 08:02:55 AM PDT 24
Peak memory 213812 kb
Host smart-87ae327c-5b0a-4408-9fc2-ec153925bdeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982651798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1982651798
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.428403418
Short name T10
Test name
Test status
Simulation time 1722022880 ps
CPU time 7.34 seconds
Started Jul 02 08:02:20 AM PDT 24
Finished Jul 02 08:02:43 AM PDT 24
Peak memory 211368 kb
Host smart-eda16779-7ebd-4326-b9b1-224d6148c089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428403418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.428403418
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3706942631
Short name T132
Test name
Test status
Simulation time 22270885455 ps
CPU time 178.59 seconds
Started Jul 02 08:02:17 AM PDT 24
Finished Jul 02 08:05:30 AM PDT 24
Peak memory 211356 kb
Host smart-68690b22-9ddb-447d-8602-5f3751c7c714
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706942631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3706942631
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.986269378
Short name T289
Test name
Test status
Simulation time 2404691934 ps
CPU time 16.88 seconds
Started Jul 02 08:02:25 AM PDT 24
Finished Jul 02 08:02:58 AM PDT 24
Peak memory 212116 kb
Host smart-4d397e36-fb30-42ad-ab8c-b60d8e09ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986269378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.986269378
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2794752829
Short name T269
Test name
Test status
Simulation time 154469057 ps
CPU time 5.64 seconds
Started Jul 02 08:02:11 AM PDT 24
Finished Jul 02 08:02:32 AM PDT 24
Peak memory 211372 kb
Host smart-ca0cb8e8-3808-41ef-86bf-318450e5fa62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2794752829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2794752829
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1366194587
Short name T142
Test name
Test status
Simulation time 1802101035 ps
CPU time 10.19 seconds
Started Jul 02 08:02:32 AM PDT 24
Finished Jul 02 08:02:58 AM PDT 24
Peak memory 212876 kb
Host smart-12a95699-2986-4ac1-a30e-7b3c210af550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366194587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1366194587
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1251360099
Short name T335
Test name
Test status
Simulation time 13267588313 ps
CPU time 55.27 seconds
Started Jul 02 08:02:22 AM PDT 24
Finished Jul 02 08:03:32 AM PDT 24
Peak memory 216728 kb
Host smart-e732a194-4c94-41f7-8f30-192d568b471a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251360099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1251360099
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1772691231
Short name T36
Test name
Test status
Simulation time 8242485149 ps
CPU time 481.87 seconds
Started Jul 02 08:02:22 AM PDT 24
Finished Jul 02 08:10:38 AM PDT 24
Peak memory 222332 kb
Host smart-62a06aff-d2e9-4bfd-82f9-4d239052035b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772691231 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1772691231
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1311893525
Short name T114
Test name
Test status
Simulation time 778635347 ps
CPU time 6.89 seconds
Started Jul 02 08:02:38 AM PDT 24
Finished Jul 02 08:03:02 AM PDT 24
Peak memory 211364 kb
Host smart-e0362703-765a-4c6d-8906-a7b5d206a733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311893525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1311893525
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.403053071
Short name T304
Test name
Test status
Simulation time 2312982107 ps
CPU time 124.69 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:04:35 AM PDT 24
Peak memory 227584 kb
Host smart-25d6e48e-956a-4e02-b04e-c30c0f910d0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403053071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.403053071
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3021606754
Short name T172
Test name
Test status
Simulation time 3754871194 ps
CPU time 28.52 seconds
Started Jul 02 08:02:29 AM PDT 24
Finished Jul 02 08:03:14 AM PDT 24
Peak memory 211884 kb
Host smart-3c7a3bd8-dec9-40b6-8c71-33d3648041e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021606754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3021606754
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2388159129
Short name T366
Test name
Test status
Simulation time 6362278296 ps
CPU time 14.52 seconds
Started Jul 02 08:02:16 AM PDT 24
Finished Jul 02 08:02:46 AM PDT 24
Peak memory 211500 kb
Host smart-a8eda791-1541-45a9-8f42-ade973ab7d12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388159129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2388159129
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2476003094
Short name T296
Test name
Test status
Simulation time 268472408 ps
CPU time 9.95 seconds
Started Jul 02 08:02:32 AM PDT 24
Finished Jul 02 08:02:58 AM PDT 24
Peak memory 212968 kb
Host smart-305544a1-2683-47a6-b9f7-f90042a6ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476003094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2476003094
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.576781395
Short name T113
Test name
Test status
Simulation time 8207964299 ps
CPU time 65.11 seconds
Started Jul 02 08:02:37 AM PDT 24
Finished Jul 02 08:03:59 AM PDT 24
Peak memory 215468 kb
Host smart-99f445a4-4e62-46e6-b3a2-b74b40639d5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576781395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.576781395
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2240181309
Short name T34
Test name
Test status
Simulation time 218064418735 ps
CPU time 1801.92 seconds
Started Jul 02 08:02:42 AM PDT 24
Finished Jul 02 08:33:00 AM PDT 24
Peak memory 236236 kb
Host smart-d8c2f573-60ec-4cc3-b999-16870f766b30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240181309 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2240181309
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.482820971
Short name T246
Test name
Test status
Simulation time 378892355 ps
CPU time 4.15 seconds
Started Jul 02 08:02:34 AM PDT 24
Finished Jul 02 08:02:55 AM PDT 24
Peak memory 211232 kb
Host smart-4a1c784b-d521-48aa-814c-fb7fb8b3d879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482820971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.482820971
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2932201469
Short name T263
Test name
Test status
Simulation time 43044768589 ps
CPU time 360.19 seconds
Started Jul 02 08:02:36 AM PDT 24
Finished Jul 02 08:08:52 AM PDT 24
Peak memory 234936 kb
Host smart-be698824-76f0-4be7-b0bb-241a58ea008d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932201469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2932201469
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2352522465
Short name T343
Test name
Test status
Simulation time 243142735 ps
CPU time 9.55 seconds
Started Jul 02 08:02:37 AM PDT 24
Finished Jul 02 08:03:03 AM PDT 24
Peak memory 211812 kb
Host smart-19ce5ceb-9402-4f96-b020-8e33deb13998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352522465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2352522465
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2146656790
Short name T283
Test name
Test status
Simulation time 2120163205 ps
CPU time 17.46 seconds
Started Jul 02 08:02:30 AM PDT 24
Finished Jul 02 08:03:04 AM PDT 24
Peak memory 211384 kb
Host smart-325d0997-1509-48d2-bc61-997f70e56a74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146656790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2146656790
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3888385614
Short name T238
Test name
Test status
Simulation time 697414964 ps
CPU time 10.33 seconds
Started Jul 02 08:02:28 AM PDT 24
Finished Jul 02 08:02:55 AM PDT 24
Peak memory 213292 kb
Host smart-98496935-d6df-498d-bacf-fe2efde18b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888385614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3888385614
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3150645878
Short name T109
Test name
Test status
Simulation time 18919357604 ps
CPU time 53.7 seconds
Started Jul 02 08:02:25 AM PDT 24
Finished Jul 02 08:03:34 AM PDT 24
Peak memory 217652 kb
Host smart-0f7e0a24-c8a1-46ce-9e68-6d7b6b7dd030
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150645878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3150645878
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1213184786
Short name T163
Test name
Test status
Simulation time 85867490 ps
CPU time 4.25 seconds
Started Jul 02 08:02:28 AM PDT 24
Finished Jul 02 08:02:49 AM PDT 24
Peak memory 211332 kb
Host smart-8bae7cb5-af80-4a79-8764-b0ca5c858ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213184786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1213184786
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1005735890
Short name T318
Test name
Test status
Simulation time 75670691164 ps
CPU time 226.29 seconds
Started Jul 02 08:02:33 AM PDT 24
Finished Jul 02 08:06:36 AM PDT 24
Peak memory 212632 kb
Host smart-eb12d39c-568b-4c0e-b405-6ffd37ee91b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005735890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1005735890
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2774542179
Short name T174
Test name
Test status
Simulation time 2439537788 ps
CPU time 14.6 seconds
Started Jul 02 08:02:32 AM PDT 24
Finished Jul 02 08:03:03 AM PDT 24
Peak memory 211940 kb
Host smart-49aeb8cb-a5df-412b-b507-d98508a684f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774542179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2774542179
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3498334078
Short name T205
Test name
Test status
Simulation time 1964743795 ps
CPU time 12.27 seconds
Started Jul 02 08:02:32 AM PDT 24
Finished Jul 02 08:03:00 AM PDT 24
Peak memory 211260 kb
Host smart-3366b077-784e-455b-86cd-cff82eb116c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498334078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3498334078
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.417730928
Short name T64
Test name
Test status
Simulation time 3937177457 ps
CPU time 41.33 seconds
Started Jul 02 08:02:37 AM PDT 24
Finished Jul 02 08:03:35 AM PDT 24
Peak memory 213888 kb
Host smart-9cf6a837-8bb0-4a29-8b41-2413e0471865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417730928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.417730928
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.47697014
Short name T208
Test name
Test status
Simulation time 40679344510 ps
CPU time 100.29 seconds
Started Jul 02 08:02:33 AM PDT 24
Finished Jul 02 08:04:30 AM PDT 24
Peak memory 218956 kb
Host smart-b03578fc-aaff-4584-8848-73291553aee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47697014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.rom_ctrl_stress_all.47697014
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4160668583
Short name T278
Test name
Test status
Simulation time 2241001502 ps
CPU time 10.62 seconds
Started Jul 02 08:02:31 AM PDT 24
Finished Jul 02 08:02:59 AM PDT 24
Peak memory 211276 kb
Host smart-8c965de8-7225-4c47-9b60-770112c48d8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160668583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4160668583
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1536406978
Short name T87
Test name
Test status
Simulation time 16733324369 ps
CPU time 337.32 seconds
Started Jul 02 08:02:37 AM PDT 24
Finished Jul 02 08:08:31 AM PDT 24
Peak memory 237844 kb
Host smart-8769cccb-d89b-4d0e-992c-0d1fa7060e42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536406978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1536406978
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1672075124
Short name T204
Test name
Test status
Simulation time 176186793 ps
CPU time 9.54 seconds
Started Jul 02 08:02:46 AM PDT 24
Finished Jul 02 08:03:12 AM PDT 24
Peak memory 212300 kb
Host smart-9f8154d7-4011-41ef-b968-3fe86aff26c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672075124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1672075124
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1431114631
Short name T320
Test name
Test status
Simulation time 17706571698 ps
CPU time 15.48 seconds
Started Jul 02 08:02:29 AM PDT 24
Finished Jul 02 08:03:01 AM PDT 24
Peak memory 211484 kb
Host smart-74e248d6-4ced-43f6-a39b-3682752a5ae5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1431114631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1431114631
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.816200210
Short name T181
Test name
Test status
Simulation time 763857331 ps
CPU time 10.25 seconds
Started Jul 02 08:02:26 AM PDT 24
Finished Jul 02 08:02:51 AM PDT 24
Peak memory 213828 kb
Host smart-3ab68f6f-7630-4ff1-8a2b-ae3d7c9e0f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816200210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.816200210
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3753555222
Short name T146
Test name
Test status
Simulation time 669415892 ps
CPU time 7.93 seconds
Started Jul 02 08:02:24 AM PDT 24
Finished Jul 02 08:02:48 AM PDT 24
Peak memory 211272 kb
Host smart-51b946b1-ec76-4e49-b99c-4288799e8d4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753555222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3753555222
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3843128063
Short name T322
Test name
Test status
Simulation time 2058789262 ps
CPU time 7.58 seconds
Started Jul 02 08:02:44 AM PDT 24
Finished Jul 02 08:03:08 AM PDT 24
Peak memory 211360 kb
Host smart-67cc5ac9-35ad-438d-a3d1-3bb28a1e0dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843128063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3843128063
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2224179642
Short name T26
Test name
Test status
Simulation time 362625395657 ps
CPU time 256.39 seconds
Started Jul 02 08:02:25 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 237888 kb
Host smart-1afdda98-4b76-4ccf-84fa-795810ef8eab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224179642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2224179642
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3990371308
Short name T31
Test name
Test status
Simulation time 1844591686 ps
CPU time 9.66 seconds
Started Jul 02 08:02:44 AM PDT 24
Finished Jul 02 08:03:11 AM PDT 24
Peak memory 211908 kb
Host smart-0266f9d0-ad78-4d17-aff6-638544fdd458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990371308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3990371308
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.838668663
Short name T42
Test name
Test status
Simulation time 823682413 ps
CPU time 10.3 seconds
Started Jul 02 08:02:25 AM PDT 24
Finished Jul 02 08:02:51 AM PDT 24
Peak memory 211412 kb
Host smart-7fe7b8ca-cf0c-4db7-9d9f-bcbc47f98e79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838668663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.838668663
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4093797275
Short name T349
Test name
Test status
Simulation time 2027739117 ps
CPU time 22.06 seconds
Started Jul 02 08:02:28 AM PDT 24
Finished Jul 02 08:03:06 AM PDT 24
Peak memory 212832 kb
Host smart-9078a129-ece9-4b8b-b1ec-5c7c402b7577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093797275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4093797275
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1965657433
Short name T198
Test name
Test status
Simulation time 7599285336 ps
CPU time 16.67 seconds
Started Jul 02 08:02:39 AM PDT 24
Finished Jul 02 08:03:12 AM PDT 24
Peak memory 212476 kb
Host smart-182f9220-c04a-4df5-9872-735647028466
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965657433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1965657433
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1429090897
Short name T139
Test name
Test status
Simulation time 1221660743 ps
CPU time 11.01 seconds
Started Jul 02 08:01:57 AM PDT 24
Finished Jul 02 08:02:23 AM PDT 24
Peak memory 211372 kb
Host smart-3262f3d8-f384-4aa9-a61e-03e74b13941e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429090897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1429090897
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.58677489
Short name T16
Test name
Test status
Simulation time 26566859292 ps
CPU time 113.11 seconds
Started Jul 02 08:02:01 AM PDT 24
Finished Jul 02 08:04:08 AM PDT 24
Peak memory 237924 kb
Host smart-5367eeb4-417f-4f4e-a43b-be2fbeb0d9a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58677489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_cor
rupt_sig_fatal_chk.58677489
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1769019575
Short name T144
Test name
Test status
Simulation time 721430231 ps
CPU time 9.41 seconds
Started Jul 02 08:01:56 AM PDT 24
Finished Jul 02 08:02:20 AM PDT 24
Peak memory 211896 kb
Host smart-c259da96-a231-418d-b949-60e292a2677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769019575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1769019575
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2728105308
Short name T165
Test name
Test status
Simulation time 3133148708 ps
CPU time 18.78 seconds
Started Jul 02 08:01:53 AM PDT 24
Finished Jul 02 08:02:27 AM PDT 24
Peak memory 213492 kb
Host smart-25acb50f-51d2-47b2-b580-0b8b13cc054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728105308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2728105308
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3071008573
Short name T162
Test name
Test status
Simulation time 25240085525 ps
CPU time 51.2 seconds
Started Jul 02 08:01:58 AM PDT 24
Finished Jul 02 08:03:04 AM PDT 24
Peak memory 214884 kb
Host smart-355edb7d-0e85-4397-8404-b4b17a48aa5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071008573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3071008573
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1631241248
Short name T159
Test name
Test status
Simulation time 2123958141 ps
CPU time 16.75 seconds
Started Jul 02 08:01:53 AM PDT 24
Finished Jul 02 08:02:26 AM PDT 24
Peak memory 211348 kb
Host smart-17b4e4f0-2a23-43c1-9998-656cd640e794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631241248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1631241248
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1149589856
Short name T175
Test name
Test status
Simulation time 34858470722 ps
CPU time 356.23 seconds
Started Jul 02 08:01:52 AM PDT 24
Finished Jul 02 08:08:04 AM PDT 24
Peak memory 237960 kb
Host smart-8f0c81ee-a211-4b06-a51b-7bb9bd1d66b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149589856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1149589856
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.341263581
Short name T143
Test name
Test status
Simulation time 12486481694 ps
CPU time 28.05 seconds
Started Jul 02 08:02:04 AM PDT 24
Finished Jul 02 08:02:47 AM PDT 24
Peak memory 211508 kb
Host smart-0856a63c-9a89-46cb-a6c8-01d39b9409bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341263581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.341263581
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1408215090
Short name T303
Test name
Test status
Simulation time 5463466926 ps
CPU time 13.43 seconds
Started Jul 02 08:02:00 AM PDT 24
Finished Jul 02 08:02:27 AM PDT 24
Peak memory 211492 kb
Host smart-8a81839b-eee5-4c6d-82bb-4738025d288f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408215090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1408215090
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1254862858
Short name T184
Test name
Test status
Simulation time 6476507459 ps
CPU time 31.35 seconds
Started Jul 02 08:02:05 AM PDT 24
Finished Jul 02 08:02:51 AM PDT 24
Peak memory 213852 kb
Host smart-f7541e2d-27c0-4133-b7c0-4bffd4e155f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254862858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1254862858
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.32197025
Short name T315
Test name
Test status
Simulation time 25637346703 ps
CPU time 64.25 seconds
Started Jul 02 08:01:49 AM PDT 24
Finished Jul 02 08:03:09 AM PDT 24
Peak memory 217960 kb
Host smart-37ce3d48-9e02-41e4-842d-91ac8b6fadaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32197025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.rom_ctrl_stress_all.32197025
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3435300378
Short name T81
Test name
Test status
Simulation time 8490789676 ps
CPU time 16.35 seconds
Started Jul 02 08:01:44 AM PDT 24
Finished Jul 02 08:02:17 AM PDT 24
Peak memory 211320 kb
Host smart-adece7d4-72f6-4407-ad59-23b8d9b88c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435300378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3435300378
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3301732703
Short name T294
Test name
Test status
Simulation time 41525672207 ps
CPU time 133.61 seconds
Started Jul 02 08:01:56 AM PDT 24
Finished Jul 02 08:04:24 AM PDT 24
Peak memory 224696 kb
Host smart-26ffdd25-f4f3-4494-a12b-d3dcfdcf07c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301732703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3301732703
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4030737330
Short name T279
Test name
Test status
Simulation time 693113845 ps
CPU time 9.33 seconds
Started Jul 02 08:01:55 AM PDT 24
Finished Jul 02 08:02:19 AM PDT 24
Peak memory 212088 kb
Host smart-ebd58f50-5415-4bc9-a539-04dd47e259c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030737330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4030737330
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3722103619
Short name T134
Test name
Test status
Simulation time 185422831 ps
CPU time 5.51 seconds
Started Jul 02 08:01:55 AM PDT 24
Finished Jul 02 08:02:16 AM PDT 24
Peak memory 211412 kb
Host smart-3eaa4fbd-ee71-4f06-90db-2ed561bc9063
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722103619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3722103619
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2828445196
Short name T302
Test name
Test status
Simulation time 3459701363 ps
CPU time 36.9 seconds
Started Jul 02 08:02:05 AM PDT 24
Finished Jul 02 08:02:57 AM PDT 24
Peak memory 213336 kb
Host smart-08a63c70-c18d-402f-be69-c008cba601ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828445196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2828445196
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1222595185
Short name T261
Test name
Test status
Simulation time 500673395 ps
CPU time 6.01 seconds
Started Jul 02 08:01:52 AM PDT 24
Finished Jul 02 08:02:14 AM PDT 24
Peak memory 211424 kb
Host smart-68ac8003-49c3-4909-9f67-98487aebd11d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222595185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1222595185
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1112939152
Short name T35
Test name
Test status
Simulation time 212668727832 ps
CPU time 5437.12 seconds
Started Jul 02 08:02:12 AM PDT 24
Finished Jul 02 09:33:04 AM PDT 24
Peak memory 236020 kb
Host smart-c5e73df2-7a34-4a12-b466-14bde542f80e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112939152 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1112939152
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.62591941
Short name T51
Test name
Test status
Simulation time 1719489062 ps
CPU time 14.61 seconds
Started Jul 02 08:01:43 AM PDT 24
Finished Jul 02 08:02:15 AM PDT 24
Peak memory 211312 kb
Host smart-c4c048bb-d624-4cc0-b612-8d58eec4fa7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62591941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.62591941
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3777770719
Short name T342
Test name
Test status
Simulation time 12019474601 ps
CPU time 230.9 seconds
Started Jul 02 08:02:06 AM PDT 24
Finished Jul 02 08:06:12 AM PDT 24
Peak memory 237864 kb
Host smart-11000898-e7ff-4377-a4ad-d7dd082a5ddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777770719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3777770719
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3342223992
Short name T211
Test name
Test status
Simulation time 176318294 ps
CPU time 9.33 seconds
Started Jul 02 08:02:10 AM PDT 24
Finished Jul 02 08:02:34 AM PDT 24
Peak memory 212900 kb
Host smart-93246cb7-983d-4047-83ff-50e3c094df64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342223992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3342223992
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2448645842
Short name T210
Test name
Test status
Simulation time 34754264608 ps
CPU time 15.35 seconds
Started Jul 02 08:02:01 AM PDT 24
Finished Jul 02 08:02:30 AM PDT 24
Peak memory 211380 kb
Host smart-fc28fcaf-483a-4ef3-b299-7603ae2e283d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2448645842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2448645842
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.263360953
Short name T111
Test name
Test status
Simulation time 21420218453 ps
CPU time 29.35 seconds
Started Jul 02 08:01:56 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 214204 kb
Host smart-077ec7d2-63d8-497b-8f47-81bf9391066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263360953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.263360953
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4040259688
Short name T231
Test name
Test status
Simulation time 2376526804 ps
CPU time 7.97 seconds
Started Jul 02 08:01:51 AM PDT 24
Finished Jul 02 08:02:15 AM PDT 24
Peak memory 211448 kb
Host smart-b6d6b0f2-0f48-4574-84eb-bc98f86ff1ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040259688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4040259688
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.36455548
Short name T186
Test name
Test status
Simulation time 3762429673 ps
CPU time 13.61 seconds
Started Jul 02 08:01:50 AM PDT 24
Finished Jul 02 08:02:20 AM PDT 24
Peak memory 211384 kb
Host smart-7db0f581-0cd1-43ad-b2f8-79dc7eed5382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36455548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.36455548
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2789362388
Short name T194
Test name
Test status
Simulation time 19060919490 ps
CPU time 110.99 seconds
Started Jul 02 08:01:52 AM PDT 24
Finished Jul 02 08:03:59 AM PDT 24
Peak memory 237800 kb
Host smart-6956884c-3d29-4ee8-adf8-efa421f46b3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789362388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2789362388
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1262319039
Short name T253
Test name
Test status
Simulation time 7881687559 ps
CPU time 21.57 seconds
Started Jul 02 08:02:15 AM PDT 24
Finished Jul 02 08:02:52 AM PDT 24
Peak memory 211748 kb
Host smart-2d54e8d2-0c5e-4bc2-83ef-dcfc3dd8a33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262319039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1262319039
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3054909883
Short name T365
Test name
Test status
Simulation time 517079009 ps
CPU time 5.6 seconds
Started Jul 02 08:02:00 AM PDT 24
Finished Jul 02 08:02:20 AM PDT 24
Peak memory 211340 kb
Host smart-6cd41dd2-ed9c-4982-9a89-977a50b59635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054909883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3054909883
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2617862911
Short name T273
Test name
Test status
Simulation time 319811358 ps
CPU time 10 seconds
Started Jul 02 08:02:03 AM PDT 24
Finished Jul 02 08:02:28 AM PDT 24
Peak memory 212896 kb
Host smart-ed48deee-3c7a-460f-9f42-d6e3d106ab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617862911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2617862911
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2161461648
Short name T354
Test name
Test status
Simulation time 11866565910 ps
CPU time 25.8 seconds
Started Jul 02 08:02:01 AM PDT 24
Finished Jul 02 08:02:41 AM PDT 24
Peak memory 215352 kb
Host smart-da659ffa-8879-419c-aaad-66fd38a91b17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161461648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2161461648
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.955391115
Short name T236
Test name
Test status
Simulation time 35561085970 ps
CPU time 1446.43 seconds
Started Jul 02 08:02:14 AM PDT 24
Finished Jul 02 08:26:36 AM PDT 24
Peak memory 233776 kb
Host smart-7f9497e9-0071-47d1-b71c-725a51e719dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955391115 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.955391115
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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