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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.67 100.00 98.28 97.30 98.37


Total test records in report: 461
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T308 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1979745036 Jul 03 04:35:04 PM PDT 24 Jul 03 04:37:23 PM PDT 24 36689814404 ps
T309 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3161146129 Jul 03 04:35:04 PM PDT 24 Jul 03 04:35:24 PM PDT 24 9197444156 ps
T310 /workspace/coverage/default/3.rom_ctrl_smoke.3669475056 Jul 03 04:34:58 PM PDT 24 Jul 03 04:35:15 PM PDT 24 3311201557 ps
T311 /workspace/coverage/default/31.rom_ctrl_smoke.398883711 Jul 03 04:35:47 PM PDT 24 Jul 03 04:36:31 PM PDT 24 4266353850 ps
T312 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2952398551 Jul 03 04:35:58 PM PDT 24 Jul 03 04:36:31 PM PDT 24 3788228142 ps
T313 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1893140351 Jul 03 04:36:21 PM PDT 24 Jul 03 04:36:35 PM PDT 24 1238945024 ps
T314 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4040334400 Jul 03 04:35:18 PM PDT 24 Jul 03 04:35:46 PM PDT 24 13922007744 ps
T315 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3181345621 Jul 03 04:36:15 PM PDT 24 Jul 03 04:36:29 PM PDT 24 4496225363 ps
T316 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1122342104 Jul 03 04:35:02 PM PDT 24 Jul 03 04:35:11 PM PDT 24 426044895 ps
T317 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.961708732 Jul 03 04:36:20 PM PDT 24 Jul 03 04:43:43 PM PDT 24 700867190409 ps
T318 /workspace/coverage/default/34.rom_ctrl_smoke.2462742446 Jul 03 04:35:52 PM PDT 24 Jul 03 04:36:21 PM PDT 24 7758694922 ps
T319 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3669975701 Jul 03 04:36:10 PM PDT 24 Jul 03 04:38:27 PM PDT 24 9509279916 ps
T320 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2151799580 Jul 03 04:36:23 PM PDT 24 Jul 03 04:36:36 PM PDT 24 1651963931 ps
T321 /workspace/coverage/default/24.rom_ctrl_stress_all.612005186 Jul 03 04:35:35 PM PDT 24 Jul 03 04:36:08 PM PDT 24 14540474521 ps
T50 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3577231677 Jul 03 04:34:54 PM PDT 24 Jul 03 05:51:47 PM PDT 24 32286263795 ps
T322 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.404596149 Jul 03 04:35:30 PM PDT 24 Jul 03 04:36:40 PM PDT 24 5242088353 ps
T323 /workspace/coverage/default/15.rom_ctrl_stress_all.1535425814 Jul 03 04:35:22 PM PDT 24 Jul 03 04:36:52 PM PDT 24 26855434790 ps
T106 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2554833186 Jul 03 04:35:54 PM PDT 24 Jul 03 05:24:37 PM PDT 24 75696682862 ps
T324 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3539227219 Jul 03 04:35:17 PM PDT 24 Jul 03 05:36:47 PM PDT 24 96540141877 ps
T91 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.618498909 Jul 03 04:35:28 PM PDT 24 Jul 03 05:16:14 PM PDT 24 69728310094 ps
T92 /workspace/coverage/default/44.rom_ctrl_alert_test.2571269092 Jul 03 04:36:21 PM PDT 24 Jul 03 04:36:29 PM PDT 24 576488070 ps
T93 /workspace/coverage/default/46.rom_ctrl_alert_test.3836295889 Jul 03 04:36:21 PM PDT 24 Jul 03 04:36:34 PM PDT 24 1246674648 ps
T94 /workspace/coverage/default/13.rom_ctrl_smoke.58866357 Jul 03 04:35:16 PM PDT 24 Jul 03 04:35:51 PM PDT 24 7381582026 ps
T95 /workspace/coverage/default/22.rom_ctrl_stress_all.1139211197 Jul 03 04:35:31 PM PDT 24 Jul 03 04:36:32 PM PDT 24 13208138230 ps
T96 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3316412376 Jul 03 04:35:12 PM PDT 24 Jul 03 04:38:41 PM PDT 24 48807022805 ps
T97 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1894982028 Jul 03 04:35:20 PM PDT 24 Jul 03 04:37:20 PM PDT 24 15626798804 ps
T98 /workspace/coverage/default/20.rom_ctrl_smoke.39961024 Jul 03 04:35:31 PM PDT 24 Jul 03 04:35:51 PM PDT 24 5392123495 ps
T99 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2018440212 Jul 03 04:35:20 PM PDT 24 Jul 03 04:41:04 PM PDT 24 138918201588 ps
T100 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1775086125 Jul 03 04:35:21 PM PDT 24 Jul 03 04:40:01 PM PDT 24 27268298731 ps
T325 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4092084880 Jul 03 04:36:18 PM PDT 24 Jul 03 04:38:10 PM PDT 24 9454999644 ps
T326 /workspace/coverage/default/28.rom_ctrl_alert_test.3012828690 Jul 03 04:35:45 PM PDT 24 Jul 03 04:35:57 PM PDT 24 2395670468 ps
T327 /workspace/coverage/default/25.rom_ctrl_smoke.2537352891 Jul 03 04:35:36 PM PDT 24 Jul 03 04:36:01 PM PDT 24 15970325391 ps
T328 /workspace/coverage/default/35.rom_ctrl_alert_test.41534767 Jul 03 04:35:56 PM PDT 24 Jul 03 04:36:01 PM PDT 24 299006733 ps
T329 /workspace/coverage/default/37.rom_ctrl_stress_all.1822617781 Jul 03 04:35:55 PM PDT 24 Jul 03 04:36:23 PM PDT 24 482172519 ps
T330 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3004175113 Jul 03 04:36:02 PM PDT 24 Jul 03 04:36:20 PM PDT 24 11496306936 ps
T331 /workspace/coverage/default/18.rom_ctrl_alert_test.695779493 Jul 03 04:35:28 PM PDT 24 Jul 03 04:35:42 PM PDT 24 6716865023 ps
T332 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3535353869 Jul 03 04:35:39 PM PDT 24 Jul 03 04:35:51 PM PDT 24 1231084365 ps
T333 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1649252877 Jul 03 04:36:21 PM PDT 24 Jul 03 04:36:35 PM PDT 24 1455342444 ps
T334 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4124762192 Jul 03 04:36:00 PM PDT 24 Jul 03 04:41:58 PM PDT 24 157446010686 ps
T335 /workspace/coverage/default/10.rom_ctrl_stress_all.4127499529 Jul 03 04:35:10 PM PDT 24 Jul 03 04:35:47 PM PDT 24 3547960380 ps
T336 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.205625689 Jul 03 04:35:12 PM PDT 24 Jul 03 04:35:18 PM PDT 24 1164049150 ps
T337 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3466323603 Jul 03 04:36:08 PM PDT 24 Jul 03 04:36:14 PM PDT 24 96828556 ps
T338 /workspace/coverage/default/25.rom_ctrl_stress_all.4083979633 Jul 03 04:35:40 PM PDT 24 Jul 03 04:36:59 PM PDT 24 50465450375 ps
T27 /workspace/coverage/default/1.rom_ctrl_sec_cm.2599716487 Jul 03 04:34:54 PM PDT 24 Jul 03 04:36:44 PM PDT 24 4264482494 ps
T339 /workspace/coverage/default/8.rom_ctrl_smoke.3888764876 Jul 03 04:35:07 PM PDT 24 Jul 03 04:35:23 PM PDT 24 3013182709 ps
T340 /workspace/coverage/default/6.rom_ctrl_alert_test.1577931921 Jul 03 04:35:03 PM PDT 24 Jul 03 04:35:14 PM PDT 24 1050211055 ps
T341 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2477760829 Jul 03 04:36:03 PM PDT 24 Jul 03 04:36:10 PM PDT 24 566952913 ps
T342 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3800454473 Jul 03 04:36:11 PM PDT 24 Jul 03 04:36:43 PM PDT 24 7979921021 ps
T343 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.641782490 Jul 03 04:35:43 PM PDT 24 Jul 03 04:42:45 PM PDT 24 278524752926 ps
T344 /workspace/coverage/default/41.rom_ctrl_alert_test.3131673522 Jul 03 04:36:05 PM PDT 24 Jul 03 04:36:15 PM PDT 24 3269316052 ps
T345 /workspace/coverage/default/46.rom_ctrl_stress_all.3607910252 Jul 03 04:36:16 PM PDT 24 Jul 03 04:37:28 PM PDT 24 13585334112 ps
T346 /workspace/coverage/default/30.rom_ctrl_smoke.1925145601 Jul 03 04:35:47 PM PDT 24 Jul 03 04:35:59 PM PDT 24 1096356338 ps
T347 /workspace/coverage/default/21.rom_ctrl_smoke.4115787611 Jul 03 04:35:31 PM PDT 24 Jul 03 04:36:00 PM PDT 24 14281326028 ps
T348 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1902150157 Jul 03 04:35:36 PM PDT 24 Jul 03 04:36:12 PM PDT 24 17427638749 ps
T349 /workspace/coverage/default/9.rom_ctrl_smoke.3449990620 Jul 03 04:35:16 PM PDT 24 Jul 03 04:35:55 PM PDT 24 44594410845 ps
T350 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2528657501 Jul 03 04:36:25 PM PDT 24 Jul 03 04:36:37 PM PDT 24 720908872 ps
T351 /workspace/coverage/default/48.rom_ctrl_alert_test.3082757424 Jul 03 04:36:20 PM PDT 24 Jul 03 04:36:35 PM PDT 24 3444267808 ps
T352 /workspace/coverage/default/35.rom_ctrl_smoke.3594837446 Jul 03 04:35:55 PM PDT 24 Jul 03 04:36:06 PM PDT 24 188010066 ps
T353 /workspace/coverage/default/27.rom_ctrl_alert_test.2734771813 Jul 03 04:35:43 PM PDT 24 Jul 03 04:35:47 PM PDT 24 128581946 ps
T354 /workspace/coverage/default/5.rom_ctrl_alert_test.3611588116 Jul 03 04:35:05 PM PDT 24 Jul 03 04:35:15 PM PDT 24 3794880282 ps
T355 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3102220842 Jul 03 04:36:09 PM PDT 24 Jul 03 04:36:24 PM PDT 24 6357992344 ps
T356 /workspace/coverage/default/24.rom_ctrl_smoke.3271923997 Jul 03 04:35:36 PM PDT 24 Jul 03 04:35:58 PM PDT 24 7579968529 ps
T357 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1035688302 Jul 03 04:36:00 PM PDT 24 Jul 03 04:36:10 PM PDT 24 2945404988 ps
T358 /workspace/coverage/default/7.rom_ctrl_alert_test.1741049193 Jul 03 04:35:06 PM PDT 24 Jul 03 04:35:12 PM PDT 24 519861364 ps
T359 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3829188576 Jul 03 04:35:22 PM PDT 24 Jul 03 04:35:54 PM PDT 24 17255381877 ps
T360 /workspace/coverage/default/2.rom_ctrl_alert_test.89892552 Jul 03 04:34:58 PM PDT 24 Jul 03 04:35:09 PM PDT 24 986684466 ps
T54 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.591411928 Jul 03 04:34:11 PM PDT 24 Jul 03 04:34:17 PM PDT 24 345651295 ps
T51 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3405656927 Jul 03 04:34:38 PM PDT 24 Jul 03 04:35:56 PM PDT 24 2188878478 ps
T55 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1654527318 Jul 03 04:34:37 PM PDT 24 Jul 03 04:34:42 PM PDT 24 86709988 ps
T361 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1379436183 Jul 03 04:34:39 PM PDT 24 Jul 03 04:34:54 PM PDT 24 1593649889 ps
T362 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2591790925 Jul 03 04:34:46 PM PDT 24 Jul 03 04:34:56 PM PDT 24 2955113123 ps
T88 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3663501129 Jul 03 04:34:38 PM PDT 24 Jul 03 04:34:43 PM PDT 24 90240582 ps
T101 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.7006475 Jul 03 04:34:45 PM PDT 24 Jul 03 04:35:13 PM PDT 24 14903673041 ps
T52 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1944097356 Jul 03 04:34:43 PM PDT 24 Jul 03 04:35:58 PM PDT 24 548421352 ps
T363 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2216821042 Jul 03 04:34:29 PM PDT 24 Jul 03 04:34:37 PM PDT 24 356015382 ps
T364 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.727091052 Jul 03 04:34:39 PM PDT 24 Jul 03 04:34:51 PM PDT 24 450460979 ps
T89 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2353229829 Jul 03 04:34:46 PM PDT 24 Jul 03 04:34:54 PM PDT 24 372338090 ps
T365 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2718730692 Jul 03 04:34:33 PM PDT 24 Jul 03 04:34:40 PM PDT 24 346262371 ps
T53 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1127899177 Jul 03 04:34:10 PM PDT 24 Jul 03 04:35:22 PM PDT 24 1914469035 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2244979603 Jul 03 04:34:14 PM PDT 24 Jul 03 04:34:19 PM PDT 24 465389313 ps
T109 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.292156882 Jul 03 04:34:23 PM PDT 24 Jul 03 04:35:33 PM PDT 24 939756924 ps
T102 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.121032701 Jul 03 04:34:52 PM PDT 24 Jul 03 04:35:06 PM PDT 24 1682481220 ps
T61 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.993754980 Jul 03 04:34:35 PM PDT 24 Jul 03 04:35:03 PM PDT 24 2452785799 ps
T367 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3573862312 Jul 03 04:34:35 PM PDT 24 Jul 03 04:34:49 PM PDT 24 1517300083 ps
T368 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2224285149 Jul 03 04:34:46 PM PDT 24 Jul 03 04:34:57 PM PDT 24 2283708118 ps
T62 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.217301349 Jul 03 04:34:53 PM PDT 24 Jul 03 04:35:06 PM PDT 24 1516201041 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2529627970 Jul 03 04:34:11 PM PDT 24 Jul 03 04:34:20 PM PDT 24 608368755 ps
T103 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1747037031 Jul 03 04:34:30 PM PDT 24 Jul 03 04:34:44 PM PDT 24 3427417268 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.780376233 Jul 03 04:34:30 PM PDT 24 Jul 03 04:34:37 PM PDT 24 486627398 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3568907118 Jul 03 04:34:22 PM PDT 24 Jul 03 04:34:38 PM PDT 24 7009135106 ps
T372 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1576284133 Jul 03 04:34:40 PM PDT 24 Jul 03 04:34:45 PM PDT 24 90975549 ps
T107 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1976436725 Jul 03 04:34:29 PM PDT 24 Jul 03 04:34:39 PM PDT 24 528327732 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2640621765 Jul 03 04:34:31 PM PDT 24 Jul 03 04:34:56 PM PDT 24 2046403369 ps
T112 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2979514309 Jul 03 04:34:35 PM PDT 24 Jul 03 04:35:54 PM PDT 24 1751869732 ps
T63 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3222820853 Jul 03 04:34:26 PM PDT 24 Jul 03 04:34:35 PM PDT 24 1393685344 ps
T374 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1649943892 Jul 03 04:34:38 PM PDT 24 Jul 03 04:34:55 PM PDT 24 10003842271 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2347284614 Jul 03 04:34:12 PM PDT 24 Jul 03 04:34:22 PM PDT 24 2062644534 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2134345483 Jul 03 04:34:29 PM PDT 24 Jul 03 04:34:47 PM PDT 24 15089395972 ps
T377 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3934976865 Jul 03 04:34:26 PM PDT 24 Jul 03 04:34:42 PM PDT 24 2686627014 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.415967669 Jul 03 04:34:22 PM PDT 24 Jul 03 04:34:35 PM PDT 24 1429696004 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3866980345 Jul 03 04:34:20 PM PDT 24 Jul 03 04:34:24 PM PDT 24 637115744 ps
T110 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.411763088 Jul 03 04:34:41 PM PDT 24 Jul 03 04:35:18 PM PDT 24 574039607 ps
T379 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1548929172 Jul 03 04:34:12 PM PDT 24 Jul 03 04:34:31 PM PDT 24 755591411 ps
T380 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2959415453 Jul 03 04:34:49 PM PDT 24 Jul 03 04:35:11 PM PDT 24 16379432330 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.742778432 Jul 03 04:34:26 PM PDT 24 Jul 03 04:34:43 PM PDT 24 2038134597 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1728528023 Jul 03 04:34:33 PM PDT 24 Jul 03 04:35:21 PM PDT 24 2197572731 ps
T65 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1230502009 Jul 03 04:34:40 PM PDT 24 Jul 03 04:34:56 PM PDT 24 20570325370 ps
T382 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.929803425 Jul 03 04:34:26 PM PDT 24 Jul 03 04:35:05 PM PDT 24 2503514228 ps
T66 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.805918206 Jul 03 04:34:47 PM PDT 24 Jul 03 04:34:52 PM PDT 24 168226906 ps
T67 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1876148350 Jul 03 04:34:26 PM PDT 24 Jul 03 04:34:54 PM PDT 24 550190958 ps
T90 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1014276673 Jul 03 04:34:47 PM PDT 24 Jul 03 04:34:51 PM PDT 24 115006651 ps
T68 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3756679459 Jul 03 04:34:37 PM PDT 24 Jul 03 04:35:25 PM PDT 24 20466498688 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1422890801 Jul 03 04:34:26 PM PDT 24 Jul 03 04:34:35 PM PDT 24 1133972013 ps
T69 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2436686050 Jul 03 04:34:29 PM PDT 24 Jul 03 04:35:57 PM PDT 24 18478246056 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.437719523 Jul 03 04:34:26 PM PDT 24 Jul 03 04:34:34 PM PDT 24 924706615 ps
T385 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1112031152 Jul 03 04:34:21 PM PDT 24 Jul 03 04:34:26 PM PDT 24 175638691 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4100674104 Jul 03 04:34:51 PM PDT 24 Jul 03 04:36:01 PM PDT 24 2501619970 ps
T387 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1951266251 Jul 03 04:34:33 PM PDT 24 Jul 03 04:34:48 PM PDT 24 9223608193 ps
T388 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3439951693 Jul 03 04:34:40 PM PDT 24 Jul 03 04:34:58 PM PDT 24 2408460617 ps
T70 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1693466249 Jul 03 04:34:36 PM PDT 24 Jul 03 04:34:51 PM PDT 24 1581498351 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2205001457 Jul 03 04:34:18 PM PDT 24 Jul 03 04:34:33 PM PDT 24 3584223710 ps
T390 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2942541848 Jul 03 04:34:37 PM PDT 24 Jul 03 04:34:44 PM PDT 24 346730843 ps
T391 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3898730434 Jul 03 04:34:39 PM PDT 24 Jul 03 04:34:51 PM PDT 24 1213848264 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.574624075 Jul 03 04:34:19 PM PDT 24 Jul 03 04:34:27 PM PDT 24 89082280 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1550262223 Jul 03 04:34:38 PM PDT 24 Jul 03 04:34:54 PM PDT 24 1571134922 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1057356791 Jul 03 04:34:21 PM PDT 24 Jul 03 04:34:27 PM PDT 24 249434901 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4216743178 Jul 03 04:34:14 PM PDT 24 Jul 03 04:34:18 PM PDT 24 640197212 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2223638844 Jul 03 04:34:30 PM PDT 24 Jul 03 04:34:38 PM PDT 24 12294154847 ps
T108 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4275227256 Jul 03 04:34:24 PM PDT 24 Jul 03 04:35:47 PM PDT 24 36480266977 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2648249806 Jul 03 04:34:25 PM PDT 24 Jul 03 04:34:30 PM PDT 24 88210472 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4036144446 Jul 03 04:34:38 PM PDT 24 Jul 03 04:34:43 PM PDT 24 106066599 ps
T398 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1695151311 Jul 03 04:34:41 PM PDT 24 Jul 03 04:35:50 PM PDT 24 2203072963 ps
T399 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4082013259 Jul 03 04:34:34 PM PDT 24 Jul 03 04:35:50 PM PDT 24 1832926599 ps
T77 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3720771449 Jul 03 04:34:21 PM PDT 24 Jul 03 04:35:00 PM PDT 24 7211207191 ps
T78 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2629029921 Jul 03 04:34:37 PM PDT 24 Jul 03 04:35:13 PM PDT 24 35101701286 ps
T79 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1293805870 Jul 03 04:34:40 PM PDT 24 Jul 03 04:35:08 PM PDT 24 2364633498 ps
T400 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.247778101 Jul 03 04:34:28 PM PDT 24 Jul 03 04:34:42 PM PDT 24 6967680529 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.289462740 Jul 03 04:34:26 PM PDT 24 Jul 03 04:34:34 PM PDT 24 498151281 ps
T402 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.194808099 Jul 03 04:34:43 PM PDT 24 Jul 03 04:34:57 PM PDT 24 1518588346 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.949247396 Jul 03 04:34:20 PM PDT 24 Jul 03 04:34:24 PM PDT 24 416190709 ps
T117 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.184445650 Jul 03 04:34:47 PM PDT 24 Jul 03 04:35:24 PM PDT 24 291656813 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3862245885 Jul 03 04:34:12 PM PDT 24 Jul 03 04:34:28 PM PDT 24 7491309812 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.816604154 Jul 03 04:34:17 PM PDT 24 Jul 03 04:35:11 PM PDT 24 8761047083 ps
T405 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.715939522 Jul 03 04:34:32 PM PDT 24 Jul 03 04:34:46 PM PDT 24 7168991271 ps
T406 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4067830924 Jul 03 04:34:47 PM PDT 24 Jul 03 04:35:03 PM PDT 24 13387914031 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3197580636 Jul 03 04:34:31 PM PDT 24 Jul 03 04:34:41 PM PDT 24 11376620457 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4264704310 Jul 03 04:34:45 PM PDT 24 Jul 03 04:35:04 PM PDT 24 3716746505 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1052377672 Jul 03 04:34:10 PM PDT 24 Jul 03 04:34:19 PM PDT 24 1309739885 ps
T85 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1720504766 Jul 03 04:34:37 PM PDT 24 Jul 03 04:35:52 PM PDT 24 31516715706 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2069740675 Jul 03 04:34:21 PM PDT 24 Jul 03 04:34:35 PM PDT 24 1692218172 ps
T411 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4011133784 Jul 03 04:34:30 PM PDT 24 Jul 03 04:34:49 PM PDT 24 5931224720 ps
T412 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.288803747 Jul 03 04:34:25 PM PDT 24 Jul 03 04:34:30 PM PDT 24 99041776 ps
T413 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3457703244 Jul 03 04:34:37 PM PDT 24 Jul 03 04:34:48 PM PDT 24 3036460519 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3349716892 Jul 03 04:34:27 PM PDT 24 Jul 03 04:35:40 PM PDT 24 3962456732 ps
T113 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2161345026 Jul 03 04:34:42 PM PDT 24 Jul 03 04:35:52 PM PDT 24 487166173 ps
T415 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2268321806 Jul 03 04:34:11 PM PDT 24 Jul 03 04:34:23 PM PDT 24 411741088 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2635179445 Jul 03 04:34:22 PM PDT 24 Jul 03 04:34:27 PM PDT 24 171554316 ps
T114 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2963666105 Jul 03 04:34:47 PM PDT 24 Jul 03 04:35:29 PM PDT 24 9854545716 ps
T416 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2026548816 Jul 03 04:34:28 PM PDT 24 Jul 03 04:34:36 PM PDT 24 397699748 ps
T115 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1200048515 Jul 03 04:34:12 PM PDT 24 Jul 03 04:35:31 PM PDT 24 4609074913 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1142543537 Jul 03 04:34:18 PM PDT 24 Jul 03 04:34:33 PM PDT 24 8796616247 ps
T417 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1354770691 Jul 03 04:34:52 PM PDT 24 Jul 03 04:34:56 PM PDT 24 1182585183 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.23714292 Jul 03 04:34:31 PM PDT 24 Jul 03 04:34:46 PM PDT 24 1906647562 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1050442943 Jul 03 04:34:44 PM PDT 24 Jul 03 04:35:03 PM PDT 24 3787994270 ps
T420 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2918540262 Jul 03 04:34:12 PM PDT 24 Jul 03 04:34:28 PM PDT 24 3657920021 ps
T116 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1481208215 Jul 03 04:34:31 PM PDT 24 Jul 03 04:35:50 PM PDT 24 2050159074 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1671765403 Jul 03 04:34:31 PM PDT 24 Jul 03 04:34:40 PM PDT 24 442448785 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2850003717 Jul 03 04:34:12 PM PDT 24 Jul 03 04:34:30 PM PDT 24 25043638011 ps
T423 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1171306482 Jul 03 04:34:40 PM PDT 24 Jul 03 04:34:56 PM PDT 24 6969051936 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3710893107 Jul 03 04:34:19 PM PDT 24 Jul 03 04:34:32 PM PDT 24 3101568085 ps
T82 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.899162294 Jul 03 04:34:42 PM PDT 24 Jul 03 04:35:34 PM PDT 24 5546374773 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1823244298 Jul 03 04:34:29 PM PDT 24 Jul 03 04:34:40 PM PDT 24 1113917494 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1418523700 Jul 03 04:34:50 PM PDT 24 Jul 03 04:35:03 PM PDT 24 2620643963 ps
T427 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1888309342 Jul 03 04:34:42 PM PDT 24 Jul 03 04:35:53 PM PDT 24 14104851146 ps
T428 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1358220803 Jul 03 04:34:17 PM PDT 24 Jul 03 04:35:46 PM PDT 24 11379312724 ps
T429 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.93933281 Jul 03 04:34:44 PM PDT 24 Jul 03 04:34:56 PM PDT 24 1196455441 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2017338973 Jul 03 04:34:28 PM PDT 24 Jul 03 04:34:38 PM PDT 24 2113038803 ps
T431 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2911657044 Jul 03 04:34:30 PM PDT 24 Jul 03 04:34:43 PM PDT 24 6312435392 ps
T432 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3412941234 Jul 03 04:34:36 PM PDT 24 Jul 03 04:35:45 PM PDT 24 216616583 ps
T433 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.256518313 Jul 03 04:34:45 PM PDT 24 Jul 03 04:34:57 PM PDT 24 654950131 ps
T434 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1400401111 Jul 03 04:34:34 PM PDT 24 Jul 03 04:34:48 PM PDT 24 1427617889 ps
T435 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1328024766 Jul 03 04:34:25 PM PDT 24 Jul 03 04:34:42 PM PDT 24 24732806048 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2080202102 Jul 03 04:34:22 PM PDT 24 Jul 03 04:34:27 PM PDT 24 363721175 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2365648226 Jul 03 04:34:42 PM PDT 24 Jul 03 04:34:49 PM PDT 24 329886101 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2976570771 Jul 03 04:34:21 PM PDT 24 Jul 03 04:34:57 PM PDT 24 152943325 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1880431422 Jul 03 04:34:12 PM PDT 24 Jul 03 04:34:22 PM PDT 24 248689712 ps
T87 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2381768176 Jul 03 04:34:52 PM PDT 24 Jul 03 04:36:13 PM PDT 24 61786748505 ps
T440 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.286980772 Jul 03 04:34:30 PM PDT 24 Jul 03 04:35:50 PM PDT 24 3940248927 ps
T441 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2263852047 Jul 03 04:34:35 PM PDT 24 Jul 03 04:34:44 PM PDT 24 914962022 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3936161552 Jul 03 04:34:19 PM PDT 24 Jul 03 04:34:25 PM PDT 24 858698130 ps
T443 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3584203948 Jul 03 04:34:31 PM PDT 24 Jul 03 04:34:41 PM PDT 24 4386399713 ps
T444 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3834450179 Jul 03 04:34:30 PM PDT 24 Jul 03 04:34:43 PM PDT 24 3602839750 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2086734169 Jul 03 04:34:23 PM PDT 24 Jul 03 04:34:39 PM PDT 24 4024145033 ps
T446 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3839949110 Jul 03 04:34:46 PM PDT 24 Jul 03 04:35:02 PM PDT 24 1730889789 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2009393690 Jul 03 04:34:42 PM PDT 24 Jul 03 04:34:53 PM PDT 24 11762823079 ps
T448 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3247247076 Jul 03 04:34:46 PM PDT 24 Jul 03 04:35:04 PM PDT 24 2238655123 ps
T449 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2278928608 Jul 03 04:34:40 PM PDT 24 Jul 03 04:34:57 PM PDT 24 2195560928 ps
T450 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2807056388 Jul 03 04:34:45 PM PDT 24 Jul 03 04:34:59 PM PDT 24 3228652605 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1351914806 Jul 03 04:34:29 PM PDT 24 Jul 03 04:34:40 PM PDT 24 943210469 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2217961067 Jul 03 04:34:23 PM PDT 24 Jul 03 04:34:28 PM PDT 24 333778376 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.285136824 Jul 03 04:34:13 PM PDT 24 Jul 03 04:34:18 PM PDT 24 175083206 ps
T454 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3018248183 Jul 03 04:34:46 PM PDT 24 Jul 03 04:34:51 PM PDT 24 91850241 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2430214741 Jul 03 04:34:21 PM PDT 24 Jul 03 04:34:27 PM PDT 24 225831396 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2128942049 Jul 03 04:34:28 PM PDT 24 Jul 03 04:34:49 PM PDT 24 1871096443 ps
T457 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.181533477 Jul 03 04:34:44 PM PDT 24 Jul 03 04:34:51 PM PDT 24 355760348 ps
T458 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2683387618 Jul 03 04:34:50 PM PDT 24 Jul 03 04:35:04 PM PDT 24 3079456540 ps
T459 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.847985881 Jul 03 04:34:51 PM PDT 24 Jul 03 04:35:00 PM PDT 24 1604682677 ps
T460 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.459174888 Jul 03 04:34:39 PM PDT 24 Jul 03 04:34:51 PM PDT 24 2010660066 ps
T83 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1616516229 Jul 03 04:34:32 PM PDT 24 Jul 03 04:34:42 PM PDT 24 1871575658 ps
T84 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3110075528 Jul 03 04:34:46 PM PDT 24 Jul 03 04:36:08 PM PDT 24 18274360959 ps
T461 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2524371705 Jul 03 04:34:32 PM PDT 24 Jul 03 04:34:44 PM PDT 24 1298556393 ps

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1718527366
Short name T10
Test name
Test status
Simulation time 87286237989 ps
CPU time 232.03 seconds
Started Jul 03 04:35:58 PM PDT 24
Finished Jul 03 04:39:50 PM PDT 24
Peak memory 215144 kb
Host smart-5421cef9-53f0-46ee-a80d-20d0f3455dc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718527366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1718527366
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1536382605
Short name T12
Test name
Test status
Simulation time 44104637447 ps
CPU time 863.63 seconds
Started Jul 03 04:35:02 PM PDT 24
Finished Jul 03 04:49:26 PM PDT 24
Peak memory 235812 kb
Host smart-c7168a0d-36fa-4e8f-bc5e-71130d0bbca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536382605 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1536382605
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1127899177
Short name T53
Test name
Test status
Simulation time 1914469035 ps
CPU time 72.07 seconds
Started Jul 03 04:34:10 PM PDT 24
Finished Jul 03 04:35:22 PM PDT 24
Peak memory 212284 kb
Host smart-0f0f22de-38c2-44c4-abeb-d5626d869900
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127899177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1127899177
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2112599814
Short name T8
Test name
Test status
Simulation time 15212923678 ps
CPU time 189.01 seconds
Started Jul 03 04:35:15 PM PDT 24
Finished Jul 03 04:38:24 PM PDT 24
Peak memory 228616 kb
Host smart-370c6391-13f5-4c41-8268-7b24c5151447
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112599814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2112599814
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.488911845
Short name T213
Test name
Test status
Simulation time 1662841572 ps
CPU time 115.55 seconds
Started Jul 03 04:35:22 PM PDT 24
Finished Jul 03 04:37:18 PM PDT 24
Peak memory 236996 kb
Host smart-e1a441e0-d06b-418b-ac6e-c0dafd39cdb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488911845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.488911845
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2296302149
Short name T5
Test name
Test status
Simulation time 35089354025 ps
CPU time 30.5 seconds
Started Jul 03 04:35:18 PM PDT 24
Finished Jul 03 04:35:49 PM PDT 24
Peak memory 213864 kb
Host smart-16a3b846-1403-4319-8731-15812302002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296302149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2296302149
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.315974081
Short name T18
Test name
Test status
Simulation time 4432721040 ps
CPU time 109.35 seconds
Started Jul 03 04:34:58 PM PDT 24
Finished Jul 03 04:36:48 PM PDT 24
Peak memory 238268 kb
Host smart-bf6f5a54-7c33-4bb2-81df-948dc9a1f81e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315974081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.315974081
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.993754980
Short name T61
Test name
Test status
Simulation time 2452785799 ps
CPU time 26.83 seconds
Started Jul 03 04:34:35 PM PDT 24
Finished Jul 03 04:35:03 PM PDT 24
Peak memory 210780 kb
Host smart-d36c12e7-3988-4aa3-8876-346bf7bb9a7b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993754980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.993754980
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2979514309
Short name T112
Test name
Test status
Simulation time 1751869732 ps
CPU time 78.24 seconds
Started Jul 03 04:34:35 PM PDT 24
Finished Jul 03 04:35:54 PM PDT 24
Peak memory 212072 kb
Host smart-2bf13c3a-5551-4b0d-8855-8555d440ee04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979514309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2979514309
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2692567391
Short name T21
Test name
Test status
Simulation time 463016333 ps
CPU time 4.3 seconds
Started Jul 03 04:35:15 PM PDT 24
Finished Jul 03 04:35:20 PM PDT 24
Peak memory 211304 kb
Host smart-e8cc11ca-d84b-497a-b35d-98ddfed4d7f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692567391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2692567391
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2168946252
Short name T24
Test name
Test status
Simulation time 1812071172 ps
CPU time 16.3 seconds
Started Jul 03 04:34:50 PM PDT 24
Finished Jul 03 04:35:07 PM PDT 24
Peak memory 211800 kb
Host smart-1a13e41c-db21-4007-9e24-7a311063cc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168946252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2168946252
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4177830788
Short name T243
Test name
Test status
Simulation time 16005288459 ps
CPU time 32.26 seconds
Started Jul 03 04:35:20 PM PDT 24
Finished Jul 03 04:35:53 PM PDT 24
Peak memory 212176 kb
Host smart-8f2b4459-50a2-4c1d-b928-6dfb4c94af1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177830788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4177830788
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1200048515
Short name T115
Test name
Test status
Simulation time 4609074913 ps
CPU time 78.09 seconds
Started Jul 03 04:34:12 PM PDT 24
Finished Jul 03 04:35:31 PM PDT 24
Peak memory 212396 kb
Host smart-32545408-adff-495b-9a1c-30b9ce842590
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200048515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1200048515
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1293805870
Short name T79
Test name
Test status
Simulation time 2364633498 ps
CPU time 28.01 seconds
Started Jul 03 04:34:40 PM PDT 24
Finished Jul 03 04:35:08 PM PDT 24
Peak memory 210776 kb
Host smart-6fbdc19b-ce38-42c1-9351-9d757eb4d2aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293805870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1293805870
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3412941234
Short name T432
Test name
Test status
Simulation time 216616583 ps
CPU time 67.88 seconds
Started Jul 03 04:34:36 PM PDT 24
Finished Jul 03 04:35:45 PM PDT 24
Peak memory 218932 kb
Host smart-b85413a6-416d-43fb-ae88-a9fb33a13651
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412941234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3412941234
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.591411928
Short name T54
Test name
Test status
Simulation time 345651295 ps
CPU time 5.42 seconds
Started Jul 03 04:34:11 PM PDT 24
Finished Jul 03 04:34:17 PM PDT 24
Peak memory 210776 kb
Host smart-0b7874d8-a540-462b-8be3-8bf6b73bc943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591411928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.591411928
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.703411592
Short name T13
Test name
Test status
Simulation time 107823169065 ps
CPU time 369.05 seconds
Started Jul 03 04:35:15 PM PDT 24
Finished Jul 03 04:41:24 PM PDT 24
Peak memory 235760 kb
Host smart-f4b267ac-6fed-40be-8a97-5856a56d41b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703411592 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.703411592
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3862245885
Short name T404
Test name
Test status
Simulation time 7491309812 ps
CPU time 15.58 seconds
Started Jul 03 04:34:12 PM PDT 24
Finished Jul 03 04:34:28 PM PDT 24
Peak memory 218744 kb
Host smart-09eb0ff3-90c0-4743-999c-94f641f6da65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862245885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3862245885
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.285136824
Short name T453
Test name
Test status
Simulation time 175083206 ps
CPU time 4.45 seconds
Started Jul 03 04:34:13 PM PDT 24
Finished Jul 03 04:34:18 PM PDT 24
Peak memory 217072 kb
Host smart-f846c636-22ca-48b8-974b-d6f39b6907e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285136824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.285136824
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2850003717
Short name T422
Test name
Test status
Simulation time 25043638011 ps
CPU time 18.12 seconds
Started Jul 03 04:34:12 PM PDT 24
Finished Jul 03 04:34:30 PM PDT 24
Peak memory 210560 kb
Host smart-b370447c-8486-4f71-be23-cbebffcaaf57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850003717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2850003717
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2244979603
Short name T366
Test name
Test status
Simulation time 465389313 ps
CPU time 5.32 seconds
Started Jul 03 04:34:14 PM PDT 24
Finished Jul 03 04:34:19 PM PDT 24
Peak memory 218948 kb
Host smart-c4c1ca3d-5a77-4637-945d-c4460b707b33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244979603 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2244979603
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1052377672
Short name T409
Test name
Test status
Simulation time 1309739885 ps
CPU time 8.29 seconds
Started Jul 03 04:34:10 PM PDT 24
Finished Jul 03 04:34:19 PM PDT 24
Peak memory 210628 kb
Host smart-4028cc24-462c-4f80-9989-9193d0731c72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052377672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1052377672
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2918540262
Short name T420
Test name
Test status
Simulation time 3657920021 ps
CPU time 15.24 seconds
Started Jul 03 04:34:12 PM PDT 24
Finished Jul 03 04:34:28 PM PDT 24
Peak memory 210624 kb
Host smart-ecde832f-5db3-486f-b639-f3ece4e05ca9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918540262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2918540262
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2529627970
Short name T369
Test name
Test status
Simulation time 608368755 ps
CPU time 7.87 seconds
Started Jul 03 04:34:11 PM PDT 24
Finished Jul 03 04:34:20 PM PDT 24
Peak memory 210508 kb
Host smart-5657dd8c-9230-4dd2-9e9e-47998dd1e757
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529627970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2529627970
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1358220803
Short name T428
Test name
Test status
Simulation time 11379312724 ps
CPU time 88.48 seconds
Started Jul 03 04:34:17 PM PDT 24
Finished Jul 03 04:35:46 PM PDT 24
Peak memory 217812 kb
Host smart-514e6add-f3b7-4dfc-8eca-b5f5062da5fb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358220803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1358220803
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2268321806
Short name T415
Test name
Test status
Simulation time 411741088 ps
CPU time 11.91 seconds
Started Jul 03 04:34:11 PM PDT 24
Finished Jul 03 04:34:23 PM PDT 24
Peak memory 218940 kb
Host smart-099da102-ea48-4f28-99b8-3442988294cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268321806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2268321806
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2205001457
Short name T389
Test name
Test status
Simulation time 3584223710 ps
CPU time 14.21 seconds
Started Jul 03 04:34:18 PM PDT 24
Finished Jul 03 04:34:33 PM PDT 24
Peak memory 210680 kb
Host smart-99d3567c-8924-404e-a9b1-6dc352219cf3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205001457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2205001457
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3936161552
Short name T442
Test name
Test status
Simulation time 858698130 ps
CPU time 6.11 seconds
Started Jul 03 04:34:19 PM PDT 24
Finished Jul 03 04:34:25 PM PDT 24
Peak memory 210668 kb
Host smart-6cb14eef-1d49-41d4-837f-2f92bbfccf02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936161552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3936161552
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1142543537
Short name T86
Test name
Test status
Simulation time 8796616247 ps
CPU time 13.97 seconds
Started Jul 03 04:34:18 PM PDT 24
Finished Jul 03 04:34:33 PM PDT 24
Peak memory 210756 kb
Host smart-91006450-1af9-4b11-be57-e15384b070e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142543537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1142543537
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3710893107
Short name T424
Test name
Test status
Simulation time 3101568085 ps
CPU time 13.26 seconds
Started Jul 03 04:34:19 PM PDT 24
Finished Jul 03 04:34:32 PM PDT 24
Peak memory 219076 kb
Host smart-83cd11af-681e-42b2-bfff-2977d061e9da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710893107 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3710893107
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3866980345
Short name T64
Test name
Test status
Simulation time 637115744 ps
CPU time 4.12 seconds
Started Jul 03 04:34:20 PM PDT 24
Finished Jul 03 04:34:24 PM PDT 24
Peak memory 217532 kb
Host smart-439e9bc9-d578-484c-8430-4d7e714fe9eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866980345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3866980345
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2347284614
Short name T375
Test name
Test status
Simulation time 2062644534 ps
CPU time 9.71 seconds
Started Jul 03 04:34:12 PM PDT 24
Finished Jul 03 04:34:22 PM PDT 24
Peak memory 210556 kb
Host smart-ad00d6ef-6087-4da7-ad66-10afe520d4f1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347284614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2347284614
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4216743178
Short name T395
Test name
Test status
Simulation time 640197212 ps
CPU time 4.17 seconds
Started Jul 03 04:34:14 PM PDT 24
Finished Jul 03 04:34:18 PM PDT 24
Peak memory 210536 kb
Host smart-6db8f3e0-645f-4869-b79d-c6b54b0b2ea8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216743178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4216743178
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1548929172
Short name T379
Test name
Test status
Simulation time 755591411 ps
CPU time 17.95 seconds
Started Jul 03 04:34:12 PM PDT 24
Finished Jul 03 04:34:31 PM PDT 24
Peak memory 210712 kb
Host smart-cf96afb1-3147-433c-8f4b-492283a3589a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548929172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1548929172
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.949247396
Short name T403
Test name
Test status
Simulation time 416190709 ps
CPU time 4.14 seconds
Started Jul 03 04:34:20 PM PDT 24
Finished Jul 03 04:34:24 PM PDT 24
Peak memory 210740 kb
Host smart-13097d3f-c4cd-4f9f-9445-e9c3e2723de2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949247396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.949247396
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1880431422
Short name T439
Test name
Test status
Simulation time 248689712 ps
CPU time 9.79 seconds
Started Jul 03 04:34:12 PM PDT 24
Finished Jul 03 04:34:22 PM PDT 24
Peak memory 218960 kb
Host smart-c0a66890-2735-4f16-8c02-19ef51a098e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880431422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1880431422
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3573862312
Short name T367
Test name
Test status
Simulation time 1517300083 ps
CPU time 13.57 seconds
Started Jul 03 04:34:35 PM PDT 24
Finished Jul 03 04:34:49 PM PDT 24
Peak memory 218908 kb
Host smart-328e5ebd-9bde-4dbd-a119-d3fb5d6ff8ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573862312 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3573862312
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2263852047
Short name T441
Test name
Test status
Simulation time 914962022 ps
CPU time 9.26 seconds
Started Jul 03 04:34:35 PM PDT 24
Finished Jul 03 04:34:44 PM PDT 24
Peak memory 210712 kb
Host smart-9b6ab26a-ac85-4caa-a270-82d7bb521264
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263852047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2263852047
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3457703244
Short name T413
Test name
Test status
Simulation time 3036460519 ps
CPU time 9.93 seconds
Started Jul 03 04:34:37 PM PDT 24
Finished Jul 03 04:34:48 PM PDT 24
Peak memory 218768 kb
Host smart-a005983d-1cca-4ea2-b464-ee505d25e3a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457703244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3457703244
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.727091052
Short name T364
Test name
Test status
Simulation time 450460979 ps
CPU time 11.28 seconds
Started Jul 03 04:34:39 PM PDT 24
Finished Jul 03 04:34:51 PM PDT 24
Peak memory 218928 kb
Host smart-aa9a48b4-4d42-4b8c-b57d-acad546469b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727091052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.727091052
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.459174888
Short name T460
Test name
Test status
Simulation time 2010660066 ps
CPU time 12.27 seconds
Started Jul 03 04:34:39 PM PDT 24
Finished Jul 03 04:34:51 PM PDT 24
Peak memory 218920 kb
Host smart-6341bd89-9847-4543-ab92-cadbf93e4c2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459174888 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.459174888
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1400401111
Short name T434
Test name
Test status
Simulation time 1427617889 ps
CPU time 13.7 seconds
Started Jul 03 04:34:34 PM PDT 24
Finished Jul 03 04:34:48 PM PDT 24
Peak memory 210688 kb
Host smart-728f7095-90d8-40dd-989c-4991529c334b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400401111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1400401111
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1720504766
Short name T85
Test name
Test status
Simulation time 31516715706 ps
CPU time 74.46 seconds
Started Jul 03 04:34:37 PM PDT 24
Finished Jul 03 04:35:52 PM PDT 24
Peak memory 210744 kb
Host smart-6f4b0ce7-69de-40b5-a280-789f7f822041
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720504766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1720504766
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1693466249
Short name T70
Test name
Test status
Simulation time 1581498351 ps
CPU time 15.44 seconds
Started Jul 03 04:34:36 PM PDT 24
Finished Jul 03 04:34:51 PM PDT 24
Peak memory 210716 kb
Host smart-6b22ab5f-1133-41b2-b55a-c6c2c59f0277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693466249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1693466249
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2718730692
Short name T365
Test name
Test status
Simulation time 346262371 ps
CPU time 6.22 seconds
Started Jul 03 04:34:33 PM PDT 24
Finished Jul 03 04:34:40 PM PDT 24
Peak memory 218964 kb
Host smart-de95361b-b7b4-4371-88ac-2f902ea6d51d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718730692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2718730692
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1728528023
Short name T111
Test name
Test status
Simulation time 2197572731 ps
CPU time 46.95 seconds
Started Jul 03 04:34:33 PM PDT 24
Finished Jul 03 04:35:21 PM PDT 24
Peak memory 218976 kb
Host smart-742125b5-76d5-4027-a434-692098e64f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728528023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1728528023
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3898730434
Short name T391
Test name
Test status
Simulation time 1213848264 ps
CPU time 11.52 seconds
Started Jul 03 04:34:39 PM PDT 24
Finished Jul 03 04:34:51 PM PDT 24
Peak memory 219012 kb
Host smart-910f7bae-3c3f-4f62-8ba3-cfb2e7bbfb34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898730434 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3898730434
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1649943892
Short name T374
Test name
Test status
Simulation time 10003842271 ps
CPU time 16.54 seconds
Started Jul 03 04:34:38 PM PDT 24
Finished Jul 03 04:34:55 PM PDT 24
Peak memory 218396 kb
Host smart-4e8710f1-d442-411d-a24c-bcb24db42ce4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649943892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1649943892
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3439951693
Short name T388
Test name
Test status
Simulation time 2408460617 ps
CPU time 18.37 seconds
Started Jul 03 04:34:40 PM PDT 24
Finished Jul 03 04:34:58 PM PDT 24
Peak memory 210720 kb
Host smart-823651bb-425d-45e1-a625-406290f53e82
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439951693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3439951693
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1230502009
Short name T65
Test name
Test status
Simulation time 20570325370 ps
CPU time 15.22 seconds
Started Jul 03 04:34:40 PM PDT 24
Finished Jul 03 04:34:56 PM PDT 24
Peak memory 218928 kb
Host smart-3980d4e0-daa4-4f94-b273-7e99276e8f70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230502009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1230502009
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1171306482
Short name T423
Test name
Test status
Simulation time 6969051936 ps
CPU time 15.94 seconds
Started Jul 03 04:34:40 PM PDT 24
Finished Jul 03 04:34:56 PM PDT 24
Peak memory 219004 kb
Host smart-2aa389c7-1233-4fd9-99e0-4d944e3ad308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171306482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1171306482
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.411763088
Short name T110
Test name
Test status
Simulation time 574039607 ps
CPU time 36.85 seconds
Started Jul 03 04:34:41 PM PDT 24
Finished Jul 03 04:35:18 PM PDT 24
Peak memory 218916 kb
Host smart-e7b2e4d6-20b3-43fb-98a1-f77a7ca44416
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411763088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.411763088
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1379436183
Short name T361
Test name
Test status
Simulation time 1593649889 ps
CPU time 14.28 seconds
Started Jul 03 04:34:39 PM PDT 24
Finished Jul 03 04:34:54 PM PDT 24
Peak memory 219024 kb
Host smart-a811f35e-1791-4ca1-b0c0-13694c52a679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379436183 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1379436183
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1654527318
Short name T55
Test name
Test status
Simulation time 86709988 ps
CPU time 4.24 seconds
Started Jul 03 04:34:37 PM PDT 24
Finished Jul 03 04:34:42 PM PDT 24
Peak memory 217924 kb
Host smart-34a42006-b60e-4828-b677-f001bd126770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654527318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1654527318
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2278928608
Short name T449
Test name
Test status
Simulation time 2195560928 ps
CPU time 15.92 seconds
Started Jul 03 04:34:40 PM PDT 24
Finished Jul 03 04:34:57 PM PDT 24
Peak memory 217992 kb
Host smart-4d25f205-76f7-42e7-b03e-20f7465bbfcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278928608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2278928608
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1550262223
Short name T393
Test name
Test status
Simulation time 1571134922 ps
CPU time 15.62 seconds
Started Jul 03 04:34:38 PM PDT 24
Finished Jul 03 04:34:54 PM PDT 24
Peak memory 215428 kb
Host smart-729eeb99-9f3a-4f48-9a99-f3b948640edc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550262223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1550262223
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3018248183
Short name T454
Test name
Test status
Simulation time 91850241 ps
CPU time 4.65 seconds
Started Jul 03 04:34:46 PM PDT 24
Finished Jul 03 04:34:51 PM PDT 24
Peak memory 212456 kb
Host smart-85112eb8-bd85-4bd4-bf35-3c8a0fee17bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018248183 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3018248183
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1354770691
Short name T417
Test name
Test status
Simulation time 1182585183 ps
CPU time 4.09 seconds
Started Jul 03 04:34:52 PM PDT 24
Finished Jul 03 04:34:56 PM PDT 24
Peak memory 210716 kb
Host smart-03cd63b1-d1f7-4f7b-b8f3-00dab0793327
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354770691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1354770691
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1888309342
Short name T427
Test name
Test status
Simulation time 14104851146 ps
CPU time 70.6 seconds
Started Jul 03 04:34:42 PM PDT 24
Finished Jul 03 04:35:53 PM PDT 24
Peak memory 210772 kb
Host smart-a203e0f3-8cde-43a6-80dd-582ef4695a08
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888309342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1888309342
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2365648226
Short name T437
Test name
Test status
Simulation time 329886101 ps
CPU time 6.14 seconds
Started Jul 03 04:34:42 PM PDT 24
Finished Jul 03 04:34:49 PM PDT 24
Peak memory 218244 kb
Host smart-459038a6-9c0a-4358-95ad-650ad99863eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365648226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2365648226
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2224285149
Short name T368
Test name
Test status
Simulation time 2283708118 ps
CPU time 10.53 seconds
Started Jul 03 04:34:46 PM PDT 24
Finished Jul 03 04:34:57 PM PDT 24
Peak memory 214480 kb
Host smart-45db99f3-2d11-4b45-a7d9-5b0b86eed471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224285149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2224285149
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2161345026
Short name T113
Test name
Test status
Simulation time 487166173 ps
CPU time 69.2 seconds
Started Jul 03 04:34:42 PM PDT 24
Finished Jul 03 04:35:52 PM PDT 24
Peak memory 218892 kb
Host smart-b186c1e1-1e03-4f23-a6a0-23901d6df55b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161345026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2161345026
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.194808099
Short name T402
Test name
Test status
Simulation time 1518588346 ps
CPU time 13.55 seconds
Started Jul 03 04:34:43 PM PDT 24
Finished Jul 03 04:34:57 PM PDT 24
Peak memory 218904 kb
Host smart-47a70413-b45d-4fb8-9c2b-94436c6f6806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194808099 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.194808099
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2009393690
Short name T447
Test name
Test status
Simulation time 11762823079 ps
CPU time 10.72 seconds
Started Jul 03 04:34:42 PM PDT 24
Finished Jul 03 04:34:53 PM PDT 24
Peak memory 218872 kb
Host smart-4de2782e-e680-4996-a6e3-644c17c5362c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009393690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2009393690
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.899162294
Short name T82
Test name
Test status
Simulation time 5546374773 ps
CPU time 51.01 seconds
Started Jul 03 04:34:42 PM PDT 24
Finished Jul 03 04:35:34 PM PDT 24
Peak memory 210696 kb
Host smart-44d95091-ee3e-42b7-ab32-9a782e3c8c15
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899162294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.899162294
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3839949110
Short name T446
Test name
Test status
Simulation time 1730889789 ps
CPU time 14.79 seconds
Started Jul 03 04:34:46 PM PDT 24
Finished Jul 03 04:35:02 PM PDT 24
Peak memory 218908 kb
Host smart-afb0f715-d0e2-428d-9790-73b1659d12cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839949110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3839949110
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1418523700
Short name T426
Test name
Test status
Simulation time 2620643963 ps
CPU time 12.33 seconds
Started Jul 03 04:34:50 PM PDT 24
Finished Jul 03 04:35:03 PM PDT 24
Peak memory 219028 kb
Host smart-9bbac795-eb26-4ccc-94ea-67a637791882
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418523700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1418523700
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1944097356
Short name T52
Test name
Test status
Simulation time 548421352 ps
CPU time 74.21 seconds
Started Jul 03 04:34:43 PM PDT 24
Finished Jul 03 04:35:58 PM PDT 24
Peak memory 213500 kb
Host smart-5f7af47e-af60-4212-901d-7ff067e93955
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944097356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1944097356
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.93933281
Short name T429
Test name
Test status
Simulation time 1196455441 ps
CPU time 11.61 seconds
Started Jul 03 04:34:44 PM PDT 24
Finished Jul 03 04:34:56 PM PDT 24
Peak memory 218896 kb
Host smart-4253011f-f53c-43f8-a590-b55afd20be2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93933281 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.93933281
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.121032701
Short name T102
Test name
Test status
Simulation time 1682481220 ps
CPU time 13.89 seconds
Started Jul 03 04:34:52 PM PDT 24
Finished Jul 03 04:35:06 PM PDT 24
Peak memory 218624 kb
Host smart-c95d4104-f1fa-40bb-8838-9cc594a55a2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121032701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.121032701
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2381768176
Short name T87
Test name
Test status
Simulation time 61786748505 ps
CPU time 80.46 seconds
Started Jul 03 04:34:52 PM PDT 24
Finished Jul 03 04:36:13 PM PDT 24
Peak memory 210800 kb
Host smart-1a0142ac-b433-4f52-b449-3f571fce4909
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381768176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2381768176
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2353229829
Short name T89
Test name
Test status
Simulation time 372338090 ps
CPU time 7.23 seconds
Started Jul 03 04:34:46 PM PDT 24
Finished Jul 03 04:34:54 PM PDT 24
Peak memory 217804 kb
Host smart-5c59639b-d005-4467-9dd9-7aa07db47bf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353229829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2353229829
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1050442943
Short name T419
Test name
Test status
Simulation time 3787994270 ps
CPU time 18.5 seconds
Started Jul 03 04:34:44 PM PDT 24
Finished Jul 03 04:35:03 PM PDT 24
Peak memory 219024 kb
Host smart-60c86884-426f-4318-bbd5-517116d48f81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050442943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1050442943
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1695151311
Short name T398
Test name
Test status
Simulation time 2203072963 ps
CPU time 69.32 seconds
Started Jul 03 04:34:41 PM PDT 24
Finished Jul 03 04:35:50 PM PDT 24
Peak memory 218976 kb
Host smart-5a7b8955-0ef8-4e97-991f-2cbcde40bc8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695151311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1695151311
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2591790925
Short name T362
Test name
Test status
Simulation time 2955113123 ps
CPU time 8.89 seconds
Started Jul 03 04:34:46 PM PDT 24
Finished Jul 03 04:34:56 PM PDT 24
Peak memory 219044 kb
Host smart-7c9f1855-44c3-439a-8de2-d44feb90c475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591790925 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2591790925
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2807056388
Short name T450
Test name
Test status
Simulation time 3228652605 ps
CPU time 13.4 seconds
Started Jul 03 04:34:45 PM PDT 24
Finished Jul 03 04:34:59 PM PDT 24
Peak memory 218888 kb
Host smart-900ed6b4-c861-4845-b17a-da487395fab8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807056388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2807056388
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3110075528
Short name T84
Test name
Test status
Simulation time 18274360959 ps
CPU time 81.59 seconds
Started Jul 03 04:34:46 PM PDT 24
Finished Jul 03 04:36:08 PM PDT 24
Peak memory 211776 kb
Host smart-33434f5d-4a12-4d86-8d3c-317372efedaa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110075528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3110075528
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4067830924
Short name T406
Test name
Test status
Simulation time 13387914031 ps
CPU time 16.14 seconds
Started Jul 03 04:34:47 PM PDT 24
Finished Jul 03 04:35:03 PM PDT 24
Peak memory 211096 kb
Host smart-7ddf7518-2124-4b1f-9213-23adcfd6b41b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067830924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4067830924
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4264704310
Short name T408
Test name
Test status
Simulation time 3716746505 ps
CPU time 18.04 seconds
Started Jul 03 04:34:45 PM PDT 24
Finished Jul 03 04:35:04 PM PDT 24
Peak memory 218984 kb
Host smart-dd053814-4580-4bed-87ff-9cb147c2c94c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264704310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4264704310
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.184445650
Short name T117
Test name
Test status
Simulation time 291656813 ps
CPU time 36.82 seconds
Started Jul 03 04:34:47 PM PDT 24
Finished Jul 03 04:35:24 PM PDT 24
Peak memory 218872 kb
Host smart-d2bc2913-0ee6-4f36-8ea6-3507539328ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184445650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.184445650
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.181533477
Short name T457
Test name
Test status
Simulation time 355760348 ps
CPU time 6.06 seconds
Started Jul 03 04:34:44 PM PDT 24
Finished Jul 03 04:34:51 PM PDT 24
Peak memory 218940 kb
Host smart-1d41564c-b9f8-47c3-a740-0494bac22278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181533477 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.181533477
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.805918206
Short name T66
Test name
Test status
Simulation time 168226906 ps
CPU time 4.2 seconds
Started Jul 03 04:34:47 PM PDT 24
Finished Jul 03 04:34:52 PM PDT 24
Peak memory 217936 kb
Host smart-cb5c1949-1e80-4e8f-9cb1-4f7322102b0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805918206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.805918206
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.7006475
Short name T101
Test name
Test status
Simulation time 14903673041 ps
CPU time 27.58 seconds
Started Jul 03 04:34:45 PM PDT 24
Finished Jul 03 04:35:13 PM PDT 24
Peak memory 210784 kb
Host smart-f99e7983-9f91-40d2-9a13-8febf8ebb72e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7006475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pass
thru_mem_tl_intg_err.7006475
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1014276673
Short name T90
Test name
Test status
Simulation time 115006651 ps
CPU time 4.25 seconds
Started Jul 03 04:34:47 PM PDT 24
Finished Jul 03 04:34:51 PM PDT 24
Peak memory 210784 kb
Host smart-be653154-9aa8-44bd-823e-6e55ab9ab745
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014276673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1014276673
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.256518313
Short name T433
Test name
Test status
Simulation time 654950131 ps
CPU time 12.24 seconds
Started Jul 03 04:34:45 PM PDT 24
Finished Jul 03 04:34:57 PM PDT 24
Peak memory 218964 kb
Host smart-c15ad39a-7a97-43a7-8e88-4eb97e43164b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256518313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.256518313
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2963666105
Short name T114
Test name
Test status
Simulation time 9854545716 ps
CPU time 42.08 seconds
Started Jul 03 04:34:47 PM PDT 24
Finished Jul 03 04:35:29 PM PDT 24
Peak memory 218960 kb
Host smart-9a026910-d319-4bc5-a482-ded902548f94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963666105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2963666105
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.847985881
Short name T459
Test name
Test status
Simulation time 1604682677 ps
CPU time 8.05 seconds
Started Jul 03 04:34:51 PM PDT 24
Finished Jul 03 04:35:00 PM PDT 24
Peak memory 219024 kb
Host smart-528eb4a5-283d-4866-ae89-85eb9ac4cbe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847985881 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.847985881
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.217301349
Short name T62
Test name
Test status
Simulation time 1516201041 ps
CPU time 13.31 seconds
Started Jul 03 04:34:53 PM PDT 24
Finished Jul 03 04:35:06 PM PDT 24
Peak memory 217752 kb
Host smart-4a1434b9-565b-4b83-ab00-9e6c4d99f3d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217301349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.217301349
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3247247076
Short name T448
Test name
Test status
Simulation time 2238655123 ps
CPU time 18.26 seconds
Started Jul 03 04:34:46 PM PDT 24
Finished Jul 03 04:35:04 PM PDT 24
Peak memory 210740 kb
Host smart-a2816f23-debf-4add-829d-b5ffc3082d9d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247247076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3247247076
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2683387618
Short name T458
Test name
Test status
Simulation time 3079456540 ps
CPU time 13.03 seconds
Started Jul 03 04:34:50 PM PDT 24
Finished Jul 03 04:35:04 PM PDT 24
Peak memory 218992 kb
Host smart-14c5273b-c6f2-4512-a3aa-bd544be9876f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683387618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2683387618
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2959415453
Short name T380
Test name
Test status
Simulation time 16379432330 ps
CPU time 21.38 seconds
Started Jul 03 04:34:49 PM PDT 24
Finished Jul 03 04:35:11 PM PDT 24
Peak memory 218840 kb
Host smart-516e0df9-7fef-4c1e-b61b-7f23caebc24f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959415453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2959415453
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4100674104
Short name T386
Test name
Test status
Simulation time 2501619970 ps
CPU time 69.48 seconds
Started Jul 03 04:34:51 PM PDT 24
Finished Jul 03 04:36:01 PM PDT 24
Peak memory 212296 kb
Host smart-1511cecc-019b-4b10-83cd-c79b5cf29669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100674104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4100674104
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1823244298
Short name T425
Test name
Test status
Simulation time 1113917494 ps
CPU time 10.16 seconds
Started Jul 03 04:34:29 PM PDT 24
Finished Jul 03 04:34:40 PM PDT 24
Peak memory 210628 kb
Host smart-9e24e85a-352a-4dfe-8f8e-189620c62884
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823244298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1823244298
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1112031152
Short name T385
Test name
Test status
Simulation time 175638691 ps
CPU time 4.6 seconds
Started Jul 03 04:34:21 PM PDT 24
Finished Jul 03 04:34:26 PM PDT 24
Peak memory 217972 kb
Host smart-0f1068d6-10fa-47ee-abca-ab4d515af803
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112031152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1112031152
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.574624075
Short name T392
Test name
Test status
Simulation time 89082280 ps
CPU time 7.21 seconds
Started Jul 03 04:34:19 PM PDT 24
Finished Jul 03 04:34:27 PM PDT 24
Peak memory 210516 kb
Host smart-b10f8dc2-8fd4-4532-91ed-09bdb0cffa79
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574624075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.574624075
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.780376233
Short name T370
Test name
Test status
Simulation time 486627398 ps
CPU time 6.97 seconds
Started Jul 03 04:34:30 PM PDT 24
Finished Jul 03 04:34:37 PM PDT 24
Peak memory 218932 kb
Host smart-dad4c24f-7f30-4646-a28a-6b4a97a3a6b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780376233 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.780376233
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2217961067
Short name T452
Test name
Test status
Simulation time 333778376 ps
CPU time 4.15 seconds
Started Jul 03 04:34:23 PM PDT 24
Finished Jul 03 04:34:28 PM PDT 24
Peak memory 217236 kb
Host smart-5f97cd20-20c4-4a25-9470-5bb830ac8c2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217961067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2217961067
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.23714292
Short name T418
Test name
Test status
Simulation time 1906647562 ps
CPU time 14.69 seconds
Started Jul 03 04:34:31 PM PDT 24
Finished Jul 03 04:34:46 PM PDT 24
Peak memory 210548 kb
Host smart-42e5cd21-3a69-44f1-b44f-7b1a480385ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23714292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_
mem_partial_access.23714292
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2086734169
Short name T445
Test name
Test status
Simulation time 4024145033 ps
CPU time 16.14 seconds
Started Jul 03 04:34:23 PM PDT 24
Finished Jul 03 04:34:39 PM PDT 24
Peak memory 210632 kb
Host smart-0f67b1b9-d8df-403e-9d3c-ccbd1206d74c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086734169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2086734169
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.816604154
Short name T80
Test name
Test status
Simulation time 8761047083 ps
CPU time 53.55 seconds
Started Jul 03 04:34:17 PM PDT 24
Finished Jul 03 04:35:11 PM PDT 24
Peak memory 210876 kb
Host smart-0fb104fc-9426-42a6-8f38-4a0258626f8c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816604154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.816604154
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2223638844
Short name T396
Test name
Test status
Simulation time 12294154847 ps
CPU time 7.94 seconds
Started Jul 03 04:34:30 PM PDT 24
Finished Jul 03 04:34:38 PM PDT 24
Peak memory 210828 kb
Host smart-cb0f4584-8e3e-4c7a-84b3-dbf6767fead4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223638844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2223638844
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1671765403
Short name T421
Test name
Test status
Simulation time 442448785 ps
CPU time 8.44 seconds
Started Jul 03 04:34:31 PM PDT 24
Finished Jul 03 04:34:40 PM PDT 24
Peak memory 218944 kb
Host smart-af996481-47f2-4121-8ca8-43d8ff35cd4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671765403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1671765403
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2976570771
Short name T438
Test name
Test status
Simulation time 152943325 ps
CPU time 35.98 seconds
Started Jul 03 04:34:21 PM PDT 24
Finished Jul 03 04:34:57 PM PDT 24
Peak memory 218920 kb
Host smart-74dbaa46-b2cd-47b8-834a-66f497c6bdcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976570771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2976570771
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2635179445
Short name T81
Test name
Test status
Simulation time 171554316 ps
CPU time 4.36 seconds
Started Jul 03 04:34:22 PM PDT 24
Finished Jul 03 04:34:27 PM PDT 24
Peak memory 217740 kb
Host smart-fc8ef434-016f-405b-9859-683a64c8ffd5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635179445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2635179445
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.415967669
Short name T378
Test name
Test status
Simulation time 1429696004 ps
CPU time 13.04 seconds
Started Jul 03 04:34:22 PM PDT 24
Finished Jul 03 04:34:35 PM PDT 24
Peak memory 210724 kb
Host smart-b99b325e-64a6-4aa3-9e6d-34e61ff75aaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415967669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.415967669
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3568907118
Short name T371
Test name
Test status
Simulation time 7009135106 ps
CPU time 16.25 seconds
Started Jul 03 04:34:22 PM PDT 24
Finished Jul 03 04:34:38 PM PDT 24
Peak memory 218884 kb
Host smart-885eb1ec-31cd-48e5-8230-2739e29ec8d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568907118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3568907118
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2080202102
Short name T436
Test name
Test status
Simulation time 363721175 ps
CPU time 4.67 seconds
Started Jul 03 04:34:22 PM PDT 24
Finished Jul 03 04:34:27 PM PDT 24
Peak memory 218960 kb
Host smart-4916c0fc-a27d-4153-a8d0-f1f463c80647
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080202102 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2080202102
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1747037031
Short name T103
Test name
Test status
Simulation time 3427417268 ps
CPU time 13.67 seconds
Started Jul 03 04:34:30 PM PDT 24
Finished Jul 03 04:34:44 PM PDT 24
Peak memory 210692 kb
Host smart-b87a107a-befa-415b-9fb2-3922a0f424d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747037031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1747037031
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2430214741
Short name T455
Test name
Test status
Simulation time 225831396 ps
CPU time 5.26 seconds
Started Jul 03 04:34:21 PM PDT 24
Finished Jul 03 04:34:27 PM PDT 24
Peak memory 210580 kb
Host smart-549293f4-55a4-4bab-bca0-e8f83d337d23
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430214741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2430214741
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2069740675
Short name T410
Test name
Test status
Simulation time 1692218172 ps
CPU time 14.41 seconds
Started Jul 03 04:34:21 PM PDT 24
Finished Jul 03 04:34:35 PM PDT 24
Peak memory 210536 kb
Host smart-89a9801a-0d67-4277-b3b8-03e863ed1b54
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069740675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2069740675
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3720771449
Short name T77
Test name
Test status
Simulation time 7211207191 ps
CPU time 38.71 seconds
Started Jul 03 04:34:21 PM PDT 24
Finished Jul 03 04:35:00 PM PDT 24
Peak memory 210792 kb
Host smart-f7859bb5-3dbf-40e2-9465-394714c1ddc3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720771449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3720771449
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1057356791
Short name T394
Test name
Test status
Simulation time 249434901 ps
CPU time 5.76 seconds
Started Jul 03 04:34:21 PM PDT 24
Finished Jul 03 04:34:27 PM PDT 24
Peak memory 218912 kb
Host smart-5c92d22e-c815-4c43-9276-06835efc4c69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057356791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1057356791
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1976436725
Short name T107
Test name
Test status
Simulation time 528327732 ps
CPU time 9.11 seconds
Started Jul 03 04:34:29 PM PDT 24
Finished Jul 03 04:34:39 PM PDT 24
Peak memory 218940 kb
Host smart-6694d834-9aa2-4a77-b1d6-9e6c2b5bb53a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976436725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1976436725
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.292156882
Short name T109
Test name
Test status
Simulation time 939756924 ps
CPU time 69.12 seconds
Started Jul 03 04:34:23 PM PDT 24
Finished Jul 03 04:35:33 PM PDT 24
Peak memory 212328 kb
Host smart-4b5fcfdb-a9bd-4bd6-9bd0-9ef77bb8586f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292156882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.292156882
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1351914806
Short name T451
Test name
Test status
Simulation time 943210469 ps
CPU time 10.33 seconds
Started Jul 03 04:34:29 PM PDT 24
Finished Jul 03 04:34:40 PM PDT 24
Peak memory 218744 kb
Host smart-dff341f1-c16f-44cc-af3a-8e6c33ef4dcf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351914806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1351914806
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.742778432
Short name T381
Test name
Test status
Simulation time 2038134597 ps
CPU time 17.2 seconds
Started Jul 03 04:34:26 PM PDT 24
Finished Jul 03 04:34:43 PM PDT 24
Peak memory 218828 kb
Host smart-dc1d23e3-8d50-4adb-ae83-f7e5bbb46614
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742778432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.742778432
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1328024766
Short name T435
Test name
Test status
Simulation time 24732806048 ps
CPU time 16.58 seconds
Started Jul 03 04:34:25 PM PDT 24
Finished Jul 03 04:34:42 PM PDT 24
Peak memory 218920 kb
Host smart-3f7e4ca8-1c3d-4f0d-8422-1cde3b2b7cee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328024766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1328024766
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1422890801
Short name T383
Test name
Test status
Simulation time 1133972013 ps
CPU time 8.09 seconds
Started Jul 03 04:34:26 PM PDT 24
Finished Jul 03 04:34:35 PM PDT 24
Peak memory 218964 kb
Host smart-db1d74f1-e5ba-44c0-91d7-127f3c52b579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422890801 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1422890801
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2017338973
Short name T430
Test name
Test status
Simulation time 2113038803 ps
CPU time 9.56 seconds
Started Jul 03 04:34:28 PM PDT 24
Finished Jul 03 04:34:38 PM PDT 24
Peak memory 218840 kb
Host smart-40f4a352-5cc2-4c2b-9d56-53db9390200b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017338973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2017338973
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.289462740
Short name T401
Test name
Test status
Simulation time 498151281 ps
CPU time 7.68 seconds
Started Jul 03 04:34:26 PM PDT 24
Finished Jul 03 04:34:34 PM PDT 24
Peak memory 210564 kb
Host smart-9afc2280-591d-4258-a4e3-12aacdd25ff1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289462740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.289462740
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2134345483
Short name T376
Test name
Test status
Simulation time 15089395972 ps
CPU time 17.3 seconds
Started Jul 03 04:34:29 PM PDT 24
Finished Jul 03 04:34:47 PM PDT 24
Peak memory 210536 kb
Host smart-7bb6f1a2-338a-41b3-bd67-0e4542a87cd4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134345483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2134345483
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1876148350
Short name T67
Test name
Test status
Simulation time 550190958 ps
CPU time 27.74 seconds
Started Jul 03 04:34:26 PM PDT 24
Finished Jul 03 04:34:54 PM PDT 24
Peak memory 210732 kb
Host smart-be99aa1d-2faf-4146-9f81-ebf6cc1495e0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876148350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1876148350
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.437719523
Short name T384
Test name
Test status
Simulation time 924706615 ps
CPU time 7.43 seconds
Started Jul 03 04:34:26 PM PDT 24
Finished Jul 03 04:34:34 PM PDT 24
Peak memory 210772 kb
Host smart-4e069f65-ccec-4db2-8b91-0070791d2ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437719523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.437719523
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2128942049
Short name T456
Test name
Test status
Simulation time 1871096443 ps
CPU time 20.24 seconds
Started Jul 03 04:34:28 PM PDT 24
Finished Jul 03 04:34:49 PM PDT 24
Peak memory 218968 kb
Host smart-c384bab4-aea0-41f2-af88-fb16085aa01b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128942049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2128942049
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3349716892
Short name T414
Test name
Test status
Simulation time 3962456732 ps
CPU time 71.87 seconds
Started Jul 03 04:34:27 PM PDT 24
Finished Jul 03 04:35:40 PM PDT 24
Peak memory 218972 kb
Host smart-d98ecae4-0f56-45bf-9213-060142ef3d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349716892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3349716892
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.288803747
Short name T412
Test name
Test status
Simulation time 99041776 ps
CPU time 4.64 seconds
Started Jul 03 04:34:25 PM PDT 24
Finished Jul 03 04:34:30 PM PDT 24
Peak memory 218980 kb
Host smart-d07c236f-62ea-4181-88bd-c186e32c5ce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288803747 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.288803747
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3222820853
Short name T63
Test name
Test status
Simulation time 1393685344 ps
CPU time 8.51 seconds
Started Jul 03 04:34:26 PM PDT 24
Finished Jul 03 04:34:35 PM PDT 24
Peak memory 210664 kb
Host smart-a5c6269d-e71b-41e5-88f8-e226a0683e28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222820853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3222820853
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4275227256
Short name T108
Test name
Test status
Simulation time 36480266977 ps
CPU time 83.28 seconds
Started Jul 03 04:34:24 PM PDT 24
Finished Jul 03 04:35:47 PM PDT 24
Peak memory 210740 kb
Host smart-374cb73f-6d1c-46e1-bde9-fb51c71229ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275227256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4275227256
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2648249806
Short name T397
Test name
Test status
Simulation time 88210472 ps
CPU time 4.35 seconds
Started Jul 03 04:34:25 PM PDT 24
Finished Jul 03 04:34:30 PM PDT 24
Peak memory 218220 kb
Host smart-978def1c-beb8-4846-a3cb-3c55f7b1632d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648249806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2648249806
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3934976865
Short name T377
Test name
Test status
Simulation time 2686627014 ps
CPU time 15.36 seconds
Started Jul 03 04:34:26 PM PDT 24
Finished Jul 03 04:34:42 PM PDT 24
Peak memory 218992 kb
Host smart-f943401b-8750-4967-907e-a4fa9e60273f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934976865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3934976865
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.929803425
Short name T382
Test name
Test status
Simulation time 2503514228 ps
CPU time 39.23 seconds
Started Jul 03 04:34:26 PM PDT 24
Finished Jul 03 04:35:05 PM PDT 24
Peak memory 212088 kb
Host smart-2b236721-6cc8-4884-880a-0536678b5cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929803425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.929803425
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3584203948
Short name T443
Test name
Test status
Simulation time 4386399713 ps
CPU time 9.46 seconds
Started Jul 03 04:34:31 PM PDT 24
Finished Jul 03 04:34:41 PM PDT 24
Peak memory 218960 kb
Host smart-96b293cb-e0c3-4851-822c-16c6487e8e05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584203948 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3584203948
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.247778101
Short name T400
Test name
Test status
Simulation time 6967680529 ps
CPU time 13.89 seconds
Started Jul 03 04:34:28 PM PDT 24
Finished Jul 03 04:34:42 PM PDT 24
Peak memory 210728 kb
Host smart-be4efa84-56fd-4600-aa30-64981868c702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247778101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.247778101
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2640621765
Short name T373
Test name
Test status
Simulation time 2046403369 ps
CPU time 25.21 seconds
Started Jul 03 04:34:31 PM PDT 24
Finished Jul 03 04:34:56 PM PDT 24
Peak memory 210708 kb
Host smart-c776ea7a-99c7-479c-914d-779b5c39ff6d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640621765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2640621765
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2911657044
Short name T431
Test name
Test status
Simulation time 6312435392 ps
CPU time 12.86 seconds
Started Jul 03 04:34:30 PM PDT 24
Finished Jul 03 04:34:43 PM PDT 24
Peak memory 210968 kb
Host smart-33a77da6-6687-4b5c-af08-cf75851d4b16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911657044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2911657044
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2942541848
Short name T390
Test name
Test status
Simulation time 346730843 ps
CPU time 6.21 seconds
Started Jul 03 04:34:37 PM PDT 24
Finished Jul 03 04:34:44 PM PDT 24
Peak memory 218964 kb
Host smart-8c86a6e2-3a17-44de-bced-13ef9f9137a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942541848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2942541848
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3405656927
Short name T51
Test name
Test status
Simulation time 2188878478 ps
CPU time 77.03 seconds
Started Jul 03 04:34:38 PM PDT 24
Finished Jul 03 04:35:56 PM PDT 24
Peak memory 218984 kb
Host smart-d418acb7-cb49-4616-b8e3-c8248ef2013c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405656927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3405656927
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2026548816
Short name T416
Test name
Test status
Simulation time 397699748 ps
CPU time 7.01 seconds
Started Jul 03 04:34:28 PM PDT 24
Finished Jul 03 04:34:36 PM PDT 24
Peak memory 218908 kb
Host smart-4edcc2f0-4b5f-4b1b-84e4-de9be58fbdb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026548816 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2026548816
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1951266251
Short name T387
Test name
Test status
Simulation time 9223608193 ps
CPU time 14.3 seconds
Started Jul 03 04:34:33 PM PDT 24
Finished Jul 03 04:34:48 PM PDT 24
Peak memory 218908 kb
Host smart-ad5ebaf4-5fc8-4c6f-b601-9709f93847bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951266251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1951266251
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2436686050
Short name T69
Test name
Test status
Simulation time 18478246056 ps
CPU time 87.39 seconds
Started Jul 03 04:34:29 PM PDT 24
Finished Jul 03 04:35:57 PM PDT 24
Peak memory 210856 kb
Host smart-1b82c588-e054-4bcb-aba5-006fec6a60cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436686050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2436686050
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3663501129
Short name T88
Test name
Test status
Simulation time 90240582 ps
CPU time 4.15 seconds
Started Jul 03 04:34:38 PM PDT 24
Finished Jul 03 04:34:43 PM PDT 24
Peak memory 218480 kb
Host smart-49a7ad72-87e7-49da-b435-dd22bc6aa386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663501129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3663501129
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3834450179
Short name T444
Test name
Test status
Simulation time 3602839750 ps
CPU time 12.47 seconds
Started Jul 03 04:34:30 PM PDT 24
Finished Jul 03 04:34:43 PM PDT 24
Peak memory 218916 kb
Host smart-6bbccb05-3c35-4005-b8d8-7656c4fd9e39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834450179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3834450179
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1481208215
Short name T116
Test name
Test status
Simulation time 2050159074 ps
CPU time 79.05 seconds
Started Jul 03 04:34:31 PM PDT 24
Finished Jul 03 04:35:50 PM PDT 24
Peak memory 212104 kb
Host smart-e8a6e292-5227-4d94-9207-ef3e63dd6f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481208215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1481208215
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3197580636
Short name T407
Test name
Test status
Simulation time 11376620457 ps
CPU time 10.21 seconds
Started Jul 03 04:34:31 PM PDT 24
Finished Jul 03 04:34:41 PM PDT 24
Peak memory 219020 kb
Host smart-858ab4f9-c3e7-4e42-b23f-696dcde5e6dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197580636 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3197580636
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1616516229
Short name T83
Test name
Test status
Simulation time 1871575658 ps
CPU time 9.67 seconds
Started Jul 03 04:34:32 PM PDT 24
Finished Jul 03 04:34:42 PM PDT 24
Peak memory 218272 kb
Host smart-66678044-65a4-492b-93b5-9b5a4ba36f18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616516229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1616516229
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3756679459
Short name T68
Test name
Test status
Simulation time 20466498688 ps
CPU time 47.36 seconds
Started Jul 03 04:34:37 PM PDT 24
Finished Jul 03 04:35:25 PM PDT 24
Peak memory 210800 kb
Host smart-87e0931f-6578-4fa4-8265-4528d673e5ac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756679459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3756679459
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.715939522
Short name T405
Test name
Test status
Simulation time 7168991271 ps
CPU time 13.66 seconds
Started Jul 03 04:34:32 PM PDT 24
Finished Jul 03 04:34:46 PM PDT 24
Peak memory 211056 kb
Host smart-32b30580-7734-40a5-a2a4-65bd78fb4a41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715939522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.715939522
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4011133784
Short name T411
Test name
Test status
Simulation time 5931224720 ps
CPU time 18.08 seconds
Started Jul 03 04:34:30 PM PDT 24
Finished Jul 03 04:34:49 PM PDT 24
Peak memory 218896 kb
Host smart-01fd556a-bec1-419b-9249-2d4c07c812ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011133784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.4011133784
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4082013259
Short name T399
Test name
Test status
Simulation time 1832926599 ps
CPU time 76.24 seconds
Started Jul 03 04:34:34 PM PDT 24
Finished Jul 03 04:35:50 PM PDT 24
Peak memory 218920 kb
Host smart-b0b19183-0486-4852-ae64-8b9bce04b18c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082013259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4082013259
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1576284133
Short name T372
Test name
Test status
Simulation time 90975549 ps
CPU time 4.29 seconds
Started Jul 03 04:34:40 PM PDT 24
Finished Jul 03 04:34:45 PM PDT 24
Peak memory 218868 kb
Host smart-68a5ed56-118d-4ddd-8a3e-69256dd81592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576284133 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1576284133
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4036144446
Short name T76
Test name
Test status
Simulation time 106066599 ps
CPU time 4.2 seconds
Started Jul 03 04:34:38 PM PDT 24
Finished Jul 03 04:34:43 PM PDT 24
Peak memory 210604 kb
Host smart-d5af47cd-0704-4d50-ad47-a02bf5ffb39b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036144446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4036144446
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2629029921
Short name T78
Test name
Test status
Simulation time 35101701286 ps
CPU time 35.54 seconds
Started Jul 03 04:34:37 PM PDT 24
Finished Jul 03 04:35:13 PM PDT 24
Peak memory 210800 kb
Host smart-c0bf8697-c4e7-48ab-80c1-17563b9149f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629029921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2629029921
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2524371705
Short name T461
Test name
Test status
Simulation time 1298556393 ps
CPU time 11.97 seconds
Started Jul 03 04:34:32 PM PDT 24
Finished Jul 03 04:34:44 PM PDT 24
Peak memory 218164 kb
Host smart-adf115d5-ae3a-46ba-9ec7-0e1a998ffaae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524371705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2524371705
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2216821042
Short name T363
Test name
Test status
Simulation time 356015382 ps
CPU time 7.79 seconds
Started Jul 03 04:34:29 PM PDT 24
Finished Jul 03 04:34:37 PM PDT 24
Peak memory 218928 kb
Host smart-58d650ef-b73a-4cef-a12f-e723ac88f2e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216821042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2216821042
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.286980772
Short name T440
Test name
Test status
Simulation time 3940248927 ps
CPU time 79.13 seconds
Started Jul 03 04:34:30 PM PDT 24
Finished Jul 03 04:35:50 PM PDT 24
Peak memory 212044 kb
Host smart-890701fc-a04e-44dd-ac8c-d7a6c90c3702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286980772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.286980772
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3932073
Short name T195
Test name
Test status
Simulation time 8019577122 ps
CPU time 15.24 seconds
Started Jul 03 04:34:51 PM PDT 24
Finished Jul 03 04:35:07 PM PDT 24
Peak memory 211300 kb
Host smart-e69610d3-87b2-4cb4-bc88-3d30dfa5e7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3932073
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2625143073
Short name T40
Test name
Test status
Simulation time 2219260078 ps
CPU time 141.72 seconds
Started Jul 03 04:34:51 PM PDT 24
Finished Jul 03 04:37:13 PM PDT 24
Peak memory 228544 kb
Host smart-80d06ba7-8bee-4668-852a-df734346936c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625143073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2625143073
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.984846335
Short name T157
Test name
Test status
Simulation time 97140114 ps
CPU time 5.51 seconds
Started Jul 03 04:34:51 PM PDT 24
Finished Jul 03 04:34:56 PM PDT 24
Peak memory 211376 kb
Host smart-3a2216d5-d59f-49a7-94be-cf02c48a9676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984846335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.984846335
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1403452576
Short name T19
Test name
Test status
Simulation time 1366660536 ps
CPU time 59.09 seconds
Started Jul 03 04:34:52 PM PDT 24
Finished Jul 03 04:35:51 PM PDT 24
Peak memory 237112 kb
Host smart-f5d6855b-9306-40ed-8fe9-438ff408cc13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403452576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1403452576
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3050233405
Short name T143
Test name
Test status
Simulation time 2155813036 ps
CPU time 21.92 seconds
Started Jul 03 04:34:52 PM PDT 24
Finished Jul 03 04:35:14 PM PDT 24
Peak memory 213276 kb
Host smart-b8df04df-95ba-4a46-87f1-ac6140d9cb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050233405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3050233405
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.166459916
Short name T182
Test name
Test status
Simulation time 15915123771 ps
CPU time 46.54 seconds
Started Jul 03 04:34:56 PM PDT 24
Finished Jul 03 04:35:43 PM PDT 24
Peak memory 215228 kb
Host smart-248f62dd-e54d-4ac2-891c-c69409e43555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166459916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.166459916
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4197705984
Short name T219
Test name
Test status
Simulation time 2323469174 ps
CPU time 11.37 seconds
Started Jul 03 04:34:54 PM PDT 24
Finished Jul 03 04:35:07 PM PDT 24
Peak memory 211352 kb
Host smart-14e087ec-abb5-4ebc-9880-ff3917bdf6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197705984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4197705984
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1730156482
Short name T16
Test name
Test status
Simulation time 27705969791 ps
CPU time 286.49 seconds
Started Jul 03 04:34:54 PM PDT 24
Finished Jul 03 04:39:42 PM PDT 24
Peak memory 212516 kb
Host smart-e9cff28e-800f-43c6-98d7-c42e72bea2eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730156482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1730156482
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2727714750
Short name T30
Test name
Test status
Simulation time 3089924040 ps
CPU time 26.31 seconds
Started Jul 03 04:34:53 PM PDT 24
Finished Jul 03 04:35:20 PM PDT 24
Peak memory 212456 kb
Host smart-288e93d5-1e3c-49af-a006-5d1eb3d494ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727714750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2727714750
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.928300631
Short name T230
Test name
Test status
Simulation time 4802310596 ps
CPU time 11.86 seconds
Started Jul 03 04:34:56 PM PDT 24
Finished Jul 03 04:35:08 PM PDT 24
Peak memory 211376 kb
Host smart-3d04873c-9b55-470d-82c4-f306a506bfc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928300631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.928300631
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2599716487
Short name T27
Test name
Test status
Simulation time 4264482494 ps
CPU time 108.67 seconds
Started Jul 03 04:34:54 PM PDT 24
Finished Jul 03 04:36:44 PM PDT 24
Peak memory 238088 kb
Host smart-16ea5365-2d98-48aa-afb5-09f7942b31c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599716487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2599716487
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2454576690
Short name T148
Test name
Test status
Simulation time 2861219645 ps
CPU time 21.91 seconds
Started Jul 03 04:34:56 PM PDT 24
Finished Jul 03 04:35:18 PM PDT 24
Peak memory 213760 kb
Host smart-2c993ea7-6946-43b5-962a-99308d7094c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454576690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2454576690
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2024967180
Short name T207
Test name
Test status
Simulation time 5152065730 ps
CPU time 50.55 seconds
Started Jul 03 04:34:54 PM PDT 24
Finished Jul 03 04:35:45 PM PDT 24
Peak memory 214856 kb
Host smart-8ba6b08b-005d-4f98-910b-82289d924d85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024967180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2024967180
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3316412376
Short name T96
Test name
Test status
Simulation time 48807022805 ps
CPU time 208.46 seconds
Started Jul 03 04:35:12 PM PDT 24
Finished Jul 03 04:38:41 PM PDT 24
Peak memory 213636 kb
Host smart-62c068a5-be4c-484e-af99-d4ab7a618692
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316412376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3316412376
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3792885055
Short name T179
Test name
Test status
Simulation time 4485368084 ps
CPU time 33.92 seconds
Started Jul 03 04:35:11 PM PDT 24
Finished Jul 03 04:35:46 PM PDT 24
Peak memory 212200 kb
Host smart-3bc5cd85-18b9-4e43-aa09-e8dd6a49d323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792885055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3792885055
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2046758786
Short name T274
Test name
Test status
Simulation time 690757384 ps
CPU time 8.54 seconds
Started Jul 03 04:35:17 PM PDT 24
Finished Jul 03 04:35:26 PM PDT 24
Peak memory 211332 kb
Host smart-6538f15f-61a7-4c3f-a3b7-c203a6c1a8af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046758786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2046758786
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.787663829
Short name T227
Test name
Test status
Simulation time 43863437666 ps
CPU time 29.28 seconds
Started Jul 03 04:35:12 PM PDT 24
Finished Jul 03 04:35:41 PM PDT 24
Peak memory 214076 kb
Host smart-0c782f1c-bc4a-4cd9-8d9e-2aac45f15df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787663829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.787663829
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4127499529
Short name T335
Test name
Test status
Simulation time 3547960380 ps
CPU time 36.6 seconds
Started Jul 03 04:35:10 PM PDT 24
Finished Jul 03 04:35:47 PM PDT 24
Peak memory 213648 kb
Host smart-ab8f8f7e-5146-435d-81f3-12c36148371f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127499529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4127499529
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1357618414
Short name T261
Test name
Test status
Simulation time 232235474 ps
CPU time 4.26 seconds
Started Jul 03 04:35:12 PM PDT 24
Finished Jul 03 04:35:17 PM PDT 24
Peak memory 211284 kb
Host smart-e4d759fb-60e8-413b-82df-08ee1c3b4228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357618414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1357618414
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3010934000
Short name T140
Test name
Test status
Simulation time 2955653256 ps
CPU time 14.37 seconds
Started Jul 03 04:35:12 PM PDT 24
Finished Jul 03 04:35:27 PM PDT 24
Peak memory 214100 kb
Host smart-b02ae673-1af6-4905-a2bf-8cd172370cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010934000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3010934000
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2200029479
Short name T280
Test name
Test status
Simulation time 543884475 ps
CPU time 8.48 seconds
Started Jul 03 04:35:13 PM PDT 24
Finished Jul 03 04:35:22 PM PDT 24
Peak memory 211300 kb
Host smart-42bf33de-82ee-4bdc-b78b-2512a45a8c30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200029479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2200029479
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2914826648
Short name T158
Test name
Test status
Simulation time 2665516666 ps
CPU time 24.22 seconds
Started Jul 03 04:35:16 PM PDT 24
Finished Jul 03 04:35:41 PM PDT 24
Peak memory 213144 kb
Host smart-94502bca-8a8d-4e62-8a92-0e9507f5edc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914826648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2914826648
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1887988136
Short name T217
Test name
Test status
Simulation time 1435283414 ps
CPU time 20.56 seconds
Started Jul 03 04:35:15 PM PDT 24
Finished Jul 03 04:35:36 PM PDT 24
Peak memory 214408 kb
Host smart-f19ff0e7-21d2-4bd1-b383-468256a24f8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887988136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1887988136
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3539227219
Short name T324
Test name
Test status
Simulation time 96540141877 ps
CPU time 3689.18 seconds
Started Jul 03 04:35:17 PM PDT 24
Finished Jul 03 05:36:47 PM PDT 24
Peak memory 252240 kb
Host smart-2c1f6ca7-ce83-4f92-aeaf-a070a0e23ff6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539227219 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3539227219
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2300008564
Short name T170
Test name
Test status
Simulation time 5750861629 ps
CPU time 13.36 seconds
Started Jul 03 04:35:20 PM PDT 24
Finished Jul 03 04:35:34 PM PDT 24
Peak memory 211396 kb
Host smart-af35064b-5120-4ba8-8929-305d8b226955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300008564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2300008564
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1598373014
Short name T41
Test name
Test status
Simulation time 114569543768 ps
CPU time 289.81 seconds
Started Jul 03 04:35:17 PM PDT 24
Finished Jul 03 04:40:07 PM PDT 24
Peak memory 228576 kb
Host smart-d6c9a79d-62f5-46a7-b6d3-450504d6bcc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598373014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1598373014
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1106010722
Short name T181
Test name
Test status
Simulation time 3947849147 ps
CPU time 33.12 seconds
Started Jul 03 04:35:15 PM PDT 24
Finished Jul 03 04:35:49 PM PDT 24
Peak memory 211864 kb
Host smart-1628f6b6-d242-4562-b446-5637b7f1f71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106010722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1106010722
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3896691112
Short name T136
Test name
Test status
Simulation time 2429372516 ps
CPU time 12.11 seconds
Started Jul 03 04:35:15 PM PDT 24
Finished Jul 03 04:35:27 PM PDT 24
Peak memory 211368 kb
Host smart-3451843c-5a52-4d6a-9f4c-ad89d76f0faf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896691112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3896691112
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2002001132
Short name T304
Test name
Test status
Simulation time 3807053227 ps
CPU time 38.85 seconds
Started Jul 03 04:35:14 PM PDT 24
Finished Jul 03 04:35:54 PM PDT 24
Peak memory 213072 kb
Host smart-f05fe3eb-eb2c-4144-ad11-357293075a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002001132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2002001132
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.684053033
Short name T35
Test name
Test status
Simulation time 3565029686 ps
CPU time 52.59 seconds
Started Jul 03 04:35:13 PM PDT 24
Finished Jul 03 04:36:06 PM PDT 24
Peak memory 216688 kb
Host smart-063e3bc6-5a6d-4d8d-9383-2a600e48be9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684053033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.684053033
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.136987360
Short name T232
Test name
Test status
Simulation time 132213701 ps
CPU time 5.04 seconds
Started Jul 03 04:35:20 PM PDT 24
Finished Jul 03 04:35:25 PM PDT 24
Peak memory 211264 kb
Host smart-8bb77082-dab2-4f6d-aee2-46c6e4b8229d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136987360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.136987360
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1894982028
Short name T97
Test name
Test status
Simulation time 15626798804 ps
CPU time 119.84 seconds
Started Jul 03 04:35:20 PM PDT 24
Finished Jul 03 04:37:20 PM PDT 24
Peak memory 237612 kb
Host smart-7f02a7df-fe57-4977-bda9-cf46301ad7a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894982028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1894982028
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2268221851
Short name T177
Test name
Test status
Simulation time 43923315699 ps
CPU time 34.26 seconds
Started Jul 03 04:35:19 PM PDT 24
Finished Jul 03 04:35:54 PM PDT 24
Peak memory 211396 kb
Host smart-44dc4650-d5ba-45fd-b97f-898c15d94eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268221851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2268221851
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3570374468
Short name T255
Test name
Test status
Simulation time 4325060910 ps
CPU time 10.23 seconds
Started Jul 03 04:35:20 PM PDT 24
Finished Jul 03 04:35:31 PM PDT 24
Peak memory 211356 kb
Host smart-607946f9-32ec-48e3-bd4d-d5deecc40015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570374468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3570374468
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.58866357
Short name T94
Test name
Test status
Simulation time 7381582026 ps
CPU time 34.66 seconds
Started Jul 03 04:35:16 PM PDT 24
Finished Jul 03 04:35:51 PM PDT 24
Peak memory 212580 kb
Host smart-9e62b4b5-65ef-4153-8509-38f5ebd88f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58866357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.58866357
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3360385265
Short name T297
Test name
Test status
Simulation time 61273582969 ps
CPU time 108.84 seconds
Started Jul 03 04:35:19 PM PDT 24
Finished Jul 03 04:37:08 PM PDT 24
Peak memory 219340 kb
Host smart-0f062f46-1951-4fb3-ab38-32f6dc7d1156
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360385265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3360385265
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2857117534
Short name T258
Test name
Test status
Simulation time 175489391 ps
CPU time 4.36 seconds
Started Jul 03 04:35:20 PM PDT 24
Finished Jul 03 04:35:25 PM PDT 24
Peak memory 211340 kb
Host smart-48d5330b-5866-41a4-b512-f10fb2cf8f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857117534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2857117534
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2018440212
Short name T99
Test name
Test status
Simulation time 138918201588 ps
CPU time 343.78 seconds
Started Jul 03 04:35:20 PM PDT 24
Finished Jul 03 04:41:04 PM PDT 24
Peak memory 236920 kb
Host smart-33cde3fc-5601-4761-81e7-000fa442b97b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018440212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2018440212
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4055817104
Short name T138
Test name
Test status
Simulation time 11448591729 ps
CPU time 10.87 seconds
Started Jul 03 04:35:20 PM PDT 24
Finished Jul 03 04:35:31 PM PDT 24
Peak memory 211432 kb
Host smart-6485eec1-2778-4e5e-89cc-98a4c5dcbdd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055817104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4055817104
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2250045999
Short name T221
Test name
Test status
Simulation time 6043218117 ps
CPU time 48.98 seconds
Started Jul 03 04:35:17 PM PDT 24
Finished Jul 03 04:36:07 PM PDT 24
Peak memory 213660 kb
Host smart-0f691453-76b7-4588-88dd-2676c8b8bcf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250045999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2250045999
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1984534039
Short name T272
Test name
Test status
Simulation time 1983037953 ps
CPU time 10.05 seconds
Started Jul 03 04:35:19 PM PDT 24
Finished Jul 03 04:35:29 PM PDT 24
Peak memory 211296 kb
Host smart-0793b29d-5ed8-485f-806f-f3a65258bd5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984534039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1984534039
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1775086125
Short name T100
Test name
Test status
Simulation time 27268298731 ps
CPU time 279.93 seconds
Started Jul 03 04:35:21 PM PDT 24
Finished Jul 03 04:40:01 PM PDT 24
Peak memory 228548 kb
Host smart-c7729c5a-2ace-4223-9ca8-5cdbe6c9b8b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775086125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1775086125
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4040334400
Short name T314
Test name
Test status
Simulation time 13922007744 ps
CPU time 28.11 seconds
Started Jul 03 04:35:18 PM PDT 24
Finished Jul 03 04:35:46 PM PDT 24
Peak memory 212352 kb
Host smart-80ddb724-abcb-4d28-9c64-c0bcefef1e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040334400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4040334400
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1295482867
Short name T196
Test name
Test status
Simulation time 1925192317 ps
CPU time 16.56 seconds
Started Jul 03 04:35:19 PM PDT 24
Finished Jul 03 04:35:36 PM PDT 24
Peak memory 211324 kb
Host smart-8aaa64cc-ec11-4d62-bfa5-a38b8e49f66d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295482867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1295482867
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4235115655
Short name T220
Test name
Test status
Simulation time 5265294085 ps
CPU time 26.76 seconds
Started Jul 03 04:35:19 PM PDT 24
Finished Jul 03 04:35:46 PM PDT 24
Peak memory 213624 kb
Host smart-2b0840c4-f5f6-4d65-805e-4a531b302a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235115655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4235115655
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1535425814
Short name T323
Test name
Test status
Simulation time 26855434790 ps
CPU time 89.63 seconds
Started Jul 03 04:35:22 PM PDT 24
Finished Jul 03 04:36:52 PM PDT 24
Peak memory 219404 kb
Host smart-eb815e5a-c5db-4180-ab12-c51bbf87579e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535425814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1535425814
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2699187231
Short name T282
Test name
Test status
Simulation time 382494592 ps
CPU time 6.75 seconds
Started Jul 03 04:35:22 PM PDT 24
Finished Jul 03 04:35:29 PM PDT 24
Peak memory 211300 kb
Host smart-76394bdf-d841-467e-8cd2-ad77198b60d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699187231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2699187231
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3829188576
Short name T359
Test name
Test status
Simulation time 17255381877 ps
CPU time 31.52 seconds
Started Jul 03 04:35:22 PM PDT 24
Finished Jul 03 04:35:54 PM PDT 24
Peak memory 212240 kb
Host smart-6efa6acd-b995-47da-a6bc-dba3f8df4473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829188576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3829188576
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1292089656
Short name T208
Test name
Test status
Simulation time 379133898 ps
CPU time 5.46 seconds
Started Jul 03 04:35:20 PM PDT 24
Finished Jul 03 04:35:26 PM PDT 24
Peak memory 211312 kb
Host smart-0a54cabf-787c-445d-8681-a032507d4d52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292089656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1292089656
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3408177344
Short name T234
Test name
Test status
Simulation time 6184848245 ps
CPU time 31.17 seconds
Started Jul 03 04:35:18 PM PDT 24
Finished Jul 03 04:35:50 PM PDT 24
Peak memory 214420 kb
Host smart-f4941838-4f33-402c-b921-974070312799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408177344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3408177344
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3293237980
Short name T246
Test name
Test status
Simulation time 7540537488 ps
CPU time 32.57 seconds
Started Jul 03 04:35:18 PM PDT 24
Finished Jul 03 04:35:51 PM PDT 24
Peak memory 214232 kb
Host smart-275d520d-ccf5-437b-a753-394698f45888
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293237980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3293237980
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.50613577
Short name T277
Test name
Test status
Simulation time 1183448542 ps
CPU time 4.24 seconds
Started Jul 03 04:35:23 PM PDT 24
Finished Jul 03 04:35:27 PM PDT 24
Peak memory 211208 kb
Host smart-43d032b3-9304-4a78-bd88-21a98b3986ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50613577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.50613577
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3089068434
Short name T193
Test name
Test status
Simulation time 16051321201 ps
CPU time 165.29 seconds
Started Jul 03 04:35:23 PM PDT 24
Finished Jul 03 04:38:08 PM PDT 24
Peak memory 233660 kb
Host smart-82a4e9fd-1614-4704-9181-9f85abacdc97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089068434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3089068434
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2404525208
Short name T172
Test name
Test status
Simulation time 4836969417 ps
CPU time 24.08 seconds
Started Jul 03 04:35:22 PM PDT 24
Finished Jul 03 04:35:46 PM PDT 24
Peak memory 212124 kb
Host smart-2211b5fe-8335-4a0c-a802-d2c8533133a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404525208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2404525208
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.540883946
Short name T130
Test name
Test status
Simulation time 1267506383 ps
CPU time 5.2 seconds
Started Jul 03 04:35:22 PM PDT 24
Finished Jul 03 04:35:27 PM PDT 24
Peak memory 211316 kb
Host smart-a023e503-8d7a-44fd-8fa9-d3c3df888d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540883946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.540883946
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.988751425
Short name T154
Test name
Test status
Simulation time 4174343681 ps
CPU time 33.09 seconds
Started Jul 03 04:35:21 PM PDT 24
Finished Jul 03 04:35:54 PM PDT 24
Peak memory 213448 kb
Host smart-6ea7f5c5-616a-473f-9d90-dc45d9db6c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988751425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.988751425
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.171143545
Short name T1
Test name
Test status
Simulation time 40499315788 ps
CPU time 60.83 seconds
Started Jul 03 04:35:22 PM PDT 24
Finished Jul 03 04:36:23 PM PDT 24
Peak memory 217244 kb
Host smart-1f97c06f-3c04-4252-8ef6-a752b9e13865
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171143545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.171143545
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.695779493
Short name T331
Test name
Test status
Simulation time 6716865023 ps
CPU time 13.67 seconds
Started Jul 03 04:35:28 PM PDT 24
Finished Jul 03 04:35:42 PM PDT 24
Peak memory 211352 kb
Host smart-8579e5ec-9d67-4993-8b4e-c962a64bb168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695779493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.695779493
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3210736678
Short name T216
Test name
Test status
Simulation time 86153551685 ps
CPU time 472.08 seconds
Started Jul 03 04:35:25 PM PDT 24
Finished Jul 03 04:43:17 PM PDT 24
Peak memory 236776 kb
Host smart-f464fc1a-170c-4d14-8cda-05c285134eef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210736678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3210736678
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.871878440
Short name T281
Test name
Test status
Simulation time 10263465667 ps
CPU time 24.62 seconds
Started Jul 03 04:35:30 PM PDT 24
Finished Jul 03 04:35:55 PM PDT 24
Peak memory 212772 kb
Host smart-3307b4c9-e412-43f0-b49a-69af02d43af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871878440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.871878440
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2205751351
Short name T211
Test name
Test status
Simulation time 35631941834 ps
CPU time 16.42 seconds
Started Jul 03 04:35:28 PM PDT 24
Finished Jul 03 04:35:45 PM PDT 24
Peak memory 211388 kb
Host smart-1e4ec9f3-6c2a-4d12-af51-a528d273dc99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205751351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2205751351
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.917198724
Short name T184
Test name
Test status
Simulation time 6484035484 ps
CPU time 23.93 seconds
Started Jul 03 04:35:21 PM PDT 24
Finished Jul 03 04:35:45 PM PDT 24
Peak memory 213864 kb
Host smart-0cd6f207-7c34-41d3-9ed4-61137f25762b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917198724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.917198724
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2107831272
Short name T287
Test name
Test status
Simulation time 6246894507 ps
CPU time 17.96 seconds
Started Jul 03 04:35:27 PM PDT 24
Finished Jul 03 04:35:45 PM PDT 24
Peak memory 214104 kb
Host smart-57b7e240-b6af-40b5-8217-34c188da68f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107831272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2107831272
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.203159153
Short name T192
Test name
Test status
Simulation time 87515393 ps
CPU time 4.27 seconds
Started Jul 03 04:35:27 PM PDT 24
Finished Jul 03 04:35:32 PM PDT 24
Peak memory 211328 kb
Host smart-30b32815-544f-4641-aaf0-d5f28c304365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203159153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.203159153
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.932767786
Short name T275
Test name
Test status
Simulation time 46020294123 ps
CPU time 127.55 seconds
Started Jul 03 04:35:27 PM PDT 24
Finished Jul 03 04:37:35 PM PDT 24
Peak memory 228356 kb
Host smart-e38d8117-ea3d-4edd-a023-773863f0c832
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932767786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.932767786
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.474440513
Short name T141
Test name
Test status
Simulation time 2757141668 ps
CPU time 13.95 seconds
Started Jul 03 04:35:26 PM PDT 24
Finished Jul 03 04:35:40 PM PDT 24
Peak memory 212028 kb
Host smart-a6d8d8bc-bed9-4cd3-ab44-c138c34b66dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474440513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.474440513
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1253408114
Short name T206
Test name
Test status
Simulation time 1544414797 ps
CPU time 13.12 seconds
Started Jul 03 04:35:28 PM PDT 24
Finished Jul 03 04:35:41 PM PDT 24
Peak memory 211260 kb
Host smart-cc0fecd9-38f4-47e3-b795-522cd282bc7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1253408114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1253408114
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1502067393
Short name T204
Test name
Test status
Simulation time 5213447055 ps
CPU time 38.21 seconds
Started Jul 03 04:35:27 PM PDT 24
Finished Jul 03 04:36:06 PM PDT 24
Peak memory 213312 kb
Host smart-af028a93-f8ab-4e91-91d2-6e5176522fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502067393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1502067393
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1533933164
Short name T218
Test name
Test status
Simulation time 63094139833 ps
CPU time 82.3 seconds
Started Jul 03 04:35:26 PM PDT 24
Finished Jul 03 04:36:49 PM PDT 24
Peak memory 219292 kb
Host smart-3979ba70-b0d9-4cc5-ae35-a2af8d42c4cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533933164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1533933164
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.618498909
Short name T91
Test name
Test status
Simulation time 69728310094 ps
CPU time 2445.12 seconds
Started Jul 03 04:35:28 PM PDT 24
Finished Jul 03 05:16:14 PM PDT 24
Peak memory 235820 kb
Host smart-bff81e7a-2299-4138-9f9f-267a7edc258e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618498909 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.618498909
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.89892552
Short name T360
Test name
Test status
Simulation time 986684466 ps
CPU time 10.36 seconds
Started Jul 03 04:34:58 PM PDT 24
Finished Jul 03 04:35:09 PM PDT 24
Peak memory 211264 kb
Host smart-4d7735af-3ee2-429a-8870-5c1335a4ebb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89892552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.89892552
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.824796012
Short name T253
Test name
Test status
Simulation time 108693333696 ps
CPU time 292.15 seconds
Started Jul 03 04:34:53 PM PDT 24
Finished Jul 03 04:39:46 PM PDT 24
Peak memory 237820 kb
Host smart-0ef4b7e6-7b22-4028-a9d0-d1a05e5e8d5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824796012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.824796012
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2742538965
Short name T146
Test name
Test status
Simulation time 4165599184 ps
CPU time 31.85 seconds
Started Jul 03 04:34:54 PM PDT 24
Finished Jul 03 04:35:26 PM PDT 24
Peak memory 211956 kb
Host smart-ee50f10f-e9e5-4836-8de4-15a65c37bac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742538965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2742538965
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2957889719
Short name T198
Test name
Test status
Simulation time 96385316 ps
CPU time 5.85 seconds
Started Jul 03 04:34:57 PM PDT 24
Finished Jul 03 04:35:03 PM PDT 24
Peak memory 211388 kb
Host smart-ecbf1521-5e84-4164-8fac-5cd454bd4725
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957889719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2957889719
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4255866145
Short name T26
Test name
Test status
Simulation time 141235855 ps
CPU time 50.54 seconds
Started Jul 03 04:34:58 PM PDT 24
Finished Jul 03 04:35:49 PM PDT 24
Peak memory 235636 kb
Host smart-4c8e9dd7-53c0-43e8-b72b-6082d022e141
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255866145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4255866145
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3487330783
Short name T120
Test name
Test status
Simulation time 13024705321 ps
CPU time 30.06 seconds
Started Jul 03 04:34:54 PM PDT 24
Finished Jul 03 04:35:25 PM PDT 24
Peak memory 213920 kb
Host smart-3d7a52f6-7a50-4eb2-ba47-af8b319a29e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487330783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3487330783
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3352036866
Short name T34
Test name
Test status
Simulation time 1199602221 ps
CPU time 14.21 seconds
Started Jul 03 04:34:54 PM PDT 24
Finished Jul 03 04:35:09 PM PDT 24
Peak memory 211176 kb
Host smart-faddeaa0-f4e1-43a9-bdc3-ba087f8b9eff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352036866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3352036866
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3577231677
Short name T50
Test name
Test status
Simulation time 32286263795 ps
CPU time 4611.91 seconds
Started Jul 03 04:34:54 PM PDT 24
Finished Jul 03 05:51:47 PM PDT 24
Peak memory 229792 kb
Host smart-806cc511-2e24-4d39-b736-1ed30db016a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577231677 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3577231677
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1688179633
Short name T233
Test name
Test status
Simulation time 13074262052 ps
CPU time 8.87 seconds
Started Jul 03 04:35:30 PM PDT 24
Finished Jul 03 04:35:39 PM PDT 24
Peak memory 211400 kb
Host smart-5c5a3d13-5403-4ff9-835e-306be08ec6d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688179633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1688179633
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.292375680
Short name T39
Test name
Test status
Simulation time 6724030936 ps
CPU time 147.51 seconds
Started Jul 03 04:35:29 PM PDT 24
Finished Jul 03 04:37:57 PM PDT 24
Peak memory 237596 kb
Host smart-4fb1a6df-9369-44cb-8c5e-56470b3cf02b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292375680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.292375680
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2326524555
Short name T144
Test name
Test status
Simulation time 723390648 ps
CPU time 9.73 seconds
Started Jul 03 04:35:38 PM PDT 24
Finished Jul 03 04:35:48 PM PDT 24
Peak memory 212032 kb
Host smart-e0be5bb0-df68-427b-aaf3-eaf60c4a0763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326524555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2326524555
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3949321811
Short name T178
Test name
Test status
Simulation time 1324016336 ps
CPU time 13.56 seconds
Started Jul 03 04:35:30 PM PDT 24
Finished Jul 03 04:35:44 PM PDT 24
Peak memory 211356 kb
Host smart-0447de91-a738-48d4-99c7-170cb1880ec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949321811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3949321811
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.39961024
Short name T98
Test name
Test status
Simulation time 5392123495 ps
CPU time 18.98 seconds
Started Jul 03 04:35:31 PM PDT 24
Finished Jul 03 04:35:51 PM PDT 24
Peak memory 213888 kb
Host smart-3b46385a-9a8e-4053-ae6c-61d29d68816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39961024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.39961024
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.365883543
Short name T185
Test name
Test status
Simulation time 252287535 ps
CPU time 14 seconds
Started Jul 03 04:35:32 PM PDT 24
Finished Jul 03 04:35:47 PM PDT 24
Peak memory 213172 kb
Host smart-feb020c1-97d7-41bf-bd1a-ce1b82b8ce26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365883543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.365883543
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.904547691
Short name T59
Test name
Test status
Simulation time 1561236041 ps
CPU time 13.24 seconds
Started Jul 03 04:35:31 PM PDT 24
Finished Jul 03 04:35:45 PM PDT 24
Peak memory 211252 kb
Host smart-a1548591-90ea-433c-8786-916059f2b36f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904547691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.904547691
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2755773857
Short name T268
Test name
Test status
Simulation time 3483253265 ps
CPU time 29.31 seconds
Started Jul 03 04:35:39 PM PDT 24
Finished Jul 03 04:36:08 PM PDT 24
Peak memory 212076 kb
Host smart-a74fc952-eb5d-4bae-bfd2-446a2de355bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755773857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2755773857
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1145510120
Short name T160
Test name
Test status
Simulation time 649464561 ps
CPU time 9.41 seconds
Started Jul 03 04:35:30 PM PDT 24
Finished Jul 03 04:35:40 PM PDT 24
Peak memory 211320 kb
Host smart-facb44ae-5059-46c8-9133-6325a32ea7c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145510120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1145510120
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.4115787611
Short name T347
Test name
Test status
Simulation time 14281326028 ps
CPU time 28.19 seconds
Started Jul 03 04:35:31 PM PDT 24
Finished Jul 03 04:36:00 PM PDT 24
Peak memory 213916 kb
Host smart-3719bd63-c8f8-4a81-89e5-4e870f5c2357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115787611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.4115787611
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3059719151
Short name T71
Test name
Test status
Simulation time 23402560725 ps
CPU time 62.91 seconds
Started Jul 03 04:35:31 PM PDT 24
Finished Jul 03 04:36:34 PM PDT 24
Peak memory 219348 kb
Host smart-eddf0b60-d741-41ac-b5c0-3ef6e562aa12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059719151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3059719151
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.347733869
Short name T56
Test name
Test status
Simulation time 1422536303 ps
CPU time 12.17 seconds
Started Jul 03 04:35:32 PM PDT 24
Finished Jul 03 04:35:45 PM PDT 24
Peak memory 211280 kb
Host smart-507c5f67-4718-4108-ac12-87f98011c236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347733869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.347733869
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.404596149
Short name T322
Test name
Test status
Simulation time 5242088353 ps
CPU time 70.1 seconds
Started Jul 03 04:35:30 PM PDT 24
Finished Jul 03 04:36:40 PM PDT 24
Peak memory 212556 kb
Host smart-d37778b5-694b-475b-bb7e-8ab86a5f58e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404596149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.404596149
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3778562019
Short name T285
Test name
Test status
Simulation time 3817194914 ps
CPU time 30.23 seconds
Started Jul 03 04:35:36 PM PDT 24
Finished Jul 03 04:36:06 PM PDT 24
Peak memory 212468 kb
Host smart-64efc8ba-d0a5-4f46-b3aa-a0e98d4bc644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778562019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3778562019
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.280603771
Short name T252
Test name
Test status
Simulation time 233008406 ps
CPU time 6.99 seconds
Started Jul 03 04:35:31 PM PDT 24
Finished Jul 03 04:35:38 PM PDT 24
Peak memory 211336 kb
Host smart-fb0eafe2-0fb2-42da-ba3a-db5b92f65312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280603771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.280603771
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.418194818
Short name T165
Test name
Test status
Simulation time 4342784046 ps
CPU time 33.66 seconds
Started Jul 03 04:35:32 PM PDT 24
Finished Jul 03 04:36:06 PM PDT 24
Peak memory 214284 kb
Host smart-1c3a44d6-1051-4458-ac60-f312217303a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418194818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.418194818
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1139211197
Short name T95
Test name
Test status
Simulation time 13208138230 ps
CPU time 60.64 seconds
Started Jul 03 04:35:31 PM PDT 24
Finished Jul 03 04:36:32 PM PDT 24
Peak memory 218096 kb
Host smart-efa7b105-181f-4d6c-83de-1a351cebed9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139211197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1139211197
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.682516861
Short name T190
Test name
Test status
Simulation time 86325117 ps
CPU time 4.21 seconds
Started Jul 03 04:35:37 PM PDT 24
Finished Jul 03 04:35:41 PM PDT 24
Peak memory 211284 kb
Host smart-82208b62-f5e8-4b47-8633-5ef68a60a28b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682516861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.682516861
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3833380896
Short name T271
Test name
Test status
Simulation time 70696098202 ps
CPU time 218.23 seconds
Started Jul 03 04:35:35 PM PDT 24
Finished Jul 03 04:39:14 PM PDT 24
Peak memory 237764 kb
Host smart-26755bf7-37aa-489c-b511-90af86203936
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833380896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3833380896
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.41979134
Short name T25
Test name
Test status
Simulation time 3503781832 ps
CPU time 26.97 seconds
Started Jul 03 04:35:35 PM PDT 24
Finished Jul 03 04:36:02 PM PDT 24
Peak memory 211832 kb
Host smart-007b25eb-3e4b-406e-807f-6d2ad5359d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41979134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.41979134
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2919412724
Short name T11
Test name
Test status
Simulation time 1409498403 ps
CPU time 12.79 seconds
Started Jul 03 04:35:32 PM PDT 24
Finished Jul 03 04:35:45 PM PDT 24
Peak memory 211324 kb
Host smart-c4e029a7-e73e-4d88-a535-ee5fe13d671f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919412724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2919412724
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1402962791
Short name T142
Test name
Test status
Simulation time 4232242083 ps
CPU time 34.19 seconds
Started Jul 03 04:35:32 PM PDT 24
Finished Jul 03 04:36:07 PM PDT 24
Peak memory 213184 kb
Host smart-ba978b9b-85d9-4d1b-a742-d3eaa1909a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402962791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1402962791
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3039964802
Short name T212
Test name
Test status
Simulation time 1966016528 ps
CPU time 25.12 seconds
Started Jul 03 04:35:32 PM PDT 24
Finished Jul 03 04:35:58 PM PDT 24
Peak memory 215928 kb
Host smart-83189390-3038-48d9-a6e3-530faa3ba72a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039964802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3039964802
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3441160175
Short name T259
Test name
Test status
Simulation time 1503348834 ps
CPU time 6.6 seconds
Started Jul 03 04:35:35 PM PDT 24
Finished Jul 03 04:35:42 PM PDT 24
Peak memory 211332 kb
Host smart-ee975bf4-085d-4ee1-bceb-d62d97db1144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441160175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3441160175
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.218390390
Short name T166
Test name
Test status
Simulation time 227617883501 ps
CPU time 298.82 seconds
Started Jul 03 04:35:34 PM PDT 24
Finished Jul 03 04:40:34 PM PDT 24
Peak memory 231912 kb
Host smart-8fe4fefc-b6e2-4f9d-976f-229459500874
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218390390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.218390390
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1902150157
Short name T348
Test name
Test status
Simulation time 17427638749 ps
CPU time 35.26 seconds
Started Jul 03 04:35:36 PM PDT 24
Finished Jul 03 04:36:12 PM PDT 24
Peak memory 212072 kb
Host smart-01077481-a456-45df-9fa3-b6c415148c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902150157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1902150157
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3049157654
Short name T307
Test name
Test status
Simulation time 7729509831 ps
CPU time 15.84 seconds
Started Jul 03 04:35:35 PM PDT 24
Finished Jul 03 04:35:51 PM PDT 24
Peak memory 211428 kb
Host smart-76329a49-a40a-4f7c-8e25-c1bda48a4f4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049157654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3049157654
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3271923997
Short name T356
Test name
Test status
Simulation time 7579968529 ps
CPU time 21.26 seconds
Started Jul 03 04:35:36 PM PDT 24
Finished Jul 03 04:35:58 PM PDT 24
Peak memory 214496 kb
Host smart-f77a60b9-d14e-4a14-8004-8a34b32be3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271923997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3271923997
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.612005186
Short name T321
Test name
Test status
Simulation time 14540474521 ps
CPU time 32.15 seconds
Started Jul 03 04:35:35 PM PDT 24
Finished Jul 03 04:36:08 PM PDT 24
Peak memory 214884 kb
Host smart-1364ab47-baf2-40db-908c-8a3b60caead1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612005186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.612005186
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.174385949
Short name T58
Test name
Test status
Simulation time 320667458 ps
CPU time 4.39 seconds
Started Jul 03 04:35:41 PM PDT 24
Finished Jul 03 04:35:46 PM PDT 24
Peak memory 211288 kb
Host smart-3adf65de-740a-4ba7-924c-abde40ae6bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174385949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.174385949
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3008340412
Short name T303
Test name
Test status
Simulation time 67226325208 ps
CPU time 289.83 seconds
Started Jul 03 04:35:39 PM PDT 24
Finished Jul 03 04:40:29 PM PDT 24
Peak memory 212548 kb
Host smart-c4c7cc16-621c-4183-9b6b-c36af4201282
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008340412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3008340412
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.375051180
Short name T189
Test name
Test status
Simulation time 7281612466 ps
CPU time 21.06 seconds
Started Jul 03 04:35:40 PM PDT 24
Finished Jul 03 04:36:02 PM PDT 24
Peak memory 211400 kb
Host smart-ed5a9a72-39c4-4767-98be-379be6f7f791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375051180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.375051180
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1573759198
Short name T129
Test name
Test status
Simulation time 7778649468 ps
CPU time 16.15 seconds
Started Jul 03 04:35:40 PM PDT 24
Finished Jul 03 04:35:57 PM PDT 24
Peak memory 211312 kb
Host smart-76dc59a5-660b-4081-9dac-f196d87d4a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573759198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1573759198
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2537352891
Short name T327
Test name
Test status
Simulation time 15970325391 ps
CPU time 25.48 seconds
Started Jul 03 04:35:36 PM PDT 24
Finished Jul 03 04:36:01 PM PDT 24
Peak memory 214068 kb
Host smart-c1d703af-3111-4333-85ce-75eaeea72757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537352891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2537352891
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4083979633
Short name T338
Test name
Test status
Simulation time 50465450375 ps
CPU time 78.3 seconds
Started Jul 03 04:35:40 PM PDT 24
Finished Jul 03 04:36:59 PM PDT 24
Peak memory 216672 kb
Host smart-fcf30749-0b51-403e-80a2-e634618183d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083979633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4083979633
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2970537030
Short name T22
Test name
Test status
Simulation time 168309365 ps
CPU time 4.17 seconds
Started Jul 03 04:35:41 PM PDT 24
Finished Jul 03 04:35:45 PM PDT 24
Peak memory 211256 kb
Host smart-58b251ee-3ef6-4dd2-8955-f98ccf4da14c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970537030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2970537030
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1244307391
Short name T269
Test name
Test status
Simulation time 15986838389 ps
CPU time 192.28 seconds
Started Jul 03 04:35:42 PM PDT 24
Finished Jul 03 04:38:54 PM PDT 24
Peak memory 212500 kb
Host smart-e40b580a-c105-4f78-b107-5f9cc19eadb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244307391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1244307391
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.516184898
Short name T137
Test name
Test status
Simulation time 7101206143 ps
CPU time 28.01 seconds
Started Jul 03 04:35:39 PM PDT 24
Finished Jul 03 04:36:07 PM PDT 24
Peak memory 212504 kb
Host smart-c7a1b08b-393a-48c0-9147-4f6a02156d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516184898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.516184898
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3535353869
Short name T332
Test name
Test status
Simulation time 1231084365 ps
CPU time 12.17 seconds
Started Jul 03 04:35:39 PM PDT 24
Finished Jul 03 04:35:51 PM PDT 24
Peak memory 211288 kb
Host smart-f8bbb0cb-fa9e-4224-9dbd-84507a08bb11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3535353869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3535353869
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.475018475
Short name T226
Test name
Test status
Simulation time 8538611736 ps
CPU time 25.7 seconds
Started Jul 03 04:35:41 PM PDT 24
Finished Jul 03 04:36:07 PM PDT 24
Peak memory 213940 kb
Host smart-f29ce8b4-f85c-49ce-84c1-9b97704e3908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475018475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.475018475
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3531949460
Short name T74
Test name
Test status
Simulation time 4302402661 ps
CPU time 27.61 seconds
Started Jul 03 04:35:40 PM PDT 24
Finished Jul 03 04:36:08 PM PDT 24
Peak memory 213384 kb
Host smart-42164981-e70d-48c6-8ede-e8b19391358c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531949460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3531949460
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2734771813
Short name T353
Test name
Test status
Simulation time 128581946 ps
CPU time 4.17 seconds
Started Jul 03 04:35:43 PM PDT 24
Finished Jul 03 04:35:47 PM PDT 24
Peak memory 211276 kb
Host smart-733ee40a-849e-4d9c-b609-9b67825a00ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734771813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2734771813
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1749594736
Short name T236
Test name
Test status
Simulation time 1375026317 ps
CPU time 79.55 seconds
Started Jul 03 04:35:40 PM PDT 24
Finished Jul 03 04:37:00 PM PDT 24
Peak memory 237716 kb
Host smart-67e88e59-a235-402c-88e5-d6c3a460f3de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749594736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1749594736
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2898340463
Short name T267
Test name
Test status
Simulation time 1550679333 ps
CPU time 18.65 seconds
Started Jul 03 04:35:40 PM PDT 24
Finished Jul 03 04:35:59 PM PDT 24
Peak memory 212148 kb
Host smart-9a541d05-00f7-45a7-8d38-39c6ffa78a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898340463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2898340463
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1926548192
Short name T242
Test name
Test status
Simulation time 1115066156 ps
CPU time 12.27 seconds
Started Jul 03 04:35:42 PM PDT 24
Finished Jul 03 04:35:54 PM PDT 24
Peak memory 211332 kb
Host smart-e8bf4bf2-1e82-412e-95fc-4c73e14a6cd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1926548192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1926548192
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3809448511
Short name T175
Test name
Test status
Simulation time 22101908062 ps
CPU time 37.47 seconds
Started Jul 03 04:35:39 PM PDT 24
Finished Jul 03 04:36:17 PM PDT 24
Peak memory 214560 kb
Host smart-af63f240-6870-490a-8f53-637f0b2747a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809448511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3809448511
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1832418266
Short name T289
Test name
Test status
Simulation time 1195325907 ps
CPU time 16.83 seconds
Started Jul 03 04:35:40 PM PDT 24
Finished Jul 03 04:35:57 PM PDT 24
Peak memory 213900 kb
Host smart-304ca801-daf4-4418-b655-857ce8febbc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832418266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1832418266
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3012828690
Short name T326
Test name
Test status
Simulation time 2395670468 ps
CPU time 11.45 seconds
Started Jul 03 04:35:45 PM PDT 24
Finished Jul 03 04:35:57 PM PDT 24
Peak memory 211400 kb
Host smart-41cf2109-b9c5-437e-a575-cc5968dee800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012828690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3012828690
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.641782490
Short name T343
Test name
Test status
Simulation time 278524752926 ps
CPU time 420.9 seconds
Started Jul 03 04:35:43 PM PDT 24
Finished Jul 03 04:42:45 PM PDT 24
Peak memory 234260 kb
Host smart-510cd4bb-fc7c-44c8-b638-73cc51c124f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641782490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.641782490
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2428465548
Short name T128
Test name
Test status
Simulation time 3765775134 ps
CPU time 30.59 seconds
Started Jul 03 04:35:42 PM PDT 24
Finished Jul 03 04:36:13 PM PDT 24
Peak memory 212324 kb
Host smart-191d1732-de41-4b29-a802-390ed477b9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428465548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2428465548
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3860879542
Short name T245
Test name
Test status
Simulation time 1730254444 ps
CPU time 14.93 seconds
Started Jul 03 04:35:45 PM PDT 24
Finished Jul 03 04:36:00 PM PDT 24
Peak memory 211344 kb
Host smart-cf470e22-4631-4159-9171-02f99587a3d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860879542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3860879542
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.354286353
Short name T200
Test name
Test status
Simulation time 14904532834 ps
CPU time 23.31 seconds
Started Jul 03 04:35:43 PM PDT 24
Finished Jul 03 04:36:07 PM PDT 24
Peak memory 213944 kb
Host smart-19b1f670-6644-4083-afc0-b0ad65ca0174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354286353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.354286353
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3472983961
Short name T205
Test name
Test status
Simulation time 841148794 ps
CPU time 12.6 seconds
Started Jul 03 04:35:44 PM PDT 24
Finished Jul 03 04:35:57 PM PDT 24
Peak memory 211516 kb
Host smart-128aa9bd-dcb8-4918-aa65-67f6a2ff44f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472983961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3472983961
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2861802950
Short name T23
Test name
Test status
Simulation time 260441717 ps
CPU time 5.09 seconds
Started Jul 03 04:35:46 PM PDT 24
Finished Jul 03 04:35:51 PM PDT 24
Peak memory 211276 kb
Host smart-ef624e25-c489-4d68-9f45-239a87164c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861802950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2861802950
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.629914581
Short name T254
Test name
Test status
Simulation time 47311219602 ps
CPU time 198.01 seconds
Started Jul 03 04:35:45 PM PDT 24
Finished Jul 03 04:39:03 PM PDT 24
Peak memory 213364 kb
Host smart-25bfb0fc-93dd-4d4a-a949-38466e2040c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629914581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.629914581
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3946522649
Short name T28
Test name
Test status
Simulation time 341240372 ps
CPU time 9.45 seconds
Started Jul 03 04:35:45 PM PDT 24
Finished Jul 03 04:35:54 PM PDT 24
Peak memory 211856 kb
Host smart-96a68827-d478-40e4-a0be-2362501e4cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946522649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3946522649
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2679509067
Short name T191
Test name
Test status
Simulation time 784848019 ps
CPU time 10.36 seconds
Started Jul 03 04:35:46 PM PDT 24
Finished Jul 03 04:35:57 PM PDT 24
Peak memory 211324 kb
Host smart-52271e4b-44b2-468e-9781-12be714b0d64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679509067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2679509067
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1520844124
Short name T199
Test name
Test status
Simulation time 6205667104 ps
CPU time 21.78 seconds
Started Jul 03 04:35:43 PM PDT 24
Finished Jul 03 04:36:06 PM PDT 24
Peak memory 213536 kb
Host smart-8e075c53-5017-4f8d-a0ce-1a8ff4693418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520844124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1520844124
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.994028965
Short name T31
Test name
Test status
Simulation time 6666148028 ps
CPU time 61.36 seconds
Started Jul 03 04:35:43 PM PDT 24
Finished Jul 03 04:36:45 PM PDT 24
Peak memory 217088 kb
Host smart-9152aabf-a2bd-4b64-a59b-edf471488333
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994028965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.994028965
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3922304411
Short name T47
Test name
Test status
Simulation time 7565321189 ps
CPU time 267.25 seconds
Started Jul 03 04:35:45 PM PDT 24
Finished Jul 03 04:40:13 PM PDT 24
Peak memory 231628 kb
Host smart-c6bfac11-65c0-48cd-b830-4030f57f0637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922304411 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3922304411
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4254612763
Short name T290
Test name
Test status
Simulation time 725855069 ps
CPU time 8.73 seconds
Started Jul 03 04:34:58 PM PDT 24
Finished Jul 03 04:35:07 PM PDT 24
Peak memory 211276 kb
Host smart-4b9a624f-5605-4fbe-8dfc-46844ab83a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254612763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4254612763
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2318928313
Short name T159
Test name
Test status
Simulation time 19881814504 ps
CPU time 217.27 seconds
Started Jul 03 04:34:58 PM PDT 24
Finished Jul 03 04:38:36 PM PDT 24
Peak memory 236808 kb
Host smart-4040c994-b925-42aa-8850-4bbf7876a16e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318928313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2318928313
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3952989460
Short name T294
Test name
Test status
Simulation time 5601961572 ps
CPU time 18.73 seconds
Started Jul 03 04:35:00 PM PDT 24
Finished Jul 03 04:35:19 PM PDT 24
Peak memory 212112 kb
Host smart-da15be0e-c93e-4661-950f-bdfb24353739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952989460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3952989460
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.779788870
Short name T298
Test name
Test status
Simulation time 6466459104 ps
CPU time 15.75 seconds
Started Jul 03 04:35:00 PM PDT 24
Finished Jul 03 04:35:17 PM PDT 24
Peak memory 211320 kb
Host smart-ae5e9baa-4b66-4c2c-965f-d88f4473e39b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=779788870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.779788870
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3669475056
Short name T310
Test name
Test status
Simulation time 3311201557 ps
CPU time 17.22 seconds
Started Jul 03 04:34:58 PM PDT 24
Finished Jul 03 04:35:15 PM PDT 24
Peak memory 214588 kb
Host smart-e0ff0c66-a8e9-4bd3-af8c-c321d286929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669475056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3669475056
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.293361444
Short name T75
Test name
Test status
Simulation time 26169702267 ps
CPU time 72.61 seconds
Started Jul 03 04:34:59 PM PDT 24
Finished Jul 03 04:36:12 PM PDT 24
Peak memory 217736 kb
Host smart-3ff3fed9-65b8-44a9-861a-186442e069fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293361444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.293361444
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3010323373
Short name T283
Test name
Test status
Simulation time 1600502645 ps
CPU time 8.83 seconds
Started Jul 03 04:35:57 PM PDT 24
Finished Jul 03 04:36:07 PM PDT 24
Peak memory 211292 kb
Host smart-3a3c6f94-b994-482c-b174-b80c1c5fcd32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010323373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3010323373
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3148149734
Short name T125
Test name
Test status
Simulation time 2685607881 ps
CPU time 94.36 seconds
Started Jul 03 04:35:46 PM PDT 24
Finished Jul 03 04:37:21 PM PDT 24
Peak memory 237108 kb
Host smart-b2bb7a93-3d9f-4ef2-b626-e8bf705eedf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148149734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3148149734
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.618323057
Short name T132
Test name
Test status
Simulation time 2259466322 ps
CPU time 23.66 seconds
Started Jul 03 04:35:50 PM PDT 24
Finished Jul 03 04:36:14 PM PDT 24
Peak memory 211916 kb
Host smart-289d02c6-ca73-4515-899a-5e25706172fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618323057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.618323057
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.235228840
Short name T131
Test name
Test status
Simulation time 2159730289 ps
CPU time 17.13 seconds
Started Jul 03 04:35:55 PM PDT 24
Finished Jul 03 04:36:12 PM PDT 24
Peak memory 211396 kb
Host smart-16416c1c-8b70-4b88-80a1-0f7a15c281a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235228840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.235228840
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1925145601
Short name T346
Test name
Test status
Simulation time 1096356338 ps
CPU time 11.61 seconds
Started Jul 03 04:35:47 PM PDT 24
Finished Jul 03 04:35:59 PM PDT 24
Peak memory 212440 kb
Host smart-bd19102c-6af2-4549-8f5f-f9242c00de97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925145601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1925145601
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2148472105
Short name T203
Test name
Test status
Simulation time 534195464 ps
CPU time 6.86 seconds
Started Jul 03 04:35:49 PM PDT 24
Finished Jul 03 04:35:56 PM PDT 24
Peak memory 211200 kb
Host smart-1800f33e-c395-4c35-b1fa-3ee8486f7e55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148472105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2148472105
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1481693540
Short name T257
Test name
Test status
Simulation time 5400417135 ps
CPU time 9.84 seconds
Started Jul 03 04:35:55 PM PDT 24
Finished Jul 03 04:36:05 PM PDT 24
Peak memory 211364 kb
Host smart-dbd45078-bd14-4355-9bd6-a704931d5ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481693540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1481693540
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4124762192
Short name T334
Test name
Test status
Simulation time 157446010686 ps
CPU time 357.73 seconds
Started Jul 03 04:36:00 PM PDT 24
Finished Jul 03 04:41:58 PM PDT 24
Peak memory 212612 kb
Host smart-7177db74-fda3-4b9f-ae42-bc2fdbbcc360
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124762192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4124762192
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4117131353
Short name T149
Test name
Test status
Simulation time 3179251237 ps
CPU time 19.39 seconds
Started Jul 03 04:35:49 PM PDT 24
Finished Jul 03 04:36:08 PM PDT 24
Peak memory 212008 kb
Host smart-1bcf509a-08d7-4202-863e-f6a5abc085c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117131353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4117131353
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3519120625
Short name T295
Test name
Test status
Simulation time 2728142233 ps
CPU time 9.58 seconds
Started Jul 03 04:35:47 PM PDT 24
Finished Jul 03 04:35:57 PM PDT 24
Peak memory 211396 kb
Host smart-943fb5f7-b142-4500-802a-f6862895648d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519120625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3519120625
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.398883711
Short name T311
Test name
Test status
Simulation time 4266353850 ps
CPU time 43.48 seconds
Started Jul 03 04:35:47 PM PDT 24
Finished Jul 03 04:36:31 PM PDT 24
Peak memory 213528 kb
Host smart-1b5368ec-3f04-4d1c-9591-2106e3d9b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398883711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.398883711
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3745135527
Short name T239
Test name
Test status
Simulation time 577856285 ps
CPU time 11.9 seconds
Started Jul 03 04:35:59 PM PDT 24
Finished Jul 03 04:36:11 PM PDT 24
Peak memory 213564 kb
Host smart-98c11a48-e1fa-4c82-bea6-a19b431bf44c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745135527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3745135527
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2930607282
Short name T240
Test name
Test status
Simulation time 463009496 ps
CPU time 4.33 seconds
Started Jul 03 04:35:51 PM PDT 24
Finished Jul 03 04:35:56 PM PDT 24
Peak memory 211304 kb
Host smart-a90a4243-ed60-498d-b907-053460ec4db6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930607282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2930607282
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4248651774
Short name T296
Test name
Test status
Simulation time 27749895638 ps
CPU time 250.18 seconds
Started Jul 03 04:35:49 PM PDT 24
Finished Jul 03 04:40:00 PM PDT 24
Peak memory 237796 kb
Host smart-bed5273f-8bf3-4064-94f1-3ea7a720ee69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248651774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.4248651774
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.309258204
Short name T260
Test name
Test status
Simulation time 922568126 ps
CPU time 15.73 seconds
Started Jul 03 04:35:55 PM PDT 24
Finished Jul 03 04:36:11 PM PDT 24
Peak memory 211812 kb
Host smart-013d7ac2-4fea-4690-92f9-a669412a2013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309258204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.309258204
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1709982651
Short name T264
Test name
Test status
Simulation time 706965210 ps
CPU time 10.07 seconds
Started Jul 03 04:35:49 PM PDT 24
Finished Jul 03 04:35:59 PM PDT 24
Peak memory 211328 kb
Host smart-57dff2fb-9a2f-49dc-8f86-d650badc0107
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709982651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1709982651
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1882699785
Short name T174
Test name
Test status
Simulation time 2966630560 ps
CPU time 27.53 seconds
Started Jul 03 04:35:49 PM PDT 24
Finished Jul 03 04:36:17 PM PDT 24
Peak memory 213196 kb
Host smart-51572503-4025-4349-99d8-9d75f67eb26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882699785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1882699785
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3073110936
Short name T168
Test name
Test status
Simulation time 6968117265 ps
CPU time 72.15 seconds
Started Jul 03 04:35:49 PM PDT 24
Finished Jul 03 04:37:02 PM PDT 24
Peak memory 215336 kb
Host smart-493a0979-ddaf-4735-b017-5c2763b10e97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073110936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3073110936
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.536120897
Short name T223
Test name
Test status
Simulation time 88993197 ps
CPU time 4.29 seconds
Started Jul 03 04:35:53 PM PDT 24
Finished Jul 03 04:35:58 PM PDT 24
Peak memory 211256 kb
Host smart-c5995477-7499-4ba2-a924-ee70fdc18b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536120897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.536120897
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2134220726
Short name T225
Test name
Test status
Simulation time 25791376527 ps
CPU time 145.35 seconds
Started Jul 03 04:35:53 PM PDT 24
Finished Jul 03 04:38:19 PM PDT 24
Peak memory 234736 kb
Host smart-bccdf83d-2686-412e-b60a-22e542c2d16a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134220726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2134220726
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3388122048
Short name T229
Test name
Test status
Simulation time 5547967216 ps
CPU time 18.13 seconds
Started Jul 03 04:35:53 PM PDT 24
Finished Jul 03 04:36:11 PM PDT 24
Peak memory 212312 kb
Host smart-550a65e7-2282-4e8b-8c6e-52477225770e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388122048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3388122048
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2605559931
Short name T105
Test name
Test status
Simulation time 177675966 ps
CPU time 6.69 seconds
Started Jul 03 04:35:53 PM PDT 24
Finished Jul 03 04:36:00 PM PDT 24
Peak memory 211328 kb
Host smart-aded7efa-993d-48de-b752-fbd9e980dd33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605559931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2605559931
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.31096476
Short name T173
Test name
Test status
Simulation time 6413072171 ps
CPU time 32.01 seconds
Started Jul 03 04:35:54 PM PDT 24
Finished Jul 03 04:36:26 PM PDT 24
Peak memory 214340 kb
Host smart-44400040-76dc-467e-a6d1-7121bf7c82a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31096476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.31096476
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.726058361
Short name T235
Test name
Test status
Simulation time 928924767 ps
CPU time 12.29 seconds
Started Jul 03 04:35:52 PM PDT 24
Finished Jul 03 04:36:04 PM PDT 24
Peak memory 211208 kb
Host smart-c1188975-9be9-4069-9e12-2ca7c999fbc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726058361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.726058361
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2554833186
Short name T106
Test name
Test status
Simulation time 75696682862 ps
CPU time 2923.09 seconds
Started Jul 03 04:35:54 PM PDT 24
Finished Jul 03 05:24:37 PM PDT 24
Peak memory 243944 kb
Host smart-b52bffbb-a208-4d34-8e35-f982106a01df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554833186 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2554833186
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1233312727
Short name T57
Test name
Test status
Simulation time 688466892 ps
CPU time 8.45 seconds
Started Jul 03 04:35:53 PM PDT 24
Finished Jul 03 04:36:02 PM PDT 24
Peak memory 211220 kb
Host smart-9dbf6dda-31c3-455a-b63b-3d9776f2dbe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233312727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1233312727
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1204206369
Short name T293
Test name
Test status
Simulation time 118467782825 ps
CPU time 288.91 seconds
Started Jul 03 04:36:00 PM PDT 24
Finished Jul 03 04:40:49 PM PDT 24
Peak memory 228504 kb
Host smart-24609a29-4e9d-4080-936c-ee947383058f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204206369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1204206369
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3301229507
Short name T237
Test name
Test status
Simulation time 417410690 ps
CPU time 9.47 seconds
Started Jul 03 04:35:54 PM PDT 24
Finished Jul 03 04:36:04 PM PDT 24
Peak memory 211916 kb
Host smart-597f0cb7-4256-4964-9fa8-6a0241c74fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301229507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3301229507
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2802940359
Short name T262
Test name
Test status
Simulation time 1759329399 ps
CPU time 13.84 seconds
Started Jul 03 04:36:02 PM PDT 24
Finished Jul 03 04:36:17 PM PDT 24
Peak memory 211336 kb
Host smart-cebbdccd-bd2b-4a58-986e-adb1d17d1de3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802940359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2802940359
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2462742446
Short name T318
Test name
Test status
Simulation time 7758694922 ps
CPU time 28.29 seconds
Started Jul 03 04:35:52 PM PDT 24
Finished Jul 03 04:36:21 PM PDT 24
Peak memory 212524 kb
Host smart-ae94f337-51bc-414f-b7c6-38d866dfb3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462742446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2462742446
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2635298053
Short name T276
Test name
Test status
Simulation time 6752896889 ps
CPU time 26.57 seconds
Started Jul 03 04:36:02 PM PDT 24
Finished Jul 03 04:36:29 PM PDT 24
Peak memory 213944 kb
Host smart-70fee359-49a5-40d0-8333-83f99baf67e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635298053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2635298053
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.41534767
Short name T328
Test name
Test status
Simulation time 299006733 ps
CPU time 4.26 seconds
Started Jul 03 04:35:56 PM PDT 24
Finished Jul 03 04:36:01 PM PDT 24
Peak memory 211248 kb
Host smart-eed4a219-d9fe-4a17-902a-60250b5a26d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41534767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.41534767
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2718644750
Short name T251
Test name
Test status
Simulation time 7376531414 ps
CPU time 106.18 seconds
Started Jul 03 04:35:57 PM PDT 24
Finished Jul 03 04:37:44 PM PDT 24
Peak memory 237864 kb
Host smart-febdeaab-6240-4606-96f2-824bf490500e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718644750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2718644750
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2952398551
Short name T312
Test name
Test status
Simulation time 3788228142 ps
CPU time 32.69 seconds
Started Jul 03 04:35:58 PM PDT 24
Finished Jul 03 04:36:31 PM PDT 24
Peak memory 211924 kb
Host smart-e9f194c2-e455-4a7c-8e8c-26da347a3098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952398551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2952398551
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2458019868
Short name T119
Test name
Test status
Simulation time 1576962277 ps
CPU time 14.1 seconds
Started Jul 03 04:35:56 PM PDT 24
Finished Jul 03 04:36:10 PM PDT 24
Peak memory 211372 kb
Host smart-891f9c93-3430-4c98-b5c3-91f8f157998e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2458019868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2458019868
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3594837446
Short name T352
Test name
Test status
Simulation time 188010066 ps
CPU time 10.11 seconds
Started Jul 03 04:35:55 PM PDT 24
Finished Jul 03 04:36:06 PM PDT 24
Peak memory 213372 kb
Host smart-e8cc952b-2cb4-4328-b995-c68e0fc9073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594837446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3594837446
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1035113421
Short name T263
Test name
Test status
Simulation time 1150317226 ps
CPU time 14.63 seconds
Started Jul 03 04:35:54 PM PDT 24
Finished Jul 03 04:36:09 PM PDT 24
Peak memory 214756 kb
Host smart-24631dc4-3cb0-41c8-be4e-b4ee5f958e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035113421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1035113421
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3086874987
Short name T14
Test name
Test status
Simulation time 33932897135 ps
CPU time 486.28 seconds
Started Jul 03 04:35:55 PM PDT 24
Finished Jul 03 04:44:02 PM PDT 24
Peak memory 232880 kb
Host smart-582a6ba2-084f-41c5-890e-57a43518b281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086874987 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3086874987
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.988208843
Short name T180
Test name
Test status
Simulation time 690828138 ps
CPU time 5.82 seconds
Started Jul 03 04:35:56 PM PDT 24
Finished Jul 03 04:36:02 PM PDT 24
Peak memory 211220 kb
Host smart-327946ee-b80c-414b-80f5-f5e8b059f636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988208843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.988208843
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4183877199
Short name T222
Test name
Test status
Simulation time 36574356042 ps
CPU time 306.2 seconds
Started Jul 03 04:35:57 PM PDT 24
Finished Jul 03 04:41:03 PM PDT 24
Peak memory 212724 kb
Host smart-03cf40e9-ff6d-4748-9a78-a6184c6eb89b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183877199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4183877199
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.120939732
Short name T151
Test name
Test status
Simulation time 692983756 ps
CPU time 9.14 seconds
Started Jul 03 04:35:55 PM PDT 24
Finished Jul 03 04:36:05 PM PDT 24
Peak memory 211884 kb
Host smart-fffb498a-77ff-487e-b06b-70305a9283a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120939732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.120939732
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1092478804
Short name T300
Test name
Test status
Simulation time 4962053390 ps
CPU time 12.59 seconds
Started Jul 03 04:35:56 PM PDT 24
Finished Jul 03 04:36:09 PM PDT 24
Peak memory 211356 kb
Host smart-fec2065d-3ff0-40e6-8895-f9d78b9777bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1092478804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1092478804
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1442530177
Short name T121
Test name
Test status
Simulation time 1596066003 ps
CPU time 13.38 seconds
Started Jul 03 04:35:57 PM PDT 24
Finished Jul 03 04:36:10 PM PDT 24
Peak memory 213432 kb
Host smart-98965556-4e77-4118-9b37-2c434ed4de65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442530177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1442530177
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4243435236
Short name T150
Test name
Test status
Simulation time 8702456390 ps
CPU time 40.57 seconds
Started Jul 03 04:35:55 PM PDT 24
Finished Jul 03 04:36:36 PM PDT 24
Peak memory 215536 kb
Host smart-f1bc5f9a-82f0-4c9c-871b-6d98fcae67ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243435236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4243435236
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.741825255
Short name T163
Test name
Test status
Simulation time 23978361192 ps
CPU time 14.49 seconds
Started Jul 03 04:36:01 PM PDT 24
Finished Jul 03 04:36:16 PM PDT 24
Peak memory 211268 kb
Host smart-264b66ec-c046-400a-a2b9-74dd7f6a037e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741825255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.741825255
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2470939060
Short name T188
Test name
Test status
Simulation time 3292581279 ps
CPU time 28.92 seconds
Started Jul 03 04:36:01 PM PDT 24
Finished Jul 03 04:36:30 PM PDT 24
Peak memory 211432 kb
Host smart-74c500d9-3336-4090-af9f-7c79ee26fab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470939060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2470939060
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1035688302
Short name T357
Test name
Test status
Simulation time 2945404988 ps
CPU time 9.4 seconds
Started Jul 03 04:36:00 PM PDT 24
Finished Jul 03 04:36:10 PM PDT 24
Peak memory 211396 kb
Host smart-0e4aa6e1-8bb5-402d-868b-317e7e61b098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1035688302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1035688302
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3291655794
Short name T292
Test name
Test status
Simulation time 188517602 ps
CPU time 9.95 seconds
Started Jul 03 04:35:55 PM PDT 24
Finished Jul 03 04:36:06 PM PDT 24
Peak memory 213604 kb
Host smart-d9e9b857-67f8-4079-8e8f-8c4b5c749a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291655794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3291655794
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1822617781
Short name T329
Test name
Test status
Simulation time 482172519 ps
CPU time 27.66 seconds
Started Jul 03 04:35:55 PM PDT 24
Finished Jul 03 04:36:23 PM PDT 24
Peak memory 215576 kb
Host smart-aed7677e-e658-47b0-bb3e-f536d8647066
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822617781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1822617781
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2618793802
Short name T48
Test name
Test status
Simulation time 211389025120 ps
CPU time 1185.59 seconds
Started Jul 03 04:36:00 PM PDT 24
Finished Jul 03 04:55:46 PM PDT 24
Peak memory 235824 kb
Host smart-e85f36ad-29cb-40f4-a7fb-daefc2f7c2aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618793802 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2618793802
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1491994276
Short name T302
Test name
Test status
Simulation time 477946887 ps
CPU time 7.47 seconds
Started Jul 03 04:36:04 PM PDT 24
Finished Jul 03 04:36:11 PM PDT 24
Peak memory 211316 kb
Host smart-ad14da58-b293-467a-9510-d4480d97052c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491994276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1491994276
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1795930241
Short name T231
Test name
Test status
Simulation time 14623271608 ps
CPU time 230.89 seconds
Started Jul 03 04:36:05 PM PDT 24
Finished Jul 03 04:39:56 PM PDT 24
Peak memory 224592 kb
Host smart-a6c99e42-88e9-4c7f-a73d-dcf206610e7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795930241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1795930241
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1792765804
Short name T134
Test name
Test status
Simulation time 340303037 ps
CPU time 9.3 seconds
Started Jul 03 04:36:08 PM PDT 24
Finished Jul 03 04:36:18 PM PDT 24
Peak memory 211884 kb
Host smart-6dd918eb-a0c8-4d1b-b05f-4d687b6f1368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792765804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1792765804
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3343442569
Short name T305
Test name
Test status
Simulation time 7889314007 ps
CPU time 16.99 seconds
Started Jul 03 04:36:02 PM PDT 24
Finished Jul 03 04:36:19 PM PDT 24
Peak memory 211396 kb
Host smart-27e6d2c5-ece8-490f-be90-e476f3558261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343442569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3343442569
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1045588718
Short name T279
Test name
Test status
Simulation time 4244743909 ps
CPU time 31.23 seconds
Started Jul 03 04:36:08 PM PDT 24
Finished Jul 03 04:36:40 PM PDT 24
Peak memory 212840 kb
Host smart-536196ff-0758-4907-be91-07bc10537e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045588718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1045588718
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2602768956
Short name T127
Test name
Test status
Simulation time 3125759928 ps
CPU time 14.89 seconds
Started Jul 03 04:36:01 PM PDT 24
Finished Jul 03 04:36:16 PM PDT 24
Peak memory 211284 kb
Host smart-4d6615d0-ca01-42e5-abd9-db7c115c943d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602768956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2602768956
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3085785575
Short name T49
Test name
Test status
Simulation time 184676033672 ps
CPU time 7240.19 seconds
Started Jul 03 04:36:00 PM PDT 24
Finished Jul 03 06:36:42 PM PDT 24
Peak memory 232376 kb
Host smart-395aa000-89a7-4782-93b6-b2b57fc79fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085785575 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3085785575
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2054960699
Short name T153
Test name
Test status
Simulation time 1383070470 ps
CPU time 4.27 seconds
Started Jul 03 04:36:04 PM PDT 24
Finished Jul 03 04:36:08 PM PDT 24
Peak memory 211296 kb
Host smart-8f7d3e1c-c0c1-492a-84e6-5e7d84358059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054960699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2054960699
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3737250304
Short name T37
Test name
Test status
Simulation time 5061724934 ps
CPU time 170.63 seconds
Started Jul 03 04:36:02 PM PDT 24
Finished Jul 03 04:38:53 PM PDT 24
Peak memory 238016 kb
Host smart-04004578-8a5c-4a8c-a8ac-98d23ae9e645
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737250304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3737250304
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3004175113
Short name T330
Test name
Test status
Simulation time 11496306936 ps
CPU time 17.59 seconds
Started Jul 03 04:36:02 PM PDT 24
Finished Jul 03 04:36:20 PM PDT 24
Peak memory 212200 kb
Host smart-5cccd3b6-c419-4293-be0b-990c2a1befa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004175113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3004175113
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2069647432
Short name T145
Test name
Test status
Simulation time 8968006448 ps
CPU time 14.11 seconds
Started Jul 03 04:36:02 PM PDT 24
Finished Jul 03 04:36:16 PM PDT 24
Peak memory 211424 kb
Host smart-65413cdf-ebbb-4f14-b85d-9c7d05024766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2069647432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2069647432
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1270563456
Short name T265
Test name
Test status
Simulation time 2934319663 ps
CPU time 20.25 seconds
Started Jul 03 04:36:01 PM PDT 24
Finished Jul 03 04:36:21 PM PDT 24
Peak memory 213524 kb
Host smart-79785166-8c40-43ba-ae14-7b1732fc5307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270563456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1270563456
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.608568152
Short name T7
Test name
Test status
Simulation time 14962183361 ps
CPU time 39.47 seconds
Started Jul 03 04:36:04 PM PDT 24
Finished Jul 03 04:36:44 PM PDT 24
Peak memory 215072 kb
Host smart-7e43dfa7-971b-4008-9449-749fc82457a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608568152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.608568152
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.718366859
Short name T286
Test name
Test status
Simulation time 1377202124 ps
CPU time 4.3 seconds
Started Jul 03 04:35:03 PM PDT 24
Finished Jul 03 04:35:08 PM PDT 24
Peak memory 211292 kb
Host smart-71d7f5fb-1a86-45ca-8f6d-4cfc1fbc699b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718366859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.718366859
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1459905625
Short name T38
Test name
Test status
Simulation time 1854767979 ps
CPU time 126.46 seconds
Started Jul 03 04:35:04 PM PDT 24
Finished Jul 03 04:37:11 PM PDT 24
Peak memory 236756 kb
Host smart-03e42fe3-9408-42a8-bc9d-32177aaef4e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459905625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1459905625
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.276071041
Short name T202
Test name
Test status
Simulation time 2918682695 ps
CPU time 26 seconds
Started Jul 03 04:35:03 PM PDT 24
Finished Jul 03 04:35:29 PM PDT 24
Peak memory 212084 kb
Host smart-1b2c4857-452b-4a30-a96a-5784c80c1841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276071041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.276071041
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2574884796
Short name T104
Test name
Test status
Simulation time 2197404268 ps
CPU time 15.99 seconds
Started Jul 03 04:35:00 PM PDT 24
Finished Jul 03 04:35:17 PM PDT 24
Peak memory 211328 kb
Host smart-1141c3a2-ee0f-4365-891f-10729d4f16f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574884796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2574884796
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.584911817
Short name T17
Test name
Test status
Simulation time 3653617175 ps
CPU time 94.27 seconds
Started Jul 03 04:35:02 PM PDT 24
Finished Jul 03 04:36:37 PM PDT 24
Peak memory 250560 kb
Host smart-3ae49790-583b-4435-845d-97c73b42391f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584911817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.584911817
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1088247694
Short name T250
Test name
Test status
Simulation time 9890471270 ps
CPU time 24.59 seconds
Started Jul 03 04:34:58 PM PDT 24
Finished Jul 03 04:35:23 PM PDT 24
Peak memory 214264 kb
Host smart-dbb40445-9c9b-4604-b1e0-eb59e97c0c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088247694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1088247694
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2536501449
Short name T32
Test name
Test status
Simulation time 20621102068 ps
CPU time 66.76 seconds
Started Jul 03 04:34:57 PM PDT 24
Finished Jul 03 04:36:04 PM PDT 24
Peak memory 219368 kb
Host smart-6506c8ba-00e0-469d-8927-9b0c3049d295
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536501449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2536501449
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3409259653
Short name T161
Test name
Test status
Simulation time 175126357 ps
CPU time 4.08 seconds
Started Jul 03 04:36:06 PM PDT 24
Finished Jul 03 04:36:10 PM PDT 24
Peak memory 211280 kb
Host smart-727eba0d-a248-46ec-ae6a-fa96530c321e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409259653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3409259653
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3247943635
Short name T215
Test name
Test status
Simulation time 5098966779 ps
CPU time 186.43 seconds
Started Jul 03 04:36:04 PM PDT 24
Finished Jul 03 04:39:11 PM PDT 24
Peak memory 228520 kb
Host smart-dde8986f-af2a-4b01-a128-4e9d2d7394bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247943635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3247943635
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3676904806
Short name T187
Test name
Test status
Simulation time 1289576396 ps
CPU time 16.8 seconds
Started Jul 03 04:36:03 PM PDT 24
Finished Jul 03 04:36:20 PM PDT 24
Peak memory 212092 kb
Host smart-1510b2e0-3f92-4886-93d3-40b210d66b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676904806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3676904806
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2477760829
Short name T341
Test name
Test status
Simulation time 566952913 ps
CPU time 6.94 seconds
Started Jul 03 04:36:03 PM PDT 24
Finished Jul 03 04:36:10 PM PDT 24
Peak memory 211348 kb
Host smart-18eec14f-4daa-418f-9e49-39243ca5086b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477760829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2477760829
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2394896762
Short name T123
Test name
Test status
Simulation time 747621946 ps
CPU time 9.78 seconds
Started Jul 03 04:36:01 PM PDT 24
Finished Jul 03 04:36:11 PM PDT 24
Peak memory 213508 kb
Host smart-0631c2b7-0878-47a5-a06a-f008314683ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394896762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2394896762
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2483343074
Short name T124
Test name
Test status
Simulation time 23690003986 ps
CPU time 54 seconds
Started Jul 03 04:36:01 PM PDT 24
Finished Jul 03 04:36:56 PM PDT 24
Peak memory 217020 kb
Host smart-5da7b0ab-eb5e-4743-9c7c-7b00b1503aa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483343074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2483343074
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3131673522
Short name T344
Test name
Test status
Simulation time 3269316052 ps
CPU time 9.87 seconds
Started Jul 03 04:36:05 PM PDT 24
Finished Jul 03 04:36:15 PM PDT 24
Peak memory 211356 kb
Host smart-4aa7fff7-3f7a-4575-a2c3-99331026835c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131673522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3131673522
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.177058491
Short name T228
Test name
Test status
Simulation time 47513798915 ps
CPU time 440.44 seconds
Started Jul 03 04:36:04 PM PDT 24
Finished Jul 03 04:43:25 PM PDT 24
Peak memory 234868 kb
Host smart-bc4c304f-7506-4ec9-bb7a-dd4c6df9f539
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177058491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.177058491
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1549832266
Short name T186
Test name
Test status
Simulation time 665584796 ps
CPU time 9.51 seconds
Started Jul 03 04:36:05 PM PDT 24
Finished Jul 03 04:36:15 PM PDT 24
Peak memory 211828 kb
Host smart-fad10556-14b1-4f64-ae6e-9404f320b56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549832266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1549832266
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3466323603
Short name T337
Test name
Test status
Simulation time 96828556 ps
CPU time 5.37 seconds
Started Jul 03 04:36:08 PM PDT 24
Finished Jul 03 04:36:14 PM PDT 24
Peak memory 211308 kb
Host smart-be0663f8-a5cd-43c0-bf4b-7bd26a813072
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466323603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3466323603
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1331277943
Short name T126
Test name
Test status
Simulation time 3136388086 ps
CPU time 28.48 seconds
Started Jul 03 04:36:04 PM PDT 24
Finished Jul 03 04:36:32 PM PDT 24
Peak memory 213528 kb
Host smart-b9d5d64b-5ed0-4dba-b98f-11d31eeb9fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331277943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1331277943
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3929603107
Short name T33
Test name
Test status
Simulation time 10748682326 ps
CPU time 30.69 seconds
Started Jul 03 04:36:05 PM PDT 24
Finished Jul 03 04:36:36 PM PDT 24
Peak memory 213988 kb
Host smart-8a6d5829-7477-4463-913f-c1529b622274
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929603107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3929603107
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2913826933
Short name T46
Test name
Test status
Simulation time 135013906331 ps
CPU time 2258.74 seconds
Started Jul 03 04:36:08 PM PDT 24
Finished Jul 03 05:13:48 PM PDT 24
Peak memory 233180 kb
Host smart-f822fe77-4c9c-4e2e-ab95-720edef15d6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913826933 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2913826933
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2610392591
Short name T169
Test name
Test status
Simulation time 4084528672 ps
CPU time 8.58 seconds
Started Jul 03 04:36:08 PM PDT 24
Finished Jul 03 04:36:17 PM PDT 24
Peak memory 211296 kb
Host smart-9d485a63-ec51-48b5-af31-111254f5cc98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610392591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2610392591
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3669975701
Short name T319
Test name
Test status
Simulation time 9509279916 ps
CPU time 136.39 seconds
Started Jul 03 04:36:10 PM PDT 24
Finished Jul 03 04:38:27 PM PDT 24
Peak memory 228560 kb
Host smart-5f648b1d-3132-4cb8-8e7b-58c6fe5b02d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669975701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3669975701
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3800454473
Short name T342
Test name
Test status
Simulation time 7979921021 ps
CPU time 31.48 seconds
Started Jul 03 04:36:11 PM PDT 24
Finished Jul 03 04:36:43 PM PDT 24
Peak memory 212196 kb
Host smart-fb21b1fd-504f-4e95-91c0-46b9ac297078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800454473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3800454473
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2070311947
Short name T201
Test name
Test status
Simulation time 1708238133 ps
CPU time 8.39 seconds
Started Jul 03 04:36:10 PM PDT 24
Finished Jul 03 04:36:19 PM PDT 24
Peak memory 211324 kb
Host smart-79e23384-6b5d-47e6-bcb0-d518ddcdd29e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070311947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2070311947
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.907941434
Short name T72
Test name
Test status
Simulation time 370279979 ps
CPU time 10.28 seconds
Started Jul 03 04:36:01 PM PDT 24
Finished Jul 03 04:36:12 PM PDT 24
Peak memory 213808 kb
Host smart-9a2b9d26-3d71-4d2b-9063-b24a36ad22f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907941434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.907941434
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3760400423
Short name T197
Test name
Test status
Simulation time 11477161534 ps
CPU time 34.9 seconds
Started Jul 03 04:36:09 PM PDT 24
Finished Jul 03 04:36:44 PM PDT 24
Peak memory 214084 kb
Host smart-d9436b6b-3d1d-422c-9376-8cdebfc4041a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760400423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3760400423
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2139591136
Short name T209
Test name
Test status
Simulation time 6883996242 ps
CPU time 13.51 seconds
Started Jul 03 04:36:12 PM PDT 24
Finished Jul 03 04:36:26 PM PDT 24
Peak memory 211392 kb
Host smart-2c832c78-d5b7-4358-943f-c29b2bc4b8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139591136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2139591136
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2796356148
Short name T164
Test name
Test status
Simulation time 20377958952 ps
CPU time 143.18 seconds
Started Jul 03 04:36:13 PM PDT 24
Finished Jul 03 04:38:37 PM PDT 24
Peak memory 237532 kb
Host smart-6eb57bc0-4600-4bb9-a3db-32fbe41565b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796356148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2796356148
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3181345621
Short name T315
Test name
Test status
Simulation time 4496225363 ps
CPU time 13.18 seconds
Started Jul 03 04:36:15 PM PDT 24
Finished Jul 03 04:36:29 PM PDT 24
Peak memory 212304 kb
Host smart-0e55bf10-2848-4b44-b5e9-6107e28e166c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181345621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3181345621
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3102220842
Short name T355
Test name
Test status
Simulation time 6357992344 ps
CPU time 13.89 seconds
Started Jul 03 04:36:09 PM PDT 24
Finished Jul 03 04:36:24 PM PDT 24
Peak memory 211388 kb
Host smart-52b5f1f9-fd32-4fd3-8c97-a2f42615f3bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102220842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3102220842
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.480446391
Short name T155
Test name
Test status
Simulation time 1567184031 ps
CPU time 19.84 seconds
Started Jul 03 04:36:07 PM PDT 24
Finished Jul 03 04:36:28 PM PDT 24
Peak memory 213464 kb
Host smart-1c639278-4140-48d6-ad13-0a29f76a12b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480446391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.480446391
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2526579098
Short name T4
Test name
Test status
Simulation time 4963979766 ps
CPU time 17.95 seconds
Started Jul 03 04:36:09 PM PDT 24
Finished Jul 03 04:36:27 PM PDT 24
Peak memory 214844 kb
Host smart-debc0795-3900-4d67-b469-5ba42e020af1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526579098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2526579098
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2571269092
Short name T92
Test name
Test status
Simulation time 576488070 ps
CPU time 8.29 seconds
Started Jul 03 04:36:21 PM PDT 24
Finished Jul 03 04:36:29 PM PDT 24
Peak memory 211272 kb
Host smart-51fe6a0c-1202-482d-893a-87c545a1c3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571269092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2571269092
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3199966480
Short name T306
Test name
Test status
Simulation time 24530345498 ps
CPU time 149.16 seconds
Started Jul 03 04:36:12 PM PDT 24
Finished Jul 03 04:38:42 PM PDT 24
Peak memory 237820 kb
Host smart-49f80a7a-16cb-49c0-ae81-80109d1f1130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199966480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3199966480
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.90417733
Short name T152
Test name
Test status
Simulation time 692419881 ps
CPU time 9.41 seconds
Started Jul 03 04:36:12 PM PDT 24
Finished Jul 03 04:36:22 PM PDT 24
Peak memory 211948 kb
Host smart-773e7fd0-3525-4dbe-9cea-0d7a40a0799a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90417733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.90417733
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.520304077
Short name T139
Test name
Test status
Simulation time 1474936838 ps
CPU time 13.17 seconds
Started Jul 03 04:36:18 PM PDT 24
Finished Jul 03 04:36:31 PM PDT 24
Peak memory 211340 kb
Host smart-5c09ea6e-17dd-420d-911f-54d30e2af028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520304077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.520304077
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2857154107
Short name T249
Test name
Test status
Simulation time 1993697061 ps
CPU time 26.06 seconds
Started Jul 03 04:36:13 PM PDT 24
Finished Jul 03 04:36:39 PM PDT 24
Peak memory 213324 kb
Host smart-4ec457c6-fe59-47a9-a002-31b886a3525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857154107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2857154107
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1749257053
Short name T248
Test name
Test status
Simulation time 3613480731 ps
CPU time 34.7 seconds
Started Jul 03 04:36:14 PM PDT 24
Finished Jul 03 04:36:49 PM PDT 24
Peak memory 213776 kb
Host smart-dc083074-f329-418d-aef8-d0658cf24cac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749257053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1749257053
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3232034782
Short name T238
Test name
Test status
Simulation time 161728604 ps
CPU time 4.23 seconds
Started Jul 03 04:36:19 PM PDT 24
Finished Jul 03 04:36:23 PM PDT 24
Peak memory 211296 kb
Host smart-1ce6bc0f-32b8-47d9-ae8e-33c8b5cffc25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232034782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3232034782
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4092084880
Short name T325
Test name
Test status
Simulation time 9454999644 ps
CPU time 111.51 seconds
Started Jul 03 04:36:18 PM PDT 24
Finished Jul 03 04:38:10 PM PDT 24
Peak memory 228604 kb
Host smart-b05614c8-47b8-4ee0-9313-d5dc9d08c3e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092084880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4092084880
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2306853296
Short name T171
Test name
Test status
Simulation time 839505577 ps
CPU time 12.48 seconds
Started Jul 03 04:36:18 PM PDT 24
Finished Jul 03 04:36:31 PM PDT 24
Peak memory 211904 kb
Host smart-8c38b4e6-b7f5-4fc2-9f64-65f2f87a9efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306853296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2306853296
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3524311317
Short name T29
Test name
Test status
Simulation time 98940995 ps
CPU time 5.42 seconds
Started Jul 03 04:36:17 PM PDT 24
Finished Jul 03 04:36:23 PM PDT 24
Peak memory 211344 kb
Host smart-e133536a-7383-4003-90a2-3f949314c39a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524311317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3524311317
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1026641802
Short name T241
Test name
Test status
Simulation time 1528135141 ps
CPU time 19.91 seconds
Started Jul 03 04:36:15 PM PDT 24
Finished Jul 03 04:36:35 PM PDT 24
Peak memory 213372 kb
Host smart-2024cea9-471d-4189-9d73-7e0aede0d0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026641802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1026641802
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1044226035
Short name T299
Test name
Test status
Simulation time 2366299632 ps
CPU time 8.41 seconds
Started Jul 03 04:36:18 PM PDT 24
Finished Jul 03 04:36:27 PM PDT 24
Peak memory 211320 kb
Host smart-e9e3737e-7a9f-42b6-b214-526647ce536a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044226035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1044226035
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3836295889
Short name T93
Test name
Test status
Simulation time 1246674648 ps
CPU time 12.16 seconds
Started Jul 03 04:36:21 PM PDT 24
Finished Jul 03 04:36:34 PM PDT 24
Peak memory 211324 kb
Host smart-2911967b-b981-4550-be9b-7c8ad778a28a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836295889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3836295889
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2723995959
Short name T167
Test name
Test status
Simulation time 28466360100 ps
CPU time 157.65 seconds
Started Jul 03 04:36:23 PM PDT 24
Finished Jul 03 04:39:01 PM PDT 24
Peak memory 212568 kb
Host smart-eefbee12-4c63-4bbc-ba9f-159f7ae1f603
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723995959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2723995959
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1893140351
Short name T313
Test name
Test status
Simulation time 1238945024 ps
CPU time 13.38 seconds
Started Jul 03 04:36:21 PM PDT 24
Finished Jul 03 04:36:35 PM PDT 24
Peak memory 211904 kb
Host smart-4ffb4211-9106-4379-b9ed-752df98944db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893140351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1893140351
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.335003910
Short name T256
Test name
Test status
Simulation time 92859709 ps
CPU time 5.32 seconds
Started Jul 03 04:36:21 PM PDT 24
Finished Jul 03 04:36:26 PM PDT 24
Peak memory 211324 kb
Host smart-820f16ab-92fd-4eb8-abdd-3879d88e8dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335003910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.335003910
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2930299936
Short name T2
Test name
Test status
Simulation time 183998442 ps
CPU time 10.41 seconds
Started Jul 03 04:36:19 PM PDT 24
Finished Jul 03 04:36:29 PM PDT 24
Peak memory 213024 kb
Host smart-84203c8c-8536-44cb-8cdf-18aa03920d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930299936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2930299936
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3607910252
Short name T345
Test name
Test status
Simulation time 13585334112 ps
CPU time 71.84 seconds
Started Jul 03 04:36:16 PM PDT 24
Finished Jul 03 04:37:28 PM PDT 24
Peak memory 219344 kb
Host smart-1450adcc-6b77-4f63-b094-230f7c0cfb76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607910252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3607910252
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3822602218
Short name T288
Test name
Test status
Simulation time 1992424595 ps
CPU time 15.22 seconds
Started Jul 03 04:36:21 PM PDT 24
Finished Jul 03 04:36:37 PM PDT 24
Peak memory 211224 kb
Host smart-4825d35d-d103-4249-8d18-0d54c4e88c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822602218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3822602218
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1313874030
Short name T118
Test name
Test status
Simulation time 263788618078 ps
CPU time 185.21 seconds
Started Jul 03 04:36:23 PM PDT 24
Finished Jul 03 04:39:29 PM PDT 24
Peak memory 238052 kb
Host smart-94ccaf53-e1a6-4f0c-9cc5-6de63b73a415
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313874030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1313874030
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2528657501
Short name T350
Test name
Test status
Simulation time 720908872 ps
CPU time 11.71 seconds
Started Jul 03 04:36:25 PM PDT 24
Finished Jul 03 04:36:37 PM PDT 24
Peak memory 211916 kb
Host smart-44dcdfc8-f534-4a17-aa27-cbe9a8418bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528657501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2528657501
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1823484296
Short name T133
Test name
Test status
Simulation time 141275018 ps
CPU time 5.9 seconds
Started Jul 03 04:36:23 PM PDT 24
Finished Jul 03 04:36:29 PM PDT 24
Peak memory 211312 kb
Host smart-caf1574a-02d3-4fa9-9a5e-7ca89be5ee48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823484296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1823484296
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1416671823
Short name T73
Test name
Test status
Simulation time 23354545309 ps
CPU time 35.14 seconds
Started Jul 03 04:36:24 PM PDT 24
Finished Jul 03 04:37:00 PM PDT 24
Peak memory 215616 kb
Host smart-fc533307-62b7-4d30-a90f-18d34566c6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416671823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1416671823
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.401039719
Short name T183
Test name
Test status
Simulation time 47628117062 ps
CPU time 72.12 seconds
Started Jul 03 04:36:22 PM PDT 24
Finished Jul 03 04:37:34 PM PDT 24
Peak memory 216420 kb
Host smart-ef32addd-a1cc-4137-bd9c-ee141834ce5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401039719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.401039719
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3082757424
Short name T351
Test name
Test status
Simulation time 3444267808 ps
CPU time 14.43 seconds
Started Jul 03 04:36:20 PM PDT 24
Finished Jul 03 04:36:35 PM PDT 24
Peak memory 211352 kb
Host smart-1ceffaac-a2b3-4a03-bb90-a175bca287eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082757424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3082757424
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.36126043
Short name T194
Test name
Test status
Simulation time 3632409531 ps
CPU time 113.63 seconds
Started Jul 03 04:36:20 PM PDT 24
Finished Jul 03 04:38:13 PM PDT 24
Peak memory 234684 kb
Host smart-c3a3d242-b0d2-4f45-80de-0d14aad94f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36126043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_co
rrupt_sig_fatal_chk.36126043
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2151799580
Short name T320
Test name
Test status
Simulation time 1651963931 ps
CPU time 12.95 seconds
Started Jul 03 04:36:23 PM PDT 24
Finished Jul 03 04:36:36 PM PDT 24
Peak memory 211348 kb
Host smart-975d6328-199d-491c-9118-b9f392242f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151799580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2151799580
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.806121671
Short name T9
Test name
Test status
Simulation time 1257531011 ps
CPU time 12.28 seconds
Started Jul 03 04:36:24 PM PDT 24
Finished Jul 03 04:36:37 PM PDT 24
Peak memory 211372 kb
Host smart-41e1ed55-bbec-43ab-a915-59a8f781e079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806121671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.806121671
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.260488379
Short name T162
Test name
Test status
Simulation time 2147813144 ps
CPU time 22.56 seconds
Started Jul 03 04:36:20 PM PDT 24
Finished Jul 03 04:36:43 PM PDT 24
Peak memory 213996 kb
Host smart-fa355b36-3a00-4d3b-9a24-601fbf2fd3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260488379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.260488379
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2251618501
Short name T60
Test name
Test status
Simulation time 1455665102 ps
CPU time 12.63 seconds
Started Jul 03 04:36:25 PM PDT 24
Finished Jul 03 04:36:38 PM PDT 24
Peak memory 211280 kb
Host smart-a0f66d36-028f-4d2f-8606-189688806fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251618501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2251618501
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.961708732
Short name T317
Test name
Test status
Simulation time 700867190409 ps
CPU time 442.38 seconds
Started Jul 03 04:36:20 PM PDT 24
Finished Jul 03 04:43:43 PM PDT 24
Peak memory 239296 kb
Host smart-dfe37645-5d1f-43ed-ad34-5d9a16a4c49c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961708732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.961708732
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2642079466
Short name T214
Test name
Test status
Simulation time 3539652551 ps
CPU time 30.8 seconds
Started Jul 03 04:36:22 PM PDT 24
Finished Jul 03 04:36:53 PM PDT 24
Peak memory 211808 kb
Host smart-1ac5fc11-bbcb-4daa-9dd7-5b38f0c0c4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642079466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2642079466
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1649252877
Short name T333
Test name
Test status
Simulation time 1455342444 ps
CPU time 13.5 seconds
Started Jul 03 04:36:21 PM PDT 24
Finished Jul 03 04:36:35 PM PDT 24
Peak memory 211328 kb
Host smart-67cb928e-c1cd-4784-8738-b4d28857fee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649252877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1649252877
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1778786678
Short name T15
Test name
Test status
Simulation time 344522518 ps
CPU time 10.21 seconds
Started Jul 03 04:36:22 PM PDT 24
Finished Jul 03 04:36:33 PM PDT 24
Peak memory 213476 kb
Host smart-0bb67c9b-edb5-474f-b242-d45c7273ee70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778786678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1778786678
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1438544135
Short name T244
Test name
Test status
Simulation time 19649291496 ps
CPU time 29.27 seconds
Started Jul 03 04:36:22 PM PDT 24
Finished Jul 03 04:36:52 PM PDT 24
Peak memory 214724 kb
Host smart-5fb433ae-6af0-45d1-99df-2927d49152e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438544135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1438544135
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3856546934
Short name T44
Test name
Test status
Simulation time 51642408942 ps
CPU time 188.77 seconds
Started Jul 03 04:36:25 PM PDT 24
Finished Jul 03 04:39:34 PM PDT 24
Peak memory 227672 kb
Host smart-d934b819-f86a-48ee-8e86-d722acd03ccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856546934 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3856546934
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3611588116
Short name T354
Test name
Test status
Simulation time 3794880282 ps
CPU time 9.85 seconds
Started Jul 03 04:35:05 PM PDT 24
Finished Jul 03 04:35:15 PM PDT 24
Peak memory 211348 kb
Host smart-f9c49452-2687-4e2b-9361-c64eacd6626b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611588116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3611588116
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1979745036
Short name T308
Test name
Test status
Simulation time 36689814404 ps
CPU time 138.5 seconds
Started Jul 03 04:35:04 PM PDT 24
Finished Jul 03 04:37:23 PM PDT 24
Peak memory 237800 kb
Host smart-c0c13423-2f42-4f22-9f68-80bbc9254d49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979745036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1979745036
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3161146129
Short name T309
Test name
Test status
Simulation time 9197444156 ps
CPU time 19.63 seconds
Started Jul 03 04:35:04 PM PDT 24
Finished Jul 03 04:35:24 PM PDT 24
Peak memory 212216 kb
Host smart-f5280227-09ea-43e4-8a37-6ae6e56be6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161146129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3161146129
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2331565376
Short name T273
Test name
Test status
Simulation time 2298786682 ps
CPU time 12.45 seconds
Started Jul 03 04:35:04 PM PDT 24
Finished Jul 03 04:35:17 PM PDT 24
Peak memory 211328 kb
Host smart-e66ed3b8-4111-47cb-a017-356b6540259d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331565376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2331565376
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2910516751
Short name T3
Test name
Test status
Simulation time 4195755567 ps
CPU time 13.05 seconds
Started Jul 03 04:35:02 PM PDT 24
Finished Jul 03 04:35:16 PM PDT 24
Peak memory 212416 kb
Host smart-5451b784-83fe-4619-a3c7-448985b15ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910516751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2910516751
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1119149086
Short name T122
Test name
Test status
Simulation time 2755970168 ps
CPU time 27.72 seconds
Started Jul 03 04:35:04 PM PDT 24
Finished Jul 03 04:35:32 PM PDT 24
Peak memory 214676 kb
Host smart-5a95e0d7-4c6b-4ad3-a96c-213d0d6871f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119149086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1119149086
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1577931921
Short name T340
Test name
Test status
Simulation time 1050211055 ps
CPU time 10.3 seconds
Started Jul 03 04:35:03 PM PDT 24
Finished Jul 03 04:35:14 PM PDT 24
Peak memory 211196 kb
Host smart-873490c6-05e6-420a-8f75-23b79b626e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577931921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1577931921
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1472025605
Short name T284
Test name
Test status
Simulation time 437839116631 ps
CPU time 347.7 seconds
Started Jul 03 04:35:04 PM PDT 24
Finished Jul 03 04:40:52 PM PDT 24
Peak memory 234860 kb
Host smart-4636c0f2-a077-4838-8963-8460a1ac790d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472025605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1472025605
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.600508543
Short name T42
Test name
Test status
Simulation time 754683850 ps
CPU time 9.54 seconds
Started Jul 03 04:35:01 PM PDT 24
Finished Jul 03 04:35:11 PM PDT 24
Peak memory 211916 kb
Host smart-86f34179-0d11-4d07-ac8d-b064d05fd30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600508543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.600508543
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1122342104
Short name T316
Test name
Test status
Simulation time 426044895 ps
CPU time 8.13 seconds
Started Jul 03 04:35:02 PM PDT 24
Finished Jul 03 04:35:11 PM PDT 24
Peak memory 211308 kb
Host smart-6f168491-4be1-42c0-a66d-97f36342d5c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122342104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1122342104
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3885754749
Short name T43
Test name
Test status
Simulation time 3441496013 ps
CPU time 22.06 seconds
Started Jul 03 04:35:09 PM PDT 24
Finished Jul 03 04:35:31 PM PDT 24
Peak memory 213960 kb
Host smart-6e25912c-1eb3-41c8-b2f6-3e87c069890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885754749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3885754749
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1992717457
Short name T278
Test name
Test status
Simulation time 6014127617 ps
CPU time 39.15 seconds
Started Jul 03 04:35:01 PM PDT 24
Finished Jul 03 04:35:40 PM PDT 24
Peak memory 217028 kb
Host smart-eaefbb91-e71d-4e72-bce0-98c20c2b1153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992717457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1992717457
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1741049193
Short name T358
Test name
Test status
Simulation time 519861364 ps
CPU time 6.08 seconds
Started Jul 03 04:35:06 PM PDT 24
Finished Jul 03 04:35:12 PM PDT 24
Peak memory 211244 kb
Host smart-5642630c-ab36-4957-8afa-a1959174ffac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741049193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1741049193
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1792025853
Short name T301
Test name
Test status
Simulation time 2690364228 ps
CPU time 169.67 seconds
Started Jul 03 04:35:05 PM PDT 24
Finished Jul 03 04:37:56 PM PDT 24
Peak memory 225168 kb
Host smart-c41ae248-fe2d-4bf4-a563-b60f4cff220f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792025853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1792025853
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2124129237
Short name T210
Test name
Test status
Simulation time 3296465595 ps
CPU time 14.55 seconds
Started Jul 03 04:35:05 PM PDT 24
Finished Jul 03 04:35:20 PM PDT 24
Peak memory 212052 kb
Host smart-07384818-eac3-4645-8abd-44ef8fb5901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124129237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2124129237
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1647117404
Short name T6
Test name
Test status
Simulation time 2072435377 ps
CPU time 11.48 seconds
Started Jul 03 04:35:03 PM PDT 24
Finished Jul 03 04:35:15 PM PDT 24
Peak memory 211328 kb
Host smart-08579951-39e9-4a48-8093-4d21ba85c4ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647117404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1647117404
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3762532564
Short name T135
Test name
Test status
Simulation time 194897475 ps
CPU time 9.86 seconds
Started Jul 03 04:35:03 PM PDT 24
Finished Jul 03 04:35:14 PM PDT 24
Peak memory 213444 kb
Host smart-5440798c-7e36-43d0-b4fc-083be63987ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762532564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3762532564
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3911457657
Short name T224
Test name
Test status
Simulation time 761112642 ps
CPU time 24.08 seconds
Started Jul 03 04:35:09 PM PDT 24
Finished Jul 03 04:35:33 PM PDT 24
Peak memory 219288 kb
Host smart-828fb770-35b2-4d50-8835-2158aeb4537a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911457657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3911457657
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3211656015
Short name T156
Test name
Test status
Simulation time 164906518 ps
CPU time 4.19 seconds
Started Jul 03 04:35:12 PM PDT 24
Finished Jul 03 04:35:17 PM PDT 24
Peak memory 211296 kb
Host smart-a8294398-d22e-477d-9a88-24bebac3721f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211656015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3211656015
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4104330218
Short name T36
Test name
Test status
Simulation time 11188464921 ps
CPU time 72.21 seconds
Started Jul 03 04:35:10 PM PDT 24
Finished Jul 03 04:36:22 PM PDT 24
Peak memory 238764 kb
Host smart-7b3d69f9-58b7-4ede-ab0c-4887f9b2a59d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104330218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4104330218
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.833064477
Short name T270
Test name
Test status
Simulation time 1161081201 ps
CPU time 16.58 seconds
Started Jul 03 04:35:07 PM PDT 24
Finished Jul 03 04:35:24 PM PDT 24
Peak memory 212044 kb
Host smart-6c92c9a3-b7a6-4d14-8d8a-51d05c65ecbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833064477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.833064477
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2657261835
Short name T147
Test name
Test status
Simulation time 911332191 ps
CPU time 11.1 seconds
Started Jul 03 04:35:06 PM PDT 24
Finished Jul 03 04:35:17 PM PDT 24
Peak memory 211360 kb
Host smart-d2fa4052-71a2-48a5-9c6d-730b957a2475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657261835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2657261835
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3888764876
Short name T339
Test name
Test status
Simulation time 3013182709 ps
CPU time 15.69 seconds
Started Jul 03 04:35:07 PM PDT 24
Finished Jul 03 04:35:23 PM PDT 24
Peak memory 213312 kb
Host smart-f7066618-f9e0-4536-a906-354bd811ba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888764876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3888764876
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4245952098
Short name T176
Test name
Test status
Simulation time 10500335730 ps
CPU time 64.82 seconds
Started Jul 03 04:35:05 PM PDT 24
Finished Jul 03 04:36:10 PM PDT 24
Peak memory 217204 kb
Host smart-0a27560e-0ac0-46cb-baab-b587fc6bb057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245952098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4245952098
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.835483847
Short name T45
Test name
Test status
Simulation time 4344902460 ps
CPU time 367.35 seconds
Started Jul 03 04:35:05 PM PDT 24
Finished Jul 03 04:41:12 PM PDT 24
Peak memory 222372 kb
Host smart-5b8f6194-74bf-4e8d-9ca2-57953084775c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835483847 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.835483847
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2573986180
Short name T266
Test name
Test status
Simulation time 461687556 ps
CPU time 4.47 seconds
Started Jul 03 04:35:16 PM PDT 24
Finished Jul 03 04:35:21 PM PDT 24
Peak memory 211284 kb
Host smart-7006f8ff-3dd2-4bc7-ba32-905e76b0fff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573986180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2573986180
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3953011988
Short name T291
Test name
Test status
Simulation time 1307032122 ps
CPU time 83.48 seconds
Started Jul 03 04:35:10 PM PDT 24
Finished Jul 03 04:36:34 PM PDT 24
Peak memory 238532 kb
Host smart-befbac65-85f4-4e80-aed4-052c1b608b6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953011988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3953011988
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2740192342
Short name T20
Test name
Test status
Simulation time 1720772652 ps
CPU time 14.35 seconds
Started Jul 03 04:35:11 PM PDT 24
Finished Jul 03 04:35:26 PM PDT 24
Peak memory 211900 kb
Host smart-6449ebc5-af22-44fa-aa4b-8685b7c80627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740192342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2740192342
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.205625689
Short name T336
Test name
Test status
Simulation time 1164049150 ps
CPU time 5.52 seconds
Started Jul 03 04:35:12 PM PDT 24
Finished Jul 03 04:35:18 PM PDT 24
Peak memory 211256 kb
Host smart-8c690afc-265b-478c-a735-d5528c0f7252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205625689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.205625689
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3449990620
Short name T349
Test name
Test status
Simulation time 44594410845 ps
CPU time 38.04 seconds
Started Jul 03 04:35:16 PM PDT 24
Finished Jul 03 04:35:55 PM PDT 24
Peak memory 214008 kb
Host smart-c7f2b746-c8b2-483b-82c4-30fbd40e094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449990620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3449990620
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.610156934
Short name T247
Test name
Test status
Simulation time 4066971411 ps
CPU time 34.96 seconds
Started Jul 03 04:35:11 PM PDT 24
Finished Jul 03 04:35:46 PM PDT 24
Peak memory 214672 kb
Host smart-1ceddb6b-185c-4f4e-bdda-a451bedbf655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610156934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.610156934
Directory /workspace/9.rom_ctrl_stress_all/latest
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