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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 96.89 92.42 97.67 100.00 98.62 97.45 98.14


Total test records in report: 468
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T299 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2659511787 Jul 04 05:10:51 PM PDT 24 Jul 04 05:11:06 PM PDT 24 6265255525 ps
T300 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3105039046 Jul 04 05:10:46 PM PDT 24 Jul 04 05:12:29 PM PDT 24 1707211309 ps
T301 /workspace/coverage/default/3.rom_ctrl_stress_all.94982626 Jul 04 05:10:38 PM PDT 24 Jul 04 05:11:07 PM PDT 24 3406172535 ps
T44 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.477106059 Jul 04 05:11:12 PM PDT 24 Jul 04 05:48:45 PM PDT 24 265043930909 ps
T302 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2506242017 Jul 04 05:10:51 PM PDT 24 Jul 04 05:14:05 PM PDT 24 67381970057 ps
T303 /workspace/coverage/default/34.rom_ctrl_alert_test.2359923590 Jul 04 05:11:08 PM PDT 24 Jul 04 05:11:12 PM PDT 24 109030856 ps
T304 /workspace/coverage/default/23.rom_ctrl_smoke.1172044632 Jul 04 05:10:57 PM PDT 24 Jul 04 05:11:07 PM PDT 24 384231441 ps
T305 /workspace/coverage/default/24.rom_ctrl_smoke.2708917863 Jul 04 05:10:53 PM PDT 24 Jul 04 05:11:27 PM PDT 24 16438972668 ps
T306 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.515881996 Jul 04 05:10:42 PM PDT 24 Jul 04 05:10:57 PM PDT 24 7202492461 ps
T307 /workspace/coverage/default/18.rom_ctrl_alert_test.2943677940 Jul 04 05:10:47 PM PDT 24 Jul 04 05:10:54 PM PDT 24 3083773435 ps
T308 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2998056047 Jul 04 05:11:30 PM PDT 24 Jul 04 05:11:49 PM PDT 24 1833320621 ps
T309 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2869056687 Jul 04 05:10:44 PM PDT 24 Jul 04 05:10:58 PM PDT 24 2750908405 ps
T310 /workspace/coverage/default/47.rom_ctrl_stress_all.1413015119 Jul 04 05:11:28 PM PDT 24 Jul 04 05:11:50 PM PDT 24 2089343132 ps
T311 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1035685505 Jul 04 05:11:13 PM PDT 24 Jul 04 05:13:40 PM PDT 24 12868549875 ps
T312 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2794226605 Jul 04 05:11:05 PM PDT 24 Jul 04 05:11:10 PM PDT 24 189306272 ps
T313 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.451386910 Jul 04 05:11:10 PM PDT 24 Jul 04 05:17:20 PM PDT 24 170968245123 ps
T314 /workspace/coverage/default/45.rom_ctrl_alert_test.1523804721 Jul 04 05:11:22 PM PDT 24 Jul 04 05:11:31 PM PDT 24 663981041 ps
T45 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.429245889 Jul 04 05:11:20 PM PDT 24 Jul 04 05:40:16 PM PDT 24 162525263435 ps
T315 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.241026769 Jul 04 05:10:44 PM PDT 24 Jul 04 05:12:36 PM PDT 24 7601852754 ps
T316 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.430441545 Jul 04 05:11:11 PM PDT 24 Jul 04 05:11:21 PM PDT 24 175862734 ps
T317 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2017621599 Jul 04 05:10:34 PM PDT 24 Jul 04 05:12:56 PM PDT 24 5425970121 ps
T318 /workspace/coverage/default/36.rom_ctrl_alert_test.1670646169 Jul 04 05:10:57 PM PDT 24 Jul 04 05:11:09 PM PDT 24 6169122138 ps
T319 /workspace/coverage/default/36.rom_ctrl_stress_all.4272115026 Jul 04 05:11:02 PM PDT 24 Jul 04 05:11:26 PM PDT 24 3201324197 ps
T320 /workspace/coverage/default/43.rom_ctrl_stress_all.1581488293 Jul 04 05:11:15 PM PDT 24 Jul 04 05:12:03 PM PDT 24 7888453138 ps
T321 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2143646655 Jul 04 05:11:31 PM PDT 24 Jul 04 05:24:01 PM PDT 24 189970226495 ps
T322 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.988612101 Jul 04 05:10:54 PM PDT 24 Jul 04 05:11:11 PM PDT 24 5608457609 ps
T323 /workspace/coverage/default/13.rom_ctrl_stress_all.373245228 Jul 04 05:10:44 PM PDT 24 Jul 04 05:10:53 PM PDT 24 176213693 ps
T324 /workspace/coverage/default/20.rom_ctrl_alert_test.4263030403 Jul 04 05:10:55 PM PDT 24 Jul 04 05:11:17 PM PDT 24 8532254885 ps
T325 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3652138085 Jul 04 05:11:36 PM PDT 24 Jul 04 05:14:12 PM PDT 24 12038316786 ps
T326 /workspace/coverage/default/42.rom_ctrl_alert_test.1143450001 Jul 04 05:11:13 PM PDT 24 Jul 04 05:11:25 PM PDT 24 5133262870 ps
T327 /workspace/coverage/default/4.rom_ctrl_stress_all.2415998805 Jul 04 05:10:37 PM PDT 24 Jul 04 05:10:56 PM PDT 24 587888469 ps
T328 /workspace/coverage/default/9.rom_ctrl_alert_test.759194695 Jul 04 05:10:51 PM PDT 24 Jul 04 05:10:58 PM PDT 24 1314161472 ps
T329 /workspace/coverage/default/1.rom_ctrl_smoke.1017623954 Jul 04 05:10:27 PM PDT 24 Jul 04 05:10:56 PM PDT 24 5864052586 ps
T330 /workspace/coverage/default/27.rom_ctrl_smoke.610031507 Jul 04 05:10:50 PM PDT 24 Jul 04 05:11:00 PM PDT 24 215729711 ps
T331 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2469004069 Jul 04 05:10:39 PM PDT 24 Jul 04 05:11:04 PM PDT 24 4821952357 ps
T332 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3763714429 Jul 04 05:11:10 PM PDT 24 Jul 04 05:11:42 PM PDT 24 16379572285 ps
T333 /workspace/coverage/default/47.rom_ctrl_alert_test.2644197848 Jul 04 05:11:30 PM PDT 24 Jul 04 05:11:41 PM PDT 24 903496075 ps
T334 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.851354951 Jul 04 05:11:10 PM PDT 24 Jul 04 05:11:25 PM PDT 24 602539956 ps
T335 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.9590671 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:53 PM PDT 24 7885559430 ps
T336 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3803005317 Jul 04 05:10:31 PM PDT 24 Jul 04 05:10:41 PM PDT 24 839296907 ps
T337 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.745010458 Jul 04 05:11:14 PM PDT 24 Jul 04 05:13:10 PM PDT 24 15962672919 ps
T338 /workspace/coverage/default/29.rom_ctrl_alert_test.2284153032 Jul 04 05:10:57 PM PDT 24 Jul 04 05:11:02 PM PDT 24 96136252 ps
T339 /workspace/coverage/default/16.rom_ctrl_stress_all.1460658861 Jul 04 05:10:44 PM PDT 24 Jul 04 05:10:55 PM PDT 24 834201072 ps
T340 /workspace/coverage/default/4.rom_ctrl_alert_test.2439118866 Jul 04 05:10:36 PM PDT 24 Jul 04 05:10:41 PM PDT 24 108726701 ps
T341 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1753520470 Jul 04 05:10:59 PM PDT 24 Jul 04 05:12:38 PM PDT 24 9708670554 ps
T342 /workspace/coverage/default/6.rom_ctrl_alert_test.3666289096 Jul 04 05:10:34 PM PDT 24 Jul 04 05:10:46 PM PDT 24 5914005475 ps
T343 /workspace/coverage/default/48.rom_ctrl_smoke.2858736573 Jul 04 05:11:29 PM PDT 24 Jul 04 05:11:39 PM PDT 24 3434972331 ps
T344 /workspace/coverage/default/10.rom_ctrl_smoke.1405332424 Jul 04 05:10:42 PM PDT 24 Jul 04 05:10:52 PM PDT 24 188577916 ps
T345 /workspace/coverage/default/10.rom_ctrl_alert_test.1743053225 Jul 04 05:10:48 PM PDT 24 Jul 04 05:10:59 PM PDT 24 1629982510 ps
T346 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1621306032 Jul 04 05:10:41 PM PDT 24 Jul 04 05:10:55 PM PDT 24 1414734077 ps
T347 /workspace/coverage/default/39.rom_ctrl_smoke.449883773 Jul 04 05:11:10 PM PDT 24 Jul 04 05:11:37 PM PDT 24 4988550361 ps
T348 /workspace/coverage/default/2.rom_ctrl_alert_test.510215788 Jul 04 05:10:37 PM PDT 24 Jul 04 05:10:50 PM PDT 24 3599633134 ps
T349 /workspace/coverage/default/27.rom_ctrl_alert_test.1969179112 Jul 04 05:11:00 PM PDT 24 Jul 04 05:11:05 PM PDT 24 171510237 ps
T350 /workspace/coverage/default/35.rom_ctrl_stress_all.4042852141 Jul 04 05:11:11 PM PDT 24 Jul 04 05:11:32 PM PDT 24 4557147957 ps
T351 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3965428010 Jul 04 05:11:10 PM PDT 24 Jul 04 05:11:16 PM PDT 24 632846070 ps
T352 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1475907006 Jul 04 05:10:33 PM PDT 24 Jul 04 05:10:58 PM PDT 24 5129867396 ps
T353 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4219478046 Jul 04 05:10:36 PM PDT 24 Jul 04 05:17:06 PM PDT 24 10158970091 ps
T354 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1224224673 Jul 04 05:11:05 PM PDT 24 Jul 04 05:14:30 PM PDT 24 13963513746 ps
T355 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.50303097 Jul 04 05:10:52 PM PDT 24 Jul 04 05:11:26 PM PDT 24 11968281926 ps
T356 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.998539890 Jul 04 05:10:59 PM PDT 24 Jul 04 05:11:14 PM PDT 24 3016366796 ps
T357 /workspace/coverage/default/17.rom_ctrl_stress_all.2990242719 Jul 04 05:10:57 PM PDT 24 Jul 04 05:11:12 PM PDT 24 1417507720 ps
T358 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3259288631 Jul 04 05:11:13 PM PDT 24 Jul 04 05:11:35 PM PDT 24 4034867545 ps
T359 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3906698780 Jul 04 05:10:59 PM PDT 24 Jul 04 05:11:09 PM PDT 24 780411283 ps
T360 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3858451167 Jul 04 05:10:42 PM PDT 24 Jul 04 05:19:06 PM PDT 24 206347608866 ps
T361 /workspace/coverage/default/33.rom_ctrl_smoke.3292700222 Jul 04 05:11:02 PM PDT 24 Jul 04 05:11:26 PM PDT 24 7212916688 ps
T362 /workspace/coverage/default/31.rom_ctrl_stress_all.185392871 Jul 04 05:11:07 PM PDT 24 Jul 04 05:11:28 PM PDT 24 321484370 ps
T363 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2492766494 Jul 04 05:10:57 PM PDT 24 Jul 04 05:11:21 PM PDT 24 2445097109 ps
T46 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1044108465 Jul 04 05:11:10 PM PDT 24 Jul 04 06:02:09 PM PDT 24 716414605257 ps
T364 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1162351187 Jul 04 05:10:52 PM PDT 24 Jul 04 05:11:19 PM PDT 24 13604505814 ps
T365 /workspace/coverage/default/39.rom_ctrl_stress_all.67865791 Jul 04 05:11:13 PM PDT 24 Jul 04 05:11:26 PM PDT 24 939893456 ps
T366 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2983739963 Jul 04 05:11:06 PM PDT 24 Jul 04 05:11:18 PM PDT 24 333404695 ps
T367 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.950032385 Jul 04 05:11:00 PM PDT 24 Jul 04 05:11:06 PM PDT 24 543752953 ps
T368 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2704507848 Jul 04 05:10:54 PM PDT 24 Jul 04 05:11:06 PM PDT 24 4648870955 ps
T57 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4017096712 Jul 04 06:39:20 PM PDT 24 Jul 04 06:39:34 PM PDT 24 1701142435 ps
T58 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2646734785 Jul 04 06:38:59 PM PDT 24 Jul 04 06:40:35 PM PDT 24 128720100167 ps
T54 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1725726402 Jul 04 06:39:06 PM PDT 24 Jul 04 06:40:19 PM PDT 24 352047359 ps
T369 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1250318311 Jul 04 06:39:28 PM PDT 24 Jul 04 06:39:37 PM PDT 24 759698739 ps
T370 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.659801524 Jul 04 06:38:39 PM PDT 24 Jul 04 06:38:59 PM PDT 24 7488778126 ps
T371 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2413489184 Jul 04 06:39:07 PM PDT 24 Jul 04 06:39:17 PM PDT 24 7199013302 ps
T93 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2930856698 Jul 04 06:39:01 PM PDT 24 Jul 04 06:39:05 PM PDT 24 121049421 ps
T94 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1959537219 Jul 04 06:39:20 PM PDT 24 Jul 04 06:39:32 PM PDT 24 1601604256 ps
T60 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1472239227 Jul 04 06:39:05 PM PDT 24 Jul 04 06:40:34 PM PDT 24 147982463813 ps
T100 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3745361121 Jul 04 06:39:00 PM PDT 24 Jul 04 06:40:09 PM PDT 24 70427241794 ps
T372 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3202115106 Jul 04 06:39:00 PM PDT 24 Jul 04 06:39:16 PM PDT 24 2083613664 ps
T55 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1726764628 Jul 04 06:39:01 PM PDT 24 Jul 04 06:39:38 PM PDT 24 325830444 ps
T56 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2583555622 Jul 04 06:39:07 PM PDT 24 Jul 04 06:40:23 PM PDT 24 6304336757 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2717226421 Jul 04 06:38:48 PM PDT 24 Jul 04 06:38:53 PM PDT 24 379757272 ps
T373 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3087398553 Jul 04 06:39:09 PM PDT 24 Jul 04 06:39:21 PM PDT 24 455550010 ps
T102 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1368966200 Jul 04 06:39:10 PM PDT 24 Jul 04 06:40:14 PM PDT 24 12815766470 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.275540299 Jul 04 06:38:39 PM PDT 24 Jul 04 06:38:48 PM PDT 24 726354884 ps
T103 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4084972026 Jul 04 06:39:22 PM PDT 24 Jul 04 06:39:51 PM PDT 24 542238961 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2431499356 Jul 04 06:38:31 PM PDT 24 Jul 04 06:38:45 PM PDT 24 3240738773 ps
T375 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1709834090 Jul 04 06:39:04 PM PDT 24 Jul 04 06:39:21 PM PDT 24 1645928768 ps
T61 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3645451105 Jul 04 06:39:06 PM PDT 24 Jul 04 06:40:15 PM PDT 24 35510777341 ps
T376 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2983585165 Jul 04 06:39:07 PM PDT 24 Jul 04 06:39:16 PM PDT 24 718457085 ps
T62 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1725497826 Jul 04 06:38:39 PM PDT 24 Jul 04 06:38:58 PM PDT 24 376571070 ps
T63 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1389532231 Jul 04 06:39:07 PM PDT 24 Jul 04 06:39:35 PM PDT 24 549894976 ps
T64 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4117857216 Jul 04 06:38:32 PM PDT 24 Jul 04 06:38:40 PM PDT 24 966986144 ps
T95 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2759086504 Jul 04 06:39:05 PM PDT 24 Jul 04 06:39:12 PM PDT 24 378899374 ps
T96 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1247190321 Jul 04 06:39:12 PM PDT 24 Jul 04 06:39:22 PM PDT 24 3412503697 ps
T377 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3897107984 Jul 04 06:39:13 PM PDT 24 Jul 04 06:39:20 PM PDT 24 85493061 ps
T97 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1878874903 Jul 04 06:39:10 PM PDT 24 Jul 04 06:39:22 PM PDT 24 1282952184 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3374377938 Jul 04 06:38:32 PM PDT 24 Jul 04 06:38:46 PM PDT 24 3875362050 ps
T65 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3717725798 Jul 04 06:39:07 PM PDT 24 Jul 04 06:39:11 PM PDT 24 347280074 ps
T379 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1472463848 Jul 04 06:39:22 PM PDT 24 Jul 04 06:39:34 PM PDT 24 3523651999 ps
T108 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3352924539 Jul 04 06:39:07 PM PDT 24 Jul 04 06:40:20 PM PDT 24 1468192099 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3342492381 Jul 04 06:38:39 PM PDT 24 Jul 04 06:38:55 PM PDT 24 3491352567 ps
T66 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2238902915 Jul 04 06:38:32 PM PDT 24 Jul 04 06:40:02 PM PDT 24 81728586811 ps
T67 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1261709518 Jul 04 06:39:20 PM PDT 24 Jul 04 06:39:26 PM PDT 24 1778336334 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.71752542 Jul 04 06:39:00 PM PDT 24 Jul 04 06:39:07 PM PDT 24 2064932851 ps
T68 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.198512842 Jul 04 06:39:05 PM PDT 24 Jul 04 06:39:21 PM PDT 24 2863062140 ps
T382 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1294383013 Jul 04 06:39:07 PM PDT 24 Jul 04 06:40:16 PM PDT 24 8473152377 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3801302438 Jul 04 06:38:32 PM PDT 24 Jul 04 06:38:37 PM PDT 24 101708833 ps
T110 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.341851763 Jul 04 06:38:39 PM PDT 24 Jul 04 06:39:49 PM PDT 24 756191650 ps
T384 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.273498510 Jul 04 06:39:00 PM PDT 24 Jul 04 06:39:12 PM PDT 24 1025755522 ps
T385 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1580416369 Jul 04 06:39:01 PM PDT 24 Jul 04 06:39:14 PM PDT 24 2867399305 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4115082517 Jul 04 06:38:34 PM PDT 24 Jul 04 06:38:53 PM PDT 24 699097784 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2495131958 Jul 04 06:38:32 PM PDT 24 Jul 04 06:38:39 PM PDT 24 1726031588 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1982263901 Jul 04 06:38:34 PM PDT 24 Jul 04 06:38:40 PM PDT 24 361588678 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.582580652 Jul 04 06:38:39 PM PDT 24 Jul 04 06:38:50 PM PDT 24 1203810492 ps
T99 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1682470129 Jul 04 06:39:04 PM PDT 24 Jul 04 06:39:10 PM PDT 24 422945678 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1645826882 Jul 04 06:38:54 PM PDT 24 Jul 04 06:39:08 PM PDT 24 1506040360 ps
T390 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2756221628 Jul 04 06:39:22 PM PDT 24 Jul 04 06:39:37 PM PDT 24 11388369797 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3547981443 Jul 04 06:38:39 PM PDT 24 Jul 04 06:38:53 PM PDT 24 6550859653 ps
T392 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1276211374 Jul 04 06:39:06 PM PDT 24 Jul 04 06:39:13 PM PDT 24 209151511 ps
T393 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4288045682 Jul 04 06:38:33 PM PDT 24 Jul 04 06:38:41 PM PDT 24 1974315256 ps
T394 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2387040779 Jul 04 06:38:54 PM PDT 24 Jul 04 06:39:53 PM PDT 24 42033388562 ps
T395 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1238482537 Jul 04 06:39:13 PM PDT 24 Jul 04 06:39:29 PM PDT 24 1352822181 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1809129375 Jul 04 06:38:35 PM PDT 24 Jul 04 06:38:45 PM PDT 24 826548893 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1998620539 Jul 04 06:38:33 PM PDT 24 Jul 04 06:38:47 PM PDT 24 3339264249 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4270307861 Jul 04 06:38:31 PM PDT 24 Jul 04 06:38:36 PM PDT 24 85554389 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.968651171 Jul 04 06:38:39 PM PDT 24 Jul 04 06:39:26 PM PDT 24 18547971996 ps
T399 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3274416700 Jul 04 06:39:03 PM PDT 24 Jul 04 06:39:43 PM PDT 24 520803247 ps
T400 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1912796344 Jul 04 06:38:59 PM PDT 24 Jul 04 06:39:04 PM PDT 24 347210263 ps
T112 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3341067251 Jul 04 06:38:58 PM PDT 24 Jul 04 06:39:34 PM PDT 24 332216029 ps
T75 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2217923976 Jul 04 06:38:59 PM PDT 24 Jul 04 06:39:18 PM PDT 24 3630812045 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3202323649 Jul 04 06:38:32 PM PDT 24 Jul 04 06:38:51 PM PDT 24 8638340730 ps
T113 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.872288052 Jul 04 06:38:32 PM PDT 24 Jul 04 06:39:43 PM PDT 24 4253800720 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2189237215 Jul 04 06:38:31 PM PDT 24 Jul 04 06:38:46 PM PDT 24 6889514915 ps
T403 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3899363331 Jul 04 06:39:35 PM PDT 24 Jul 04 06:39:51 PM PDT 24 2003425168 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2748324897 Jul 04 06:38:24 PM PDT 24 Jul 04 06:39:05 PM PDT 24 14632922158 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2814017016 Jul 04 06:38:36 PM PDT 24 Jul 04 06:38:46 PM PDT 24 943910347 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2289234120 Jul 04 06:38:46 PM PDT 24 Jul 04 06:38:54 PM PDT 24 1271205064 ps
T407 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.780946108 Jul 04 06:39:08 PM PDT 24 Jul 04 06:39:12 PM PDT 24 753651780 ps
T408 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1685841613 Jul 04 06:38:55 PM PDT 24 Jul 04 06:39:04 PM PDT 24 6067739833 ps
T409 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2481962688 Jul 04 06:39:14 PM PDT 24 Jul 04 06:39:25 PM PDT 24 1089065565 ps
T410 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2563056366 Jul 04 06:39:30 PM PDT 24 Jul 04 06:39:34 PM PDT 24 85448343 ps
T76 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4024234389 Jul 04 06:38:59 PM PDT 24 Jul 04 06:39:03 PM PDT 24 461231866 ps
T411 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3139997050 Jul 04 06:39:20 PM PDT 24 Jul 04 06:39:28 PM PDT 24 517071463 ps
T412 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2255993503 Jul 04 06:38:58 PM PDT 24 Jul 04 06:39:03 PM PDT 24 103156396 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4155663297 Jul 04 06:38:49 PM PDT 24 Jul 04 06:39:04 PM PDT 24 1908362271 ps
T78 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2929005909 Jul 04 06:39:22 PM PDT 24 Jul 04 06:40:37 PM PDT 24 82191694766 ps
T414 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4038558849 Jul 04 06:38:58 PM PDT 24 Jul 04 06:39:14 PM PDT 24 1281900250 ps
T81 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3826930906 Jul 04 06:38:47 PM PDT 24 Jul 04 06:38:58 PM PDT 24 8922409145 ps
T415 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3655334861 Jul 04 06:38:58 PM PDT 24 Jul 04 06:39:36 PM PDT 24 6866033012 ps
T82 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3832665724 Jul 04 06:39:16 PM PDT 24 Jul 04 06:40:23 PM PDT 24 6953008946 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.736838025 Jul 04 06:38:39 PM PDT 24 Jul 04 06:38:56 PM PDT 24 2117251707 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2318274918 Jul 04 06:38:32 PM PDT 24 Jul 04 06:38:43 PM PDT 24 4256030474 ps
T418 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2859744164 Jul 04 06:38:53 PM PDT 24 Jul 04 06:39:41 PM PDT 24 10490009332 ps
T419 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2698166468 Jul 04 06:38:49 PM PDT 24 Jul 04 06:39:07 PM PDT 24 5871891585 ps
T420 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4073711459 Jul 04 06:38:32 PM PDT 24 Jul 04 06:38:49 PM PDT 24 1866235828 ps
T421 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3718256614 Jul 04 06:39:03 PM PDT 24 Jul 04 06:39:12 PM PDT 24 761625147 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2842115561 Jul 04 06:39:21 PM PDT 24 Jul 04 06:40:01 PM PDT 24 3366901983 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1827104675 Jul 04 06:38:39 PM PDT 24 Jul 04 06:38:49 PM PDT 24 6752727671 ps
T423 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.233983616 Jul 04 06:39:09 PM PDT 24 Jul 04 06:39:15 PM PDT 24 1035187463 ps
T424 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.590804373 Jul 04 06:38:58 PM PDT 24 Jul 04 06:39:06 PM PDT 24 309837822 ps
T425 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1531787255 Jul 04 06:39:21 PM PDT 24 Jul 04 06:39:29 PM PDT 24 309391287 ps
T426 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1720476828 Jul 04 06:38:34 PM PDT 24 Jul 04 06:38:49 PM PDT 24 1839364605 ps
T79 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2387630267 Jul 04 06:38:53 PM PDT 24 Jul 04 06:39:08 PM PDT 24 7123075013 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.92502559 Jul 04 06:38:40 PM PDT 24 Jul 04 06:38:47 PM PDT 24 299030636 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.152038349 Jul 04 06:39:23 PM PDT 24 Jul 04 06:39:38 PM PDT 24 14481380015 ps
T429 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3243673662 Jul 04 06:39:05 PM PDT 24 Jul 04 06:39:25 PM PDT 24 2202672855 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1595782120 Jul 04 06:39:13 PM PDT 24 Jul 04 06:39:25 PM PDT 24 760191660 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3791977787 Jul 04 06:38:36 PM PDT 24 Jul 04 06:38:52 PM PDT 24 2140703865 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.203345179 Jul 04 06:38:40 PM PDT 24 Jul 04 06:38:56 PM PDT 24 1864398210 ps
T114 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1347834621 Jul 04 06:39:29 PM PDT 24 Jul 04 06:40:17 PM PDT 24 2258636975 ps
T80 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1882954588 Jul 04 06:39:06 PM PDT 24 Jul 04 06:40:45 PM PDT 24 46601720475 ps
T433 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.347214648 Jul 04 06:38:55 PM PDT 24 Jul 04 06:39:13 PM PDT 24 4818321428 ps
T117 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2630321306 Jul 04 06:38:58 PM PDT 24 Jul 04 06:39:38 PM PDT 24 4920330384 ps
T434 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3981108464 Jul 04 06:38:53 PM PDT 24 Jul 04 06:39:08 PM PDT 24 12101451061 ps
T435 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1197108105 Jul 04 06:38:32 PM PDT 24 Jul 04 06:38:45 PM PDT 24 3111958019 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1518539462 Jul 04 06:39:08 PM PDT 24 Jul 04 06:39:17 PM PDT 24 2422932210 ps
T437 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4001391345 Jul 04 06:39:07 PM PDT 24 Jul 04 06:39:17 PM PDT 24 788359648 ps
T438 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3837321914 Jul 04 06:38:46 PM PDT 24 Jul 04 06:39:33 PM PDT 24 19075235283 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2735889964 Jul 04 06:38:31 PM PDT 24 Jul 04 06:38:36 PM PDT 24 232021913 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2607535344 Jul 04 06:39:06 PM PDT 24 Jul 04 06:39:19 PM PDT 24 1494712914 ps
T440 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.369687365 Jul 04 06:39:07 PM PDT 24 Jul 04 06:39:21 PM PDT 24 1766968147 ps
T116 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.438746412 Jul 04 06:39:20 PM PDT 24 Jul 04 06:39:58 PM PDT 24 1270331430 ps
T441 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.360580583 Jul 04 06:38:53 PM PDT 24 Jul 04 06:39:00 PM PDT 24 833630886 ps
T442 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2746061817 Jul 04 06:39:06 PM PDT 24 Jul 04 06:39:11 PM PDT 24 103383966 ps
T443 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2533560117 Jul 04 06:39:15 PM PDT 24 Jul 04 06:39:57 PM PDT 24 2307786299 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.72625984 Jul 04 06:38:31 PM PDT 24 Jul 04 06:39:08 PM PDT 24 319344500 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1787433813 Jul 04 06:38:39 PM PDT 24 Jul 04 06:39:23 PM PDT 24 3162543417 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1913753538 Jul 04 06:38:32 PM PDT 24 Jul 04 06:38:47 PM PDT 24 7279093519 ps
T447 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.535439263 Jul 04 06:38:58 PM PDT 24 Jul 04 06:39:03 PM PDT 24 172094938 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3868403583 Jul 04 06:39:07 PM PDT 24 Jul 04 06:39:18 PM PDT 24 3477251732 ps
T449 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.998005308 Jul 04 06:39:00 PM PDT 24 Jul 04 06:39:13 PM PDT 24 6653032778 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.632308419 Jul 04 06:39:09 PM PDT 24 Jul 04 06:39:52 PM PDT 24 1201711614 ps
T450 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2673072251 Jul 04 06:39:05 PM PDT 24 Jul 04 06:39:48 PM PDT 24 4024503312 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4377803 Jul 04 06:38:40 PM PDT 24 Jul 04 06:38:51 PM PDT 24 2114477382 ps
T452 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.584850046 Jul 04 06:39:08 PM PDT 24 Jul 04 06:39:16 PM PDT 24 401607166 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1089732374 Jul 04 06:38:49 PM PDT 24 Jul 04 06:39:04 PM PDT 24 1682214453 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2067713622 Jul 04 06:38:40 PM PDT 24 Jul 04 06:38:56 PM PDT 24 4122471166 ps
T455 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.422022135 Jul 04 06:38:29 PM PDT 24 Jul 04 06:38:42 PM PDT 24 5483243258 ps
T456 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.276552829 Jul 04 06:38:36 PM PDT 24 Jul 04 06:39:20 PM PDT 24 1420534829 ps
T457 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1954489682 Jul 04 06:39:03 PM PDT 24 Jul 04 06:39:09 PM PDT 24 401086478 ps
T458 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.103779055 Jul 04 06:39:13 PM PDT 24 Jul 04 06:39:24 PM PDT 24 956967220 ps
T459 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3745093735 Jul 04 06:38:47 PM PDT 24 Jul 04 06:38:53 PM PDT 24 214826830 ps
T460 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2737760389 Jul 04 06:38:34 PM PDT 24 Jul 04 06:38:42 PM PDT 24 324011186 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2393135904 Jul 04 06:38:48 PM PDT 24 Jul 04 06:39:05 PM PDT 24 1884433510 ps
T111 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3551905506 Jul 04 06:38:55 PM PDT 24 Jul 04 06:40:07 PM PDT 24 374208281 ps
T462 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3796875322 Jul 04 06:38:49 PM PDT 24 Jul 04 06:38:56 PM PDT 24 5779305777 ps
T463 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2034917062 Jul 04 06:38:39 PM PDT 24 Jul 04 06:38:49 PM PDT 24 4104034015 ps
T464 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1034125291 Jul 04 06:38:32 PM PDT 24 Jul 04 06:38:50 PM PDT 24 7545937334 ps
T465 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2949870796 Jul 04 06:38:38 PM PDT 24 Jul 04 06:38:52 PM PDT 24 1645374846 ps
T466 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2763995287 Jul 04 06:38:53 PM PDT 24 Jul 04 06:39:01 PM PDT 24 216531373 ps
T467 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1127986642 Jul 04 06:38:38 PM PDT 24 Jul 04 06:38:43 PM PDT 24 346214996 ps
T468 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1997421214 Jul 04 06:39:14 PM PDT 24 Jul 04 06:39:27 PM PDT 24 1935956413 ps

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.84048829
Short name T8
Test name
Test status
Simulation time 15070900101 ps
CPU time 184.76 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:13:55 PM PDT 24
Peak memory 212860 kb
Host smart-d747dd6a-bdec-4b7b-8944-54c533a3567c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84048829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_co
rrupt_sig_fatal_chk.84048829
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.4018046019
Short name T16
Test name
Test status
Simulation time 129247439154 ps
CPU time 3316.94 seconds
Started Jul 04 05:10:37 PM PDT 24
Finished Jul 04 06:05:54 PM PDT 24
Peak memory 235832 kb
Host smart-9c70a238-0d8c-490e-8455-303e0e070b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018046019 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.4018046019
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3527463341
Short name T18
Test name
Test status
Simulation time 127497782448 ps
CPU time 331.14 seconds
Started Jul 04 05:10:43 PM PDT 24
Finished Jul 04 05:16:14 PM PDT 24
Peak memory 224608 kb
Host smart-56544c5f-f630-4543-a1c0-fbba5fe12346
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527463341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3527463341
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1725726402
Short name T54
Test name
Test status
Simulation time 352047359 ps
CPU time 73.05 seconds
Started Jul 04 06:39:06 PM PDT 24
Finished Jul 04 06:40:19 PM PDT 24
Peak memory 219036 kb
Host smart-64adfe3b-0443-456b-912e-b031f4ab408e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725726402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1725726402
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3358634338
Short name T35
Test name
Test status
Simulation time 2819061243 ps
CPU time 21.79 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:11:13 PM PDT 24
Peak memory 214040 kb
Host smart-5183802a-62cc-4e14-b668-8dfaf8a02c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358634338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3358634338
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2031130390
Short name T19
Test name
Test status
Simulation time 6825434887 ps
CPU time 104.73 seconds
Started Jul 04 05:10:35 PM PDT 24
Finished Jul 04 05:12:20 PM PDT 24
Peak memory 236892 kb
Host smart-d39e1ac1-8f91-467d-a7ef-c3374644c493
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031130390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2031130390
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1472239227
Short name T60
Test name
Test status
Simulation time 147982463813 ps
CPU time 88.49 seconds
Started Jul 04 06:39:05 PM PDT 24
Finished Jul 04 06:40:34 PM PDT 24
Peak memory 210852 kb
Host smart-e454a5ef-0af6-447b-a8fa-1bb40f37f162
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472239227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1472239227
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1044108465
Short name T46
Test name
Test status
Simulation time 716414605257 ps
CPU time 3058.06 seconds
Started Jul 04 05:11:10 PM PDT 24
Finished Jul 04 06:02:09 PM PDT 24
Peak memory 238640 kb
Host smart-f6eaf6dd-0813-48d3-ae08-e3c61fdbfa6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044108465 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1044108465
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.354106711
Short name T22
Test name
Test status
Simulation time 88193006 ps
CPU time 4.25 seconds
Started Jul 04 05:10:45 PM PDT 24
Finished Jul 04 05:10:49 PM PDT 24
Peak memory 211292 kb
Host smart-36abc9ff-7274-4c6d-bbe6-75a800990933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354106711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.354106711
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.51320197
Short name T28
Test name
Test status
Simulation time 3918626292 ps
CPU time 31.57 seconds
Started Jul 04 05:11:05 PM PDT 24
Finished Jul 04 05:11:37 PM PDT 24
Peak memory 212004 kb
Host smart-afbd0087-2447-46f0-ae59-e8845e69c64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51320197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.51320197
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1165284312
Short name T88
Test name
Test status
Simulation time 922661725 ps
CPU time 9.49 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:03 PM PDT 24
Peak memory 211736 kb
Host smart-78d97d4a-e81e-453c-a7f8-e7eacb3ff704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165284312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1165284312
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.872288052
Short name T113
Test name
Test status
Simulation time 4253800720 ps
CPU time 70.97 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:39:43 PM PDT 24
Peak memory 219100 kb
Host smart-52477b54-b99e-4116-a3e4-e7adeaca0a50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872288052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.872288052
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.341851763
Short name T110
Test name
Test status
Simulation time 756191650 ps
CPU time 69.39 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:39:49 PM PDT 24
Peak memory 219016 kb
Host smart-a88b701a-c66e-4095-8ce1-52629ad3d476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341851763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.341851763
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2238902915
Short name T66
Test name
Test status
Simulation time 81728586811 ps
CPU time 89.66 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:40:02 PM PDT 24
Peak memory 210856 kb
Host smart-1abb63b1-58ad-484b-931e-66275c598a41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238902915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2238902915
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.157555019
Short name T189
Test name
Test status
Simulation time 1817615738 ps
CPU time 105.08 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:12:35 PM PDT 24
Peak memory 212480 kb
Host smart-2596cf0a-3e69-4009-ad11-97b03288b3a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157555019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.157555019
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.632308419
Short name T109
Test name
Test status
Simulation time 1201711614 ps
CPU time 42.31 seconds
Started Jul 04 06:39:09 PM PDT 24
Finished Jul 04 06:39:52 PM PDT 24
Peak memory 219000 kb
Host smart-0c8fa351-1e36-4550-9d4f-87ef3bbdf3ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632308419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.632308419
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2842115561
Short name T115
Test name
Test status
Simulation time 3366901983 ps
CPU time 40.06 seconds
Started Jul 04 06:39:21 PM PDT 24
Finished Jul 04 06:40:01 PM PDT 24
Peak memory 219092 kb
Host smart-89e3ceb3-9483-4861-93ea-88c366fed219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842115561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2842115561
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3341067251
Short name T112
Test name
Test status
Simulation time 332216029 ps
CPU time 36.49 seconds
Started Jul 04 06:38:58 PM PDT 24
Finished Jul 04 06:39:34 PM PDT 24
Peak memory 218988 kb
Host smart-6ca60d0c-c709-4d87-bd3f-e86229c220f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341067251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3341067251
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2621130934
Short name T13
Test name
Test status
Simulation time 25407086529 ps
CPU time 28.05 seconds
Started Jul 04 05:10:45 PM PDT 24
Finished Jul 04 05:11:14 PM PDT 24
Peak memory 212020 kb
Host smart-ec20c9ed-f2ac-4b60-afb3-9746d16940e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621130934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2621130934
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2365232731
Short name T83
Test name
Test status
Simulation time 1182681826 ps
CPU time 7.38 seconds
Started Jul 04 05:10:44 PM PDT 24
Finished Jul 04 05:10:52 PM PDT 24
Peak memory 211288 kb
Host smart-d24125df-3b43-4f00-aedf-5fa4902b11dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365232731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2365232731
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3837642157
Short name T190
Test name
Test status
Simulation time 6168080935 ps
CPU time 93.26 seconds
Started Jul 04 05:10:51 PM PDT 24
Finished Jul 04 05:12:25 PM PDT 24
Peak memory 237052 kb
Host smart-0eab5e9f-4198-4c2a-a18f-e07f46882b22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837642157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3837642157
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2431499356
Short name T104
Test name
Test status
Simulation time 3240738773 ps
CPU time 14.57 seconds
Started Jul 04 06:38:31 PM PDT 24
Finished Jul 04 06:38:45 PM PDT 24
Peak memory 210832 kb
Host smart-5c0c438d-6daa-4709-898a-983e338aadf5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431499356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2431499356
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4073711459
Short name T420
Test name
Test status
Simulation time 1866235828 ps
CPU time 16.11 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:38:49 PM PDT 24
Peak memory 210800 kb
Host smart-67362ef1-6632-4868-adb9-d02dcdbd984f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073711459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4073711459
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4117857216
Short name T64
Test name
Test status
Simulation time 966986144 ps
CPU time 7.46 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:38:40 PM PDT 24
Peak memory 210760 kb
Host smart-0f18d6b2-7e43-46f4-bb16-044e1814d85c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117857216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4117857216
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1720476828
Short name T426
Test name
Test status
Simulation time 1839364605 ps
CPU time 15.12 seconds
Started Jul 04 06:38:34 PM PDT 24
Finished Jul 04 06:38:49 PM PDT 24
Peak memory 219108 kb
Host smart-6fb43f90-0496-4f7f-98ee-a654c6ffc71c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720476828 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1720476828
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2814017016
Short name T405
Test name
Test status
Simulation time 943910347 ps
CPU time 10.16 seconds
Started Jul 04 06:38:36 PM PDT 24
Finished Jul 04 06:38:46 PM PDT 24
Peak memory 218488 kb
Host smart-e7942504-1bc1-4c37-9058-4b3a80bff955
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814017016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2814017016
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3374377938
Short name T378
Test name
Test status
Simulation time 3875362050 ps
CPU time 13.14 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:38:46 PM PDT 24
Peak memory 210668 kb
Host smart-96085431-4688-459f-86df-9c825b2c1d1d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374377938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3374377938
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2495131958
Short name T387
Test name
Test status
Simulation time 1726031588 ps
CPU time 6.94 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:38:39 PM PDT 24
Peak memory 210604 kb
Host smart-164b96d8-35d9-4ff2-a7a8-6871771532fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495131958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2495131958
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2748324897
Short name T404
Test name
Test status
Simulation time 14632922158 ps
CPU time 40.57 seconds
Started Jul 04 06:38:24 PM PDT 24
Finished Jul 04 06:39:05 PM PDT 24
Peak memory 210660 kb
Host smart-6e6b3e6c-33e1-4473-aaa0-e19f7ebe0514
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748324897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2748324897
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1197108105
Short name T435
Test name
Test status
Simulation time 3111958019 ps
CPU time 13.32 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:38:45 PM PDT 24
Peak memory 219064 kb
Host smart-76935d7d-0660-4374-ad28-d7b053d14cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197108105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1197108105
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1809129375
Short name T396
Test name
Test status
Simulation time 826548893 ps
CPU time 9.85 seconds
Started Jul 04 06:38:35 PM PDT 24
Finished Jul 04 06:38:45 PM PDT 24
Peak memory 219032 kb
Host smart-348068c7-73ed-4ade-ad2e-ee1f97edb824
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809129375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1809129375
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.72625984
Short name T444
Test name
Test status
Simulation time 319344500 ps
CPU time 36.2 seconds
Started Jul 04 06:38:31 PM PDT 24
Finished Jul 04 06:39:08 PM PDT 24
Peak memory 211376 kb
Host smart-b172e942-5c69-495c-8129-9ab60ad0362f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72625984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg
_err.72625984
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1982263901
Short name T388
Test name
Test status
Simulation time 361588678 ps
CPU time 6.28 seconds
Started Jul 04 06:38:34 PM PDT 24
Finished Jul 04 06:38:40 PM PDT 24
Peak memory 217196 kb
Host smart-eb516673-c7c2-4be8-b86c-b78d43820fed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982263901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1982263901
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2318274918
Short name T417
Test name
Test status
Simulation time 4256030474 ps
CPU time 10.32 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:38:43 PM PDT 24
Peak memory 217704 kb
Host smart-bf95ada4-3790-45f2-b980-5a7781b73f09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318274918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2318274918
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2737760389
Short name T460
Test name
Test status
Simulation time 324011186 ps
CPU time 7.78 seconds
Started Jul 04 06:38:34 PM PDT 24
Finished Jul 04 06:38:42 PM PDT 24
Peak memory 218612 kb
Host smart-4e4df614-b9b4-4495-8bc8-5c1f6f8ffbfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737760389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2737760389
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3801302438
Short name T383
Test name
Test status
Simulation time 101708833 ps
CPU time 4.93 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:38:37 PM PDT 24
Peak memory 219112 kb
Host smart-3cb7b757-ef5d-45f3-9bcf-d2c2b450fdea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801302438 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3801302438
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2735889964
Short name T77
Test name
Test status
Simulation time 232021913 ps
CPU time 4.27 seconds
Started Jul 04 06:38:31 PM PDT 24
Finished Jul 04 06:38:36 PM PDT 24
Peak memory 210724 kb
Host smart-5d5df0cf-9928-4c4a-8126-df235bcaaa4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735889964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2735889964
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1913753538
Short name T446
Test name
Test status
Simulation time 7279093519 ps
CPU time 15.07 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:38:47 PM PDT 24
Peak memory 210652 kb
Host smart-f38f55a5-4103-412d-ae13-14d0ae50c842
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913753538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1913753538
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.422022135
Short name T455
Test name
Test status
Simulation time 5483243258 ps
CPU time 12.02 seconds
Started Jul 04 06:38:29 PM PDT 24
Finished Jul 04 06:38:42 PM PDT 24
Peak memory 210712 kb
Host smart-7bacb78d-bec1-4909-875f-fb16448ae4f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422022135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
422022135
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4115082517
Short name T386
Test name
Test status
Simulation time 699097784 ps
CPU time 19.11 seconds
Started Jul 04 06:38:34 PM PDT 24
Finished Jul 04 06:38:53 PM PDT 24
Peak memory 210784 kb
Host smart-07444655-7e07-45d4-8559-964b0c2a8693
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115082517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4115082517
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4270307861
Short name T398
Test name
Test status
Simulation time 85554389 ps
CPU time 4.3 seconds
Started Jul 04 06:38:31 PM PDT 24
Finished Jul 04 06:38:36 PM PDT 24
Peak memory 210768 kb
Host smart-acbbb10f-c0ab-4233-8da4-29cc53688ed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270307861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4270307861
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3202323649
Short name T401
Test name
Test status
Simulation time 8638340730 ps
CPU time 18.8 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:38:51 PM PDT 24
Peak memory 219088 kb
Host smart-aff3b62d-1be2-41eb-8f71-71b222fbb9de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202323649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3202323649
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.103779055
Short name T458
Test name
Test status
Simulation time 956967220 ps
CPU time 10.71 seconds
Started Jul 04 06:39:13 PM PDT 24
Finished Jul 04 06:39:24 PM PDT 24
Peak memory 219096 kb
Host smart-c84c8415-16e2-4441-94ec-b4cc830dc2a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103779055 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.103779055
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4024234389
Short name T76
Test name
Test status
Simulation time 461231866 ps
CPU time 4.25 seconds
Started Jul 04 06:38:59 PM PDT 24
Finished Jul 04 06:39:03 PM PDT 24
Peak memory 210708 kb
Host smart-c29a4751-3940-4ce4-aa64-42dc7bacffd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024234389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4024234389
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2646734785
Short name T58
Test name
Test status
Simulation time 128720100167 ps
CPU time 96.54 seconds
Started Jul 04 06:38:59 PM PDT 24
Finished Jul 04 06:40:35 PM PDT 24
Peak memory 210800 kb
Host smart-26cff5a5-2675-4c95-89c1-f778c8e0922f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646734785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2646734785
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1954489682
Short name T457
Test name
Test status
Simulation time 401086478 ps
CPU time 6.3 seconds
Started Jul 04 06:39:03 PM PDT 24
Finished Jul 04 06:39:09 PM PDT 24
Peak memory 210892 kb
Host smart-bd4cba96-90ce-4be1-a604-c6b79f7b6504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954489682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1954489682
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.590804373
Short name T424
Test name
Test status
Simulation time 309837822 ps
CPU time 7.21 seconds
Started Jul 04 06:38:58 PM PDT 24
Finished Jul 04 06:39:06 PM PDT 24
Peak memory 219048 kb
Host smart-eb4788e3-bf9d-41df-8d4c-4e36cc512dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590804373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.590804373
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1726764628
Short name T55
Test name
Test status
Simulation time 325830444 ps
CPU time 37.12 seconds
Started Jul 04 06:39:01 PM PDT 24
Finished Jul 04 06:39:38 PM PDT 24
Peak memory 218996 kb
Host smart-6ff6d8c7-5e3a-418d-93cf-7d9b866c6987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726764628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1726764628
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2413489184
Short name T371
Test name
Test status
Simulation time 7199013302 ps
CPU time 9.77 seconds
Started Jul 04 06:39:07 PM PDT 24
Finished Jul 04 06:39:17 PM PDT 24
Peak memory 219164 kb
Host smart-2de1eba5-87a6-49c6-96a6-f382cef9cb5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413489184 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2413489184
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.369687365
Short name T440
Test name
Test status
Simulation time 1766968147 ps
CPU time 13.73 seconds
Started Jul 04 06:39:07 PM PDT 24
Finished Jul 04 06:39:21 PM PDT 24
Peak memory 210712 kb
Host smart-d74ee153-fe2b-4e8b-827f-122d6f0c2947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369687365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.369687365
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1294383013
Short name T382
Test name
Test status
Simulation time 8473152377 ps
CPU time 68.75 seconds
Started Jul 04 06:39:07 PM PDT 24
Finished Jul 04 06:40:16 PM PDT 24
Peak memory 210760 kb
Host smart-1adc1ab5-544e-4aea-989b-2657642eec00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294383013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1294383013
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.780946108
Short name T407
Test name
Test status
Simulation time 753651780 ps
CPU time 4.25 seconds
Started Jul 04 06:39:08 PM PDT 24
Finished Jul 04 06:39:12 PM PDT 24
Peak memory 210816 kb
Host smart-646b19ae-cc4d-4b76-8c5f-76458705a9ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780946108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.780946108
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.584850046
Short name T452
Test name
Test status
Simulation time 401607166 ps
CPU time 8.15 seconds
Started Jul 04 06:39:08 PM PDT 24
Finished Jul 04 06:39:16 PM PDT 24
Peak memory 219044 kb
Host smart-6f7a70a5-9761-4afc-80b8-54bd23b84a58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584850046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.584850046
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2673072251
Short name T450
Test name
Test status
Simulation time 4024503312 ps
CPU time 41.92 seconds
Started Jul 04 06:39:05 PM PDT 24
Finished Jul 04 06:39:48 PM PDT 24
Peak memory 219044 kb
Host smart-81f7a666-e8e0-4993-bd29-6c7b8081b079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673072251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2673072251
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2746061817
Short name T442
Test name
Test status
Simulation time 103383966 ps
CPU time 4.98 seconds
Started Jul 04 06:39:06 PM PDT 24
Finished Jul 04 06:39:11 PM PDT 24
Peak memory 219076 kb
Host smart-d0ebb909-7cc1-47f1-80db-b3937f0e3c63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746061817 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2746061817
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.198512842
Short name T68
Test name
Test status
Simulation time 2863062140 ps
CPU time 15.6 seconds
Started Jul 04 06:39:05 PM PDT 24
Finished Jul 04 06:39:21 PM PDT 24
Peak memory 210764 kb
Host smart-09e5be1c-f484-42ce-b291-2fcb38577750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198512842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.198512842
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1389532231
Short name T63
Test name
Test status
Simulation time 549894976 ps
CPU time 28.05 seconds
Started Jul 04 06:39:07 PM PDT 24
Finished Jul 04 06:39:35 PM PDT 24
Peak memory 210776 kb
Host smart-cf019c27-f02f-40f8-bb71-4f0d739703ab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389532231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1389532231
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2759086504
Short name T95
Test name
Test status
Simulation time 378899374 ps
CPU time 6.04 seconds
Started Jul 04 06:39:05 PM PDT 24
Finished Jul 04 06:39:12 PM PDT 24
Peak memory 210828 kb
Host smart-63cb4d49-70b0-4c9d-987e-2c9cd8f09bf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759086504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2759086504
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3243673662
Short name T429
Test name
Test status
Simulation time 2202672855 ps
CPU time 19.44 seconds
Started Jul 04 06:39:05 PM PDT 24
Finished Jul 04 06:39:25 PM PDT 24
Peak memory 219096 kb
Host smart-8cc63615-df19-4cee-9373-1490e8e57200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243673662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3243673662
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2983585165
Short name T376
Test name
Test status
Simulation time 718457085 ps
CPU time 9.26 seconds
Started Jul 04 06:39:07 PM PDT 24
Finished Jul 04 06:39:16 PM PDT 24
Peak memory 219084 kb
Host smart-9e7b31f9-1e4e-4cb2-a278-8c71dedd906f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983585165 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2983585165
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4001391345
Short name T437
Test name
Test status
Simulation time 788359648 ps
CPU time 9.13 seconds
Started Jul 04 06:39:07 PM PDT 24
Finished Jul 04 06:39:17 PM PDT 24
Peak memory 210716 kb
Host smart-39413237-7b0e-4009-9d3e-71f3cceca0d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001391345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4001391345
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1878874903
Short name T97
Test name
Test status
Simulation time 1282952184 ps
CPU time 11.93 seconds
Started Jul 04 06:39:10 PM PDT 24
Finished Jul 04 06:39:22 PM PDT 24
Peak memory 210868 kb
Host smart-db732429-b87c-4137-b6ee-0107f8c72e7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878874903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1878874903
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3087398553
Short name T373
Test name
Test status
Simulation time 455550010 ps
CPU time 11.66 seconds
Started Jul 04 06:39:09 PM PDT 24
Finished Jul 04 06:39:21 PM PDT 24
Peak memory 215708 kb
Host smart-cb90f4b5-b731-4914-91be-abbe183a3508
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087398553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3087398553
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2583555622
Short name T56
Test name
Test status
Simulation time 6304336757 ps
CPU time 75.83 seconds
Started Jul 04 06:39:07 PM PDT 24
Finished Jul 04 06:40:23 PM PDT 24
Peak memory 219092 kb
Host smart-d0e03327-2a50-4c00-8c86-4fa23a1a3de2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583555622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2583555622
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2607535344
Short name T439
Test name
Test status
Simulation time 1494712914 ps
CPU time 12.75 seconds
Started Jul 04 06:39:06 PM PDT 24
Finished Jul 04 06:39:19 PM PDT 24
Peak memory 216360 kb
Host smart-f6da4ea9-a4ea-446e-b8e1-b9eb39a0a046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607535344 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2607535344
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1518539462
Short name T436
Test name
Test status
Simulation time 2422932210 ps
CPU time 8.47 seconds
Started Jul 04 06:39:08 PM PDT 24
Finished Jul 04 06:39:17 PM PDT 24
Peak memory 219000 kb
Host smart-11e72acf-7aaa-40e7-bd33-b1a76c7a1542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518539462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1518539462
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3645451105
Short name T61
Test name
Test status
Simulation time 35510777341 ps
CPU time 69.12 seconds
Started Jul 04 06:39:06 PM PDT 24
Finished Jul 04 06:40:15 PM PDT 24
Peak memory 210860 kb
Host smart-5f7ec332-07fc-4c40-84f1-b408b6d97c53
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645451105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3645451105
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1682470129
Short name T99
Test name
Test status
Simulation time 422945678 ps
CPU time 5.79 seconds
Started Jul 04 06:39:04 PM PDT 24
Finished Jul 04 06:39:10 PM PDT 24
Peak memory 210860 kb
Host smart-481c273e-d950-4828-8706-7225f2ebae95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682470129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1682470129
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1238482537
Short name T395
Test name
Test status
Simulation time 1352822181 ps
CPU time 15.97 seconds
Started Jul 04 06:39:13 PM PDT 24
Finished Jul 04 06:39:29 PM PDT 24
Peak memory 219036 kb
Host smart-99488f12-097f-4aac-bd8f-b589cb0b0b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238482537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1238482537
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3868403583
Short name T448
Test name
Test status
Simulation time 3477251732 ps
CPU time 11.48 seconds
Started Jul 04 06:39:07 PM PDT 24
Finished Jul 04 06:39:18 PM PDT 24
Peak memory 219196 kb
Host smart-d85c2e3f-982e-461e-b893-0acec8eb444e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868403583 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3868403583
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3717725798
Short name T65
Test name
Test status
Simulation time 347280074 ps
CPU time 4.31 seconds
Started Jul 04 06:39:07 PM PDT 24
Finished Jul 04 06:39:11 PM PDT 24
Peak memory 217868 kb
Host smart-649774d2-3612-4c04-b6d8-f04a9ba06043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717725798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3717725798
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1882954588
Short name T80
Test name
Test status
Simulation time 46601720475 ps
CPU time 98.1 seconds
Started Jul 04 06:39:06 PM PDT 24
Finished Jul 04 06:40:45 PM PDT 24
Peak memory 211876 kb
Host smart-de63ff14-7f74-43df-bb75-8fab97e1d33b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882954588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1882954588
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.233983616
Short name T423
Test name
Test status
Simulation time 1035187463 ps
CPU time 5.41 seconds
Started Jul 04 06:39:09 PM PDT 24
Finished Jul 04 06:39:15 PM PDT 24
Peak memory 218092 kb
Host smart-e4fcd303-9b29-4138-9c25-120b1a523f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233983616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.233983616
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1276211374
Short name T392
Test name
Test status
Simulation time 209151511 ps
CPU time 6.74 seconds
Started Jul 04 06:39:06 PM PDT 24
Finished Jul 04 06:39:13 PM PDT 24
Peak memory 219028 kb
Host smart-ed7ad43d-ee8a-42fd-9f10-c3c45e3f4f34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276211374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1276211374
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3352924539
Short name T108
Test name
Test status
Simulation time 1468192099 ps
CPU time 72.99 seconds
Started Jul 04 06:39:07 PM PDT 24
Finished Jul 04 06:40:20 PM PDT 24
Peak memory 212272 kb
Host smart-7e0276fa-4be8-4f4d-b665-60837ac2788e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352924539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3352924539
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1997421214
Short name T468
Test name
Test status
Simulation time 1935956413 ps
CPU time 12.6 seconds
Started Jul 04 06:39:14 PM PDT 24
Finished Jul 04 06:39:27 PM PDT 24
Peak memory 212616 kb
Host smart-2c01f764-13d1-4ce9-b82c-c4b77f252b95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997421214 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1997421214
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2481962688
Short name T409
Test name
Test status
Simulation time 1089065565 ps
CPU time 10.7 seconds
Started Jul 04 06:39:14 PM PDT 24
Finished Jul 04 06:39:25 PM PDT 24
Peak memory 210804 kb
Host smart-ac32ea81-07ab-498c-87de-6e086edaffc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481962688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2481962688
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1368966200
Short name T102
Test name
Test status
Simulation time 12815766470 ps
CPU time 63.26 seconds
Started Jul 04 06:39:10 PM PDT 24
Finished Jul 04 06:40:14 PM PDT 24
Peak memory 210856 kb
Host smart-9cba936f-2978-470f-8a8f-256b49744341
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368966200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1368966200
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1247190321
Short name T96
Test name
Test status
Simulation time 3412503697 ps
CPU time 10.02 seconds
Started Jul 04 06:39:12 PM PDT 24
Finished Jul 04 06:39:22 PM PDT 24
Peak memory 210844 kb
Host smart-39e00bd6-724d-4ce6-8795-9097efdc37f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247190321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1247190321
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1595782120
Short name T430
Test name
Test status
Simulation time 760191660 ps
CPU time 11.67 seconds
Started Jul 04 06:39:13 PM PDT 24
Finished Jul 04 06:39:25 PM PDT 24
Peak memory 219036 kb
Host smart-a738ff95-9562-49f4-b4dc-2572bd1806df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595782120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1595782120
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2533560117
Short name T443
Test name
Test status
Simulation time 2307786299 ps
CPU time 41.71 seconds
Started Jul 04 06:39:15 PM PDT 24
Finished Jul 04 06:39:57 PM PDT 24
Peak memory 211324 kb
Host smart-894436b5-a08d-4d8b-828b-9f09d061b917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533560117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2533560117
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2756221628
Short name T390
Test name
Test status
Simulation time 11388369797 ps
CPU time 14.01 seconds
Started Jul 04 06:39:22 PM PDT 24
Finished Jul 04 06:39:37 PM PDT 24
Peak memory 219148 kb
Host smart-e40b378a-dc52-45e1-8ea3-28ba356b9b35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756221628 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2756221628
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4017096712
Short name T57
Test name
Test status
Simulation time 1701142435 ps
CPU time 13.69 seconds
Started Jul 04 06:39:20 PM PDT 24
Finished Jul 04 06:39:34 PM PDT 24
Peak memory 218760 kb
Host smart-50df99e4-68d5-40de-82bb-c314abc40d30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017096712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4017096712
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3832665724
Short name T82
Test name
Test status
Simulation time 6953008946 ps
CPU time 66.91 seconds
Started Jul 04 06:39:16 PM PDT 24
Finished Jul 04 06:40:23 PM PDT 24
Peak memory 210944 kb
Host smart-e0cfcf1d-761c-48f4-956c-65a2afd0e916
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832665724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3832665724
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1261709518
Short name T67
Test name
Test status
Simulation time 1778336334 ps
CPU time 5.29 seconds
Started Jul 04 06:39:20 PM PDT 24
Finished Jul 04 06:39:26 PM PDT 24
Peak memory 218508 kb
Host smart-002ca8da-17c8-44cc-92f7-7e33070b1add
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261709518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1261709518
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3897107984
Short name T377
Test name
Test status
Simulation time 85493061 ps
CPU time 7.14 seconds
Started Jul 04 06:39:13 PM PDT 24
Finished Jul 04 06:39:20 PM PDT 24
Peak memory 216688 kb
Host smart-b59d34e2-490a-4bff-8faf-bb82724c60a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897107984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3897107984
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.438746412
Short name T116
Test name
Test status
Simulation time 1270331430 ps
CPU time 37.6 seconds
Started Jul 04 06:39:20 PM PDT 24
Finished Jul 04 06:39:58 PM PDT 24
Peak memory 219000 kb
Host smart-478ba530-79b8-4d77-8d64-446e1bfa8e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438746412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.438746412
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.152038349
Short name T428
Test name
Test status
Simulation time 14481380015 ps
CPU time 14.9 seconds
Started Jul 04 06:39:23 PM PDT 24
Finished Jul 04 06:39:38 PM PDT 24
Peak memory 219092 kb
Host smart-95005042-e605-401e-952d-dc62731ed3d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152038349 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.152038349
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3139997050
Short name T411
Test name
Test status
Simulation time 517071463 ps
CPU time 7.28 seconds
Started Jul 04 06:39:20 PM PDT 24
Finished Jul 04 06:39:28 PM PDT 24
Peak memory 210740 kb
Host smart-bd88a16b-7d38-44a3-8d77-80614cd23747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139997050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3139997050
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2929005909
Short name T78
Test name
Test status
Simulation time 82191694766 ps
CPU time 74.53 seconds
Started Jul 04 06:39:22 PM PDT 24
Finished Jul 04 06:40:37 PM PDT 24
Peak memory 210840 kb
Host smart-7bd7c32c-a39a-4fa9-82a5-1d96e1c13895
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929005909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2929005909
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1959537219
Short name T94
Test name
Test status
Simulation time 1601604256 ps
CPU time 12.42 seconds
Started Jul 04 06:39:20 PM PDT 24
Finished Jul 04 06:39:32 PM PDT 24
Peak memory 218916 kb
Host smart-d9270637-a847-4122-995d-dfdd35ccd948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959537219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1959537219
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1472463848
Short name T379
Test name
Test status
Simulation time 3523651999 ps
CPU time 11.54 seconds
Started Jul 04 06:39:22 PM PDT 24
Finished Jul 04 06:39:34 PM PDT 24
Peak memory 219088 kb
Host smart-341f2e14-ab35-4af1-98d7-4b9508bf1760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472463848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1472463848
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1250318311
Short name T369
Test name
Test status
Simulation time 759698739 ps
CPU time 9.09 seconds
Started Jul 04 06:39:28 PM PDT 24
Finished Jul 04 06:39:37 PM PDT 24
Peak memory 219108 kb
Host smart-0dd93fe7-8950-4f59-a188-5b155b50803c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250318311 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1250318311
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2563056366
Short name T410
Test name
Test status
Simulation time 85448343 ps
CPU time 4.26 seconds
Started Jul 04 06:39:30 PM PDT 24
Finished Jul 04 06:39:34 PM PDT 24
Peak memory 210732 kb
Host smart-1b7216d2-f731-42e1-aec7-ef85ecd8bf59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563056366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2563056366
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4084972026
Short name T103
Test name
Test status
Simulation time 542238961 ps
CPU time 28.47 seconds
Started Jul 04 06:39:22 PM PDT 24
Finished Jul 04 06:39:51 PM PDT 24
Peak memory 210796 kb
Host smart-c1c7d495-0aab-48df-b9c9-9492b736a3f3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084972026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4084972026
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3899363331
Short name T403
Test name
Test status
Simulation time 2003425168 ps
CPU time 16.37 seconds
Started Jul 04 06:39:35 PM PDT 24
Finished Jul 04 06:39:51 PM PDT 24
Peak memory 218980 kb
Host smart-b2e4670b-b821-4eb9-9464-a71893f58772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899363331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3899363331
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1531787255
Short name T425
Test name
Test status
Simulation time 309391287 ps
CPU time 7.44 seconds
Started Jul 04 06:39:21 PM PDT 24
Finished Jul 04 06:39:29 PM PDT 24
Peak memory 219020 kb
Host smart-9e82bb1d-a5cd-4356-b6a9-865e20500a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531787255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1531787255
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1347834621
Short name T114
Test name
Test status
Simulation time 2258636975 ps
CPU time 48.13 seconds
Started Jul 04 06:39:29 PM PDT 24
Finished Jul 04 06:40:17 PM PDT 24
Peak memory 211196 kb
Host smart-6f99fb6d-76a5-4607-95bb-d2699c3dafef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347834621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1347834621
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1127986642
Short name T467
Test name
Test status
Simulation time 346214996 ps
CPU time 4.26 seconds
Started Jul 04 06:38:38 PM PDT 24
Finished Jul 04 06:38:43 PM PDT 24
Peak memory 210792 kb
Host smart-210216b3-5697-49f7-b7a8-130063093cda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127986642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1127986642
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.736838025
Short name T416
Test name
Test status
Simulation time 2117251707 ps
CPU time 17.33 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:38:56 PM PDT 24
Peak memory 210796 kb
Host smart-13a91e44-11eb-4a72-a838-d76438ee0c8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736838025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.736838025
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2189237215
Short name T402
Test name
Test status
Simulation time 6889514915 ps
CPU time 15.48 seconds
Started Jul 04 06:38:31 PM PDT 24
Finished Jul 04 06:38:46 PM PDT 24
Peak memory 210772 kb
Host smart-1f1b64ce-bfd4-4996-8c84-54dde2f41634
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189237215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2189237215
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.92502559
Short name T427
Test name
Test status
Simulation time 299030636 ps
CPU time 6.69 seconds
Started Jul 04 06:38:40 PM PDT 24
Finished Jul 04 06:38:47 PM PDT 24
Peak memory 219028 kb
Host smart-6f2ff0e5-2c60-4098-a333-b50b9a4ee533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92502559 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.92502559
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3791977787
Short name T431
Test name
Test status
Simulation time 2140703865 ps
CPU time 15.68 seconds
Started Jul 04 06:38:36 PM PDT 24
Finished Jul 04 06:38:52 PM PDT 24
Peak memory 210784 kb
Host smart-cbefe3df-e006-4582-a50a-715370f24f53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791977787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3791977787
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1998620539
Short name T397
Test name
Test status
Simulation time 3339264249 ps
CPU time 13.56 seconds
Started Jul 04 06:38:33 PM PDT 24
Finished Jul 04 06:38:47 PM PDT 24
Peak memory 210624 kb
Host smart-12df704f-a7e9-49e5-ac90-2e73464d8b99
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998620539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1998620539
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4288045682
Short name T393
Test name
Test status
Simulation time 1974315256 ps
CPU time 7.62 seconds
Started Jul 04 06:38:33 PM PDT 24
Finished Jul 04 06:38:41 PM PDT 24
Peak memory 210564 kb
Host smart-dc94a69a-7545-4d39-ad08-db7cbc177590
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288045682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4288045682
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3547981443
Short name T391
Test name
Test status
Simulation time 6550859653 ps
CPU time 13.87 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:38:53 PM PDT 24
Peak memory 211088 kb
Host smart-fec7cd90-7b31-42bc-930d-0faee32312a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547981443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3547981443
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1034125291
Short name T464
Test name
Test status
Simulation time 7545937334 ps
CPU time 17.9 seconds
Started Jul 04 06:38:32 PM PDT 24
Finished Jul 04 06:38:50 PM PDT 24
Peak memory 219128 kb
Host smart-5ed2cd75-3f8f-46f3-a2b5-38add9f4279d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034125291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1034125291
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.276552829
Short name T456
Test name
Test status
Simulation time 1420534829 ps
CPU time 43.82 seconds
Started Jul 04 06:38:36 PM PDT 24
Finished Jul 04 06:39:20 PM PDT 24
Peak memory 212048 kb
Host smart-b5941a29-9c7c-43c6-8b59-ae7ebe10fcc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276552829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.276552829
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2034917062
Short name T463
Test name
Test status
Simulation time 4104034015 ps
CPU time 10.42 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:38:49 PM PDT 24
Peak memory 217836 kb
Host smart-3f7a08de-3264-4a94-a7e4-a02a4ab32597
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034917062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2034917062
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1827104675
Short name T422
Test name
Test status
Simulation time 6752727671 ps
CPU time 9.29 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:38:49 PM PDT 24
Peak memory 210868 kb
Host smart-d9a62c25-1c1a-4e70-8f48-42c0e0630e40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827104675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1827104675
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.203345179
Short name T432
Test name
Test status
Simulation time 1864398210 ps
CPU time 15.91 seconds
Started Jul 04 06:38:40 PM PDT 24
Finished Jul 04 06:38:56 PM PDT 24
Peak memory 210748 kb
Host smart-2cda5463-2819-4857-95d6-172fb2e228fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203345179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.203345179
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4377803
Short name T451
Test name
Test status
Simulation time 2114477382 ps
CPU time 10.73 seconds
Started Jul 04 06:38:40 PM PDT 24
Finished Jul 04 06:38:51 PM PDT 24
Peak memory 219024 kb
Host smart-bf968a15-3bf6-42e2-99e0-9fa76e985ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4377803 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4377803
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3342492381
Short name T380
Test name
Test status
Simulation time 3491352567 ps
CPU time 15.57 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:38:55 PM PDT 24
Peak memory 210860 kb
Host smart-6b271ec6-8f08-475e-8f7d-ab5934816828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342492381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3342492381
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.275540299
Short name T374
Test name
Test status
Simulation time 726354884 ps
CPU time 8.71 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:38:48 PM PDT 24
Peak memory 210636 kb
Host smart-f7144e68-5f69-4596-8b92-6140a0c49dae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275540299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.275540299
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2949870796
Short name T465
Test name
Test status
Simulation time 1645374846 ps
CPU time 13.62 seconds
Started Jul 04 06:38:38 PM PDT 24
Finished Jul 04 06:38:52 PM PDT 24
Peak memory 210652 kb
Host smart-49694f03-f8aa-4c43-b889-6fb13a2f90ed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949870796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2949870796
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1725497826
Short name T62
Test name
Test status
Simulation time 376571070 ps
CPU time 18.98 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:38:58 PM PDT 24
Peak memory 210820 kb
Host smart-2ca177c1-f891-48fe-9b94-fd47fdcc8058
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725497826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1725497826
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.582580652
Short name T98
Test name
Test status
Simulation time 1203810492 ps
CPU time 11.51 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:38:50 PM PDT 24
Peak memory 210864 kb
Host smart-77196b28-27b8-40d3-abe6-749809fa6092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582580652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.582580652
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.659801524
Short name T370
Test name
Test status
Simulation time 7488778126 ps
CPU time 19.41 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:38:59 PM PDT 24
Peak memory 219072 kb
Host smart-633491dd-0654-47db-b1bb-8372736b13c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659801524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.659801524
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1787433813
Short name T445
Test name
Test status
Simulation time 3162543417 ps
CPU time 43.05 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:39:23 PM PDT 24
Peak memory 219044 kb
Host smart-cd36e62c-4929-48cc-a7b8-05492161a664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787433813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1787433813
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2717226421
Short name T101
Test name
Test status
Simulation time 379757272 ps
CPU time 4.32 seconds
Started Jul 04 06:38:48 PM PDT 24
Finished Jul 04 06:38:53 PM PDT 24
Peak memory 217876 kb
Host smart-61115297-444b-4f2b-a2f3-3f70f9e66ffa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717226421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2717226421
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2393135904
Short name T461
Test name
Test status
Simulation time 1884433510 ps
CPU time 16.08 seconds
Started Jul 04 06:38:48 PM PDT 24
Finished Jul 04 06:39:05 PM PDT 24
Peak memory 210800 kb
Host smart-0dddd4ad-0bab-44d0-a106-411ee0794f9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393135904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2393135904
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3826930906
Short name T81
Test name
Test status
Simulation time 8922409145 ps
CPU time 11.22 seconds
Started Jul 04 06:38:47 PM PDT 24
Finished Jul 04 06:38:58 PM PDT 24
Peak memory 218908 kb
Host smart-9f381248-97b8-419e-a374-9c29441413aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826930906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3826930906
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1089732374
Short name T453
Test name
Test status
Simulation time 1682214453 ps
CPU time 14.59 seconds
Started Jul 04 06:38:49 PM PDT 24
Finished Jul 04 06:39:04 PM PDT 24
Peak memory 219108 kb
Host smart-7b63a21e-b4ff-42ef-ab96-714c2fb26a4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089732374 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1089732374
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3796875322
Short name T462
Test name
Test status
Simulation time 5779305777 ps
CPU time 6.27 seconds
Started Jul 04 06:38:49 PM PDT 24
Finished Jul 04 06:38:56 PM PDT 24
Peak memory 210868 kb
Host smart-45397053-2cae-4545-b7e2-56591bb91073
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796875322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3796875322
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3745093735
Short name T459
Test name
Test status
Simulation time 214826830 ps
CPU time 5.71 seconds
Started Jul 04 06:38:47 PM PDT 24
Finished Jul 04 06:38:53 PM PDT 24
Peak memory 210536 kb
Host smart-4e7e11a6-29f6-4bfc-94b2-acb9e1151a41
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745093735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3745093735
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2289234120
Short name T406
Test name
Test status
Simulation time 1271205064 ps
CPU time 8.01 seconds
Started Jul 04 06:38:46 PM PDT 24
Finished Jul 04 06:38:54 PM PDT 24
Peak memory 210656 kb
Host smart-4272ae15-170e-4ff8-a4f0-e94e355055fb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289234120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2289234120
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.968651171
Short name T74
Test name
Test status
Simulation time 18547971996 ps
CPU time 46.31 seconds
Started Jul 04 06:38:39 PM PDT 24
Finished Jul 04 06:39:26 PM PDT 24
Peak memory 217952 kb
Host smart-81234db3-6a14-4e5c-a4e7-2ada7172f488
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968651171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.968651171
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4155663297
Short name T413
Test name
Test status
Simulation time 1908362271 ps
CPU time 14.85 seconds
Started Jul 04 06:38:49 PM PDT 24
Finished Jul 04 06:39:04 PM PDT 24
Peak memory 210876 kb
Host smart-c5e12591-49d0-4179-b1a2-afa735efadce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155663297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4155663297
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2067713622
Short name T454
Test name
Test status
Simulation time 4122471166 ps
CPU time 16.56 seconds
Started Jul 04 06:38:40 PM PDT 24
Finished Jul 04 06:38:56 PM PDT 24
Peak memory 219124 kb
Host smart-a35b35cc-0592-40ec-b1b9-fc5e12478193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067713622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2067713622
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1685841613
Short name T408
Test name
Test status
Simulation time 6067739833 ps
CPU time 9.29 seconds
Started Jul 04 06:38:55 PM PDT 24
Finished Jul 04 06:39:04 PM PDT 24
Peak memory 219060 kb
Host smart-1f453193-fec2-4111-9f56-f104f63749ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685841613 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1685841613
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2387630267
Short name T79
Test name
Test status
Simulation time 7123075013 ps
CPU time 14.96 seconds
Started Jul 04 06:38:53 PM PDT 24
Finished Jul 04 06:39:08 PM PDT 24
Peak memory 210920 kb
Host smart-7f5e23e2-1da9-4526-adff-51c142024e3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387630267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2387630267
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3837321914
Short name T438
Test name
Test status
Simulation time 19075235283 ps
CPU time 47.57 seconds
Started Jul 04 06:38:46 PM PDT 24
Finished Jul 04 06:39:33 PM PDT 24
Peak memory 210852 kb
Host smart-e80161f1-e017-4b22-a437-082d694257b5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837321914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3837321914
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2763995287
Short name T466
Test name
Test status
Simulation time 216531373 ps
CPU time 7.58 seconds
Started Jul 04 06:38:53 PM PDT 24
Finished Jul 04 06:39:01 PM PDT 24
Peak memory 218972 kb
Host smart-5e6e86ad-ba70-4668-b8c4-b05c5651198f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763995287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2763995287
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2698166468
Short name T419
Test name
Test status
Simulation time 5871891585 ps
CPU time 17.67 seconds
Started Jul 04 06:38:49 PM PDT 24
Finished Jul 04 06:39:07 PM PDT 24
Peak memory 219100 kb
Host smart-07f76bda-4316-4fa1-8c1d-9e7d8402e0c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698166468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2698166468
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2859744164
Short name T418
Test name
Test status
Simulation time 10490009332 ps
CPU time 47.39 seconds
Started Jul 04 06:38:53 PM PDT 24
Finished Jul 04 06:39:41 PM PDT 24
Peak memory 219060 kb
Host smart-73e7bee8-fedd-4022-a45f-b09246b2d2b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859744164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2859744164
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.360580583
Short name T441
Test name
Test status
Simulation time 833630886 ps
CPU time 7.26 seconds
Started Jul 04 06:38:53 PM PDT 24
Finished Jul 04 06:39:00 PM PDT 24
Peak memory 219072 kb
Host smart-45d821ec-870a-4ed8-9208-5e3722caede5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360580583 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.360580583
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3981108464
Short name T434
Test name
Test status
Simulation time 12101451061 ps
CPU time 14.24 seconds
Started Jul 04 06:38:53 PM PDT 24
Finished Jul 04 06:39:08 PM PDT 24
Peak memory 210808 kb
Host smart-ecc4b7b4-c5ed-4ac4-b174-0bd7663ae158
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981108464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3981108464
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2387040779
Short name T394
Test name
Test status
Simulation time 42033388562 ps
CPU time 58.59 seconds
Started Jul 04 06:38:54 PM PDT 24
Finished Jul 04 06:39:53 PM PDT 24
Peak memory 210832 kb
Host smart-396a118e-7cff-45e5-8b8c-f21c02fc2ad5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387040779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2387040779
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1645826882
Short name T389
Test name
Test status
Simulation time 1506040360 ps
CPU time 14.56 seconds
Started Jul 04 06:38:54 PM PDT 24
Finished Jul 04 06:39:08 PM PDT 24
Peak memory 210852 kb
Host smart-d900c42c-57e9-4bd7-b5fc-d2c6516088be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645826882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1645826882
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.347214648
Short name T433
Test name
Test status
Simulation time 4818321428 ps
CPU time 17.74 seconds
Started Jul 04 06:38:55 PM PDT 24
Finished Jul 04 06:39:13 PM PDT 24
Peak memory 219092 kb
Host smart-c6205e11-ff22-4eb8-a2c8-26c6fb1f7076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347214648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.347214648
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3551905506
Short name T111
Test name
Test status
Simulation time 374208281 ps
CPU time 71.83 seconds
Started Jul 04 06:38:55 PM PDT 24
Finished Jul 04 06:40:07 PM PDT 24
Peak memory 212308 kb
Host smart-2c6019cf-4ed1-4bf0-948b-da8db0ab256c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551905506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3551905506
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3202115106
Short name T372
Test name
Test status
Simulation time 2083613664 ps
CPU time 16.13 seconds
Started Jul 04 06:39:00 PM PDT 24
Finished Jul 04 06:39:16 PM PDT 24
Peak memory 219116 kb
Host smart-43fd3ade-51d8-40d8-8978-f7afddc7fb73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202115106 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3202115106
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3718256614
Short name T421
Test name
Test status
Simulation time 761625147 ps
CPU time 8.81 seconds
Started Jul 04 06:39:03 PM PDT 24
Finished Jul 04 06:39:12 PM PDT 24
Peak memory 218664 kb
Host smart-299ce2d2-7631-4f7d-9c7e-953c3b897b5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718256614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3718256614
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3655334861
Short name T415
Test name
Test status
Simulation time 6866033012 ps
CPU time 37.89 seconds
Started Jul 04 06:38:58 PM PDT 24
Finished Jul 04 06:39:36 PM PDT 24
Peak memory 210856 kb
Host smart-946d7be1-6763-4d0f-9d88-de67307384c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655334861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3655334861
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1912796344
Short name T400
Test name
Test status
Simulation time 347210263 ps
CPU time 4.5 seconds
Started Jul 04 06:38:59 PM PDT 24
Finished Jul 04 06:39:04 PM PDT 24
Peak memory 210844 kb
Host smart-ea484662-5434-4827-98f2-913925bb6561
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912796344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1912796344
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4038558849
Short name T414
Test name
Test status
Simulation time 1281900250 ps
CPU time 15.81 seconds
Started Jul 04 06:38:58 PM PDT 24
Finished Jul 04 06:39:14 PM PDT 24
Peak memory 219020 kb
Host smart-a0620fd0-8c24-4470-af6b-8e977d36d012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038558849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4038558849
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.998005308
Short name T449
Test name
Test status
Simulation time 6653032778 ps
CPU time 12.76 seconds
Started Jul 04 06:39:00 PM PDT 24
Finished Jul 04 06:39:13 PM PDT 24
Peak memory 219136 kb
Host smart-c3ee7c33-fffa-4dd9-ad8c-7fc3dea4850f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998005308 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.998005308
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1580416369
Short name T385
Test name
Test status
Simulation time 2867399305 ps
CPU time 12.89 seconds
Started Jul 04 06:39:01 PM PDT 24
Finished Jul 04 06:39:14 PM PDT 24
Peak memory 210856 kb
Host smart-5670ae8d-003f-4dc3-a387-fc0b11eb67b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580416369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1580416369
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2217923976
Short name T75
Test name
Test status
Simulation time 3630812045 ps
CPU time 18.52 seconds
Started Jul 04 06:38:59 PM PDT 24
Finished Jul 04 06:39:18 PM PDT 24
Peak memory 210880 kb
Host smart-db53dd1c-f286-472f-85bd-4f783cb6482d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217923976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2217923976
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2930856698
Short name T93
Test name
Test status
Simulation time 121049421 ps
CPU time 4.43 seconds
Started Jul 04 06:39:01 PM PDT 24
Finished Jul 04 06:39:05 PM PDT 24
Peak memory 210836 kb
Host smart-fbf9c58f-1f3b-4990-9434-229e8b97e0c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930856698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2930856698
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1709834090
Short name T375
Test name
Test status
Simulation time 1645928768 ps
CPU time 16.77 seconds
Started Jul 04 06:39:04 PM PDT 24
Finished Jul 04 06:39:21 PM PDT 24
Peak memory 219068 kb
Host smart-9c4db207-7806-4930-8c8c-440d362dd7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709834090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1709834090
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3274416700
Short name T399
Test name
Test status
Simulation time 520803247 ps
CPU time 39.3 seconds
Started Jul 04 06:39:03 PM PDT 24
Finished Jul 04 06:39:43 PM PDT 24
Peak memory 211892 kb
Host smart-c09162eb-8391-44c5-805a-84e37ad3f55b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274416700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3274416700
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2255993503
Short name T412
Test name
Test status
Simulation time 103156396 ps
CPU time 4.88 seconds
Started Jul 04 06:38:58 PM PDT 24
Finished Jul 04 06:39:03 PM PDT 24
Peak memory 219080 kb
Host smart-9e3e5166-c9a2-4ddd-936e-c488a2b39abf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255993503 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2255993503
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.71752542
Short name T381
Test name
Test status
Simulation time 2064932851 ps
CPU time 7.5 seconds
Started Jul 04 06:39:00 PM PDT 24
Finished Jul 04 06:39:07 PM PDT 24
Peak memory 218016 kb
Host smart-d0d65aca-f8cf-4ee8-a9f0-09e00480dd9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71752542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.71752542
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3745361121
Short name T100
Test name
Test status
Simulation time 70427241794 ps
CPU time 68.17 seconds
Started Jul 04 06:39:00 PM PDT 24
Finished Jul 04 06:40:09 PM PDT 24
Peak memory 210876 kb
Host smart-907cea4a-8b8f-4ee3-9f9f-05edc84b3c6f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745361121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3745361121
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.535439263
Short name T447
Test name
Test status
Simulation time 172094938 ps
CPU time 4.43 seconds
Started Jul 04 06:38:58 PM PDT 24
Finished Jul 04 06:39:03 PM PDT 24
Peak memory 219008 kb
Host smart-999eef71-e53a-46cf-b0a0-bc2110c2621f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535439263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.535439263
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.273498510
Short name T384
Test name
Test status
Simulation time 1025755522 ps
CPU time 11.68 seconds
Started Jul 04 06:39:00 PM PDT 24
Finished Jul 04 06:39:12 PM PDT 24
Peak memory 219004 kb
Host smart-89f851cc-ee50-42e1-b860-ac47e362ca6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273498510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.273498510
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2630321306
Short name T117
Test name
Test status
Simulation time 4920330384 ps
CPU time 39.48 seconds
Started Jul 04 06:38:58 PM PDT 24
Finished Jul 04 06:39:38 PM PDT 24
Peak memory 219032 kb
Host smart-4b2aca8c-1c2e-42fc-b00b-fd5b299a0329
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630321306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2630321306
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.643732597
Short name T292
Test name
Test status
Simulation time 89159094 ps
CPU time 4.37 seconds
Started Jul 04 05:10:22 PM PDT 24
Finished Jul 04 05:10:27 PM PDT 24
Peak memory 211264 kb
Host smart-9dc29796-7f69-4157-92a6-4616c746c851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643732597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.643732597
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3159348161
Short name T288
Test name
Test status
Simulation time 1233047023 ps
CPU time 66.92 seconds
Started Jul 04 05:10:29 PM PDT 24
Finished Jul 04 05:11:36 PM PDT 24
Peak memory 228388 kb
Host smart-ce8ed8a9-6eed-411c-8e2e-ab154c480127
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159348161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3159348161
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1247901791
Short name T245
Test name
Test status
Simulation time 11506474812 ps
CPU time 25.49 seconds
Started Jul 04 05:10:30 PM PDT 24
Finished Jul 04 05:10:56 PM PDT 24
Peak memory 212540 kb
Host smart-dee3ba4f-db2c-4c07-b9d8-204550695aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247901791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1247901791
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2730628497
Short name T286
Test name
Test status
Simulation time 22146482829 ps
CPU time 15.24 seconds
Started Jul 04 05:10:34 PM PDT 24
Finished Jul 04 05:10:49 PM PDT 24
Peak memory 211428 kb
Host smart-8e07022e-9558-4f58-8168-829a471f0d17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730628497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2730628497
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1396590155
Short name T30
Test name
Test status
Simulation time 2910360950 ps
CPU time 100.29 seconds
Started Jul 04 05:10:30 PM PDT 24
Finished Jul 04 05:12:10 PM PDT 24
Peak memory 236748 kb
Host smart-aaff850b-8ba3-4b27-b6fc-bbfab4fa0648
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396590155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1396590155
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.280898993
Short name T224
Test name
Test status
Simulation time 751478520 ps
CPU time 9.69 seconds
Started Jul 04 05:10:30 PM PDT 24
Finished Jul 04 05:10:40 PM PDT 24
Peak memory 213448 kb
Host smart-6127bdc9-d316-4fdc-afa2-01a68a14525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280898993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.280898993
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.609781330
Short name T15
Test name
Test status
Simulation time 17485314334 ps
CPU time 72.12 seconds
Started Jul 04 05:10:30 PM PDT 24
Finished Jul 04 05:11:43 PM PDT 24
Peak memory 216776 kb
Host smart-15236797-8d2c-4aa3-9af0-454c84db2ae9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609781330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.609781330
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1613422587
Short name T49
Test name
Test status
Simulation time 46103107599 ps
CPU time 2235.49 seconds
Started Jul 04 05:10:29 PM PDT 24
Finished Jul 04 05:47:46 PM PDT 24
Peak memory 233852 kb
Host smart-ab506c04-ebe0-4d6a-8487-7d59bc2172ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613422587 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1613422587
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3024402040
Short name T290
Test name
Test status
Simulation time 1907484056 ps
CPU time 15.29 seconds
Started Jul 04 05:10:38 PM PDT 24
Finished Jul 04 05:10:53 PM PDT 24
Peak memory 211192 kb
Host smart-f24ebd03-cfb5-40f6-8c14-0578308b8ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024402040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3024402040
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2202679350
Short name T281
Test name
Test status
Simulation time 22565542942 ps
CPU time 258.5 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:14:55 PM PDT 24
Peak memory 213552 kb
Host smart-ced3450f-0bc3-4a18-b1ba-9aa2de6801bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202679350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2202679350
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1475907006
Short name T352
Test name
Test status
Simulation time 5129867396 ps
CPU time 25.02 seconds
Started Jul 04 05:10:33 PM PDT 24
Finished Jul 04 05:10:58 PM PDT 24
Peak memory 212236 kb
Host smart-0fc4d5fb-b18a-4871-805b-7c147be32306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475907006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1475907006
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3803005317
Short name T336
Test name
Test status
Simulation time 839296907 ps
CPU time 10.31 seconds
Started Jul 04 05:10:31 PM PDT 24
Finished Jul 04 05:10:41 PM PDT 24
Peak memory 211240 kb
Host smart-55a186f2-95f0-42fe-a1aa-eaa00e5ecb23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803005317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3803005317
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3179289995
Short name T29
Test name
Test status
Simulation time 748530649 ps
CPU time 99.57 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:12:17 PM PDT 24
Peak memory 236020 kb
Host smart-e01e55bf-713a-497d-9568-16dc62e957bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179289995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3179289995
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1017623954
Short name T329
Test name
Test status
Simulation time 5864052586 ps
CPU time 28.87 seconds
Started Jul 04 05:10:27 PM PDT 24
Finished Jul 04 05:10:56 PM PDT 24
Peak memory 214548 kb
Host smart-50f0eccd-d3a6-434e-a036-8cbc42db6dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017623954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1017623954
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.118900227
Short name T283
Test name
Test status
Simulation time 10446120098 ps
CPU time 34.13 seconds
Started Jul 04 05:10:29 PM PDT 24
Finished Jul 04 05:11:04 PM PDT 24
Peak memory 216924 kb
Host smart-cb38b2dc-ef90-49b4-be73-aa5a999b5cdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118900227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.118900227
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1743053225
Short name T345
Test name
Test status
Simulation time 1629982510 ps
CPU time 10.6 seconds
Started Jul 04 05:10:48 PM PDT 24
Finished Jul 04 05:10:59 PM PDT 24
Peak memory 211320 kb
Host smart-695f2723-960c-4532-ab31-a77780799c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743053225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1743053225
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.281687791
Short name T38
Test name
Test status
Simulation time 16230887700 ps
CPU time 188.18 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:13:58 PM PDT 24
Peak memory 237912 kb
Host smart-e2fd3828-ed68-4221-9d11-b6059845397d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281687791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.281687791
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.750759191
Short name T27
Test name
Test status
Simulation time 8150176631 ps
CPU time 25.71 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:11:15 PM PDT 24
Peak memory 212572 kb
Host smart-222212b4-f5e2-4812-b3cb-e4fa610218a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750759191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.750759191
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1597011344
Short name T105
Test name
Test status
Simulation time 2414690136 ps
CPU time 13.68 seconds
Started Jul 04 05:10:42 PM PDT 24
Finished Jul 04 05:10:56 PM PDT 24
Peak memory 211396 kb
Host smart-4c1a17ba-2a14-40a0-9b07-46a83ed56d24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597011344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1597011344
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1405332424
Short name T344
Test name
Test status
Simulation time 188577916 ps
CPU time 10.2 seconds
Started Jul 04 05:10:42 PM PDT 24
Finished Jul 04 05:10:52 PM PDT 24
Peak memory 213740 kb
Host smart-0c9e9e95-2276-4b9b-8b8a-a4884f9fb561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405332424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1405332424
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1826166680
Short name T132
Test name
Test status
Simulation time 4041687845 ps
CPU time 34.68 seconds
Started Jul 04 05:10:48 PM PDT 24
Finished Jul 04 05:11:23 PM PDT 24
Peak memory 213784 kb
Host smart-e5d08088-678d-4078-ab0f-84865654c0c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826166680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1826166680
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1300988331
Short name T269
Test name
Test status
Simulation time 879701521 ps
CPU time 10.54 seconds
Started Jul 04 05:10:51 PM PDT 24
Finished Jul 04 05:11:02 PM PDT 24
Peak memory 211264 kb
Host smart-7685e262-a51b-49ef-ac4b-56e8275121e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300988331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1300988331
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1145314177
Short name T256
Test name
Test status
Simulation time 4609030575 ps
CPU time 23.71 seconds
Started Jul 04 05:10:44 PM PDT 24
Finished Jul 04 05:11:08 PM PDT 24
Peak memory 212372 kb
Host smart-b3765162-8d4f-4edc-9f32-0371827a3bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145314177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1145314177
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3117092713
Short name T272
Test name
Test status
Simulation time 99219449 ps
CPU time 5.5 seconds
Started Jul 04 05:10:48 PM PDT 24
Finished Jul 04 05:10:54 PM PDT 24
Peak memory 211336 kb
Host smart-0cf46e53-99b4-440b-bcb8-a57f4ba22898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117092713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3117092713
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3894642147
Short name T197
Test name
Test status
Simulation time 6578612171 ps
CPU time 28.37 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:22 PM PDT 24
Peak memory 214708 kb
Host smart-86263716-462d-469a-a45c-f31b23dd9a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894642147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3894642147
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3541918032
Short name T217
Test name
Test status
Simulation time 7775498273 ps
CPU time 51.62 seconds
Started Jul 04 05:10:43 PM PDT 24
Finished Jul 04 05:11:35 PM PDT 24
Peak memory 217636 kb
Host smart-6af1cd34-4882-4e54-9b2b-398a56067aaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541918032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3541918032
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3456230768
Short name T53
Test name
Test status
Simulation time 47660134308 ps
CPU time 954.45 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:26:45 PM PDT 24
Peak memory 235832 kb
Host smart-73f444ba-fd56-4ed4-beb7-f52b4387b95d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456230768 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3456230768
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.484700828
Short name T37
Test name
Test status
Simulation time 85443814 ps
CPU time 4.49 seconds
Started Jul 04 05:10:54 PM PDT 24
Finished Jul 04 05:10:59 PM PDT 24
Peak memory 211208 kb
Host smart-bb3cb1e7-ca4b-484f-a0d9-d19d19a91e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484700828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.484700828
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1966177802
Short name T90
Test name
Test status
Simulation time 16898155970 ps
CPU time 101.41 seconds
Started Jul 04 05:10:42 PM PDT 24
Finished Jul 04 05:12:23 PM PDT 24
Peak memory 237764 kb
Host smart-9282ae4c-d8cd-4733-b052-2cebc8b237ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966177802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1966177802
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1889472117
Short name T123
Test name
Test status
Simulation time 3949807464 ps
CPU time 33.13 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:25 PM PDT 24
Peak memory 211876 kb
Host smart-06c04f74-4600-4aa9-9b54-350e458d7f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889472117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1889472117
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3765285645
Short name T25
Test name
Test status
Simulation time 100240658 ps
CPU time 5.63 seconds
Started Jul 04 05:10:47 PM PDT 24
Finished Jul 04 05:10:53 PM PDT 24
Peak memory 211300 kb
Host smart-f6239528-c345-4a21-b780-82197f6e2566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3765285645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3765285645
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1797139994
Short name T209
Test name
Test status
Simulation time 3867652449 ps
CPU time 12.98 seconds
Started Jul 04 05:10:51 PM PDT 24
Finished Jul 04 05:11:04 PM PDT 24
Peak memory 213620 kb
Host smart-a9d851db-fa7b-4c96-bc76-40db5f3263e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797139994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1797139994
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.436772509
Short name T136
Test name
Test status
Simulation time 12460245913 ps
CPU time 30.85 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:11:21 PM PDT 24
Peak memory 214708 kb
Host smart-8b5b23cf-b93b-417a-b537-125f28b1cfc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436772509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.436772509
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.851972767
Short name T51
Test name
Test status
Simulation time 26879964830 ps
CPU time 566.48 seconds
Started Jul 04 05:10:43 PM PDT 24
Finished Jul 04 05:20:10 PM PDT 24
Peak memory 234256 kb
Host smart-5bfdfcc8-e696-4e13-a8fb-5e223a3af244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851972767 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.851972767
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2621421445
Short name T159
Test name
Test status
Simulation time 1841266421 ps
CPU time 15.18 seconds
Started Jul 04 05:10:43 PM PDT 24
Finished Jul 04 05:10:58 PM PDT 24
Peak memory 211200 kb
Host smart-d0ec0f4a-81fc-4a36-b237-0a5630105645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621421445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2621421445
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2455370354
Short name T186
Test name
Test status
Simulation time 13049790682 ps
CPU time 200.05 seconds
Started Jul 04 05:10:53 PM PDT 24
Finished Jul 04 05:14:14 PM PDT 24
Peak memory 237708 kb
Host smart-40c3f1a5-14ea-4ad6-8cab-85d71825fd21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455370354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2455370354
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.515881996
Short name T306
Test name
Test status
Simulation time 7202492461 ps
CPU time 15.66 seconds
Started Jul 04 05:10:42 PM PDT 24
Finished Jul 04 05:10:57 PM PDT 24
Peak memory 211404 kb
Host smart-73aeac71-8b67-43ee-85ca-01410f1a6388
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515881996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.515881996
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2405081682
Short name T297
Test name
Test status
Simulation time 689368704 ps
CPU time 9.94 seconds
Started Jul 04 05:10:46 PM PDT 24
Finished Jul 04 05:10:56 PM PDT 24
Peak memory 213172 kb
Host smart-d77d15ce-8ce9-47ce-af92-56a6f1a31d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405081682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2405081682
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.373245228
Short name T323
Test name
Test status
Simulation time 176213693 ps
CPU time 8.12 seconds
Started Jul 04 05:10:44 PM PDT 24
Finished Jul 04 05:10:53 PM PDT 24
Peak memory 211108 kb
Host smart-71edb985-0e19-4f71-ba12-6a221983e7df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373245228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.373245228
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.379561750
Short name T214
Test name
Test status
Simulation time 3792825283 ps
CPU time 14.47 seconds
Started Jul 04 05:10:41 PM PDT 24
Finished Jul 04 05:10:56 PM PDT 24
Peak memory 211240 kb
Host smart-6e70c18f-2f7b-4165-9bf8-8ef3cb17e0ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379561750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.379561750
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3793326029
Short name T260
Test name
Test status
Simulation time 22221498198 ps
CPU time 19.36 seconds
Started Jul 04 05:10:41 PM PDT 24
Finished Jul 04 05:11:01 PM PDT 24
Peak memory 212264 kb
Host smart-989b83b0-c365-4caf-8fb6-0b76c8a1c53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793326029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3793326029
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1712423168
Short name T239
Test name
Test status
Simulation time 6017209229 ps
CPU time 19.8 seconds
Started Jul 04 05:10:48 PM PDT 24
Finished Jul 04 05:11:08 PM PDT 24
Peak memory 214728 kb
Host smart-d95933dd-ec8f-4102-a6c9-c65b0fe7c3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712423168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1712423168
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3935506106
Short name T69
Test name
Test status
Simulation time 297621170 ps
CPU time 17.64 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:10 PM PDT 24
Peak memory 215196 kb
Host smart-94916a0e-3c5f-4a9f-b4e9-1ba363b71540
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935506106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3935506106
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2798825917
Short name T59
Test name
Test status
Simulation time 6871128758 ps
CPU time 14.41 seconds
Started Jul 04 05:10:47 PM PDT 24
Finished Jul 04 05:11:02 PM PDT 24
Peak memory 211296 kb
Host smart-685f10be-9b22-4a42-8a84-f90106c98976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798825917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2798825917
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2506242017
Short name T302
Test name
Test status
Simulation time 67381970057 ps
CPU time 193.33 seconds
Started Jul 04 05:10:51 PM PDT 24
Finished Jul 04 05:14:05 PM PDT 24
Peak memory 234824 kb
Host smart-5ad36e76-6051-4091-9f41-f87bc63f194a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506242017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2506242017
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4010032866
Short name T235
Test name
Test status
Simulation time 694239375 ps
CPU time 9.55 seconds
Started Jul 04 05:10:46 PM PDT 24
Finished Jul 04 05:10:56 PM PDT 24
Peak memory 211852 kb
Host smart-567953fd-f788-4a9b-bfe1-3b0d7e7948c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010032866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4010032866
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2120723352
Short name T32
Test name
Test status
Simulation time 439763439 ps
CPU time 6.62 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:10:57 PM PDT 24
Peak memory 211324 kb
Host smart-c6f29962-5001-47c2-8ed9-8618d5da270f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120723352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2120723352
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3844454575
Short name T253
Test name
Test status
Simulation time 945424789 ps
CPU time 16.49 seconds
Started Jul 04 05:10:48 PM PDT 24
Finished Jul 04 05:11:05 PM PDT 24
Peak memory 213544 kb
Host smart-4fbbc735-4a49-44e7-917b-2a3d0ffbc8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844454575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3844454575
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1773041308
Short name T271
Test name
Test status
Simulation time 6791287621 ps
CPU time 36.67 seconds
Started Jul 04 05:10:46 PM PDT 24
Finished Jul 04 05:11:23 PM PDT 24
Peak memory 214464 kb
Host smart-5009a2a6-0b2e-4bac-a410-0308c1b78257
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773041308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1773041308
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.502214864
Short name T187
Test name
Test status
Simulation time 2361605096 ps
CPU time 11.35 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:11:01 PM PDT 24
Peak memory 211364 kb
Host smart-bb034a54-4780-4aa4-b5d2-37c9a91ff285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502214864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.502214864
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1337917988
Short name T210
Test name
Test status
Simulation time 1583538626 ps
CPU time 100.42 seconds
Started Jul 04 05:10:54 PM PDT 24
Finished Jul 04 05:12:35 PM PDT 24
Peak memory 233660 kb
Host smart-283c508c-6142-4323-b1cf-2640b6ad2c23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337917988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1337917988
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4094791166
Short name T150
Test name
Test status
Simulation time 12592260744 ps
CPU time 28.95 seconds
Started Jul 04 05:10:42 PM PDT 24
Finished Jul 04 05:11:11 PM PDT 24
Peak memory 212180 kb
Host smart-2b09cd28-9522-424b-b31d-4c423195b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094791166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4094791166
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.621687512
Short name T211
Test name
Test status
Simulation time 1147920920 ps
CPU time 12.18 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:11:01 PM PDT 24
Peak memory 211340 kb
Host smart-d39a4847-40da-417a-bb1d-acfe38ccbb01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621687512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.621687512
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1270161311
Short name T170
Test name
Test status
Simulation time 616508060 ps
CPU time 10.35 seconds
Started Jul 04 05:10:45 PM PDT 24
Finished Jul 04 05:10:56 PM PDT 24
Peak memory 212788 kb
Host smart-448122a4-9308-4937-ba1d-d703dc9a15de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270161311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1270161311
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1460658861
Short name T339
Test name
Test status
Simulation time 834201072 ps
CPU time 10.23 seconds
Started Jul 04 05:10:44 PM PDT 24
Finished Jul 04 05:10:55 PM PDT 24
Peak memory 214352 kb
Host smart-94fa0dbd-6232-41f2-a614-cf3eef146a74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460658861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1460658861
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2372686368
Short name T284
Test name
Test status
Simulation time 11614685855 ps
CPU time 119.04 seconds
Started Jul 04 05:10:46 PM PDT 24
Finished Jul 04 05:12:46 PM PDT 24
Peak memory 228064 kb
Host smart-1a727325-9a63-474e-a725-3a4d9bb5f215
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372686368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2372686368
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2117668258
Short name T3
Test name
Test status
Simulation time 677063458 ps
CPU time 13.6 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:07 PM PDT 24
Peak memory 212188 kb
Host smart-d43b0f69-b151-4f4c-a7df-112ba1f6b357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117668258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2117668258
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.490253594
Short name T266
Test name
Test status
Simulation time 497730298 ps
CPU time 6.47 seconds
Started Jul 04 05:10:54 PM PDT 24
Finished Jul 04 05:11:00 PM PDT 24
Peak memory 211336 kb
Host smart-342fac4b-4581-4b47-b974-3932452322dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=490253594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.490253594
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3409862057
Short name T147
Test name
Test status
Simulation time 1266518161 ps
CPU time 11.58 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:11:02 PM PDT 24
Peak memory 213808 kb
Host smart-7734d70a-95f5-4b67-a3cb-963c0e834fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409862057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3409862057
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2990242719
Short name T357
Test name
Test status
Simulation time 1417507720 ps
CPU time 14.85 seconds
Started Jul 04 05:10:57 PM PDT 24
Finished Jul 04 05:11:12 PM PDT 24
Peak memory 211224 kb
Host smart-d262393f-3bad-44b1-93be-16f32ceaeb7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990242719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2990242719
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2943677940
Short name T307
Test name
Test status
Simulation time 3083773435 ps
CPU time 6.61 seconds
Started Jul 04 05:10:47 PM PDT 24
Finished Jul 04 05:10:54 PM PDT 24
Peak memory 211384 kb
Host smart-e5600c5c-4aac-4698-b2be-b75e16a22fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943677940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2943677940
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3105039046
Short name T300
Test name
Test status
Simulation time 1707211309 ps
CPU time 102.67 seconds
Started Jul 04 05:10:46 PM PDT 24
Finished Jul 04 05:12:29 PM PDT 24
Peak memory 213548 kb
Host smart-d501f220-a3ce-453b-86e3-3753baf50ac9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105039046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3105039046
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.50303097
Short name T355
Test name
Test status
Simulation time 11968281926 ps
CPU time 33.31 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:26 PM PDT 24
Peak memory 212724 kb
Host smart-8fe23bfb-e2b0-44e9-882c-fa06e1f9563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50303097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.50303097
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1529318356
Short name T178
Test name
Test status
Simulation time 1984711799 ps
CPU time 11.34 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:11:01 PM PDT 24
Peak memory 211276 kb
Host smart-17a30e01-ff67-478a-8fb8-d4145e7c3e98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529318356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1529318356
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3880403864
Short name T238
Test name
Test status
Simulation time 16897635524 ps
CPU time 43.42 seconds
Started Jul 04 05:11:02 PM PDT 24
Finished Jul 04 05:11:45 PM PDT 24
Peak memory 216780 kb
Host smart-e3a62462-3a49-42d9-853f-3d3341e6ab69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880403864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3880403864
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3234128154
Short name T251
Test name
Test status
Simulation time 82172285048 ps
CPU time 870.33 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:25:20 PM PDT 24
Peak memory 235732 kb
Host smart-4f927722-da81-420f-8f41-99cc7c9214c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234128154 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3234128154
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2993990208
Short name T161
Test name
Test status
Simulation time 167902062 ps
CPU time 4.3 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:10:56 PM PDT 24
Peak memory 211172 kb
Host smart-a25f131b-7c15-4488-bd10-6fa1ee97c37f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993990208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2993990208
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.241026769
Short name T315
Test name
Test status
Simulation time 7601852754 ps
CPU time 111.36 seconds
Started Jul 04 05:10:44 PM PDT 24
Finished Jul 04 05:12:36 PM PDT 24
Peak memory 212520 kb
Host smart-1a44d41e-42ff-4d29-8827-afbad6f4923d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241026769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.241026769
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1162351187
Short name T364
Test name
Test status
Simulation time 13604505814 ps
CPU time 25.97 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:19 PM PDT 24
Peak memory 212148 kb
Host smart-a01cd8b8-5188-460b-bb9d-48aae632ca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162351187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1162351187
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1560609795
Short name T222
Test name
Test status
Simulation time 192191167 ps
CPU time 5.52 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:10:55 PM PDT 24
Peak memory 211280 kb
Host smart-43a0db77-4928-4e47-b3c9-8a75fd34a7a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560609795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1560609795
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3658437982
Short name T70
Test name
Test status
Simulation time 3028257043 ps
CPU time 30.07 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:11:19 PM PDT 24
Peak memory 213056 kb
Host smart-cf558e5a-1e08-4bb8-b58f-362a57640f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658437982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3658437982
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4165693214
Short name T273
Test name
Test status
Simulation time 3105005093 ps
CPU time 31.88 seconds
Started Jul 04 05:10:53 PM PDT 24
Finished Jul 04 05:11:25 PM PDT 24
Peak memory 216236 kb
Host smart-53087feb-a6fc-474e-8352-134e5bd0fcd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165693214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4165693214
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1061658671
Short name T52
Test name
Test status
Simulation time 93267202351 ps
CPU time 6398.95 seconds
Started Jul 04 05:10:55 PM PDT 24
Finished Jul 04 06:57:35 PM PDT 24
Peak memory 235808 kb
Host smart-b43e7b7f-d794-4c7f-9b9f-3dcdfc354c84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061658671 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1061658671
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.510215788
Short name T348
Test name
Test status
Simulation time 3599633134 ps
CPU time 12.83 seconds
Started Jul 04 05:10:37 PM PDT 24
Finished Jul 04 05:10:50 PM PDT 24
Peak memory 211284 kb
Host smart-9c111cea-dfb0-4cab-b667-3fdcfc7f8ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510215788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.510215788
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1644204646
Short name T40
Test name
Test status
Simulation time 79418222320 ps
CPU time 231.2 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:14:27 PM PDT 24
Peak memory 212596 kb
Host smart-a50498d4-6863-4b56-badc-1d64831f9a63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644204646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1644204646
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3043864975
Short name T139
Test name
Test status
Simulation time 3730294748 ps
CPU time 14.79 seconds
Started Jul 04 05:10:31 PM PDT 24
Finished Jul 04 05:10:46 PM PDT 24
Peak memory 212320 kb
Host smart-ddde8b4c-8af5-48d7-8bce-f7d7679da0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043864975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3043864975
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1257589652
Short name T7
Test name
Test status
Simulation time 2612641395 ps
CPU time 13.32 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:10:49 PM PDT 24
Peak memory 211400 kb
Host smart-282b70ae-5e63-42eb-8808-feab592cbd9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257589652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1257589652
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2310176167
Short name T21
Test name
Test status
Simulation time 5391382156 ps
CPU time 101.98 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:12:18 PM PDT 24
Peak memory 235224 kb
Host smart-f4a6cf41-193b-4f71-9125-d50dba5555b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310176167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2310176167
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1876780131
Short name T188
Test name
Test status
Simulation time 2668211636 ps
CPU time 14.34 seconds
Started Jul 04 05:10:37 PM PDT 24
Finished Jul 04 05:10:52 PM PDT 24
Peak memory 212516 kb
Host smart-153164f6-73a7-4280-9c0d-e75cd598c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876780131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1876780131
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.990821535
Short name T34
Test name
Test status
Simulation time 2225749237 ps
CPU time 24.65 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:11:01 PM PDT 24
Peak memory 216124 kb
Host smart-22b8cfea-6bf5-4853-9343-103260ccfeb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990821535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.990821535
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4219478046
Short name T353
Test name
Test status
Simulation time 10158970091 ps
CPU time 389.54 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:17:06 PM PDT 24
Peak memory 227568 kb
Host smart-16cac9d1-39bd-43b5-9da0-662b5f8326ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219478046 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.4219478046
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4263030403
Short name T324
Test name
Test status
Simulation time 8532254885 ps
CPU time 16.59 seconds
Started Jul 04 05:10:55 PM PDT 24
Finished Jul 04 05:11:17 PM PDT 24
Peak memory 211364 kb
Host smart-827dc232-b9c7-4a3d-b539-29733efb8b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263030403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4263030403
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2195303264
Short name T174
Test name
Test status
Simulation time 1845286825 ps
CPU time 9.62 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:11:01 PM PDT 24
Peak memory 211864 kb
Host smart-6423aab5-b037-4c60-b527-0bb6fcee90fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195303264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2195303264
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.998539890
Short name T356
Test name
Test status
Simulation time 3016366796 ps
CPU time 14.07 seconds
Started Jul 04 05:10:59 PM PDT 24
Finished Jul 04 05:11:14 PM PDT 24
Peak memory 211404 kb
Host smart-3d374322-cbf6-4815-a08f-391f30cdfb2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=998539890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.998539890
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2608301340
Short name T36
Test name
Test status
Simulation time 2331803901 ps
CPU time 26.93 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:11:17 PM PDT 24
Peak memory 213780 kb
Host smart-f1d5aa05-ce99-4950-a25f-be53044ff450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608301340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2608301340
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.149221504
Short name T295
Test name
Test status
Simulation time 16152667129 ps
CPU time 40.94 seconds
Started Jul 04 05:10:54 PM PDT 24
Finished Jul 04 05:11:35 PM PDT 24
Peak memory 214184 kb
Host smart-3436a263-2a18-4e16-9792-8134caeae10e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149221504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.149221504
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1783509163
Short name T50
Test name
Test status
Simulation time 131440793579 ps
CPU time 2518.97 seconds
Started Jul 04 05:11:02 PM PDT 24
Finished Jul 04 05:53:02 PM PDT 24
Peak memory 234548 kb
Host smart-baba7abb-fa9b-49f2-8216-62ab737d09f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783509163 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1783509163
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1146989764
Short name T252
Test name
Test status
Simulation time 87074512 ps
CPU time 4.2 seconds
Started Jul 04 05:10:58 PM PDT 24
Finished Jul 04 05:11:03 PM PDT 24
Peak memory 211280 kb
Host smart-917cec2e-a6be-4ffa-9077-d9c9d6d04977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146989764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1146989764
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4067096086
Short name T41
Test name
Test status
Simulation time 38544492822 ps
CPU time 259.77 seconds
Started Jul 04 05:10:54 PM PDT 24
Finished Jul 04 05:15:14 PM PDT 24
Peak memory 225616 kb
Host smart-ddcb8456-8741-41c0-8871-4de1fe9734c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067096086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4067096086
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.988612101
Short name T322
Test name
Test status
Simulation time 5608457609 ps
CPU time 16.17 seconds
Started Jul 04 05:10:54 PM PDT 24
Finished Jul 04 05:11:11 PM PDT 24
Peak memory 212120 kb
Host smart-c1325826-8766-44fd-a7ef-83f27133feee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988612101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.988612101
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3646816962
Short name T228
Test name
Test status
Simulation time 1025399235 ps
CPU time 11.82 seconds
Started Jul 04 05:10:53 PM PDT 24
Finished Jul 04 05:11:05 PM PDT 24
Peak memory 211336 kb
Host smart-a4347219-ef0a-4330-8874-0a9c3339eec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646816962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3646816962
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3403981392
Short name T151
Test name
Test status
Simulation time 4282819894 ps
CPU time 33.62 seconds
Started Jul 04 05:10:51 PM PDT 24
Finished Jul 04 05:11:25 PM PDT 24
Peak memory 213756 kb
Host smart-c90e96e9-adf3-498c-a98d-68c559071106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403981392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3403981392
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3887009448
Short name T118
Test name
Test status
Simulation time 1844820852 ps
CPU time 34.34 seconds
Started Jul 04 05:10:51 PM PDT 24
Finished Jul 04 05:11:26 PM PDT 24
Peak memory 215596 kb
Host smart-c47cbcb1-b782-499e-a44a-096c0b3517a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887009448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3887009448
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.347403012
Short name T33
Test name
Test status
Simulation time 26130458453 ps
CPU time 314.83 seconds
Started Jul 04 05:11:01 PM PDT 24
Finished Jul 04 05:16:16 PM PDT 24
Peak memory 224260 kb
Host smart-df8d5e66-7d92-45c1-b68e-cec7c336a064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347403012 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.347403012
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.940475116
Short name T234
Test name
Test status
Simulation time 1716762086 ps
CPU time 14.15 seconds
Started Jul 04 05:11:01 PM PDT 24
Finished Jul 04 05:11:16 PM PDT 24
Peak memory 211232 kb
Host smart-bee5fe5c-726f-4447-b1aa-423b66e4e11b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940475116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.940475116
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3458484714
Short name T134
Test name
Test status
Simulation time 6143744841 ps
CPU time 67.17 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:11:57 PM PDT 24
Peak memory 239332 kb
Host smart-149b5258-9771-4fa0-8b70-5992996f4d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458484714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3458484714
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3624623446
Short name T91
Test name
Test status
Simulation time 5983663374 ps
CPU time 27.23 seconds
Started Jul 04 05:10:56 PM PDT 24
Finished Jul 04 05:11:23 PM PDT 24
Peak memory 212480 kb
Host smart-eab2e817-ae20-4e69-9b78-e9e8717c3b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624623446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3624623446
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.950032385
Short name T367
Test name
Test status
Simulation time 543752953 ps
CPU time 5.72 seconds
Started Jul 04 05:11:00 PM PDT 24
Finished Jul 04 05:11:06 PM PDT 24
Peak memory 211328 kb
Host smart-f524caa0-2783-4e57-9a36-0e52ddbdc16c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950032385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.950032385
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.341412087
Short name T92
Test name
Test status
Simulation time 23369577568 ps
CPU time 29.14 seconds
Started Jul 04 05:10:55 PM PDT 24
Finished Jul 04 05:11:24 PM PDT 24
Peak memory 214356 kb
Host smart-91d18fe2-0ac8-4624-876e-ac5f5328e8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341412087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.341412087
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3512220577
Short name T257
Test name
Test status
Simulation time 1008226162 ps
CPU time 12.55 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:11:01 PM PDT 24
Peak memory 212360 kb
Host smart-1fc0ce95-b3be-4f48-9bd7-4f428af08ecb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512220577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3512220577
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1579629503
Short name T152
Test name
Test status
Simulation time 5533214001 ps
CPU time 12.9 seconds
Started Jul 04 05:11:00 PM PDT 24
Finished Jul 04 05:11:13 PM PDT 24
Peak memory 211316 kb
Host smart-795a26d5-1804-4fff-ac5d-25dd2fffac1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579629503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1579629503
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.496934393
Short name T172
Test name
Test status
Simulation time 4518875979 ps
CPU time 136.09 seconds
Started Jul 04 05:10:54 PM PDT 24
Finished Jul 04 05:13:11 PM PDT 24
Peak memory 228604 kb
Host smart-c00c1cdc-c49f-42c9-94a5-c47e97938050
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496934393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.496934393
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1819444824
Short name T264
Test name
Test status
Simulation time 823348921 ps
CPU time 14.85 seconds
Started Jul 04 05:11:02 PM PDT 24
Finished Jul 04 05:11:17 PM PDT 24
Peak memory 211736 kb
Host smart-b737b2d6-e570-4f52-af60-c13764df7316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819444824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1819444824
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2971543127
Short name T162
Test name
Test status
Simulation time 7271781552 ps
CPU time 15.64 seconds
Started Jul 04 05:10:55 PM PDT 24
Finished Jul 04 05:11:10 PM PDT 24
Peak memory 211396 kb
Host smart-a982e504-a84e-45d5-a136-e7339ea88646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971543127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2971543127
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1172044632
Short name T304
Test name
Test status
Simulation time 384231441 ps
CPU time 9.81 seconds
Started Jul 04 05:10:57 PM PDT 24
Finished Jul 04 05:11:07 PM PDT 24
Peak memory 213420 kb
Host smart-aa24e58c-0807-4afa-bace-3f7546dfa435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172044632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1172044632
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.754098488
Short name T254
Test name
Test status
Simulation time 18099825149 ps
CPU time 69.65 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:12:01 PM PDT 24
Peak memory 219388 kb
Host smart-028d96a2-4d4d-4225-88a2-4ef5e1e772e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754098488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.754098488
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1841786209
Short name T237
Test name
Test status
Simulation time 8423606517 ps
CPU time 16.34 seconds
Started Jul 04 05:10:53 PM PDT 24
Finished Jul 04 05:11:10 PM PDT 24
Peak memory 211216 kb
Host smart-1adfab29-105f-4f70-b6b4-a7e9ae9e2ba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841786209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1841786209
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2469281465
Short name T240
Test name
Test status
Simulation time 1225818298 ps
CPU time 78.29 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:12:09 PM PDT 24
Peak memory 237724 kb
Host smart-a21b4e0d-da4c-40db-8208-d8d9e69a78b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469281465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2469281465
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.554448477
Short name T194
Test name
Test status
Simulation time 4810907354 ps
CPU time 23.98 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:16 PM PDT 24
Peak memory 212288 kb
Host smart-cf0c83f3-a806-4989-b700-c5c418b6d142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554448477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.554448477
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.439186615
Short name T31
Test name
Test status
Simulation time 24000149455 ps
CPU time 13.8 seconds
Started Jul 04 05:11:02 PM PDT 24
Finished Jul 04 05:11:16 PM PDT 24
Peak memory 211300 kb
Host smart-4aef9bfb-ec10-4098-a2a1-1516f4ad2479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439186615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.439186615
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2708917863
Short name T305
Test name
Test status
Simulation time 16438972668 ps
CPU time 33.68 seconds
Started Jul 04 05:10:53 PM PDT 24
Finished Jul 04 05:11:27 PM PDT 24
Peak memory 213908 kb
Host smart-acde09b2-5ec4-457c-ba53-5552119118e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708917863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2708917863
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3207483240
Short name T249
Test name
Test status
Simulation time 25717478346 ps
CPU time 58.2 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:51 PM PDT 24
Peak memory 217376 kb
Host smart-f3be1422-f60f-47fd-94f8-1c745df1ca07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207483240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3207483240
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.482689038
Short name T23
Test name
Test status
Simulation time 3523397590 ps
CPU time 14.67 seconds
Started Jul 04 05:11:02 PM PDT 24
Finished Jul 04 05:11:17 PM PDT 24
Peak memory 211208 kb
Host smart-2ebddd33-74ea-4d10-a0b5-6101375f3d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482689038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.482689038
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3564931237
Short name T5
Test name
Test status
Simulation time 2817745693 ps
CPU time 26.03 seconds
Started Jul 04 05:11:00 PM PDT 24
Finished Jul 04 05:11:26 PM PDT 24
Peak memory 212564 kb
Host smart-7b652c5f-bd49-4056-ae9f-157e39abc5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564931237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3564931237
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3058089315
Short name T274
Test name
Test status
Simulation time 3129837858 ps
CPU time 9.59 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:02 PM PDT 24
Peak memory 211696 kb
Host smart-5f84e7bc-4914-4b02-9336-eede69415b09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058089315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3058089315
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2449737668
Short name T262
Test name
Test status
Simulation time 14061994971 ps
CPU time 33.17 seconds
Started Jul 04 05:10:53 PM PDT 24
Finished Jul 04 05:11:27 PM PDT 24
Peak memory 213480 kb
Host smart-1d5683eb-135e-4447-bab4-116a88222a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449737668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2449737668
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1563086379
Short name T250
Test name
Test status
Simulation time 7552575354 ps
CPU time 76.92 seconds
Started Jul 04 05:11:02 PM PDT 24
Finished Jul 04 05:12:20 PM PDT 24
Peak memory 215656 kb
Host smart-63205d3c-55b7-4b75-8300-2e9f1355a1fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563086379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1563086379
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1298968632
Short name T154
Test name
Test status
Simulation time 3215617974 ps
CPU time 13.82 seconds
Started Jul 04 05:11:00 PM PDT 24
Finished Jul 04 05:11:14 PM PDT 24
Peak memory 211200 kb
Host smart-dc4120d2-4a1d-430d-8872-12af27b470c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298968632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1298968632
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3544198802
Short name T48
Test name
Test status
Simulation time 31757474772 ps
CPU time 313.02 seconds
Started Jul 04 05:10:59 PM PDT 24
Finished Jul 04 05:16:13 PM PDT 24
Peak memory 235884 kb
Host smart-e49684a9-d463-420f-a691-3a576f0b5299
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544198802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3544198802
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3161473840
Short name T180
Test name
Test status
Simulation time 3344743683 ps
CPU time 27.77 seconds
Started Jul 04 05:10:51 PM PDT 24
Finished Jul 04 05:11:19 PM PDT 24
Peak memory 211860 kb
Host smart-5a817464-68f5-469b-b610-c884ec7a0c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161473840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3161473840
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2659511787
Short name T299
Test name
Test status
Simulation time 6265255525 ps
CPU time 13.73 seconds
Started Jul 04 05:10:51 PM PDT 24
Finished Jul 04 05:11:06 PM PDT 24
Peak memory 211692 kb
Host smart-db2345cb-3ccd-425b-af09-decefa8b70b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659511787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2659511787
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2698638810
Short name T160
Test name
Test status
Simulation time 2175905757 ps
CPU time 10 seconds
Started Jul 04 05:10:55 PM PDT 24
Finished Jul 04 05:11:05 PM PDT 24
Peak memory 213644 kb
Host smart-730572d3-e4bb-41c5-baa5-afb156d7f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698638810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2698638810
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1271974093
Short name T294
Test name
Test status
Simulation time 12503720672 ps
CPU time 41.19 seconds
Started Jul 04 05:10:55 PM PDT 24
Finished Jul 04 05:11:37 PM PDT 24
Peak memory 217404 kb
Host smart-2bc69ffc-2edf-4c88-aa49-2770e0757f94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271974093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1271974093
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1969179112
Short name T349
Test name
Test status
Simulation time 171510237 ps
CPU time 4.2 seconds
Started Jul 04 05:11:00 PM PDT 24
Finished Jul 04 05:11:05 PM PDT 24
Peak memory 211204 kb
Host smart-c72bfd79-8501-41c0-9e70-bd8a6c430853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969179112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1969179112
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4229617068
Short name T202
Test name
Test status
Simulation time 60031081017 ps
CPU time 161.14 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:13:32 PM PDT 24
Peak memory 238676 kb
Host smart-bfe70b70-9a42-4bc0-b1c6-a2389121cd51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229617068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4229617068
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2794542890
Short name T293
Test name
Test status
Simulation time 14266634964 ps
CPU time 28.42 seconds
Started Jul 04 05:11:00 PM PDT 24
Finished Jul 04 05:11:29 PM PDT 24
Peak memory 211348 kb
Host smart-6e2ea5fc-7ff8-4c8f-a3ce-6ce599b66d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794542890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2794542890
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3563897950
Short name T133
Test name
Test status
Simulation time 96680112 ps
CPU time 5.64 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:10:58 PM PDT 24
Peak memory 211240 kb
Host smart-5a10f666-5492-4b7a-b3fb-119c5752295e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3563897950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3563897950
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.610031507
Short name T330
Test name
Test status
Simulation time 215729711 ps
CPU time 9.85 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:11:00 PM PDT 24
Peak memory 213876 kb
Host smart-39ca584e-86b8-4e08-a8e8-e5a9d0054a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610031507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.610031507
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3613070462
Short name T226
Test name
Test status
Simulation time 268688488 ps
CPU time 17.38 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:10 PM PDT 24
Peak memory 213232 kb
Host smart-930ea9ac-e558-4b2a-846e-2a1e6cd31a89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613070462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3613070462
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2142688814
Short name T165
Test name
Test status
Simulation time 4097009381 ps
CPU time 15.75 seconds
Started Jul 04 05:10:59 PM PDT 24
Finished Jul 04 05:11:15 PM PDT 24
Peak memory 211352 kb
Host smart-96d95402-ac25-4980-81b4-d8d74450e967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142688814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2142688814
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2798161843
Short name T157
Test name
Test status
Simulation time 7943428807 ps
CPU time 115.96 seconds
Started Jul 04 05:11:02 PM PDT 24
Finished Jul 04 05:12:59 PM PDT 24
Peak memory 233632 kb
Host smart-5cf49152-0c5d-4652-a1ed-09533cc5866b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798161843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2798161843
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2492766494
Short name T363
Test name
Test status
Simulation time 2445097109 ps
CPU time 23.72 seconds
Started Jul 04 05:10:57 PM PDT 24
Finished Jul 04 05:11:21 PM PDT 24
Peak memory 212184 kb
Host smart-99877148-9fd6-4624-b57e-07445b0e6feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492766494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2492766494
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.5093263
Short name T17
Test name
Test status
Simulation time 530414532 ps
CPU time 6.2 seconds
Started Jul 04 05:10:59 PM PDT 24
Finished Jul 04 05:11:05 PM PDT 24
Peak memory 211324 kb
Host smart-994577f4-ab3f-44c6-a532-29f458b7de5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5093263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.5093263
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2348078605
Short name T246
Test name
Test status
Simulation time 782929679 ps
CPU time 14.86 seconds
Started Jul 04 05:10:58 PM PDT 24
Finished Jul 04 05:11:13 PM PDT 24
Peak memory 213420 kb
Host smart-97d4fcbb-3aa7-48d0-9eb2-40745b08d903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348078605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2348078605
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2233151054
Short name T163
Test name
Test status
Simulation time 471878092 ps
CPU time 26.66 seconds
Started Jul 04 05:10:52 PM PDT 24
Finished Jul 04 05:11:20 PM PDT 24
Peak memory 215424 kb
Host smart-7c49f11e-308a-407f-9304-891d9da5138f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233151054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2233151054
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2284153032
Short name T338
Test name
Test status
Simulation time 96136252 ps
CPU time 4.2 seconds
Started Jul 04 05:10:57 PM PDT 24
Finished Jul 04 05:11:02 PM PDT 24
Peak memory 211292 kb
Host smart-f9860637-06a9-4d82-8502-16b96454c827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284153032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2284153032
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1835406123
Short name T87
Test name
Test status
Simulation time 12715983133 ps
CPU time 128.7 seconds
Started Jul 04 05:10:53 PM PDT 24
Finished Jul 04 05:13:02 PM PDT 24
Peak memory 227812 kb
Host smart-25ad1f35-21e4-424d-ba6d-4b211ee80e17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835406123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1835406123
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3539219884
Short name T119
Test name
Test status
Simulation time 15732316559 ps
CPU time 33.8 seconds
Started Jul 04 05:10:58 PM PDT 24
Finished Jul 04 05:11:32 PM PDT 24
Peak memory 212144 kb
Host smart-3e390e64-5c59-4f1b-86ae-610fbbc33f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539219884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3539219884
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2704507848
Short name T368
Test name
Test status
Simulation time 4648870955 ps
CPU time 12 seconds
Started Jul 04 05:10:54 PM PDT 24
Finished Jul 04 05:11:06 PM PDT 24
Peak memory 211396 kb
Host smart-da08b660-e3da-45de-905c-7f6b3d37963c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704507848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2704507848
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1501338300
Short name T175
Test name
Test status
Simulation time 361545808 ps
CPU time 7.95 seconds
Started Jul 04 05:10:56 PM PDT 24
Finished Jul 04 05:11:04 PM PDT 24
Peak memory 211504 kb
Host smart-4ee03f1b-a6b6-438e-b845-796fabec3365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501338300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1501338300
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2385287748
Short name T43
Test name
Test status
Simulation time 78821240381 ps
CPU time 2848.48 seconds
Started Jul 04 05:11:00 PM PDT 24
Finished Jul 04 05:58:29 PM PDT 24
Peak memory 240496 kb
Host smart-2911a002-399b-44f7-881a-563d7323b1d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385287748 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2385287748
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2735119932
Short name T205
Test name
Test status
Simulation time 3002894931 ps
CPU time 12.44 seconds
Started Jul 04 05:10:34 PM PDT 24
Finished Jul 04 05:10:47 PM PDT 24
Peak memory 211356 kb
Host smart-643c5833-4951-4b2f-90a7-af8a7e3beb56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735119932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2735119932
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1101195316
Short name T212
Test name
Test status
Simulation time 10340877999 ps
CPU time 169.86 seconds
Started Jul 04 05:10:39 PM PDT 24
Finished Jul 04 05:13:29 PM PDT 24
Peak memory 237824 kb
Host smart-42be7aaf-ea23-4d05-9a38-fd9f30f0501f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101195316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1101195316
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.545761906
Short name T220
Test name
Test status
Simulation time 1399751214 ps
CPU time 19.01 seconds
Started Jul 04 05:10:35 PM PDT 24
Finished Jul 04 05:10:54 PM PDT 24
Peak memory 211684 kb
Host smart-64721133-2b6d-40ba-8915-329e5205bd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545761906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.545761906
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3153296759
Short name T169
Test name
Test status
Simulation time 7310346554 ps
CPU time 14.98 seconds
Started Jul 04 05:10:38 PM PDT 24
Finished Jul 04 05:10:53 PM PDT 24
Peak memory 211336 kb
Host smart-1b662e5d-ef3c-4368-bd45-331cc7c648d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3153296759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3153296759
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.759893215
Short name T20
Test name
Test status
Simulation time 946436515 ps
CPU time 99.55 seconds
Started Jul 04 05:10:35 PM PDT 24
Finished Jul 04 05:12:15 PM PDT 24
Peak memory 235932 kb
Host smart-8331517e-6292-4787-b370-d9688450479f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759893215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.759893215
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.604303473
Short name T277
Test name
Test status
Simulation time 2969032686 ps
CPU time 30.17 seconds
Started Jul 04 05:10:35 PM PDT 24
Finished Jul 04 05:11:06 PM PDT 24
Peak memory 213432 kb
Host smart-9d97e4e9-1901-4b68-aaf6-a14cc408eb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604303473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.604303473
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.94982626
Short name T301
Test name
Test status
Simulation time 3406172535 ps
CPU time 28.83 seconds
Started Jul 04 05:10:38 PM PDT 24
Finished Jul 04 05:11:07 PM PDT 24
Peak memory 214716 kb
Host smart-40605317-95c1-4523-a91c-2d97ae130074
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94982626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.rom_ctrl_stress_all.94982626
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3940905694
Short name T10
Test name
Test status
Simulation time 294311537 ps
CPU time 6.09 seconds
Started Jul 04 05:11:06 PM PDT 24
Finished Jul 04 05:11:12 PM PDT 24
Peak memory 211256 kb
Host smart-f06a80e6-c54f-47b3-8098-13d0def47026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940905694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3940905694
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1750683297
Short name T195
Test name
Test status
Simulation time 32371028111 ps
CPU time 305.41 seconds
Started Jul 04 05:10:59 PM PDT 24
Finished Jul 04 05:16:05 PM PDT 24
Peak memory 232772 kb
Host smart-b32d937d-3571-4d81-a580-c91c12ac7b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750683297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1750683297
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2983739963
Short name T366
Test name
Test status
Simulation time 333404695 ps
CPU time 11.61 seconds
Started Jul 04 05:11:06 PM PDT 24
Finished Jul 04 05:11:18 PM PDT 24
Peak memory 212024 kb
Host smart-083024f8-dcf4-4d44-b994-e46d0ee7dbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983739963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2983739963
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2794226605
Short name T312
Test name
Test status
Simulation time 189306272 ps
CPU time 5.22 seconds
Started Jul 04 05:11:05 PM PDT 24
Finished Jul 04 05:11:10 PM PDT 24
Peak memory 211328 kb
Host smart-bd1e193c-68c6-4190-95ca-e80380f17c72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2794226605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2794226605
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.953033066
Short name T72
Test name
Test status
Simulation time 8267488291 ps
CPU time 25.51 seconds
Started Jul 04 05:11:03 PM PDT 24
Finished Jul 04 05:11:29 PM PDT 24
Peak memory 214324 kb
Host smart-9829ad24-e8c8-45c9-9ae3-271f3447992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953033066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.953033066
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3154468477
Short name T137
Test name
Test status
Simulation time 480924195 ps
CPU time 7.66 seconds
Started Jul 04 05:11:06 PM PDT 24
Finished Jul 04 05:11:14 PM PDT 24
Peak memory 211260 kb
Host smart-21fdc28c-1d5a-4a6c-bca2-5f25f05be96f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154468477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3154468477
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.449498898
Short name T200
Test name
Test status
Simulation time 8436524835 ps
CPU time 15.22 seconds
Started Jul 04 05:10:59 PM PDT 24
Finished Jul 04 05:11:15 PM PDT 24
Peak memory 211236 kb
Host smart-5ad5d36f-d95a-454e-9265-94a25ea089df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449498898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.449498898
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.505199121
Short name T1
Test name
Test status
Simulation time 50367420958 ps
CPU time 173.7 seconds
Started Jul 04 05:11:05 PM PDT 24
Finished Jul 04 05:13:58 PM PDT 24
Peak memory 233692 kb
Host smart-aa57afcf-00a3-4d1f-916e-bf167bd94b8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505199121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.505199121
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.760687327
Short name T9
Test name
Test status
Simulation time 2364373329 ps
CPU time 23.34 seconds
Started Jul 04 05:11:11 PM PDT 24
Finished Jul 04 05:11:34 PM PDT 24
Peak memory 211892 kb
Host smart-da0f1eeb-72f2-4aea-a71e-e499cc1a0739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760687327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.760687327
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1847314350
Short name T86
Test name
Test status
Simulation time 93127259 ps
CPU time 5.25 seconds
Started Jul 04 05:11:04 PM PDT 24
Finished Jul 04 05:11:09 PM PDT 24
Peak memory 211336 kb
Host smart-2de7fd77-adae-4e99-bb13-8ddb2fadb0f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1847314350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1847314350
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2210215857
Short name T73
Test name
Test status
Simulation time 2907895997 ps
CPU time 15.02 seconds
Started Jul 04 05:11:02 PM PDT 24
Finished Jul 04 05:11:18 PM PDT 24
Peak memory 213776 kb
Host smart-7b0a3e6e-1168-4e4f-94d9-d2e30f7497b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210215857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2210215857
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.185392871
Short name T362
Test name
Test status
Simulation time 321484370 ps
CPU time 20.8 seconds
Started Jul 04 05:11:07 PM PDT 24
Finished Jul 04 05:11:28 PM PDT 24
Peak memory 214452 kb
Host smart-29fa992a-5f7b-44d9-923b-2ac88d244244
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185392871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.185392871
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.520076984
Short name T84
Test name
Test status
Simulation time 1858846558 ps
CPU time 14.15 seconds
Started Jul 04 05:11:09 PM PDT 24
Finished Jul 04 05:11:24 PM PDT 24
Peak memory 211264 kb
Host smart-60494173-8536-4ac9-b315-73e5d9f2add3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520076984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.520076984
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1224224673
Short name T354
Test name
Test status
Simulation time 13963513746 ps
CPU time 204.32 seconds
Started Jul 04 05:11:05 PM PDT 24
Finished Jul 04 05:14:30 PM PDT 24
Peak memory 212496 kb
Host smart-39245c9d-ef62-486f-b28b-8973bdcb741d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224224673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1224224673
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2757291354
Short name T171
Test name
Test status
Simulation time 19928130802 ps
CPU time 20.94 seconds
Started Jul 04 05:11:01 PM PDT 24
Finished Jul 04 05:11:22 PM PDT 24
Peak memory 212164 kb
Host smart-a1850d96-7f60-4520-89e2-f36a4d74fc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757291354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2757291354
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1467909819
Short name T179
Test name
Test status
Simulation time 730481905 ps
CPU time 6.73 seconds
Started Jul 04 05:10:59 PM PDT 24
Finished Jul 04 05:11:06 PM PDT 24
Peak memory 211336 kb
Host smart-381c5574-519a-4088-97dc-a6fdd3ce5461
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467909819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1467909819
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2837062577
Short name T140
Test name
Test status
Simulation time 741145368 ps
CPU time 10.36 seconds
Started Jul 04 05:10:58 PM PDT 24
Finished Jul 04 05:11:09 PM PDT 24
Peak memory 213672 kb
Host smart-bd44f337-7223-4e50-b9ee-2043106ec245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837062577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2837062577
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1810782701
Short name T287
Test name
Test status
Simulation time 9214346519 ps
CPU time 64.57 seconds
Started Jul 04 05:11:06 PM PDT 24
Finished Jul 04 05:12:11 PM PDT 24
Peak memory 216112 kb
Host smart-1b8c4c6c-a511-46ea-afa6-d1011fc11074
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810782701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1810782701
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2858494756
Short name T244
Test name
Test status
Simulation time 474924953 ps
CPU time 7.51 seconds
Started Jul 04 05:11:07 PM PDT 24
Finished Jul 04 05:11:15 PM PDT 24
Peak memory 211216 kb
Host smart-888bbb88-486d-450e-9d4c-22c2b9685740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858494756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2858494756
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3024662642
Short name T164
Test name
Test status
Simulation time 252974997356 ps
CPU time 512.22 seconds
Started Jul 04 05:11:07 PM PDT 24
Finished Jul 04 05:19:40 PM PDT 24
Peak memory 212540 kb
Host smart-f73a317d-5a61-415f-ae5a-52b7e64cb51f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024662642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3024662642
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3906698780
Short name T359
Test name
Test status
Simulation time 780411283 ps
CPU time 9.45 seconds
Started Jul 04 05:10:59 PM PDT 24
Finished Jul 04 05:11:09 PM PDT 24
Peak memory 211304 kb
Host smart-6d2e5c55-0b62-4497-b455-a7661af53ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906698780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3906698780
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3292700222
Short name T361
Test name
Test status
Simulation time 7212916688 ps
CPU time 24.06 seconds
Started Jul 04 05:11:02 PM PDT 24
Finished Jul 04 05:11:26 PM PDT 24
Peak memory 214344 kb
Host smart-d8fbe0fc-290d-4095-aee4-8d702962a6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292700222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3292700222
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1785968527
Short name T196
Test name
Test status
Simulation time 299194258 ps
CPU time 15.44 seconds
Started Jul 04 05:10:57 PM PDT 24
Finished Jul 04 05:11:13 PM PDT 24
Peak memory 215268 kb
Host smart-21b1deca-2afe-4ffc-a182-bf94de91d82d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785968527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1785968527
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2359923590
Short name T303
Test name
Test status
Simulation time 109030856 ps
CPU time 4.2 seconds
Started Jul 04 05:11:08 PM PDT 24
Finished Jul 04 05:11:12 PM PDT 24
Peak memory 211308 kb
Host smart-367f18a6-2eb4-4208-9ab4-073d354749e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359923590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2359923590
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.338147111
Short name T242
Test name
Test status
Simulation time 40182769428 ps
CPU time 213.18 seconds
Started Jul 04 05:11:06 PM PDT 24
Finished Jul 04 05:14:40 PM PDT 24
Peak memory 232772 kb
Host smart-7fa5aa35-e4e5-4fbc-9f1f-82f8bb5de6d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338147111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.338147111
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4201536887
Short name T259
Test name
Test status
Simulation time 666700183 ps
CPU time 13.65 seconds
Started Jul 04 05:11:03 PM PDT 24
Finished Jul 04 05:11:17 PM PDT 24
Peak memory 212160 kb
Host smart-7bec5351-768b-469d-af1c-6e096dc5fa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201536887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4201536887
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.585873001
Short name T278
Test name
Test status
Simulation time 1071750190 ps
CPU time 7.08 seconds
Started Jul 04 05:11:06 PM PDT 24
Finished Jul 04 05:11:13 PM PDT 24
Peak memory 211236 kb
Host smart-9c5958fe-ff28-4069-9d8b-bc6e65f452c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585873001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.585873001
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2173302951
Short name T282
Test name
Test status
Simulation time 2239155378 ps
CPU time 17.26 seconds
Started Jul 04 05:11:09 PM PDT 24
Finished Jul 04 05:11:27 PM PDT 24
Peak memory 213348 kb
Host smart-d697cb93-af2a-45a4-89d7-4ac678a9ad42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173302951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2173302951
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.192427464
Short name T149
Test name
Test status
Simulation time 386699361 ps
CPU time 25.73 seconds
Started Jul 04 05:11:03 PM PDT 24
Finished Jul 04 05:11:29 PM PDT 24
Peak memory 215352 kb
Host smart-d7e82df6-6da6-4ff9-af64-bfe4e3c2bbf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192427464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.192427464
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3838597579
Short name T125
Test name
Test status
Simulation time 6408618538 ps
CPU time 14.67 seconds
Started Jul 04 05:11:00 PM PDT 24
Finished Jul 04 05:11:15 PM PDT 24
Peak memory 211196 kb
Host smart-37bd9a5c-a359-4762-b9ee-17b06d2f1375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838597579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3838597579
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.15427922
Short name T289
Test name
Test status
Simulation time 98292161784 ps
CPU time 515.83 seconds
Started Jul 04 05:10:58 PM PDT 24
Finished Jul 04 05:19:34 PM PDT 24
Peak memory 225144 kb
Host smart-112fa5f3-f63f-4ca1-9682-b6d8d6490369
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15427922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_co
rrupt_sig_fatal_chk.15427922
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3685496543
Short name T218
Test name
Test status
Simulation time 12598709802 ps
CPU time 27.22 seconds
Started Jul 04 05:11:09 PM PDT 24
Finished Jul 04 05:11:36 PM PDT 24
Peak memory 212344 kb
Host smart-807df61a-7b46-4f28-a976-7aa0abb820a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685496543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3685496543
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4274198008
Short name T199
Test name
Test status
Simulation time 826736572 ps
CPU time 10.42 seconds
Started Jul 04 05:11:08 PM PDT 24
Finished Jul 04 05:11:19 PM PDT 24
Peak memory 211296 kb
Host smart-d540b374-bdf0-453d-a347-cd918467e5bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274198008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4274198008
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1009477714
Short name T14
Test name
Test status
Simulation time 5688215874 ps
CPU time 25.08 seconds
Started Jul 04 05:10:58 PM PDT 24
Finished Jul 04 05:11:23 PM PDT 24
Peak memory 213324 kb
Host smart-235cee86-a27d-4611-85fd-7295f2db19b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009477714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1009477714
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4042852141
Short name T350
Test name
Test status
Simulation time 4557147957 ps
CPU time 21.49 seconds
Started Jul 04 05:11:11 PM PDT 24
Finished Jul 04 05:11:32 PM PDT 24
Peak memory 216476 kb
Host smart-7c8cc655-7fb0-4fc3-b094-a0f86e92c469
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042852141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4042852141
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1670646169
Short name T318
Test name
Test status
Simulation time 6169122138 ps
CPU time 11.98 seconds
Started Jul 04 05:10:57 PM PDT 24
Finished Jul 04 05:11:09 PM PDT 24
Peak memory 211336 kb
Host smart-2b4c2b2c-cf7b-4950-bfdd-5ef4576a92be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670646169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1670646169
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1753520470
Short name T341
Test name
Test status
Simulation time 9708670554 ps
CPU time 98.28 seconds
Started Jul 04 05:10:59 PM PDT 24
Finished Jul 04 05:12:38 PM PDT 24
Peak memory 236836 kb
Host smart-b6eaf90f-01d3-4465-83d1-9b1cd0749ea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753520470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1753520470
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2354146840
Short name T215
Test name
Test status
Simulation time 334021306 ps
CPU time 9.52 seconds
Started Jul 04 05:11:05 PM PDT 24
Finished Jul 04 05:11:15 PM PDT 24
Peak memory 211732 kb
Host smart-08dbcc6d-e6ad-4966-919a-dae28cb63960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354146840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2354146840
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2632121675
Short name T124
Test name
Test status
Simulation time 5789303719 ps
CPU time 13.15 seconds
Started Jul 04 05:11:11 PM PDT 24
Finished Jul 04 05:11:25 PM PDT 24
Peak memory 211384 kb
Host smart-aa2fb0a0-514f-41b8-a1c3-b087c5fb2c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632121675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2632121675
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2934032294
Short name T216
Test name
Test status
Simulation time 731039175 ps
CPU time 9.89 seconds
Started Jul 04 05:11:07 PM PDT 24
Finished Jul 04 05:11:17 PM PDT 24
Peak memory 213752 kb
Host smart-8f5a78c8-8d1d-4e94-a5af-d0ee601cd568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934032294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2934032294
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4272115026
Short name T319
Test name
Test status
Simulation time 3201324197 ps
CPU time 22.92 seconds
Started Jul 04 05:11:02 PM PDT 24
Finished Jul 04 05:11:26 PM PDT 24
Peak memory 216660 kb
Host smart-ccc8749f-e533-4975-9b12-4b647d5c3115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272115026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4272115026
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3814091648
Short name T122
Test name
Test status
Simulation time 799987884 ps
CPU time 9.37 seconds
Started Jul 04 05:11:11 PM PDT 24
Finished Jul 04 05:11:21 PM PDT 24
Peak memory 211212 kb
Host smart-e44435e4-c0c7-463a-956d-e29a1810ba26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814091648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3814091648
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.71995882
Short name T231
Test name
Test status
Simulation time 24566562425 ps
CPU time 234.25 seconds
Started Jul 04 05:11:11 PM PDT 24
Finished Jul 04 05:15:05 PM PDT 24
Peak memory 228484 kb
Host smart-0620aa57-d04e-47d1-bd8b-ffbf4b47d899
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71995882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_co
rrupt_sig_fatal_chk.71995882
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3999656526
Short name T208
Test name
Test status
Simulation time 5921256101 ps
CPU time 32.54 seconds
Started Jul 04 05:11:09 PM PDT 24
Finished Jul 04 05:11:42 PM PDT 24
Peak memory 212820 kb
Host smart-7eac7c58-2458-4864-943a-e82cdc6533ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999656526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3999656526
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3965428010
Short name T351
Test name
Test status
Simulation time 632846070 ps
CPU time 5.82 seconds
Started Jul 04 05:11:10 PM PDT 24
Finished Jul 04 05:11:16 PM PDT 24
Peak memory 211336 kb
Host smart-47fdb55c-7537-469d-9b46-08496dc571c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965428010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3965428010
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.582342507
Short name T236
Test name
Test status
Simulation time 2222643968 ps
CPU time 25.47 seconds
Started Jul 04 05:11:08 PM PDT 24
Finished Jul 04 05:11:33 PM PDT 24
Peak memory 213420 kb
Host smart-16fcbf17-1aaa-4dc4-9c3d-3b920adc4808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582342507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.582342507
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.978298698
Short name T128
Test name
Test status
Simulation time 11329081834 ps
CPU time 23.91 seconds
Started Jul 04 05:11:09 PM PDT 24
Finished Jul 04 05:11:33 PM PDT 24
Peak memory 211260 kb
Host smart-497b3c6f-6632-486e-9601-78537f4cd293
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978298698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.978298698
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2466035537
Short name T148
Test name
Test status
Simulation time 9929050328 ps
CPU time 16.4 seconds
Started Jul 04 05:11:11 PM PDT 24
Finished Jul 04 05:11:28 PM PDT 24
Peak memory 211292 kb
Host smart-1b66d6fe-9a6c-4727-bb5c-c342440b5548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466035537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2466035537
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.451386910
Short name T313
Test name
Test status
Simulation time 170968245123 ps
CPU time 369.22 seconds
Started Jul 04 05:11:10 PM PDT 24
Finished Jul 04 05:17:20 PM PDT 24
Peak memory 234324 kb
Host smart-1b48b8b7-8388-4e2c-b1f5-941ea47b1668
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451386910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.451386910
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.122179936
Short name T4
Test name
Test status
Simulation time 1961155208 ps
CPU time 22.05 seconds
Started Jul 04 05:11:14 PM PDT 24
Finished Jul 04 05:11:36 PM PDT 24
Peak memory 211700 kb
Host smart-e253315b-f2c9-4f6f-af0c-259faaea69c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122179936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.122179936
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.64592272
Short name T155
Test name
Test status
Simulation time 1242348556 ps
CPU time 6.53 seconds
Started Jul 04 05:11:09 PM PDT 24
Finished Jul 04 05:11:16 PM PDT 24
Peak memory 211632 kb
Host smart-ce9926eb-411d-4e00-91de-9d22ffce99f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64592272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.64592272
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1397689943
Short name T185
Test name
Test status
Simulation time 15727877871 ps
CPU time 32.72 seconds
Started Jul 04 05:11:13 PM PDT 24
Finished Jul 04 05:11:46 PM PDT 24
Peak memory 213976 kb
Host smart-1270593c-d41d-486b-8bc3-3976e5951512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397689943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1397689943
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2871648257
Short name T268
Test name
Test status
Simulation time 3889134246 ps
CPU time 33.44 seconds
Started Jul 04 05:11:12 PM PDT 24
Finished Jul 04 05:11:46 PM PDT 24
Peak memory 215104 kb
Host smart-9dca8ebb-a151-49e7-8bd3-da87349d2c27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871648257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2871648257
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2921360718
Short name T156
Test name
Test status
Simulation time 7527655789 ps
CPU time 15.76 seconds
Started Jul 04 05:11:09 PM PDT 24
Finished Jul 04 05:11:25 PM PDT 24
Peak memory 211344 kb
Host smart-d95670cb-a5df-46a4-8fee-09e96584abc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921360718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2921360718
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.806871407
Short name T230
Test name
Test status
Simulation time 2787562783 ps
CPU time 93.65 seconds
Started Jul 04 05:11:11 PM PDT 24
Finished Jul 04 05:12:45 PM PDT 24
Peak memory 212456 kb
Host smart-37a22bc4-326b-4766-ad8e-b9db9e03349f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806871407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.806871407
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3763714429
Short name T332
Test name
Test status
Simulation time 16379572285 ps
CPU time 30.77 seconds
Started Jul 04 05:11:10 PM PDT 24
Finished Jul 04 05:11:42 PM PDT 24
Peak memory 212276 kb
Host smart-e2c52087-3094-4437-8b38-15f6cf7884b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763714429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3763714429
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2955960350
Short name T280
Test name
Test status
Simulation time 1734016964 ps
CPU time 8.63 seconds
Started Jul 04 05:11:16 PM PDT 24
Finished Jul 04 05:11:25 PM PDT 24
Peak memory 211268 kb
Host smart-26610af2-dbe3-46f1-a126-07fe4e24ea37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955960350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2955960350
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.449883773
Short name T347
Test name
Test status
Simulation time 4988550361 ps
CPU time 27.22 seconds
Started Jul 04 05:11:10 PM PDT 24
Finished Jul 04 05:11:37 PM PDT 24
Peak memory 213780 kb
Host smart-6d3bdbb4-62a7-457e-9cd9-4dd8bb67ee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449883773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.449883773
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.67865791
Short name T365
Test name
Test status
Simulation time 939893456 ps
CPU time 12.47 seconds
Started Jul 04 05:11:13 PM PDT 24
Finished Jul 04 05:11:26 PM PDT 24
Peak memory 213816 kb
Host smart-5600cbde-075c-405d-a1be-531fd27dcdab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67865791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.rom_ctrl_stress_all.67865791
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2439118866
Short name T340
Test name
Test status
Simulation time 108726701 ps
CPU time 4.29 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:10:41 PM PDT 24
Peak memory 211308 kb
Host smart-6f8ebfdb-747f-4920-b61c-747f8d2cc708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439118866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2439118866
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.328068881
Short name T130
Test name
Test status
Simulation time 269394277570 ps
CPU time 666.23 seconds
Started Jul 04 05:10:33 PM PDT 24
Finished Jul 04 05:21:40 PM PDT 24
Peak memory 236712 kb
Host smart-95a4efbb-121f-439e-89fa-aed69090f807
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328068881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.328068881
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3362815009
Short name T248
Test name
Test status
Simulation time 1508477831 ps
CPU time 14.48 seconds
Started Jul 04 05:10:37 PM PDT 24
Finished Jul 04 05:10:51 PM PDT 24
Peak memory 211884 kb
Host smart-035d0b4c-0680-4c51-8d6c-3ca2b82a4c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362815009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3362815009
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4202139773
Short name T166
Test name
Test status
Simulation time 203335157 ps
CPU time 5.79 seconds
Started Jul 04 05:10:37 PM PDT 24
Finished Jul 04 05:10:43 PM PDT 24
Peak memory 211280 kb
Host smart-1bdd30b2-0d95-48c6-8c89-c47b23472b3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202139773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4202139773
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1341406857
Short name T106
Test name
Test status
Simulation time 3356013914 ps
CPU time 28.86 seconds
Started Jul 04 05:10:31 PM PDT 24
Finished Jul 04 05:11:00 PM PDT 24
Peak memory 213332 kb
Host smart-dab6dcca-ecc6-4976-bfc9-e90b2f8644f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341406857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1341406857
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2415998805
Short name T327
Test name
Test status
Simulation time 587888469 ps
CPU time 19.27 seconds
Started Jul 04 05:10:37 PM PDT 24
Finished Jul 04 05:10:56 PM PDT 24
Peak memory 215112 kb
Host smart-69a4a32f-dfe4-441f-ae85-fae1301ab879
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415998805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2415998805
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.327396150
Short name T261
Test name
Test status
Simulation time 754366876100 ps
CPU time 1982.48 seconds
Started Jul 04 05:10:39 PM PDT 24
Finished Jul 04 05:43:42 PM PDT 24
Peak memory 237444 kb
Host smart-9b12aea4-389c-48a9-8592-3ca13e51d29b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327396150 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.327396150
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.962736643
Short name T184
Test name
Test status
Simulation time 6486762941 ps
CPU time 13.93 seconds
Started Jul 04 05:11:09 PM PDT 24
Finished Jul 04 05:11:23 PM PDT 24
Peak memory 211336 kb
Host smart-a5038902-89b4-4894-b306-5a664469f31e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962736643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.962736643
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.745010458
Short name T337
Test name
Test status
Simulation time 15962672919 ps
CPU time 116.04 seconds
Started Jul 04 05:11:14 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 234192 kb
Host smart-8b88efce-8600-4696-a5fa-348f38e32c15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745010458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.745010458
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.851354951
Short name T334
Test name
Test status
Simulation time 602539956 ps
CPU time 13.9 seconds
Started Jul 04 05:11:10 PM PDT 24
Finished Jul 04 05:11:25 PM PDT 24
Peak memory 211832 kb
Host smart-9ac213d6-5043-4da3-b04c-32b6bd906ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851354951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.851354951
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2293886241
Short name T229
Test name
Test status
Simulation time 916073962 ps
CPU time 11.08 seconds
Started Jul 04 05:11:10 PM PDT 24
Finished Jul 04 05:11:22 PM PDT 24
Peak memory 211340 kb
Host smart-ffe7fcbd-aad4-4df8-977a-36c9ec563bae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293886241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2293886241
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.848209783
Short name T131
Test name
Test status
Simulation time 16389893724 ps
CPU time 27.07 seconds
Started Jul 04 05:11:11 PM PDT 24
Finished Jul 04 05:11:38 PM PDT 24
Peak memory 213660 kb
Host smart-583f5fd0-bcf3-43dc-9199-a18593baf271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848209783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.848209783
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4256170708
Short name T167
Test name
Test status
Simulation time 1699752729 ps
CPU time 23.48 seconds
Started Jul 04 05:11:10 PM PDT 24
Finished Jul 04 05:11:34 PM PDT 24
Peak memory 212884 kb
Host smart-02ad5704-4b0e-4982-998e-8e26f64f27fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256170708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4256170708
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3704901452
Short name T267
Test name
Test status
Simulation time 175618891 ps
CPU time 4.36 seconds
Started Jul 04 05:11:09 PM PDT 24
Finished Jul 04 05:11:14 PM PDT 24
Peak memory 211196 kb
Host smart-6bab6170-e201-4402-a0a0-13a46987db27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704901452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3704901452
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1035685505
Short name T311
Test name
Test status
Simulation time 12868549875 ps
CPU time 146.99 seconds
Started Jul 04 05:11:13 PM PDT 24
Finished Jul 04 05:13:40 PM PDT 24
Peak memory 228576 kb
Host smart-78042910-a8fd-405e-834f-810b6a01ffab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035685505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1035685505
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.669997156
Short name T298
Test name
Test status
Simulation time 10927241303 ps
CPU time 25.29 seconds
Started Jul 04 05:11:12 PM PDT 24
Finished Jul 04 05:11:38 PM PDT 24
Peak memory 212304 kb
Host smart-93de3e65-0419-4af8-b30a-f1c47c052de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669997156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.669997156
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2930077353
Short name T120
Test name
Test status
Simulation time 3886227276 ps
CPU time 9.34 seconds
Started Jul 04 05:11:12 PM PDT 24
Finished Jul 04 05:11:21 PM PDT 24
Peak memory 211360 kb
Host smart-99f81e38-fb4b-44c3-bd7b-1432132e6c31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2930077353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2930077353
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2153554461
Short name T225
Test name
Test status
Simulation time 1044491917 ps
CPU time 11.51 seconds
Started Jul 04 05:11:05 PM PDT 24
Finished Jul 04 05:11:17 PM PDT 24
Peak memory 212564 kb
Host smart-2251fc9d-aa0a-4bc4-bb0b-2af2861aecc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153554461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2153554461
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2457704079
Short name T285
Test name
Test status
Simulation time 183704465 ps
CPU time 10.4 seconds
Started Jul 04 05:11:14 PM PDT 24
Finished Jul 04 05:11:25 PM PDT 24
Peak memory 211180 kb
Host smart-4fa949f2-ca6a-4ab3-ac77-e128d1d4c385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457704079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2457704079
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1143450001
Short name T326
Test name
Test status
Simulation time 5133262870 ps
CPU time 11.5 seconds
Started Jul 04 05:11:13 PM PDT 24
Finished Jul 04 05:11:25 PM PDT 24
Peak memory 211368 kb
Host smart-4805d714-f341-486b-b33f-c81a44ffc482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143450001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1143450001
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.347408370
Short name T241
Test name
Test status
Simulation time 19498442262 ps
CPU time 139.18 seconds
Started Jul 04 05:11:14 PM PDT 24
Finished Jul 04 05:13:34 PM PDT 24
Peak memory 235024 kb
Host smart-01b1c634-f8dd-445c-a25a-9a1645c271c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347408370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.347408370
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3259288631
Short name T358
Test name
Test status
Simulation time 4034867545 ps
CPU time 22.14 seconds
Started Jul 04 05:11:13 PM PDT 24
Finished Jul 04 05:11:35 PM PDT 24
Peak memory 211844 kb
Host smart-588a3359-64a1-424f-8510-62fb7bb41854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259288631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3259288631
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.597839228
Short name T85
Test name
Test status
Simulation time 6664012100 ps
CPU time 14.58 seconds
Started Jul 04 05:11:13 PM PDT 24
Finished Jul 04 05:11:27 PM PDT 24
Peak memory 211360 kb
Host smart-a7fac81e-6307-4c25-907a-48a0f34ac2b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=597839228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.597839228
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1460218400
Short name T233
Test name
Test status
Simulation time 4020528228 ps
CPU time 31.59 seconds
Started Jul 04 05:11:13 PM PDT 24
Finished Jul 04 05:11:44 PM PDT 24
Peak memory 212032 kb
Host smart-daa3022c-c26c-4e1f-b1bb-99ab6d1fe009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460218400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1460218400
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.785901122
Short name T141
Test name
Test status
Simulation time 3452904703 ps
CPU time 17.42 seconds
Started Jul 04 05:11:12 PM PDT 24
Finished Jul 04 05:11:30 PM PDT 24
Peak memory 211292 kb
Host smart-17d2c1fc-0b1e-408d-a0d6-0ebeba821571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785901122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.785901122
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.477106059
Short name T44
Test name
Test status
Simulation time 265043930909 ps
CPU time 2252.28 seconds
Started Jul 04 05:11:12 PM PDT 24
Finished Jul 04 05:48:45 PM PDT 24
Peak memory 237532 kb
Host smart-8d8d39c5-d06b-417d-bd74-410170fe93db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477106059 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.477106059
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2790496689
Short name T207
Test name
Test status
Simulation time 3215336492 ps
CPU time 14.14 seconds
Started Jul 04 05:11:15 PM PDT 24
Finished Jul 04 05:11:30 PM PDT 24
Peak memory 211324 kb
Host smart-2bb5838c-875a-4522-81a6-d97224a4798e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790496689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2790496689
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.942419352
Short name T204
Test name
Test status
Simulation time 47949574581 ps
CPU time 470.05 seconds
Started Jul 04 05:11:13 PM PDT 24
Finished Jul 04 05:19:04 PM PDT 24
Peak memory 237828 kb
Host smart-04115103-8ffa-477d-a9f5-e2d11ab4b0a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942419352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.942419352
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.430441545
Short name T316
Test name
Test status
Simulation time 175862734 ps
CPU time 9.39 seconds
Started Jul 04 05:11:11 PM PDT 24
Finished Jul 04 05:11:21 PM PDT 24
Peak memory 211904 kb
Host smart-a0e3152d-024d-4dd9-b56f-df6eca08957b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430441545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.430441545
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.324438611
Short name T2
Test name
Test status
Simulation time 1202707323 ps
CPU time 11.78 seconds
Started Jul 04 05:11:19 PM PDT 24
Finished Jul 04 05:11:31 PM PDT 24
Peak memory 211288 kb
Host smart-4860081c-e067-4c15-a8b1-5c14dc974bb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324438611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.324438611
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3232491404
Short name T145
Test name
Test status
Simulation time 7003757895 ps
CPU time 22.33 seconds
Started Jul 04 05:11:12 PM PDT 24
Finished Jul 04 05:11:35 PM PDT 24
Peak memory 213404 kb
Host smart-7e339336-4672-4f37-aadd-b2498696de48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232491404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3232491404
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1581488293
Short name T320
Test name
Test status
Simulation time 7888453138 ps
CPU time 47.77 seconds
Started Jul 04 05:11:15 PM PDT 24
Finished Jul 04 05:12:03 PM PDT 24
Peak memory 213924 kb
Host smart-0820a558-bedb-4020-b7bf-d38b2b4adaa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581488293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1581488293
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1793689264
Short name T270
Test name
Test status
Simulation time 88532884861 ps
CPU time 6419.85 seconds
Started Jul 04 05:11:18 PM PDT 24
Finished Jul 04 06:58:19 PM PDT 24
Peak memory 235760 kb
Host smart-666ba0ed-2a9a-4fc1-845e-8949b8cfd692
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793689264 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1793689264
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.868736475
Short name T142
Test name
Test status
Simulation time 4759088987 ps
CPU time 11.82 seconds
Started Jul 04 05:11:21 PM PDT 24
Finished Jul 04 05:11:33 PM PDT 24
Peak memory 211340 kb
Host smart-4e29ddb1-9584-4af2-912e-f6740c1efba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868736475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.868736475
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.666185886
Short name T158
Test name
Test status
Simulation time 64034881138 ps
CPU time 611.51 seconds
Started Jul 04 05:11:23 PM PDT 24
Finished Jul 04 05:21:35 PM PDT 24
Peak memory 212832 kb
Host smart-829728a2-7668-40b0-9272-4cc7e1758468
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666185886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.666185886
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3604695110
Short name T279
Test name
Test status
Simulation time 168681885 ps
CPU time 9.28 seconds
Started Jul 04 05:11:22 PM PDT 24
Finished Jul 04 05:11:31 PM PDT 24
Peak memory 211964 kb
Host smart-a7893b5e-4ba9-4378-9965-c43554a0e9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604695110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3604695110
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1299752487
Short name T177
Test name
Test status
Simulation time 26528375616 ps
CPU time 12.63 seconds
Started Jul 04 05:11:21 PM PDT 24
Finished Jul 04 05:11:34 PM PDT 24
Peak memory 211368 kb
Host smart-cac47866-f56f-4002-add2-57ef3c257b87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299752487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1299752487
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3836929697
Short name T206
Test name
Test status
Simulation time 863749134 ps
CPU time 13.42 seconds
Started Jul 04 05:11:25 PM PDT 24
Finished Jul 04 05:11:39 PM PDT 24
Peak memory 213132 kb
Host smart-c0aa7dea-2906-4163-aea3-fa8674132a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836929697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3836929697
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2762418680
Short name T126
Test name
Test status
Simulation time 2660393850 ps
CPU time 13.08 seconds
Started Jul 04 05:11:21 PM PDT 24
Finished Jul 04 05:11:34 PM PDT 24
Peak memory 211276 kb
Host smart-a593ca84-074d-49e7-8580-29d9f7df7ef7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762418680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2762418680
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1523804721
Short name T314
Test name
Test status
Simulation time 663981041 ps
CPU time 8.8 seconds
Started Jul 04 05:11:22 PM PDT 24
Finished Jul 04 05:11:31 PM PDT 24
Peak memory 211304 kb
Host smart-12dfcf3e-8223-4437-afa0-a7db2daf3300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523804721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1523804721
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.285135895
Short name T219
Test name
Test status
Simulation time 3641170127 ps
CPU time 92.02 seconds
Started Jul 04 05:11:19 PM PDT 24
Finished Jul 04 05:12:52 PM PDT 24
Peak memory 228116 kb
Host smart-d07ece63-f113-48c2-97ee-f9e90a7bbca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285135895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.285135895
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4005261578
Short name T247
Test name
Test status
Simulation time 8030127652 ps
CPU time 35.24 seconds
Started Jul 04 05:11:21 PM PDT 24
Finished Jul 04 05:11:56 PM PDT 24
Peak memory 212140 kb
Host smart-dc0c6b0a-19bf-492a-93ed-b0d6f51ce303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005261578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4005261578
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1922228957
Short name T255
Test name
Test status
Simulation time 1533227550 ps
CPU time 13.52 seconds
Started Jul 04 05:11:23 PM PDT 24
Finished Jul 04 05:11:37 PM PDT 24
Peak memory 211368 kb
Host smart-2e376fb0-04fd-4683-a924-6b45d3e6fe87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922228957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1922228957
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1666801772
Short name T296
Test name
Test status
Simulation time 8850934213 ps
CPU time 34.57 seconds
Started Jul 04 05:11:25 PM PDT 24
Finished Jul 04 05:12:00 PM PDT 24
Peak memory 213860 kb
Host smart-f4d2c560-7f11-468b-972a-d84add14cd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666801772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1666801772
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.460747669
Short name T143
Test name
Test status
Simulation time 2367835069 ps
CPU time 30.91 seconds
Started Jul 04 05:11:21 PM PDT 24
Finished Jul 04 05:11:52 PM PDT 24
Peak memory 213516 kb
Host smart-04595d57-df07-4e82-89eb-874eabae14f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460747669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.460747669
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.429245889
Short name T45
Test name
Test status
Simulation time 162525263435 ps
CPU time 1735.13 seconds
Started Jul 04 05:11:20 PM PDT 24
Finished Jul 04 05:40:16 PM PDT 24
Peak memory 235840 kb
Host smart-41a175c4-69a7-4613-8d54-bc0ec9807f00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429245889 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.429245889
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2708942544
Short name T24
Test name
Test status
Simulation time 7186536141 ps
CPU time 16.06 seconds
Started Jul 04 05:11:33 PM PDT 24
Finished Jul 04 05:11:49 PM PDT 24
Peak memory 211348 kb
Host smart-1f1d865b-a93c-4353-8e45-6329ee1cf111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708942544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2708942544
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1859687318
Short name T39
Test name
Test status
Simulation time 23697353915 ps
CPU time 278.61 seconds
Started Jul 04 05:11:28 PM PDT 24
Finished Jul 04 05:16:07 PM PDT 24
Peak memory 237780 kb
Host smart-46dbf1da-87f6-4707-969a-34db3e69e209
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859687318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1859687318
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1826080431
Short name T144
Test name
Test status
Simulation time 1679410211 ps
CPU time 18.95 seconds
Started Jul 04 05:11:29 PM PDT 24
Finished Jul 04 05:11:48 PM PDT 24
Peak memory 211868 kb
Host smart-31b89088-2e0d-433d-b5a1-5483cb85383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826080431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1826080431
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.165680257
Short name T121
Test name
Test status
Simulation time 895728465 ps
CPU time 6.84 seconds
Started Jul 04 05:11:29 PM PDT 24
Finished Jul 04 05:11:36 PM PDT 24
Peak memory 211368 kb
Host smart-d98e73eb-413e-4383-a9da-20588fd01f21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165680257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.165680257
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1185659276
Short name T181
Test name
Test status
Simulation time 2427502478 ps
CPU time 18.87 seconds
Started Jul 04 05:11:27 PM PDT 24
Finished Jul 04 05:11:46 PM PDT 24
Peak memory 213608 kb
Host smart-e8b84fef-9b0c-4087-b245-427dbf1b584c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185659276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1185659276
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2890275842
Short name T89
Test name
Test status
Simulation time 338685673 ps
CPU time 8.22 seconds
Started Jul 04 05:11:30 PM PDT 24
Finished Jul 04 05:11:38 PM PDT 24
Peak memory 211372 kb
Host smart-2496cdc5-1aed-47bf-ad47-f997183c7f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890275842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2890275842
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2644197848
Short name T333
Test name
Test status
Simulation time 903496075 ps
CPU time 10.06 seconds
Started Jul 04 05:11:30 PM PDT 24
Finished Jul 04 05:11:41 PM PDT 24
Peak memory 211292 kb
Host smart-cba89f7c-a0eb-4faa-bcb7-a391837fa9c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644197848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2644197848
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1338275636
Short name T42
Test name
Test status
Simulation time 7733612994 ps
CPU time 161.77 seconds
Started Jul 04 05:11:28 PM PDT 24
Finished Jul 04 05:14:10 PM PDT 24
Peak memory 234840 kb
Host smart-8aed0d50-c24c-45c3-bba8-70638c979125
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338275636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1338275636
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2998056047
Short name T308
Test name
Test status
Simulation time 1833320621 ps
CPU time 18.28 seconds
Started Jul 04 05:11:30 PM PDT 24
Finished Jul 04 05:11:49 PM PDT 24
Peak memory 211960 kb
Host smart-cf5c821c-73d7-4539-994a-744c6c7efa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998056047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2998056047
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.310626203
Short name T193
Test name
Test status
Simulation time 99346947 ps
CPU time 5.35 seconds
Started Jul 04 05:11:29 PM PDT 24
Finished Jul 04 05:11:35 PM PDT 24
Peak memory 211336 kb
Host smart-3c25b8dd-c07e-4130-9766-e8d9edec4998
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=310626203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.310626203
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3212696994
Short name T6
Test name
Test status
Simulation time 4133835970 ps
CPU time 36.24 seconds
Started Jul 04 05:11:29 PM PDT 24
Finished Jul 04 05:12:06 PM PDT 24
Peak memory 213456 kb
Host smart-9b4841e5-1689-4260-9c9c-e1959848acb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212696994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3212696994
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1413015119
Short name T310
Test name
Test status
Simulation time 2089343132 ps
CPU time 21.46 seconds
Started Jul 04 05:11:28 PM PDT 24
Finished Jul 04 05:11:50 PM PDT 24
Peak memory 215360 kb
Host smart-9899ac37-f44d-4375-a817-e50cdd6c7b77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413015119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1413015119
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2143646655
Short name T321
Test name
Test status
Simulation time 189970226495 ps
CPU time 749.56 seconds
Started Jul 04 05:11:31 PM PDT 24
Finished Jul 04 05:24:01 PM PDT 24
Peak memory 235812 kb
Host smart-dd2cf98d-8142-4bf3-a065-bd83b0c2fe64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143646655 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2143646655
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3133174764
Short name T153
Test name
Test status
Simulation time 1581208725 ps
CPU time 13.86 seconds
Started Jul 04 05:11:30 PM PDT 24
Finished Jul 04 05:11:44 PM PDT 24
Peak memory 211316 kb
Host smart-a7591e13-c800-4b67-81b5-a8dac5b6b468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133174764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3133174764
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4212449536
Short name T168
Test name
Test status
Simulation time 128392865172 ps
CPU time 336.55 seconds
Started Jul 04 05:11:30 PM PDT 24
Finished Jul 04 05:17:06 PM PDT 24
Peak memory 213548 kb
Host smart-b6859a55-e21a-4a61-a9c1-bcd007ac1202
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212449536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.4212449536
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.666222442
Short name T47
Test name
Test status
Simulation time 3174660033 ps
CPU time 19.52 seconds
Started Jul 04 05:11:28 PM PDT 24
Finished Jul 04 05:11:48 PM PDT 24
Peak memory 212144 kb
Host smart-67a9ef7e-d206-4ac5-bc97-fcad8d9b0a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666222442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.666222442
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1059527811
Short name T198
Test name
Test status
Simulation time 378677539 ps
CPU time 5.49 seconds
Started Jul 04 05:11:29 PM PDT 24
Finished Jul 04 05:11:35 PM PDT 24
Peak memory 211320 kb
Host smart-c9a0a89b-d199-49a4-9d48-cf38fb21b220
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059527811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1059527811
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2858736573
Short name T343
Test name
Test status
Simulation time 3434972331 ps
CPU time 10.05 seconds
Started Jul 04 05:11:29 PM PDT 24
Finished Jul 04 05:11:39 PM PDT 24
Peak memory 213424 kb
Host smart-dda0ab53-8b03-4d2c-82f0-1b23e7d360fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858736573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2858736573
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4226073439
Short name T71
Test name
Test status
Simulation time 5294021514 ps
CPU time 15.2 seconds
Started Jul 04 05:11:29 PM PDT 24
Finished Jul 04 05:11:44 PM PDT 24
Peak memory 211408 kb
Host smart-a43672b0-7b30-49d7-8e2c-2676ea05468d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226073439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4226073439
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3936090867
Short name T11
Test name
Test status
Simulation time 130783569648 ps
CPU time 2239.35 seconds
Started Jul 04 05:11:29 PM PDT 24
Finished Jul 04 05:48:49 PM PDT 24
Peak memory 235744 kb
Host smart-3e3f9889-f4f0-4570-afcf-b8422847e49a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936090867 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3936090867
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2289745826
Short name T221
Test name
Test status
Simulation time 7018794981 ps
CPU time 15.96 seconds
Started Jul 04 05:11:35 PM PDT 24
Finished Jul 04 05:11:51 PM PDT 24
Peak memory 211412 kb
Host smart-83829e5f-27fe-469e-ac5e-2fdac4784471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289745826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2289745826
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3652138085
Short name T325
Test name
Test status
Simulation time 12038316786 ps
CPU time 156.04 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:14:12 PM PDT 24
Peak memory 235240 kb
Host smart-09ff1636-3770-4489-aa51-9435d7cedf10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652138085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3652138085
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3105471761
Short name T243
Test name
Test status
Simulation time 4143967366 ps
CPU time 33.12 seconds
Started Jul 04 05:11:34 PM PDT 24
Finished Jul 04 05:12:07 PM PDT 24
Peak memory 212924 kb
Host smart-12470306-362f-44b2-b90d-48449fc0d7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105471761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3105471761
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.9590671
Short name T335
Test name
Test status
Simulation time 7885559430 ps
CPU time 16.39 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:53 PM PDT 24
Peak memory 211352 kb
Host smart-f0005f74-0033-4f7e-bf1e-2689760beba0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9590671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.9590671
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.830026996
Short name T263
Test name
Test status
Simulation time 191670293 ps
CPU time 9.91 seconds
Started Jul 04 05:11:27 PM PDT 24
Finished Jul 04 05:11:37 PM PDT 24
Peak memory 212996 kb
Host smart-390dcce8-fb65-44b5-acd1-4fdeeebd290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830026996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.830026996
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3774833888
Short name T182
Test name
Test status
Simulation time 555375810 ps
CPU time 31.01 seconds
Started Jul 04 05:11:37 PM PDT 24
Finished Jul 04 05:12:08 PM PDT 24
Peak memory 216740 kb
Host smart-9b9b713d-3577-4226-9944-f5dd7886d3e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774833888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3774833888
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2138652562
Short name T138
Test name
Test status
Simulation time 5198377037 ps
CPU time 8.01 seconds
Started Jul 04 05:10:31 PM PDT 24
Finished Jul 04 05:10:39 PM PDT 24
Peak memory 211368 kb
Host smart-5e11b8ed-69d6-4d0e-99d6-5909218ba867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138652562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2138652562
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3638175926
Short name T227
Test name
Test status
Simulation time 44247374588 ps
CPU time 447.07 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:18:03 PM PDT 24
Peak memory 233828 kb
Host smart-97bee60f-09a6-451c-a43c-254c0a72243f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638175926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3638175926
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3031538408
Short name T191
Test name
Test status
Simulation time 1106256547 ps
CPU time 9.6 seconds
Started Jul 04 05:10:31 PM PDT 24
Finished Jul 04 05:10:41 PM PDT 24
Peak memory 211884 kb
Host smart-60fbf57f-8d9b-4859-9c23-f8f9bdc0b2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031538408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3031538408
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3042569411
Short name T146
Test name
Test status
Simulation time 2199999578 ps
CPU time 17.71 seconds
Started Jul 04 05:10:37 PM PDT 24
Finished Jul 04 05:10:55 PM PDT 24
Peak memory 211308 kb
Host smart-aadad6d0-194a-4bd5-b64c-79f845e822bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042569411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3042569411
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2473552855
Short name T129
Test name
Test status
Simulation time 2695486815 ps
CPU time 14.63 seconds
Started Jul 04 05:10:39 PM PDT 24
Finished Jul 04 05:10:54 PM PDT 24
Peak memory 213820 kb
Host smart-96a117cd-2e5f-498e-8bf6-0542e22229fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473552855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2473552855
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3322932195
Short name T201
Test name
Test status
Simulation time 18859194981 ps
CPU time 38.43 seconds
Started Jul 04 05:10:35 PM PDT 24
Finished Jul 04 05:11:14 PM PDT 24
Peak memory 216792 kb
Host smart-9314bc1b-4362-4596-a2d0-d72e893c57fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322932195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3322932195
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3666289096
Short name T342
Test name
Test status
Simulation time 5914005475 ps
CPU time 11.13 seconds
Started Jul 04 05:10:34 PM PDT 24
Finished Jul 04 05:10:46 PM PDT 24
Peak memory 211356 kb
Host smart-9e73668e-cf52-486b-9c41-313ec9ee8ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666289096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3666289096
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2017621599
Short name T317
Test name
Test status
Simulation time 5425970121 ps
CPU time 141.03 seconds
Started Jul 04 05:10:34 PM PDT 24
Finished Jul 04 05:12:56 PM PDT 24
Peak memory 228560 kb
Host smart-c4050d83-ed21-482e-9c53-31a1cc24a678
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017621599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2017621599
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2717661587
Short name T291
Test name
Test status
Simulation time 3966106589 ps
CPU time 15.73 seconds
Started Jul 04 05:10:35 PM PDT 24
Finished Jul 04 05:10:51 PM PDT 24
Peak memory 212516 kb
Host smart-94bd684e-2416-432f-b644-9585ac0b867a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717661587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2717661587
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3093580722
Short name T223
Test name
Test status
Simulation time 98302447 ps
CPU time 5.37 seconds
Started Jul 04 05:10:35 PM PDT 24
Finished Jul 04 05:10:41 PM PDT 24
Peak memory 211388 kb
Host smart-e1c33668-17ca-4b1c-82a7-0732fcf07666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093580722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3093580722
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1204894861
Short name T173
Test name
Test status
Simulation time 4949799169 ps
CPU time 35.77 seconds
Started Jul 04 05:10:31 PM PDT 24
Finished Jul 04 05:11:07 PM PDT 24
Peak memory 213512 kb
Host smart-f0fef59f-4d1a-4dfc-8a65-a2e6415fb66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204894861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1204894861
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1274606833
Short name T203
Test name
Test status
Simulation time 2507770363 ps
CPU time 22.58 seconds
Started Jul 04 05:10:34 PM PDT 24
Finished Jul 04 05:10:57 PM PDT 24
Peak memory 216032 kb
Host smart-6a979e1b-84c6-43ce-b425-534120106858
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274606833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1274606833
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2568302231
Short name T26
Test name
Test status
Simulation time 14475054739 ps
CPU time 510.26 seconds
Started Jul 04 05:10:30 PM PDT 24
Finished Jul 04 05:19:01 PM PDT 24
Peak memory 228068 kb
Host smart-c330e424-5e42-4cb3-8034-d2cc5f1ea108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568302231 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2568302231
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4021188945
Short name T265
Test name
Test status
Simulation time 379284502 ps
CPU time 4.32 seconds
Started Jul 04 05:10:35 PM PDT 24
Finished Jul 04 05:10:40 PM PDT 24
Peak memory 211264 kb
Host smart-82a1c4e3-afbc-4a31-9797-9e6d33b8d9c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021188945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4021188945
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.287926197
Short name T213
Test name
Test status
Simulation time 29386870448 ps
CPU time 280.26 seconds
Started Jul 04 05:10:34 PM PDT 24
Finished Jul 04 05:15:15 PM PDT 24
Peak memory 237808 kb
Host smart-a451d759-b46e-483f-85ab-2478b7b7635d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287926197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.287926197
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2469004069
Short name T331
Test name
Test status
Simulation time 4821952357 ps
CPU time 25.1 seconds
Started Jul 04 05:10:39 PM PDT 24
Finished Jul 04 05:11:04 PM PDT 24
Peak memory 212088 kb
Host smart-def9028e-0b26-4cdb-bf86-3cfb00c17366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469004069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2469004069
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.247522193
Short name T107
Test name
Test status
Simulation time 8816449264 ps
CPU time 9.35 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:10:46 PM PDT 24
Peak memory 211396 kb
Host smart-5d8ca4ee-a23c-4780-bfbd-256d60461be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247522193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.247522193
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.407197802
Short name T232
Test name
Test status
Simulation time 12985064944 ps
CPU time 26.3 seconds
Started Jul 04 05:10:34 PM PDT 24
Finished Jul 04 05:11:01 PM PDT 24
Peak memory 214484 kb
Host smart-92f77b77-631a-4c75-9d00-1bc0737fbea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407197802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.407197802
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.760295346
Short name T12
Test name
Test status
Simulation time 116731364381 ps
CPU time 74.55 seconds
Started Jul 04 05:10:34 PM PDT 24
Finished Jul 04 05:11:49 PM PDT 24
Peak memory 219384 kb
Host smart-a2ecc4a1-7e4c-4814-8ee6-b32ce968dcf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760295346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.760295346
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.518664604
Short name T176
Test name
Test status
Simulation time 5270898837 ps
CPU time 11.93 seconds
Started Jul 04 05:10:50 PM PDT 24
Finished Jul 04 05:11:02 PM PDT 24
Peak memory 211200 kb
Host smart-f0cdf94b-3b57-42bd-bfff-bdd559c2c013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518664604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.518664604
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3858451167
Short name T360
Test name
Test status
Simulation time 206347608866 ps
CPU time 503.53 seconds
Started Jul 04 05:10:42 PM PDT 24
Finished Jul 04 05:19:06 PM PDT 24
Peak memory 212524 kb
Host smart-5918a221-ba84-4c3b-bb0b-a896735969d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858451167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3858451167
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2869056687
Short name T309
Test name
Test status
Simulation time 2750908405 ps
CPU time 14.47 seconds
Started Jul 04 05:10:44 PM PDT 24
Finished Jul 04 05:10:58 PM PDT 24
Peak memory 211932 kb
Host smart-7f4cfda5-9b2e-4fe1-bde8-47efd7afd1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869056687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2869056687
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2113446759
Short name T275
Test name
Test status
Simulation time 7023668598 ps
CPU time 15.06 seconds
Started Jul 04 05:10:36 PM PDT 24
Finished Jul 04 05:10:51 PM PDT 24
Peak memory 211316 kb
Host smart-5ffcd299-e265-4bd4-9fac-244a6749172d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113446759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2113446759
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2056058264
Short name T127
Test name
Test status
Simulation time 1543066662 ps
CPU time 16.3 seconds
Started Jul 04 05:10:37 PM PDT 24
Finished Jul 04 05:10:54 PM PDT 24
Peak memory 213652 kb
Host smart-b1ae47b0-19aa-4557-a439-133d5a8b1d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056058264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2056058264
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3628329160
Short name T183
Test name
Test status
Simulation time 11549574632 ps
CPU time 96.68 seconds
Started Jul 04 05:10:39 PM PDT 24
Finished Jul 04 05:12:16 PM PDT 24
Peak memory 219404 kb
Host smart-f3ec9b81-c3eb-4d52-ab01-1fba99b9c090
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628329160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3628329160
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.759194695
Short name T328
Test name
Test status
Simulation time 1314161472 ps
CPU time 6.34 seconds
Started Jul 04 05:10:51 PM PDT 24
Finished Jul 04 05:10:58 PM PDT 24
Peak memory 211324 kb
Host smart-002b0c28-77b5-4540-b416-f61625b46e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759194695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.759194695
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.852051641
Short name T192
Test name
Test status
Simulation time 60128409291 ps
CPU time 568.05 seconds
Started Jul 04 05:10:49 PM PDT 24
Finished Jul 04 05:20:17 PM PDT 24
Peak memory 225896 kb
Host smart-108f5d9d-b8d7-474f-8ae6-c7eaedfac323
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852051641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.852051641
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1642141395
Short name T276
Test name
Test status
Simulation time 8865395456 ps
CPU time 22.74 seconds
Started Jul 04 05:10:48 PM PDT 24
Finished Jul 04 05:11:11 PM PDT 24
Peak memory 212300 kb
Host smart-1675afb3-fefd-4fde-914b-9c0940add941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642141395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1642141395
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1621306032
Short name T346
Test name
Test status
Simulation time 1414734077 ps
CPU time 13.38 seconds
Started Jul 04 05:10:41 PM PDT 24
Finished Jul 04 05:10:55 PM PDT 24
Peak memory 211264 kb
Host smart-3c0710ab-3197-46b2-b1f4-825d2dac1f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621306032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1621306032
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1539304487
Short name T258
Test name
Test status
Simulation time 2099389545 ps
CPU time 16.49 seconds
Started Jul 04 05:10:42 PM PDT 24
Finished Jul 04 05:10:58 PM PDT 24
Peak memory 213420 kb
Host smart-c6e7d85b-7889-41a1-8e24-0a5a85443d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539304487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1539304487
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.716515264
Short name T135
Test name
Test status
Simulation time 346401785 ps
CPU time 15.3 seconds
Started Jul 04 05:10:54 PM PDT 24
Finished Jul 04 05:11:09 PM PDT 24
Peak memory 214540 kb
Host smart-e7879b3a-9591-4a1d-a5b3-8b461f31ed53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716515264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.716515264
Directory /workspace/9.rom_ctrl_stress_all/latest
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