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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.51 96.89 92.56 97.67 100.00 98.97 97.45 99.07


Total test records in report: 464
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T296 /workspace/coverage/default/24.rom_ctrl_alert_test.4228397618 Jul 05 04:32:53 PM PDT 24 Jul 05 04:33:09 PM PDT 24 8084999976 ps
T297 /workspace/coverage/default/37.rom_ctrl_smoke.3278364368 Jul 05 04:33:08 PM PDT 24 Jul 05 04:33:40 PM PDT 24 20208116369 ps
T298 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1135145181 Jul 05 04:33:03 PM PDT 24 Jul 05 04:36:46 PM PDT 24 24199982362 ps
T299 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.781222675 Jul 05 04:32:42 PM PDT 24 Jul 05 04:32:56 PM PDT 24 519156116 ps
T300 /workspace/coverage/default/20.rom_ctrl_alert_test.1285317691 Jul 05 04:32:50 PM PDT 24 Jul 05 04:32:58 PM PDT 24 1032733575 ps
T301 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1711303105 Jul 05 04:32:47 PM PDT 24 Jul 05 04:33:13 PM PDT 24 10588709150 ps
T302 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.349075357 Jul 05 04:32:44 PM PDT 24 Jul 05 04:32:51 PM PDT 24 99900701 ps
T303 /workspace/coverage/default/39.rom_ctrl_smoke.3010406614 Jul 05 04:34:10 PM PDT 24 Jul 05 04:34:40 PM PDT 24 3022777791 ps
T304 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1447672556 Jul 05 04:32:53 PM PDT 24 Jul 05 04:36:37 PM PDT 24 18147851187 ps
T305 /workspace/coverage/default/10.rom_ctrl_smoke.988200355 Jul 05 04:32:54 PM PDT 24 Jul 05 04:33:32 PM PDT 24 13626294768 ps
T306 /workspace/coverage/default/21.rom_ctrl_alert_test.3732947773 Jul 05 04:32:36 PM PDT 24 Jul 05 04:32:57 PM PDT 24 6951707679 ps
T307 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4280893559 Jul 05 04:32:47 PM PDT 24 Jul 05 04:33:07 PM PDT 24 3115092843 ps
T308 /workspace/coverage/default/41.rom_ctrl_smoke.36115726 Jul 05 04:33:14 PM PDT 24 Jul 05 04:33:28 PM PDT 24 717121616 ps
T309 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1366448512 Jul 05 04:32:43 PM PDT 24 Jul 05 04:32:51 PM PDT 24 436040959 ps
T310 /workspace/coverage/default/31.rom_ctrl_stress_all.1236141045 Jul 05 04:32:50 PM PDT 24 Jul 05 04:33:53 PM PDT 24 5556205580 ps
T48 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.658904022 Jul 05 04:32:51 PM PDT 24 Jul 05 04:33:26 PM PDT 24 3644237557 ps
T311 /workspace/coverage/default/49.rom_ctrl_smoke.3267523763 Jul 05 04:33:08 PM PDT 24 Jul 05 04:33:39 PM PDT 24 15045107673 ps
T312 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.254226800 Jul 05 04:32:47 PM PDT 24 Jul 05 04:33:03 PM PDT 24 2903177001 ps
T313 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3033966513 Jul 05 04:33:05 PM PDT 24 Jul 05 04:35:20 PM PDT 24 5399809379 ps
T314 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1206737775 Jul 05 04:32:28 PM PDT 24 Jul 05 04:53:08 PM PDT 24 96623304916 ps
T315 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3013739094 Jul 05 04:32:58 PM PDT 24 Jul 05 04:33:26 PM PDT 24 2989415826 ps
T316 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3349861706 Jul 05 04:32:47 PM PDT 24 Jul 05 04:32:55 PM PDT 24 368183702 ps
T317 /workspace/coverage/default/4.rom_ctrl_alert_test.2305036013 Jul 05 04:32:23 PM PDT 24 Jul 05 04:32:31 PM PDT 24 581015701 ps
T318 /workspace/coverage/default/3.rom_ctrl_stress_all.1876955610 Jul 05 04:32:38 PM PDT 24 Jul 05 04:33:13 PM PDT 24 2982074264 ps
T319 /workspace/coverage/default/14.rom_ctrl_alert_test.2604034175 Jul 05 04:32:53 PM PDT 24 Jul 05 04:33:09 PM PDT 24 1401546485 ps
T320 /workspace/coverage/default/36.rom_ctrl_stress_all.885231059 Jul 05 04:32:58 PM PDT 24 Jul 05 04:33:20 PM PDT 24 300303973 ps
T321 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.358587236 Jul 05 04:32:43 PM PDT 24 Jul 05 04:33:03 PM PDT 24 8651886888 ps
T322 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1926531203 Jul 05 04:32:28 PM PDT 24 Jul 05 04:32:59 PM PDT 24 14434341686 ps
T323 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.664564770 Jul 05 04:33:04 PM PDT 24 Jul 05 04:33:16 PM PDT 24 334527906 ps
T324 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3814438742 Jul 05 04:32:31 PM PDT 24 Jul 05 04:36:37 PM PDT 24 29972693284 ps
T325 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.175412730 Jul 05 04:32:58 PM PDT 24 Jul 05 04:33:14 PM PDT 24 2636901026 ps
T326 /workspace/coverage/default/47.rom_ctrl_stress_all.3294942798 Jul 05 04:33:09 PM PDT 24 Jul 05 04:33:37 PM PDT 24 4039716844 ps
T327 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2715919917 Jul 05 04:33:21 PM PDT 24 Jul 05 04:35:11 PM PDT 24 4010276035 ps
T328 /workspace/coverage/default/39.rom_ctrl_stress_all.397562759 Jul 05 04:33:19 PM PDT 24 Jul 05 04:33:42 PM PDT 24 6114635899 ps
T329 /workspace/coverage/default/28.rom_ctrl_alert_test.1757203478 Jul 05 04:32:58 PM PDT 24 Jul 05 04:33:04 PM PDT 24 87218634 ps
T330 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.174969310 Jul 05 04:32:50 PM PDT 24 Jul 05 04:33:10 PM PDT 24 2179797291 ps
T331 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.617100450 Jul 05 04:32:41 PM PDT 24 Jul 05 05:42:27 PM PDT 24 450482248853 ps
T332 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4277021759 Jul 05 04:32:58 PM PDT 24 Jul 05 04:33:28 PM PDT 24 6244751188 ps
T333 /workspace/coverage/default/13.rom_ctrl_stress_all.3551641174 Jul 05 04:32:48 PM PDT 24 Jul 05 04:33:04 PM PDT 24 215266485 ps
T103 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4095822724 Jul 05 04:33:09 PM PDT 24 Jul 05 04:33:16 PM PDT 24 381522656 ps
T334 /workspace/coverage/default/48.rom_ctrl_stress_all.568983409 Jul 05 04:33:07 PM PDT 24 Jul 05 04:34:35 PM PDT 24 18802004397 ps
T335 /workspace/coverage/default/38.rom_ctrl_stress_all.2120135402 Jul 05 04:33:00 PM PDT 24 Jul 05 04:33:13 PM PDT 24 3289106307 ps
T336 /workspace/coverage/default/5.rom_ctrl_smoke.3527381336 Jul 05 04:32:23 PM PDT 24 Jul 05 04:32:34 PM PDT 24 185889075 ps
T337 /workspace/coverage/default/8.rom_ctrl_stress_all.2590829802 Jul 05 04:32:22 PM PDT 24 Jul 05 04:33:39 PM PDT 24 17526588844 ps
T338 /workspace/coverage/default/44.rom_ctrl_smoke.2189474499 Jul 05 04:33:05 PM PDT 24 Jul 05 04:33:44 PM PDT 24 3921551080 ps
T339 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1665263444 Jul 05 04:33:03 PM PDT 24 Jul 05 04:40:42 PM PDT 24 307120248178 ps
T340 /workspace/coverage/default/41.rom_ctrl_alert_test.3087126118 Jul 05 04:33:07 PM PDT 24 Jul 05 04:33:21 PM PDT 24 5105770702 ps
T341 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2868484987 Jul 05 04:32:50 PM PDT 24 Jul 05 04:33:11 PM PDT 24 2104595054 ps
T342 /workspace/coverage/default/33.rom_ctrl_smoke.806000838 Jul 05 04:32:42 PM PDT 24 Jul 05 04:33:12 PM PDT 24 4980562348 ps
T343 /workspace/coverage/default/3.rom_ctrl_smoke.3225459208 Jul 05 04:32:21 PM PDT 24 Jul 05 04:32:55 PM PDT 24 3919464305 ps
T344 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.975183351 Jul 05 04:32:58 PM PDT 24 Jul 05 04:33:14 PM PDT 24 5963230288 ps
T345 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1722887229 Jul 05 04:32:39 PM PDT 24 Jul 05 04:33:02 PM PDT 24 9424515446 ps
T346 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.211314203 Jul 05 04:32:48 PM PDT 24 Jul 05 04:33:03 PM PDT 24 2282636808 ps
T347 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2179738195 Jul 05 04:33:10 PM PDT 24 Jul 05 05:17:05 PM PDT 24 70291559314 ps
T348 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3746640355 Jul 05 04:33:12 PM PDT 24 Jul 05 04:33:25 PM PDT 24 173711705 ps
T349 /workspace/coverage/default/9.rom_ctrl_alert_test.3435007308 Jul 05 04:32:53 PM PDT 24 Jul 05 04:33:04 PM PDT 24 278446901 ps
T350 /workspace/coverage/default/0.rom_ctrl_alert_test.4217282799 Jul 05 04:32:32 PM PDT 24 Jul 05 04:32:39 PM PDT 24 210417382 ps
T351 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3103469564 Jul 05 04:32:54 PM PDT 24 Jul 05 06:15:27 PM PDT 24 26129507327 ps
T352 /workspace/coverage/default/14.rom_ctrl_stress_all.4063700231 Jul 05 04:32:51 PM PDT 24 Jul 05 04:33:58 PM PDT 24 11427037815 ps
T353 /workspace/coverage/default/16.rom_ctrl_stress_all.1263908057 Jul 05 04:32:40 PM PDT 24 Jul 05 04:33:51 PM PDT 24 25514854991 ps
T354 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2980240351 Jul 05 04:33:10 PM PDT 24 Jul 05 04:33:21 PM PDT 24 340748726 ps
T355 /workspace/coverage/default/30.rom_ctrl_alert_test.464201014 Jul 05 04:33:03 PM PDT 24 Jul 05 04:33:19 PM PDT 24 6403974208 ps
T356 /workspace/coverage/default/16.rom_ctrl_smoke.2410272394 Jul 05 04:32:51 PM PDT 24 Jul 05 04:33:09 PM PDT 24 2996743873 ps
T357 /workspace/coverage/default/42.rom_ctrl_alert_test.1390057128 Jul 05 04:33:25 PM PDT 24 Jul 05 04:33:34 PM PDT 24 98988830 ps
T358 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3724892023 Jul 05 04:33:13 PM PDT 24 Jul 05 04:33:24 PM PDT 24 1783035663 ps
T359 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.34128752 Jul 05 04:33:04 PM PDT 24 Jul 05 05:37:03 PM PDT 24 154471758861 ps
T360 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3698194579 Jul 05 04:32:49 PM PDT 24 Jul 05 04:33:16 PM PDT 24 49432642890 ps
T361 /workspace/coverage/default/7.rom_ctrl_stress_all.1507960289 Jul 05 04:32:29 PM PDT 24 Jul 05 04:33:10 PM PDT 24 3568650910 ps
T362 /workspace/coverage/default/49.rom_ctrl_stress_all.1032251440 Jul 05 04:33:08 PM PDT 24 Jul 05 04:35:46 PM PDT 24 46115376177 ps
T66 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1927530012 Jul 05 04:29:03 PM PDT 24 Jul 05 04:29:45 PM PDT 24 2914386596 ps
T67 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.757572958 Jul 05 04:28:56 PM PDT 24 Jul 05 04:29:12 PM PDT 24 705772992 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2593961667 Jul 05 04:28:33 PM PDT 24 Jul 05 04:28:59 PM PDT 24 1577450228 ps
T63 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3735050781 Jul 05 04:28:32 PM PDT 24 Jul 05 04:29:56 PM PDT 24 3561528865 ps
T363 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3002731316 Jul 05 04:28:48 PM PDT 24 Jul 05 04:29:04 PM PDT 24 464193620 ps
T72 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1891788267 Jul 05 04:28:52 PM PDT 24 Jul 05 04:29:12 PM PDT 24 7459458445 ps
T73 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3429785116 Jul 05 04:28:45 PM PDT 24 Jul 05 04:29:06 PM PDT 24 1172272747 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3024402083 Jul 05 04:28:26 PM PDT 24 Jul 05 04:28:51 PM PDT 24 5267493134 ps
T365 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1623877110 Jul 05 04:28:55 PM PDT 24 Jul 05 04:29:16 PM PDT 24 1303652796 ps
T104 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2924623243 Jul 05 04:28:57 PM PDT 24 Jul 05 04:29:23 PM PDT 24 8027461263 ps
T64 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.974518495 Jul 05 04:28:55 PM PDT 24 Jul 05 04:29:44 PM PDT 24 278408589 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2822592605 Jul 05 04:28:36 PM PDT 24 Jul 05 04:29:09 PM PDT 24 2780488688 ps
T105 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3924952493 Jul 05 04:28:57 PM PDT 24 Jul 05 04:29:23 PM PDT 24 3843390563 ps
T65 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3038908706 Jul 05 04:28:45 PM PDT 24 Jul 05 04:29:43 PM PDT 24 21618684242 ps
T367 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3557928578 Jul 05 04:29:03 PM PDT 24 Jul 05 04:29:17 PM PDT 24 380756728 ps
T368 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1647056228 Jul 05 04:28:46 PM PDT 24 Jul 05 04:29:08 PM PDT 24 2614631919 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1553879848 Jul 05 04:28:59 PM PDT 24 Jul 05 04:29:12 PM PDT 24 91108460 ps
T369 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.989868148 Jul 05 04:28:46 PM PDT 24 Jul 05 04:29:01 PM PDT 24 209603421 ps
T74 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.168515587 Jul 05 04:28:47 PM PDT 24 Jul 05 04:30:25 PM PDT 24 39480592222 ps
T97 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.419639293 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:16 PM PDT 24 1787366847 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1631709610 Jul 05 04:28:59 PM PDT 24 Jul 05 04:29:27 PM PDT 24 1449688417 ps
T370 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3769794434 Jul 05 04:29:05 PM PDT 24 Jul 05 04:29:19 PM PDT 24 381027596 ps
T107 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2771449755 Jul 05 04:28:36 PM PDT 24 Jul 05 04:28:55 PM PDT 24 6246428554 ps
T98 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3516713778 Jul 05 04:29:03 PM PDT 24 Jul 05 04:29:28 PM PDT 24 8068714038 ps
T99 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.824155579 Jul 05 04:28:57 PM PDT 24 Jul 05 04:29:16 PM PDT 24 3276810910 ps
T76 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1673542990 Jul 05 04:28:52 PM PDT 24 Jul 05 04:29:17 PM PDT 24 3954784965 ps
T77 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1337024564 Jul 05 04:28:50 PM PDT 24 Jul 05 04:29:14 PM PDT 24 9283078523 ps
T100 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.359600645 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:06 PM PDT 24 95800213 ps
T371 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3993250969 Jul 05 04:28:49 PM PDT 24 Jul 05 04:29:04 PM PDT 24 1563308142 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2559838715 Jul 05 04:28:41 PM PDT 24 Jul 05 04:29:07 PM PDT 24 2459298063 ps
T373 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.317995206 Jul 05 04:28:36 PM PDT 24 Jul 05 04:28:59 PM PDT 24 2823698244 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3814822408 Jul 05 04:28:48 PM PDT 24 Jul 05 04:29:06 PM PDT 24 696391108 ps
T78 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.130634401 Jul 05 04:28:52 PM PDT 24 Jul 05 04:29:14 PM PDT 24 977775131 ps
T375 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.136169201 Jul 05 04:28:34 PM PDT 24 Jul 05 04:28:58 PM PDT 24 3599033024 ps
T79 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.316965259 Jul 05 04:28:38 PM PDT 24 Jul 05 04:29:04 PM PDT 24 6558889750 ps
T80 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2101389490 Jul 05 04:28:57 PM PDT 24 Jul 05 04:29:24 PM PDT 24 2061804374 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2504545432 Jul 05 04:28:30 PM PDT 24 Jul 05 04:28:52 PM PDT 24 3229051781 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1466228904 Jul 05 04:28:51 PM PDT 24 Jul 05 04:30:20 PM PDT 24 33524586350 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3810881458 Jul 05 04:28:31 PM PDT 24 Jul 05 04:28:53 PM PDT 24 1538000160 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.564397842 Jul 05 04:28:52 PM PDT 24 Jul 05 04:29:13 PM PDT 24 564265345 ps
T379 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.752162223 Jul 05 04:28:41 PM PDT 24 Jul 05 04:29:11 PM PDT 24 3939648312 ps
T380 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.459027009 Jul 05 04:28:37 PM PDT 24 Jul 05 04:29:06 PM PDT 24 37914847073 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1767120704 Jul 05 04:28:49 PM PDT 24 Jul 05 04:29:13 PM PDT 24 3518904525 ps
T111 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2358111057 Jul 05 04:29:00 PM PDT 24 Jul 05 04:29:56 PM PDT 24 1220519424 ps
T381 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3835266490 Jul 05 04:28:45 PM PDT 24 Jul 05 04:28:59 PM PDT 24 347846804 ps
T112 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2991300188 Jul 05 04:28:54 PM PDT 24 Jul 05 04:29:39 PM PDT 24 290505670 ps
T382 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3095516848 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:20 PM PDT 24 290843215 ps
T88 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.537409877 Jul 05 04:28:45 PM PDT 24 Jul 05 04:30:27 PM PDT 24 22640538577 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2438836872 Jul 05 04:28:56 PM PDT 24 Jul 05 04:29:16 PM PDT 24 1083605884 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.469694536 Jul 05 04:28:51 PM PDT 24 Jul 05 04:29:11 PM PDT 24 992857760 ps
T385 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.216660874 Jul 05 04:28:50 PM PDT 24 Jul 05 04:29:15 PM PDT 24 5053103680 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2761889629 Jul 05 04:28:36 PM PDT 24 Jul 05 04:29:02 PM PDT 24 1246412346 ps
T387 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.833718389 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:18 PM PDT 24 171751292 ps
T388 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4141294751 Jul 05 04:29:05 PM PDT 24 Jul 05 04:29:30 PM PDT 24 2145784567 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3366703655 Jul 05 04:28:34 PM PDT 24 Jul 05 04:29:28 PM PDT 24 15798470897 ps
T389 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4130242531 Jul 05 04:28:55 PM PDT 24 Jul 05 04:29:47 PM PDT 24 4700141668 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.452047754 Jul 05 04:28:56 PM PDT 24 Jul 05 04:29:21 PM PDT 24 6123152444 ps
T391 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4195808611 Jul 05 04:29:02 PM PDT 24 Jul 05 04:30:13 PM PDT 24 7646622679 ps
T115 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3538074621 Jul 05 04:28:36 PM PDT 24 Jul 05 04:29:57 PM PDT 24 1166046217 ps
T392 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2570730818 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:43 PM PDT 24 1034864410 ps
T117 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2907013393 Jul 05 04:28:56 PM PDT 24 Jul 05 04:30:15 PM PDT 24 836538406 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.223566977 Jul 05 04:28:57 PM PDT 24 Jul 05 04:29:12 PM PDT 24 263758653 ps
T91 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1275118586 Jul 05 04:28:59 PM PDT 24 Jul 05 04:29:13 PM PDT 24 463186673 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1064900133 Jul 05 04:28:41 PM PDT 24 Jul 05 04:29:06 PM PDT 24 5897716152 ps
T394 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1594501341 Jul 05 04:28:52 PM PDT 24 Jul 05 04:29:18 PM PDT 24 8178635425 ps
T395 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2663665388 Jul 05 04:28:52 PM PDT 24 Jul 05 04:29:10 PM PDT 24 1970121100 ps
T93 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4060157715 Jul 05 04:28:50 PM PDT 24 Jul 05 04:29:59 PM PDT 24 17544517167 ps
T118 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.583160649 Jul 05 04:28:22 PM PDT 24 Jul 05 04:29:54 PM PDT 24 2460569911 ps
T396 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2129391273 Jul 05 04:28:40 PM PDT 24 Jul 05 04:28:59 PM PDT 24 708898885 ps
T397 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2384204262 Jul 05 04:28:46 PM PDT 24 Jul 05 04:29:00 PM PDT 24 347406332 ps
T398 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3729172213 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:17 PM PDT 24 7762182730 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3303535734 Jul 05 04:28:41 PM PDT 24 Jul 05 04:28:59 PM PDT 24 506485884 ps
T400 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.88966174 Jul 05 04:29:06 PM PDT 24 Jul 05 04:29:32 PM PDT 24 2762090404 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.886200581 Jul 05 04:28:47 PM PDT 24 Jul 05 04:29:11 PM PDT 24 3507598106 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.141893363 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:19 PM PDT 24 507804374 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1257546904 Jul 05 04:28:47 PM PDT 24 Jul 05 04:29:06 PM PDT 24 747368654 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1526191522 Jul 05 04:28:39 PM PDT 24 Jul 05 04:28:55 PM PDT 24 88083038 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4187111233 Jul 05 04:28:50 PM PDT 24 Jul 05 04:29:12 PM PDT 24 15418707575 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.590012812 Jul 05 04:28:42 PM PDT 24 Jul 05 04:29:09 PM PDT 24 9223595875 ps
T407 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2299475700 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:57 PM PDT 24 2254089195 ps
T408 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.820794112 Jul 05 04:28:55 PM PDT 24 Jul 05 04:29:22 PM PDT 24 1844636112 ps
T409 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.388962827 Jul 05 04:29:03 PM PDT 24 Jul 05 04:30:24 PM PDT 24 561826262 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4007119368 Jul 05 04:28:33 PM PDT 24 Jul 05 04:29:38 PM PDT 24 6376880684 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1382976663 Jul 05 04:28:33 PM PDT 24 Jul 05 04:29:01 PM PDT 24 8910608655 ps
T412 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1460040527 Jul 05 04:28:55 PM PDT 24 Jul 05 04:29:20 PM PDT 24 3092564283 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1823202465 Jul 05 04:28:43 PM PDT 24 Jul 05 04:28:59 PM PDT 24 221618273 ps
T114 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3109955209 Jul 05 04:28:54 PM PDT 24 Jul 05 04:30:21 PM PDT 24 1943370318 ps
T414 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1266631696 Jul 05 04:28:51 PM PDT 24 Jul 05 04:29:44 PM PDT 24 2791235382 ps
T415 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2538691262 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:35 PM PDT 24 365523075 ps
T416 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3500081018 Jul 05 04:28:34 PM PDT 24 Jul 05 04:28:55 PM PDT 24 221717800 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3550001252 Jul 05 04:28:48 PM PDT 24 Jul 05 04:29:04 PM PDT 24 387590033 ps
T418 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1279334816 Jul 05 04:28:38 PM PDT 24 Jul 05 04:28:59 PM PDT 24 906087540 ps
T419 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3037350341 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:19 PM PDT 24 6726740471 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.536201749 Jul 05 04:29:00 PM PDT 24 Jul 05 04:29:28 PM PDT 24 11796385921 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3374325243 Jul 05 04:28:41 PM PDT 24 Jul 05 04:29:08 PM PDT 24 8849548831 ps
T422 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.438342234 Jul 05 04:28:59 PM PDT 24 Jul 05 04:30:36 PM PDT 24 43283456220 ps
T423 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2155230633 Jul 05 04:28:59 PM PDT 24 Jul 05 04:29:13 PM PDT 24 555209742 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1301155653 Jul 05 04:33:22 PM PDT 24 Jul 05 04:33:44 PM PDT 24 1921220007 ps
T425 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3799042670 Jul 05 04:28:39 PM PDT 24 Jul 05 04:29:36 PM PDT 24 6987904868 ps
T426 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3013943962 Jul 05 04:28:50 PM PDT 24 Jul 05 04:29:13 PM PDT 24 5809693497 ps
T427 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2384601962 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:11 PM PDT 24 2306751934 ps
T113 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3096596650 Jul 05 04:28:41 PM PDT 24 Jul 05 04:30:03 PM PDT 24 2206818526 ps
T428 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3676755293 Jul 05 04:28:47 PM PDT 24 Jul 05 04:29:14 PM PDT 24 2096557637 ps
T429 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2934451897 Jul 05 04:28:49 PM PDT 24 Jul 05 04:29:17 PM PDT 24 1448099211 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3749430844 Jul 05 04:28:54 PM PDT 24 Jul 05 04:29:15 PM PDT 24 913745610 ps
T116 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.923400416 Jul 05 04:28:56 PM PDT 24 Jul 05 04:30:26 PM PDT 24 683887719 ps
T431 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1226942613 Jul 05 04:28:53 PM PDT 24 Jul 05 04:30:38 PM PDT 24 48331169513 ps
T92 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2991068204 Jul 05 04:28:30 PM PDT 24 Jul 05 04:28:57 PM PDT 24 4850219650 ps
T432 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.556094996 Jul 05 04:28:50 PM PDT 24 Jul 05 04:29:12 PM PDT 24 1787705446 ps
T433 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2773111671 Jul 05 04:28:45 PM PDT 24 Jul 05 04:29:53 PM PDT 24 7714315869 ps
T434 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2355392195 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:06 PM PDT 24 520588101 ps
T435 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3214240479 Jul 05 04:28:49 PM PDT 24 Jul 05 04:29:10 PM PDT 24 5861097484 ps
T436 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1181487062 Jul 05 04:28:56 PM PDT 24 Jul 05 04:30:02 PM PDT 24 27727232680 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4083462502 Jul 05 04:28:51 PM PDT 24 Jul 05 04:29:06 PM PDT 24 954787419 ps
T438 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2286487422 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:10 PM PDT 24 480241141 ps
T439 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2371707414 Jul 05 04:28:50 PM PDT 24 Jul 05 04:29:13 PM PDT 24 90146231 ps
T440 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1709562578 Jul 05 04:28:56 PM PDT 24 Jul 05 04:29:42 PM PDT 24 197786797 ps
T441 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.402219370 Jul 05 04:28:48 PM PDT 24 Jul 05 04:29:13 PM PDT 24 2025954851 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3586577516 Jul 05 04:28:51 PM PDT 24 Jul 05 04:30:17 PM PDT 24 9575252154 ps
T443 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1990190125 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:18 PM PDT 24 2156354395 ps
T444 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.746130549 Jul 05 04:29:05 PM PDT 24 Jul 05 04:29:23 PM PDT 24 488529054 ps
T120 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.90404754 Jul 05 04:29:05 PM PDT 24 Jul 05 04:30:28 PM PDT 24 2409281049 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3622135005 Jul 05 04:28:32 PM PDT 24 Jul 05 04:28:55 PM PDT 24 3759138517 ps
T446 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2361246485 Jul 05 04:28:46 PM PDT 24 Jul 05 04:29:05 PM PDT 24 817823017 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2214919698 Jul 05 04:29:00 PM PDT 24 Jul 05 04:29:23 PM PDT 24 6042571945 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1487512367 Jul 05 04:28:32 PM PDT 24 Jul 05 04:28:56 PM PDT 24 1240803257 ps
T449 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3849938631 Jul 05 04:29:04 PM PDT 24 Jul 05 04:29:18 PM PDT 24 195140461 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4105409206 Jul 05 04:28:57 PM PDT 24 Jul 05 04:30:19 PM PDT 24 1346787401 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3692932072 Jul 05 04:28:28 PM PDT 24 Jul 05 04:28:56 PM PDT 24 8056114308 ps
T122 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2122314698 Jul 05 04:28:56 PM PDT 24 Jul 05 04:30:23 PM PDT 24 1968052952 ps
T452 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.509112871 Jul 05 04:28:20 PM PDT 24 Jul 05 04:28:41 PM PDT 24 6539317889 ps
T453 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4290543110 Jul 05 04:28:50 PM PDT 24 Jul 05 04:29:15 PM PDT 24 5696882514 ps
T454 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.195136717 Jul 05 04:28:51 PM PDT 24 Jul 05 04:29:13 PM PDT 24 4638605609 ps
T455 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3933612402 Jul 05 04:28:52 PM PDT 24 Jul 05 04:29:10 PM PDT 24 2221039945 ps
T119 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2398674144 Jul 05 04:28:50 PM PDT 24 Jul 05 04:29:43 PM PDT 24 7300332121 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1209771646 Jul 05 04:28:58 PM PDT 24 Jul 05 04:29:17 PM PDT 24 2037826275 ps
T457 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1817276424 Jul 05 04:28:36 PM PDT 24 Jul 05 04:29:07 PM PDT 24 2634683629 ps
T458 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.599371497 Jul 05 04:28:56 PM PDT 24 Jul 05 04:29:13 PM PDT 24 10773029567 ps
T459 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4089958369 Jul 05 04:28:39 PM PDT 24 Jul 05 04:28:57 PM PDT 24 689617880 ps
T460 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1634433054 Jul 05 04:28:48 PM PDT 24 Jul 05 04:29:09 PM PDT 24 5113936669 ps
T461 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.765853601 Jul 05 04:28:36 PM PDT 24 Jul 05 04:28:52 PM PDT 24 85569894 ps
T462 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.461838177 Jul 05 04:28:47 PM PDT 24 Jul 05 04:30:03 PM PDT 24 32869440860 ps
T463 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2619664682 Jul 05 04:28:29 PM PDT 24 Jul 05 04:28:50 PM PDT 24 305775003 ps
T464 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.726263009 Jul 05 04:28:43 PM PDT 24 Jul 05 04:29:04 PM PDT 24 777027878 ps
T121 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1967494232 Jul 05 04:28:29 PM PDT 24 Jul 05 04:29:20 PM PDT 24 596663126 ps

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3759158423
Short name T2
Test name
Test status
Simulation time 27178590261 ps
CPU time 314.07 seconds
Started Jul 05 04:33:04 PM PDT 24
Finished Jul 05 04:38:21 PM PDT 24
Peak memory 237812 kb
Host smart-551861ee-d583-452f-a7ac-6eae3b403abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759158423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3759158423
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3989249358
Short name T21
Test name
Test status
Simulation time 131632558262 ps
CPU time 3004.08 seconds
Started Jul 05 04:33:01 PM PDT 24
Finished Jul 05 05:23:08 PM PDT 24
Peak memory 235748 kb
Host smart-7573fc3a-d263-4930-9d38-df88a3ff210e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989249358 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3989249358
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.24400085
Short name T108
Test name
Test status
Simulation time 309874606 ps
CPU time 15.93 seconds
Started Jul 05 04:32:39 PM PDT 24
Finished Jul 05 04:32:55 PM PDT 24
Peak memory 215304 kb
Host smart-4fed0c18-1b74-4170-ba59-00860c242479
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24400085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.rom_ctrl_stress_all.24400085
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3735050781
Short name T63
Test name
Test status
Simulation time 3561528865 ps
CPU time 70.77 seconds
Started Jul 05 04:28:32 PM PDT 24
Finished Jul 05 04:29:56 PM PDT 24
Peak memory 212216 kb
Host smart-c19275f7-cb4e-49ea-81e5-75233a91d748
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735050781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3735050781
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1642790198
Short name T12
Test name
Test status
Simulation time 13776892209 ps
CPU time 31.17 seconds
Started Jul 05 04:33:01 PM PDT 24
Finished Jul 05 04:33:34 PM PDT 24
Peak memory 213948 kb
Host smart-b0a5043e-aa4b-4e7f-97f9-ca03b078a51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642790198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1642790198
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2709651092
Short name T17
Test name
Test status
Simulation time 4603286389 ps
CPU time 109.76 seconds
Started Jul 05 04:32:22 PM PDT 24
Finished Jul 05 04:34:13 PM PDT 24
Peak memory 236960 kb
Host smart-b21b8c67-ca1a-4920-9fb7-8941788cac1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709651092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2709651092
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1631709610
Short name T75
Test name
Test status
Simulation time 1449688417 ps
CPU time 19.23 seconds
Started Jul 05 04:28:59 PM PDT 24
Finished Jul 05 04:29:27 PM PDT 24
Peak memory 210616 kb
Host smart-35ca807f-78f0-41af-850b-286a49f25f64
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631709610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1631709610
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.923400416
Short name T116
Test name
Test status
Simulation time 683887719 ps
CPU time 80.61 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:30:26 PM PDT 24
Peak memory 213340 kb
Host smart-e9aee73a-0b15-4610-8fcb-7f159ad2e41b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923400416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.923400416
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3000053344
Short name T45
Test name
Test status
Simulation time 42240691024 ps
CPU time 1637.17 seconds
Started Jul 05 04:32:30 PM PDT 24
Finished Jul 05 04:59:48 PM PDT 24
Peak memory 235864 kb
Host smart-8ba4d9aa-7bc4-4202-a022-bf7e45e12e31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000053344 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3000053344
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1485504739
Short name T30
Test name
Test status
Simulation time 7422488451 ps
CPU time 63.61 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:33:53 PM PDT 24
Peak memory 219356 kb
Host smart-b06e6103-5ab4-4636-ba33-fcf5fb2f3245
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485504739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1485504739
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.837790335
Short name T140
Test name
Test status
Simulation time 5438316899 ps
CPU time 12.11 seconds
Started Jul 05 04:32:31 PM PDT 24
Finished Jul 05 04:32:44 PM PDT 24
Peak memory 211312 kb
Host smart-247e5011-d2bf-4750-a654-48771999e891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837790335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.837790335
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3109955209
Short name T114
Test name
Test status
Simulation time 1943370318 ps
CPU time 78.3 seconds
Started Jul 05 04:28:54 PM PDT 24
Finished Jul 05 04:30:21 PM PDT 24
Peak memory 211916 kb
Host smart-a1e26978-f24e-4193-a159-f82cc38bf768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109955209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3109955209
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2168511361
Short name T37
Test name
Test status
Simulation time 35665056599 ps
CPU time 303.33 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:38:10 PM PDT 24
Peak memory 212668 kb
Host smart-951ef191-2b90-4ac6-853e-383c9ef69517
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168511361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2168511361
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2059254951
Short name T142
Test name
Test status
Simulation time 3293717699 ps
CPU time 19.68 seconds
Started Jul 05 04:33:03 PM PDT 24
Finished Jul 05 04:33:25 PM PDT 24
Peak memory 211908 kb
Host smart-d454f72f-1535-4f9c-a53b-0e10569103fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059254951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2059254951
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2629033883
Short name T216
Test name
Test status
Simulation time 168723752 ps
CPU time 9.52 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:33:03 PM PDT 24
Peak memory 211876 kb
Host smart-743760ef-1a67-4883-98d8-7cfdb44eccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629033883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2629033883
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.658904022
Short name T48
Test name
Test status
Simulation time 3644237557 ps
CPU time 30.74 seconds
Started Jul 05 04:32:51 PM PDT 24
Finished Jul 05 04:33:26 PM PDT 24
Peak memory 211820 kb
Host smart-0a7817c8-2402-4337-8d67-1b22fe663b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658904022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.658904022
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3366703655
Short name T89
Test name
Test status
Simulation time 15798470897 ps
CPU time 42.3 seconds
Started Jul 05 04:28:34 PM PDT 24
Finished Jul 05 04:29:28 PM PDT 24
Peak memory 211684 kb
Host smart-35f307a7-34ec-4d1a-9842-babe8501165c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366703655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3366703655
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2991300188
Short name T112
Test name
Test status
Simulation time 290505670 ps
CPU time 36.43 seconds
Started Jul 05 04:28:54 PM PDT 24
Finished Jul 05 04:29:39 PM PDT 24
Peak memory 218804 kb
Host smart-f75b34a7-9dac-4cd5-b549-aac722ec03c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991300188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2991300188
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2460050666
Short name T8
Test name
Test status
Simulation time 2297524857 ps
CPU time 16.08 seconds
Started Jul 05 04:32:22 PM PDT 24
Finished Jul 05 04:32:39 PM PDT 24
Peak memory 211364 kb
Host smart-3d5e7102-6fae-4416-96a7-33eae6415635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460050666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2460050666
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.419639293
Short name T97
Test name
Test status
Simulation time 1787366847 ps
CPU time 14.3 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:16 PM PDT 24
Peak memory 210672 kb
Host smart-8ac55e82-1be8-4132-a82f-e2b8e9f719b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419639293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.419639293
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3530556377
Short name T153
Test name
Test status
Simulation time 6470290011 ps
CPU time 19.98 seconds
Started Jul 05 04:32:37 PM PDT 24
Finished Jul 05 04:32:58 PM PDT 24
Peak memory 212788 kb
Host smart-2106e745-4ddd-47ac-af08-798c69efa7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530556377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3530556377
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.765853601
Short name T461
Test name
Test status
Simulation time 85569894 ps
CPU time 4.24 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:28:52 PM PDT 24
Peak memory 210580 kb
Host smart-cbbd9b18-f628-4fd9-81b3-27ad92f47912
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765853601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.765853601
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2559838715
Short name T372
Test name
Test status
Simulation time 2459298063 ps
CPU time 14.37 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:29:07 PM PDT 24
Peak memory 210664 kb
Host smart-1b7fe129-12d5-4fb5-9cfa-acfe078d2a36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559838715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2559838715
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2991068204
Short name T92
Test name
Test status
Simulation time 4850219650 ps
CPU time 14.38 seconds
Started Jul 05 04:28:30 PM PDT 24
Finished Jul 05 04:28:57 PM PDT 24
Peak memory 218792 kb
Host smart-e058d049-f005-4f07-beef-2c81ea3c1ce9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991068204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2991068204
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3692932072
Short name T451
Test name
Test status
Simulation time 8056114308 ps
CPU time 15.62 seconds
Started Jul 05 04:28:28 PM PDT 24
Finished Jul 05 04:28:56 PM PDT 24
Peak memory 218976 kb
Host smart-cde38bef-aae6-4f46-9112-66d5a823e701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692932072 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3692932072
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1382976663
Short name T411
Test name
Test status
Simulation time 8910608655 ps
CPU time 16.43 seconds
Started Jul 05 04:28:33 PM PDT 24
Finished Jul 05 04:29:01 PM PDT 24
Peak memory 218760 kb
Host smart-7763a207-1df8-4b92-b8ad-08af90fd4bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382976663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1382976663
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3622135005
Short name T445
Test name
Test status
Simulation time 3759138517 ps
CPU time 10.12 seconds
Started Jul 05 04:28:32 PM PDT 24
Finished Jul 05 04:28:55 PM PDT 24
Peak memory 210480 kb
Host smart-899b3bcf-1f35-49ad-a7d2-7f9d4b2531d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622135005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3622135005
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.509112871
Short name T452
Test name
Test status
Simulation time 6539317889 ps
CPU time 7.91 seconds
Started Jul 05 04:28:20 PM PDT 24
Finished Jul 05 04:28:41 PM PDT 24
Peak memory 210512 kb
Host smart-eeaa84c8-ce6b-4a4e-98ec-5935c00915a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509112871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
509112871
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.88966174
Short name T400
Test name
Test status
Simulation time 2762090404 ps
CPU time 16.59 seconds
Started Jul 05 04:29:06 PM PDT 24
Finished Jul 05 04:29:32 PM PDT 24
Peak memory 210724 kb
Host smart-35b83844-25a8-460a-8008-b6f51f2f1ffe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88966174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_same_csr_outstanding.88966174
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3676755293
Short name T428
Test name
Test status
Simulation time 2096557637 ps
CPU time 17.82 seconds
Started Jul 05 04:28:47 PM PDT 24
Finished Jul 05 04:29:14 PM PDT 24
Peak memory 218768 kb
Host smart-3a3d3a2c-30cd-4bae-b161-6eba3957042e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676755293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3676755293
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1967494232
Short name T121
Test name
Test status
Simulation time 596663126 ps
CPU time 38.52 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:29:20 PM PDT 24
Peak memory 218784 kb
Host smart-beca2f25-c98b-43db-aa7e-92db621c00cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967494232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1967494232
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2438836872
Short name T383
Test name
Test status
Simulation time 1083605884 ps
CPU time 10.36 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:29:16 PM PDT 24
Peak memory 210604 kb
Host smart-34754e3d-16ec-4dae-8f5f-c0e1e2a935da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438836872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2438836872
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4089958369
Short name T459
Test name
Test status
Simulation time 689617880 ps
CPU time 6.56 seconds
Started Jul 05 04:28:39 PM PDT 24
Finished Jul 05 04:28:57 PM PDT 24
Peak memory 210596 kb
Host smart-5b193606-4dbe-4064-a13c-0f2c62be1c91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089958369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4089958369
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2619664682
Short name T463
Test name
Test status
Simulation time 305775003 ps
CPU time 7.32 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:28:50 PM PDT 24
Peak memory 218744 kb
Host smart-dc15ce3b-c3d2-464e-8bdc-cd492a5b7fd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619664682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2619664682
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3024402083
Short name T364
Test name
Test status
Simulation time 5267493134 ps
CPU time 12.28 seconds
Started Jul 05 04:28:26 PM PDT 24
Finished Jul 05 04:28:51 PM PDT 24
Peak memory 218904 kb
Host smart-81c4fe51-b68e-458f-a65a-6431f3e4968b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024402083 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3024402083
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3810881458
Short name T86
Test name
Test status
Simulation time 1538000160 ps
CPU time 8.98 seconds
Started Jul 05 04:28:31 PM PDT 24
Finished Jul 05 04:28:53 PM PDT 24
Peak memory 210600 kb
Host smart-a4cf344e-b934-44c0-a37a-813bda02f318
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810881458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3810881458
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1279334816
Short name T418
Test name
Test status
Simulation time 906087540 ps
CPU time 9.64 seconds
Started Jul 05 04:28:38 PM PDT 24
Finished Jul 05 04:28:59 PM PDT 24
Peak memory 210416 kb
Host smart-c7dde216-c0ac-44ab-9523-4519a5c385a5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279334816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1279334816
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1301155653
Short name T424
Test name
Test status
Simulation time 1921220007 ps
CPU time 15.89 seconds
Started Jul 05 04:33:22 PM PDT 24
Finished Jul 05 04:33:44 PM PDT 24
Peak memory 210568 kb
Host smart-ed1f5eea-ddce-459a-b06a-8b9b444c4213
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301155653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1301155653
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4007119368
Short name T410
Test name
Test status
Simulation time 6376880684 ps
CPU time 52.99 seconds
Started Jul 05 04:28:33 PM PDT 24
Finished Jul 05 04:29:38 PM PDT 24
Peak memory 210688 kb
Host smart-db9aadfe-1729-47a7-a00c-6bda058821fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007119368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4007119368
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4187111233
Short name T405
Test name
Test status
Simulation time 15418707575 ps
CPU time 13.8 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:12 PM PDT 24
Peak memory 218868 kb
Host smart-7657e97e-9d4c-436d-b48d-34a30fe3dc9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187111233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4187111233
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.590012812
Short name T406
Test name
Test status
Simulation time 9223595875 ps
CPU time 15.23 seconds
Started Jul 05 04:28:42 PM PDT 24
Finished Jul 05 04:29:09 PM PDT 24
Peak memory 218872 kb
Host smart-b19ad515-7886-41a2-8e5c-6c6dfe17ec51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590012812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.590012812
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1266631696
Short name T414
Test name
Test status
Simulation time 2791235382 ps
CPU time 43.42 seconds
Started Jul 05 04:28:51 PM PDT 24
Finished Jul 05 04:29:44 PM PDT 24
Peak memory 212040 kb
Host smart-cb06318f-64c1-4b36-9ca0-291a2a229090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266631696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1266631696
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1623877110
Short name T365
Test name
Test status
Simulation time 1303652796 ps
CPU time 11.89 seconds
Started Jul 05 04:28:55 PM PDT 24
Finished Jul 05 04:29:16 PM PDT 24
Peak memory 218916 kb
Host smart-a2b9dc6c-ff10-4f49-bb18-b02b976de1d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623877110 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1623877110
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.556094996
Short name T432
Test name
Test status
Simulation time 1787705446 ps
CPU time 12.8 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:12 PM PDT 24
Peak memory 210460 kb
Host smart-87b24ed4-4bc5-48a0-b984-c6b155e08fb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556094996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.556094996
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3799042670
Short name T425
Test name
Test status
Simulation time 6987904868 ps
CPU time 45.17 seconds
Started Jul 05 04:28:39 PM PDT 24
Finished Jul 05 04:29:36 PM PDT 24
Peak memory 210636 kb
Host smart-fae3cb38-511f-410a-bdd9-3e68706d7873
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799042670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3799042670
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.564397842
Short name T378
Test name
Test status
Simulation time 564265345 ps
CPU time 11.6 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 218808 kb
Host smart-9bee9484-2562-4ee0-9a9d-c9bbf46743b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564397842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.564397842
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3538074621
Short name T115
Test name
Test status
Simulation time 1166046217 ps
CPU time 69.38 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:29:57 PM PDT 24
Peak memory 212184 kb
Host smart-e4e5e350-df53-4f88-9675-9832ad8ee21e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538074621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3538074621
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2129391273
Short name T396
Test name
Test status
Simulation time 708898885 ps
CPU time 7.03 seconds
Started Jul 05 04:28:40 PM PDT 24
Finished Jul 05 04:28:59 PM PDT 24
Peak memory 218908 kb
Host smart-28fdaf6f-1840-4caf-8862-ff2b89602bbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129391273 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2129391273
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2355392195
Short name T434
Test name
Test status
Simulation time 520588101 ps
CPU time 4.21 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 210592 kb
Host smart-febf9fbf-fc3f-411a-bc90-cc12a18dc847
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355392195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2355392195
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1181487062
Short name T436
Test name
Test status
Simulation time 27727232680 ps
CPU time 56.05 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:30:02 PM PDT 24
Peak memory 210628 kb
Host smart-92f17f53-7990-4732-b7a3-bffbd36a460a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181487062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1181487062
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2155230633
Short name T423
Test name
Test status
Simulation time 555209742 ps
CPU time 4.17 seconds
Started Jul 05 04:28:59 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 210644 kb
Host smart-f278d61c-c614-42ed-9338-b31e4098ea2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155230633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2155230633
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.459027009
Short name T380
Test name
Test status
Simulation time 37914847073 ps
CPU time 17.91 seconds
Started Jul 05 04:28:37 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 218916 kb
Host smart-0a051c9c-5b2a-470d-912e-626678517ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459027009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.459027009
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4141294751
Short name T388
Test name
Test status
Simulation time 2145784567 ps
CPU time 16.64 seconds
Started Jul 05 04:29:05 PM PDT 24
Finished Jul 05 04:29:30 PM PDT 24
Peak memory 218808 kb
Host smart-59c8d495-a55c-4710-8a97-eeec1a243e2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141294751 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4141294751
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3835266490
Short name T381
Test name
Test status
Simulation time 347846804 ps
CPU time 4.23 seconds
Started Jul 05 04:28:45 PM PDT 24
Finished Jul 05 04:28:59 PM PDT 24
Peak memory 210584 kb
Host smart-96699fbd-a411-4f19-a7c5-bcbf29a7809e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835266490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3835266490
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4195808611
Short name T391
Test name
Test status
Simulation time 7646622679 ps
CPU time 62.1 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:30:13 PM PDT 24
Peak memory 210636 kb
Host smart-263c6a82-92b0-4b8b-ba56-b3eeb89c91b3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195808611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4195808611
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.824155579
Short name T99
Test name
Test status
Simulation time 3276810910 ps
CPU time 9.2 seconds
Started Jul 05 04:28:57 PM PDT 24
Finished Jul 05 04:29:16 PM PDT 24
Peak memory 210740 kb
Host smart-0a015077-9e9d-4615-a218-09b6105082ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824155579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.824155579
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.833718389
Short name T387
Test name
Test status
Simulation time 171751292 ps
CPU time 7.31 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 218832 kb
Host smart-0bff3b1f-6db4-43a2-a2b8-2c64523822ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833718389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.833718389
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2358111057
Short name T111
Test name
Test status
Simulation time 1220519424 ps
CPU time 42.58 seconds
Started Jul 05 04:29:00 PM PDT 24
Finished Jul 05 04:29:56 PM PDT 24
Peak memory 218808 kb
Host smart-5277b8e8-2b66-49ea-950e-1ff75e0146e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358111057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2358111057
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.195136717
Short name T454
Test name
Test status
Simulation time 4638605609 ps
CPU time 12.77 seconds
Started Jul 05 04:28:51 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 218892 kb
Host smart-f7c39e60-e5a1-4a30-a535-ebf19a92c557
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195136717 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.195136717
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.599371497
Short name T458
Test name
Test status
Simulation time 10773029567 ps
CPU time 7.79 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 210664 kb
Host smart-22eb5609-d576-4514-b9be-e2972b1ea5c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599371497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.599371497
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2934451897
Short name T429
Test name
Test status
Simulation time 1448099211 ps
CPU time 18.61 seconds
Started Jul 05 04:28:49 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 210596 kb
Host smart-a7e79268-e789-48df-a527-f259df649425
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934451897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2934451897
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.130634401
Short name T78
Test name
Test status
Simulation time 977775131 ps
CPU time 11.59 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:14 PM PDT 24
Peak memory 218816 kb
Host smart-188672ef-139d-472a-b749-cd2ad920010f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130634401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.130634401
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.752162223
Short name T379
Test name
Test status
Simulation time 3939648312 ps
CPU time 17.93 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 218916 kb
Host smart-a1a670a8-8612-4b07-963f-e2b6ee5deb1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752162223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.752162223
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2663665388
Short name T395
Test name
Test status
Simulation time 1970121100 ps
CPU time 8.85 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:10 PM PDT 24
Peak memory 218844 kb
Host smart-66b6f44a-9be1-41ec-aa5f-5f92541feb8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663665388 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2663665388
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1553879848
Short name T106
Test name
Test status
Simulation time 91108460 ps
CPU time 4.3 seconds
Started Jul 05 04:28:59 PM PDT 24
Finished Jul 05 04:29:12 PM PDT 24
Peak memory 210504 kb
Host smart-1029fa2d-e70e-4580-a67b-915533853a7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553879848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1553879848
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2570730818
Short name T392
Test name
Test status
Simulation time 1034864410 ps
CPU time 26.94 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:43 PM PDT 24
Peak memory 210584 kb
Host smart-eebfa06d-826f-466d-b9da-f4673c203dd5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570730818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2570730818
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2384601962
Short name T427
Test name
Test status
Simulation time 2306751934 ps
CPU time 8.01 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 210720 kb
Host smart-50b4e014-b0f3-4c4a-847b-df66dc7e593b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384601962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2384601962
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.726263009
Short name T464
Test name
Test status
Simulation time 777027878 ps
CPU time 10.12 seconds
Started Jul 05 04:28:43 PM PDT 24
Finished Jul 05 04:29:04 PM PDT 24
Peak memory 218856 kb
Host smart-d18b0cea-22ba-4be2-ade4-502d739c5e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726263009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.726263009
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2299475700
Short name T407
Test name
Test status
Simulation time 2254089195 ps
CPU time 46.36 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:57 PM PDT 24
Peak memory 210756 kb
Host smart-b8f7994a-e82c-46ec-92da-b67748e6d1d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299475700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2299475700
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3769794434
Short name T370
Test name
Test status
Simulation time 381027596 ps
CPU time 5.33 seconds
Started Jul 05 04:29:05 PM PDT 24
Finished Jul 05 04:29:19 PM PDT 24
Peak memory 218916 kb
Host smart-c2702ed5-9c9e-4b1e-8c9b-ce6da378307c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769794434 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3769794434
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2286487422
Short name T438
Test name
Test status
Simulation time 480241141 ps
CPU time 7.3 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:10 PM PDT 24
Peak memory 217408 kb
Host smart-6afe67e6-9e87-428f-a73f-55db450488dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286487422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2286487422
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2538691262
Short name T415
Test name
Test status
Simulation time 365523075 ps
CPU time 18.66 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:35 PM PDT 24
Peak memory 210596 kb
Host smart-d7d3bbaf-d00e-4d04-9bb6-19a2a56f7ff5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538691262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2538691262
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2214919698
Short name T447
Test name
Test status
Simulation time 6042571945 ps
CPU time 13.24 seconds
Started Jul 05 04:29:00 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 210860 kb
Host smart-d926a04a-dd20-4a26-a5a2-8e3740e042aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214919698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2214919698
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4290543110
Short name T453
Test name
Test status
Simulation time 5696882514 ps
CPU time 15.36 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:15 PM PDT 24
Peak memory 218924 kb
Host smart-0388f52d-fce7-4b90-847f-96f4fa3b6772
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290543110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4290543110
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.90404754
Short name T120
Test name
Test status
Simulation time 2409281049 ps
CPU time 74.42 seconds
Started Jul 05 04:29:05 PM PDT 24
Finished Jul 05 04:30:28 PM PDT 24
Peak memory 218872 kb
Host smart-f426953c-8c71-4e38-a471-3a15fae751d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90404754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_int
g_err.90404754
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1990190125
Short name T443
Test name
Test status
Simulation time 2156354395 ps
CPU time 15.91 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 218840 kb
Host smart-c1226553-79f6-4994-930a-6b87a0a57da9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990190125 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1990190125
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2924623243
Short name T104
Test name
Test status
Simulation time 8027461263 ps
CPU time 16.13 seconds
Started Jul 05 04:28:57 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 218780 kb
Host smart-c9cf47fd-84cd-4f7c-ab35-b512c87a4a96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924623243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2924623243
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1927530012
Short name T66
Test name
Test status
Simulation time 2914386596 ps
CPU time 32.38 seconds
Started Jul 05 04:29:03 PM PDT 24
Finished Jul 05 04:29:45 PM PDT 24
Peak memory 210652 kb
Host smart-7d647f2d-6986-4ec5-b29d-2b70ea206b75
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927530012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1927530012
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1209771646
Short name T456
Test name
Test status
Simulation time 2037826275 ps
CPU time 8.97 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 217944 kb
Host smart-66d1f371-8e27-4589-bffd-00df2192f14f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209771646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1209771646
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2371707414
Short name T439
Test name
Test status
Simulation time 90146231 ps
CPU time 8.14 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 218804 kb
Host smart-ce83c305-e8fd-41de-bd72-6e414e462cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371707414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2371707414
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3849938631
Short name T449
Test name
Test status
Simulation time 195140461 ps
CPU time 5.46 seconds
Started Jul 05 04:29:04 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 218936 kb
Host smart-b1ea60ad-e1da-433d-abbd-661fcb62a65c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849938631 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3849938631
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1275118586
Short name T91
Test name
Test status
Simulation time 463186673 ps
CPU time 4.29 seconds
Started Jul 05 04:28:59 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 218044 kb
Host smart-a2051ee3-d49f-468a-904b-39511984ebc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275118586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1275118586
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2773111671
Short name T433
Test name
Test status
Simulation time 7714315869 ps
CPU time 57.54 seconds
Started Jul 05 04:28:45 PM PDT 24
Finished Jul 05 04:29:53 PM PDT 24
Peak memory 210632 kb
Host smart-a8965c57-eb89-49f3-b8bc-a7f7aa3781f1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773111671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2773111671
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3037350341
Short name T419
Test name
Test status
Simulation time 6726740471 ps
CPU time 17.21 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:19 PM PDT 24
Peak memory 218880 kb
Host smart-b97631a6-1970-49e9-bbe1-fe2b1eb394b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037350341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3037350341
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.746130549
Short name T444
Test name
Test status
Simulation time 488529054 ps
CPU time 8.9 seconds
Started Jul 05 04:29:05 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 218848 kb
Host smart-be46cffb-01b5-4b63-9788-0d95e078f16d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746130549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.746130549
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2122314698
Short name T122
Test name
Test status
Simulation time 1968052952 ps
CPU time 77.55 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:30:23 PM PDT 24
Peak memory 218804 kb
Host smart-b950af46-4174-4a91-8645-1de3921667f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122314698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2122314698
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3557928578
Short name T367
Test name
Test status
Simulation time 380756728 ps
CPU time 4.8 seconds
Started Jul 05 04:29:03 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 218868 kb
Host smart-a4d0a017-ff79-436a-a560-7a5ab7726b2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557928578 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3557928578
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3729172213
Short name T398
Test name
Test status
Simulation time 7762182730 ps
CPU time 14.44 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 218664 kb
Host smart-0931c0c1-3301-4345-ac4d-fd0351a46199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729172213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3729172213
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4130242531
Short name T389
Test name
Test status
Simulation time 4700141668 ps
CPU time 42.95 seconds
Started Jul 05 04:28:55 PM PDT 24
Finished Jul 05 04:29:47 PM PDT 24
Peak memory 210636 kb
Host smart-98dfaa6f-ed51-42c8-bded-fccd1daa16ca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130242531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4130242531
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2101389490
Short name T80
Test name
Test status
Simulation time 2061804374 ps
CPU time 17.28 seconds
Started Jul 05 04:28:57 PM PDT 24
Finished Jul 05 04:29:24 PM PDT 24
Peak memory 210728 kb
Host smart-3d95609e-86cf-4eee-bfc3-d1a139022aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101389490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2101389490
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.536201749
Short name T420
Test name
Test status
Simulation time 11796385921 ps
CPU time 17.64 seconds
Started Jul 05 04:29:00 PM PDT 24
Finished Jul 05 04:29:28 PM PDT 24
Peak memory 218916 kb
Host smart-8a45c06d-97c9-4d64-bf4d-aea252debe23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536201749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.536201749
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4105409206
Short name T450
Test name
Test status
Simulation time 1346787401 ps
CPU time 73.12 seconds
Started Jul 05 04:28:57 PM PDT 24
Finished Jul 05 04:30:19 PM PDT 24
Peak memory 211020 kb
Host smart-91fe27d0-dcc7-422c-924c-3ec12f80d337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105409206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.4105409206
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.757572958
Short name T67
Test name
Test status
Simulation time 705772992 ps
CPU time 7.21 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:29:12 PM PDT 24
Peak memory 218816 kb
Host smart-c9ae2258-3b46-4636-8062-60d9277fd7f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757572958 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.757572958
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1891788267
Short name T72
Test name
Test status
Simulation time 7459458445 ps
CPU time 12.05 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:12 PM PDT 24
Peak memory 210604 kb
Host smart-6565e18f-8cef-4db0-802e-d8c65c16fea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891788267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1891788267
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.438342234
Short name T422
Test name
Test status
Simulation time 43283456220 ps
CPU time 87.87 seconds
Started Jul 05 04:28:59 PM PDT 24
Finished Jul 05 04:30:36 PM PDT 24
Peak memory 210632 kb
Host smart-456dab6d-2292-4cb5-a71c-01b03d4307a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438342234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.438342234
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1337024564
Short name T77
Test name
Test status
Simulation time 9283078523 ps
CPU time 14.72 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:14 PM PDT 24
Peak memory 218856 kb
Host smart-6a61df46-6d0f-418d-90af-360e92888f4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337024564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1337024564
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1460040527
Short name T412
Test name
Test status
Simulation time 3092564283 ps
CPU time 14.77 seconds
Started Jul 05 04:28:55 PM PDT 24
Finished Jul 05 04:29:20 PM PDT 24
Peak memory 218860 kb
Host smart-b6e2f920-b9b0-4941-b647-6131193adb96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460040527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1460040527
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.388962827
Short name T409
Test name
Test status
Simulation time 561826262 ps
CPU time 71.21 seconds
Started Jul 05 04:29:03 PM PDT 24
Finished Jul 05 04:30:24 PM PDT 24
Peak memory 218808 kb
Host smart-17417944-e44d-4596-9e72-374a09c0c63a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388962827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.388962827
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.316965259
Short name T79
Test name
Test status
Simulation time 6558889750 ps
CPU time 14.02 seconds
Started Jul 05 04:28:38 PM PDT 24
Finished Jul 05 04:29:04 PM PDT 24
Peak memory 218660 kb
Host smart-eabbd9d8-30a9-4b30-ac5f-5f2b6db07f5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316965259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.316965259
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4083462502
Short name T437
Test name
Test status
Simulation time 954787419 ps
CPU time 6.25 seconds
Started Jul 05 04:28:51 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 210588 kb
Host smart-3350be56-855b-4451-8749-dc6c1cded7bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083462502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4083462502
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1817276424
Short name T457
Test name
Test status
Simulation time 2634683629 ps
CPU time 11.23 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:29:07 PM PDT 24
Peak memory 217556 kb
Host smart-3ed01063-f150-4515-91ed-d77afa033063
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817276424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1817276424
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2593961667
Short name T68
Test name
Test status
Simulation time 1577450228 ps
CPU time 13.49 seconds
Started Jul 05 04:28:33 PM PDT 24
Finished Jul 05 04:28:59 PM PDT 24
Peak memory 218876 kb
Host smart-6df94b5f-5de5-450d-bd68-8468e1ef75fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593961667 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2593961667
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3374325243
Short name T421
Test name
Test status
Simulation time 8849548831 ps
CPU time 16.11 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:29:08 PM PDT 24
Peak memory 218760 kb
Host smart-44d4bef7-7784-4e67-bfaf-e556e2fe3db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374325243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3374325243
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2504545432
Short name T376
Test name
Test status
Simulation time 3229051781 ps
CPU time 8.92 seconds
Started Jul 05 04:28:30 PM PDT 24
Finished Jul 05 04:28:52 PM PDT 24
Peak memory 210464 kb
Host smart-799701f5-19d9-44e3-94dd-4a2a003ca15d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504545432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2504545432
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3002731316
Short name T363
Test name
Test status
Simulation time 464193620 ps
CPU time 7.07 seconds
Started Jul 05 04:28:48 PM PDT 24
Finished Jul 05 04:29:04 PM PDT 24
Peak memory 210444 kb
Host smart-5111244b-e879-4643-8b26-35d28185ea8b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002731316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3002731316
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1466228904
Short name T377
Test name
Test status
Simulation time 33524586350 ps
CPU time 79.71 seconds
Started Jul 05 04:28:51 PM PDT 24
Finished Jul 05 04:30:20 PM PDT 24
Peak memory 210640 kb
Host smart-ab900ab8-d180-46a7-8b62-9229d89f4dc7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466228904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1466228904
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3013943962
Short name T426
Test name
Test status
Simulation time 5809693497 ps
CPU time 14.36 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 210736 kb
Host smart-2e7fb56d-0091-4e1c-ae46-de87ea414ea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013943962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3013943962
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2822592605
Short name T366
Test name
Test status
Simulation time 2780488688 ps
CPU time 21.04 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:29:09 PM PDT 24
Peak memory 218912 kb
Host smart-48ed14c2-3598-4f53-b852-26b883109b9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822592605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2822592605
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.583160649
Short name T118
Test name
Test status
Simulation time 2460569911 ps
CPU time 79.53 seconds
Started Jul 05 04:28:22 PM PDT 24
Finished Jul 05 04:29:54 PM PDT 24
Peak memory 218896 kb
Host smart-bd652288-3726-4f26-a5e5-5e98a1ab6224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583160649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.583160649
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.317995206
Short name T373
Test name
Test status
Simulation time 2823698244 ps
CPU time 11.56 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:28:59 PM PDT 24
Peak memory 218760 kb
Host smart-58a9074e-a6c9-47d5-8d5c-2a028c79420e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317995206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.317995206
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1487512367
Short name T448
Test name
Test status
Simulation time 1240803257 ps
CPU time 11.6 seconds
Started Jul 05 04:28:32 PM PDT 24
Finished Jul 05 04:28:56 PM PDT 24
Peak memory 210604 kb
Host smart-c5a4ac4d-0f43-4c5d-ad78-4dd278bc2920
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487512367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1487512367
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2761889629
Short name T386
Test name
Test status
Simulation time 1246412346 ps
CPU time 13.78 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:29:02 PM PDT 24
Peak memory 210572 kb
Host smart-48554abd-7a99-4fba-b25b-5bd7a474232d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761889629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2761889629
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1823202465
Short name T413
Test name
Test status
Simulation time 221618273 ps
CPU time 5.37 seconds
Started Jul 05 04:28:43 PM PDT 24
Finished Jul 05 04:28:59 PM PDT 24
Peak memory 218912 kb
Host smart-ba14b928-0af3-46d6-af29-9e6321366748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823202465 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1823202465
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2771449755
Short name T107
Test name
Test status
Simulation time 6246428554 ps
CPU time 6.91 seconds
Started Jul 05 04:28:36 PM PDT 24
Finished Jul 05 04:28:55 PM PDT 24
Peak memory 210668 kb
Host smart-66372199-6bee-4409-885e-686704ea8b6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771449755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2771449755
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1526191522
Short name T404
Test name
Test status
Simulation time 88083038 ps
CPU time 4.22 seconds
Started Jul 05 04:28:39 PM PDT 24
Finished Jul 05 04:28:55 PM PDT 24
Peak memory 210408 kb
Host smart-9ce3bead-c08e-4323-a434-3d3fbeee3b62
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526191522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1526191522
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1647056228
Short name T368
Test name
Test status
Simulation time 2614631919 ps
CPU time 11.7 seconds
Started Jul 05 04:28:46 PM PDT 24
Finished Jul 05 04:29:08 PM PDT 24
Peak memory 210508 kb
Host smart-2a3c891d-5b5d-4661-bc27-f36b19cd7134
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647056228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1647056228
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.359600645
Short name T100
Test name
Test status
Simulation time 95800213 ps
CPU time 4.12 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 218144 kb
Host smart-f71f04a9-9c98-4fb5-8df2-24bbd184dc4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359600645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.359600645
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.452047754
Short name T390
Test name
Test status
Simulation time 6123152444 ps
CPU time 15.88 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:29:21 PM PDT 24
Peak memory 218916 kb
Host smart-eb214355-ed40-421c-bd8e-ea922c010c39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452047754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.452047754
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3038908706
Short name T65
Test name
Test status
Simulation time 21618684242 ps
CPU time 47.55 seconds
Started Jul 05 04:28:45 PM PDT 24
Finished Jul 05 04:29:43 PM PDT 24
Peak memory 218868 kb
Host smart-3532a0f3-d123-4a90-ac40-3a196296729b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038908706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3038908706
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.223566977
Short name T90
Test name
Test status
Simulation time 263758653 ps
CPU time 5.89 seconds
Started Jul 05 04:28:57 PM PDT 24
Finished Jul 05 04:29:12 PM PDT 24
Peak memory 217656 kb
Host smart-3762577e-053d-4dbb-9d14-11cc48d73c4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223566977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.223566977
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.886200581
Short name T401
Test name
Test status
Simulation time 3507598106 ps
CPU time 14.32 seconds
Started Jul 05 04:28:47 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 210624 kb
Host smart-04adcb6b-d649-43b4-9feb-10456643ab61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886200581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.886200581
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3749430844
Short name T430
Test name
Test status
Simulation time 913745610 ps
CPU time 12.8 seconds
Started Jul 05 04:28:54 PM PDT 24
Finished Jul 05 04:29:15 PM PDT 24
Peak memory 210536 kb
Host smart-9a27f352-c46b-4a94-b7eb-f6b32a445395
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749430844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3749430844
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3214240479
Short name T435
Test name
Test status
Simulation time 5861097484 ps
CPU time 11.62 seconds
Started Jul 05 04:28:49 PM PDT 24
Finished Jul 05 04:29:10 PM PDT 24
Peak memory 218972 kb
Host smart-82b0fcde-87ad-453a-93c3-e50ecd130b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214240479 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3214240479
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1673542990
Short name T76
Test name
Test status
Simulation time 3954784965 ps
CPU time 15.02 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 210660 kb
Host smart-6f632529-79b0-4f1d-adc1-b8348e08f502
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673542990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1673542990
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1064900133
Short name T393
Test name
Test status
Simulation time 5897716152 ps
CPU time 13.28 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 210528 kb
Host smart-91d219a2-7c67-4e01-b2d4-f553223c927e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064900133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1064900133
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3814822408
Short name T374
Test name
Test status
Simulation time 696391108 ps
CPU time 8.84 seconds
Started Jul 05 04:28:48 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 210444 kb
Host smart-15819419-54c7-4782-a730-7dd6e98dccdb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814822408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3814822408
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3586577516
Short name T442
Test name
Test status
Simulation time 9575252154 ps
CPU time 76.79 seconds
Started Jul 05 04:28:51 PM PDT 24
Finished Jul 05 04:30:17 PM PDT 24
Peak memory 210612 kb
Host smart-01cc8912-1481-4f99-b0bb-43b242b89d22
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586577516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3586577516
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3550001252
Short name T417
Test name
Test status
Simulation time 387590033 ps
CPU time 6.39 seconds
Started Jul 05 04:28:48 PM PDT 24
Finished Jul 05 04:29:04 PM PDT 24
Peak memory 218104 kb
Host smart-1f767098-7add-4ba4-b3e3-b335b4ab74a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550001252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3550001252
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.469694536
Short name T384
Test name
Test status
Simulation time 992857760 ps
CPU time 10.92 seconds
Started Jul 05 04:28:51 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 218836 kb
Host smart-485e6918-fc2a-4108-8637-5b11d6da3393
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469694536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.469694536
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.974518495
Short name T64
Test name
Test status
Simulation time 278408589 ps
CPU time 39.38 seconds
Started Jul 05 04:28:55 PM PDT 24
Finished Jul 05 04:29:44 PM PDT 24
Peak memory 213120 kb
Host smart-b18c7956-ee7d-43bf-b824-615f0c0b50cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974518495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.974518495
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1257546904
Short name T403
Test name
Test status
Simulation time 747368654 ps
CPU time 9.21 seconds
Started Jul 05 04:28:47 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 219324 kb
Host smart-1e25520c-e664-4870-805e-5e272b2ab4b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257546904 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1257546904
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1767120704
Short name T87
Test name
Test status
Simulation time 3518904525 ps
CPU time 14.45 seconds
Started Jul 05 04:28:49 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 210668 kb
Host smart-bad9cbcf-e0f2-4055-8a81-626f618ab2a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767120704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1767120704
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.537409877
Short name T88
Test name
Test status
Simulation time 22640538577 ps
CPU time 91.55 seconds
Started Jul 05 04:28:45 PM PDT 24
Finished Jul 05 04:30:27 PM PDT 24
Peak memory 211700 kb
Host smart-4e891261-b81e-4d39-860e-bb4fc2bb9c95
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537409877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.537409877
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3429785116
Short name T73
Test name
Test status
Simulation time 1172272747 ps
CPU time 10.8 seconds
Started Jul 05 04:28:45 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 218768 kb
Host smart-ff84e140-18e6-47f6-8a72-250049c00a2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429785116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3429785116
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3500081018
Short name T416
Test name
Test status
Simulation time 221717800 ps
CPU time 7.91 seconds
Started Jul 05 04:28:34 PM PDT 24
Finished Jul 05 04:28:55 PM PDT 24
Peak memory 218852 kb
Host smart-3edf3f60-126b-478e-9503-0c9ef75daee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500081018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3500081018
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3096596650
Short name T113
Test name
Test status
Simulation time 2206818526 ps
CPU time 70.35 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:30:03 PM PDT 24
Peak memory 211124 kb
Host smart-750ba9aa-148b-4a12-9323-5ec747c84a70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096596650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3096596650
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1594501341
Short name T394
Test name
Test status
Simulation time 8178635425 ps
CPU time 16.02 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 218968 kb
Host smart-680fb717-8dea-4c8b-8d28-804cb50ca8a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594501341 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1594501341
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3924952493
Short name T105
Test name
Test status
Simulation time 3843390563 ps
CPU time 15.8 seconds
Started Jul 05 04:28:57 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 210604 kb
Host smart-85c611cd-5cd9-4135-b345-5023052ddd08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924952493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3924952493
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.168515587
Short name T74
Test name
Test status
Simulation time 39480592222 ps
CPU time 88.14 seconds
Started Jul 05 04:28:47 PM PDT 24
Finished Jul 05 04:30:25 PM PDT 24
Peak memory 210688 kb
Host smart-1e92b7f5-3058-4378-b63a-4a580506b582
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168515587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.168515587
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.141893363
Short name T402
Test name
Test status
Simulation time 507804374 ps
CPU time 7.34 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:19 PM PDT 24
Peak memory 218068 kb
Host smart-b7c4fe19-4b50-4ff8-abfd-fc51986ed619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141893363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.141893363
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.216660874
Short name T385
Test name
Test status
Simulation time 5053103680 ps
CPU time 15.33 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:15 PM PDT 24
Peak memory 218872 kb
Host smart-6833ada5-8446-4b6e-ade8-dff3991a0225
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216660874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.216660874
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2907013393
Short name T117
Test name
Test status
Simulation time 836538406 ps
CPU time 69.62 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:30:15 PM PDT 24
Peak memory 218832 kb
Host smart-7bf88a83-743a-47b0-b4c6-cb047c1666ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907013393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2907013393
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3933612402
Short name T455
Test name
Test status
Simulation time 2221039945 ps
CPU time 7.96 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:10 PM PDT 24
Peak memory 218948 kb
Host smart-e7431a3d-2d5e-4e7b-b323-7a1275972d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933612402 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3933612402
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3993250969
Short name T371
Test name
Test status
Simulation time 1563308142 ps
CPU time 6.45 seconds
Started Jul 05 04:28:49 PM PDT 24
Finished Jul 05 04:29:04 PM PDT 24
Peak memory 217552 kb
Host smart-aacd2a08-4f92-40e8-92cd-17783a3c2f20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993250969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3993250969
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4060157715
Short name T93
Test name
Test status
Simulation time 17544517167 ps
CPU time 59.18 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:59 PM PDT 24
Peak memory 210576 kb
Host smart-0b51fb35-7636-45cf-98d9-06f8656f2c36
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060157715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.4060157715
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3516713778
Short name T98
Test name
Test status
Simulation time 8068714038 ps
CPU time 16.02 seconds
Started Jul 05 04:29:03 PM PDT 24
Finished Jul 05 04:29:28 PM PDT 24
Peak memory 218836 kb
Host smart-950aa30f-6121-4986-b525-417cd0558943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516713778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3516713778
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.820794112
Short name T408
Test name
Test status
Simulation time 1844636112 ps
CPU time 17.68 seconds
Started Jul 05 04:28:55 PM PDT 24
Finished Jul 05 04:29:22 PM PDT 24
Peak memory 218848 kb
Host smart-5b402260-148f-4c91-93ef-1b2a60905665
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820794112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.820794112
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1709562578
Short name T440
Test name
Test status
Simulation time 197786797 ps
CPU time 36.58 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:29:42 PM PDT 24
Peak memory 212044 kb
Host smart-8b8cd7d8-d62f-4612-a7ad-185d95078c85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709562578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1709562578
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2361246485
Short name T446
Test name
Test status
Simulation time 817823017 ps
CPU time 9.14 seconds
Started Jul 05 04:28:46 PM PDT 24
Finished Jul 05 04:29:05 PM PDT 24
Peak memory 218752 kb
Host smart-175bd0ab-ae15-4f5b-a5e8-6f9716926080
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361246485 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2361246485
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2384204262
Short name T397
Test name
Test status
Simulation time 347406332 ps
CPU time 4.17 seconds
Started Jul 05 04:28:46 PM PDT 24
Finished Jul 05 04:29:00 PM PDT 24
Peak memory 217688 kb
Host smart-f9096238-558b-4fb7-9edd-30f5ddf5f4c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384204262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2384204262
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.461838177
Short name T462
Test name
Test status
Simulation time 32869440860 ps
CPU time 66.27 seconds
Started Jul 05 04:28:47 PM PDT 24
Finished Jul 05 04:30:03 PM PDT 24
Peak memory 210656 kb
Host smart-276bb640-b24b-4c27-877d-b15cd7977ae5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461838177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.461838177
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.402219370
Short name T441
Test name
Test status
Simulation time 2025954851 ps
CPU time 15.59 seconds
Started Jul 05 04:28:48 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 218804 kb
Host smart-b52bb35a-4ea7-41d8-9d56-799b31b8680d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402219370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.402219370
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.136169201
Short name T375
Test name
Test status
Simulation time 3599033024 ps
CPU time 11.67 seconds
Started Jul 05 04:28:34 PM PDT 24
Finished Jul 05 04:28:58 PM PDT 24
Peak memory 218912 kb
Host smart-013fa621-f8ad-412f-a771-0994afee2d58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136169201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.136169201
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2398674144
Short name T119
Test name
Test status
Simulation time 7300332121 ps
CPU time 44.26 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:43 PM PDT 24
Peak memory 212300 kb
Host smart-9ce49850-7a22-450e-b619-3e66d769dd14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398674144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2398674144
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.989868148
Short name T369
Test name
Test status
Simulation time 209603421 ps
CPU time 5.2 seconds
Started Jul 05 04:28:46 PM PDT 24
Finished Jul 05 04:29:01 PM PDT 24
Peak memory 218848 kb
Host smart-fb0e495f-79ad-4ddd-816c-d3a5aa79dbc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989868148 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.989868148
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3303535734
Short name T399
Test name
Test status
Simulation time 506485884 ps
CPU time 5.88 seconds
Started Jul 05 04:28:41 PM PDT 24
Finished Jul 05 04:28:59 PM PDT 24
Peak memory 210532 kb
Host smart-55d49c89-c715-4c75-85bb-1488aec527ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303535734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3303535734
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1226942613
Short name T431
Test name
Test status
Simulation time 48331169513 ps
CPU time 95.93 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:30:38 PM PDT 24
Peak memory 210688 kb
Host smart-5ad56323-1cae-41d2-9746-4482bc49bb3b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226942613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1226942613
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1634433054
Short name T460
Test name
Test status
Simulation time 5113936669 ps
CPU time 11.84 seconds
Started Jul 05 04:28:48 PM PDT 24
Finished Jul 05 04:29:09 PM PDT 24
Peak memory 211004 kb
Host smart-05196530-15ee-463f-a5e0-5e1a58b606fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634433054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1634433054
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3095516848
Short name T382
Test name
Test status
Simulation time 290843215 ps
CPU time 9.49 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:20 PM PDT 24
Peak memory 218856 kb
Host smart-c3526e8b-7082-41c8-9aee-626c26011d34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095516848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3095516848
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4217282799
Short name T350
Test name
Test status
Simulation time 210417382 ps
CPU time 5.59 seconds
Started Jul 05 04:32:32 PM PDT 24
Finished Jul 05 04:32:39 PM PDT 24
Peak memory 211248 kb
Host smart-22b03acf-1f71-4781-a7ea-082abcfa4098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217282799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4217282799
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.354131470
Short name T1
Test name
Test status
Simulation time 5542193906 ps
CPU time 70.74 seconds
Started Jul 05 04:32:30 PM PDT 24
Finished Jul 05 04:33:41 PM PDT 24
Peak memory 233880 kb
Host smart-58807161-78d5-4be5-954a-bde7627010aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354131470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.354131470
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1926531203
Short name T322
Test name
Test status
Simulation time 14434341686 ps
CPU time 30.63 seconds
Started Jul 05 04:32:28 PM PDT 24
Finished Jul 05 04:32:59 PM PDT 24
Peak memory 212256 kb
Host smart-b118b752-7511-440a-864e-1e187670e254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926531203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1926531203
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2846770106
Short name T266
Test name
Test status
Simulation time 190933752 ps
CPU time 10.11 seconds
Started Jul 05 04:32:51 PM PDT 24
Finished Jul 05 04:33:05 PM PDT 24
Peak memory 213592 kb
Host smart-b1393809-552b-416a-8d8a-f43284e09611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846770106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2846770106
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.669514344
Short name T290
Test name
Test status
Simulation time 1182276797 ps
CPU time 15.34 seconds
Started Jul 05 04:32:26 PM PDT 24
Finished Jul 05 04:32:41 PM PDT 24
Peak memory 215132 kb
Host smart-ab6810d2-f443-4f2f-8109-e5cc5e923b83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669514344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.669514344
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1943849545
Short name T150
Test name
Test status
Simulation time 1532645411 ps
CPU time 13.33 seconds
Started Jul 05 04:32:24 PM PDT 24
Finished Jul 05 04:32:38 PM PDT 24
Peak memory 211280 kb
Host smart-e2279b61-529e-45bb-9377-17fa6dcd15bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943849545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1943849545
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2052953663
Short name T137
Test name
Test status
Simulation time 18836774904 ps
CPU time 176.07 seconds
Started Jul 05 04:32:25 PM PDT 24
Finished Jul 05 04:35:22 PM PDT 24
Peak memory 212584 kb
Host smart-174ca9ba-ea80-4386-bed4-24351b41a0a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052953663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2052953663
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.162978006
Short name T171
Test name
Test status
Simulation time 6903658198 ps
CPU time 29.22 seconds
Started Jul 05 04:32:35 PM PDT 24
Finished Jul 05 04:33:05 PM PDT 24
Peak memory 212168 kb
Host smart-148b984e-1ec9-4942-9e5f-84abdae01bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162978006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.162978006
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1537542741
Short name T207
Test name
Test status
Simulation time 3784611039 ps
CPU time 17.04 seconds
Started Jul 05 04:32:20 PM PDT 24
Finished Jul 05 04:32:38 PM PDT 24
Peak memory 211348 kb
Host smart-44052882-ddea-45b2-b6e0-6cf50441b0a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1537542741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1537542741
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.950390598
Short name T26
Test name
Test status
Simulation time 7261020610 ps
CPU time 107.39 seconds
Started Jul 05 04:32:25 PM PDT 24
Finished Jul 05 04:34:13 PM PDT 24
Peak memory 236248 kb
Host smart-5aa10b8b-9775-41c9-a05a-96b197ae9c8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950390598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.950390598
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4278987671
Short name T222
Test name
Test status
Simulation time 9895481046 ps
CPU time 23.85 seconds
Started Jul 05 04:32:23 PM PDT 24
Finished Jul 05 04:32:47 PM PDT 24
Peak memory 214412 kb
Host smart-de0f4d64-29c1-4ed4-912b-776b5fceaa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278987671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4278987671
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3305981628
Short name T82
Test name
Test status
Simulation time 20790720622 ps
CPU time 67.38 seconds
Started Jul 05 04:32:24 PM PDT 24
Finished Jul 05 04:33:32 PM PDT 24
Peak memory 219308 kb
Host smart-b4a3287c-ab4b-4bf7-a61b-68febfb3f13f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305981628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3305981628
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.661417176
Short name T211
Test name
Test status
Simulation time 5518600771 ps
CPU time 8.43 seconds
Started Jul 05 04:32:42 PM PDT 24
Finished Jul 05 04:32:51 PM PDT 24
Peak memory 211432 kb
Host smart-0a54484c-50ac-491e-aba4-a72877480c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661417176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.661417176
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3814438742
Short name T324
Test name
Test status
Simulation time 29972693284 ps
CPU time 244.46 seconds
Started Jul 05 04:32:31 PM PDT 24
Finished Jul 05 04:36:37 PM PDT 24
Peak memory 233876 kb
Host smart-bdc4a7e9-1dbb-4bcc-8278-ba8f5cbdcf0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814438742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3814438742
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3147500538
Short name T219
Test name
Test status
Simulation time 2427669084 ps
CPU time 12.12 seconds
Started Jul 05 04:32:41 PM PDT 24
Finished Jul 05 04:32:54 PM PDT 24
Peak memory 211400 kb
Host smart-528f3bff-8810-4921-9b0d-8d2c0e4d9874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147500538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3147500538
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.988200355
Short name T305
Test name
Test status
Simulation time 13626294768 ps
CPU time 34.5 seconds
Started Jul 05 04:32:54 PM PDT 24
Finished Jul 05 04:33:32 PM PDT 24
Peak memory 213744 kb
Host smart-ab25b8ff-1a9e-4c4c-98b3-e8fa9928edd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988200355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.988200355
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3599054494
Short name T148
Test name
Test status
Simulation time 539183656 ps
CPU time 7.78 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:30 PM PDT 24
Peak memory 211340 kb
Host smart-d98d5c85-5ead-461f-aa1a-932f9f10d630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599054494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3599054494
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3416418885
Short name T274
Test name
Test status
Simulation time 3117626312 ps
CPU time 192.77 seconds
Started Jul 05 04:32:58 PM PDT 24
Finished Jul 05 04:36:13 PM PDT 24
Peak memory 234564 kb
Host smart-121b991e-e59e-4c96-887e-0c26341681c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416418885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3416418885
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3531515463
Short name T165
Test name
Test status
Simulation time 8185304455 ps
CPU time 15.38 seconds
Started Jul 05 04:32:45 PM PDT 24
Finished Jul 05 04:33:02 PM PDT 24
Peak memory 212452 kb
Host smart-5b1f8dec-158b-4ac7-8b14-8ccb08bc7118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531515463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3531515463
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3622112631
Short name T102
Test name
Test status
Simulation time 3802420666 ps
CPU time 16.18 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:33:06 PM PDT 24
Peak memory 211428 kb
Host smart-747e48c1-d43a-4025-a233-ecdf4c0416df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622112631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3622112631
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1312286876
Short name T31
Test name
Test status
Simulation time 28650072953 ps
CPU time 32.02 seconds
Started Jul 05 04:32:34 PM PDT 24
Finished Jul 05 04:33:07 PM PDT 24
Peak memory 213584 kb
Host smart-2a074a0d-9d60-4938-abf3-5e07a58a9398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312286876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1312286876
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3534545810
Short name T175
Test name
Test status
Simulation time 2089919459 ps
CPU time 26.76 seconds
Started Jul 05 04:32:34 PM PDT 24
Finished Jul 05 04:33:01 PM PDT 24
Peak memory 215712 kb
Host smart-f0a97610-a202-4084-86cc-8b4d0ba13738
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534545810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3534545810
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2157148804
Short name T181
Test name
Test status
Simulation time 5693859622 ps
CPU time 12.55 seconds
Started Jul 05 04:32:39 PM PDT 24
Finished Jul 05 04:32:52 PM PDT 24
Peak memory 211400 kb
Host smart-8b89fbad-29ea-44f8-9645-cbc373d41013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157148804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2157148804
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2298216797
Short name T196
Test name
Test status
Simulation time 1124844622 ps
CPU time 60.75 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:33:54 PM PDT 24
Peak memory 228376 kb
Host smart-61ac1f20-ea3a-4f0a-aab4-4d479eef4c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298216797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2298216797
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.358587236
Short name T321
Test name
Test status
Simulation time 8651886888 ps
CPU time 18.76 seconds
Started Jul 05 04:32:43 PM PDT 24
Finished Jul 05 04:33:03 PM PDT 24
Peak memory 212264 kb
Host smart-c9ebb12c-dc6e-4048-bd01-4d77e89c1b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358587236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.358587236
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3926923022
Short name T4
Test name
Test status
Simulation time 3906294549 ps
CPU time 13.59 seconds
Started Jul 05 04:32:44 PM PDT 24
Finished Jul 05 04:33:00 PM PDT 24
Peak memory 211364 kb
Host smart-ef62b21e-934e-4947-9b07-8a29f386954e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926923022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3926923022
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3010512712
Short name T223
Test name
Test status
Simulation time 7419105187 ps
CPU time 34.48 seconds
Started Jul 05 04:32:39 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 214220 kb
Host smart-2b27f70b-db89-4f90-897a-a32bcfe8241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010512712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3010512712
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2227408978
Short name T292
Test name
Test status
Simulation time 11980463043 ps
CPU time 35.4 seconds
Started Jul 05 04:32:53 PM PDT 24
Finished Jul 05 04:33:32 PM PDT 24
Peak memory 216728 kb
Host smart-7ad80d15-34f6-4a6c-ac5f-e11168cc1397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227408978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2227408978
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.667728089
Short name T69
Test name
Test status
Simulation time 1054996316 ps
CPU time 7.52 seconds
Started Jul 05 04:32:29 PM PDT 24
Finished Jul 05 04:32:38 PM PDT 24
Peak memory 211204 kb
Host smart-613f34a1-7556-480b-85d2-5d0bc185d071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667728089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.667728089
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1647317295
Short name T124
Test name
Test status
Simulation time 76847168195 ps
CPU time 139.19 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:35:13 PM PDT 24
Peak memory 227336 kb
Host smart-641cb899-1685-4986-9791-cb567749569f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647317295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1647317295
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2274411768
Short name T206
Test name
Test status
Simulation time 825321506 ps
CPU time 15.2 seconds
Started Jul 05 04:32:28 PM PDT 24
Finished Jul 05 04:32:44 PM PDT 24
Peak memory 211880 kb
Host smart-cc700232-0575-42c0-9105-f5fa3d4c0b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274411768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2274411768
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.349075357
Short name T302
Test name
Test status
Simulation time 99900701 ps
CPU time 5.42 seconds
Started Jul 05 04:32:44 PM PDT 24
Finished Jul 05 04:32:51 PM PDT 24
Peak memory 211340 kb
Host smart-5adca354-4ee9-4a23-b0f7-af2e4a273a46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349075357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.349075357
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3551641174
Short name T333
Test name
Test status
Simulation time 215266485 ps
CPU time 12.51 seconds
Started Jul 05 04:32:48 PM PDT 24
Finished Jul 05 04:33:04 PM PDT 24
Peak memory 213544 kb
Host smart-5f0e41f2-fbbd-4289-b364-6304820224a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551641174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3551641174
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2604034175
Short name T319
Test name
Test status
Simulation time 1401546485 ps
CPU time 12.49 seconds
Started Jul 05 04:32:53 PM PDT 24
Finished Jul 05 04:33:09 PM PDT 24
Peak memory 211372 kb
Host smart-3ec4cc04-e806-44a1-88d0-e872dd7cffda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604034175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2604034175
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.125160573
Short name T123
Test name
Test status
Simulation time 24976655743 ps
CPU time 242.07 seconds
Started Jul 05 04:32:51 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 213644 kb
Host smart-77e967bf-80e0-4cd9-b988-b231455eac14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125160573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.125160573
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.289454709
Short name T287
Test name
Test status
Simulation time 858719668 ps
CPU time 15.34 seconds
Started Jul 05 04:32:51 PM PDT 24
Finished Jul 05 04:33:10 PM PDT 24
Peak memory 211888 kb
Host smart-355bcbdd-92d5-4e51-b929-3e98c0721ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289454709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.289454709
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2401261604
Short name T262
Test name
Test status
Simulation time 18345836720 ps
CPU time 15.57 seconds
Started Jul 05 04:32:42 PM PDT 24
Finished Jul 05 04:33:02 PM PDT 24
Peak memory 211360 kb
Host smart-260d6911-603c-4ae9-8b8b-ebd8e64c7ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401261604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2401261604
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.209435320
Short name T13
Test name
Test status
Simulation time 3940003323 ps
CPU time 30.88 seconds
Started Jul 05 04:32:49 PM PDT 24
Finished Jul 05 04:33:23 PM PDT 24
Peak memory 213492 kb
Host smart-701e31fe-0159-4b3b-bd0f-ad14f724bf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209435320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.209435320
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.4063700231
Short name T352
Test name
Test status
Simulation time 11427037815 ps
CPU time 64.07 seconds
Started Jul 05 04:32:51 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 217140 kb
Host smart-6b316a77-1d9e-4dd7-804c-058576515329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063700231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.4063700231
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.4218857413
Short name T44
Test name
Test status
Simulation time 21748858682 ps
CPU time 688.17 seconds
Started Jul 05 04:32:37 PM PDT 24
Finished Jul 05 04:44:06 PM PDT 24
Peak memory 227600 kb
Host smart-57aebad5-12d4-462b-a8b6-dcc3e8459f62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218857413 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.4218857413
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2124742113
Short name T157
Test name
Test status
Simulation time 701782756 ps
CPU time 8.58 seconds
Started Jul 05 04:32:43 PM PDT 24
Finished Jul 05 04:32:54 PM PDT 24
Peak memory 211304 kb
Host smart-af0208a3-4b57-47b0-acda-9ab228e6c15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124742113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2124742113
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2675732796
Short name T183
Test name
Test status
Simulation time 79430577242 ps
CPU time 414.84 seconds
Started Jul 05 04:32:44 PM PDT 24
Finished Jul 05 04:39:41 PM PDT 24
Peak memory 212548 kb
Host smart-293db237-f28c-4fea-b5c0-92f24fadaba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675732796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2675732796
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3313403284
Short name T267
Test name
Test status
Simulation time 3812560021 ps
CPU time 21.58 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:33:11 PM PDT 24
Peak memory 211944 kb
Host smart-cff5152d-ab7e-442c-a474-6c14f951f5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313403284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3313403284
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.254226800
Short name T312
Test name
Test status
Simulation time 2903177001 ps
CPU time 13.42 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:33:03 PM PDT 24
Peak memory 211404 kb
Host smart-ee3f576b-0edd-41ea-a77c-ece17b318786
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254226800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.254226800
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.483017857
Short name T161
Test name
Test status
Simulation time 877437950 ps
CPU time 17.96 seconds
Started Jul 05 04:32:46 PM PDT 24
Finished Jul 05 04:33:06 PM PDT 24
Peak memory 213756 kb
Host smart-60e1006b-dd79-4bfc-8cce-f80343c99213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483017857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.483017857
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3229337846
Short name T94
Test name
Test status
Simulation time 221810469 ps
CPU time 10.96 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:33:00 PM PDT 24
Peak memory 214928 kb
Host smart-a8993f95-bae4-4565-8ff3-6f340181c3d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229337846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3229337846
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.617100450
Short name T331
Test name
Test status
Simulation time 450482248853 ps
CPU time 4184.85 seconds
Started Jul 05 04:32:41 PM PDT 24
Finished Jul 05 05:42:27 PM PDT 24
Peak memory 252196 kb
Host smart-a17811fc-6607-4e7c-865d-d08e4ff51985
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617100450 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.617100450
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.15015993
Short name T247
Test name
Test status
Simulation time 4098910898 ps
CPU time 10.52 seconds
Started Jul 05 04:32:44 PM PDT 24
Finished Jul 05 04:32:57 PM PDT 24
Peak memory 211312 kb
Host smart-89f4f5a1-a492-439a-8421-4a570f2c7196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15015993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.15015993
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1184053562
Short name T218
Test name
Test status
Simulation time 28444656631 ps
CPU time 107.77 seconds
Started Jul 05 04:32:30 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 212492 kb
Host smart-89d1b17f-a494-41e9-9463-e165e81c74a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184053562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1184053562
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1711303105
Short name T301
Test name
Test status
Simulation time 10588709150 ps
CPU time 24.44 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:33:13 PM PDT 24
Peak memory 212220 kb
Host smart-1f133f92-a2f1-45f2-84c4-6dcf43278fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711303105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1711303105
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2868484987
Short name T341
Test name
Test status
Simulation time 2104595054 ps
CPU time 17.4 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:33:11 PM PDT 24
Peak memory 211320 kb
Host smart-2d292949-5892-4777-b899-240c0f8020a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868484987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2868484987
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2410272394
Short name T356
Test name
Test status
Simulation time 2996743873 ps
CPU time 14.5 seconds
Started Jul 05 04:32:51 PM PDT 24
Finished Jul 05 04:33:09 PM PDT 24
Peak memory 213860 kb
Host smart-e99d3196-88ec-47d3-9649-e03e9cada4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410272394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2410272394
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1263908057
Short name T353
Test name
Test status
Simulation time 25514854991 ps
CPU time 70.94 seconds
Started Jul 05 04:32:40 PM PDT 24
Finished Jul 05 04:33:51 PM PDT 24
Peak memory 217412 kb
Host smart-1cc49658-f047-4316-a49e-6c3531c762ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263908057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1263908057
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.222117640
Short name T179
Test name
Test status
Simulation time 7603195021 ps
CPU time 10.3 seconds
Started Jul 05 04:32:43 PM PDT 24
Finished Jul 05 04:32:56 PM PDT 24
Peak memory 211372 kb
Host smart-91b660e0-aa3b-40cf-b20f-6914ead3fa12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222117640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.222117640
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.881791701
Short name T231
Test name
Test status
Simulation time 74104117983 ps
CPU time 189.16 seconds
Started Jul 05 04:32:49 PM PDT 24
Finished Jul 05 04:36:01 PM PDT 24
Peak memory 212628 kb
Host smart-ddb69270-ade4-46e9-9128-45fb82c89638
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881791701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.881791701
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1849883930
Short name T189
Test name
Test status
Simulation time 3449460000 ps
CPU time 20.93 seconds
Started Jul 05 04:33:06 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 211804 kb
Host smart-f537294d-3d77-4c70-946a-33ddcccf123f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849883930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1849883930
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2068932996
Short name T156
Test name
Test status
Simulation time 3995866562 ps
CPU time 11.36 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:33:05 PM PDT 24
Peak memory 211388 kb
Host smart-d01606d8-be4a-48ae-a42c-b74a91ac38e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068932996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2068932996
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.74271720
Short name T255
Test name
Test status
Simulation time 2143724385 ps
CPU time 22.74 seconds
Started Jul 05 04:32:39 PM PDT 24
Finished Jul 05 04:33:03 PM PDT 24
Peak memory 213344 kb
Host smart-d185f705-cd96-440e-8f55-15ae86b32604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74271720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.74271720
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3834686606
Short name T256
Test name
Test status
Simulation time 1615006521 ps
CPU time 34.55 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:33:24 PM PDT 24
Peak memory 216584 kb
Host smart-20170058-f997-4403-8032-5a9e6f14d88a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834686606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3834686606
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2166579858
Short name T56
Test name
Test status
Simulation time 45363913825 ps
CPU time 1831.19 seconds
Started Jul 05 04:32:44 PM PDT 24
Finished Jul 05 05:03:17 PM PDT 24
Peak memory 235840 kb
Host smart-f9b4c262-9de2-47d9-aeb2-51245c89b5d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166579858 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2166579858
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2038664355
Short name T60
Test name
Test status
Simulation time 1102727940 ps
CPU time 10.64 seconds
Started Jul 05 04:33:00 PM PDT 24
Finished Jul 05 04:33:12 PM PDT 24
Peak memory 211356 kb
Host smart-e34f09e7-a0b8-4d1c-a0b2-e4dbba259088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038664355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2038664355
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.561513423
Short name T260
Test name
Test status
Simulation time 27297051679 ps
CPU time 122.89 seconds
Started Jul 05 04:32:48 PM PDT 24
Finished Jul 05 04:34:54 PM PDT 24
Peak memory 212644 kb
Host smart-c0afa64a-4124-4c52-8d67-bd3a9cbe3479
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561513423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.561513423
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2169964950
Short name T282
Test name
Test status
Simulation time 1155894171 ps
CPU time 16.6 seconds
Started Jul 05 04:32:36 PM PDT 24
Finished Jul 05 04:32:53 PM PDT 24
Peak memory 211952 kb
Host smart-7512069c-4bf2-4f46-a307-e02de8dcb39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169964950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2169964950
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1722887229
Short name T345
Test name
Test status
Simulation time 9424515446 ps
CPU time 17.18 seconds
Started Jul 05 04:32:39 PM PDT 24
Finished Jul 05 04:33:02 PM PDT 24
Peak memory 211356 kb
Host smart-9d642fdc-f994-45d6-8482-85cb5538ddf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722887229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1722887229
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2685547382
Short name T272
Test name
Test status
Simulation time 7579807823 ps
CPU time 37.04 seconds
Started Jul 05 04:32:44 PM PDT 24
Finished Jul 05 04:33:23 PM PDT 24
Peak memory 213604 kb
Host smart-47f29d1c-e35d-47a2-afdd-51f8e2a0b786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685547382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2685547382
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1809980179
Short name T185
Test name
Test status
Simulation time 4610764270 ps
CPU time 46.66 seconds
Started Jul 05 04:32:48 PM PDT 24
Finished Jul 05 04:33:38 PM PDT 24
Peak memory 213176 kb
Host smart-a056d76a-bd38-4e79-8965-654587e83da9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809980179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1809980179
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1672243449
Short name T281
Test name
Test status
Simulation time 2675593876 ps
CPU time 12.53 seconds
Started Jul 05 04:32:46 PM PDT 24
Finished Jul 05 04:33:01 PM PDT 24
Peak memory 211324 kb
Host smart-54696655-13b3-4faf-8438-66482ce3e467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672243449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1672243449
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1408369806
Short name T205
Test name
Test status
Simulation time 150945845202 ps
CPU time 336.82 seconds
Started Jul 05 04:32:55 PM PDT 24
Finished Jul 05 04:38:39 PM PDT 24
Peak memory 233736 kb
Host smart-a39b73c4-7ee7-4324-9160-666cd4d7140d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408369806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1408369806
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.108839047
Short name T240
Test name
Test status
Simulation time 14218571650 ps
CPU time 28.58 seconds
Started Jul 05 04:32:59 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 212420 kb
Host smart-614f5e28-c260-4272-8cd8-643f912d930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108839047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.108839047
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.405092483
Short name T159
Test name
Test status
Simulation time 6819695715 ps
CPU time 12.75 seconds
Started Jul 05 04:32:56 PM PDT 24
Finished Jul 05 04:33:11 PM PDT 24
Peak memory 211376 kb
Host smart-bfd89881-cb4d-40da-9a04-d76419b921dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405092483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.405092483
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2127922300
Short name T169
Test name
Test status
Simulation time 4049843490 ps
CPU time 44.3 seconds
Started Jul 05 04:32:55 PM PDT 24
Finished Jul 05 04:33:42 PM PDT 24
Peak memory 213632 kb
Host smart-de5ceb9a-50c7-4543-b1eb-d1ca98a7fba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127922300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2127922300
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3081459627
Short name T34
Test name
Test status
Simulation time 11162293221 ps
CPU time 54.55 seconds
Started Jul 05 04:32:52 PM PDT 24
Finished Jul 05 04:33:50 PM PDT 24
Peak memory 217580 kb
Host smart-4e80c6d2-5631-4ca7-9f45-d74603bfa89f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081459627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3081459627
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1102086946
Short name T283
Test name
Test status
Simulation time 3167925500 ps
CPU time 13.45 seconds
Started Jul 05 04:32:32 PM PDT 24
Finished Jul 05 04:32:47 PM PDT 24
Peak memory 211308 kb
Host smart-7be1e0cc-a561-4af0-81ea-2fba04d21af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102086946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1102086946
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2687473628
Short name T244
Test name
Test status
Simulation time 85381950304 ps
CPU time 242.76 seconds
Started Jul 05 04:32:41 PM PDT 24
Finished Jul 05 04:36:44 PM PDT 24
Peak memory 236764 kb
Host smart-c6a75fc2-2e09-4e9b-bf6b-ffaf7843526a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687473628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2687473628
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1346930169
Short name T243
Test name
Test status
Simulation time 341344718 ps
CPU time 9.57 seconds
Started Jul 05 04:32:28 PM PDT 24
Finished Jul 05 04:32:38 PM PDT 24
Peak memory 211864 kb
Host smart-7e9665e7-4fd9-433d-aeb6-6cf5bf6e2daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346930169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1346930169
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.76888839
Short name T128
Test name
Test status
Simulation time 7557126247 ps
CPU time 16.55 seconds
Started Jul 05 04:32:34 PM PDT 24
Finished Jul 05 04:32:52 PM PDT 24
Peak memory 211432 kb
Host smart-1e8d822d-e6df-4bc1-976b-5b906ebc4e94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76888839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.76888839
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.864425042
Short name T18
Test name
Test status
Simulation time 5927480644 ps
CPU time 104.93 seconds
Started Jul 05 04:32:16 PM PDT 24
Finished Jul 05 04:34:02 PM PDT 24
Peak memory 237304 kb
Host smart-fa10c102-0705-49d2-9bd2-7e7c4d1b2aaf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864425042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.864425042
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1839804200
Short name T215
Test name
Test status
Simulation time 216371318 ps
CPU time 10.07 seconds
Started Jul 05 04:32:42 PM PDT 24
Finished Jul 05 04:32:53 PM PDT 24
Peak memory 213972 kb
Host smart-36bb3dc5-32ff-4019-a348-9aa133cfe339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839804200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1839804200
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4156159894
Short name T149
Test name
Test status
Simulation time 4658311640 ps
CPU time 42.64 seconds
Started Jul 05 04:32:18 PM PDT 24
Finished Jul 05 04:33:02 PM PDT 24
Peak memory 216712 kb
Host smart-f0fa4794-5d8c-45c4-a7ab-e853b748dea2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156159894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4156159894
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1285317691
Short name T300
Test name
Test status
Simulation time 1032733575 ps
CPU time 4.32 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:32:58 PM PDT 24
Peak memory 211268 kb
Host smart-6790d719-2705-4796-ab86-8153a07d70a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285317691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1285317691
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2853308630
Short name T201
Test name
Test status
Simulation time 25215935382 ps
CPU time 261.32 seconds
Started Jul 05 04:32:53 PM PDT 24
Finished Jul 05 04:37:18 PM PDT 24
Peak memory 212612 kb
Host smart-f4b2353b-dbe7-40c9-bced-196e076adc28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853308630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2853308630
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3007826512
Short name T263
Test name
Test status
Simulation time 4256492315 ps
CPU time 33.37 seconds
Started Jul 05 04:32:39 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 212116 kb
Host smart-73db2ae5-4470-4cbe-bd9d-fb0d89025d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007826512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3007826512
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1039844434
Short name T173
Test name
Test status
Simulation time 2195502051 ps
CPU time 17.58 seconds
Started Jul 05 04:32:59 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 211352 kb
Host smart-314175c7-48f0-4707-8a26-656e089c2a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039844434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1039844434
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2821374423
Short name T59
Test name
Test status
Simulation time 777357240 ps
CPU time 10.27 seconds
Started Jul 05 04:32:48 PM PDT 24
Finished Jul 05 04:33:02 PM PDT 24
Peak memory 213668 kb
Host smart-5a2dd163-c383-4f33-84d2-f1ab4c43416e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821374423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2821374423
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2675046912
Short name T193
Test name
Test status
Simulation time 2611207613 ps
CPU time 20.88 seconds
Started Jul 05 04:32:45 PM PDT 24
Finished Jul 05 04:33:08 PM PDT 24
Peak memory 213772 kb
Host smart-c99e41ae-9130-4b20-887a-9333d38bde94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675046912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2675046912
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3732947773
Short name T306
Test name
Test status
Simulation time 6951707679 ps
CPU time 15.28 seconds
Started Jul 05 04:32:36 PM PDT 24
Finished Jul 05 04:32:57 PM PDT 24
Peak memory 211320 kb
Host smart-f9724c99-1658-4c4c-b988-0b401d7da6a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732947773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3732947773
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1366758263
Short name T236
Test name
Test status
Simulation time 37129064052 ps
CPU time 184.32 seconds
Started Jul 05 04:32:39 PM PDT 24
Finished Jul 05 04:35:44 PM PDT 24
Peak memory 237800 kb
Host smart-0ad1c44a-7736-45ee-8468-45e3d0208e74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366758263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1366758263
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.555979347
Short name T279
Test name
Test status
Simulation time 32903595403 ps
CPU time 22.44 seconds
Started Jul 05 04:32:55 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 212096 kb
Host smart-c8c8772a-c3c9-437b-96f4-cc703a576ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555979347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.555979347
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2745370556
Short name T242
Test name
Test status
Simulation time 218495066 ps
CPU time 7.14 seconds
Started Jul 05 04:32:43 PM PDT 24
Finished Jul 05 04:32:52 PM PDT 24
Peak memory 211300 kb
Host smart-64c205d3-0a5c-4799-bb32-86d693c18be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745370556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2745370556
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.22298373
Short name T29
Test name
Test status
Simulation time 7993081233 ps
CPU time 32.07 seconds
Started Jul 05 04:32:55 PM PDT 24
Finished Jul 05 04:33:30 PM PDT 24
Peak memory 214504 kb
Host smart-11d7a8c0-367b-423f-bfbd-abc6b01beac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22298373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.22298373
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1845043032
Short name T249
Test name
Test status
Simulation time 8425728405 ps
CPU time 30.34 seconds
Started Jul 05 04:32:43 PM PDT 24
Finished Jul 05 04:33:16 PM PDT 24
Peak memory 215576 kb
Host smart-845bac49-880d-4d65-93d5-9696ce568fdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845043032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1845043032
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.777521670
Short name T213
Test name
Test status
Simulation time 771291068 ps
CPU time 5.71 seconds
Started Jul 05 04:32:41 PM PDT 24
Finished Jul 05 04:32:47 PM PDT 24
Peak memory 211312 kb
Host smart-7d49dced-95c8-428c-9cd4-0c235bf6dfa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777521670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.777521670
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1598813178
Short name T40
Test name
Test status
Simulation time 117232082180 ps
CPU time 152.36 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:35:21 PM PDT 24
Peak memory 236812 kb
Host smart-545f62bf-c740-48be-b0bd-11bb11eddb41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598813178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1598813178
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2957701915
Short name T248
Test name
Test status
Simulation time 4476124926 ps
CPU time 21.99 seconds
Started Jul 05 04:32:49 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 212408 kb
Host smart-45197312-dc8e-481f-94d8-fa3a7627f709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957701915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2957701915
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.211314203
Short name T346
Test name
Test status
Simulation time 2282636808 ps
CPU time 12.08 seconds
Started Jul 05 04:32:48 PM PDT 24
Finished Jul 05 04:33:03 PM PDT 24
Peak memory 211352 kb
Host smart-9b8015cf-86f2-4eb0-a1b8-7b831da4e3e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211314203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.211314203
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1951678916
Short name T202
Test name
Test status
Simulation time 7895649684 ps
CPU time 24.52 seconds
Started Jul 05 04:32:56 PM PDT 24
Finished Jul 05 04:33:23 PM PDT 24
Peak memory 213512 kb
Host smart-2e661492-69b6-4f14-8b9d-029e54c233be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951678916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1951678916
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.361650506
Short name T9
Test name
Test status
Simulation time 499284947 ps
CPU time 8.33 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:33:02 PM PDT 24
Peak memory 211240 kb
Host smart-2d0bf258-21e6-4e57-9b55-f4677726a53d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361650506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.361650506
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2993483379
Short name T55
Test name
Test status
Simulation time 69165847779 ps
CPU time 2658.59 seconds
Started Jul 05 04:32:42 PM PDT 24
Finished Jul 05 05:17:02 PM PDT 24
Peak memory 240736 kb
Host smart-3f437b16-919a-4b1d-8a29-8e93bb78bffa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993483379 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2993483379
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3157141787
Short name T71
Test name
Test status
Simulation time 602122366 ps
CPU time 6.11 seconds
Started Jul 05 04:32:49 PM PDT 24
Finished Jul 05 04:32:58 PM PDT 24
Peak memory 211368 kb
Host smart-4fa79b10-5e99-4cb5-b2cc-97fa4c5187cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157141787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3157141787
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1929313984
Short name T277
Test name
Test status
Simulation time 1531932843 ps
CPU time 101.59 seconds
Started Jul 05 04:32:41 PM PDT 24
Finished Jul 05 04:34:24 PM PDT 24
Peak memory 237012 kb
Host smart-e9068dfc-5916-445f-8e3e-2d3cc80fc663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929313984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1929313984
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1189010291
Short name T190
Test name
Test status
Simulation time 7577112644 ps
CPU time 15.65 seconds
Started Jul 05 04:32:56 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 211280 kb
Host smart-d40ddba5-76fa-4d55-8142-1713939be924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1189010291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1189010291
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2760009271
Short name T252
Test name
Test status
Simulation time 17454111995 ps
CPU time 37.32 seconds
Started Jul 05 04:32:43 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 214560 kb
Host smart-3c1c4c1a-43db-40d8-b6e7-c778695adde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760009271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2760009271
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.50819219
Short name T227
Test name
Test status
Simulation time 10324969173 ps
CPU time 32.26 seconds
Started Jul 05 04:32:44 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 213892 kb
Host smart-719cb17c-dd81-4500-ad15-4c034c3ca205
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50819219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.rom_ctrl_stress_all.50819219
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4228397618
Short name T296
Test name
Test status
Simulation time 8084999976 ps
CPU time 13.41 seconds
Started Jul 05 04:32:53 PM PDT 24
Finished Jul 05 04:33:09 PM PDT 24
Peak memory 211336 kb
Host smart-a89829ad-5af5-4cfa-985e-9e4963fbb6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228397618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4228397618
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.587016531
Short name T20
Test name
Test status
Simulation time 63269956159 ps
CPU time 347.93 seconds
Started Jul 05 04:32:53 PM PDT 24
Finished Jul 05 04:38:45 PM PDT 24
Peak memory 237764 kb
Host smart-ba972838-bd0a-4d4e-894c-75bf6e151292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587016531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.587016531
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1719774075
Short name T46
Test name
Test status
Simulation time 185093276 ps
CPU time 9.39 seconds
Started Jul 05 04:32:52 PM PDT 24
Finished Jul 05 04:33:05 PM PDT 24
Peak memory 211776 kb
Host smart-147ff221-a441-4a6e-8aef-618d0301c688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719774075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1719774075
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4280893559
Short name T307
Test name
Test status
Simulation time 3115092843 ps
CPU time 17.35 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:33:07 PM PDT 24
Peak memory 211432 kb
Host smart-ad24ee3f-f8fa-4767-85c7-ff4c73c10eaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280893559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.4280893559
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3322811481
Short name T295
Test name
Test status
Simulation time 7646361480 ps
CPU time 32.36 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:33:40 PM PDT 24
Peak memory 214624 kb
Host smart-c4047b88-00ce-4a4f-9206-8e28a2a2b864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322811481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3322811481
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1071801494
Short name T33
Test name
Test status
Simulation time 16180451397 ps
CPU time 42.15 seconds
Started Jul 05 04:32:49 PM PDT 24
Finished Jul 05 04:33:35 PM PDT 24
Peak memory 216908 kb
Host smart-e9fa85d1-90e7-420a-b1f9-494829cce1ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071801494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1071801494
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.67089551
Short name T177
Test name
Test status
Simulation time 2471043568 ps
CPU time 5.88 seconds
Started Jul 05 04:33:13 PM PDT 24
Finished Jul 05 04:33:23 PM PDT 24
Peak memory 211292 kb
Host smart-adf6be0f-1b0f-44d6-b652-79e089a92527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67089551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.67089551
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1013818221
Short name T38
Test name
Test status
Simulation time 27047119551 ps
CPU time 205.1 seconds
Started Jul 05 04:32:53 PM PDT 24
Finished Jul 05 04:36:21 PM PDT 24
Peak memory 237396 kb
Host smart-600da6dc-bda3-4eca-ac65-5ceba9648fca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013818221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1013818221
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1454358144
Short name T24
Test name
Test status
Simulation time 665727288 ps
CPU time 9.39 seconds
Started Jul 05 04:32:49 PM PDT 24
Finished Jul 05 04:33:02 PM PDT 24
Peak memory 211796 kb
Host smart-5d9a7bd6-e850-4858-aef9-4b437b6d5e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454358144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1454358144
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3408052119
Short name T160
Test name
Test status
Simulation time 5635902780 ps
CPU time 11.21 seconds
Started Jul 05 04:33:01 PM PDT 24
Finished Jul 05 04:33:15 PM PDT 24
Peak memory 211428 kb
Host smart-8018fa5e-bd50-4b42-9e1d-f2d2593959b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408052119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3408052119
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2700456906
Short name T203
Test name
Test status
Simulation time 25651478787 ps
CPU time 37.22 seconds
Started Jul 05 04:32:49 PM PDT 24
Finished Jul 05 04:33:30 PM PDT 24
Peak memory 214204 kb
Host smart-4e09fa37-dddb-4126-9226-c761be29e1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700456906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2700456906
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2088433647
Short name T271
Test name
Test status
Simulation time 4279515060 ps
CPU time 48.07 seconds
Started Jul 05 04:32:39 PM PDT 24
Finished Jul 05 04:33:27 PM PDT 24
Peak memory 217296 kb
Host smart-6442da50-e911-46e7-a029-a63a3e53d09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088433647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2088433647
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2643682029
Short name T285
Test name
Test status
Simulation time 2668780093 ps
CPU time 7.44 seconds
Started Jul 05 04:33:09 PM PDT 24
Finished Jul 05 04:33:19 PM PDT 24
Peak memory 211360 kb
Host smart-f74b3d76-3972-4e8c-8f58-1112607b6550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643682029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2643682029
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3912613528
Short name T41
Test name
Test status
Simulation time 18871876106 ps
CPU time 106.85 seconds
Started Jul 05 04:32:52 PM PDT 24
Finished Jul 05 04:34:43 PM PDT 24
Peak memory 234808 kb
Host smart-6aa87635-1406-40f8-be48-8fa1e93d4c16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912613528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3912613528
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2710156692
Short name T245
Test name
Test status
Simulation time 4710911040 ps
CPU time 33.84 seconds
Started Jul 05 04:32:54 PM PDT 24
Finished Jul 05 04:33:31 PM PDT 24
Peak memory 216732 kb
Host smart-6eb95a24-a6ab-49e8-8032-dee465d20c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710156692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2710156692
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3368596659
Short name T134
Test name
Test status
Simulation time 937984090 ps
CPU time 5.54 seconds
Started Jul 05 04:32:53 PM PDT 24
Finished Jul 05 04:33:01 PM PDT 24
Peak memory 211308 kb
Host smart-000f4f1e-f896-4e57-a3cd-5095977e1c8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368596659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3368596659
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.765909143
Short name T234
Test name
Test status
Simulation time 2798101582 ps
CPU time 14.58 seconds
Started Jul 05 04:32:49 PM PDT 24
Finished Jul 05 04:33:07 PM PDT 24
Peak memory 213864 kb
Host smart-1a3f1d3c-e77b-499c-b48d-ca343d2448fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765909143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.765909143
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2535185217
Short name T250
Test name
Test status
Simulation time 77592924919 ps
CPU time 113.34 seconds
Started Jul 05 04:32:42 PM PDT 24
Finished Jul 05 04:34:37 PM PDT 24
Peak memory 219324 kb
Host smart-d0db2149-3007-4265-a07c-9a364b4a8102
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535185217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2535185217
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.918380440
Short name T180
Test name
Test status
Simulation time 397154793 ps
CPU time 4.39 seconds
Started Jul 05 04:32:51 PM PDT 24
Finished Jul 05 04:32:59 PM PDT 24
Peak memory 211288 kb
Host smart-358cf2df-aa2b-4f2a-bd30-07c4fab5d076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918380440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.918380440
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1135145181
Short name T298
Test name
Test status
Simulation time 24199982362 ps
CPU time 220.47 seconds
Started Jul 05 04:33:03 PM PDT 24
Finished Jul 05 04:36:46 PM PDT 24
Peak memory 234728 kb
Host smart-cec7c90e-e0a1-4d2d-bf7e-b0cb73c926b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135145181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1135145181
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3698194579
Short name T360
Test name
Test status
Simulation time 49432642890 ps
CPU time 24.6 seconds
Started Jul 05 04:32:49 PM PDT 24
Finished Jul 05 04:33:16 PM PDT 24
Peak memory 211356 kb
Host smart-31d90d9c-5f3d-4e9c-a3e9-26b7075e8241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698194579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3698194579
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.71061951
Short name T152
Test name
Test status
Simulation time 2170215542 ps
CPU time 8.7 seconds
Started Jul 05 04:33:09 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 211364 kb
Host smart-bc7c9f50-1b5a-4e22-8425-2762dc10b2b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71061951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.71061951
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.862145536
Short name T200
Test name
Test status
Simulation time 190150949 ps
CPU time 10.36 seconds
Started Jul 05 04:33:03 PM PDT 24
Finished Jul 05 04:33:15 PM PDT 24
Peak memory 213356 kb
Host smart-7bfb4d45-6025-431a-aa8a-df7f24740e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862145536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.862145536
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3033930974
Short name T110
Test name
Test status
Simulation time 24198903117 ps
CPU time 54.18 seconds
Started Jul 05 04:32:55 PM PDT 24
Finished Jul 05 04:33:52 PM PDT 24
Peak memory 219436 kb
Host smart-b0d77497-5abd-4e9d-9e14-da24e2607aa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033930974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3033930974
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3103469564
Short name T351
Test name
Test status
Simulation time 26129507327 ps
CPU time 6149.89 seconds
Started Jul 05 04:32:54 PM PDT 24
Finished Jul 05 06:15:27 PM PDT 24
Peak memory 229276 kb
Host smart-e89af36d-0799-4b53-998d-620a1b93bb54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103469564 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3103469564
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1757203478
Short name T329
Test name
Test status
Simulation time 87218634 ps
CPU time 4.24 seconds
Started Jul 05 04:32:58 PM PDT 24
Finished Jul 05 04:33:04 PM PDT 24
Peak memory 211324 kb
Host smart-640f5ec6-eb01-4d8b-8aae-aa86b247cd7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757203478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1757203478
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3033966513
Short name T313
Test name
Test status
Simulation time 5399809379 ps
CPU time 133.35 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:35:20 PM PDT 24
Peak memory 212580 kb
Host smart-4520d9ba-f149-4cff-b172-1b8398a22f62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033966513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3033966513
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.390776284
Short name T276
Test name
Test status
Simulation time 2367398615 ps
CPU time 9.41 seconds
Started Jul 05 04:32:56 PM PDT 24
Finished Jul 05 04:33:08 PM PDT 24
Peak memory 211872 kb
Host smart-4dc2f70f-8adb-4ccf-ab50-086d5159f2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390776284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.390776284
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.76418696
Short name T237
Test name
Test status
Simulation time 379646962 ps
CPU time 5.42 seconds
Started Jul 05 04:33:00 PM PDT 24
Finished Jul 05 04:33:07 PM PDT 24
Peak memory 211296 kb
Host smart-5f53141b-ab43-42d5-ac42-9ccdb6b8e92b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76418696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.76418696
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1959123821
Short name T11
Test name
Test status
Simulation time 13380370545 ps
CPU time 26.58 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:33:15 PM PDT 24
Peak memory 213728 kb
Host smart-9bc603ae-48e9-43be-af13-8959ef5ef33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959123821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1959123821
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2361810772
Short name T167
Test name
Test status
Simulation time 110242481 ps
CPU time 8.83 seconds
Started Jul 05 04:32:46 PM PDT 24
Finished Jul 05 04:32:57 PM PDT 24
Peak memory 211180 kb
Host smart-b446ff95-4266-4272-931f-458f0ccaf39a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361810772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2361810772
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1996986446
Short name T269
Test name
Test status
Simulation time 1736656165 ps
CPU time 14.28 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:33:08 PM PDT 24
Peak memory 211268 kb
Host smart-cacb1dbf-af19-4432-87a7-3836606ab0aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996986446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1996986446
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1098448865
Short name T184
Test name
Test status
Simulation time 11710160589 ps
CPU time 93.78 seconds
Started Jul 05 04:33:01 PM PDT 24
Finished Jul 05 04:34:37 PM PDT 24
Peak memory 212632 kb
Host smart-34744932-3cf2-429c-9380-f2862e3f5bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098448865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1098448865
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.175412730
Short name T325
Test name
Test status
Simulation time 2636901026 ps
CPU time 14.5 seconds
Started Jul 05 04:32:58 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 211904 kb
Host smart-90aa325a-fc3e-4d21-a9be-42fabe7b6bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175412730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.175412730
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3724892023
Short name T358
Test name
Test status
Simulation time 1783035663 ps
CPU time 7.41 seconds
Started Jul 05 04:33:13 PM PDT 24
Finished Jul 05 04:33:24 PM PDT 24
Peak memory 211376 kb
Host smart-2480c11a-21d5-42d1-817f-5ecd053f8a7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3724892023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3724892023
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2808787620
Short name T178
Test name
Test status
Simulation time 771525172 ps
CPU time 15.52 seconds
Started Jul 05 04:32:57 PM PDT 24
Finished Jul 05 04:33:15 PM PDT 24
Peak memory 213384 kb
Host smart-959e002f-7980-48cf-83aa-07f0f2a730d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808787620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2808787620
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4096282418
Short name T15
Test name
Test status
Simulation time 154524185031 ps
CPU time 71.83 seconds
Started Jul 05 04:33:00 PM PDT 24
Finished Jul 05 04:34:13 PM PDT 24
Peak memory 215428 kb
Host smart-9911f51b-20ce-4efb-8fad-3fc9e5e5320c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096282418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4096282418
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3805678516
Short name T7
Test name
Test status
Simulation time 18788474860 ps
CPU time 12.43 seconds
Started Jul 05 04:32:23 PM PDT 24
Finished Jul 05 04:32:36 PM PDT 24
Peak memory 211316 kb
Host smart-c97ddf89-2ad2-4997-b3b9-d4aab8bca7d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805678516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3805678516
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1242468593
Short name T204
Test name
Test status
Simulation time 61822199600 ps
CPU time 277.2 seconds
Started Jul 05 04:32:21 PM PDT 24
Finished Jul 05 04:37:00 PM PDT 24
Peak memory 240120 kb
Host smart-47a2c4fb-8ed1-4b9d-a984-7417c2395a5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242468593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1242468593
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3439521748
Short name T246
Test name
Test status
Simulation time 16391025039 ps
CPU time 32.51 seconds
Started Jul 05 04:32:13 PM PDT 24
Finished Jul 05 04:32:47 PM PDT 24
Peak memory 212172 kb
Host smart-61055a25-a811-4b3a-b7c5-0b24098ccf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439521748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3439521748
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2423342175
Short name T199
Test name
Test status
Simulation time 344440314 ps
CPU time 5.33 seconds
Started Jul 05 04:32:34 PM PDT 24
Finished Jul 05 04:32:40 PM PDT 24
Peak memory 211280 kb
Host smart-bbda27ef-800c-4f41-bf8e-8701c786882a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423342175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2423342175
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.255689921
Short name T16
Test name
Test status
Simulation time 756249407 ps
CPU time 98.09 seconds
Started Jul 05 04:32:36 PM PDT 24
Finished Jul 05 04:34:15 PM PDT 24
Peak memory 236848 kb
Host smart-fcc51bda-3c54-4e78-b5a1-b491ac0bd012
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255689921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.255689921
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3225459208
Short name T343
Test name
Test status
Simulation time 3919464305 ps
CPU time 32.38 seconds
Started Jul 05 04:32:21 PM PDT 24
Finished Jul 05 04:32:55 PM PDT 24
Peak memory 213288 kb
Host smart-0c9b4b17-9cc4-4efb-ac9c-4177f69f32d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225459208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3225459208
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1876955610
Short name T318
Test name
Test status
Simulation time 2982074264 ps
CPU time 34.36 seconds
Started Jul 05 04:32:38 PM PDT 24
Finished Jul 05 04:33:13 PM PDT 24
Peak memory 213224 kb
Host smart-ba92553e-df9a-40b0-9256-a200bc95088c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876955610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1876955610
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.464201014
Short name T355
Test name
Test status
Simulation time 6403974208 ps
CPU time 13.64 seconds
Started Jul 05 04:33:03 PM PDT 24
Finished Jul 05 04:33:19 PM PDT 24
Peak memory 211396 kb
Host smart-2847bfe5-61c0-4d55-b061-d438ee9da3d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464201014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.464201014
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1319608694
Short name T265
Test name
Test status
Simulation time 60828755174 ps
CPU time 179.36 seconds
Started Jul 05 04:32:55 PM PDT 24
Finished Jul 05 04:35:57 PM PDT 24
Peak memory 237832 kb
Host smart-1634f994-c056-4420-b18e-7e8145dc01a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319608694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1319608694
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.589865091
Short name T254
Test name
Test status
Simulation time 1367048088 ps
CPU time 13.83 seconds
Started Jul 05 04:32:54 PM PDT 24
Finished Jul 05 04:33:10 PM PDT 24
Peak memory 211960 kb
Host smart-2e2b08a4-b952-4b8c-bc51-d3f1de526840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589865091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.589865091
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2305084306
Short name T209
Test name
Test status
Simulation time 1302338700 ps
CPU time 8.98 seconds
Started Jul 05 04:32:55 PM PDT 24
Finished Jul 05 04:33:07 PM PDT 24
Peak memory 211368 kb
Host smart-d6606877-952b-4510-ac99-2ab7ffdb3a3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305084306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2305084306
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1359040110
Short name T286
Test name
Test status
Simulation time 318415414 ps
CPU time 10.19 seconds
Started Jul 05 04:32:57 PM PDT 24
Finished Jul 05 04:33:10 PM PDT 24
Peak memory 213892 kb
Host smart-7877995c-6bf1-4e37-92a6-1a61a035c252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359040110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1359040110
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1895948048
Short name T83
Test name
Test status
Simulation time 4238796398 ps
CPU time 19.22 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 213540 kb
Host smart-e026c59b-2f04-4029-bd97-9f8a97153e62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895948048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1895948048
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2025737476
Short name T52
Test name
Test status
Simulation time 248134354792 ps
CPU time 2627.62 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 05:17:06 PM PDT 24
Peak memory 244300 kb
Host smart-445cddb5-3f4f-45eb-a6c3-b4338d7c4241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025737476 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2025737476
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2401738103
Short name T162
Test name
Test status
Simulation time 1745998145 ps
CPU time 13.86 seconds
Started Jul 05 04:33:06 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 211340 kb
Host smart-a3427e5e-20a6-4ecb-994a-cff6279655ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401738103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2401738103
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1665263444
Short name T339
Test name
Test status
Simulation time 307120248178 ps
CPU time 456.55 seconds
Started Jul 05 04:33:03 PM PDT 24
Finished Jul 05 04:40:42 PM PDT 24
Peak memory 236512 kb
Host smart-fa5d894a-56f1-420c-8e06-ffb83cd64783
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665263444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1665263444
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3349861706
Short name T316
Test name
Test status
Simulation time 368183702 ps
CPU time 5.95 seconds
Started Jul 05 04:32:47 PM PDT 24
Finished Jul 05 04:32:55 PM PDT 24
Peak memory 211372 kb
Host smart-bf908cc7-8020-4a3d-adb7-367b016c5983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349861706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3349861706
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1789869172
Short name T62
Test name
Test status
Simulation time 2098499505 ps
CPU time 21.83 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:31 PM PDT 24
Peak memory 213664 kb
Host smart-724ecbd9-8faa-449d-9a81-ab483dad2061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789869172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1789869172
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1236141045
Short name T310
Test name
Test status
Simulation time 5556205580 ps
CPU time 58.87 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:33:53 PM PDT 24
Peak memory 216236 kb
Host smart-4eb71068-3599-4e21-b443-e4b87150d6a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236141045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1236141045
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2179738195
Short name T347
Test name
Test status
Simulation time 70291559314 ps
CPU time 2632.15 seconds
Started Jul 05 04:33:10 PM PDT 24
Finished Jul 05 05:17:05 PM PDT 24
Peak memory 242876 kb
Host smart-14a87d00-2954-41d4-8197-66ed2f22b995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179738195 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2179738195
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1674086637
Short name T239
Test name
Test status
Simulation time 175577743 ps
CPU time 4.28 seconds
Started Jul 05 04:32:59 PM PDT 24
Finished Jul 05 04:33:05 PM PDT 24
Peak memory 211312 kb
Host smart-b5e4b45a-f82e-4ec9-a6ee-734df2f7eadb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674086637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1674086637
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2586918685
Short name T136
Test name
Test status
Simulation time 6798110984 ps
CPU time 118.38 seconds
Started Jul 05 04:32:55 PM PDT 24
Finished Jul 05 04:34:56 PM PDT 24
Peak memory 237816 kb
Host smart-62e7c11d-19d4-40be-9a33-182a51e47288
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586918685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2586918685
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.174969310
Short name T330
Test name
Test status
Simulation time 2179797291 ps
CPU time 16.22 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:33:10 PM PDT 24
Peak memory 211852 kb
Host smart-a310097f-910f-448a-bb7d-a9dff16f41d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174969310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.174969310
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.975183351
Short name T344
Test name
Test status
Simulation time 5963230288 ps
CPU time 14.62 seconds
Started Jul 05 04:32:58 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 211400 kb
Host smart-5079d576-d77f-4ee1-89bf-57acb2c96d0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975183351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.975183351
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2885594524
Short name T224
Test name
Test status
Simulation time 13804251125 ps
CPU time 33.76 seconds
Started Jul 05 04:33:20 PM PDT 24
Finished Jul 05 04:33:59 PM PDT 24
Peak memory 213900 kb
Host smart-4c531296-9f0c-4353-8d4c-bba59de97257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885594524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2885594524
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1851782973
Short name T57
Test name
Test status
Simulation time 8647387229 ps
CPU time 24.33 seconds
Started Jul 05 04:32:45 PM PDT 24
Finished Jul 05 04:33:12 PM PDT 24
Peak memory 214968 kb
Host smart-60034e10-90ff-45ea-bc2a-7917d96d0d3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851782973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1851782973
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2681800933
Short name T22
Test name
Test status
Simulation time 32178340028 ps
CPU time 1234.38 seconds
Started Jul 05 04:32:51 PM PDT 24
Finished Jul 05 04:53:30 PM PDT 24
Peak memory 235856 kb
Host smart-ff65cd47-20c8-4c12-9fa6-f6d58e1e14d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681800933 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2681800933
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2533483690
Short name T241
Test name
Test status
Simulation time 588808439 ps
CPU time 6.17 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:24 PM PDT 24
Peak memory 211264 kb
Host smart-46d54fbd-b666-49c3-a9d1-5f6a16452aab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533483690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2533483690
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1447672556
Short name T304
Test name
Test status
Simulation time 18147851187 ps
CPU time 220.75 seconds
Started Jul 05 04:32:53 PM PDT 24
Finished Jul 05 04:36:37 PM PDT 24
Peak memory 212528 kb
Host smart-42ce0a3c-cdb5-4f41-a8f3-b823001d3ea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447672556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1447672556
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4277021759
Short name T332
Test name
Test status
Simulation time 6244751188 ps
CPU time 27.54 seconds
Started Jul 05 04:32:58 PM PDT 24
Finished Jul 05 04:33:28 PM PDT 24
Peak memory 212428 kb
Host smart-bdb2c9b9-b6b3-4a69-a96d-fafa7f377288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277021759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4277021759
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.666313821
Short name T144
Test name
Test status
Simulation time 2886054476 ps
CPU time 13.3 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 211428 kb
Host smart-db7d10cb-76d3-41dd-b446-ee0dbcb427d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=666313821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.666313821
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.806000838
Short name T342
Test name
Test status
Simulation time 4980562348 ps
CPU time 28.49 seconds
Started Jul 05 04:32:42 PM PDT 24
Finished Jul 05 04:33:12 PM PDT 24
Peak memory 214048 kb
Host smart-3fc986e2-d52d-48aa-8795-608ffcba94ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806000838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.806000838
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2233361071
Short name T47
Test name
Test status
Simulation time 2947970312 ps
CPU time 35.35 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:33:29 PM PDT 24
Peak memory 213432 kb
Host smart-e8430db9-7f5f-4dde-b7cd-da471db126f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233361071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2233361071
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3195080444
Short name T23
Test name
Test status
Simulation time 19015183304 ps
CPU time 677.82 seconds
Started Jul 05 04:33:01 PM PDT 24
Finished Jul 05 04:44:21 PM PDT 24
Peak memory 228020 kb
Host smart-bb10bb6b-1227-4846-bb92-b6da658c1738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195080444 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3195080444
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3460139065
Short name T198
Test name
Test status
Simulation time 1980570189 ps
CPU time 15.5 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:37 PM PDT 24
Peak memory 211340 kb
Host smart-12d76c16-b69e-42eb-84da-662b9c0fbee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460139065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3460139065
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.214766660
Short name T264
Test name
Test status
Simulation time 2966922057 ps
CPU time 88.98 seconds
Started Jul 05 04:32:56 PM PDT 24
Finished Jul 05 04:34:28 PM PDT 24
Peak memory 224632 kb
Host smart-95a7e94c-b5f5-49e7-9c7c-f3ef1f91d737
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214766660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.214766660
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4062841331
Short name T25
Test name
Test status
Simulation time 398345014 ps
CPU time 9.25 seconds
Started Jul 05 04:32:54 PM PDT 24
Finished Jul 05 04:33:06 PM PDT 24
Peak memory 212028 kb
Host smart-50495593-3a91-4909-bb95-7d1bc4c2f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062841331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4062841331
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3938896368
Short name T151
Test name
Test status
Simulation time 374066538 ps
CPU time 5.16 seconds
Started Jul 05 04:33:13 PM PDT 24
Finished Jul 05 04:33:23 PM PDT 24
Peak memory 211368 kb
Host smart-3b82be23-85ca-4cac-9e54-70e43d998a2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938896368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3938896368
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1564436476
Short name T172
Test name
Test status
Simulation time 12690926490 ps
CPU time 28.95 seconds
Started Jul 05 04:33:04 PM PDT 24
Finished Jul 05 04:33:35 PM PDT 24
Peak memory 213776 kb
Host smart-179fe405-6ba2-4919-9f14-eacadb5aab8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564436476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1564436476
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3894758526
Short name T280
Test name
Test status
Simulation time 5203327030 ps
CPU time 72.65 seconds
Started Jul 05 04:32:55 PM PDT 24
Finished Jul 05 04:34:11 PM PDT 24
Peak memory 218232 kb
Host smart-08e3cb87-8599-4419-ac34-c1ecdb7080b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894758526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3894758526
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2554409908
Short name T19
Test name
Test status
Simulation time 161499603 ps
CPU time 4.17 seconds
Started Jul 05 04:33:00 PM PDT 24
Finished Jul 05 04:33:07 PM PDT 24
Peak memory 211340 kb
Host smart-ccf16697-090d-4117-b9f0-59d71133d06e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554409908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2554409908
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2715919917
Short name T327
Test name
Test status
Simulation time 4010276035 ps
CPU time 103.44 seconds
Started Jul 05 04:33:21 PM PDT 24
Finished Jul 05 04:35:11 PM PDT 24
Peak memory 238852 kb
Host smart-04b1f675-b3ad-4caa-aaf4-44ba3342df5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715919917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2715919917
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1072996557
Short name T217
Test name
Test status
Simulation time 3395515323 ps
CPU time 28.89 seconds
Started Jul 05 04:32:42 PM PDT 24
Finished Jul 05 04:33:12 PM PDT 24
Peak memory 211820 kb
Host smart-2659d96b-7fad-4aed-878a-c75b29c6d13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072996557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1072996557
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4077820463
Short name T147
Test name
Test status
Simulation time 93339137 ps
CPU time 5.32 seconds
Started Jul 05 04:32:52 PM PDT 24
Finished Jul 05 04:33:01 PM PDT 24
Peak memory 211640 kb
Host smart-a85225b8-6bf1-4281-a285-2c7e8dfedab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077820463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4077820463
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3141504541
Short name T53
Test name
Test status
Simulation time 114996805308 ps
CPU time 2158.29 seconds
Started Jul 05 04:32:56 PM PDT 24
Finished Jul 05 05:08:57 PM PDT 24
Peak memory 237116 kb
Host smart-2674d1a7-25be-4716-b786-694c01dd4e9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141504541 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3141504541
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2076828100
Short name T146
Test name
Test status
Simulation time 1196203983 ps
CPU time 11.29 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 211336 kb
Host smart-cb03de3b-b77f-4340-b822-cd5e7b4042be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076828100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2076828100
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.117794151
Short name T194
Test name
Test status
Simulation time 168574779288 ps
CPU time 104.73 seconds
Started Jul 05 04:32:58 PM PDT 24
Finished Jul 05 04:34:45 PM PDT 24
Peak memory 235916 kb
Host smart-1f8c0cbf-064f-4734-a8d5-97894f27839b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117794151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.117794151
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3013739094
Short name T315
Test name
Test status
Simulation time 2989415826 ps
CPU time 26.19 seconds
Started Jul 05 04:32:58 PM PDT 24
Finished Jul 05 04:33:26 PM PDT 24
Peak memory 212064 kb
Host smart-030a1664-3e58-4ac3-95a1-5ab6c1b1bb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013739094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3013739094
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4095822724
Short name T103
Test name
Test status
Simulation time 381522656 ps
CPU time 5.32 seconds
Started Jul 05 04:33:09 PM PDT 24
Finished Jul 05 04:33:16 PM PDT 24
Peak memory 211292 kb
Host smart-e048ca29-daa0-41f3-a12d-d1a6a5e2425b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4095822724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4095822724
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1193583108
Short name T253
Test name
Test status
Simulation time 1288830140 ps
CPU time 9.97 seconds
Started Jul 05 04:33:08 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 213636 kb
Host smart-3cb50a46-05b7-4a90-a2a8-98f1e2134b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193583108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1193583108
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.885231059
Short name T320
Test name
Test status
Simulation time 300303973 ps
CPU time 19.51 seconds
Started Jul 05 04:32:58 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 216300 kb
Host smart-e4c5d8e7-449a-4321-a978-7c4fddd8b7a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885231059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.885231059
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.886393984
Short name T220
Test name
Test status
Simulation time 174931948 ps
CPU time 4.09 seconds
Started Jul 05 04:33:54 PM PDT 24
Finished Jul 05 04:34:00 PM PDT 24
Peak memory 210468 kb
Host smart-3641a79b-758e-40fe-85f0-7d754c8605f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886393984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.886393984
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1916659914
Short name T51
Test name
Test status
Simulation time 9076899253 ps
CPU time 116.62 seconds
Started Jul 05 04:32:50 PM PDT 24
Finished Jul 05 04:34:50 PM PDT 24
Peak memory 238132 kb
Host smart-99beb7d0-31c5-4150-ad49-dd04a5e2c6e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916659914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1916659914
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2980240351
Short name T354
Test name
Test status
Simulation time 340748726 ps
CPU time 9.37 seconds
Started Jul 05 04:33:10 PM PDT 24
Finished Jul 05 04:33:21 PM PDT 24
Peak memory 211816 kb
Host smart-d9d94098-117f-4990-bc7f-3c62ae39ee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980240351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2980240351
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2966497620
Short name T126
Test name
Test status
Simulation time 99557556 ps
CPU time 5.56 seconds
Started Jul 05 04:33:00 PM PDT 24
Finished Jul 05 04:33:07 PM PDT 24
Peak memory 211384 kb
Host smart-52ac71d6-e1a0-40af-86f7-ccc7c5b97a60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966497620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2966497620
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3278364368
Short name T297
Test name
Test status
Simulation time 20208116369 ps
CPU time 28.79 seconds
Started Jul 05 04:33:08 PM PDT 24
Finished Jul 05 04:33:40 PM PDT 24
Peak memory 214656 kb
Host smart-7abad5b0-8074-4fc0-8d99-2d6ef313880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278364368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3278364368
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2237432767
Short name T192
Test name
Test status
Simulation time 5507332743 ps
CPU time 55.72 seconds
Started Jul 05 04:33:11 PM PDT 24
Finished Jul 05 04:34:10 PM PDT 24
Peak memory 215576 kb
Host smart-a285bbdd-357a-47fd-b403-b3251b7289f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237432767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2237432767
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2384141082
Short name T155
Test name
Test status
Simulation time 2087041452 ps
CPU time 15.57 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 04:34:36 PM PDT 24
Peak memory 211212 kb
Host smart-524e31b0-2e37-4aac-b4e9-46d6751d5bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384141082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2384141082
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2071522954
Short name T187
Test name
Test status
Simulation time 27801975386 ps
CPU time 314.13 seconds
Started Jul 05 04:32:55 PM PDT 24
Finished Jul 05 04:38:12 PM PDT 24
Peak memory 233788 kb
Host smart-27e7c900-3c41-4b8f-9dc5-1573e5a49536
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071522954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2071522954
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2214797217
Short name T168
Test name
Test status
Simulation time 1384498901 ps
CPU time 9.49 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:33:17 PM PDT 24
Peak memory 211920 kb
Host smart-d8237f00-d70f-447b-8ebe-2386f100829d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214797217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2214797217
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4259298006
Short name T154
Test name
Test status
Simulation time 1874677051 ps
CPU time 15.47 seconds
Started Jul 05 04:33:00 PM PDT 24
Finished Jul 05 04:33:18 PM PDT 24
Peak memory 211372 kb
Host smart-247d7dc2-c448-4348-94ae-dd116089b435
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259298006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4259298006
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2031164032
Short name T188
Test name
Test status
Simulation time 186377750 ps
CPU time 10.41 seconds
Started Jul 05 04:32:57 PM PDT 24
Finished Jul 05 04:33:15 PM PDT 24
Peak memory 212128 kb
Host smart-f5f7f9de-5fc5-420c-a8c9-faa9ea1baf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031164032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2031164032
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2120135402
Short name T335
Test name
Test status
Simulation time 3289106307 ps
CPU time 11.35 seconds
Started Jul 05 04:33:00 PM PDT 24
Finished Jul 05 04:33:13 PM PDT 24
Peak memory 211324 kb
Host smart-77f90062-2842-4629-828b-847087b5bb75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120135402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2120135402
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.673126087
Short name T225
Test name
Test status
Simulation time 1379815324 ps
CPU time 11.7 seconds
Started Jul 05 04:33:03 PM PDT 24
Finished Jul 05 04:33:17 PM PDT 24
Peak memory 211284 kb
Host smart-792bc889-9d0f-426b-a747-dbee81618367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673126087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.673126087
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3137262114
Short name T43
Test name
Test status
Simulation time 92201021782 ps
CPU time 236.15 seconds
Started Jul 05 04:33:10 PM PDT 24
Finished Jul 05 04:37:09 PM PDT 24
Peak memory 236652 kb
Host smart-8efd380b-abf4-4214-9022-ba476eebe93b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137262114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3137262114
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.908401781
Short name T233
Test name
Test status
Simulation time 2544170165 ps
CPU time 24.17 seconds
Started Jul 05 04:32:56 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 212204 kb
Host smart-b7003a0e-a1f8-4601-a609-263e57e76951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908401781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.908401781
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2707710576
Short name T261
Test name
Test status
Simulation time 579178696 ps
CPU time 5.22 seconds
Started Jul 05 04:34:23 PM PDT 24
Finished Jul 05 04:34:29 PM PDT 24
Peak memory 211248 kb
Host smart-3cdf43ec-e5d9-45cb-aea0-75b415424edb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2707710576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2707710576
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3010406614
Short name T303
Test name
Test status
Simulation time 3022777791 ps
CPU time 26.03 seconds
Started Jul 05 04:34:10 PM PDT 24
Finished Jul 05 04:34:40 PM PDT 24
Peak memory 213568 kb
Host smart-50dd86b1-ee1f-4a25-9375-a360f87d9c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010406614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3010406614
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.397562759
Short name T328
Test name
Test status
Simulation time 6114635899 ps
CPU time 17.65 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 04:33:42 PM PDT 24
Peak memory 211264 kb
Host smart-2de55276-1d51-4477-9735-9b50894e3f6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397562759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.397562759
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2305036013
Short name T317
Test name
Test status
Simulation time 581015701 ps
CPU time 7.86 seconds
Started Jul 05 04:32:23 PM PDT 24
Finished Jul 05 04:32:31 PM PDT 24
Peak memory 211356 kb
Host smart-d0cea443-3161-48eb-92d2-afce93e13148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305036013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2305036013
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2164157875
Short name T288
Test name
Test status
Simulation time 19133158689 ps
CPU time 195.18 seconds
Started Jul 05 04:32:25 PM PDT 24
Finished Jul 05 04:35:41 PM PDT 24
Peak memory 234716 kb
Host smart-f88c66c1-aeb7-4649-a6c3-0b279b3b1044
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164157875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2164157875
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3146479958
Short name T163
Test name
Test status
Simulation time 25181908019 ps
CPU time 33.1 seconds
Started Jul 05 04:32:35 PM PDT 24
Finished Jul 05 04:33:09 PM PDT 24
Peak memory 212332 kb
Host smart-d23d0c1b-4db2-4ffb-b1fc-e5688b4461a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146479958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3146479958
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1446951788
Short name T212
Test name
Test status
Simulation time 1165786355 ps
CPU time 11.69 seconds
Started Jul 05 04:32:29 PM PDT 24
Finished Jul 05 04:32:41 PM PDT 24
Peak memory 211328 kb
Host smart-255c9415-5711-4392-8bc4-f46954caafa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446951788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1446951788
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1548614813
Short name T27
Test name
Test status
Simulation time 1770635143 ps
CPU time 108.97 seconds
Started Jul 05 04:32:30 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 238136 kb
Host smart-045f1d8a-d8cc-45b0-b2af-d4ec28a5eb57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548614813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1548614813
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2412591165
Short name T84
Test name
Test status
Simulation time 3708153206 ps
CPU time 41.86 seconds
Started Jul 05 04:32:26 PM PDT 24
Finished Jul 05 04:33:08 PM PDT 24
Peak memory 213736 kb
Host smart-a4be5c98-d28a-4b20-b73c-c498535752f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412591165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2412591165
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2415183280
Short name T176
Test name
Test status
Simulation time 5387532272 ps
CPU time 12.96 seconds
Started Jul 05 04:32:40 PM PDT 24
Finished Jul 05 04:32:54 PM PDT 24
Peak memory 211612 kb
Host smart-093b5d2c-7ad5-47d4-b2c0-a5481abc01ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415183280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2415183280
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1206737775
Short name T314
Test name
Test status
Simulation time 96623304916 ps
CPU time 1238.82 seconds
Started Jul 05 04:32:28 PM PDT 24
Finished Jul 05 04:53:08 PM PDT 24
Peak memory 235796 kb
Host smart-6908b9a0-f825-4892-8376-af22880f4dfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206737775 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1206737775
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.4039747665
Short name T143
Test name
Test status
Simulation time 88450213 ps
CPU time 4.26 seconds
Started Jul 05 04:32:52 PM PDT 24
Finished Jul 05 04:33:00 PM PDT 24
Peak memory 211296 kb
Host smart-6632a85b-284c-4216-b36f-a2e49f1c1678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039747665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4039747665
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2998336196
Short name T145
Test name
Test status
Simulation time 36600574491 ps
CPU time 208.29 seconds
Started Jul 05 04:32:58 PM PDT 24
Finished Jul 05 04:36:28 PM PDT 24
Peak memory 212888 kb
Host smart-5ea2ec1e-1039-4c72-98ac-3c0851e49fcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998336196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2998336196
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3091674575
Short name T10
Test name
Test status
Simulation time 8513938764 ps
CPU time 22.01 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:45 PM PDT 24
Peak memory 212128 kb
Host smart-382d6ea9-e852-4dea-b3cd-4ed0095a7ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091674575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3091674575
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1067362890
Short name T182
Test name
Test status
Simulation time 3941339219 ps
CPU time 10.89 seconds
Started Jul 05 04:33:01 PM PDT 24
Finished Jul 05 04:33:15 PM PDT 24
Peak memory 211352 kb
Host smart-85f6295c-31af-4741-bf32-f064812affae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067362890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1067362890
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2010705251
Short name T5
Test name
Test status
Simulation time 16884091610 ps
CPU time 30.8 seconds
Started Jul 05 04:34:07 PM PDT 24
Finished Jul 05 04:34:41 PM PDT 24
Peak memory 214232 kb
Host smart-567ab381-0624-4e2b-be3e-cf0af4500a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010705251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2010705251
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3840824407
Short name T125
Test name
Test status
Simulation time 2425530395 ps
CPU time 24.4 seconds
Started Jul 05 04:32:59 PM PDT 24
Finished Jul 05 04:33:25 PM PDT 24
Peak memory 215184 kb
Host smart-914a3d5c-6744-44dc-a9c3-6995939e0678
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840824407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3840824407
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3087126118
Short name T340
Test name
Test status
Simulation time 5105770702 ps
CPU time 11.76 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:21 PM PDT 24
Peak memory 211400 kb
Host smart-c3ee99b1-8a86-4354-8491-716b19dd373f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087126118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3087126118
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.291211572
Short name T3
Test name
Test status
Simulation time 9607304195 ps
CPU time 170.43 seconds
Started Jul 05 04:33:21 PM PDT 24
Finished Jul 05 04:36:17 PM PDT 24
Peak memory 237992 kb
Host smart-ae915668-b138-4d46-93c0-0067046b5ca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291211572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.291211572
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3822443990
Short name T35
Test name
Test status
Simulation time 1039556268 ps
CPU time 9.3 seconds
Started Jul 05 04:33:00 PM PDT 24
Finished Jul 05 04:33:11 PM PDT 24
Peak memory 211900 kb
Host smart-70f2ecd9-6c7f-4a9c-aa4a-ee7fffbf96bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822443990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3822443990
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1916188843
Short name T132
Test name
Test status
Simulation time 762531258 ps
CPU time 7.89 seconds
Started Jul 05 04:33:03 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 211256 kb
Host smart-afbbae1f-f8ef-4a17-830c-42b8c3ca1db4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916188843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1916188843
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.36115726
Short name T308
Test name
Test status
Simulation time 717121616 ps
CPU time 10.14 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:33:28 PM PDT 24
Peak memory 213116 kb
Host smart-4aff196a-67d5-4cd7-bce9-c7b3b662bdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36115726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.36115726
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3559228487
Short name T85
Test name
Test status
Simulation time 28773799102 ps
CPU time 71.36 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:34:21 PM PDT 24
Peak memory 215992 kb
Host smart-750de7b9-85d7-4fb5-916b-24839678c229
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559228487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3559228487
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1390057128
Short name T357
Test name
Test status
Simulation time 98988830 ps
CPU time 4.23 seconds
Started Jul 05 04:33:25 PM PDT 24
Finished Jul 05 04:33:34 PM PDT 24
Peak memory 211316 kb
Host smart-c1e574be-a968-4df8-99f3-eb4a9d61c872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390057128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1390057128
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2265636416
Short name T251
Test name
Test status
Simulation time 47528264995 ps
CPU time 364.32 seconds
Started Jul 05 04:33:11 PM PDT 24
Finished Jul 05 04:39:19 PM PDT 24
Peak memory 224960 kb
Host smart-b3bb811f-0b67-4e4e-b178-fc9630295c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265636416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2265636416
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2053518127
Short name T135
Test name
Test status
Simulation time 11104565918 ps
CPU time 25.6 seconds
Started Jul 05 04:33:10 PM PDT 24
Finished Jul 05 04:33:38 PM PDT 24
Peak memory 212300 kb
Host smart-e18bbc43-4934-4f26-b488-3a241270547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053518127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2053518127
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4273685827
Short name T186
Test name
Test status
Simulation time 374862504 ps
CPU time 5.56 seconds
Started Jul 05 04:32:58 PM PDT 24
Finished Jul 05 04:33:06 PM PDT 24
Peak memory 211324 kb
Host smart-ab93a129-5c86-4b84-993b-2eae307494ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4273685827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4273685827
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.31739171
Short name T278
Test name
Test status
Simulation time 4335382243 ps
CPU time 33.74 seconds
Started Jul 05 04:33:29 PM PDT 24
Finished Jul 05 04:34:06 PM PDT 24
Peak memory 213436 kb
Host smart-40a4b718-d24e-4de7-9caa-fb35f89df91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31739171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.31739171
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1614270978
Short name T270
Test name
Test status
Simulation time 305666327 ps
CPU time 17.3 seconds
Started Jul 05 04:33:03 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 214452 kb
Host smart-09a7617b-3385-4fa2-a932-61157ffd4d69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614270978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1614270978
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.219259962
Short name T32
Test name
Test status
Simulation time 92737406 ps
CPU time 4.35 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:27 PM PDT 24
Peak memory 211252 kb
Host smart-0fb34f34-c4e1-452d-9e30-0d732662f7a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219259962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.219259962
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1443770238
Short name T226
Test name
Test status
Simulation time 16311309827 ps
CPU time 120.91 seconds
Started Jul 05 04:33:14 PM PDT 24
Finished Jul 05 04:35:19 PM PDT 24
Peak memory 233792 kb
Host smart-48ab233a-f697-4c3c-8ca8-95983a5cd950
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443770238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1443770238
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3746640355
Short name T348
Test name
Test status
Simulation time 173711705 ps
CPU time 9.42 seconds
Started Jul 05 04:33:12 PM PDT 24
Finished Jul 05 04:33:25 PM PDT 24
Peak memory 211952 kb
Host smart-8fb753ae-48a8-4999-a3d7-bdbb28797e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746640355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3746640355
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4015714143
Short name T141
Test name
Test status
Simulation time 348472044 ps
CPU time 6.5 seconds
Started Jul 05 04:33:11 PM PDT 24
Finished Jul 05 04:33:20 PM PDT 24
Peak memory 211372 kb
Host smart-45b102e5-4419-4b12-a982-33e15a42f133
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015714143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4015714143
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2883469734
Short name T191
Test name
Test status
Simulation time 186644979 ps
CPU time 10.06 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:33:17 PM PDT 24
Peak memory 213588 kb
Host smart-03202e63-3d5b-40b9-9d4b-76fc6dd9d13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883469734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2883469734
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2042515834
Short name T129
Test name
Test status
Simulation time 3309732166 ps
CPU time 23.87 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:33 PM PDT 24
Peak memory 214940 kb
Host smart-a1b8603c-53c0-4479-b1b7-46465cdade4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042515834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2042515834
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.34128752
Short name T359
Test name
Test status
Simulation time 154471758861 ps
CPU time 3836.17 seconds
Started Jul 05 04:33:04 PM PDT 24
Finished Jul 05 05:37:03 PM PDT 24
Peak memory 230484 kb
Host smart-18e3090d-a962-4891-b071-6139028b27f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128752 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.34128752
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3507828402
Short name T174
Test name
Test status
Simulation time 1021457307 ps
CPU time 10.65 seconds
Started Jul 05 04:33:03 PM PDT 24
Finished Jul 05 04:33:16 PM PDT 24
Peak memory 211264 kb
Host smart-af02eee2-c8d7-4fb1-af2e-620120a20c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507828402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3507828402
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1736324439
Short name T229
Test name
Test status
Simulation time 6126119085 ps
CPU time 99.18 seconds
Started Jul 05 04:32:57 PM PDT 24
Finished Jul 05 04:34:39 PM PDT 24
Peak memory 234744 kb
Host smart-6342d737-eba5-4982-93c3-ffff7e234484
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736324439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1736324439
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3916983453
Short name T268
Test name
Test status
Simulation time 19234712378 ps
CPU time 29.43 seconds
Started Jul 05 04:33:09 PM PDT 24
Finished Jul 05 04:33:41 PM PDT 24
Peak memory 212300 kb
Host smart-a1bfe802-907d-4c89-b56d-9f39a93cacf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916983453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3916983453
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1021103642
Short name T139
Test name
Test status
Simulation time 137357444 ps
CPU time 6.42 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:16 PM PDT 24
Peak memory 211296 kb
Host smart-a1991c93-2d5e-4187-af18-83c49dd357d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021103642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1021103642
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2189474499
Short name T338
Test name
Test status
Simulation time 3921551080 ps
CPU time 35.87 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:33:44 PM PDT 24
Peak memory 213312 kb
Host smart-f7acee5f-83a2-4e3b-8a6c-3490a01fd8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189474499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2189474499
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.165564276
Short name T232
Test name
Test status
Simulation time 32760522885 ps
CPU time 79.5 seconds
Started Jul 05 04:33:09 PM PDT 24
Finished Jul 05 04:34:31 PM PDT 24
Peak memory 218248 kb
Host smart-fefc754f-e6ab-4841-83ad-ae95a50c19ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165564276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.165564276
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.383072981
Short name T293
Test name
Test status
Simulation time 2062532051 ps
CPU time 16.96 seconds
Started Jul 05 04:33:12 PM PDT 24
Finished Jul 05 04:33:33 PM PDT 24
Peak memory 211316 kb
Host smart-b968a080-26b2-4ebf-ac3c-49279c70181f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383072981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.383072981
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1637684019
Short name T49
Test name
Test status
Simulation time 27458372470 ps
CPU time 34.1 seconds
Started Jul 05 04:33:10 PM PDT 24
Finished Jul 05 04:33:47 PM PDT 24
Peak memory 212288 kb
Host smart-d589e439-7663-4703-9433-15d0819376ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637684019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1637684019
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3463655478
Short name T61
Test name
Test status
Simulation time 1208361821 ps
CPU time 7 seconds
Started Jul 05 04:33:02 PM PDT 24
Finished Jul 05 04:33:12 PM PDT 24
Peak memory 211372 kb
Host smart-64a040d4-ed0b-4220-87b5-0269bdca026f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3463655478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3463655478
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.25033803
Short name T130
Test name
Test status
Simulation time 1313981786 ps
CPU time 14.11 seconds
Started Jul 05 04:33:19 PM PDT 24
Finished Jul 05 04:33:39 PM PDT 24
Peak memory 212996 kb
Host smart-4f980f82-46e4-492d-98dc-7868007750e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25033803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.25033803
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3685416052
Short name T131
Test name
Test status
Simulation time 415468432 ps
CPU time 23.46 seconds
Started Jul 05 04:33:05 PM PDT 24
Finished Jul 05 04:33:31 PM PDT 24
Peak memory 216352 kb
Host smart-6ed23be2-7ce9-4812-8c94-a1c0f8080d73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685416052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3685416052
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2345342674
Short name T54
Test name
Test status
Simulation time 220854630979 ps
CPU time 2120.25 seconds
Started Jul 05 04:33:20 PM PDT 24
Finished Jul 05 05:08:47 PM PDT 24
Peak memory 234592 kb
Host smart-69b81720-fe49-4778-aaa0-9c3613a19514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345342674 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2345342674
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1039082724
Short name T96
Test name
Test status
Simulation time 3443357866 ps
CPU time 9.14 seconds
Started Jul 05 04:33:20 PM PDT 24
Finished Jul 05 04:33:35 PM PDT 24
Peak memory 211396 kb
Host smart-86b7b50a-f865-4616-bb5b-58194cf70578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039082724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1039082724
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2969656815
Short name T158
Test name
Test status
Simulation time 174749470816 ps
CPU time 283.45 seconds
Started Jul 05 04:33:02 PM PDT 24
Finished Jul 05 04:37:48 PM PDT 24
Peak memory 234208 kb
Host smart-23318c99-f88f-43d4-83bc-f3be711b8a54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969656815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2969656815
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2352946764
Short name T164
Test name
Test status
Simulation time 866029220 ps
CPU time 14.96 seconds
Started Jul 05 04:33:08 PM PDT 24
Finished Jul 05 04:33:25 PM PDT 24
Peak memory 211920 kb
Host smart-5c5d9d84-280c-46ee-9732-b46cc0a9bf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352946764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2352946764
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2479444319
Short name T109
Test name
Test status
Simulation time 362247535 ps
CPU time 5.35 seconds
Started Jul 05 04:33:01 PM PDT 24
Finished Jul 05 04:33:09 PM PDT 24
Peak memory 211328 kb
Host smart-e3cba304-1eac-4ff2-b65d-eb2f7dba4a91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2479444319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2479444319
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3560674507
Short name T36
Test name
Test status
Simulation time 6920091467 ps
CPU time 17.66 seconds
Started Jul 05 04:33:15 PM PDT 24
Finished Jul 05 04:33:36 PM PDT 24
Peak memory 214372 kb
Host smart-a6113854-669f-4a2b-a42b-d0d1d88e92c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560674507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3560674507
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1347878323
Short name T210
Test name
Test status
Simulation time 15842044481 ps
CPU time 42.47 seconds
Started Jul 05 04:32:51 PM PDT 24
Finished Jul 05 04:33:37 PM PDT 24
Peak memory 214080 kb
Host smart-a3d04743-38c2-4d6e-b2b6-444a1bcfeb93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347878323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1347878323
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.826345525
Short name T6
Test name
Test status
Simulation time 5133796759 ps
CPU time 11.29 seconds
Started Jul 05 04:33:09 PM PDT 24
Finished Jul 05 04:33:22 PM PDT 24
Peak memory 210388 kb
Host smart-aa23df91-d59e-4379-97e9-2bee70f83960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826345525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.826345525
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4012267120
Short name T273
Test name
Test status
Simulation time 2413993278 ps
CPU time 23.16 seconds
Started Jul 05 04:33:13 PM PDT 24
Finished Jul 05 04:33:40 PM PDT 24
Peak memory 212576 kb
Host smart-a5cb26ae-eb21-4304-84f4-45a823cfcf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012267120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4012267120
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.614502357
Short name T127
Test name
Test status
Simulation time 101461843 ps
CPU time 5.51 seconds
Started Jul 05 04:33:17 PM PDT 24
Finished Jul 05 04:33:28 PM PDT 24
Peak memory 211372 kb
Host smart-c1a09f3d-99aa-4e53-a994-01e585550225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614502357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.614502357
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2409003588
Short name T259
Test name
Test status
Simulation time 2691492785 ps
CPU time 25.33 seconds
Started Jul 05 04:32:57 PM PDT 24
Finished Jul 05 04:33:25 PM PDT 24
Peak memory 212920 kb
Host smart-16016513-d439-48ee-9d60-575846d8d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409003588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2409003588
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3294942798
Short name T326
Test name
Test status
Simulation time 4039716844 ps
CPU time 24.87 seconds
Started Jul 05 04:33:09 PM PDT 24
Finished Jul 05 04:33:37 PM PDT 24
Peak memory 215232 kb
Host smart-9d50abf9-9e57-49e7-ba56-f726edefb67f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294942798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3294942798
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2297541023
Short name T195
Test name
Test status
Simulation time 2410506400 ps
CPU time 10.74 seconds
Started Jul 05 04:33:04 PM PDT 24
Finished Jul 05 04:33:17 PM PDT 24
Peak memory 211332 kb
Host smart-57fb3083-dfd8-4a73-8026-e08c459f397b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297541023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2297541023
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.73988704
Short name T221
Test name
Test status
Simulation time 479425686588 ps
CPU time 250.35 seconds
Started Jul 05 04:33:01 PM PDT 24
Finished Jul 05 04:37:13 PM PDT 24
Peak memory 236744 kb
Host smart-320a0a65-b741-4caa-b1c3-7def2661d3e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73988704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_co
rrupt_sig_fatal_chk.73988704
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.664564770
Short name T323
Test name
Test status
Simulation time 334527906 ps
CPU time 9.61 seconds
Started Jul 05 04:33:04 PM PDT 24
Finished Jul 05 04:33:16 PM PDT 24
Peak memory 211948 kb
Host smart-663649a5-ebfb-480f-a317-2815797b4460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664564770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.664564770
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2577005465
Short name T294
Test name
Test status
Simulation time 542622191 ps
CPU time 8.58 seconds
Started Jul 05 04:33:12 PM PDT 24
Finished Jul 05 04:33:25 PM PDT 24
Peak memory 211400 kb
Host smart-9c9b562e-926b-4226-b81e-6e56dedda76c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577005465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2577005465
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1355737826
Short name T197
Test name
Test status
Simulation time 50822897245 ps
CPU time 33.65 seconds
Started Jul 05 04:33:02 PM PDT 24
Finished Jul 05 04:33:39 PM PDT 24
Peak memory 214184 kb
Host smart-b0851412-da91-44e4-81b4-e018bffc01fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355737826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1355737826
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.568983409
Short name T334
Test name
Test status
Simulation time 18802004397 ps
CPU time 86.08 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:34:35 PM PDT 24
Peak memory 217768 kb
Host smart-177ba235-2706-4ddf-80c0-c579600bd0a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568983409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.568983409
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1637299283
Short name T257
Test name
Test status
Simulation time 115897877 ps
CPU time 4.18 seconds
Started Jul 05 04:33:07 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 211336 kb
Host smart-d9de86bd-2e3e-413c-95a2-714b07623b3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637299283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1637299283
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1701177236
Short name T170
Test name
Test status
Simulation time 115186242754 ps
CPU time 325.59 seconds
Started Jul 05 04:33:10 PM PDT 24
Finished Jul 05 04:38:38 PM PDT 24
Peak memory 237336 kb
Host smart-5e089376-9460-4c72-9460-78b57241f51e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701177236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1701177236
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3381835304
Short name T275
Test name
Test status
Simulation time 3997308821 ps
CPU time 33.18 seconds
Started Jul 05 04:33:16 PM PDT 24
Finished Jul 05 04:33:53 PM PDT 24
Peak memory 211904 kb
Host smart-d2f1d8a4-9dd7-4b35-afe6-5cda7fdf516a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381835304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3381835304
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2352366453
Short name T284
Test name
Test status
Simulation time 5889559261 ps
CPU time 7.38 seconds
Started Jul 05 04:33:02 PM PDT 24
Finished Jul 05 04:33:12 PM PDT 24
Peak memory 211384 kb
Host smart-af3c7e66-3604-4eca-8279-154beac8eb03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352366453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2352366453
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3267523763
Short name T311
Test name
Test status
Simulation time 15045107673 ps
CPU time 28.16 seconds
Started Jul 05 04:33:08 PM PDT 24
Finished Jul 05 04:33:39 PM PDT 24
Peak memory 214148 kb
Host smart-e39b4b35-94ec-4716-abc1-4978ec57afd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267523763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3267523763
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1032251440
Short name T362
Test name
Test status
Simulation time 46115376177 ps
CPU time 155.52 seconds
Started Jul 05 04:33:08 PM PDT 24
Finished Jul 05 04:35:46 PM PDT 24
Peak memory 219360 kb
Host smart-675fc7fc-22ba-4126-ba1c-4faea03d6f31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032251440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1032251440
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.913959800
Short name T58
Test name
Test status
Simulation time 332780916 ps
CPU time 4.35 seconds
Started Jul 05 04:32:24 PM PDT 24
Finished Jul 05 04:32:29 PM PDT 24
Peak memory 211256 kb
Host smart-0543b393-e1a8-4f8d-b302-90ace91e73cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913959800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.913959800
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2014498889
Short name T258
Test name
Test status
Simulation time 3472785351 ps
CPU time 120.28 seconds
Started Jul 05 04:32:40 PM PDT 24
Finished Jul 05 04:34:41 PM PDT 24
Peak memory 212124 kb
Host smart-cc8547e8-59d5-4a92-9f92-585fcc3ca513
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014498889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2014498889
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3084633176
Short name T228
Test name
Test status
Simulation time 1687571557 ps
CPU time 15.02 seconds
Started Jul 05 04:32:28 PM PDT 24
Finished Jul 05 04:32:44 PM PDT 24
Peak memory 211900 kb
Host smart-9f1b6120-6972-4387-a6af-0a2f5d9bb5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084633176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3084633176
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3203935315
Short name T28
Test name
Test status
Simulation time 2219251516 ps
CPU time 17.78 seconds
Started Jul 05 04:32:29 PM PDT 24
Finished Jul 05 04:32:48 PM PDT 24
Peak memory 211348 kb
Host smart-17a0b31c-98b7-4f32-b4b1-95e144727f96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203935315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3203935315
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3527381336
Short name T336
Test name
Test status
Simulation time 185889075 ps
CPU time 10.12 seconds
Started Jul 05 04:32:23 PM PDT 24
Finished Jul 05 04:32:34 PM PDT 24
Peak memory 212148 kb
Host smart-1f12e29c-c85b-4fa4-b8b0-5809bdc36a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527381336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3527381336
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1479007511
Short name T81
Test name
Test status
Simulation time 3792471119 ps
CPU time 37.96 seconds
Started Jul 05 04:32:20 PM PDT 24
Finished Jul 05 04:32:59 PM PDT 24
Peak memory 213600 kb
Host smart-23257ae4-c845-4761-a691-21f4ec837ea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479007511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1479007511
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.834694192
Short name T70
Test name
Test status
Simulation time 6566707584 ps
CPU time 13.65 seconds
Started Jul 05 04:32:19 PM PDT 24
Finished Jul 05 04:32:33 PM PDT 24
Peak memory 211308 kb
Host smart-ba79a560-f358-442a-8f8e-f70fe2afe7ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834694192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.834694192
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4205781993
Short name T42
Test name
Test status
Simulation time 6150943131 ps
CPU time 94.79 seconds
Started Jul 05 04:32:22 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 212640 kb
Host smart-b558a6bc-6048-40d8-9b6e-834b04681fd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205781993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4205781993
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.929759202
Short name T289
Test name
Test status
Simulation time 2108373112 ps
CPU time 20.33 seconds
Started Jul 05 04:37:56 PM PDT 24
Finished Jul 05 04:38:19 PM PDT 24
Peak memory 211908 kb
Host smart-48fbe8c8-8471-43f7-81ab-90230299fbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929759202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.929759202
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2750852576
Short name T101
Test name
Test status
Simulation time 671495239 ps
CPU time 9.24 seconds
Started Jul 05 04:32:32 PM PDT 24
Finished Jul 05 04:32:42 PM PDT 24
Peak memory 211368 kb
Host smart-0504dce7-4337-4142-94ae-b10afbfaa540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750852576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2750852576
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3036122150
Short name T208
Test name
Test status
Simulation time 16448192809 ps
CPU time 22.7 seconds
Started Jul 05 04:32:48 PM PDT 24
Finished Jul 05 04:33:13 PM PDT 24
Peak memory 214272 kb
Host smart-228595f3-ea99-4ebf-9b54-feac04c7b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036122150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3036122150
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1886209589
Short name T291
Test name
Test status
Simulation time 6190941088 ps
CPU time 16.6 seconds
Started Jul 05 04:32:46 PM PDT 24
Finished Jul 05 04:33:05 PM PDT 24
Peak memory 212544 kb
Host smart-a1b2ca1f-798f-4c82-a2fd-ddfb252c0915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886209589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1886209589
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1930638960
Short name T214
Test name
Test status
Simulation time 62622357525 ps
CPU time 311.24 seconds
Started Jul 05 04:32:38 PM PDT 24
Finished Jul 05 04:37:50 PM PDT 24
Peak memory 224704 kb
Host smart-65d0d287-8def-4d7a-ac9b-10bd1774ac46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930638960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1930638960
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2869712312
Short name T95
Test name
Test status
Simulation time 3517643657 ps
CPU time 30.81 seconds
Started Jul 05 04:32:22 PM PDT 24
Finished Jul 05 04:32:54 PM PDT 24
Peak memory 211956 kb
Host smart-6678e790-d2c6-4037-bd52-05c8ba143fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869712312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2869712312
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.312185284
Short name T14
Test name
Test status
Simulation time 11133807660 ps
CPU time 16.65 seconds
Started Jul 05 04:32:42 PM PDT 24
Finished Jul 05 04:33:00 PM PDT 24
Peak memory 211428 kb
Host smart-9e5dfa60-8a45-4b5a-817b-7082719db991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312185284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.312185284
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2908158289
Short name T133
Test name
Test status
Simulation time 1396574699 ps
CPU time 14.82 seconds
Started Jul 05 04:32:28 PM PDT 24
Finished Jul 05 04:32:44 PM PDT 24
Peak memory 213672 kb
Host smart-72d2303a-7dfe-45d4-b136-279c649af8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908158289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2908158289
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1507960289
Short name T361
Test name
Test status
Simulation time 3568650910 ps
CPU time 39.76 seconds
Started Jul 05 04:32:29 PM PDT 24
Finished Jul 05 04:33:10 PM PDT 24
Peak memory 212980 kb
Host smart-989a391e-3a99-412e-bdca-26fa1513a237
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507960289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1507960289
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4176736410
Short name T238
Test name
Test status
Simulation time 347663525 ps
CPU time 4.21 seconds
Started Jul 05 04:32:32 PM PDT 24
Finished Jul 05 04:32:37 PM PDT 24
Peak memory 211336 kb
Host smart-0ea2290d-3247-44b3-8dd2-3c4f4640a3a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176736410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4176736410
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3210651193
Short name T138
Test name
Test status
Simulation time 100463859159 ps
CPU time 137.69 seconds
Started Jul 05 04:32:29 PM PDT 24
Finished Jul 05 04:34:47 PM PDT 24
Peak memory 236816 kb
Host smart-5db39a87-6aa3-4b93-a3c2-2f9ae500bb4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210651193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3210651193
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3119629224
Short name T50
Test name
Test status
Simulation time 5899884979 ps
CPU time 19.23 seconds
Started Jul 05 04:32:28 PM PDT 24
Finished Jul 05 04:32:48 PM PDT 24
Peak memory 212468 kb
Host smart-b224b4ff-552c-4d8c-8fe9-2070745779d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119629224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3119629224
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1366448512
Short name T309
Test name
Test status
Simulation time 436040959 ps
CPU time 6.87 seconds
Started Jul 05 04:32:43 PM PDT 24
Finished Jul 05 04:32:51 PM PDT 24
Peak memory 211292 kb
Host smart-d0988833-22b5-497d-b50a-6b62763ee1bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1366448512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1366448512
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.403230650
Short name T230
Test name
Test status
Simulation time 2639028582 ps
CPU time 24.9 seconds
Started Jul 05 04:32:36 PM PDT 24
Finished Jul 05 04:33:02 PM PDT 24
Peak memory 213816 kb
Host smart-04024aa2-b342-48bf-9657-90bc96cbb2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403230650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.403230650
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2590829802
Short name T337
Test name
Test status
Simulation time 17526588844 ps
CPU time 76.92 seconds
Started Jul 05 04:32:22 PM PDT 24
Finished Jul 05 04:33:39 PM PDT 24
Peak memory 217496 kb
Host smart-521dfe88-9ad8-418b-9cfc-7de8107207fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590829802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2590829802
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3435007308
Short name T349
Test name
Test status
Simulation time 278446901 ps
CPU time 4.27 seconds
Started Jul 05 04:32:53 PM PDT 24
Finished Jul 05 04:33:04 PM PDT 24
Peak memory 211284 kb
Host smart-b2f95cdf-9763-4bf6-8442-0661009d80e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435007308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3435007308
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1556478039
Short name T39
Test name
Test status
Simulation time 492984187292 ps
CPU time 447.03 seconds
Started Jul 05 04:32:36 PM PDT 24
Finished Jul 05 04:40:04 PM PDT 24
Peak memory 212580 kb
Host smart-97f36078-1fc0-41a9-a58b-7ca424665a1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556478039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1556478039
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.781222675
Short name T299
Test name
Test status
Simulation time 519156116 ps
CPU time 13.12 seconds
Started Jul 05 04:32:42 PM PDT 24
Finished Jul 05 04:32:56 PM PDT 24
Peak memory 211976 kb
Host smart-433a1236-f7a4-45b8-8079-301971e7f1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781222675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.781222675
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1024034323
Short name T235
Test name
Test status
Simulation time 869627827 ps
CPU time 5.77 seconds
Started Jul 05 04:32:42 PM PDT 24
Finished Jul 05 04:32:49 PM PDT 24
Peak memory 211336 kb
Host smart-4c34d022-75a3-4ce3-8357-19819d926539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024034323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1024034323
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2945837113
Short name T166
Test name
Test status
Simulation time 1003612675 ps
CPU time 9.76 seconds
Started Jul 05 04:32:34 PM PDT 24
Finished Jul 05 04:32:45 PM PDT 24
Peak memory 213648 kb
Host smart-ecde692d-2831-441c-bafe-2b3fc432eea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945837113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2945837113
Directory /workspace/9.rom_ctrl_smoke/latest
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