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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 96.89 91.99 97.67 100.00 98.28 97.30 99.07


Total test records in report: 465
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T302 /workspace/coverage/default/40.rom_ctrl_stress_all.1044035709 Jul 06 04:51:18 PM PDT 24 Jul 06 04:51:47 PM PDT 24 3379682868 ps
T303 /workspace/coverage/default/23.rom_ctrl_stress_all.108735965 Jul 06 04:50:58 PM PDT 24 Jul 06 04:51:52 PM PDT 24 5498850903 ps
T304 /workspace/coverage/default/2.rom_ctrl_stress_all.3539056935 Jul 06 04:50:37 PM PDT 24 Jul 06 04:51:22 PM PDT 24 5367572399 ps
T305 /workspace/coverage/default/29.rom_ctrl_stress_all.3634434102 Jul 06 04:51:02 PM PDT 24 Jul 06 04:51:23 PM PDT 24 8923760215 ps
T306 /workspace/coverage/default/18.rom_ctrl_alert_test.1537926732 Jul 06 04:50:45 PM PDT 24 Jul 06 04:51:01 PM PDT 24 12027034400 ps
T307 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.978114875 Jul 06 04:51:22 PM PDT 24 Jul 06 04:51:33 PM PDT 24 3610980377 ps
T308 /workspace/coverage/default/23.rom_ctrl_alert_test.2149967819 Jul 06 04:50:43 PM PDT 24 Jul 06 04:50:51 PM PDT 24 1756474324 ps
T309 /workspace/coverage/default/37.rom_ctrl_smoke.3529470952 Jul 06 04:51:20 PM PDT 24 Jul 06 04:51:53 PM PDT 24 12199281313 ps
T310 /workspace/coverage/default/4.rom_ctrl_stress_all.2281636042 Jul 06 04:50:35 PM PDT 24 Jul 06 04:50:42 PM PDT 24 110489843 ps
T311 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2042984244 Jul 06 04:51:19 PM PDT 24 Jul 06 04:53:35 PM PDT 24 9682819390 ps
T312 /workspace/coverage/default/7.rom_ctrl_smoke.1260767283 Jul 06 04:50:42 PM PDT 24 Jul 06 04:51:00 PM PDT 24 4870350091 ps
T313 /workspace/coverage/default/13.rom_ctrl_alert_test.1489677021 Jul 06 04:50:57 PM PDT 24 Jul 06 04:51:03 PM PDT 24 343886273 ps
T314 /workspace/coverage/default/45.rom_ctrl_stress_all.1841521425 Jul 06 04:51:23 PM PDT 24 Jul 06 04:51:40 PM PDT 24 310824837 ps
T315 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4239760224 Jul 06 04:50:47 PM PDT 24 Jul 06 04:56:34 PM PDT 24 142958390631 ps
T316 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3746464060 Jul 06 04:51:10 PM PDT 24 Jul 06 04:57:30 PM PDT 24 46089328014 ps
T317 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2939205952 Jul 06 04:50:36 PM PDT 24 Jul 06 04:50:55 PM PDT 24 2358117693 ps
T318 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3345594033 Jul 06 04:50:52 PM PDT 24 Jul 06 04:51:11 PM PDT 24 5799169915 ps
T319 /workspace/coverage/default/20.rom_ctrl_alert_test.155234060 Jul 06 04:50:59 PM PDT 24 Jul 06 04:51:03 PM PDT 24 346261225 ps
T320 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.277741739 Jul 06 04:51:09 PM PDT 24 Jul 06 04:51:22 PM PDT 24 4626300215 ps
T321 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3972194825 Jul 06 04:50:41 PM PDT 24 Jul 06 04:51:02 PM PDT 24 1647282091 ps
T322 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3339804708 Jul 06 04:51:17 PM PDT 24 Jul 06 04:51:33 PM PDT 24 1979220871 ps
T323 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2859031848 Jul 06 04:51:24 PM PDT 24 Jul 06 04:51:45 PM PDT 24 11065491594 ps
T324 /workspace/coverage/default/28.rom_ctrl_alert_test.1568185455 Jul 06 04:51:05 PM PDT 24 Jul 06 04:51:12 PM PDT 24 1547941930 ps
T325 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4046617897 Jul 06 04:51:07 PM PDT 24 Jul 06 04:51:14 PM PDT 24 182977183 ps
T326 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1017609693 Jul 06 04:50:37 PM PDT 24 Jul 06 04:52:53 PM PDT 24 2174739441 ps
T327 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.614857736 Jul 06 04:50:51 PM PDT 24 Jul 06 04:51:01 PM PDT 24 2428987894 ps
T328 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2464122535 Jul 06 04:51:25 PM PDT 24 Jul 06 04:51:35 PM PDT 24 804853756 ps
T329 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2335418065 Jul 06 04:50:41 PM PDT 24 Jul 06 05:19:21 PM PDT 24 182245988204 ps
T330 /workspace/coverage/default/27.rom_ctrl_stress_all.4031095493 Jul 06 04:50:55 PM PDT 24 Jul 06 04:52:12 PM PDT 24 29872356459 ps
T331 /workspace/coverage/default/29.rom_ctrl_alert_test.2453283768 Jul 06 04:51:03 PM PDT 24 Jul 06 04:51:17 PM PDT 24 5680149462 ps
T332 /workspace/coverage/default/20.rom_ctrl_stress_all.451900156 Jul 06 04:50:57 PM PDT 24 Jul 06 04:52:06 PM PDT 24 26654022303 ps
T333 /workspace/coverage/default/34.rom_ctrl_alert_test.3891004577 Jul 06 04:51:07 PM PDT 24 Jul 06 04:51:18 PM PDT 24 2928788094 ps
T334 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1729052132 Jul 06 04:50:44 PM PDT 24 Jul 06 04:51:12 PM PDT 24 5814927230 ps
T335 /workspace/coverage/default/8.rom_ctrl_stress_all.1891951227 Jul 06 04:50:34 PM PDT 24 Jul 06 04:51:47 PM PDT 24 6620041343 ps
T336 /workspace/coverage/default/35.rom_ctrl_alert_test.2036431696 Jul 06 04:51:08 PM PDT 24 Jul 06 04:51:13 PM PDT 24 88842956 ps
T337 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.402841028 Jul 06 04:50:58 PM PDT 24 Jul 06 04:51:07 PM PDT 24 364130995 ps
T338 /workspace/coverage/default/31.rom_ctrl_alert_test.3781325864 Jul 06 04:50:59 PM PDT 24 Jul 06 04:51:15 PM PDT 24 3933383469 ps
T339 /workspace/coverage/default/7.rom_ctrl_stress_all.2663310099 Jul 06 04:50:50 PM PDT 24 Jul 06 04:51:11 PM PDT 24 4143349430 ps
T340 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1987308345 Jul 06 04:50:52 PM PDT 24 Jul 06 04:51:43 PM PDT 24 1391655368 ps
T341 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3302337357 Jul 06 04:50:36 PM PDT 24 Jul 06 04:51:53 PM PDT 24 2276619013 ps
T342 /workspace/coverage/default/47.rom_ctrl_smoke.2058820548 Jul 06 04:51:20 PM PDT 24 Jul 06 04:51:40 PM PDT 24 8737995891 ps
T343 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2276238483 Jul 06 04:51:03 PM PDT 24 Jul 06 04:51:11 PM PDT 24 267402083 ps
T344 /workspace/coverage/default/19.rom_ctrl_smoke.4011446426 Jul 06 04:50:59 PM PDT 24 Jul 06 04:51:10 PM PDT 24 185875394 ps
T345 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.558187982 Jul 06 04:50:38 PM PDT 24 Jul 06 04:50:55 PM PDT 24 911971648 ps
T346 /workspace/coverage/default/18.rom_ctrl_stress_all.3180986443 Jul 06 04:50:52 PM PDT 24 Jul 06 04:51:42 PM PDT 24 4718180885 ps
T347 /workspace/coverage/default/3.rom_ctrl_smoke.974543494 Jul 06 04:50:37 PM PDT 24 Jul 06 04:51:14 PM PDT 24 3900379905 ps
T348 /workspace/coverage/default/25.rom_ctrl_stress_all.285507727 Jul 06 04:50:51 PM PDT 24 Jul 06 04:51:24 PM PDT 24 4003637445 ps
T349 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.650624728 Jul 06 04:50:41 PM PDT 24 Jul 06 04:51:03 PM PDT 24 2649706821 ps
T350 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.455898316 Jul 06 04:51:06 PM PDT 24 Jul 06 04:53:41 PM PDT 24 25467295096 ps
T351 /workspace/coverage/default/27.rom_ctrl_smoke.3306497300 Jul 06 04:51:13 PM PDT 24 Jul 06 04:51:35 PM PDT 24 7960666530 ps
T352 /workspace/coverage/default/37.rom_ctrl_alert_test.402178935 Jul 06 04:51:15 PM PDT 24 Jul 06 04:51:27 PM PDT 24 5349735574 ps
T353 /workspace/coverage/default/42.rom_ctrl_stress_all.1709825987 Jul 06 04:51:23 PM PDT 24 Jul 06 04:52:35 PM PDT 24 8622615895 ps
T354 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2815309799 Jul 06 04:50:55 PM PDT 24 Jul 06 04:51:22 PM PDT 24 2987603858 ps
T355 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4090756485 Jul 06 04:51:20 PM PDT 24 Jul 06 04:54:27 PM PDT 24 67859618440 ps
T356 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.576678980 Jul 06 04:51:01 PM PDT 24 Jul 06 05:03:18 PM PDT 24 18137642521 ps
T357 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3656994431 Jul 06 04:51:00 PM PDT 24 Jul 06 04:51:17 PM PDT 24 4897459586 ps
T358 /workspace/coverage/default/31.rom_ctrl_smoke.3500310999 Jul 06 04:50:55 PM PDT 24 Jul 06 04:51:06 PM PDT 24 669308674 ps
T359 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1849113720 Jul 06 04:51:02 PM PDT 24 Jul 06 04:51:12 PM PDT 24 2365129039 ps
T360 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.394537738 Jul 06 04:50:35 PM PDT 24 Jul 06 04:54:16 PM PDT 24 31324796826 ps
T361 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.563289165 Jul 06 04:51:20 PM PDT 24 Jul 06 04:51:45 PM PDT 24 2528880534 ps
T362 /workspace/coverage/default/35.rom_ctrl_smoke.939944686 Jul 06 04:51:09 PM PDT 24 Jul 06 04:51:30 PM PDT 24 3477396973 ps
T363 /workspace/coverage/default/34.rom_ctrl_stress_all.2386907382 Jul 06 04:51:10 PM PDT 24 Jul 06 04:51:31 PM PDT 24 308891881 ps
T364 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.343174821 Jul 06 04:50:37 PM PDT 24 Jul 06 04:54:17 PM PDT 24 90874786131 ps
T365 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4109468560 Jul 06 04:50:43 PM PDT 24 Jul 06 04:51:01 PM PDT 24 3037997810 ps
T366 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.584736936 Jul 06 04:51:06 PM PDT 24 Jul 06 04:55:27 PM PDT 24 232046245625 ps
T367 /workspace/coverage/default/46.rom_ctrl_smoke.4008200719 Jul 06 04:51:21 PM PDT 24 Jul 06 04:51:32 PM PDT 24 618007436 ps
T368 /workspace/coverage/default/4.rom_ctrl_smoke.4021222529 Jul 06 04:50:32 PM PDT 24 Jul 06 04:51:07 PM PDT 24 3374654064 ps
T369 /workspace/coverage/default/49.rom_ctrl_smoke.3058443370 Jul 06 04:51:33 PM PDT 24 Jul 06 04:52:12 PM PDT 24 12006665666 ps
T370 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4049514510 Jul 06 04:50:52 PM PDT 24 Jul 06 04:51:01 PM PDT 24 3040474331 ps
T371 /workspace/coverage/default/3.rom_ctrl_stress_all.3598294802 Jul 06 04:50:41 PM PDT 24 Jul 06 04:51:58 PM PDT 24 39596393295 ps
T67 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3718200357 Jul 06 04:51:43 PM PDT 24 Jul 06 04:51:54 PM PDT 24 1153958736 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3369859383 Jul 06 04:51:42 PM PDT 24 Jul 06 04:51:57 PM PDT 24 2983265791 ps
T69 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2609672531 Jul 06 04:51:28 PM PDT 24 Jul 06 04:51:43 PM PDT 24 8415422289 ps
T372 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.911863235 Jul 06 04:51:46 PM PDT 24 Jul 06 04:51:56 PM PDT 24 1673131424 ps
T373 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1581437625 Jul 06 04:51:46 PM PDT 24 Jul 06 04:52:04 PM PDT 24 7002029600 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1218772388 Jul 06 04:51:27 PM PDT 24 Jul 06 04:51:42 PM PDT 24 1775943409 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2343877088 Jul 06 04:51:58 PM PDT 24 Jul 06 04:52:15 PM PDT 24 4279144327 ps
T73 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.338506995 Jul 06 04:51:46 PM PDT 24 Jul 06 04:52:43 PM PDT 24 6640781603 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1206565645 Jul 06 04:51:53 PM PDT 24 Jul 06 04:52:10 PM PDT 24 8242395943 ps
T75 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.138729422 Jul 06 04:51:49 PM PDT 24 Jul 06 04:51:57 PM PDT 24 1108946604 ps
T76 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3406791815 Jul 06 04:51:45 PM PDT 24 Jul 06 04:51:51 PM PDT 24 89149134 ps
T64 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1273775865 Jul 06 04:51:50 PM PDT 24 Jul 06 04:52:38 PM PDT 24 2151806504 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1306274253 Jul 06 04:51:35 PM PDT 24 Jul 06 04:51:48 PM PDT 24 2770835009 ps
T377 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.147138370 Jul 06 04:51:51 PM PDT 24 Jul 06 04:52:03 PM PDT 24 1733344075 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4242007395 Jul 06 04:51:40 PM PDT 24 Jul 06 04:51:51 PM PDT 24 3904639610 ps
T77 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3774103531 Jul 06 04:52:02 PM PDT 24 Jul 06 04:52:07 PM PDT 24 348345070 ps
T378 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3252117585 Jul 06 04:51:43 PM PDT 24 Jul 06 04:52:00 PM PDT 24 4498791355 ps
T106 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.803830187 Jul 06 04:51:53 PM PDT 24 Jul 06 04:51:58 PM PDT 24 86288642 ps
T107 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.742264721 Jul 06 04:51:49 PM PDT 24 Jul 06 04:52:36 PM PDT 24 13588312357 ps
T65 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.889550490 Jul 06 04:51:46 PM PDT 24 Jul 06 04:52:28 PM PDT 24 3790096507 ps
T66 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4257492205 Jul 06 04:51:46 PM PDT 24 Jul 06 04:52:24 PM PDT 24 330713368 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3918791823 Jul 06 04:51:35 PM PDT 24 Jul 06 04:51:40 PM PDT 24 333224632 ps
T380 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3511327251 Jul 06 04:51:44 PM PDT 24 Jul 06 04:51:56 PM PDT 24 4732653720 ps
T381 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.754017434 Jul 06 04:51:40 PM PDT 24 Jul 06 04:51:58 PM PDT 24 1920143742 ps
T382 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2153266594 Jul 06 04:51:51 PM PDT 24 Jul 06 04:51:56 PM PDT 24 1142115788 ps
T99 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1228799353 Jul 06 04:51:45 PM PDT 24 Jul 06 04:52:01 PM PDT 24 1991136999 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2374221431 Jul 06 04:51:45 PM PDT 24 Jul 06 04:52:00 PM PDT 24 2197582003 ps
T78 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3384282036 Jul 06 04:51:39 PM PDT 24 Jul 06 04:51:51 PM PDT 24 1392072307 ps
T79 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1852173836 Jul 06 04:51:27 PM PDT 24 Jul 06 04:52:36 PM PDT 24 17490495531 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4050659545 Jul 06 04:51:51 PM PDT 24 Jul 06 04:52:07 PM PDT 24 7303015573 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2553580892 Jul 06 04:51:39 PM PDT 24 Jul 06 04:51:44 PM PDT 24 122655352 ps
T108 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1592034281 Jul 06 04:51:51 PM PDT 24 Jul 06 04:52:52 PM PDT 24 14797775769 ps
T100 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2722687103 Jul 06 04:51:48 PM PDT 24 Jul 06 04:52:08 PM PDT 24 433297222 ps
T80 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1995607272 Jul 06 04:51:40 PM PDT 24 Jul 06 04:51:52 PM PDT 24 1219098336 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3913894675 Jul 06 04:51:33 PM PDT 24 Jul 06 04:51:44 PM PDT 24 4099602720 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1813486393 Jul 06 04:51:36 PM PDT 24 Jul 06 04:51:43 PM PDT 24 332571919 ps
T114 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.345483360 Jul 06 04:51:52 PM PDT 24 Jul 06 04:52:37 PM PDT 24 6542289477 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3240761294 Jul 06 04:51:35 PM PDT 24 Jul 06 04:51:46 PM PDT 24 633185188 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.944640253 Jul 06 04:51:39 PM PDT 24 Jul 06 04:51:47 PM PDT 24 1971626788 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3292650158 Jul 06 04:51:40 PM PDT 24 Jul 06 04:51:52 PM PDT 24 1234290746 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.184647109 Jul 06 04:51:45 PM PDT 24 Jul 06 04:51:58 PM PDT 24 1246786551 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1794261567 Jul 06 04:51:35 PM PDT 24 Jul 06 04:51:48 PM PDT 24 12968098532 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3281474487 Jul 06 04:51:39 PM PDT 24 Jul 06 04:51:50 PM PDT 24 1105093825 ps
T112 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3328030784 Jul 06 04:51:43 PM PDT 24 Jul 06 04:52:57 PM PDT 24 5298586709 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.883361957 Jul 06 04:51:44 PM PDT 24 Jul 06 04:52:02 PM PDT 24 3417353330 ps
T394 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2212487008 Jul 06 04:51:50 PM PDT 24 Jul 06 04:52:01 PM PDT 24 2126067772 ps
T102 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3590296125 Jul 06 04:51:55 PM PDT 24 Jul 06 04:52:09 PM PDT 24 1693297258 ps
T103 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1516992282 Jul 06 04:51:50 PM PDT 24 Jul 06 04:52:04 PM PDT 24 3246419286 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3952098755 Jul 06 04:51:40 PM PDT 24 Jul 06 04:51:54 PM PDT 24 1156919422 ps
T82 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.193238862 Jul 06 04:51:44 PM PDT 24 Jul 06 04:51:56 PM PDT 24 1023989773 ps
T104 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.90234430 Jul 06 04:51:53 PM PDT 24 Jul 06 04:52:10 PM PDT 24 2095149125 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1205956402 Jul 06 04:51:31 PM PDT 24 Jul 06 04:51:41 PM PDT 24 2673272007 ps
T88 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2340918213 Jul 06 04:51:48 PM PDT 24 Jul 06 04:51:53 PM PDT 24 101415284 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3928997884 Jul 06 04:51:37 PM PDT 24 Jul 06 04:51:53 PM PDT 24 6170540465 ps
T105 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.720429965 Jul 06 04:51:57 PM PDT 24 Jul 06 04:52:12 PM PDT 24 6690918655 ps
T89 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.269970568 Jul 06 04:51:39 PM PDT 24 Jul 06 04:51:55 PM PDT 24 8818968798 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.473808185 Jul 06 04:51:41 PM PDT 24 Jul 06 04:51:47 PM PDT 24 210764825 ps
T398 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1394681993 Jul 06 04:51:40 PM PDT 24 Jul 06 04:51:48 PM PDT 24 383285058 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.724047695 Jul 06 04:52:31 PM PDT 24 Jul 06 04:53:25 PM PDT 24 10832233773 ps
T115 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2534080592 Jul 06 04:51:52 PM PDT 24 Jul 06 04:53:08 PM PDT 24 6777468237 ps
T399 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2644841275 Jul 06 04:51:40 PM PDT 24 Jul 06 04:51:46 PM PDT 24 400040540 ps
T400 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3548944506 Jul 06 04:51:54 PM PDT 24 Jul 06 04:51:59 PM PDT 24 100339944 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2161182777 Jul 06 04:51:47 PM PDT 24 Jul 06 04:52:03 PM PDT 24 2873709957 ps
T402 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3054499775 Jul 06 04:51:55 PM PDT 24 Jul 06 04:52:01 PM PDT 24 103831510 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1200678570 Jul 06 04:51:41 PM PDT 24 Jul 06 04:51:46 PM PDT 24 431912773 ps
T404 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.489975986 Jul 06 04:51:56 PM PDT 24 Jul 06 04:53:00 PM PDT 24 9306324465 ps
T405 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.349654437 Jul 06 04:51:45 PM PDT 24 Jul 06 04:51:58 PM PDT 24 2445998100 ps
T406 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1938396152 Jul 06 04:51:44 PM PDT 24 Jul 06 04:51:51 PM PDT 24 822489465 ps
T116 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.379584821 Jul 06 04:51:45 PM PDT 24 Jul 06 04:52:27 PM PDT 24 1175503946 ps
T113 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.985769308 Jul 06 04:52:48 PM PDT 24 Jul 06 04:54:01 PM PDT 24 3057246621 ps
T117 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1186510918 Jul 06 04:51:57 PM PDT 24 Jul 06 04:52:37 PM PDT 24 2329600203 ps
T407 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3806789279 Jul 06 04:51:52 PM PDT 24 Jul 06 04:52:06 PM PDT 24 3077845612 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1977289033 Jul 06 04:51:52 PM PDT 24 Jul 06 04:52:08 PM PDT 24 1859832689 ps
T409 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1070248049 Jul 06 04:51:47 PM PDT 24 Jul 06 04:52:05 PM PDT 24 8402121682 ps
T410 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.936693038 Jul 06 04:51:52 PM PDT 24 Jul 06 04:52:20 PM PDT 24 569612721 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3758621477 Jul 06 04:51:36 PM PDT 24 Jul 06 04:51:50 PM PDT 24 2780466722 ps
T120 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3832621017 Jul 06 04:51:39 PM PDT 24 Jul 06 04:52:56 PM PDT 24 3672446026 ps
T412 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2811842926 Jul 06 04:51:51 PM PDT 24 Jul 06 04:52:10 PM PDT 24 1502255130 ps
T118 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.640825633 Jul 06 04:51:54 PM PDT 24 Jul 06 04:53:03 PM PDT 24 1148809317 ps
T413 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1370136827 Jul 06 04:51:57 PM PDT 24 Jul 06 04:52:06 PM PDT 24 2419302041 ps
T122 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4005752677 Jul 06 04:51:40 PM PDT 24 Jul 06 04:52:17 PM PDT 24 606025832 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3280100648 Jul 06 04:51:33 PM PDT 24 Jul 06 04:51:41 PM PDT 24 177135871 ps
T414 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1345501764 Jul 06 04:51:53 PM PDT 24 Jul 06 04:52:01 PM PDT 24 304882610 ps
T121 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4239031132 Jul 06 04:51:49 PM PDT 24 Jul 06 04:52:58 PM PDT 24 1467222274 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1084440780 Jul 06 04:51:53 PM PDT 24 Jul 06 04:52:06 PM PDT 24 4022747900 ps
T91 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2270723286 Jul 06 04:51:48 PM PDT 24 Jul 06 04:52:55 PM PDT 24 8899882266 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4156906263 Jul 06 04:51:35 PM PDT 24 Jul 06 04:51:39 PM PDT 24 178523878 ps
T417 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1599963140 Jul 06 04:51:44 PM PDT 24 Jul 06 04:52:00 PM PDT 24 7006510800 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1730228030 Jul 06 04:51:33 PM PDT 24 Jul 06 04:52:01 PM PDT 24 4502522613 ps
T418 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2356866224 Jul 06 04:52:21 PM PDT 24 Jul 06 04:52:29 PM PDT 24 600415440 ps
T419 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.221449066 Jul 06 04:51:45 PM PDT 24 Jul 06 04:52:07 PM PDT 24 2051119554 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.976145023 Jul 06 04:51:34 PM PDT 24 Jul 06 04:51:46 PM PDT 24 1030010619 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1152279980 Jul 06 04:51:41 PM PDT 24 Jul 06 04:53:03 PM PDT 24 39602649038 ps
T422 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3903085644 Jul 06 04:51:41 PM PDT 24 Jul 06 04:51:54 PM PDT 24 2381778339 ps
T423 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3101066121 Jul 06 04:51:44 PM PDT 24 Jul 06 04:52:01 PM PDT 24 13290276056 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3051600843 Jul 06 04:51:41 PM PDT 24 Jul 06 04:51:54 PM PDT 24 2842173137 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1152494349 Jul 06 04:51:41 PM PDT 24 Jul 06 04:51:51 PM PDT 24 247925540 ps
T426 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2345472976 Jul 06 04:51:49 PM PDT 24 Jul 06 04:51:55 PM PDT 24 96853948 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1007335960 Jul 06 04:51:41 PM PDT 24 Jul 06 04:51:58 PM PDT 24 7605495527 ps
T428 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3676239655 Jul 06 04:51:40 PM PDT 24 Jul 06 04:52:44 PM PDT 24 10830421215 ps
T429 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4229633980 Jul 06 04:51:54 PM PDT 24 Jul 06 04:51:59 PM PDT 24 720782284 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3200563131 Jul 06 04:51:34 PM PDT 24 Jul 06 04:51:41 PM PDT 24 662115312 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.143020393 Jul 06 04:51:42 PM PDT 24 Jul 06 04:51:52 PM PDT 24 1450075896 ps
T431 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.635430938 Jul 06 04:51:51 PM PDT 24 Jul 06 04:52:06 PM PDT 24 1895320059 ps
T432 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1048797058 Jul 06 04:51:44 PM PDT 24 Jul 06 04:51:55 PM PDT 24 1625891126 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2571844508 Jul 06 04:51:35 PM PDT 24 Jul 06 04:51:45 PM PDT 24 1571588537 ps
T97 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2606531852 Jul 06 04:51:44 PM PDT 24 Jul 06 04:52:12 PM PDT 24 2005759398 ps
T434 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.849483116 Jul 06 04:51:44 PM PDT 24 Jul 06 04:52:01 PM PDT 24 1860523287 ps
T435 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.980042109 Jul 06 04:51:47 PM PDT 24 Jul 06 04:52:03 PM PDT 24 1641312046 ps
T436 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3411406965 Jul 06 04:51:48 PM PDT 24 Jul 06 04:51:57 PM PDT 24 3082039581 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.70903832 Jul 06 04:51:45 PM PDT 24 Jul 06 04:51:55 PM PDT 24 2913794849 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3960730050 Jul 06 04:51:41 PM PDT 24 Jul 06 04:51:53 PM PDT 24 3468130385 ps
T438 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2998995949 Jul 06 04:51:54 PM PDT 24 Jul 06 04:52:00 PM PDT 24 1786133413 ps
T439 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.312313221 Jul 06 04:51:50 PM PDT 24 Jul 06 04:52:08 PM PDT 24 2040773909 ps
T440 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2978779421 Jul 06 04:51:48 PM PDT 24 Jul 06 04:51:55 PM PDT 24 258395005 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.626642472 Jul 06 04:51:34 PM PDT 24 Jul 06 04:51:43 PM PDT 24 1259848132 ps
T96 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4174697143 Jul 06 04:51:36 PM PDT 24 Jul 06 04:51:55 PM PDT 24 3002977558 ps
T442 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.675085426 Jul 06 04:51:50 PM PDT 24 Jul 06 04:51:54 PM PDT 24 101401004 ps
T443 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.716448925 Jul 06 04:51:40 PM PDT 24 Jul 06 04:51:58 PM PDT 24 370780773 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.907310233 Jul 06 04:51:40 PM PDT 24 Jul 06 04:51:59 PM PDT 24 1909162886 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3671883232 Jul 06 04:51:40 PM PDT 24 Jul 06 04:52:21 PM PDT 24 3356689553 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3969826921 Jul 06 04:51:36 PM PDT 24 Jul 06 04:51:48 PM PDT 24 2214732769 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1844891850 Jul 06 04:51:41 PM PDT 24 Jul 06 04:52:18 PM PDT 24 151583305 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1383869662 Jul 06 04:51:41 PM PDT 24 Jul 06 04:51:51 PM PDT 24 290173365 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1566919492 Jul 06 04:51:32 PM PDT 24 Jul 06 04:51:45 PM PDT 24 1526998410 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2081322680 Jul 06 04:51:28 PM PDT 24 Jul 06 04:52:45 PM PDT 24 1828409253 ps
T451 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3720704949 Jul 06 04:51:45 PM PDT 24 Jul 06 04:52:24 PM PDT 24 1653076710 ps
T119 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1975916172 Jul 06 04:51:44 PM PDT 24 Jul 06 04:52:31 PM PDT 24 7815860156 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1924138420 Jul 06 04:51:35 PM PDT 24 Jul 06 04:51:48 PM PDT 24 1290048384 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2625172285 Jul 06 04:51:34 PM PDT 24 Jul 06 04:51:42 PM PDT 24 846307873 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2605556983 Jul 06 04:51:25 PM PDT 24 Jul 06 04:51:35 PM PDT 24 782809303 ps
T455 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.60977038 Jul 06 04:51:58 PM PDT 24 Jul 06 04:52:17 PM PDT 24 8317287908 ps
T111 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2904549707 Jul 06 04:51:40 PM PDT 24 Jul 06 04:52:00 PM PDT 24 736400767 ps
T456 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3349589190 Jul 06 04:51:50 PM PDT 24 Jul 06 04:52:08 PM PDT 24 2797786520 ps
T457 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1111639438 Jul 06 04:51:33 PM PDT 24 Jul 06 04:51:44 PM PDT 24 556887688 ps
T458 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4242821004 Jul 06 04:51:48 PM PDT 24 Jul 06 04:51:59 PM PDT 24 4892846343 ps
T123 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3267521619 Jul 06 04:51:49 PM PDT 24 Jul 06 04:53:08 PM PDT 24 10807682441 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.633681455 Jul 06 04:51:25 PM PDT 24 Jul 06 04:51:35 PM PDT 24 3585161728 ps
T460 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2939604418 Jul 06 04:51:26 PM PDT 24 Jul 06 04:51:41 PM PDT 24 1354817901 ps
T461 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1527970614 Jul 06 04:51:49 PM PDT 24 Jul 06 04:52:28 PM PDT 24 6262245659 ps
T462 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2615153360 Jul 06 04:51:41 PM PDT 24 Jul 06 04:52:19 PM PDT 24 3141713454 ps
T95 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3652999650 Jul 06 04:51:52 PM PDT 24 Jul 06 04:52:49 PM PDT 24 13094065321 ps
T463 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3215722411 Jul 06 04:51:33 PM PDT 24 Jul 06 04:52:16 PM PDT 24 5126864478 ps
T464 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4035492658 Jul 06 04:51:38 PM PDT 24 Jul 06 04:51:43 PM PDT 24 348155387 ps
T465 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.771230808 Jul 06 04:51:33 PM PDT 24 Jul 06 04:51:42 PM PDT 24 3040938279 ps

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.738911136
Short name T3
Test name
Test status
Simulation time 91825511548 ps
CPU time 339.97 seconds
Started Jul 06 04:51:21 PM PDT 24
Finished Jul 06 04:57:01 PM PDT 24
Peak memory 234172 kb
Host smart-9148b28e-5c12-4cff-b620-eefea41cce06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738911136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.738911136
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2102488383
Short name T15
Test name
Test status
Simulation time 88146491341 ps
CPU time 3585.12 seconds
Started Jul 06 04:50:52 PM PDT 24
Finished Jul 06 05:50:38 PM PDT 24
Peak memory 252216 kb
Host smart-924b409a-5013-4d4d-84c6-da307bf1c0eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102488383 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2102488383
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3482339899
Short name T20
Test name
Test status
Simulation time 11039364038 ps
CPU time 36.78 seconds
Started Jul 06 04:50:59 PM PDT 24
Finished Jul 06 04:51:36 PM PDT 24
Peak memory 217520 kb
Host smart-7314ebed-ddc1-4f41-b157-9ced61d2f683
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482339899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3482339899
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2493665044
Short name T26
Test name
Test status
Simulation time 1778142106 ps
CPU time 100.13 seconds
Started Jul 06 04:50:46 PM PDT 24
Finished Jul 06 04:52:27 PM PDT 24
Peak memory 212536 kb
Host smart-f9f93789-b0fe-4c2e-891a-852a837ff97d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493665044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2493665044
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3328030784
Short name T112
Test name
Test status
Simulation time 5298586709 ps
CPU time 73.39 seconds
Started Jul 06 04:51:43 PM PDT 24
Finished Jul 06 04:52:57 PM PDT 24
Peak memory 218944 kb
Host smart-915c5213-5de0-4a75-86a4-bff15b3e5df8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328030784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3328030784
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1082156330
Short name T56
Test name
Test status
Simulation time 33392619160 ps
CPU time 652.55 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 05:01:35 PM PDT 24
Peak memory 232492 kb
Host smart-eb03199a-63d1-40ca-827d-57188c3b139d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082156330 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1082156330
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1201537812
Short name T12
Test name
Test status
Simulation time 4359248217 ps
CPU time 15.19 seconds
Started Jul 06 04:51:21 PM PDT 24
Finished Jul 06 04:51:37 PM PDT 24
Peak memory 211432 kb
Host smart-b64a8a91-1be6-4c81-a94a-3737edb9969c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201537812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1201537812
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2548565559
Short name T28
Test name
Test status
Simulation time 4727789772 ps
CPU time 105.94 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:52:26 PM PDT 24
Peak memory 236860 kb
Host smart-56be232a-0869-449c-ac86-24098ba69601
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548565559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2548565559
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2261299519
Short name T85
Test name
Test status
Simulation time 5824466423 ps
CPU time 58.89 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:51:39 PM PDT 24
Peak memory 213512 kb
Host smart-2d3fbf33-3112-412b-9890-ba3f091a8b77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261299519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2261299519
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.338506995
Short name T73
Test name
Test status
Simulation time 6640781603 ps
CPU time 56 seconds
Started Jul 06 04:51:46 PM PDT 24
Finished Jul 06 04:52:43 PM PDT 24
Peak memory 210704 kb
Host smart-a25ca279-4ab4-452a-9f59-0df43c7ae8af
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338506995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.338506995
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.640825633
Short name T118
Test name
Test status
Simulation time 1148809317 ps
CPU time 69.56 seconds
Started Jul 06 04:51:54 PM PDT 24
Finished Jul 06 04:53:03 PM PDT 24
Peak memory 211192 kb
Host smart-7a2707f1-06e7-48fc-a00c-f1f287718687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640825633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.640825633
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1563303812
Short name T8
Test name
Test status
Simulation time 97333846 ps
CPU time 5.53 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 04:50:48 PM PDT 24
Peak memory 211292 kb
Host smart-e232d817-2766-4ee3-9c12-3313cf0c899a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1563303812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1563303812
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1281546737
Short name T40
Test name
Test status
Simulation time 2053039399 ps
CPU time 12.9 seconds
Started Jul 06 04:51:02 PM PDT 24
Finished Jul 06 04:51:15 PM PDT 24
Peak memory 211836 kb
Host smart-39acf72b-f4ee-4874-a65c-324aef2c5215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281546737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1281546737
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.257325752
Short name T187
Test name
Test status
Simulation time 716319701 ps
CPU time 11.19 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:50:52 PM PDT 24
Peak memory 218116 kb
Host smart-d7c96b34-4c74-477e-9dd0-0ff8d663113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257325752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.257325752
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3267521619
Short name T123
Test name
Test status
Simulation time 10807682441 ps
CPU time 79.09 seconds
Started Jul 06 04:51:49 PM PDT 24
Finished Jul 06 04:53:08 PM PDT 24
Peak memory 219068 kb
Host smart-6412eac5-40b4-41b0-a78a-5de2bdc1dd4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267521619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3267521619
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3652999650
Short name T95
Test name
Test status
Simulation time 13094065321 ps
CPU time 56.72 seconds
Started Jul 06 04:51:52 PM PDT 24
Finished Jul 06 04:52:49 PM PDT 24
Peak memory 210636 kb
Host smart-a14f0224-b94e-48ef-ac18-6d831e87165b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652999650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3652999650
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.724047695
Short name T109
Test name
Test status
Simulation time 10832233773 ps
CPU time 47.88 seconds
Started Jul 06 04:52:31 PM PDT 24
Finished Jul 06 04:53:25 PM PDT 24
Peak memory 210752 kb
Host smart-1c1f4d17-84f5-4ffd-a019-82907543ff84
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724047695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.724047695
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2534080592
Short name T115
Test name
Test status
Simulation time 6777468237 ps
CPU time 75.47 seconds
Started Jul 06 04:51:52 PM PDT 24
Finished Jul 06 04:53:08 PM PDT 24
Peak memory 211528 kb
Host smart-9285fe20-729f-4414-b431-584ce762bd89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534080592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2534080592
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4239031132
Short name T121
Test name
Test status
Simulation time 1467222274 ps
CPU time 68.79 seconds
Started Jul 06 04:51:49 PM PDT 24
Finished Jul 06 04:52:58 PM PDT 24
Peak memory 218928 kb
Host smart-adb0f742-ec97-42b7-bb52-60305c821768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239031132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4239031132
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1228799353
Short name T99
Test name
Test status
Simulation time 1991136999 ps
CPU time 14.89 seconds
Started Jul 06 04:51:45 PM PDT 24
Finished Jul 06 04:52:01 PM PDT 24
Peak memory 218868 kb
Host smart-7d31243c-b8e6-47ab-8230-23334dfb1972
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228799353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1228799353
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.855479545
Short name T22
Test name
Test status
Simulation time 221441438189 ps
CPU time 7709.14 seconds
Started Jul 06 04:51:12 PM PDT 24
Finished Jul 06 06:59:42 PM PDT 24
Peak memory 237380 kb
Host smart-1c07b7f8-7fb7-496e-8b14-fd085ec7f248
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855479545 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.855479545
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3969826921
Short name T446
Test name
Test status
Simulation time 2214732769 ps
CPU time 11.54 seconds
Started Jul 06 04:51:36 PM PDT 24
Finished Jul 06 04:51:48 PM PDT 24
Peak memory 210788 kb
Host smart-b6081f17-78d4-409e-88c4-cd3578f9e60e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969826921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3969826921
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2605556983
Short name T454
Test name
Test status
Simulation time 782809303 ps
CPU time 9.46 seconds
Started Jul 06 04:51:25 PM PDT 24
Finished Jul 06 04:51:35 PM PDT 24
Peak memory 210676 kb
Host smart-ebecc8dc-c4b4-4c35-931c-c7ce2498fe96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605556983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2605556983
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2939604418
Short name T460
Test name
Test status
Simulation time 1354817901 ps
CPU time 14.6 seconds
Started Jul 06 04:51:26 PM PDT 24
Finished Jul 06 04:51:41 PM PDT 24
Peak memory 210712 kb
Host smart-aa9e528f-2056-4b1a-953b-0d9ab89cc28a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939604418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2939604418
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2609672531
Short name T69
Test name
Test status
Simulation time 8415422289 ps
CPU time 14.93 seconds
Started Jul 06 04:51:28 PM PDT 24
Finished Jul 06 04:51:43 PM PDT 24
Peak memory 219076 kb
Host smart-69daa71b-e563-4efb-91ed-3df81934150b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609672531 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2609672531
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2625172285
Short name T453
Test name
Test status
Simulation time 846307873 ps
CPU time 7.19 seconds
Started Jul 06 04:51:34 PM PDT 24
Finished Jul 06 04:51:42 PM PDT 24
Peak memory 217524 kb
Host smart-481cd5c1-37b7-4b07-8d21-607116a364f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625172285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2625172285
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1566919492
Short name T449
Test name
Test status
Simulation time 1526998410 ps
CPU time 12.97 seconds
Started Jul 06 04:51:32 PM PDT 24
Finished Jul 06 04:51:45 PM PDT 24
Peak memory 210628 kb
Host smart-2740dd7f-e333-46e4-aa4c-d3ed9d3bf7a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566919492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1566919492
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1218772388
Short name T374
Test name
Test status
Simulation time 1775943409 ps
CPU time 14.35 seconds
Started Jul 06 04:51:27 PM PDT 24
Finished Jul 06 04:51:42 PM PDT 24
Peak memory 210588 kb
Host smart-3f054b5e-448a-4456-8344-291e1dafac7e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218772388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1218772388
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1852173836
Short name T79
Test name
Test status
Simulation time 17490495531 ps
CPU time 68.18 seconds
Started Jul 06 04:51:27 PM PDT 24
Finished Jul 06 04:52:36 PM PDT 24
Peak memory 210792 kb
Host smart-9971395c-4db6-4bf9-8c69-94dcf59cf80a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852173836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1852173836
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.633681455
Short name T459
Test name
Test status
Simulation time 3585161728 ps
CPU time 9.61 seconds
Started Jul 06 04:51:25 PM PDT 24
Finished Jul 06 04:51:35 PM PDT 24
Peak memory 210792 kb
Host smart-36104374-5942-4838-9895-801ff63bf395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633681455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.633681455
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3928997884
Short name T396
Test name
Test status
Simulation time 6170540465 ps
CPU time 16.32 seconds
Started Jul 06 04:51:37 PM PDT 24
Finished Jul 06 04:51:53 PM PDT 24
Peak memory 218936 kb
Host smart-badbbd9f-4358-4201-ad0a-55edb72e458c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928997884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3928997884
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2081322680
Short name T450
Test name
Test status
Simulation time 1828409253 ps
CPU time 76.77 seconds
Started Jul 06 04:51:28 PM PDT 24
Finished Jul 06 04:52:45 PM PDT 24
Peak memory 219016 kb
Host smart-c27cc13a-b80c-4e09-b27d-1c3b6be3bbd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081322680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2081322680
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3758621477
Short name T411
Test name
Test status
Simulation time 2780466722 ps
CPU time 13.01 seconds
Started Jul 06 04:51:36 PM PDT 24
Finished Jul 06 04:51:50 PM PDT 24
Peak memory 210768 kb
Host smart-acd271dd-6b60-491a-aeb6-49c3549bd8cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758621477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3758621477
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3960730050
Short name T437
Test name
Test status
Simulation time 3468130385 ps
CPU time 10.64 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:51:53 PM PDT 24
Peak memory 218780 kb
Host smart-913ee656-0b5d-4f62-a595-ecb277084c74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960730050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3960730050
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3952098755
Short name T81
Test name
Test status
Simulation time 1156919422 ps
CPU time 12.7 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:51:54 PM PDT 24
Peak memory 210608 kb
Host smart-29d980f7-af30-46a2-9b59-a28c203e17f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952098755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3952098755
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.771230808
Short name T465
Test name
Test status
Simulation time 3040938279 ps
CPU time 8.48 seconds
Started Jul 06 04:51:33 PM PDT 24
Finished Jul 06 04:51:42 PM PDT 24
Peak memory 218952 kb
Host smart-8431795c-2c87-4921-b260-c6fca2a44a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771230808 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.771230808
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1205956402
Short name T395
Test name
Test status
Simulation time 2673272007 ps
CPU time 9.47 seconds
Started Jul 06 04:51:31 PM PDT 24
Finished Jul 06 04:51:41 PM PDT 24
Peak memory 210780 kb
Host smart-917ce35f-7106-46c1-b08d-481a019515d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205956402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1205956402
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1813486393
Short name T387
Test name
Test status
Simulation time 332571919 ps
CPU time 6.39 seconds
Started Jul 06 04:51:36 PM PDT 24
Finished Jul 06 04:51:43 PM PDT 24
Peak memory 210464 kb
Host smart-eb93985b-a209-4a4d-8df6-7c35143e2e8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813486393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1813486393
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2571844508
Short name T433
Test name
Test status
Simulation time 1571588537 ps
CPU time 8.76 seconds
Started Jul 06 04:51:35 PM PDT 24
Finished Jul 06 04:51:45 PM PDT 24
Peak memory 210500 kb
Host smart-9c19b758-1bd2-444f-b4c8-a41eee5d101a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571844508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2571844508
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1152279980
Short name T421
Test name
Test status
Simulation time 39602649038 ps
CPU time 80.5 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:53:03 PM PDT 24
Peak memory 211780 kb
Host smart-49cd96c7-f572-4bc3-a1b0-3bb77edb8201
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152279980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1152279980
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3200563131
Short name T430
Test name
Test status
Simulation time 662115312 ps
CPU time 6.34 seconds
Started Jul 06 04:51:34 PM PDT 24
Finished Jul 06 04:51:41 PM PDT 24
Peak memory 210852 kb
Host smart-2451deb6-e89b-4d89-ab64-305979d4b412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200563131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3200563131
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1383869662
Short name T448
Test name
Test status
Simulation time 290173365 ps
CPU time 8.62 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:51:51 PM PDT 24
Peak memory 215024 kb
Host smart-0a5bdb3c-3900-4f69-a034-bac0fecf540b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383869662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1383869662
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3215722411
Short name T463
Test name
Test status
Simulation time 5126864478 ps
CPU time 42.39 seconds
Started Jul 06 04:51:33 PM PDT 24
Finished Jul 06 04:52:16 PM PDT 24
Peak memory 211144 kb
Host smart-aa3a9fa2-9b68-4b52-9dbd-1e5b82a1f236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215722411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3215722411
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.184647109
Short name T391
Test name
Test status
Simulation time 1246786551 ps
CPU time 12 seconds
Started Jul 06 04:51:45 PM PDT 24
Finished Jul 06 04:51:58 PM PDT 24
Peak memory 218904 kb
Host smart-4c982de5-f392-47a6-a657-77cd1f250aff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184647109 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.184647109
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3406791815
Short name T76
Test name
Test status
Simulation time 89149134 ps
CPU time 4.21 seconds
Started Jul 06 04:51:45 PM PDT 24
Finished Jul 06 04:51:51 PM PDT 24
Peak memory 218044 kb
Host smart-0b2f2011-f5c3-49ad-8d2a-516cedfcd6d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406791815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3406791815
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.883361957
Short name T393
Test name
Test status
Simulation time 3417353330 ps
CPU time 17.53 seconds
Started Jul 06 04:51:44 PM PDT 24
Finished Jul 06 04:52:02 PM PDT 24
Peak memory 219064 kb
Host smart-6355cd05-7adf-4b1d-ab07-95607fabd884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883361957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.883361957
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.985769308
Short name T113
Test name
Test status
Simulation time 3057246621 ps
CPU time 71.71 seconds
Started Jul 06 04:52:48 PM PDT 24
Finished Jul 06 04:54:01 PM PDT 24
Peak memory 212064 kb
Host smart-83163e45-8f99-4c7b-af8b-8ab81ebc2b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985769308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.985769308
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2374221431
Short name T383
Test name
Test status
Simulation time 2197582003 ps
CPU time 13.64 seconds
Started Jul 06 04:51:45 PM PDT 24
Finished Jul 06 04:52:00 PM PDT 24
Peak memory 218916 kb
Host smart-5fa35afc-652f-4d5f-b790-541220e1f1e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374221431 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2374221431
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.911863235
Short name T372
Test name
Test status
Simulation time 1673131424 ps
CPU time 9.01 seconds
Started Jul 06 04:51:46 PM PDT 24
Finished Jul 06 04:51:56 PM PDT 24
Peak memory 210748 kb
Host smart-25bbad8b-ea02-431e-86b6-5a09da696826
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911863235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.911863235
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1527970614
Short name T461
Test name
Test status
Simulation time 6262245659 ps
CPU time 38.5 seconds
Started Jul 06 04:51:49 PM PDT 24
Finished Jul 06 04:52:28 PM PDT 24
Peak memory 210760 kb
Host smart-d119fe4e-cf56-4279-a433-128f9c63497f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527970614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1527970614
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1048797058
Short name T432
Test name
Test status
Simulation time 1625891126 ps
CPU time 8.96 seconds
Started Jul 06 04:51:44 PM PDT 24
Finished Jul 06 04:51:55 PM PDT 24
Peak memory 218252 kb
Host smart-4a7fea46-adff-49c8-b7d2-1dc57c14addf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048797058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1048797058
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.980042109
Short name T435
Test name
Test status
Simulation time 1641312046 ps
CPU time 16.09 seconds
Started Jul 06 04:51:47 PM PDT 24
Finished Jul 06 04:52:03 PM PDT 24
Peak memory 218872 kb
Host smart-a2f42577-5ed5-463b-aab8-d92276c52928
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980042109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.980042109
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.379584821
Short name T116
Test name
Test status
Simulation time 1175503946 ps
CPU time 41.28 seconds
Started Jul 06 04:51:45 PM PDT 24
Finished Jul 06 04:52:27 PM PDT 24
Peak memory 212168 kb
Host smart-5192c25a-3f4d-4dcc-8e33-05480a12d430
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379584821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.379584821
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1599963140
Short name T417
Test name
Test status
Simulation time 7006510800 ps
CPU time 14.75 seconds
Started Jul 06 04:51:44 PM PDT 24
Finished Jul 06 04:52:00 PM PDT 24
Peak memory 212748 kb
Host smart-d0ef2ac3-15f8-48fd-a1a6-1456aba5f680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599963140 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1599963140
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2998995949
Short name T438
Test name
Test status
Simulation time 1786133413 ps
CPU time 6.12 seconds
Started Jul 06 04:51:54 PM PDT 24
Finished Jul 06 04:52:00 PM PDT 24
Peak memory 217844 kb
Host smart-ce3927ce-f9a6-4775-a25f-f4e91210dd2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998995949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2998995949
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2356866224
Short name T418
Test name
Test status
Simulation time 600415440 ps
CPU time 8.06 seconds
Started Jul 06 04:52:21 PM PDT 24
Finished Jul 06 04:52:29 PM PDT 24
Peak memory 210672 kb
Host smart-5f0494bb-b155-494a-a1d2-c80ed486a53b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356866224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2356866224
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.349654437
Short name T405
Test name
Test status
Simulation time 2445998100 ps
CPU time 11.91 seconds
Started Jul 06 04:51:45 PM PDT 24
Finished Jul 06 04:51:58 PM PDT 24
Peak memory 218976 kb
Host smart-e1c2ff95-efea-40b8-8954-ed80c6b8402b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349654437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.349654437
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1975916172
Short name T119
Test name
Test status
Simulation time 7815860156 ps
CPU time 45.67 seconds
Started Jul 06 04:51:44 PM PDT 24
Finished Jul 06 04:52:31 PM PDT 24
Peak memory 212536 kb
Host smart-07b56a61-7980-495d-a104-5302d4f0c5c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975916172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1975916172
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2345472976
Short name T426
Test name
Test status
Simulation time 96853948 ps
CPU time 5.74 seconds
Started Jul 06 04:51:49 PM PDT 24
Finished Jul 06 04:51:55 PM PDT 24
Peak memory 218928 kb
Host smart-27db4546-c18b-4c67-b94e-6aba0d58f14a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345472976 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2345472976
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3411406965
Short name T436
Test name
Test status
Simulation time 3082039581 ps
CPU time 8.93 seconds
Started Jul 06 04:51:48 PM PDT 24
Finished Jul 06 04:51:57 PM PDT 24
Peak memory 210780 kb
Host smart-ecba3535-05fc-47d0-86e2-f4d9d392ad50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411406965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3411406965
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4229633980
Short name T429
Test name
Test status
Simulation time 720782284 ps
CPU time 5.26 seconds
Started Jul 06 04:51:54 PM PDT 24
Finished Jul 06 04:51:59 PM PDT 24
Peak memory 210748 kb
Host smart-9f7c3076-2daa-4577-bd2b-07d1c1796aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229633980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4229633980
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1581437625
Short name T373
Test name
Test status
Simulation time 7002029600 ps
CPU time 17.26 seconds
Started Jul 06 04:51:46 PM PDT 24
Finished Jul 06 04:52:04 PM PDT 24
Peak memory 218992 kb
Host smart-b55c3ec9-0c9a-4a62-9ec3-2c086e2dd797
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581437625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1581437625
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.345483360
Short name T114
Test name
Test status
Simulation time 6542289477 ps
CPU time 44.7 seconds
Started Jul 06 04:51:52 PM PDT 24
Finished Jul 06 04:52:37 PM PDT 24
Peak memory 218912 kb
Host smart-95790734-e360-4f2b-bd89-89895af0c76b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345483360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.345483360
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1977289033
Short name T408
Test name
Test status
Simulation time 1859832689 ps
CPU time 15.65 seconds
Started Jul 06 04:51:52 PM PDT 24
Finished Jul 06 04:52:08 PM PDT 24
Peak memory 218940 kb
Host smart-43f7c685-8876-4ee8-bfe5-95c6c82d9410
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977289033 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1977289033
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.138729422
Short name T75
Test name
Test status
Simulation time 1108946604 ps
CPU time 7.75 seconds
Started Jul 06 04:51:49 PM PDT 24
Finished Jul 06 04:51:57 PM PDT 24
Peak memory 217760 kb
Host smart-98b3a846-6f8c-4002-a994-d7c5f3266588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138729422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.138729422
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1592034281
Short name T108
Test name
Test status
Simulation time 14797775769 ps
CPU time 59.98 seconds
Started Jul 06 04:51:51 PM PDT 24
Finished Jul 06 04:52:52 PM PDT 24
Peak memory 210700 kb
Host smart-db120e33-9994-49c9-acac-70bc83b714f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592034281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1592034281
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2978779421
Short name T440
Test name
Test status
Simulation time 258395005 ps
CPU time 6.02 seconds
Started Jul 06 04:51:48 PM PDT 24
Finished Jul 06 04:51:55 PM PDT 24
Peak memory 217932 kb
Host smart-abf8f553-8b1c-4d54-81f3-cbd2d80ba6af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978779421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2978779421
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2212487008
Short name T394
Test name
Test status
Simulation time 2126067772 ps
CPU time 11.19 seconds
Started Jul 06 04:51:50 PM PDT 24
Finished Jul 06 04:52:01 PM PDT 24
Peak memory 219028 kb
Host smart-2ff3e113-efc3-4f67-a1e3-c0ecb37cd86b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212487008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2212487008
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4050659545
Short name T384
Test name
Test status
Simulation time 7303015573 ps
CPU time 15.77 seconds
Started Jul 06 04:51:51 PM PDT 24
Finished Jul 06 04:52:07 PM PDT 24
Peak memory 219044 kb
Host smart-c8321dca-d766-4b54-a7f4-2be09da94d04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050659545 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4050659545
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2161182777
Short name T401
Test name
Test status
Simulation time 2873709957 ps
CPU time 15.34 seconds
Started Jul 06 04:51:47 PM PDT 24
Finished Jul 06 04:52:03 PM PDT 24
Peak memory 210740 kb
Host smart-3eeb5d0c-fb9d-4d6b-9e46-8075246582c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161182777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2161182777
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.742264721
Short name T107
Test name
Test status
Simulation time 13588312357 ps
CPU time 46.81 seconds
Started Jul 06 04:51:49 PM PDT 24
Finished Jul 06 04:52:36 PM PDT 24
Peak memory 210676 kb
Host smart-e2ea6ab6-0286-40ba-9a31-8661e26db1ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742264721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.742264721
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1516992282
Short name T103
Test name
Test status
Simulation time 3246419286 ps
CPU time 13.59 seconds
Started Jul 06 04:51:50 PM PDT 24
Finished Jul 06 04:52:04 PM PDT 24
Peak memory 210760 kb
Host smart-9fd6653f-3564-4922-9cc3-3b9a6b7f0956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516992282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1516992282
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1070248049
Short name T409
Test name
Test status
Simulation time 8402121682 ps
CPU time 16.99 seconds
Started Jul 06 04:51:47 PM PDT 24
Finished Jul 06 04:52:05 PM PDT 24
Peak memory 219060 kb
Host smart-4be53500-bdb8-44f4-ad53-ede39f6c78a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070248049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1070248049
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4242821004
Short name T458
Test name
Test status
Simulation time 4892846343 ps
CPU time 9.75 seconds
Started Jul 06 04:51:48 PM PDT 24
Finished Jul 06 04:51:59 PM PDT 24
Peak memory 218952 kb
Host smart-ff4e3db3-19aa-4afa-8aba-18815f06dcd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242821004 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4242821004
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.803830187
Short name T106
Test name
Test status
Simulation time 86288642 ps
CPU time 4.43 seconds
Started Jul 06 04:51:53 PM PDT 24
Finished Jul 06 04:51:58 PM PDT 24
Peak memory 210580 kb
Host smart-3b20feeb-152d-40bf-8243-361b4566ecef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803830187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.803830187
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2270723286
Short name T91
Test name
Test status
Simulation time 8899882266 ps
CPU time 66.33 seconds
Started Jul 06 04:51:48 PM PDT 24
Finished Jul 06 04:52:55 PM PDT 24
Peak memory 210820 kb
Host smart-2ee53cb2-9462-4aba-88ca-a24a90fdcce1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270723286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2270723286
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.675085426
Short name T442
Test name
Test status
Simulation time 101401004 ps
CPU time 4.3 seconds
Started Jul 06 04:51:50 PM PDT 24
Finished Jul 06 04:51:54 PM PDT 24
Peak memory 210740 kb
Host smart-0e5c4608-2826-481f-9bfa-239c9dfae508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675085426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.675085426
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.312313221
Short name T439
Test name
Test status
Simulation time 2040773909 ps
CPU time 17.89 seconds
Started Jul 06 04:51:50 PM PDT 24
Finished Jul 06 04:52:08 PM PDT 24
Peak memory 219016 kb
Host smart-e1be1818-b953-4383-bc1e-068522cab0bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312313221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.312313221
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1273775865
Short name T64
Test name
Test status
Simulation time 2151806504 ps
CPU time 47.9 seconds
Started Jul 06 04:51:50 PM PDT 24
Finished Jul 06 04:52:38 PM PDT 24
Peak memory 212148 kb
Host smart-9eb50020-1e70-44d1-8b75-f6de2064f912
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273775865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1273775865
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.147138370
Short name T377
Test name
Test status
Simulation time 1733344075 ps
CPU time 12.3 seconds
Started Jul 06 04:51:51 PM PDT 24
Finished Jul 06 04:52:03 PM PDT 24
Peak memory 218972 kb
Host smart-25772bf1-abe4-433a-9995-3ca56e902f38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147138370 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.147138370
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2340918213
Short name T88
Test name
Test status
Simulation time 101415284 ps
CPU time 4.38 seconds
Started Jul 06 04:51:48 PM PDT 24
Finished Jul 06 04:51:53 PM PDT 24
Peak memory 210624 kb
Host smart-d7bb30ae-621c-4dcf-a1e9-8a7a7335ab3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340918213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2340918213
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2722687103
Short name T100
Test name
Test status
Simulation time 433297222 ps
CPU time 19.81 seconds
Started Jul 06 04:51:48 PM PDT 24
Finished Jul 06 04:52:08 PM PDT 24
Peak memory 210804 kb
Host smart-46907d21-23f7-4c76-bb11-9b6b06c0b27c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722687103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2722687103
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.90234430
Short name T104
Test name
Test status
Simulation time 2095149125 ps
CPU time 16.76 seconds
Started Jul 06 04:51:53 PM PDT 24
Finished Jul 06 04:52:10 PM PDT 24
Peak memory 210648 kb
Host smart-40364cc1-1657-4bf6-9fa8-c6d6480917b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90234430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ct
rl_same_csr_outstanding.90234430
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3349589190
Short name T456
Test name
Test status
Simulation time 2797786520 ps
CPU time 17.14 seconds
Started Jul 06 04:51:50 PM PDT 24
Finished Jul 06 04:52:08 PM PDT 24
Peak memory 219044 kb
Host smart-ba097974-ba6a-48ba-814a-e0d606fe8fac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349589190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3349589190
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3054499775
Short name T402
Test name
Test status
Simulation time 103831510 ps
CPU time 5.64 seconds
Started Jul 06 04:51:55 PM PDT 24
Finished Jul 06 04:52:01 PM PDT 24
Peak memory 219024 kb
Host smart-9f467449-372f-450e-aef2-5c62888fd66a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054499775 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3054499775
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3774103531
Short name T77
Test name
Test status
Simulation time 348345070 ps
CPU time 4.33 seconds
Started Jul 06 04:52:02 PM PDT 24
Finished Jul 06 04:52:07 PM PDT 24
Peak memory 210608 kb
Host smart-6ebc3335-9b59-4df5-b7a1-0856c0e17f9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774103531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3774103531
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2811842926
Short name T412
Test name
Test status
Simulation time 1502255130 ps
CPU time 19.44 seconds
Started Jul 06 04:51:51 PM PDT 24
Finished Jul 06 04:52:10 PM PDT 24
Peak memory 210688 kb
Host smart-677a944b-06c4-45f0-90d3-c42715888940
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811842926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2811842926
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.720429965
Short name T105
Test name
Test status
Simulation time 6690918655 ps
CPU time 13.85 seconds
Started Jul 06 04:51:57 PM PDT 24
Finished Jul 06 04:52:12 PM PDT 24
Peak memory 210884 kb
Host smart-f340ac81-71be-40d0-b7a2-81af75fb9642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720429965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.720429965
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1370136827
Short name T413
Test name
Test status
Simulation time 2419302041 ps
CPU time 8.45 seconds
Started Jul 06 04:51:57 PM PDT 24
Finished Jul 06 04:52:06 PM PDT 24
Peak memory 218924 kb
Host smart-88aace7f-01be-4102-90a2-badc86449d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370136827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1370136827
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3548944506
Short name T400
Test name
Test status
Simulation time 100339944 ps
CPU time 5.09 seconds
Started Jul 06 04:51:54 PM PDT 24
Finished Jul 06 04:51:59 PM PDT 24
Peak memory 218956 kb
Host smart-236b3c41-6928-4167-ac6c-4268cbba8296
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548944506 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3548944506
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2343877088
Short name T375
Test name
Test status
Simulation time 4279144327 ps
CPU time 17.29 seconds
Started Jul 06 04:51:58 PM PDT 24
Finished Jul 06 04:52:15 PM PDT 24
Peak memory 218744 kb
Host smart-f62306b5-a5c3-4121-abda-f2ec51e63ecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343877088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2343877088
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.489975986
Short name T404
Test name
Test status
Simulation time 9306324465 ps
CPU time 63.91 seconds
Started Jul 06 04:51:56 PM PDT 24
Finished Jul 06 04:53:00 PM PDT 24
Peak memory 210704 kb
Host smart-36ff9986-a1f8-47ff-89dc-5523d218ec05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489975986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.489975986
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3590296125
Short name T102
Test name
Test status
Simulation time 1693297258 ps
CPU time 14.43 seconds
Started Jul 06 04:51:55 PM PDT 24
Finished Jul 06 04:52:09 PM PDT 24
Peak memory 218992 kb
Host smart-7704f2b1-e08d-4681-a52e-9b2742de265b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590296125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3590296125
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.60977038
Short name T455
Test name
Test status
Simulation time 8317287908 ps
CPU time 18.79 seconds
Started Jul 06 04:51:58 PM PDT 24
Finished Jul 06 04:52:17 PM PDT 24
Peak memory 218956 kb
Host smart-3e98075c-6414-4122-9f83-f26f8cae84bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60977038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.60977038
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1186510918
Short name T117
Test name
Test status
Simulation time 2329600203 ps
CPU time 39.73 seconds
Started Jul 06 04:51:57 PM PDT 24
Finished Jul 06 04:52:37 PM PDT 24
Peak memory 219056 kb
Host smart-b818d18f-1eef-47f9-a89d-e720651db2dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186510918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1186510918
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4156906263
Short name T416
Test name
Test status
Simulation time 178523878 ps
CPU time 4.32 seconds
Started Jul 06 04:51:35 PM PDT 24
Finished Jul 06 04:51:39 PM PDT 24
Peak memory 210608 kb
Host smart-020c1f4f-82b8-49ab-b55e-1e9661cf4b60
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156906263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4156906263
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.626642472
Short name T441
Test name
Test status
Simulation time 1259848132 ps
CPU time 8.54 seconds
Started Jul 06 04:51:34 PM PDT 24
Finished Jul 06 04:51:43 PM PDT 24
Peak memory 217284 kb
Host smart-5ef693da-d3ee-4e72-8c4e-7c045f8f8a8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626642472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.626642472
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3280100648
Short name T90
Test name
Test status
Simulation time 177135871 ps
CPU time 7.39 seconds
Started Jul 06 04:51:33 PM PDT 24
Finished Jul 06 04:51:41 PM PDT 24
Peak memory 218808 kb
Host smart-bc5abb72-f4e6-429d-bcfb-d33e8af968fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280100648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3280100648
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1306274253
Short name T376
Test name
Test status
Simulation time 2770835009 ps
CPU time 12.35 seconds
Started Jul 06 04:51:35 PM PDT 24
Finished Jul 06 04:51:48 PM PDT 24
Peak memory 218948 kb
Host smart-72e9d15a-d39d-49e3-a890-2c64bbe8b3c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306274253 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1306274253
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.269970568
Short name T89
Test name
Test status
Simulation time 8818968798 ps
CPU time 15.06 seconds
Started Jul 06 04:51:39 PM PDT 24
Finished Jul 06 04:51:55 PM PDT 24
Peak memory 210784 kb
Host smart-6e8fbad2-6789-4ac9-a161-bc5e080405b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269970568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.269970568
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1924138420
Short name T452
Test name
Test status
Simulation time 1290048384 ps
CPU time 11.65 seconds
Started Jul 06 04:51:35 PM PDT 24
Finished Jul 06 04:51:48 PM PDT 24
Peak memory 210644 kb
Host smart-f07757a6-26f9-4293-b1d5-00b9b95387c8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924138420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1924138420
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3918791823
Short name T379
Test name
Test status
Simulation time 333224632 ps
CPU time 4.19 seconds
Started Jul 06 04:51:35 PM PDT 24
Finished Jul 06 04:51:40 PM PDT 24
Peak memory 210468 kb
Host smart-8a1e7139-3b87-4b54-83af-e7d8230e6095
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918791823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3918791823
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4174697143
Short name T96
Test name
Test status
Simulation time 3002977558 ps
CPU time 18.76 seconds
Started Jul 06 04:51:36 PM PDT 24
Finished Jul 06 04:51:55 PM PDT 24
Peak memory 210868 kb
Host smart-99b31669-cfaa-4e04-9d07-e5406acc1e04
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174697143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4174697143
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1794261567
Short name T101
Test name
Test status
Simulation time 12968098532 ps
CPU time 11.72 seconds
Started Jul 06 04:51:35 PM PDT 24
Finished Jul 06 04:51:48 PM PDT 24
Peak memory 218916 kb
Host smart-8ebe5084-2bf6-4766-a525-13a09b2a39d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794261567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1794261567
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1111639438
Short name T457
Test name
Test status
Simulation time 556887688 ps
CPU time 10.12 seconds
Started Jul 06 04:51:33 PM PDT 24
Finished Jul 06 04:51:44 PM PDT 24
Peak memory 218988 kb
Host smart-3098ab5b-da9b-4195-b6a6-513e9a92213b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111639438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1111639438
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1844891850
Short name T447
Test name
Test status
Simulation time 151583305 ps
CPU time 36.3 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:52:18 PM PDT 24
Peak memory 218880 kb
Host smart-8b594a82-58b8-4960-b194-1af11f44b551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844891850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1844891850
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4035492658
Short name T464
Test name
Test status
Simulation time 348155387 ps
CPU time 4.19 seconds
Started Jul 06 04:51:38 PM PDT 24
Finished Jul 06 04:51:43 PM PDT 24
Peak memory 217660 kb
Host smart-cfc832dc-2c24-4e0a-a761-6c6878651301
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035492658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4035492658
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1084440780
Short name T415
Test name
Test status
Simulation time 4022747900 ps
CPU time 13.11 seconds
Started Jul 06 04:51:53 PM PDT 24
Finished Jul 06 04:52:06 PM PDT 24
Peak memory 210740 kb
Host smart-1eebefbf-c2c2-4b53-b933-581b36a090e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084440780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1084440780
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3240761294
Short name T388
Test name
Test status
Simulation time 633185188 ps
CPU time 9.47 seconds
Started Jul 06 04:51:35 PM PDT 24
Finished Jul 06 04:51:46 PM PDT 24
Peak memory 210764 kb
Host smart-e650e040-832b-4b9e-b538-50dc9813de14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240761294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3240761294
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1007335960
Short name T427
Test name
Test status
Simulation time 7605495527 ps
CPU time 16.26 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:51:58 PM PDT 24
Peak memory 218964 kb
Host smart-e73c2495-44b7-43db-afdc-dd2ac120565a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007335960 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1007335960
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3369859383
Short name T68
Test name
Test status
Simulation time 2983265791 ps
CPU time 14.2 seconds
Started Jul 06 04:51:42 PM PDT 24
Finished Jul 06 04:51:57 PM PDT 24
Peak memory 210712 kb
Host smart-4ec177d1-a97e-47f8-a3da-7837d30d8af5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369859383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3369859383
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3913894675
Short name T386
Test name
Test status
Simulation time 4099602720 ps
CPU time 10.48 seconds
Started Jul 06 04:51:33 PM PDT 24
Finished Jul 06 04:51:44 PM PDT 24
Peak memory 210552 kb
Host smart-9ded98df-209e-46e8-b1e2-87f988b4600b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913894675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3913894675
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3292650158
Short name T390
Test name
Test status
Simulation time 1234290746 ps
CPU time 11.51 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:51:52 PM PDT 24
Peak memory 210484 kb
Host smart-bfb007fc-5833-4ba4-9be9-057f44903474
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292650158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3292650158
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1730228030
Short name T92
Test name
Test status
Simulation time 4502522613 ps
CPU time 28.18 seconds
Started Jul 06 04:51:33 PM PDT 24
Finished Jul 06 04:52:01 PM PDT 24
Peak memory 210832 kb
Host smart-c3b136f4-c43d-494f-b178-425969883079
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730228030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1730228030
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4242007395
Short name T98
Test name
Test status
Simulation time 3904639610 ps
CPU time 9.58 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:51:51 PM PDT 24
Peak memory 219008 kb
Host smart-de28475c-535b-4ce7-bed7-3d44c0a3db03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242007395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4242007395
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.976145023
Short name T420
Test name
Test status
Simulation time 1030010619 ps
CPU time 12.01 seconds
Started Jul 06 04:51:34 PM PDT 24
Finished Jul 06 04:51:46 PM PDT 24
Peak memory 218872 kb
Host smart-26df4e4b-d22d-4fe6-831e-c642b63bde5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976145023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.976145023
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4005752677
Short name T122
Test name
Test status
Simulation time 606025832 ps
CPU time 36.4 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:52:17 PM PDT 24
Peak memory 211124 kb
Host smart-660cc638-9137-4f55-a5e1-0b4db08c9e06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005752677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4005752677
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.944640253
Short name T389
Test name
Test status
Simulation time 1971626788 ps
CPU time 7.43 seconds
Started Jul 06 04:51:39 PM PDT 24
Finished Jul 06 04:51:47 PM PDT 24
Peak memory 217924 kb
Host smart-953d1cae-dd6e-454f-989d-e615c2e57f54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944640253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.944640253
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3281474487
Short name T392
Test name
Test status
Simulation time 1105093825 ps
CPU time 10.79 seconds
Started Jul 06 04:51:39 PM PDT 24
Finished Jul 06 04:51:50 PM PDT 24
Peak memory 210660 kb
Host smart-c6ca0c7d-c85f-4856-83ba-3b96b56914a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281474487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3281474487
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1206565645
Short name T74
Test name
Test status
Simulation time 8242395943 ps
CPU time 17.14 seconds
Started Jul 06 04:51:53 PM PDT 24
Finished Jul 06 04:52:10 PM PDT 24
Peak memory 218812 kb
Host smart-73c36a00-7d35-4f16-9296-330420d6dbbf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206565645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1206565645
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2553580892
Short name T385
Test name
Test status
Simulation time 122655352 ps
CPU time 5.39 seconds
Started Jul 06 04:51:39 PM PDT 24
Finished Jul 06 04:51:44 PM PDT 24
Peak memory 219012 kb
Host smart-b1e1d297-cd86-47bc-bb7f-6113d76760cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553580892 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2553580892
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.143020393
Short name T93
Test name
Test status
Simulation time 1450075896 ps
CPU time 8.46 seconds
Started Jul 06 04:51:42 PM PDT 24
Finished Jul 06 04:51:52 PM PDT 24
Peak memory 210672 kb
Host smart-49fc0576-f973-493d-b216-356237e7a584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143020393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.143020393
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3051600843
Short name T424
Test name
Test status
Simulation time 2842173137 ps
CPU time 12.62 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:51:54 PM PDT 24
Peak memory 210448 kb
Host smart-58637f50-900d-45e8-b32f-6d5fa5217c30
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051600843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3051600843
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.473808185
Short name T397
Test name
Test status
Simulation time 210764825 ps
CPU time 5.73 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:51:47 PM PDT 24
Peak memory 210468 kb
Host smart-bb0ee864-ef17-4edc-a9a9-5a3bef5c75aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473808185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
473808185
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2904549707
Short name T111
Test name
Test status
Simulation time 736400767 ps
CPU time 18.92 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:52:00 PM PDT 24
Peak memory 210672 kb
Host smart-63e94ad5-e07b-4b87-9d28-666bf289966a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904549707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2904549707
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1200678570
Short name T403
Test name
Test status
Simulation time 431912773 ps
CPU time 5.13 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:51:46 PM PDT 24
Peak memory 210792 kb
Host smart-1d0d4c6e-751d-4137-8816-788e46b85047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200678570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1200678570
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1152494349
Short name T425
Test name
Test status
Simulation time 247925540 ps
CPU time 8.46 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:51:51 PM PDT 24
Peak memory 218864 kb
Host smart-5b8bfb7d-fd0b-4ba1-96cb-e7c84862b9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152494349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1152494349
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3832621017
Short name T120
Test name
Test status
Simulation time 3672446026 ps
CPU time 76.33 seconds
Started Jul 06 04:51:39 PM PDT 24
Finished Jul 06 04:52:56 PM PDT 24
Peak memory 211992 kb
Host smart-408978cb-7b44-40d0-be81-1360e97f38f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832621017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3832621017
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2644841275
Short name T399
Test name
Test status
Simulation time 400040540 ps
CPU time 4.99 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:51:46 PM PDT 24
Peak memory 219020 kb
Host smart-2ee71728-1dee-4515-8826-60a52a106d6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644841275 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2644841275
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3384282036
Short name T78
Test name
Test status
Simulation time 1392072307 ps
CPU time 12.32 seconds
Started Jul 06 04:51:39 PM PDT 24
Finished Jul 06 04:51:51 PM PDT 24
Peak memory 210784 kb
Host smart-2c8187b5-f332-47c6-bd1f-e8595963507d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384282036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3384282036
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.716448925
Short name T443
Test name
Test status
Simulation time 370780773 ps
CPU time 18.29 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:51:58 PM PDT 24
Peak memory 210688 kb
Host smart-f3f4a07b-f7b1-4fc1-ae6b-36ffffd48889
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716448925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.716448925
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.193238862
Short name T82
Test name
Test status
Simulation time 1023989773 ps
CPU time 10.4 seconds
Started Jul 06 04:51:44 PM PDT 24
Finished Jul 06 04:51:56 PM PDT 24
Peak memory 218936 kb
Host smart-135e8ffc-64f2-48fe-ba82-8bcdaf2b9875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193238862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.193238862
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.907310233
Short name T444
Test name
Test status
Simulation time 1909162886 ps
CPU time 18.32 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:51:59 PM PDT 24
Peak memory 218912 kb
Host smart-a025d8a2-1ecc-4d75-87e1-21f52173df2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907310233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.907310233
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2153266594
Short name T382
Test name
Test status
Simulation time 1142115788 ps
CPU time 4.54 seconds
Started Jul 06 04:51:51 PM PDT 24
Finished Jul 06 04:51:56 PM PDT 24
Peak memory 218952 kb
Host smart-bfaa3140-4c16-4bb9-aaa2-fb334a685483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153266594 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2153266594
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3903085644
Short name T422
Test name
Test status
Simulation time 2381778339 ps
CPU time 11.5 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:51:54 PM PDT 24
Peak memory 218584 kb
Host smart-9d94fdad-a601-4f1d-924b-35920a55507c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903085644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3903085644
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.936693038
Short name T410
Test name
Test status
Simulation time 569612721 ps
CPU time 27.9 seconds
Started Jul 06 04:51:52 PM PDT 24
Finished Jul 06 04:52:20 PM PDT 24
Peak memory 210692 kb
Host smart-9446d927-0a2a-40e4-879c-24695fe449a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936693038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.936693038
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3806789279
Short name T407
Test name
Test status
Simulation time 3077845612 ps
CPU time 13.2 seconds
Started Jul 06 04:51:52 PM PDT 24
Finished Jul 06 04:52:06 PM PDT 24
Peak memory 210812 kb
Host smart-bbf470e5-6cee-4d55-b509-3b75166e113d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806789279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3806789279
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.754017434
Short name T381
Test name
Test status
Simulation time 1920143742 ps
CPU time 17.15 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:51:58 PM PDT 24
Peak memory 218996 kb
Host smart-978c33fa-f1c4-4e8b-86a9-5fea7341b7bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754017434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.754017434
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3720704949
Short name T451
Test name
Test status
Simulation time 1653076710 ps
CPU time 38.02 seconds
Started Jul 06 04:51:45 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 211184 kb
Host smart-3d89f56a-90a0-4fae-8a79-b56bf1aa7292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720704949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3720704949
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3252117585
Short name T378
Test name
Test status
Simulation time 4498791355 ps
CPU time 16.13 seconds
Started Jul 06 04:51:43 PM PDT 24
Finished Jul 06 04:52:00 PM PDT 24
Peak memory 219052 kb
Host smart-f037484a-cbc4-4953-945a-c0c5f1404dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252117585 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3252117585
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3718200357
Short name T67
Test name
Test status
Simulation time 1153958736 ps
CPU time 10.53 seconds
Started Jul 06 04:51:43 PM PDT 24
Finished Jul 06 04:51:54 PM PDT 24
Peak memory 218816 kb
Host smart-bd88e520-11d5-467c-a3fd-0de170dcbaf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718200357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3718200357
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3676239655
Short name T428
Test name
Test status
Simulation time 10830421215 ps
CPU time 62.58 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:52:44 PM PDT 24
Peak memory 210620 kb
Host smart-ef82d837-9217-4e3f-a2fc-ed98484604ae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676239655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3676239655
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1995607272
Short name T80
Test name
Test status
Simulation time 1219098336 ps
CPU time 11.49 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:51:52 PM PDT 24
Peak memory 210760 kb
Host smart-7aaf3436-1a69-4a5a-a825-65fc1be455fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995607272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1995607272
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1394681993
Short name T398
Test name
Test status
Simulation time 383285058 ps
CPU time 7.41 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:51:48 PM PDT 24
Peak memory 218908 kb
Host smart-2bb689ad-e771-4526-97f3-b057e6e69585
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394681993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1394681993
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3671883232
Short name T445
Test name
Test status
Simulation time 3356689553 ps
CPU time 40.8 seconds
Started Jul 06 04:51:40 PM PDT 24
Finished Jul 06 04:52:21 PM PDT 24
Peak memory 211984 kb
Host smart-37d36b84-cbb0-42e4-875a-7e13e8bc662f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671883232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3671883232
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.635430938
Short name T431
Test name
Test status
Simulation time 1895320059 ps
CPU time 14.54 seconds
Started Jul 06 04:51:51 PM PDT 24
Finished Jul 06 04:52:06 PM PDT 24
Peak memory 218924 kb
Host smart-2719229f-4fab-4c34-94f7-e042af75f50e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635430938 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.635430938
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.70903832
Short name T94
Test name
Test status
Simulation time 2913794849 ps
CPU time 8.65 seconds
Started Jul 06 04:51:45 PM PDT 24
Finished Jul 06 04:51:55 PM PDT 24
Peak memory 217672 kb
Host smart-6cc3ff96-795e-4d1a-a474-a1364fcbd30f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70903832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.70903832
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2615153360
Short name T462
Test name
Test status
Simulation time 3141713454 ps
CPU time 38 seconds
Started Jul 06 04:51:41 PM PDT 24
Finished Jul 06 04:52:19 PM PDT 24
Peak memory 210688 kb
Host smart-ea80a8ea-0044-4f9f-a276-fcdb659f59e2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615153360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2615153360
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1345501764
Short name T414
Test name
Test status
Simulation time 304882610 ps
CPU time 7.99 seconds
Started Jul 06 04:51:53 PM PDT 24
Finished Jul 06 04:52:01 PM PDT 24
Peak memory 210748 kb
Host smart-14dc44bd-ce98-4d62-82fb-ceb7cdbee7ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345501764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1345501764
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.221449066
Short name T419
Test name
Test status
Simulation time 2051119554 ps
CPU time 20.86 seconds
Started Jul 06 04:51:45 PM PDT 24
Finished Jul 06 04:52:07 PM PDT 24
Peak memory 218892 kb
Host smart-4b5a8d30-cd6a-4481-b975-520d430aa21b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221449066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.221449066
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4257492205
Short name T66
Test name
Test status
Simulation time 330713368 ps
CPU time 37.05 seconds
Started Jul 06 04:51:46 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 218848 kb
Host smart-ddd86201-56bf-44e5-a56e-0f9187a2c295
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257492205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4257492205
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.849483116
Short name T434
Test name
Test status
Simulation time 1860523287 ps
CPU time 15.96 seconds
Started Jul 06 04:51:44 PM PDT 24
Finished Jul 06 04:52:01 PM PDT 24
Peak memory 218956 kb
Host smart-f8ae5508-3c08-4cdb-9e0a-a574711a7242
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849483116 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.849483116
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3511327251
Short name T380
Test name
Test status
Simulation time 4732653720 ps
CPU time 11.59 seconds
Started Jul 06 04:51:44 PM PDT 24
Finished Jul 06 04:51:56 PM PDT 24
Peak memory 218948 kb
Host smart-d6bec950-4e6f-4f40-a753-884c763cdf1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511327251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3511327251
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2606531852
Short name T97
Test name
Test status
Simulation time 2005759398 ps
CPU time 27.33 seconds
Started Jul 06 04:51:44 PM PDT 24
Finished Jul 06 04:52:12 PM PDT 24
Peak memory 210800 kb
Host smart-570f5404-742f-4b5d-a51d-c87066845fbe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606531852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2606531852
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1938396152
Short name T406
Test name
Test status
Simulation time 822489465 ps
CPU time 5.98 seconds
Started Jul 06 04:51:44 PM PDT 24
Finished Jul 06 04:51:51 PM PDT 24
Peak memory 218264 kb
Host smart-d74ba56e-85de-410d-aac9-44964fd46f2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938396152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1938396152
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3101066121
Short name T423
Test name
Test status
Simulation time 13290276056 ps
CPU time 15.58 seconds
Started Jul 06 04:51:44 PM PDT 24
Finished Jul 06 04:52:01 PM PDT 24
Peak memory 218952 kb
Host smart-39dc0936-d744-401a-83de-c47ca931505f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101066121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3101066121
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.889550490
Short name T65
Test name
Test status
Simulation time 3790096507 ps
CPU time 40.71 seconds
Started Jul 06 04:51:46 PM PDT 24
Finished Jul 06 04:52:28 PM PDT 24
Peak memory 219016 kb
Host smart-29dc67b1-25cf-4f83-af48-f7e051c7ed59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889550490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.889550490
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1768194556
Short name T191
Test name
Test status
Simulation time 6121187928 ps
CPU time 11.56 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:50:52 PM PDT 24
Peak memory 211400 kb
Host smart-6a085ebd-7ed9-4c5c-a3cf-a63293ea5494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768194556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1768194556
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3018676558
Short name T13
Test name
Test status
Simulation time 6575991246 ps
CPU time 112.76 seconds
Started Jul 06 04:50:50 PM PDT 24
Finished Jul 06 04:52:43 PM PDT 24
Peak memory 236932 kb
Host smart-25b1a34e-79ba-442e-9a90-268ca8504126
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018676558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3018676558
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4109468560
Short name T365
Test name
Test status
Simulation time 3037997810 ps
CPU time 17.28 seconds
Started Jul 06 04:50:43 PM PDT 24
Finished Jul 06 04:51:01 PM PDT 24
Peak memory 211928 kb
Host smart-1cb22789-b379-45ec-8805-ce590d1e2caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109468560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4109468560
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.229626596
Short name T11
Test name
Test status
Simulation time 2927330596 ps
CPU time 9.56 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:46 PM PDT 24
Peak memory 211364 kb
Host smart-9c298b10-72df-47de-ae30-46222ca4e4b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229626596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.229626596
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.570217343
Short name T242
Test name
Test status
Simulation time 22097495132 ps
CPU time 20.54 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:51:01 PM PDT 24
Peak memory 213860 kb
Host smart-109c5775-dea2-4348-b4f5-cc18918a50dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570217343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.570217343
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4005867345
Short name T23
Test name
Test status
Simulation time 333298204 ps
CPU time 15.95 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:50:54 PM PDT 24
Peak memory 213232 kb
Host smart-e29cfdbe-3f0a-4d9a-8b71-42917a21c4e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005867345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4005867345
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3834308588
Short name T213
Test name
Test status
Simulation time 16294235595 ps
CPU time 9.56 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:50:48 PM PDT 24
Peak memory 211308 kb
Host smart-8ebc82d7-a813-480b-aaa9-7af964107d01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834308588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3834308588
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1642445901
Short name T61
Test name
Test status
Simulation time 3940918069 ps
CPU time 113.44 seconds
Started Jul 06 04:50:32 PM PDT 24
Finished Jul 06 04:52:26 PM PDT 24
Peak memory 238924 kb
Host smart-91ab476f-99c3-4d38-a470-b6a07e885b8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642445901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1642445901
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2075398170
Short name T237
Test name
Test status
Simulation time 38594967651 ps
CPU time 28.62 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:51:09 PM PDT 24
Peak memory 212264 kb
Host smart-f31b654b-a461-4e3d-b96e-f1297345f1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075398170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2075398170
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.951576367
Short name T130
Test name
Test status
Simulation time 3415672945 ps
CPU time 9.85 seconds
Started Jul 06 04:50:46 PM PDT 24
Finished Jul 06 04:50:57 PM PDT 24
Peak memory 211368 kb
Host smart-09de597d-5235-498c-a9df-f179f37bb488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951576367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.951576367
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3460349652
Short name T27
Test name
Test status
Simulation time 2071403298 ps
CPU time 61.2 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:51:40 PM PDT 24
Peak memory 237568 kb
Host smart-dfba9d08-343e-4627-a6f3-b50468599443
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460349652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3460349652
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2404257507
Short name T58
Test name
Test status
Simulation time 7302462903 ps
CPU time 24.93 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:51:01 PM PDT 24
Peak memory 213788 kb
Host smart-40ce47de-1f8e-41e9-a8e4-05c8ff150ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404257507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2404257507
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.303151130
Short name T168
Test name
Test status
Simulation time 22741365604 ps
CPU time 48.48 seconds
Started Jul 06 04:50:40 PM PDT 24
Finished Jul 06 04:51:30 PM PDT 24
Peak memory 219324 kb
Host smart-7c14e05c-a32f-4e54-9df8-c23c5e084cf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303151130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.303151130
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2704428166
Short name T71
Test name
Test status
Simulation time 6744225756 ps
CPU time 14.47 seconds
Started Jul 06 04:50:43 PM PDT 24
Finished Jul 06 04:50:58 PM PDT 24
Peak memory 211312 kb
Host smart-35f21df4-7017-4553-adb3-39093592655f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704428166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2704428166
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.55122295
Short name T247
Test name
Test status
Simulation time 20364667369 ps
CPU time 209.06 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:54:17 PM PDT 24
Peak memory 236816 kb
Host smart-916ca5c7-8ba1-4930-a896-341a5701f4f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55122295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_co
rrupt_sig_fatal_chk.55122295
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2320019006
Short name T280
Test name
Test status
Simulation time 1956538675 ps
CPU time 20.09 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:51:08 PM PDT 24
Peak memory 212140 kb
Host smart-9142b399-8363-4e1b-bb33-0899a4e01436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320019006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2320019006
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4050102136
Short name T145
Test name
Test status
Simulation time 366998590 ps
CPU time 5.45 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 04:50:48 PM PDT 24
Peak memory 211316 kb
Host smart-032992a9-61d4-4f3b-af73-c44d57847586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050102136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4050102136
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2243916778
Short name T161
Test name
Test status
Simulation time 190521375 ps
CPU time 10.13 seconds
Started Jul 06 04:50:33 PM PDT 24
Finished Jul 06 04:50:43 PM PDT 24
Peak memory 213452 kb
Host smart-d17515c7-690e-4443-bf9f-6f9c4f4b68f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243916778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2243916778
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1452618544
Short name T194
Test name
Test status
Simulation time 529322520 ps
CPU time 17.75 seconds
Started Jul 06 04:50:45 PM PDT 24
Finished Jul 06 04:51:03 PM PDT 24
Peak memory 215388 kb
Host smart-ea92bf68-13ad-4b1d-88f1-5c00db0a216c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452618544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1452618544
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.893573712
Short name T275
Test name
Test status
Simulation time 3045186051 ps
CPU time 12.89 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:50 PM PDT 24
Peak memory 211412 kb
Host smart-29035880-1ba1-4f9c-9811-efad3e893590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893573712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.893573712
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3885086007
Short name T218
Test name
Test status
Simulation time 16131807833 ps
CPU time 190.95 seconds
Started Jul 06 04:50:33 PM PDT 24
Finished Jul 06 04:53:44 PM PDT 24
Peak memory 237776 kb
Host smart-7a45cc6a-e7bd-4d80-aebe-1924bfdf0f89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885086007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3885086007
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3972194825
Short name T321
Test name
Test status
Simulation time 1647282091 ps
CPU time 19.76 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:51:02 PM PDT 24
Peak memory 211840 kb
Host smart-0df578d3-e3da-4e57-9857-87c918e5cb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972194825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3972194825
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3404311821
Short name T155
Test name
Test status
Simulation time 2636455332 ps
CPU time 12.9 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:51:00 PM PDT 24
Peak memory 211388 kb
Host smart-128f331d-ea21-42f2-83b1-2e6421e289a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404311821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3404311821
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.312582065
Short name T223
Test name
Test status
Simulation time 4115307577 ps
CPU time 20.53 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:51:08 PM PDT 24
Peak memory 213344 kb
Host smart-31c3b0dc-b9a0-43de-829b-a6a72557656b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312582065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.312582065
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.576678980
Short name T356
Test name
Test status
Simulation time 18137642521 ps
CPU time 736.63 seconds
Started Jul 06 04:51:01 PM PDT 24
Finished Jul 06 05:03:18 PM PDT 24
Peak memory 235772 kb
Host smart-db4b157c-afd9-413d-a693-5174e0af84a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576678980 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.576678980
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.877468659
Short name T150
Test name
Test status
Simulation time 11397121357 ps
CPU time 8.08 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 04:50:51 PM PDT 24
Peak memory 211332 kb
Host smart-6e21ac2b-0005-4cd0-98de-8b11955582f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877468659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.877468659
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4239760224
Short name T315
Test name
Test status
Simulation time 142958390631 ps
CPU time 347.01 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:56:34 PM PDT 24
Peak memory 213608 kb
Host smart-2fe44e10-f7a2-45e6-8fe5-9de0af275a74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239760224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4239760224
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1036024039
Short name T193
Test name
Test status
Simulation time 1630986022 ps
CPU time 19.6 seconds
Started Jul 06 04:50:50 PM PDT 24
Finished Jul 06 04:51:09 PM PDT 24
Peak memory 211772 kb
Host smart-fa4371e3-99b1-44bf-80ba-335ec3269be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036024039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1036024039
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2727139914
Short name T152
Test name
Test status
Simulation time 828940625 ps
CPU time 7.02 seconds
Started Jul 06 04:50:44 PM PDT 24
Finished Jul 06 04:50:51 PM PDT 24
Peak memory 211280 kb
Host smart-14d24d66-f70c-47cd-af87-04ac7dbcb3f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727139914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2727139914
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1311257000
Short name T83
Test name
Test status
Simulation time 2375300075 ps
CPU time 14.91 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:50:57 PM PDT 24
Peak memory 213380 kb
Host smart-4e0ee3d5-7a2f-49a3-9194-fc23ff0d0209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311257000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1311257000
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1161991539
Short name T221
Test name
Test status
Simulation time 2581894832 ps
CPU time 27.64 seconds
Started Jul 06 04:50:50 PM PDT 24
Finished Jul 06 04:51:18 PM PDT 24
Peak memory 214456 kb
Host smart-1f1472a4-5702-48b0-9002-dd49b28b51fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161991539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1161991539
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2335418065
Short name T329
Test name
Test status
Simulation time 182245988204 ps
CPU time 1718.26 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 05:19:21 PM PDT 24
Peak memory 233452 kb
Host smart-cba06bff-57a1-4d14-985f-2eb605b15452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335418065 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2335418065
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1489677021
Short name T313
Test name
Test status
Simulation time 343886273 ps
CPU time 5.45 seconds
Started Jul 06 04:50:57 PM PDT 24
Finished Jul 06 04:51:03 PM PDT 24
Peak memory 211256 kb
Host smart-5a2e7190-3b60-42b6-821f-e19531a358ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489677021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1489677021
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1401170261
Short name T203
Test name
Test status
Simulation time 200453926106 ps
CPU time 493.88 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:58:55 PM PDT 24
Peak memory 235460 kb
Host smart-40915b89-4902-4cd9-9f93-34ab183335ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401170261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1401170261
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3345594033
Short name T318
Test name
Test status
Simulation time 5799169915 ps
CPU time 18.81 seconds
Started Jul 06 04:50:52 PM PDT 24
Finished Jul 06 04:51:11 PM PDT 24
Peak memory 212156 kb
Host smart-a3f0ba14-eadd-4685-9c2b-4b0fcb3e5daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345594033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3345594033
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1954987252
Short name T125
Test name
Test status
Simulation time 7268421934 ps
CPU time 15.86 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:50:58 PM PDT 24
Peak memory 211380 kb
Host smart-70b8f184-dfd9-4351-9e86-dc34e2d53b1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954987252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1954987252
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3772330311
Short name T269
Test name
Test status
Simulation time 11222127312 ps
CPU time 39.34 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:51:27 PM PDT 24
Peak memory 213880 kb
Host smart-2c6031ef-366f-47ad-8f1d-24b94ff278d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772330311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3772330311
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3240547168
Short name T216
Test name
Test status
Simulation time 799968235 ps
CPU time 20.92 seconds
Started Jul 06 04:50:50 PM PDT 24
Finished Jul 06 04:51:11 PM PDT 24
Peak memory 213540 kb
Host smart-045a0400-a442-462c-97b6-332fc3320c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240547168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3240547168
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.873380544
Short name T287
Test name
Test status
Simulation time 7826115852 ps
CPU time 16.12 seconds
Started Jul 06 04:50:43 PM PDT 24
Finished Jul 06 04:51:00 PM PDT 24
Peak memory 211324 kb
Host smart-e557ff10-fa56-4305-89d5-bc6482334a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873380544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.873380544
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4197384183
Short name T249
Test name
Test status
Simulation time 61054540871 ps
CPU time 185.93 seconds
Started Jul 06 04:50:57 PM PDT 24
Finished Jul 06 04:54:03 PM PDT 24
Peak memory 212568 kb
Host smart-79d472c7-ea43-4c6c-b586-1078a59122ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197384183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4197384183
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1352236851
Short name T178
Test name
Test status
Simulation time 14358639097 ps
CPU time 30.22 seconds
Started Jul 06 04:51:02 PM PDT 24
Finished Jul 06 04:51:33 PM PDT 24
Peak memory 215212 kb
Host smart-9f19f41f-195b-4f98-835f-fc3ea029ebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352236851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1352236851
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1979343260
Short name T235
Test name
Test status
Simulation time 2419953329 ps
CPU time 18.19 seconds
Started Jul 06 04:50:48 PM PDT 24
Finished Jul 06 04:51:07 PM PDT 24
Peak memory 211836 kb
Host smart-04d451cc-f731-4e43-aa9b-3fc64d2f6280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979343260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1979343260
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.119084601
Short name T24
Test name
Test status
Simulation time 11832042867 ps
CPU time 39.68 seconds
Started Jul 06 04:50:56 PM PDT 24
Finished Jul 06 04:51:36 PM PDT 24
Peak memory 216996 kb
Host smart-9fe9078e-d5e5-404c-8926-3d266d14ef67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119084601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.119084601
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3838064524
Short name T300
Test name
Test status
Simulation time 249084876 ps
CPU time 6.05 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 04:50:49 PM PDT 24
Peak memory 211360 kb
Host smart-4dbca52d-d702-40ff-959d-f88a4f037654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838064524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3838064524
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.856678492
Short name T47
Test name
Test status
Simulation time 37206526015 ps
CPU time 220.84 seconds
Started Jul 06 04:50:49 PM PDT 24
Finished Jul 06 04:54:30 PM PDT 24
Peak memory 228532 kb
Host smart-5cef973d-df73-46c6-8855-5a0e4044a4d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856678492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.856678492
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2357098404
Short name T179
Test name
Test status
Simulation time 3062906796 ps
CPU time 10.39 seconds
Started Jul 06 04:51:00 PM PDT 24
Finished Jul 06 04:51:17 PM PDT 24
Peak memory 211396 kb
Host smart-b0cdc219-33d6-4f2f-8a06-d484a5876fda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357098404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2357098404
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1562302149
Short name T210
Test name
Test status
Simulation time 2050892490 ps
CPU time 22.9 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 04:51:06 PM PDT 24
Peak memory 213680 kb
Host smart-a9271ea1-a12e-4172-aa41-eaf4ed27ab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562302149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1562302149
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.165254555
Short name T148
Test name
Test status
Simulation time 175442357 ps
CPU time 4.18 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:50:46 PM PDT 24
Peak memory 211324 kb
Host smart-20a333fe-a96e-4ed1-8b45-58757db86e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165254555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.165254555
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1446113251
Short name T217
Test name
Test status
Simulation time 6931486607 ps
CPU time 120.3 seconds
Started Jul 06 04:50:45 PM PDT 24
Finished Jul 06 04:52:45 PM PDT 24
Peak memory 232644 kb
Host smart-a8555625-3c62-4a46-ad45-02bdfab089f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446113251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1446113251
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3923347983
Short name T266
Test name
Test status
Simulation time 12169653048 ps
CPU time 26.74 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:51:07 PM PDT 24
Peak memory 212280 kb
Host smart-ddd8f94d-1a17-4555-a38e-2f5cade51ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923347983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3923347983
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2655759871
Short name T51
Test name
Test status
Simulation time 2278171826 ps
CPU time 14.15 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:51:02 PM PDT 24
Peak memory 211388 kb
Host smart-de68311a-8a59-4ccf-8739-21563374dcc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2655759871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2655759871
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2491727535
Short name T41
Test name
Test status
Simulation time 193574932 ps
CPU time 9.96 seconds
Started Jul 06 04:51:01 PM PDT 24
Finished Jul 06 04:51:12 PM PDT 24
Peak memory 213408 kb
Host smart-5a86f572-ae6f-44af-8ab4-4c0214de4a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491727535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2491727535
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2805938873
Short name T234
Test name
Test status
Simulation time 932718543 ps
CPU time 24.83 seconds
Started Jul 06 04:50:51 PM PDT 24
Finished Jul 06 04:51:16 PM PDT 24
Peak memory 215656 kb
Host smart-e0ef157b-55ac-4d85-bef4-f8a58a99d337
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805938873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2805938873
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1033386660
Short name T270
Test name
Test status
Simulation time 1684125501 ps
CPU time 6.53 seconds
Started Jul 06 04:50:48 PM PDT 24
Finished Jul 06 04:50:54 PM PDT 24
Peak memory 211296 kb
Host smart-772aad48-176c-4679-a3a3-2cfd67d59342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033386660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1033386660
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1729052132
Short name T334
Test name
Test status
Simulation time 5814927230 ps
CPU time 26.95 seconds
Started Jul 06 04:50:44 PM PDT 24
Finished Jul 06 04:51:12 PM PDT 24
Peak memory 212204 kb
Host smart-29aaf304-f73a-4542-8e2c-41ae25e2ccd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729052132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1729052132
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1987978522
Short name T128
Test name
Test status
Simulation time 2248936698 ps
CPU time 11.24 seconds
Started Jul 06 04:50:52 PM PDT 24
Finished Jul 06 04:51:03 PM PDT 24
Peak memory 211380 kb
Host smart-1b6e602e-8aac-460c-a38f-854aad1bdb17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987978522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1987978522
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.368196344
Short name T243
Test name
Test status
Simulation time 4009737100 ps
CPU time 37.93 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:51:20 PM PDT 24
Peak memory 213560 kb
Host smart-cde9e609-a219-4de2-9020-f9901eb7f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368196344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.368196344
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3935382410
Short name T271
Test name
Test status
Simulation time 21074360170 ps
CPU time 84.76 seconds
Started Jul 06 04:50:44 PM PDT 24
Finished Jul 06 04:52:09 PM PDT 24
Peak memory 219312 kb
Host smart-82285afe-436f-49ee-9247-1f15313ece90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935382410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3935382410
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1537926732
Short name T306
Test name
Test status
Simulation time 12027034400 ps
CPU time 16 seconds
Started Jul 06 04:50:45 PM PDT 24
Finished Jul 06 04:51:01 PM PDT 24
Peak memory 211348 kb
Host smart-fe8ae216-d963-448d-9f28-0604205b17d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537926732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1537926732
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2263234721
Short name T246
Test name
Test status
Simulation time 51522361634 ps
CPU time 340.26 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:56:22 PM PDT 24
Peak memory 234884 kb
Host smart-1f76943a-df0a-46eb-8c71-784b3f953124
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263234721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2263234721
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3656994431
Short name T357
Test name
Test status
Simulation time 4897459586 ps
CPU time 17.53 seconds
Started Jul 06 04:51:00 PM PDT 24
Finished Jul 06 04:51:17 PM PDT 24
Peak memory 212296 kb
Host smart-2dd339fa-085f-4c71-9832-1708be296874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656994431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3656994431
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3278289259
Short name T141
Test name
Test status
Simulation time 4145240644 ps
CPU time 17.03 seconds
Started Jul 06 04:50:45 PM PDT 24
Finished Jul 06 04:51:02 PM PDT 24
Peak memory 211420 kb
Host smart-cb2206a9-12a7-4819-8936-756bc6875a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3278289259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3278289259
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2520707931
Short name T6
Test name
Test status
Simulation time 3094329750 ps
CPU time 15.46 seconds
Started Jul 06 04:50:59 PM PDT 24
Finished Jul 06 04:51:15 PM PDT 24
Peak memory 213356 kb
Host smart-a73ac539-e778-46d0-b83d-8ddb35d8ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520707931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2520707931
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3180986443
Short name T346
Test name
Test status
Simulation time 4718180885 ps
CPU time 49.3 seconds
Started Jul 06 04:50:52 PM PDT 24
Finished Jul 06 04:51:42 PM PDT 24
Peak memory 217176 kb
Host smart-f07d9ad7-3056-41a6-99df-f7216974febf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180986443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3180986443
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3196392084
Short name T185
Test name
Test status
Simulation time 87106155 ps
CPU time 4.26 seconds
Started Jul 06 04:50:54 PM PDT 24
Finished Jul 06 04:50:59 PM PDT 24
Peak memory 211308 kb
Host smart-1231f840-a453-4e93-97ac-4f03537309bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196392084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3196392084
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1792362910
Short name T46
Test name
Test status
Simulation time 35370351819 ps
CPU time 345.41 seconds
Started Jul 06 04:50:45 PM PDT 24
Finished Jul 06 04:56:31 PM PDT 24
Peak memory 228620 kb
Host smart-33abcb11-0f63-41a3-b8c1-b3abc68aa9a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792362910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1792362910
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4116115455
Short name T147
Test name
Test status
Simulation time 1150090434 ps
CPU time 5.65 seconds
Started Jul 06 04:50:59 PM PDT 24
Finished Jul 06 04:51:05 PM PDT 24
Peak memory 211324 kb
Host smart-866b04c5-61c8-4a0d-a577-34ae5fc74d66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116115455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4116115455
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.4011446426
Short name T344
Test name
Test status
Simulation time 185875394 ps
CPU time 10.29 seconds
Started Jul 06 04:50:59 PM PDT 24
Finished Jul 06 04:51:10 PM PDT 24
Peak memory 213464 kb
Host smart-d7f5733b-0219-4e4c-8f17-2ec45c2d82cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011446426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.4011446426
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2135258696
Short name T265
Test name
Test status
Simulation time 13148447394 ps
CPU time 56.54 seconds
Started Jul 06 04:50:46 PM PDT 24
Finished Jul 06 04:51:43 PM PDT 24
Peak memory 216320 kb
Host smart-d4bc9d14-b026-4451-9581-9cc9ea92931c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135258696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2135258696
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.75720803
Short name T212
Test name
Test status
Simulation time 3207593560 ps
CPU time 10.17 seconds
Started Jul 06 04:50:44 PM PDT 24
Finished Jul 06 04:50:54 PM PDT 24
Peak memory 211272 kb
Host smart-1552a635-a1cd-483a-8bae-ff82ebb79d3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75720803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.75720803
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1978878242
Short name T170
Test name
Test status
Simulation time 2448651548 ps
CPU time 143.57 seconds
Started Jul 06 04:50:34 PM PDT 24
Finished Jul 06 04:52:58 PM PDT 24
Peak memory 225088 kb
Host smart-2da80967-4d05-4eeb-a0de-06f2bf3ad701
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978878242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1978878242
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.558187982
Short name T345
Test name
Test status
Simulation time 911971648 ps
CPU time 15.62 seconds
Started Jul 06 04:50:38 PM PDT 24
Finished Jul 06 04:50:55 PM PDT 24
Peak memory 211836 kb
Host smart-01387ab6-eb5a-4ac0-ad54-539c6e595df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558187982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.558187982
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1059625517
Short name T298
Test name
Test status
Simulation time 2098474197 ps
CPU time 11.71 seconds
Started Jul 06 04:50:33 PM PDT 24
Finished Jul 06 04:50:45 PM PDT 24
Peak memory 211336 kb
Host smart-41659e0d-7942-4b47-bada-807b2aebff21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059625517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1059625517
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.626119998
Short name T29
Test name
Test status
Simulation time 7583676706 ps
CPU time 106.66 seconds
Started Jul 06 04:50:49 PM PDT 24
Finished Jul 06 04:52:36 PM PDT 24
Peak memory 237516 kb
Host smart-ce6562c2-c974-4170-a7cf-964181fbfd21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626119998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.626119998
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2037297309
Short name T188
Test name
Test status
Simulation time 2033826386 ps
CPU time 16.17 seconds
Started Jul 06 04:50:40 PM PDT 24
Finished Jul 06 04:50:57 PM PDT 24
Peak memory 211796 kb
Host smart-c84ef390-4ea8-4a20-a209-95015aaf8a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037297309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2037297309
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3539056935
Short name T304
Test name
Test status
Simulation time 5367572399 ps
CPU time 42.98 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:51:22 PM PDT 24
Peak memory 219332 kb
Host smart-85a6b2ea-563c-448f-96dc-331387484aaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539056935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3539056935
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.155234060
Short name T319
Test name
Test status
Simulation time 346261225 ps
CPU time 4.29 seconds
Started Jul 06 04:50:59 PM PDT 24
Finished Jul 06 04:51:03 PM PDT 24
Peak memory 211188 kb
Host smart-57427a63-9f01-4368-a014-2db15b64d343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155234060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.155234060
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3725311118
Short name T44
Test name
Test status
Simulation time 28454502703 ps
CPU time 310.86 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:55:59 PM PDT 24
Peak memory 216740 kb
Host smart-e1955e54-c600-40f2-87c6-40321e86729e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725311118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3725311118
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.402841028
Short name T337
Test name
Test status
Simulation time 364130995 ps
CPU time 9.56 seconds
Started Jul 06 04:50:58 PM PDT 24
Finished Jul 06 04:51:07 PM PDT 24
Peak memory 212368 kb
Host smart-00c652fd-6077-46df-8cc2-e9ae11577c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402841028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.402841028
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1864523670
Short name T25
Test name
Test status
Simulation time 8529526292 ps
CPU time 16.92 seconds
Started Jul 06 04:50:44 PM PDT 24
Finished Jul 06 04:51:02 PM PDT 24
Peak memory 211380 kb
Host smart-340aba32-15f1-4676-b635-0870b39b0c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864523670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1864523670
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2141525367
Short name T175
Test name
Test status
Simulation time 7067153861 ps
CPU time 29.4 seconds
Started Jul 06 04:50:59 PM PDT 24
Finished Jul 06 04:51:29 PM PDT 24
Peak memory 213852 kb
Host smart-d79b44f8-c5cd-4767-92d1-c28e6a21154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141525367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2141525367
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.451900156
Short name T332
Test name
Test status
Simulation time 26654022303 ps
CPU time 68.32 seconds
Started Jul 06 04:50:57 PM PDT 24
Finished Jul 06 04:52:06 PM PDT 24
Peak memory 219248 kb
Host smart-4fecb5e6-7f70-4551-b660-cc58d084850b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451900156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.451900156
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1059744910
Short name T173
Test name
Test status
Simulation time 31636084010 ps
CPU time 16.57 seconds
Started Jul 06 04:50:55 PM PDT 24
Finished Jul 06 04:51:12 PM PDT 24
Peak memory 211368 kb
Host smart-dbfa2624-2458-4134-b01d-a029a2e53cfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059744910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1059744910
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3752991112
Short name T45
Test name
Test status
Simulation time 13094268698 ps
CPU time 157.08 seconds
Started Jul 06 04:50:49 PM PDT 24
Finished Jul 06 04:53:27 PM PDT 24
Peak memory 233868 kb
Host smart-7c3369c4-2139-4ad2-8fb9-fc32c68c09b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752991112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3752991112
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.335476581
Short name T177
Test name
Test status
Simulation time 3921380092 ps
CPU time 32.58 seconds
Started Jul 06 04:51:01 PM PDT 24
Finished Jul 06 04:51:34 PM PDT 24
Peak memory 211872 kb
Host smart-ab04b705-694d-426a-a9bc-83e378a317e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335476581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.335476581
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.614857736
Short name T327
Test name
Test status
Simulation time 2428987894 ps
CPU time 9.37 seconds
Started Jul 06 04:50:51 PM PDT 24
Finished Jul 06 04:51:01 PM PDT 24
Peak memory 211444 kb
Host smart-ad995dce-307c-4cd9-bf7e-ea8725416294
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614857736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.614857736
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3649217512
Short name T240
Test name
Test status
Simulation time 10337798099 ps
CPU time 24.48 seconds
Started Jul 06 04:50:58 PM PDT 24
Finished Jul 06 04:51:23 PM PDT 24
Peak memory 213384 kb
Host smart-511d604d-f914-4b81-aed6-9ed6f5d06c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649217512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3649217512
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1673829917
Short name T299
Test name
Test status
Simulation time 9624729956 ps
CPU time 23.14 seconds
Started Jul 06 04:51:04 PM PDT 24
Finished Jul 06 04:51:27 PM PDT 24
Peak memory 211552 kb
Host smart-e418a05f-3259-4108-ae4b-a7a87a6748eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673829917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1673829917
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.416310372
Short name T164
Test name
Test status
Simulation time 1243842143 ps
CPU time 11.53 seconds
Started Jul 06 04:51:01 PM PDT 24
Finished Jul 06 04:51:13 PM PDT 24
Peak memory 211256 kb
Host smart-433bf98e-c0da-48f8-a8af-5b65f47d26ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416310372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.416310372
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4002150545
Short name T137
Test name
Test status
Simulation time 2314475355 ps
CPU time 114.81 seconds
Started Jul 06 04:51:00 PM PDT 24
Finished Jul 06 04:52:55 PM PDT 24
Peak memory 233728 kb
Host smart-df017753-3222-4394-ba4e-7188ad22ffab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002150545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4002150545
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1849113720
Short name T359
Test name
Test status
Simulation time 2365129039 ps
CPU time 9.31 seconds
Started Jul 06 04:51:02 PM PDT 24
Finished Jul 06 04:51:12 PM PDT 24
Peak memory 212024 kb
Host smart-119fea9c-66fa-44db-9390-1f496b7eddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849113720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1849113720
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.327617213
Short name T289
Test name
Test status
Simulation time 2134096715 ps
CPU time 18.58 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:51:06 PM PDT 24
Peak memory 211316 kb
Host smart-39becb94-6dc1-47a5-b350-66a22705db9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=327617213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.327617213
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3291161309
Short name T239
Test name
Test status
Simulation time 189392820 ps
CPU time 10.26 seconds
Started Jul 06 04:50:57 PM PDT 24
Finished Jul 06 04:51:08 PM PDT 24
Peak memory 213252 kb
Host smart-a316214c-10bc-42f8-88da-8d3ee7cfb2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291161309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3291161309
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.384275205
Short name T132
Test name
Test status
Simulation time 5264855016 ps
CPU time 18.44 seconds
Started Jul 06 04:50:56 PM PDT 24
Finished Jul 06 04:51:15 PM PDT 24
Peak memory 211376 kb
Host smart-45718994-f386-4923-b05f-16b4ce8ad2ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384275205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.384275205
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2149967819
Short name T308
Test name
Test status
Simulation time 1756474324 ps
CPU time 7.43 seconds
Started Jul 06 04:50:43 PM PDT 24
Finished Jul 06 04:50:51 PM PDT 24
Peak memory 211308 kb
Host smart-4656f874-90ed-4c6a-819a-0867b4f57712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149967819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2149967819
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3916611289
Short name T274
Test name
Test status
Simulation time 69828619439 ps
CPU time 341.42 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:56:29 PM PDT 24
Peak memory 236812 kb
Host smart-8edace87-05a7-4598-b913-ec831ff46fd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916611289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3916611289
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3729536410
Short name T296
Test name
Test status
Simulation time 3009109766 ps
CPU time 18.41 seconds
Started Jul 06 04:50:46 PM PDT 24
Finished Jul 06 04:51:04 PM PDT 24
Peak memory 212340 kb
Host smart-e911233c-d88f-4a73-9cf8-e703a48db97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729536410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3729536410
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2276238483
Short name T343
Test name
Test status
Simulation time 267402083 ps
CPU time 7.22 seconds
Started Jul 06 04:51:03 PM PDT 24
Finished Jul 06 04:51:11 PM PDT 24
Peak memory 211404 kb
Host smart-9b54a2e6-eba0-45fb-82cc-c87b042fe7ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2276238483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2276238483
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1397609053
Short name T255
Test name
Test status
Simulation time 22731321918 ps
CPU time 36.04 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:51:24 PM PDT 24
Peak memory 213912 kb
Host smart-48fa7d4b-e727-4c59-b4c2-05ab9106ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397609053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1397609053
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.108735965
Short name T303
Test name
Test status
Simulation time 5498850903 ps
CPU time 53.49 seconds
Started Jul 06 04:50:58 PM PDT 24
Finished Jul 06 04:51:52 PM PDT 24
Peak memory 216976 kb
Host smart-b75e07a3-e85c-4120-b700-2e4616c234c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108735965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.108735965
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3372667846
Short name T259
Test name
Test status
Simulation time 1788840216 ps
CPU time 9.16 seconds
Started Jul 06 04:51:08 PM PDT 24
Finished Jul 06 04:51:17 PM PDT 24
Peak memory 211272 kb
Host smart-4305c388-42b1-4ce4-9993-7652dad17447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372667846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3372667846
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1987308345
Short name T340
Test name
Test status
Simulation time 1391655368 ps
CPU time 50.32 seconds
Started Jul 06 04:50:52 PM PDT 24
Finished Jul 06 04:51:43 PM PDT 24
Peak memory 237764 kb
Host smart-cdd8fba5-27b3-4c9d-b60f-4b041d9af8ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987308345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1987308345
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1761966721
Short name T165
Test name
Test status
Simulation time 9066126512 ps
CPU time 19.4 seconds
Started Jul 06 04:50:51 PM PDT 24
Finished Jul 06 04:51:11 PM PDT 24
Peak memory 212528 kb
Host smart-38e53b9c-4b5b-47a9-b157-7a584eeb3d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761966721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1761966721
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3261787630
Short name T72
Test name
Test status
Simulation time 2015692119 ps
CPU time 16.57 seconds
Started Jul 06 04:50:51 PM PDT 24
Finished Jul 06 04:51:08 PM PDT 24
Peak memory 211320 kb
Host smart-7245c924-5210-4a57-a8f5-7423fd9cba53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261787630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3261787630
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.467439148
Short name T291
Test name
Test status
Simulation time 15045140813 ps
CPU time 32.5 seconds
Started Jul 06 04:50:57 PM PDT 24
Finished Jul 06 04:51:29 PM PDT 24
Peak memory 214200 kb
Host smart-1aa92de2-a1a6-4016-ad44-6d524d336aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467439148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.467439148
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2545672538
Short name T195
Test name
Test status
Simulation time 2196754435 ps
CPU time 17.69 seconds
Started Jul 06 04:51:05 PM PDT 24
Finished Jul 06 04:51:23 PM PDT 24
Peak memory 211952 kb
Host smart-a13c6722-107a-43ad-9c50-1d8c0e6b207f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545672538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2545672538
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2657728389
Short name T59
Test name
Test status
Simulation time 1803144852 ps
CPU time 14.67 seconds
Started Jul 06 04:50:51 PM PDT 24
Finished Jul 06 04:51:06 PM PDT 24
Peak memory 211244 kb
Host smart-4b9d7c78-7a32-4c2d-8081-9fae5a9f950c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657728389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2657728389
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3037918204
Short name T124
Test name
Test status
Simulation time 50483574532 ps
CPU time 556.71 seconds
Started Jul 06 04:51:01 PM PDT 24
Finished Jul 06 05:00:18 PM PDT 24
Peak memory 228588 kb
Host smart-7d6802e4-08ac-47ed-919e-55c32af9957b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037918204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3037918204
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.631609142
Short name T50
Test name
Test status
Simulation time 170170740 ps
CPU time 9.66 seconds
Started Jul 06 04:50:50 PM PDT 24
Finished Jul 06 04:51:00 PM PDT 24
Peak memory 211932 kb
Host smart-66273da2-2c21-4209-9fc9-31baa6a35403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631609142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.631609142
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.366270126
Short name T5
Test name
Test status
Simulation time 6962749202 ps
CPU time 15.42 seconds
Started Jul 06 04:50:50 PM PDT 24
Finished Jul 06 04:51:06 PM PDT 24
Peak memory 211456 kb
Host smart-9c7b2dcb-227d-446e-8744-10d6a610463f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=366270126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.366270126
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2344220539
Short name T220
Test name
Test status
Simulation time 12094539184 ps
CPU time 20.4 seconds
Started Jul 06 04:51:01 PM PDT 24
Finished Jul 06 04:51:22 PM PDT 24
Peak memory 213528 kb
Host smart-bac280d2-b8c9-45b0-ab33-c498eaad17c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344220539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2344220539
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.285507727
Short name T348
Test name
Test status
Simulation time 4003637445 ps
CPU time 32.96 seconds
Started Jul 06 04:50:51 PM PDT 24
Finished Jul 06 04:51:24 PM PDT 24
Peak memory 215112 kb
Host smart-471d8dc6-09d7-4299-93cd-f807129dd3c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285507727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.285507727
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2987689355
Short name T19
Test name
Test status
Simulation time 292996661358 ps
CPU time 2262.72 seconds
Started Jul 06 04:50:59 PM PDT 24
Finished Jul 06 05:28:42 PM PDT 24
Peak memory 236636 kb
Host smart-6ceef7c1-95bb-46dd-9e65-343fcbf4e7bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987689355 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2987689355
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2277921122
Short name T199
Test name
Test status
Simulation time 4022286228 ps
CPU time 16.1 seconds
Started Jul 06 04:50:55 PM PDT 24
Finished Jul 06 04:51:12 PM PDT 24
Peak memory 211316 kb
Host smart-d8f57612-c5ba-4d3b-9b65-6a09a5ea82de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277921122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2277921122
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3897697447
Short name T142
Test name
Test status
Simulation time 6558824611 ps
CPU time 158.82 seconds
Started Jul 06 04:51:00 PM PDT 24
Finished Jul 06 04:53:39 PM PDT 24
Peak memory 237072 kb
Host smart-273f8267-c318-4d0c-8acc-d5f8f671cd7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897697447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3897697447
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.209139381
Short name T43
Test name
Test status
Simulation time 175540890 ps
CPU time 9.48 seconds
Started Jul 06 04:50:54 PM PDT 24
Finished Jul 06 04:51:03 PM PDT 24
Peak memory 211976 kb
Host smart-92b31ca5-c632-4ce6-a87d-e1ff2625e9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209139381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.209139381
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2082417939
Short name T273
Test name
Test status
Simulation time 94738184 ps
CPU time 5.61 seconds
Started Jul 06 04:50:54 PM PDT 24
Finished Jul 06 04:51:00 PM PDT 24
Peak memory 211324 kb
Host smart-0215b15f-0da2-45d4-af2e-f3f815b436a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082417939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2082417939
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2406404415
Short name T230
Test name
Test status
Simulation time 21114691125 ps
CPU time 31.93 seconds
Started Jul 06 04:51:00 PM PDT 24
Finished Jul 06 04:51:33 PM PDT 24
Peak memory 214116 kb
Host smart-3aab29fa-1e27-4d54-898a-864d87494dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406404415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2406404415
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1652698678
Short name T233
Test name
Test status
Simulation time 990748946 ps
CPU time 18.91 seconds
Started Jul 06 04:51:03 PM PDT 24
Finished Jul 06 04:51:22 PM PDT 24
Peak memory 212728 kb
Host smart-7b242cfa-cade-476e-9a65-c1a0ab83fd84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652698678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1652698678
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.838316671
Short name T57
Test name
Test status
Simulation time 133135514678 ps
CPU time 2447.05 seconds
Started Jul 06 04:50:50 PM PDT 24
Finished Jul 06 05:31:38 PM PDT 24
Peak memory 238524 kb
Host smart-18e4778c-1467-414d-ad39-3a48905de2a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838316671 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.838316671
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3001974113
Short name T286
Test name
Test status
Simulation time 700401890 ps
CPU time 5.44 seconds
Started Jul 06 04:50:56 PM PDT 24
Finished Jul 06 04:51:02 PM PDT 24
Peak memory 211288 kb
Host smart-bf04d0c4-dcdd-4072-bf4d-f0d716635613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001974113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3001974113
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.373379220
Short name T182
Test name
Test status
Simulation time 18087577197 ps
CPU time 198.45 seconds
Started Jul 06 04:51:05 PM PDT 24
Finished Jul 06 04:54:24 PM PDT 24
Peak memory 233816 kb
Host smart-f5682b2d-175f-4469-b145-1409e4f5e323
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373379220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.373379220
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2815309799
Short name T354
Test name
Test status
Simulation time 2987603858 ps
CPU time 27.37 seconds
Started Jul 06 04:50:55 PM PDT 24
Finished Jul 06 04:51:22 PM PDT 24
Peak memory 211772 kb
Host smart-95501218-b656-4804-bdbf-131484ca539a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815309799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2815309799
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3363368649
Short name T37
Test name
Test status
Simulation time 2198941796 ps
CPU time 17.44 seconds
Started Jul 06 04:50:57 PM PDT 24
Finished Jul 06 04:51:15 PM PDT 24
Peak memory 211464 kb
Host smart-0c2aa689-ee39-4f2a-b5c7-a093adb228d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3363368649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3363368649
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3306497300
Short name T351
Test name
Test status
Simulation time 7960666530 ps
CPU time 21.92 seconds
Started Jul 06 04:51:13 PM PDT 24
Finished Jul 06 04:51:35 PM PDT 24
Peak memory 213252 kb
Host smart-88f1bef3-f01c-4744-aa8e-4d84aaf94b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306497300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3306497300
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4031095493
Short name T330
Test name
Test status
Simulation time 29872356459 ps
CPU time 76.54 seconds
Started Jul 06 04:50:55 PM PDT 24
Finished Jul 06 04:52:12 PM PDT 24
Peak memory 219336 kb
Host smart-2ff2db64-01ed-4ff9-875e-497b86fb8a83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031095493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4031095493
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3290941244
Short name T110
Test name
Test status
Simulation time 50402249127 ps
CPU time 2060.6 seconds
Started Jul 06 04:50:51 PM PDT 24
Finished Jul 06 05:25:12 PM PDT 24
Peak memory 237052 kb
Host smart-b904644d-def4-4c45-8a6c-35d095b0a2d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290941244 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3290941244
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1568185455
Short name T324
Test name
Test status
Simulation time 1547941930 ps
CPU time 6.85 seconds
Started Jul 06 04:51:05 PM PDT 24
Finished Jul 06 04:51:12 PM PDT 24
Peak memory 211372 kb
Host smart-def80ec4-31ec-45e1-ac87-216da7465d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568185455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1568185455
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3440047559
Short name T219
Test name
Test status
Simulation time 3232450033 ps
CPU time 59.42 seconds
Started Jul 06 04:51:03 PM PDT 24
Finished Jul 06 04:52:03 PM PDT 24
Peak memory 237768 kb
Host smart-60037bcd-9eeb-41f2-a415-3d06a1eb3209
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440047559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3440047559
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.141758492
Short name T260
Test name
Test status
Simulation time 24743458000 ps
CPU time 31.65 seconds
Started Jul 06 04:51:08 PM PDT 24
Finished Jul 06 04:51:40 PM PDT 24
Peak memory 212100 kb
Host smart-1c7d28da-99b4-4e29-8bbe-5f6a4ff6f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141758492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.141758492
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1496281929
Short name T228
Test name
Test status
Simulation time 1254568550 ps
CPU time 9.36 seconds
Started Jul 06 04:50:56 PM PDT 24
Finished Jul 06 04:51:06 PM PDT 24
Peak memory 211372 kb
Host smart-ea3bf990-5229-4f4f-884d-1359b02b899b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496281929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1496281929
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2976078266
Short name T292
Test name
Test status
Simulation time 3324590152 ps
CPU time 15.81 seconds
Started Jul 06 04:51:12 PM PDT 24
Finished Jul 06 04:51:28 PM PDT 24
Peak memory 213628 kb
Host smart-919782ce-65e0-4f6f-9664-c7b5d7064359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976078266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2976078266
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2458489075
Short name T197
Test name
Test status
Simulation time 10866547560 ps
CPU time 64.63 seconds
Started Jul 06 04:51:05 PM PDT 24
Finished Jul 06 04:52:10 PM PDT 24
Peak memory 219316 kb
Host smart-6601a98b-62cb-4aff-b05b-902db3cf26bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458489075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2458489075
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2453283768
Short name T331
Test name
Test status
Simulation time 5680149462 ps
CPU time 12.9 seconds
Started Jul 06 04:51:03 PM PDT 24
Finished Jul 06 04:51:17 PM PDT 24
Peak memory 211428 kb
Host smart-6aab29d4-eb2a-43da-bd31-c3a54e73bb9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453283768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2453283768
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.455898316
Short name T350
Test name
Test status
Simulation time 25467295096 ps
CPU time 153.77 seconds
Started Jul 06 04:51:06 PM PDT 24
Finished Jul 06 04:53:41 PM PDT 24
Peak memory 227752 kb
Host smart-63bf9098-8223-42e7-94bd-30c4710fdc3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455898316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.455898316
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1778634748
Short name T207
Test name
Test status
Simulation time 3451497265 ps
CPU time 20.66 seconds
Started Jul 06 04:51:03 PM PDT 24
Finished Jul 06 04:51:24 PM PDT 24
Peak memory 211376 kb
Host smart-856753df-2674-4564-9a33-32536f427e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778634748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1778634748
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.534869668
Short name T157
Test name
Test status
Simulation time 5368613447 ps
CPU time 13.66 seconds
Started Jul 06 04:51:05 PM PDT 24
Finished Jul 06 04:51:20 PM PDT 24
Peak memory 211468 kb
Host smart-82e3753a-ec1d-4fa8-a4d9-dd8520dc089b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534869668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.534869668
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3017933530
Short name T226
Test name
Test status
Simulation time 14139827858 ps
CPU time 25.22 seconds
Started Jul 06 04:51:00 PM PDT 24
Finished Jul 06 04:51:25 PM PDT 24
Peak memory 214112 kb
Host smart-86c89254-a9ee-4f42-8445-a3a880fccf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017933530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3017933530
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3634434102
Short name T305
Test name
Test status
Simulation time 8923760215 ps
CPU time 20.29 seconds
Started Jul 06 04:51:02 PM PDT 24
Finished Jul 06 04:51:23 PM PDT 24
Peak memory 212424 kb
Host smart-26e909ed-b7f7-4179-9161-b83f8813612c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634434102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3634434102
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.911228237
Short name T224
Test name
Test status
Simulation time 4372025600 ps
CPU time 14.46 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:50:53 PM PDT 24
Peak memory 211336 kb
Host smart-a5173e82-e6dc-4d7a-9593-d2496fbda648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911228237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.911228237
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.394537738
Short name T360
Test name
Test status
Simulation time 31324796826 ps
CPU time 220.13 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:54:16 PM PDT 24
Peak memory 234860 kb
Host smart-2aebc115-058e-4d6f-9b8d-f38dca4d8270
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394537738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.394537738
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3687524934
Short name T295
Test name
Test status
Simulation time 13786523182 ps
CPU time 29.64 seconds
Started Jul 06 04:50:38 PM PDT 24
Finished Jul 06 04:51:08 PM PDT 24
Peak memory 212112 kb
Host smart-ec1fe3ad-9536-4e35-931e-97287601b8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687524934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3687524934
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1380983343
Short name T7
Test name
Test status
Simulation time 194998467 ps
CPU time 5.81 seconds
Started Jul 06 04:50:30 PM PDT 24
Finished Jul 06 04:50:37 PM PDT 24
Peak memory 211316 kb
Host smart-1e52974b-3c94-4c30-9931-03263179713e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380983343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1380983343
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.681557279
Short name T34
Test name
Test status
Simulation time 1062349554 ps
CPU time 103.23 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:52:30 PM PDT 24
Peak memory 238188 kb
Host smart-4f04225f-b1a3-44c9-8b4f-27d0e50353f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681557279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.681557279
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.974543494
Short name T347
Test name
Test status
Simulation time 3900379905 ps
CPU time 35.7 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:51:14 PM PDT 24
Peak memory 213404 kb
Host smart-e018ea8d-1850-4c8a-a753-e5666b18202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974543494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.974543494
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3598294802
Short name T371
Test name
Test status
Simulation time 39596393295 ps
CPU time 76.52 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:51:58 PM PDT 24
Peak memory 217944 kb
Host smart-59716857-6e9d-45e1-93af-618e97cb6084
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598294802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3598294802
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3477303724
Short name T135
Test name
Test status
Simulation time 980490426 ps
CPU time 5.43 seconds
Started Jul 06 04:51:10 PM PDT 24
Finished Jul 06 04:51:15 PM PDT 24
Peak memory 211264 kb
Host smart-ec7dd737-2fca-449d-8855-f65706de9f75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477303724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3477303724
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.929480883
Short name T162
Test name
Test status
Simulation time 43579487091 ps
CPU time 107.35 seconds
Started Jul 06 04:51:01 PM PDT 24
Finished Jul 06 04:52:49 PM PDT 24
Peak memory 224536 kb
Host smart-32284c2c-dff1-4c84-95d7-8a06d2b3e469
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929480883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.929480883
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4158086584
Short name T267
Test name
Test status
Simulation time 315475834 ps
CPU time 9.53 seconds
Started Jul 06 04:51:00 PM PDT 24
Finished Jul 06 04:51:11 PM PDT 24
Peak memory 212108 kb
Host smart-32b831ce-f55a-429b-8005-03daca8bd7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158086584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4158086584
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3373657568
Short name T158
Test name
Test status
Simulation time 5200866860 ps
CPU time 12.55 seconds
Started Jul 06 04:51:02 PM PDT 24
Finished Jul 06 04:51:15 PM PDT 24
Peak memory 211384 kb
Host smart-d97f40a8-23ad-47bc-b974-df01cdfeea70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373657568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3373657568
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1960001902
Short name T169
Test name
Test status
Simulation time 179893359 ps
CPU time 10.24 seconds
Started Jul 06 04:51:07 PM PDT 24
Finished Jul 06 04:51:18 PM PDT 24
Peak memory 213348 kb
Host smart-322e0d4d-dbfa-48c1-8789-030abe35829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960001902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1960001902
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.195997475
Short name T282
Test name
Test status
Simulation time 9848345295 ps
CPU time 33.84 seconds
Started Jul 06 04:51:05 PM PDT 24
Finished Jul 06 04:51:39 PM PDT 24
Peak memory 216472 kb
Host smart-1528f9be-9bcd-48b7-ae03-394472b7eb09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195997475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.195997475
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3781325864
Short name T338
Test name
Test status
Simulation time 3933383469 ps
CPU time 15.31 seconds
Started Jul 06 04:50:59 PM PDT 24
Finished Jul 06 04:51:15 PM PDT 24
Peak memory 211364 kb
Host smart-f9729244-6f45-49f8-a4be-fa1450bb2778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781325864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3781325864
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3746464060
Short name T316
Test name
Test status
Simulation time 46089328014 ps
CPU time 379.53 seconds
Started Jul 06 04:51:10 PM PDT 24
Finished Jul 06 04:57:30 PM PDT 24
Peak memory 225236 kb
Host smart-a91a04a7-0f51-42df-8f9e-3a206e944e3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746464060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3746464060
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4059625641
Short name T227
Test name
Test status
Simulation time 8509298939 ps
CPU time 33.89 seconds
Started Jul 06 04:50:59 PM PDT 24
Finished Jul 06 04:51:33 PM PDT 24
Peak memory 212256 kb
Host smart-ce9dcd79-36f6-4c7c-a68c-459e7423760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059625641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4059625641
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2506876693
Short name T272
Test name
Test status
Simulation time 3220901180 ps
CPU time 14.33 seconds
Started Jul 06 04:51:04 PM PDT 24
Finished Jul 06 04:51:19 PM PDT 24
Peak memory 211444 kb
Host smart-dc4d4fbf-62c5-48d0-8d9a-6f2c09af3c84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506876693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2506876693
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3500310999
Short name T358
Test name
Test status
Simulation time 669308674 ps
CPU time 10.16 seconds
Started Jul 06 04:50:55 PM PDT 24
Finished Jul 06 04:51:06 PM PDT 24
Peak memory 213256 kb
Host smart-d57549d8-8dae-4fc5-b5da-643fb537caea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500310999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3500310999
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1726342822
Short name T222
Test name
Test status
Simulation time 1650981815 ps
CPU time 24.87 seconds
Started Jul 06 04:51:02 PM PDT 24
Finished Jul 06 04:51:27 PM PDT 24
Peak memory 214012 kb
Host smart-91e0bb93-f93e-4d3c-b207-cab3af801f63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726342822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1726342822
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2242107736
Short name T156
Test name
Test status
Simulation time 1089037251 ps
CPU time 7.89 seconds
Started Jul 06 04:51:08 PM PDT 24
Finished Jul 06 04:51:17 PM PDT 24
Peak memory 211244 kb
Host smart-a0340626-2316-46e9-8edd-fd888a30c061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242107736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2242107736
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3048995450
Short name T133
Test name
Test status
Simulation time 26725659720 ps
CPU time 175.3 seconds
Started Jul 06 04:51:09 PM PDT 24
Finished Jul 06 04:54:04 PM PDT 24
Peak memory 228604 kb
Host smart-a254e963-3f65-4de0-917e-4fff331a484e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048995450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3048995450
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2677849643
Short name T293
Test name
Test status
Simulation time 5508856629 ps
CPU time 25.56 seconds
Started Jul 06 04:51:12 PM PDT 24
Finished Jul 06 04:51:38 PM PDT 24
Peak memory 212284 kb
Host smart-5e90edce-d163-4856-add4-303d26aa11d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677849643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2677849643
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3705829605
Short name T139
Test name
Test status
Simulation time 1268371035 ps
CPU time 12.86 seconds
Started Jul 06 04:51:02 PM PDT 24
Finished Jul 06 04:51:16 PM PDT 24
Peak memory 211300 kb
Host smart-0b0b8e2c-ae90-47d8-8e85-bc65a7ecc209
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705829605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3705829605
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.728872921
Short name T154
Test name
Test status
Simulation time 7596604740 ps
CPU time 21.85 seconds
Started Jul 06 04:51:03 PM PDT 24
Finished Jul 06 04:51:25 PM PDT 24
Peak memory 214776 kb
Host smart-dd1a7cea-7bb5-4c0a-8f59-8c4c95536dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728872921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.728872921
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2639302480
Short name T229
Test name
Test status
Simulation time 8228124739 ps
CPU time 40.81 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:52:01 PM PDT 24
Peak memory 216284 kb
Host smart-d4d50408-df6f-47b8-aff6-7a334c956b35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639302480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2639302480
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3648178272
Short name T52
Test name
Test status
Simulation time 42962213271 ps
CPU time 867.5 seconds
Started Jul 06 04:51:17 PM PDT 24
Finished Jul 06 05:05:45 PM PDT 24
Peak memory 231512 kb
Host smart-8a55777e-4d73-4429-a207-1a39113b366c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648178272 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3648178272
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2310975991
Short name T129
Test name
Test status
Simulation time 1178357559 ps
CPU time 11.17 seconds
Started Jul 06 04:51:09 PM PDT 24
Finished Jul 06 04:51:20 PM PDT 24
Peak memory 211372 kb
Host smart-940782bc-b618-42b0-a454-60ca2cd3966c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310975991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2310975991
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.656952940
Short name T252
Test name
Test status
Simulation time 54619898765 ps
CPU time 180.79 seconds
Started Jul 06 04:51:12 PM PDT 24
Finished Jul 06 04:54:13 PM PDT 24
Peak memory 237856 kb
Host smart-452b9cd5-5e84-494f-8157-d3dff4c2b3bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656952940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.656952940
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1868512399
Short name T248
Test name
Test status
Simulation time 390555208 ps
CPU time 11.71 seconds
Started Jul 06 04:51:03 PM PDT 24
Finished Jul 06 04:51:15 PM PDT 24
Peak memory 211876 kb
Host smart-52927724-329c-40d6-a73d-4e997f5d496b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868512399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1868512399
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4046617897
Short name T325
Test name
Test status
Simulation time 182977183 ps
CPU time 5.56 seconds
Started Jul 06 04:51:07 PM PDT 24
Finished Jul 06 04:51:14 PM PDT 24
Peak memory 211376 kb
Host smart-14df5795-3720-4d64-b8d1-84f581456295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046617897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4046617897
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2726150514
Short name T285
Test name
Test status
Simulation time 834571899 ps
CPU time 16.57 seconds
Started Jul 06 04:51:18 PM PDT 24
Finished Jul 06 04:51:35 PM PDT 24
Peak memory 212376 kb
Host smart-5eb2a1fb-be63-4683-8944-0d4dd81aa17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726150514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2726150514
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.872353210
Short name T288
Test name
Test status
Simulation time 12114405631 ps
CPU time 60.26 seconds
Started Jul 06 04:51:08 PM PDT 24
Finished Jul 06 04:52:09 PM PDT 24
Peak memory 215012 kb
Host smart-a3a944c3-7bc7-4548-b220-534ca08f5aa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872353210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.872353210
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.4193797046
Short name T54
Test name
Test status
Simulation time 73283477287 ps
CPU time 2045.49 seconds
Started Jul 06 04:51:09 PM PDT 24
Finished Jul 06 05:25:15 PM PDT 24
Peak memory 237000 kb
Host smart-33ba404d-f1b7-47c7-9b19-4a8ae86edfb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193797046 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.4193797046
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3891004577
Short name T333
Test name
Test status
Simulation time 2928788094 ps
CPU time 9.79 seconds
Started Jul 06 04:51:07 PM PDT 24
Finished Jul 06 04:51:18 PM PDT 24
Peak memory 211400 kb
Host smart-53e5264b-21d4-4c6b-a502-bd194d4dc251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891004577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3891004577
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1591766709
Short name T297
Test name
Test status
Simulation time 38581453298 ps
CPU time 388.33 seconds
Started Jul 06 04:51:09 PM PDT 24
Finished Jul 06 04:57:38 PM PDT 24
Peak memory 237792 kb
Host smart-3537a056-a002-4d74-aec7-ebb65ff13e3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591766709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1591766709
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1764055669
Short name T215
Test name
Test status
Simulation time 665272234 ps
CPU time 9.46 seconds
Started Jul 06 04:51:15 PM PDT 24
Finished Jul 06 04:51:25 PM PDT 24
Peak memory 211876 kb
Host smart-ff659091-3b00-42b8-9d7f-18943102aa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764055669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1764055669
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3350993488
Short name T238
Test name
Test status
Simulation time 5795458189 ps
CPU time 13.69 seconds
Started Jul 06 04:51:07 PM PDT 24
Finished Jul 06 04:51:22 PM PDT 24
Peak memory 211360 kb
Host smart-30c9b79f-a46c-489d-bd27-ad463a02cfc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350993488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3350993488
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2355752690
Short name T251
Test name
Test status
Simulation time 21641225646 ps
CPU time 20.65 seconds
Started Jul 06 04:51:11 PM PDT 24
Finished Jul 06 04:51:33 PM PDT 24
Peak memory 213744 kb
Host smart-1b481993-7ada-4d4b-8c65-0700684bcf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355752690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2355752690
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2386907382
Short name T363
Test name
Test status
Simulation time 308891881 ps
CPU time 21.39 seconds
Started Jul 06 04:51:10 PM PDT 24
Finished Jul 06 04:51:31 PM PDT 24
Peak memory 212728 kb
Host smart-03d20a09-00d1-4a46-8cf8-772a5a623eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386907382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2386907382
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2036431696
Short name T336
Test name
Test status
Simulation time 88842956 ps
CPU time 4.38 seconds
Started Jul 06 04:51:08 PM PDT 24
Finished Jul 06 04:51:13 PM PDT 24
Peak memory 211244 kb
Host smart-70bd3da5-eefa-4b45-9f92-9a4d6152c6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036431696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2036431696
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3917664208
Short name T206
Test name
Test status
Simulation time 40942197107 ps
CPU time 429.76 seconds
Started Jul 06 04:51:07 PM PDT 24
Finished Jul 06 04:58:18 PM PDT 24
Peak memory 236640 kb
Host smart-bcfa35c9-874a-4542-9418-e38607384ee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917664208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3917664208
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1383692457
Short name T39
Test name
Test status
Simulation time 53713827510 ps
CPU time 32.97 seconds
Started Jul 06 04:51:10 PM PDT 24
Finished Jul 06 04:51:43 PM PDT 24
Peak memory 212176 kb
Host smart-3f46a89a-6d6f-423f-8b1a-140c030dcc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383692457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1383692457
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1488253870
Short name T231
Test name
Test status
Simulation time 1277475228 ps
CPU time 13.11 seconds
Started Jul 06 04:51:15 PM PDT 24
Finished Jul 06 04:51:29 PM PDT 24
Peak memory 211280 kb
Host smart-568e0c93-393a-422f-bad2-9e4519a3ebb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488253870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1488253870
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.939944686
Short name T362
Test name
Test status
Simulation time 3477396973 ps
CPU time 21.39 seconds
Started Jul 06 04:51:09 PM PDT 24
Finished Jul 06 04:51:30 PM PDT 24
Peak memory 213388 kb
Host smart-1312f579-57f2-4e3f-a307-bb7279b0e7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939944686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.939944686
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2930758684
Short name T36
Test name
Test status
Simulation time 23787337002 ps
CPU time 60.25 seconds
Started Jul 06 04:51:01 PM PDT 24
Finished Jul 06 04:52:02 PM PDT 24
Peak memory 217256 kb
Host smart-82722647-3b42-41e8-aaed-1cd7376f81fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930758684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2930758684
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4223684558
Short name T214
Test name
Test status
Simulation time 2103545788 ps
CPU time 16.56 seconds
Started Jul 06 04:51:13 PM PDT 24
Finished Jul 06 04:51:30 PM PDT 24
Peak memory 211316 kb
Host smart-606b9f4b-8c46-4ad4-97b5-94ea179a598a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223684558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4223684558
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.584736936
Short name T366
Test name
Test status
Simulation time 232046245625 ps
CPU time 259.88 seconds
Started Jul 06 04:51:06 PM PDT 24
Finished Jul 06 04:55:27 PM PDT 24
Peak memory 234896 kb
Host smart-a212e4c4-aa9d-4340-abdd-bc25f8341188
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584736936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.584736936
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1952015458
Short name T192
Test name
Test status
Simulation time 175468993 ps
CPU time 9.44 seconds
Started Jul 06 04:51:09 PM PDT 24
Finished Jul 06 04:51:19 PM PDT 24
Peak memory 211724 kb
Host smart-c211401b-faf6-4d7c-833b-f4c9e537e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952015458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1952015458
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.277741739
Short name T320
Test name
Test status
Simulation time 4626300215 ps
CPU time 12.33 seconds
Started Jul 06 04:51:09 PM PDT 24
Finished Jul 06 04:51:22 PM PDT 24
Peak memory 211368 kb
Host smart-c8038439-7b31-48c0-9576-70c2b1f8d50b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=277741739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.277741739
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3874661871
Short name T211
Test name
Test status
Simulation time 778281502 ps
CPU time 10.15 seconds
Started Jul 06 04:51:06 PM PDT 24
Finished Jul 06 04:51:17 PM PDT 24
Peak memory 213456 kb
Host smart-dc24db79-c189-4a83-b819-0f8e3e51faa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874661871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3874661871
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2542884758
Short name T160
Test name
Test status
Simulation time 5559887711 ps
CPU time 49.38 seconds
Started Jul 06 04:51:17 PM PDT 24
Finished Jul 06 04:52:06 PM PDT 24
Peak memory 216784 kb
Host smart-78adef44-52e5-4f65-96b0-1c057a0631a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542884758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2542884758
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.402178935
Short name T352
Test name
Test status
Simulation time 5349735574 ps
CPU time 11.19 seconds
Started Jul 06 04:51:15 PM PDT 24
Finished Jul 06 04:51:27 PM PDT 24
Peak memory 211248 kb
Host smart-0ce11419-4792-4b01-8c86-a08e19e50dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402178935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.402178935
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2311720459
Short name T2
Test name
Test status
Simulation time 19883370128 ps
CPU time 226.65 seconds
Started Jul 06 04:51:19 PM PDT 24
Finished Jul 06 04:55:06 PM PDT 24
Peak memory 237996 kb
Host smart-589cdb39-80c0-4aa5-8544-956eb3eac8ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311720459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2311720459
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1336778032
Short name T172
Test name
Test status
Simulation time 3004564393 ps
CPU time 12.01 seconds
Started Jul 06 04:51:13 PM PDT 24
Finished Jul 06 04:51:25 PM PDT 24
Peak memory 211896 kb
Host smart-9f5baa0e-9448-43aa-a487-ce080d50f213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336778032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1336778032
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.978114875
Short name T307
Test name
Test status
Simulation time 3610980377 ps
CPU time 10.64 seconds
Started Jul 06 04:51:22 PM PDT 24
Finished Jul 06 04:51:33 PM PDT 24
Peak memory 211376 kb
Host smart-23181f3d-5283-4c6f-9dea-83b4a65b4e9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978114875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.978114875
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3529470952
Short name T309
Test name
Test status
Simulation time 12199281313 ps
CPU time 32.14 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:51:53 PM PDT 24
Peak memory 214284 kb
Host smart-03246dea-7833-47d6-8e98-2be30ed823a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529470952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3529470952
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.365842414
Short name T253
Test name
Test status
Simulation time 2058047706 ps
CPU time 18.59 seconds
Started Jul 06 04:51:11 PM PDT 24
Finished Jul 06 04:51:30 PM PDT 24
Peak memory 214520 kb
Host smart-a33a5bf3-4667-41f3-a425-93e2556e679c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365842414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.365842414
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2736412756
Short name T55
Test name
Test status
Simulation time 656124722590 ps
CPU time 1810.14 seconds
Started Jul 06 04:51:07 PM PDT 24
Finished Jul 06 05:21:18 PM PDT 24
Peak memory 236896 kb
Host smart-00da17a8-66ad-4727-9da9-31011336019c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736412756 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2736412756
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3154739065
Short name T10
Test name
Test status
Simulation time 1035788049 ps
CPU time 6.24 seconds
Started Jul 06 04:51:12 PM PDT 24
Finished Jul 06 04:51:19 PM PDT 24
Peak memory 211340 kb
Host smart-9cac1850-ee06-4dce-b28e-06c33b5e823a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154739065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3154739065
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.318458983
Short name T143
Test name
Test status
Simulation time 19061568346 ps
CPU time 149.67 seconds
Started Jul 06 04:51:08 PM PDT 24
Finished Jul 06 04:53:38 PM PDT 24
Peak memory 211572 kb
Host smart-fe6de15e-66fe-451a-a16e-8455ef74a7ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318458983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.318458983
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3987003730
Short name T263
Test name
Test status
Simulation time 14316440281 ps
CPU time 30.61 seconds
Started Jul 06 04:51:19 PM PDT 24
Finished Jul 06 04:51:50 PM PDT 24
Peak memory 212360 kb
Host smart-050be404-3bbe-4873-9ad1-bab825e8be15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987003730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3987003730
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.480938396
Short name T261
Test name
Test status
Simulation time 1105598334 ps
CPU time 8.93 seconds
Started Jul 06 04:51:17 PM PDT 24
Finished Jul 06 04:51:27 PM PDT 24
Peak memory 211284 kb
Host smart-9178ce92-7601-48c7-b880-e0b7d3359960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480938396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.480938396
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3525974224
Short name T134
Test name
Test status
Simulation time 3677135912 ps
CPU time 29.85 seconds
Started Jul 06 04:51:16 PM PDT 24
Finished Jul 06 04:51:46 PM PDT 24
Peak memory 213648 kb
Host smart-6f47f5a7-0150-4695-913d-9cc6125ddf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525974224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3525974224
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3787761781
Short name T245
Test name
Test status
Simulation time 340038211 ps
CPU time 18.08 seconds
Started Jul 06 04:51:22 PM PDT 24
Finished Jul 06 04:51:41 PM PDT 24
Peak memory 215192 kb
Host smart-7e5ea5d1-eef3-4db0-9494-bd8446776773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787761781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3787761781
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1523287928
Short name T62
Test name
Test status
Simulation time 85652767 ps
CPU time 4.29 seconds
Started Jul 06 04:51:15 PM PDT 24
Finished Jul 06 04:51:20 PM PDT 24
Peak memory 211280 kb
Host smart-e65c5bb8-714c-4bc5-9640-45eca06d5390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523287928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1523287928
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1660570110
Short name T284
Test name
Test status
Simulation time 3026574787 ps
CPU time 121.1 seconds
Started Jul 06 04:51:13 PM PDT 24
Finished Jul 06 04:53:14 PM PDT 24
Peak memory 234092 kb
Host smart-3269ebbc-1084-49c4-a746-2ddfcca6810d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660570110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1660570110
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3066399547
Short name T176
Test name
Test status
Simulation time 13716676676 ps
CPU time 25.33 seconds
Started Jul 06 04:51:12 PM PDT 24
Finished Jul 06 04:51:38 PM PDT 24
Peak memory 212212 kb
Host smart-dd581a54-ec19-496d-a9b0-70fec59a1021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066399547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3066399547
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3339804708
Short name T322
Test name
Test status
Simulation time 1979220871 ps
CPU time 15.96 seconds
Started Jul 06 04:51:17 PM PDT 24
Finished Jul 06 04:51:33 PM PDT 24
Peak memory 211404 kb
Host smart-3788825e-185a-49b1-b62c-5650ef9e378f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3339804708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3339804708
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3550280117
Short name T84
Test name
Test status
Simulation time 727640508 ps
CPU time 10.35 seconds
Started Jul 06 04:51:16 PM PDT 24
Finished Jul 06 04:51:27 PM PDT 24
Peak memory 213704 kb
Host smart-7a2a7ba0-0242-47ae-b87b-2d0f1da4b773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550280117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3550280117
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2669451039
Short name T196
Test name
Test status
Simulation time 4855590894 ps
CPU time 15.22 seconds
Started Jul 06 04:51:13 PM PDT 24
Finished Jul 06 04:51:28 PM PDT 24
Peak memory 211244 kb
Host smart-d09f1335-83d9-49dc-8ca6-9071402277c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669451039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2669451039
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3940145205
Short name T53
Test name
Test status
Simulation time 136859500093 ps
CPU time 6122.14 seconds
Started Jul 06 04:51:21 PM PDT 24
Finished Jul 06 06:33:24 PM PDT 24
Peak memory 233032 kb
Host smart-f45a5c49-88db-4ee6-b2fe-d44d4afbe074
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940145205 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3940145205
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.443688937
Short name T232
Test name
Test status
Simulation time 3765282642 ps
CPU time 9.97 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:48 PM PDT 24
Peak memory 211308 kb
Host smart-7e601846-57f6-4784-8cc2-f224129ea67d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443688937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.443688937
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1017609693
Short name T326
Test name
Test status
Simulation time 2174739441 ps
CPU time 134.67 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:52:53 PM PDT 24
Peak memory 237824 kb
Host smart-0d26984d-5683-4965-8dd5-e3ff4d6a26e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017609693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1017609693
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2982690292
Short name T9
Test name
Test status
Simulation time 168512013 ps
CPU time 9.76 seconds
Started Jul 06 04:50:32 PM PDT 24
Finished Jul 06 04:50:43 PM PDT 24
Peak memory 211916 kb
Host smart-9a1042eb-3024-46bd-867a-0e69684040cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982690292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2982690292
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4049514510
Short name T370
Test name
Test status
Simulation time 3040474331 ps
CPU time 8.07 seconds
Started Jul 06 04:50:52 PM PDT 24
Finished Jul 06 04:51:01 PM PDT 24
Peak memory 211444 kb
Host smart-e1601b68-1e3e-4c0c-9d66-e9be9cec53e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4049514510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4049514510
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4283260574
Short name T33
Test name
Test status
Simulation time 378379272 ps
CPU time 99.52 seconds
Started Jul 06 04:50:40 PM PDT 24
Finished Jul 06 04:52:21 PM PDT 24
Peak memory 238216 kb
Host smart-7c9b4f81-9f96-4ad7-949b-c97395a2734b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283260574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4283260574
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4021222529
Short name T368
Test name
Test status
Simulation time 3374654064 ps
CPU time 34.12 seconds
Started Jul 06 04:50:32 PM PDT 24
Finished Jul 06 04:51:07 PM PDT 24
Peak memory 213400 kb
Host smart-0cf98f0f-70f0-46cd-b6ac-c3578c787d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021222529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4021222529
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2281636042
Short name T310
Test name
Test status
Simulation time 110489843 ps
CPU time 5.91 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:42 PM PDT 24
Peak memory 211428 kb
Host smart-f10729a8-83a5-456f-9647-fbb7871e976a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281636042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2281636042
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1519071868
Short name T35
Test name
Test status
Simulation time 167846800 ps
CPU time 4.34 seconds
Started Jul 06 04:51:18 PM PDT 24
Finished Jul 06 04:51:23 PM PDT 24
Peak memory 211300 kb
Host smart-33305d64-4796-46df-85e7-e116ce8b328e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519071868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1519071868
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2042984244
Short name T311
Test name
Test status
Simulation time 9682819390 ps
CPU time 136.17 seconds
Started Jul 06 04:51:19 PM PDT 24
Finished Jul 06 04:53:35 PM PDT 24
Peak memory 237248 kb
Host smart-00ddfa97-fc0d-483b-9697-c28a9e7d8c4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042984244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2042984244
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.16139258
Short name T151
Test name
Test status
Simulation time 1885711265 ps
CPU time 20.43 seconds
Started Jul 06 04:51:26 PM PDT 24
Finished Jul 06 04:51:46 PM PDT 24
Peak memory 212136 kb
Host smart-a0fe1247-de36-4533-b503-2c0773732956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16139258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.16139258
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.18420278
Short name T225
Test name
Test status
Simulation time 97249239 ps
CPU time 5.26 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:51:26 PM PDT 24
Peak memory 211404 kb
Host smart-04ca3f8e-7e08-409c-8276-26074bc7dd8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18420278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.18420278
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1629359242
Short name T60
Test name
Test status
Simulation time 365161886 ps
CPU time 9.67 seconds
Started Jul 06 04:51:21 PM PDT 24
Finished Jul 06 04:51:31 PM PDT 24
Peak memory 213064 kb
Host smart-2473f21d-0916-4532-a023-643693b5357f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629359242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1629359242
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1044035709
Short name T302
Test name
Test status
Simulation time 3379682868 ps
CPU time 28.89 seconds
Started Jul 06 04:51:18 PM PDT 24
Finished Jul 06 04:51:47 PM PDT 24
Peak memory 216724 kb
Host smart-db3cf002-ecf5-4943-b8a1-260f5bdc0d1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044035709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1044035709
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1236518037
Short name T244
Test name
Test status
Simulation time 3796255616 ps
CPU time 10.42 seconds
Started Jul 06 04:51:23 PM PDT 24
Finished Jul 06 04:51:34 PM PDT 24
Peak memory 211368 kb
Host smart-42c42ebe-0d80-4c6f-9152-c501b5053011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236518037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1236518037
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2385839715
Short name T208
Test name
Test status
Simulation time 112804889688 ps
CPU time 280.48 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:56:01 PM PDT 24
Peak memory 237088 kb
Host smart-9e58000b-a4f8-4039-bd84-58ce3f5765f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385839715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2385839715
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.203741608
Short name T38
Test name
Test status
Simulation time 2642502832 ps
CPU time 14.07 seconds
Started Jul 06 04:51:18 PM PDT 24
Finished Jul 06 04:51:32 PM PDT 24
Peak memory 211896 kb
Host smart-3397d4c2-5db6-437f-b621-e3d58ecfd183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203741608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.203741608
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.37655153
Short name T262
Test name
Test status
Simulation time 2227757662 ps
CPU time 11.05 seconds
Started Jul 06 04:51:18 PM PDT 24
Finished Jul 06 04:51:30 PM PDT 24
Peak memory 211336 kb
Host smart-10c8fd67-0f19-494f-bcbf-c1cfc4453bb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37655153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.37655153
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4200770222
Short name T87
Test name
Test status
Simulation time 7702610707 ps
CPU time 38.43 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:51:59 PM PDT 24
Peak memory 213520 kb
Host smart-cda74f80-60a9-4073-ae79-53d7f939c4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200770222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4200770222
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3127961006
Short name T202
Test name
Test status
Simulation time 5328585014 ps
CPU time 26.1 seconds
Started Jul 06 04:51:19 PM PDT 24
Finished Jul 06 04:51:45 PM PDT 24
Peak memory 214156 kb
Host smart-0724358b-6717-4dea-bfe5-4802e7995b20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127961006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3127961006
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.532793662
Short name T31
Test name
Test status
Simulation time 1508175974 ps
CPU time 12.94 seconds
Started Jul 06 04:51:21 PM PDT 24
Finished Jul 06 04:51:34 PM PDT 24
Peak memory 211292 kb
Host smart-0a87dbb7-5931-4ef8-af1a-1a4bd627013a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532793662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.532793662
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3340818594
Short name T166
Test name
Test status
Simulation time 110574751098 ps
CPU time 309.41 seconds
Started Jul 06 04:51:18 PM PDT 24
Finished Jul 06 04:56:28 PM PDT 24
Peak memory 236824 kb
Host smart-90afd37b-6933-417e-9594-f66b5e4a6aea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340818594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3340818594
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2859031848
Short name T323
Test name
Test status
Simulation time 11065491594 ps
CPU time 20.94 seconds
Started Jul 06 04:51:24 PM PDT 24
Finished Jul 06 04:51:45 PM PDT 24
Peak memory 212132 kb
Host smart-05ecd19a-b14d-4c76-b7c2-4dbbcfc372a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859031848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2859031848
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.719939818
Short name T290
Test name
Test status
Simulation time 184877986 ps
CPU time 5.45 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:51:26 PM PDT 24
Peak memory 211256 kb
Host smart-19c325d2-b342-4263-94c2-73dbc9af2df6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719939818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.719939818
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2909858613
Short name T146
Test name
Test status
Simulation time 2198919867 ps
CPU time 21.99 seconds
Started Jul 06 04:51:21 PM PDT 24
Finished Jul 06 04:51:43 PM PDT 24
Peak memory 213532 kb
Host smart-728c5dc0-3002-4420-86ac-1dbd744da071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909858613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2909858613
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1709825987
Short name T353
Test name
Test status
Simulation time 8622615895 ps
CPU time 70.99 seconds
Started Jul 06 04:51:23 PM PDT 24
Finished Jul 06 04:52:35 PM PDT 24
Peak memory 216992 kb
Host smart-876e4202-961d-4616-9d93-03acaa2192d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709825987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1709825987
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1469979403
Short name T14
Test name
Test status
Simulation time 6695833683 ps
CPU time 14.84 seconds
Started Jul 06 04:51:19 PM PDT 24
Finished Jul 06 04:51:34 PM PDT 24
Peak memory 212628 kb
Host smart-44dd395c-4de6-44f0-893f-1fc159baf72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469979403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1469979403
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1265093645
Short name T126
Test name
Test status
Simulation time 2439858861 ps
CPU time 9.24 seconds
Started Jul 06 04:51:24 PM PDT 24
Finished Jul 06 04:51:34 PM PDT 24
Peak memory 211364 kb
Host smart-969311a2-aefd-4321-9078-ed261fcc291a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265093645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1265093645
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1861964317
Short name T86
Test name
Test status
Simulation time 735426348 ps
CPU time 10.51 seconds
Started Jul 06 04:51:16 PM PDT 24
Finished Jul 06 04:51:27 PM PDT 24
Peak memory 213840 kb
Host smart-cb3b3686-79f5-4251-a64a-b7cbfbf94aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861964317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1861964317
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.264501424
Short name T21
Test name
Test status
Simulation time 2048215555 ps
CPU time 35.43 seconds
Started Jul 06 04:51:19 PM PDT 24
Finished Jul 06 04:51:55 PM PDT 24
Peak memory 215932 kb
Host smart-b810a50e-18bd-43cd-88a3-0d4f7a466568
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264501424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.264501424
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.58885051
Short name T30
Test name
Test status
Simulation time 682913321 ps
CPU time 8.37 seconds
Started Jul 06 04:51:29 PM PDT 24
Finished Jul 06 04:51:38 PM PDT 24
Peak memory 211336 kb
Host smart-fac7dfc3-766c-43ed-a452-cc6fdebf63dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58885051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.58885051
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2705912458
Short name T256
Test name
Test status
Simulation time 28414503343 ps
CPU time 134.15 seconds
Started Jul 06 04:51:18 PM PDT 24
Finished Jul 06 04:53:33 PM PDT 24
Peak memory 228224 kb
Host smart-485c0ac1-45fa-4ef7-ba44-72587599d68f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705912458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2705912458
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4148563347
Short name T184
Test name
Test status
Simulation time 169033280 ps
CPU time 9.54 seconds
Started Jul 06 04:51:32 PM PDT 24
Finished Jul 06 04:51:42 PM PDT 24
Peak memory 211864 kb
Host smart-d9f246ff-ccd3-4c48-9b8c-04a70babf9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148563347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.4148563347
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1319247131
Short name T138
Test name
Test status
Simulation time 1651595932 ps
CPU time 8.15 seconds
Started Jul 06 04:51:22 PM PDT 24
Finished Jul 06 04:51:30 PM PDT 24
Peak memory 211288 kb
Host smart-097c0744-0a20-4e68-8254-8aac0fd4a55c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319247131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1319247131
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4118534176
Short name T181
Test name
Test status
Simulation time 5758345372 ps
CPU time 28.45 seconds
Started Jul 06 04:51:18 PM PDT 24
Finished Jul 06 04:51:47 PM PDT 24
Peak memory 213924 kb
Host smart-b38f4916-da9f-4d32-95bf-d3f57caa268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118534176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4118534176
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2401950161
Short name T171
Test name
Test status
Simulation time 1175345891 ps
CPU time 20.52 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:51:41 PM PDT 24
Peak memory 212400 kb
Host smart-11db4ca1-27f3-4f73-a036-b8f737ac14b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401950161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2401950161
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1789011197
Short name T131
Test name
Test status
Simulation time 1544757598 ps
CPU time 13.08 seconds
Started Jul 06 04:51:29 PM PDT 24
Finished Jul 06 04:51:42 PM PDT 24
Peak memory 211348 kb
Host smart-f253fabb-0cd4-45dd-9d4c-a4aedf3a54a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789011197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1789011197
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2313229749
Short name T258
Test name
Test status
Simulation time 43516215619 ps
CPU time 434.94 seconds
Started Jul 06 04:51:21 PM PDT 24
Finished Jul 06 04:58:36 PM PDT 24
Peak memory 228128 kb
Host smart-c63f0464-3f45-474b-949a-904c0701b937
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313229749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2313229749
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1496233363
Short name T254
Test name
Test status
Simulation time 1088254431 ps
CPU time 16.71 seconds
Started Jul 06 04:51:27 PM PDT 24
Finished Jul 06 04:51:44 PM PDT 24
Peak memory 211824 kb
Host smart-97bbf83d-8a50-4673-bda2-fc2e2b2742d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496233363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1496233363
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4095319008
Short name T201
Test name
Test status
Simulation time 6616984912 ps
CPU time 14.14 seconds
Started Jul 06 04:51:23 PM PDT 24
Finished Jul 06 04:51:38 PM PDT 24
Peak memory 211428 kb
Host smart-0d97940b-2121-4c5b-8c3b-e3ebad5a0e31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4095319008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4095319008
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2325303137
Short name T276
Test name
Test status
Simulation time 703723511 ps
CPU time 15.46 seconds
Started Jul 06 04:51:22 PM PDT 24
Finished Jul 06 04:51:38 PM PDT 24
Peak memory 213732 kb
Host smart-ec5c3a87-726f-440b-ae35-77b050eabb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325303137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2325303137
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1841521425
Short name T314
Test name
Test status
Simulation time 310824837 ps
CPU time 16.58 seconds
Started Jul 06 04:51:23 PM PDT 24
Finished Jul 06 04:51:40 PM PDT 24
Peak memory 214992 kb
Host smart-471ff48a-b430-4891-b6c8-56b2cc940d4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841521425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1841521425
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3726803140
Short name T241
Test name
Test status
Simulation time 1106588267 ps
CPU time 10.87 seconds
Started Jul 06 04:51:22 PM PDT 24
Finished Jul 06 04:51:33 PM PDT 24
Peak memory 211304 kb
Host smart-965df2d8-87d8-4e08-bef2-eb680177ba6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726803140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3726803140
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4090756485
Short name T355
Test name
Test status
Simulation time 67859618440 ps
CPU time 185.65 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:54:27 PM PDT 24
Peak memory 237876 kb
Host smart-f5ea1913-ab7e-4999-9f34-2b46206117dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090756485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4090756485
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.362952267
Short name T250
Test name
Test status
Simulation time 304410111 ps
CPU time 9.82 seconds
Started Jul 06 04:51:35 PM PDT 24
Finished Jul 06 04:51:45 PM PDT 24
Peak memory 211852 kb
Host smart-c4e436d6-b1bc-497f-8997-f9202aa85869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362952267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.362952267
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.896464093
Short name T174
Test name
Test status
Simulation time 1534365859 ps
CPU time 14.22 seconds
Started Jul 06 04:51:27 PM PDT 24
Finished Jul 06 04:51:42 PM PDT 24
Peak memory 211372 kb
Host smart-6fed2ae2-f1b3-4500-a4e4-14d5bdae16d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896464093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.896464093
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4008200719
Short name T367
Test name
Test status
Simulation time 618007436 ps
CPU time 10.25 seconds
Started Jul 06 04:51:21 PM PDT 24
Finished Jul 06 04:51:32 PM PDT 24
Peak memory 213452 kb
Host smart-ca43c13e-9c30-4282-9df6-de51ddf6142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008200719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4008200719
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3403307905
Short name T63
Test name
Test status
Simulation time 8040320814 ps
CPU time 90.01 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:52:51 PM PDT 24
Peak memory 217196 kb
Host smart-d7372ffe-fbd1-49b5-a1a4-ef6a6017f698
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403307905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3403307905
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2682655158
Short name T1
Test name
Test status
Simulation time 1224637852 ps
CPU time 10.95 seconds
Started Jul 06 04:51:18 PM PDT 24
Finished Jul 06 04:51:30 PM PDT 24
Peak memory 211376 kb
Host smart-3810b199-c8e7-4f34-8b84-e82687e3977b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682655158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2682655158
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4064773043
Short name T48
Test name
Test status
Simulation time 35983661471 ps
CPU time 309.67 seconds
Started Jul 06 04:51:29 PM PDT 24
Finished Jul 06 04:56:39 PM PDT 24
Peak memory 212560 kb
Host smart-1caaff07-1c59-4a30-9556-7f1952ea9458
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064773043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4064773043
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.563289165
Short name T361
Test name
Test status
Simulation time 2528880534 ps
CPU time 24.43 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:51:45 PM PDT 24
Peak memory 211928 kb
Host smart-9714f9e0-3092-48ec-9e48-fab734630fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563289165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.563289165
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2464122535
Short name T328
Test name
Test status
Simulation time 804853756 ps
CPU time 10.2 seconds
Started Jul 06 04:51:25 PM PDT 24
Finished Jul 06 04:51:35 PM PDT 24
Peak memory 211300 kb
Host smart-23c642ae-b500-42f7-ae30-125a6cb4e169
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464122535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2464122535
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2058820548
Short name T342
Test name
Test status
Simulation time 8737995891 ps
CPU time 18.87 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:51:40 PM PDT 24
Peak memory 214372 kb
Host smart-b28b9d39-2ba0-4e85-9f66-5abca9463cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058820548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2058820548
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.623464510
Short name T209
Test name
Test status
Simulation time 4043665934 ps
CPU time 41.71 seconds
Started Jul 06 04:51:24 PM PDT 24
Finished Jul 06 04:52:06 PM PDT 24
Peak memory 213424 kb
Host smart-887ea56c-c3d2-4988-93f9-555c9e6c5120
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623464510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.623464510
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3111465095
Short name T18
Test name
Test status
Simulation time 44292259770 ps
CPU time 1664.79 seconds
Started Jul 06 04:51:27 PM PDT 24
Finished Jul 06 05:19:12 PM PDT 24
Peak memory 232320 kb
Host smart-cdc5c89e-75a9-41f6-95ec-eb6a73cc99c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111465095 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3111465095
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.29966970
Short name T149
Test name
Test status
Simulation time 5167942062 ps
CPU time 12.13 seconds
Started Jul 06 04:51:35 PM PDT 24
Finished Jul 06 04:51:48 PM PDT 24
Peak memory 211384 kb
Host smart-45b44b7f-4a84-4b6b-8253-f67ec61f1382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29966970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.29966970
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2811513346
Short name T167
Test name
Test status
Simulation time 1736559525 ps
CPU time 105.23 seconds
Started Jul 06 04:51:25 PM PDT 24
Finished Jul 06 04:53:11 PM PDT 24
Peak memory 233672 kb
Host smart-3336c45b-4953-48d0-97b5-abfd6aeebea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811513346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2811513346
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.367847089
Short name T189
Test name
Test status
Simulation time 692802802 ps
CPU time 9.19 seconds
Started Jul 06 04:51:32 PM PDT 24
Finished Jul 06 04:51:42 PM PDT 24
Peak memory 212136 kb
Host smart-c053bb24-0f59-4e67-9bb7-738e5102f3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367847089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.367847089
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4041210366
Short name T205
Test name
Test status
Simulation time 3299490968 ps
CPU time 10.46 seconds
Started Jul 06 04:51:20 PM PDT 24
Finished Jul 06 04:51:31 PM PDT 24
Peak memory 211380 kb
Host smart-862c6207-8772-4dae-a803-713e22adef66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4041210366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4041210366
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.748522356
Short name T278
Test name
Test status
Simulation time 30656103436 ps
CPU time 28.64 seconds
Started Jul 06 04:51:21 PM PDT 24
Finished Jul 06 04:51:50 PM PDT 24
Peak memory 214644 kb
Host smart-843e97c6-2252-432e-92bb-e6f0d2327d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748522356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.748522356
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1944694728
Short name T283
Test name
Test status
Simulation time 4292882682 ps
CPU time 21.29 seconds
Started Jul 06 04:51:27 PM PDT 24
Finished Jul 06 04:51:49 PM PDT 24
Peak memory 211788 kb
Host smart-2da395bc-ffe9-4d48-96b7-c3a374a6dd6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944694728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1944694728
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2366165225
Short name T70
Test name
Test status
Simulation time 6056576729 ps
CPU time 12.96 seconds
Started Jul 06 04:51:31 PM PDT 24
Finished Jul 06 04:51:44 PM PDT 24
Peak memory 211288 kb
Host smart-8c49581c-9211-4cac-9183-b6f0fd1c1eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366165225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2366165225
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.428624614
Short name T186
Test name
Test status
Simulation time 8848009484 ps
CPU time 164.79 seconds
Started Jul 06 04:51:28 PM PDT 24
Finished Jul 06 04:54:13 PM PDT 24
Peak memory 237828 kb
Host smart-a0c10d8d-38ca-41d8-b967-639eaf7fa11d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428624614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.428624614
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2747182243
Short name T144
Test name
Test status
Simulation time 2065894282 ps
CPU time 13.01 seconds
Started Jul 06 04:51:35 PM PDT 24
Finished Jul 06 04:51:49 PM PDT 24
Peak memory 213300 kb
Host smart-0c1f0c6f-807f-463a-bac0-1b08a6d0fda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747182243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2747182243
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1243709181
Short name T159
Test name
Test status
Simulation time 20704868877 ps
CPU time 14.17 seconds
Started Jul 06 04:51:25 PM PDT 24
Finished Jul 06 04:51:40 PM PDT 24
Peak memory 211352 kb
Host smart-01a74e9d-3f44-4e44-94db-ed2401d04d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243709181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1243709181
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3058443370
Short name T369
Test name
Test status
Simulation time 12006665666 ps
CPU time 38.75 seconds
Started Jul 06 04:51:33 PM PDT 24
Finished Jul 06 04:52:12 PM PDT 24
Peak memory 214136 kb
Host smart-9399e6e1-cf82-47d6-a81c-7600015bf7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058443370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3058443370
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4287353699
Short name T153
Test name
Test status
Simulation time 6315027566 ps
CPU time 52.58 seconds
Started Jul 06 04:51:28 PM PDT 24
Finished Jul 06 04:52:21 PM PDT 24
Peak memory 216620 kb
Host smart-a0f0aacc-464f-4eb8-8a19-0b5d156d1a41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287353699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.4287353699
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2461475645
Short name T236
Test name
Test status
Simulation time 27085745332 ps
CPU time 2671.42 seconds
Started Jul 06 04:51:32 PM PDT 24
Finished Jul 06 05:36:05 PM PDT 24
Peak memory 235824 kb
Host smart-ff09b5d6-3ff4-4716-b182-0d3f4953b38f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461475645 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2461475645
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.717171091
Short name T204
Test name
Test status
Simulation time 347699370 ps
CPU time 4.29 seconds
Started Jul 06 04:50:59 PM PDT 24
Finished Jul 06 04:51:04 PM PDT 24
Peak memory 211348 kb
Host smart-37c5cd0f-8fd1-43e8-9549-7837f99ae382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717171091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.717171091
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3783316934
Short name T49
Test name
Test status
Simulation time 156920305403 ps
CPU time 352.33 seconds
Started Jul 06 04:50:38 PM PDT 24
Finished Jul 06 04:56:31 PM PDT 24
Peak memory 236924 kb
Host smart-778e4caa-0715-428e-ad21-774d47a33c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783316934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3783316934
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.650624728
Short name T349
Test name
Test status
Simulation time 2649706821 ps
CPU time 20.87 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:51:03 PM PDT 24
Peak memory 211980 kb
Host smart-76754faf-48b6-43e7-b28d-4baa897630cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650624728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.650624728
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2436666919
Short name T127
Test name
Test status
Simulation time 1075645974 ps
CPU time 8.73 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:50:49 PM PDT 24
Peak memory 211324 kb
Host smart-38013fc6-3ab1-43b8-9d49-413ea4978aaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436666919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2436666919
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3033588704
Short name T136
Test name
Test status
Simulation time 1503019856 ps
CPU time 14.42 seconds
Started Jul 06 04:50:52 PM PDT 24
Finished Jul 06 04:51:07 PM PDT 24
Peak memory 213088 kb
Host smart-5fe3abb9-9dd8-4d50-ba2a-ff2c3f7f2593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033588704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3033588704
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1761566507
Short name T264
Test name
Test status
Simulation time 43201102164 ps
CPU time 64.21 seconds
Started Jul 06 04:50:34 PM PDT 24
Finished Jul 06 04:51:38 PM PDT 24
Peak memory 217632 kb
Host smart-3de43bbf-b20b-4514-8747-cc87d7544f8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761566507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1761566507
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1739829896
Short name T183
Test name
Test status
Simulation time 2147226976 ps
CPU time 17.01 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:50:55 PM PDT 24
Peak memory 211244 kb
Host smart-06039afa-57b1-4bcf-b8fe-f2672d3789ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739829896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1739829896
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1625163932
Short name T42
Test name
Test status
Simulation time 5451949270 ps
CPU time 172.54 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:53:28 PM PDT 24
Peak memory 237864 kb
Host smart-1fb5b237-933d-41b5-be64-8f071194a267
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625163932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1625163932
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2939205952
Short name T317
Test name
Test status
Simulation time 2358117693 ps
CPU time 17.02 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:55 PM PDT 24
Peak memory 211940 kb
Host smart-11341fc0-7d45-41bc-b358-029b2182efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939205952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2939205952
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3735501625
Short name T257
Test name
Test status
Simulation time 1987009037 ps
CPU time 15.97 seconds
Started Jul 06 04:50:50 PM PDT 24
Finished Jul 06 04:51:06 PM PDT 24
Peak memory 211332 kb
Host smart-a15d3d2c-01e8-4c90-9d1e-596815e9b45a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735501625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3735501625
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3425649299
Short name T17
Test name
Test status
Simulation time 1349949163 ps
CPU time 22.58 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:51:03 PM PDT 24
Peak memory 213796 kb
Host smart-626868c3-fe06-4d48-8bdb-625483a95915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425649299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3425649299
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3001414494
Short name T281
Test name
Test status
Simulation time 15299227027 ps
CPU time 33.63 seconds
Started Jul 06 04:50:40 PM PDT 24
Finished Jul 06 04:51:15 PM PDT 24
Peak memory 217540 kb
Host smart-4095242d-ed19-4537-9763-6d474d4b2211
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001414494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3001414494
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3967083296
Short name T4
Test name
Test status
Simulation time 361642652 ps
CPU time 4.35 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 04:50:47 PM PDT 24
Peak memory 211360 kb
Host smart-c4f515f2-9049-49da-8a0a-33ee7196e7c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967083296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3967083296
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3302337357
Short name T341
Test name
Test status
Simulation time 2276619013 ps
CPU time 75.18 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:51:53 PM PDT 24
Peak memory 228560 kb
Host smart-88506168-627d-466a-b6a6-a1a6da64dc84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302337357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3302337357
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.755925581
Short name T32
Test name
Test status
Simulation time 339394191 ps
CPU time 11.91 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:50:54 PM PDT 24
Peak memory 211772 kb
Host smart-7e7dfde0-a1ee-4844-b924-c2551731b9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755925581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.755925581
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2159380578
Short name T294
Test name
Test status
Simulation time 284556601 ps
CPU time 6.75 seconds
Started Jul 06 04:50:51 PM PDT 24
Finished Jul 06 04:50:58 PM PDT 24
Peak memory 211292 kb
Host smart-fb256abc-7081-410e-a24c-dbc059f70b34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159380578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2159380578
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1260767283
Short name T312
Test name
Test status
Simulation time 4870350091 ps
CPU time 17.31 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 04:51:00 PM PDT 24
Peak memory 214296 kb
Host smart-84f61bbf-6cd5-4ff0-bd11-baf8dcca266d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260767283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1260767283
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2663310099
Short name T339
Test name
Test status
Simulation time 4143349430 ps
CPU time 19.92 seconds
Started Jul 06 04:50:50 PM PDT 24
Finished Jul 06 04:51:11 PM PDT 24
Peak memory 213560 kb
Host smart-5793e162-fa2b-449e-9cc1-a2194fa52b32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663310099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2663310099
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2028504356
Short name T140
Test name
Test status
Simulation time 712168582 ps
CPU time 8.74 seconds
Started Jul 06 04:50:54 PM PDT 24
Finished Jul 06 04:51:03 PM PDT 24
Peak memory 211232 kb
Host smart-3d824fe0-769a-45d5-84dc-4b0a8066bd78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028504356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2028504356
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3564848434
Short name T200
Test name
Test status
Simulation time 130179066047 ps
CPU time 318.99 seconds
Started Jul 06 04:50:44 PM PDT 24
Finished Jul 06 04:56:03 PM PDT 24
Peak memory 212512 kb
Host smart-e5cb2255-ef02-4952-8977-372085a4744b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564848434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3564848434
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4059536099
Short name T277
Test name
Test status
Simulation time 175891790 ps
CPU time 9.31 seconds
Started Jul 06 04:50:46 PM PDT 24
Finished Jul 06 04:50:56 PM PDT 24
Peak memory 212076 kb
Host smart-2aaeded5-a15d-487f-9ed6-abe3337bc856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059536099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4059536099
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4071735684
Short name T16
Test name
Test status
Simulation time 7752645753 ps
CPU time 16.07 seconds
Started Jul 06 04:50:46 PM PDT 24
Finished Jul 06 04:51:03 PM PDT 24
Peak memory 211388 kb
Host smart-f7b299f1-8f2e-425e-842e-2ed066c672b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071735684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4071735684
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.260283434
Short name T268
Test name
Test status
Simulation time 1363798624 ps
CPU time 12.47 seconds
Started Jul 06 04:50:53 PM PDT 24
Finished Jul 06 04:51:06 PM PDT 24
Peak memory 213184 kb
Host smart-a5b0781e-c7c5-4749-96d9-c98d0df3e772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260283434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.260283434
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1891951227
Short name T335
Test name
Test status
Simulation time 6620041343 ps
CPU time 72.02 seconds
Started Jul 06 04:50:34 PM PDT 24
Finished Jul 06 04:51:47 PM PDT 24
Peak memory 216100 kb
Host smart-9eaec401-3cbe-436c-8084-96a9831a310b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891951227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1891951227
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2766076645
Short name T190
Test name
Test status
Simulation time 3294986684 ps
CPU time 14.8 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:51 PM PDT 24
Peak memory 211420 kb
Host smart-2d9b08f4-5a59-4365-b39c-89ad7c3b8ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766076645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2766076645
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.343174821
Short name T364
Test name
Test status
Simulation time 90874786131 ps
CPU time 219.38 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:54:17 PM PDT 24
Peak memory 228672 kb
Host smart-a91ea490-a09f-4c36-b987-333ef6a398e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343174821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.343174821
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1031261263
Short name T301
Test name
Test status
Simulation time 2749293171 ps
CPU time 23 seconds
Started Jul 06 04:50:40 PM PDT 24
Finished Jul 06 04:51:04 PM PDT 24
Peak memory 212884 kb
Host smart-6373d5ec-21ad-4d2f-aa51-fbc0b51aef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031261263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1031261263
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2487766717
Short name T198
Test name
Test status
Simulation time 2129404784 ps
CPU time 16.97 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:54 PM PDT 24
Peak memory 211288 kb
Host smart-23ab38bb-c633-4bba-85f7-92a1178f03ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487766717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2487766717
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1502026128
Short name T163
Test name
Test status
Simulation time 512040830 ps
CPU time 13.79 seconds
Started Jul 06 04:50:46 PM PDT 24
Finished Jul 06 04:51:00 PM PDT 24
Peak memory 213620 kb
Host smart-4b4790ba-c18f-4992-bbe3-ed5ba0dd5fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502026128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1502026128
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3893314
Short name T279
Test name
Test status
Simulation time 591964858 ps
CPU time 15.52 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 04:50:58 PM PDT 24
Peak memory 214088 kb
Host smart-84f63cbd-7d4d-4cfe-8ac5-f3c389cfce6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.rom_ctrl_stress_all.3893314
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.4090977462
Short name T180
Test name
Test status
Simulation time 60894840974 ps
CPU time 9546.5 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 07:29:48 PM PDT 24
Peak memory 235784 kb
Host smart-877dd0ab-9edc-4c64-8a71-5df0df152493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090977462 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.4090977462
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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