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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.34 96.89 91.99 97.67 100.00 98.28 97.45 99.07


Total test records in report: 467
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T300 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2029557650 Jul 07 05:05:01 PM PDT 24 Jul 07 05:43:54 PM PDT 24 72233366375 ps
T301 /workspace/coverage/default/48.rom_ctrl_stress_all.2536378925 Jul 07 05:05:00 PM PDT 24 Jul 07 05:06:02 PM PDT 24 5928847013 ps
T302 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.372020166 Jul 07 05:02:30 PM PDT 24 Jul 07 05:04:17 PM PDT 24 1829631316 ps
T303 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1125134594 Jul 07 05:03:24 PM PDT 24 Jul 07 05:03:38 PM PDT 24 2969031060 ps
T304 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1504430865 Jul 07 05:04:19 PM PDT 24 Jul 07 05:04:46 PM PDT 24 3076760949 ps
T305 /workspace/coverage/default/12.rom_ctrl_alert_test.4246971888 Jul 07 05:02:42 PM PDT 24 Jul 07 05:02:47 PM PDT 24 270011102 ps
T306 /workspace/coverage/default/13.rom_ctrl_alert_test.3898567952 Jul 07 05:02:47 PM PDT 24 Jul 07 05:03:00 PM PDT 24 1594641333 ps
T307 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.721514715 Jul 07 05:01:52 PM PDT 24 Jul 07 05:02:02 PM PDT 24 321420491 ps
T308 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1902390546 Jul 07 05:02:26 PM PDT 24 Jul 07 05:02:34 PM PDT 24 2186372472 ps
T309 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2848696364 Jul 07 05:03:56 PM PDT 24 Jul 07 05:06:11 PM PDT 24 4852870074 ps
T310 /workspace/coverage/default/40.rom_ctrl_smoke.368122638 Jul 07 05:04:34 PM PDT 24 Jul 07 05:05:03 PM PDT 24 3498639072 ps
T311 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1101852155 Jul 07 05:04:12 PM PDT 24 Jul 07 05:04:38 PM PDT 24 11140238210 ps
T312 /workspace/coverage/default/0.rom_ctrl_smoke.2364710486 Jul 07 05:01:35 PM PDT 24 Jul 07 05:01:45 PM PDT 24 361063262 ps
T313 /workspace/coverage/default/15.rom_ctrl_smoke.3290986498 Jul 07 05:02:57 PM PDT 24 Jul 07 05:03:08 PM PDT 24 909491102 ps
T314 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4235633004 Jul 07 05:02:26 PM PDT 24 Jul 07 05:26:36 PM PDT 24 159586028605 ps
T315 /workspace/coverage/default/49.rom_ctrl_smoke.901104288 Jul 07 05:05:07 PM PDT 24 Jul 07 05:05:45 PM PDT 24 3926375401 ps
T316 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1539013294 Jul 07 05:03:02 PM PDT 24 Jul 07 05:04:44 PM PDT 24 8842372166 ps
T317 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.927117769 Jul 07 05:04:26 PM PDT 24 Jul 07 05:09:29 PM PDT 24 62860224424 ps
T318 /workspace/coverage/default/45.rom_ctrl_stress_all.1816447525 Jul 07 05:04:52 PM PDT 24 Jul 07 05:05:46 PM PDT 24 6470211099 ps
T319 /workspace/coverage/default/36.rom_ctrl_smoke.777506332 Jul 07 05:04:12 PM PDT 24 Jul 07 05:04:30 PM PDT 24 4819981335 ps
T30 /workspace/coverage/default/2.rom_ctrl_sec_cm.2847092549 Jul 07 05:01:51 PM PDT 24 Jul 07 05:03:35 PM PDT 24 1120289768 ps
T320 /workspace/coverage/default/20.rom_ctrl_alert_test.4156058350 Jul 07 05:03:21 PM PDT 24 Jul 07 05:03:29 PM PDT 24 1332365645 ps
T321 /workspace/coverage/default/23.rom_ctrl_alert_test.2368597068 Jul 07 05:03:30 PM PDT 24 Jul 07 05:03:43 PM PDT 24 1366401544 ps
T322 /workspace/coverage/default/13.rom_ctrl_smoke.2530097857 Jul 07 05:02:44 PM PDT 24 Jul 07 05:03:02 PM PDT 24 3086695801 ps
T323 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2240475622 Jul 07 05:03:06 PM PDT 24 Jul 07 05:03:17 PM PDT 24 991875629 ps
T324 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.416530623 Jul 07 05:03:01 PM PDT 24 Jul 07 05:15:46 PM PDT 24 28969455756 ps
T325 /workspace/coverage/default/21.rom_ctrl_smoke.2724958020 Jul 07 05:03:20 PM PDT 24 Jul 07 05:03:31 PM PDT 24 361849786 ps
T326 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2460012897 Jul 07 05:03:25 PM PDT 24 Jul 07 05:08:20 PM PDT 24 43243169783 ps
T327 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1749414994 Jul 07 05:03:34 PM PDT 24 Jul 07 05:04:01 PM PDT 24 26927544877 ps
T328 /workspace/coverage/default/33.rom_ctrl_alert_test.2815757658 Jul 07 05:04:11 PM PDT 24 Jul 07 05:04:26 PM PDT 24 1560073523 ps
T329 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2015510422 Jul 07 05:02:42 PM PDT 24 Jul 07 05:02:48 PM PDT 24 485160737 ps
T330 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1308395680 Jul 07 05:04:39 PM PDT 24 Jul 07 05:07:47 PM PDT 24 31716036552 ps
T331 /workspace/coverage/default/6.rom_ctrl_alert_test.3395272934 Jul 07 05:02:13 PM PDT 24 Jul 07 05:02:18 PM PDT 24 85643541 ps
T332 /workspace/coverage/default/32.rom_ctrl_alert_test.1159641686 Jul 07 05:04:02 PM PDT 24 Jul 07 05:04:19 PM PDT 24 2198983843 ps
T333 /workspace/coverage/default/12.rom_ctrl_stress_all.1778780802 Jul 07 05:02:42 PM PDT 24 Jul 07 05:02:50 PM PDT 24 2600346377 ps
T334 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1469553075 Jul 07 05:04:54 PM PDT 24 Jul 07 05:07:36 PM PDT 24 11204737513 ps
T335 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3761710457 Jul 07 05:03:26 PM PDT 24 Jul 07 05:18:47 PM PDT 24 26141716853 ps
T336 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.633220189 Jul 07 05:03:04 PM PDT 24 Jul 07 05:03:12 PM PDT 24 2434560822 ps
T337 /workspace/coverage/default/16.rom_ctrl_alert_test.3938019826 Jul 07 05:03:06 PM PDT 24 Jul 07 05:03:17 PM PDT 24 1105020782 ps
T338 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.487044817 Jul 07 05:02:52 PM PDT 24 Jul 07 05:06:42 PM PDT 24 56754672261 ps
T339 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4292613470 Jul 07 05:03:10 PM PDT 24 Jul 07 05:03:36 PM PDT 24 11268900616 ps
T340 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1457476295 Jul 07 05:02:01 PM PDT 24 Jul 07 05:02:18 PM PDT 24 2090955437 ps
T341 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1328551865 Jul 07 05:04:52 PM PDT 24 Jul 07 05:05:06 PM PDT 24 721277751 ps
T342 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2829923712 Jul 07 05:04:35 PM PDT 24 Jul 07 05:06:27 PM PDT 24 1700193058 ps
T343 /workspace/coverage/default/3.rom_ctrl_alert_test.276816480 Jul 07 05:02:03 PM PDT 24 Jul 07 05:02:11 PM PDT 24 2226581787 ps
T344 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3535994969 Jul 07 05:04:11 PM PDT 24 Jul 07 05:09:59 PM PDT 24 72641745883 ps
T345 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3338661375 Jul 07 05:04:01 PM PDT 24 Jul 07 05:04:36 PM PDT 24 48497306467 ps
T346 /workspace/coverage/default/22.rom_ctrl_stress_all.3022290457 Jul 07 05:03:22 PM PDT 24 Jul 07 05:03:39 PM PDT 24 1248613948 ps
T347 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3689029243 Jul 07 05:05:09 PM PDT 24 Jul 07 05:07:22 PM PDT 24 4265157919 ps
T348 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1922494957 Jul 07 05:03:58 PM PDT 24 Jul 07 05:06:30 PM PDT 24 12262282284 ps
T349 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3261647288 Jul 07 05:03:44 PM PDT 24 Jul 07 05:34:45 PM PDT 24 111505290485 ps
T350 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2687169117 Jul 07 05:03:02 PM PDT 24 Jul 07 05:03:27 PM PDT 24 2406420552 ps
T351 /workspace/coverage/default/2.rom_ctrl_alert_test.3318609945 Jul 07 05:01:52 PM PDT 24 Jul 07 05:02:03 PM PDT 24 3263844552 ps
T352 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4001887190 Jul 07 05:02:16 PM PDT 24 Jul 07 05:02:33 PM PDT 24 8376604520 ps
T353 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.967212377 Jul 07 05:03:45 PM PDT 24 Jul 07 05:03:59 PM PDT 24 21096491509 ps
T354 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2065275633 Jul 07 05:02:30 PM PDT 24 Jul 07 05:03:03 PM PDT 24 8206282700 ps
T355 /workspace/coverage/default/42.rom_ctrl_stress_all.1182262331 Jul 07 05:04:38 PM PDT 24 Jul 07 05:04:47 PM PDT 24 785912315 ps
T356 /workspace/coverage/default/28.rom_ctrl_alert_test.329095136 Jul 07 05:03:45 PM PDT 24 Jul 07 05:04:01 PM PDT 24 7625523880 ps
T357 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.777091149 Jul 07 05:04:52 PM PDT 24 Jul 07 05:05:22 PM PDT 24 15483973414 ps
T358 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.317388124 Jul 07 05:04:13 PM PDT 24 Jul 07 05:06:53 PM PDT 24 17954427003 ps
T359 /workspace/coverage/default/25.rom_ctrl_alert_test.1938382081 Jul 07 05:03:34 PM PDT 24 Jul 07 05:03:40 PM PDT 24 431700052 ps
T360 /workspace/coverage/default/10.rom_ctrl_stress_all.1536721626 Jul 07 05:02:31 PM PDT 24 Jul 07 05:02:42 PM PDT 24 714116348 ps
T361 /workspace/coverage/default/9.rom_ctrl_smoke.2505479697 Jul 07 05:02:26 PM PDT 24 Jul 07 05:02:41 PM PDT 24 696811231 ps
T362 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.490832452 Jul 07 05:04:47 PM PDT 24 Jul 07 05:04:52 PM PDT 24 177649644 ps
T363 /workspace/coverage/default/27.rom_ctrl_alert_test.75111459 Jul 07 05:03:45 PM PDT 24 Jul 07 05:03:50 PM PDT 24 462480589 ps
T364 /workspace/coverage/default/20.rom_ctrl_smoke.55696144 Jul 07 05:03:20 PM PDT 24 Jul 07 05:03:51 PM PDT 24 13666451177 ps
T365 /workspace/coverage/default/18.rom_ctrl_alert_test.632493474 Jul 07 05:03:12 PM PDT 24 Jul 07 05:03:26 PM PDT 24 1663063684 ps
T366 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3240350689 Jul 07 05:03:36 PM PDT 24 Jul 07 05:03:44 PM PDT 24 1243833490 ps
T367 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3837553315 Jul 07 05:02:09 PM PDT 24 Jul 07 05:02:14 PM PDT 24 196780904 ps
T368 /workspace/coverage/default/47.rom_ctrl_stress_all.3627100706 Jul 07 05:04:55 PM PDT 24 Jul 07 05:05:52 PM PDT 24 5710321588 ps
T369 /workspace/coverage/default/11.rom_ctrl_smoke.2231285208 Jul 07 05:02:34 PM PDT 24 Jul 07 05:02:58 PM PDT 24 4202248946 ps
T370 /workspace/coverage/default/8.rom_ctrl_alert_test.850293229 Jul 07 05:02:25 PM PDT 24 Jul 07 05:02:30 PM PDT 24 85757544 ps
T371 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4188880062 Jul 07 05:05:56 PM PDT 24 Jul 07 05:06:10 PM PDT 24 2471766192 ps
T55 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2053012660 Jul 07 05:05:56 PM PDT 24 Jul 07 05:06:06 PM PDT 24 984121640 ps
T56 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.232365793 Jul 07 05:05:12 PM PDT 24 Jul 07 05:05:28 PM PDT 24 32928122852 ps
T57 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1781891649 Jul 07 05:05:51 PM PDT 24 Jul 07 05:07:03 PM PDT 24 139585519432 ps
T52 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1806470595 Jul 07 05:05:23 PM PDT 24 Jul 07 05:06:00 PM PDT 24 325790723 ps
T372 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2447257614 Jul 07 05:05:50 PM PDT 24 Jul 07 05:06:00 PM PDT 24 515215038 ps
T61 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1051347910 Jul 07 05:05:37 PM PDT 24 Jul 07 05:05:46 PM PDT 24 729119917 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3594419108 Jul 07 05:05:15 PM PDT 24 Jul 07 05:05:27 PM PDT 24 4289583269 ps
T62 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3136971305 Jul 07 05:05:07 PM PDT 24 Jul 07 05:05:36 PM PDT 24 6062152056 ps
T63 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.202245891 Jul 07 05:05:26 PM PDT 24 Jul 07 05:06:24 PM PDT 24 16552752172 ps
T373 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1682136798 Jul 07 05:05:22 PM PDT 24 Jul 07 05:05:34 PM PDT 24 2680199534 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2906053838 Jul 07 05:05:22 PM PDT 24 Jul 07 05:05:28 PM PDT 24 1046425833 ps
T65 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1446201655 Jul 07 05:05:37 PM PDT 24 Jul 07 05:06:23 PM PDT 24 4819971361 ps
T94 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1962547732 Jul 07 05:06:00 PM PDT 24 Jul 07 05:06:16 PM PDT 24 3987939020 ps
T53 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.655904963 Jul 07 05:05:41 PM PDT 24 Jul 07 05:06:53 PM PDT 24 751877930 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1325383813 Jul 07 05:05:25 PM PDT 24 Jul 07 05:05:36 PM PDT 24 2706107257 ps
T54 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.624540131 Jul 07 05:05:31 PM PDT 24 Jul 07 05:06:46 PM PDT 24 4756574903 ps
T99 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2902126438 Jul 07 05:05:57 PM PDT 24 Jul 07 05:06:41 PM PDT 24 6096069276 ps
T375 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2597786708 Jul 07 05:05:42 PM PDT 24 Jul 07 05:05:48 PM PDT 24 2086383954 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2067216602 Jul 07 05:05:16 PM PDT 24 Jul 07 05:05:31 PM PDT 24 3774245375 ps
T66 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2432777389 Jul 07 05:05:20 PM PDT 24 Jul 07 05:05:30 PM PDT 24 973477021 ps
T67 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1990876628 Jul 07 05:05:35 PM PDT 24 Jul 07 05:06:01 PM PDT 24 4428420723 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.48427019 Jul 07 05:05:25 PM PDT 24 Jul 07 05:05:40 PM PDT 24 15657495396 ps
T68 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1713578494 Jul 07 05:05:50 PM PDT 24 Jul 07 05:07:00 PM PDT 24 35941244633 ps
T73 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.622322622 Jul 07 05:05:50 PM PDT 24 Jul 07 05:05:55 PM PDT 24 85588798 ps
T378 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2779429915 Jul 07 05:05:31 PM PDT 24 Jul 07 05:05:36 PM PDT 24 206454730 ps
T110 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1301635515 Jul 07 05:05:25 PM PDT 24 Jul 07 05:06:44 PM PDT 24 1846691230 ps
T86 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2929398632 Jul 07 05:05:37 PM PDT 24 Jul 07 05:05:46 PM PDT 24 1280573820 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.385889372 Jul 07 05:05:08 PM PDT 24 Jul 07 05:05:19 PM PDT 24 4393292043 ps
T87 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2201386483 Jul 07 05:05:41 PM PDT 24 Jul 07 05:05:52 PM PDT 24 3000839968 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3079343350 Jul 07 05:05:16 PM PDT 24 Jul 07 05:05:20 PM PDT 24 333410400 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1109532982 Jul 07 05:05:20 PM PDT 24 Jul 07 05:05:26 PM PDT 24 333714715 ps
T382 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2962135846 Jul 07 05:06:00 PM PDT 24 Jul 07 05:06:17 PM PDT 24 3974243640 ps
T88 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3568795223 Jul 07 05:05:35 PM PDT 24 Jul 07 05:05:40 PM PDT 24 88997890 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3207476173 Jul 07 05:05:26 PM PDT 24 Jul 07 05:05:42 PM PDT 24 3973594151 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1302965501 Jul 07 05:05:11 PM PDT 24 Jul 07 05:05:21 PM PDT 24 3149659037 ps
T384 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3831423947 Jul 07 05:05:35 PM PDT 24 Jul 07 05:05:44 PM PDT 24 8933075027 ps
T385 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.607254553 Jul 07 05:05:35 PM PDT 24 Jul 07 05:05:46 PM PDT 24 595412768 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1900117636 Jul 07 05:05:19 PM PDT 24 Jul 07 05:05:33 PM PDT 24 792774441 ps
T89 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3018686223 Jul 07 05:06:02 PM PDT 24 Jul 07 05:06:07 PM PDT 24 1656246438 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.340501375 Jul 07 05:05:25 PM PDT 24 Jul 07 05:05:30 PM PDT 24 174949504 ps
T90 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4141076574 Jul 07 05:06:01 PM PDT 24 Jul 07 05:06:07 PM PDT 24 347954966 ps
T388 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1434081505 Jul 07 05:05:48 PM PDT 24 Jul 07 05:06:01 PM PDT 24 1568254634 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2119364750 Jul 07 05:05:11 PM PDT 24 Jul 07 05:05:23 PM PDT 24 2397251778 ps
T390 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2241493335 Jul 07 05:05:59 PM PDT 24 Jul 07 05:06:10 PM PDT 24 2216101999 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.665487190 Jul 07 05:05:10 PM PDT 24 Jul 07 05:05:20 PM PDT 24 3913605706 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2613072283 Jul 07 05:06:01 PM PDT 24 Jul 07 05:06:12 PM PDT 24 5966566494 ps
T393 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.588234607 Jul 07 05:05:16 PM PDT 24 Jul 07 05:05:37 PM PDT 24 8672288783 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2916814525 Jul 07 05:05:06 PM PDT 24 Jul 07 05:05:49 PM PDT 24 4869187515 ps
T394 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.237099200 Jul 07 05:05:12 PM PDT 24 Jul 07 05:05:21 PM PDT 24 510270130 ps
T395 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.811997448 Jul 07 05:05:46 PM PDT 24 Jul 07 05:06:07 PM PDT 24 27762689621 ps
T104 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.591777235 Jul 07 05:05:36 PM PDT 24 Jul 07 05:06:16 PM PDT 24 2193346402 ps
T396 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2151987212 Jul 07 05:05:31 PM PDT 24 Jul 07 05:05:46 PM PDT 24 1164304981 ps
T397 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3089723087 Jul 07 05:05:50 PM PDT 24 Jul 07 05:06:08 PM PDT 24 1935734761 ps
T398 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3228025143 Jul 07 05:05:35 PM PDT 24 Jul 07 05:05:46 PM PDT 24 5110256409 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2932809487 Jul 07 05:05:16 PM PDT 24 Jul 07 05:05:29 PM PDT 24 1782117803 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2661033516 Jul 07 05:05:24 PM PDT 24 Jul 07 05:05:39 PM PDT 24 1752731211 ps
T401 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1238834742 Jul 07 05:05:57 PM PDT 24 Jul 07 05:06:13 PM PDT 24 1263484312 ps
T91 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3999463957 Jul 07 05:05:22 PM PDT 24 Jul 07 05:05:30 PM PDT 24 535250434 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.300635975 Jul 07 05:05:11 PM PDT 24 Jul 07 05:05:29 PM PDT 24 2112555602 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3535604417 Jul 07 05:05:21 PM PDT 24 Jul 07 05:05:28 PM PDT 24 1376351091 ps
T109 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2846193097 Jul 07 05:05:55 PM PDT 24 Jul 07 05:06:39 PM PDT 24 4189830101 ps
T404 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2219077125 Jul 07 05:05:43 PM PDT 24 Jul 07 05:06:00 PM PDT 24 5943597656 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3628019954 Jul 07 05:05:15 PM PDT 24 Jul 07 05:05:32 PM PDT 24 3780342045 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2213286644 Jul 07 05:05:08 PM PDT 24 Jul 07 05:05:39 PM PDT 24 9615372357 ps
T407 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3866644726 Jul 07 05:05:45 PM PDT 24 Jul 07 05:06:03 PM PDT 24 8460656550 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.56551870 Jul 07 05:05:25 PM PDT 24 Jul 07 05:05:35 PM PDT 24 1458047388 ps
T102 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1625696074 Jul 07 05:05:15 PM PDT 24 Jul 07 05:06:03 PM PDT 24 2020737254 ps
T409 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2537296959 Jul 07 05:06:01 PM PDT 24 Jul 07 05:06:17 PM PDT 24 2576885139 ps
T410 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3243122346 Jul 07 05:05:51 PM PDT 24 Jul 07 05:06:06 PM PDT 24 3672726735 ps
T411 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3541706823 Jul 07 05:05:55 PM PDT 24 Jul 07 05:06:10 PM PDT 24 6346123775 ps
T75 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3108398581 Jul 07 05:05:43 PM PDT 24 Jul 07 05:05:58 PM PDT 24 3188966002 ps
T412 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4186126064 Jul 07 05:06:01 PM PDT 24 Jul 07 05:06:50 PM PDT 24 19118075539 ps
T76 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3767688780 Jul 07 05:06:02 PM PDT 24 Jul 07 05:06:30 PM PDT 24 2024131582 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3589940475 Jul 07 05:05:22 PM PDT 24 Jul 07 05:05:30 PM PDT 24 1082173239 ps
T414 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1349328811 Jul 07 05:05:51 PM PDT 24 Jul 07 05:06:00 PM PDT 24 704465811 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4170735149 Jul 07 05:05:28 PM PDT 24 Jul 07 05:05:34 PM PDT 24 306015223 ps
T416 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3750421020 Jul 07 05:06:00 PM PDT 24 Jul 07 05:06:06 PM PDT 24 106743150 ps
T81 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2680382975 Jul 07 05:05:09 PM PDT 24 Jul 07 05:05:14 PM PDT 24 85395278 ps
T417 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.164914670 Jul 07 05:05:48 PM PDT 24 Jul 07 05:06:01 PM PDT 24 1494059518 ps
T418 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.177706128 Jul 07 05:06:00 PM PDT 24 Jul 07 05:06:13 PM PDT 24 8922247489 ps
T419 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3714183410 Jul 07 05:05:35 PM PDT 24 Jul 07 05:05:51 PM PDT 24 1983776011 ps
T420 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3885863608 Jul 07 05:05:37 PM PDT 24 Jul 07 05:05:49 PM PDT 24 1291733229 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3581983394 Jul 07 05:05:19 PM PDT 24 Jul 07 05:05:24 PM PDT 24 85758776 ps
T422 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.350453212 Jul 07 05:05:34 PM PDT 24 Jul 07 05:05:44 PM PDT 24 476890272 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2510423725 Jul 07 05:05:24 PM PDT 24 Jul 07 05:05:38 PM PDT 24 6439048208 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2712461348 Jul 07 05:05:11 PM PDT 24 Jul 07 05:05:55 PM PDT 24 1355511639 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3098667296 Jul 07 05:05:26 PM PDT 24 Jul 07 05:05:38 PM PDT 24 2296461227 ps
T425 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.182701237 Jul 07 05:06:04 PM PDT 24 Jul 07 05:06:14 PM PDT 24 978658880 ps
T426 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.539660644 Jul 07 05:05:21 PM PDT 24 Jul 07 05:05:26 PM PDT 24 346426610 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2238891988 Jul 07 05:05:23 PM PDT 24 Jul 07 05:05:38 PM PDT 24 2028986892 ps
T428 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3632947877 Jul 07 05:05:41 PM PDT 24 Jul 07 05:06:56 PM PDT 24 7654624385 ps
T429 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3582182611 Jul 07 05:05:59 PM PDT 24 Jul 07 05:06:13 PM PDT 24 5997412668 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4014065691 Jul 07 05:05:42 PM PDT 24 Jul 07 05:05:58 PM PDT 24 1349812201 ps
T431 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2535832774 Jul 07 05:05:41 PM PDT 24 Jul 07 05:05:57 PM PDT 24 1965058222 ps
T432 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.897072987 Jul 07 05:05:41 PM PDT 24 Jul 07 05:05:49 PM PDT 24 778486269 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1027515475 Jul 07 05:05:07 PM PDT 24 Jul 07 05:05:23 PM PDT 24 6284441704 ps
T434 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3419441805 Jul 07 05:05:46 PM PDT 24 Jul 07 05:05:53 PM PDT 24 1599270639 ps
T77 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3217554778 Jul 07 05:05:20 PM PDT 24 Jul 07 05:05:36 PM PDT 24 4339223212 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.307427875 Jul 07 05:05:31 PM PDT 24 Jul 07 05:05:44 PM PDT 24 1453043213 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2596560316 Jul 07 05:05:20 PM PDT 24 Jul 07 05:06:12 PM PDT 24 21300009571 ps
T437 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1385811986 Jul 07 05:05:46 PM PDT 24 Jul 07 05:06:26 PM PDT 24 324260841 ps
T438 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3342721867 Jul 07 05:06:02 PM PDT 24 Jul 07 05:06:23 PM PDT 24 3578084423 ps
T439 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.599994521 Jul 07 05:05:46 PM PDT 24 Jul 07 05:05:58 PM PDT 24 5378324009 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3842096793 Jul 07 05:05:11 PM PDT 24 Jul 07 05:05:27 PM PDT 24 2142930309 ps
T441 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1741759717 Jul 07 05:05:36 PM PDT 24 Jul 07 05:05:51 PM PDT 24 1196653396 ps
T103 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3793553036 Jul 07 05:05:52 PM PDT 24 Jul 07 05:07:05 PM PDT 24 3478799282 ps
T108 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.57599920 Jul 07 05:05:55 PM PDT 24 Jul 07 05:07:08 PM PDT 24 2276259884 ps
T442 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1043118410 Jul 07 05:05:42 PM PDT 24 Jul 07 05:05:57 PM PDT 24 1995809383 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.980197670 Jul 07 05:05:28 PM PDT 24 Jul 07 05:05:38 PM PDT 24 16468404991 ps
T444 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1304998437 Jul 07 05:06:04 PM PDT 24 Jul 07 05:06:08 PM PDT 24 179422969 ps
T445 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1412182879 Jul 07 05:05:46 PM PDT 24 Jul 07 05:05:56 PM PDT 24 150466782 ps
T446 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2130947612 Jul 07 05:05:41 PM PDT 24 Jul 07 05:05:51 PM PDT 24 1286997377 ps
T97 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.233586584 Jul 07 05:06:00 PM PDT 24 Jul 07 05:06:31 PM PDT 24 3344908241 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1961422857 Jul 07 05:05:15 PM PDT 24 Jul 07 05:05:29 PM PDT 24 4737260203 ps
T98 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.413743764 Jul 07 05:05:47 PM PDT 24 Jul 07 05:07:14 PM PDT 24 42673897859 ps
T78 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2734151711 Jul 07 05:05:56 PM PDT 24 Jul 07 05:06:00 PM PDT 24 321775500 ps
T448 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4216710263 Jul 07 05:05:56 PM PDT 24 Jul 07 05:06:10 PM PDT 24 2477511453 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.974953620 Jul 07 05:05:10 PM PDT 24 Jul 07 05:05:20 PM PDT 24 279969358 ps
T450 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.153647785 Jul 07 05:05:51 PM PDT 24 Jul 07 05:06:00 PM PDT 24 5912291409 ps
T105 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1876788469 Jul 07 05:05:41 PM PDT 24 Jul 07 05:06:58 PM PDT 24 3507989982 ps
T111 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2255900160 Jul 07 05:06:01 PM PDT 24 Jul 07 05:06:43 PM PDT 24 1793646254 ps
T451 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2368205977 Jul 07 05:05:46 PM PDT 24 Jul 07 05:06:02 PM PDT 24 6362532341 ps
T452 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3686506169 Jul 07 05:05:55 PM PDT 24 Jul 07 05:06:42 PM PDT 24 23941540246 ps
T453 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2291994725 Jul 07 05:05:46 PM PDT 24 Jul 07 05:06:03 PM PDT 24 12303190477 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2748019550 Jul 07 05:05:22 PM PDT 24 Jul 07 05:05:36 PM PDT 24 2577134552 ps
T455 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.883539260 Jul 07 05:05:41 PM PDT 24 Jul 07 05:06:26 PM PDT 24 5635182539 ps
T79 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.740514805 Jul 07 05:05:40 PM PDT 24 Jul 07 05:06:46 PM PDT 24 27788852401 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.351419484 Jul 07 05:05:55 PM PDT 24 Jul 07 05:06:02 PM PDT 24 1719479983 ps
T80 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3843447497 Jul 07 05:05:31 PM PDT 24 Jul 07 05:06:38 PM PDT 24 34250699331 ps
T457 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1590694829 Jul 07 05:05:20 PM PDT 24 Jul 07 05:05:25 PM PDT 24 85705901 ps
T458 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4166078734 Jul 07 05:05:35 PM PDT 24 Jul 07 05:05:50 PM PDT 24 1787852756 ps
T459 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1651384916 Jul 07 05:05:42 PM PDT 24 Jul 07 05:06:12 PM PDT 24 1838281865 ps
T100 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.948104789 Jul 07 05:06:01 PM PDT 24 Jul 07 05:06:39 PM PDT 24 794801367 ps
T82 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.431685857 Jul 07 05:05:41 PM PDT 24 Jul 07 05:06:17 PM PDT 24 5331998416 ps
T460 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1325766344 Jul 07 05:05:40 PM PDT 24 Jul 07 05:05:57 PM PDT 24 7890804134 ps
T461 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1833302920 Jul 07 05:05:24 PM PDT 24 Jul 07 05:05:39 PM PDT 24 3904727868 ps
T106 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3936745535 Jul 07 05:05:47 PM PDT 24 Jul 07 05:07:05 PM PDT 24 3512739201 ps
T462 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4271779286 Jul 07 05:05:25 PM PDT 24 Jul 07 05:06:15 PM PDT 24 6239908446 ps
T463 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.321419503 Jul 07 05:05:25 PM PDT 24 Jul 07 05:05:36 PM PDT 24 5052072677 ps
T464 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2363524093 Jul 07 05:05:38 PM PDT 24 Jul 07 05:06:18 PM PDT 24 894130124 ps
T465 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3181232230 Jul 07 05:05:11 PM PDT 24 Jul 07 05:05:22 PM PDT 24 4615058574 ps
T101 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.721579528 Jul 07 05:05:36 PM PDT 24 Jul 07 05:06:14 PM PDT 24 368728370 ps
T466 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3725752255 Jul 07 05:05:32 PM PDT 24 Jul 07 05:05:39 PM PDT 24 1905276585 ps
T467 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3311322385 Jul 07 05:05:45 PM PDT 24 Jul 07 05:06:39 PM PDT 24 4581864145 ps

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3374349610
Short name T7
Test name
Test status
Simulation time 56910920347 ps
CPU time 178.24 seconds
Started Jul 07 05:05:00 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 237680 kb
Host smart-29d9c473-0597-4e6b-9884-262c50fd9795
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374349610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3374349610
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3015206953
Short name T12
Test name
Test status
Simulation time 69763404496 ps
CPU time 689.68 seconds
Started Jul 07 05:02:04 PM PDT 24
Finished Jul 07 05:13:34 PM PDT 24
Peak memory 228388 kb
Host smart-9489c72d-4644-4979-8058-8158e6d15401
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015206953 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3015206953
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.325496815
Short name T14
Test name
Test status
Simulation time 69836858844 ps
CPU time 2796.54 seconds
Started Jul 07 05:04:48 PM PDT 24
Finished Jul 07 05:51:25 PM PDT 24
Peak memory 240656 kb
Host smart-8fd4cdcc-eadc-46c5-9ea3-1a4e116774cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325496815 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.325496815
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3663249210
Short name T3
Test name
Test status
Simulation time 70367514650 ps
CPU time 389.64 seconds
Started Jul 07 05:03:44 PM PDT 24
Finished Jul 07 05:10:14 PM PDT 24
Peak memory 212520 kb
Host smart-0c5dfc33-a805-4a3e-88b4-809935f89236
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663249210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3663249210
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1847174823
Short name T39
Test name
Test status
Simulation time 1028827444 ps
CPU time 10.62 seconds
Started Jul 07 05:03:39 PM PDT 24
Finished Jul 07 05:03:50 PM PDT 24
Peak memory 211236 kb
Host smart-ff8c4abf-6fec-4478-b223-03bb0a3d48f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847174823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1847174823
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.655904963
Short name T53
Test name
Test status
Simulation time 751877930 ps
CPU time 71.59 seconds
Started Jul 07 05:05:41 PM PDT 24
Finished Jul 07 05:06:53 PM PDT 24
Peak memory 211212 kb
Host smart-8e6ca58c-97f7-44fb-ac75-a3ea12f32753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655904963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.655904963
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1620863924
Short name T13
Test name
Test status
Simulation time 49592253170 ps
CPU time 902.44 seconds
Started Jul 07 05:03:25 PM PDT 24
Finished Jul 07 05:18:28 PM PDT 24
Peak memory 235760 kb
Host smart-903460f6-36c5-4fd4-8ee3-2c6e479805d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620863924 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1620863924
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2804147010
Short name T22
Test name
Test status
Simulation time 930132848 ps
CPU time 102.06 seconds
Started Jul 07 05:01:38 PM PDT 24
Finished Jul 07 05:03:21 PM PDT 24
Peak memory 236780 kb
Host smart-ec17bff4-0276-442b-9542-532b7c3e2eac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804147010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2804147010
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3136971305
Short name T62
Test name
Test status
Simulation time 6062152056 ps
CPU time 28.58 seconds
Started Jul 07 05:05:07 PM PDT 24
Finished Jul 07 05:05:36 PM PDT 24
Peak memory 210740 kb
Host smart-d8fc99ad-58a9-4a42-8f2c-a11dc7704e65
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136971305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3136971305
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.156629408
Short name T26
Test name
Test status
Simulation time 3402835769 ps
CPU time 30.37 seconds
Started Jul 07 05:03:25 PM PDT 24
Finished Jul 07 05:03:56 PM PDT 24
Peak memory 211920 kb
Host smart-9cd58258-03e6-4643-9cbc-360154820bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156629408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.156629408
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.198515780
Short name T214
Test name
Test status
Simulation time 3604138035 ps
CPU time 20.41 seconds
Started Jul 07 05:02:30 PM PDT 24
Finished Jul 07 05:02:50 PM PDT 24
Peak memory 211848 kb
Host smart-d530c589-d803-481b-b902-0b0f77870742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198515780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.198515780
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2712461348
Short name T107
Test name
Test status
Simulation time 1355511639 ps
CPU time 43.56 seconds
Started Jul 07 05:05:11 PM PDT 24
Finished Jul 07 05:05:55 PM PDT 24
Peak memory 218852 kb
Host smart-d19eaa21-622b-4933-80ba-4df0c54dc835
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712461348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2712461348
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1876788469
Short name T105
Test name
Test status
Simulation time 3507989982 ps
CPU time 76.27 seconds
Started Jul 07 05:05:41 PM PDT 24
Finished Jul 07 05:06:58 PM PDT 24
Peak memory 218916 kb
Host smart-bd7bc24b-3865-4bc3-b606-47998ffe7e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876788469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1876788469
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1206195986
Short name T9
Test name
Test status
Simulation time 5182761468 ps
CPU time 65.15 seconds
Started Jul 07 05:03:34 PM PDT 24
Finished Jul 07 05:04:39 PM PDT 24
Peak memory 216656 kb
Host smart-07835750-2e83-4a90-8e88-54e601778168
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206195986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1206195986
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2916814525
Short name T112
Test name
Test status
Simulation time 4869187515 ps
CPU time 42.86 seconds
Started Jul 07 05:05:06 PM PDT 24
Finished Jul 07 05:05:49 PM PDT 24
Peak memory 218868 kb
Host smart-20fc4b7c-0741-4ea9-9baf-8703b4267e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916814525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2916814525
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.413743764
Short name T98
Test name
Test status
Simulation time 42673897859 ps
CPU time 87.49 seconds
Started Jul 07 05:05:47 PM PDT 24
Finished Jul 07 05:07:14 PM PDT 24
Peak memory 210728 kb
Host smart-f021ee9d-3f17-4b34-9887-f237b665e433
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413743764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.413743764
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3793553036
Short name T103
Test name
Test status
Simulation time 3478799282 ps
CPU time 73.11 seconds
Started Jul 07 05:05:52 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 218932 kb
Host smart-a760a07d-c329-4967-890a-c94b15ad0a27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793553036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3793553036
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.948104789
Short name T100
Test name
Test status
Simulation time 794801367 ps
CPU time 38.06 seconds
Started Jul 07 05:06:01 PM PDT 24
Finished Jul 07 05:06:39 PM PDT 24
Peak memory 218828 kb
Host smart-84fb4295-0b3f-454e-a408-b4128b8c5ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948104789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.948104789
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.591777235
Short name T104
Test name
Test status
Simulation time 2193346402 ps
CPU time 39.76 seconds
Started Jul 07 05:05:36 PM PDT 24
Finished Jul 07 05:06:16 PM PDT 24
Peak memory 210724 kb
Host smart-0c5215f0-04e6-4a2b-9472-280b1dcf2026
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591777235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.591777235
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1494073566
Short name T92
Test name
Test status
Simulation time 26444645412 ps
CPU time 14.66 seconds
Started Jul 07 05:03:12 PM PDT 24
Finished Jul 07 05:03:27 PM PDT 24
Peak memory 211376 kb
Host smart-0acf0eb8-9ffd-4e41-b0a2-fda225d6d74f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494073566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1494073566
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.679802370
Short name T15
Test name
Test status
Simulation time 328062062506 ps
CPU time 3427.28 seconds
Started Jul 07 05:03:21 PM PDT 24
Finished Jul 07 06:00:29 PM PDT 24
Peak memory 235816 kb
Host smart-3877db9b-e3b6-4b87-bfd4-21cad634ec13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679802370 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.679802370
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2680382975
Short name T81
Test name
Test status
Simulation time 85395278 ps
CPU time 4.33 seconds
Started Jul 07 05:05:09 PM PDT 24
Finished Jul 07 05:05:14 PM PDT 24
Peak memory 210652 kb
Host smart-68e57e3e-7ac3-45be-b0cf-ce07c0e278f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680382975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2680382975
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3181232230
Short name T465
Test name
Test status
Simulation time 4615058574 ps
CPU time 11 seconds
Started Jul 07 05:05:11 PM PDT 24
Finished Jul 07 05:05:22 PM PDT 24
Peak memory 217708 kb
Host smart-47510e2c-83d7-459c-b6c6-126ff2d52093
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181232230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3181232230
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.237099200
Short name T394
Test name
Test status
Simulation time 510270130 ps
CPU time 8.79 seconds
Started Jul 07 05:05:12 PM PDT 24
Finished Jul 07 05:05:21 PM PDT 24
Peak memory 210668 kb
Host smart-8c529692-5241-4fd3-be21-f8ca71a52aa9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237099200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.237099200
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.300635975
Short name T402
Test name
Test status
Simulation time 2112555602 ps
CPU time 17.4 seconds
Started Jul 07 05:05:11 PM PDT 24
Finished Jul 07 05:05:29 PM PDT 24
Peak memory 218824 kb
Host smart-4e01ddf4-2260-4b96-b89f-4de74d13bc51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300635975 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.300635975
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.232365793
Short name T56
Test name
Test status
Simulation time 32928122852 ps
CPU time 15.78 seconds
Started Jul 07 05:05:12 PM PDT 24
Finished Jul 07 05:05:28 PM PDT 24
Peak memory 218896 kb
Host smart-7dd6bf36-b7b5-43bc-b689-5c8581309f03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232365793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.232365793
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.665487190
Short name T391
Test name
Test status
Simulation time 3913605706 ps
CPU time 9.92 seconds
Started Jul 07 05:05:10 PM PDT 24
Finished Jul 07 05:05:20 PM PDT 24
Peak memory 210584 kb
Host smart-d73576ca-699a-492c-921d-37b03f3a4b42
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665487190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.665487190
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.385889372
Short name T379
Test name
Test status
Simulation time 4393292043 ps
CPU time 10.77 seconds
Started Jul 07 05:05:08 PM PDT 24
Finished Jul 07 05:05:19 PM PDT 24
Peak memory 210452 kb
Host smart-997ce53f-445d-4ddc-8abc-ac29a7540c36
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385889372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
385889372
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3842096793
Short name T440
Test name
Test status
Simulation time 2142930309 ps
CPU time 15.75 seconds
Started Jul 07 05:05:11 PM PDT 24
Finished Jul 07 05:05:27 PM PDT 24
Peak memory 218892 kb
Host smart-301d20b9-5cf6-4067-9dd9-f309d640f593
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842096793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3842096793
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1027515475
Short name T433
Test name
Test status
Simulation time 6284441704 ps
CPU time 15.69 seconds
Started Jul 07 05:05:07 PM PDT 24
Finished Jul 07 05:05:23 PM PDT 24
Peak memory 218996 kb
Host smart-6f1e20de-6275-4849-9575-e298deb296ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027515475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1027515475
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3581983394
Short name T421
Test name
Test status
Simulation time 85758776 ps
CPU time 4.3 seconds
Started Jul 07 05:05:19 PM PDT 24
Finished Jul 07 05:05:24 PM PDT 24
Peak memory 210580 kb
Host smart-0f58915a-25ec-4cf2-ba56-3b51bff1d6dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581983394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3581983394
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3079343350
Short name T380
Test name
Test status
Simulation time 333410400 ps
CPU time 4.56 seconds
Started Jul 07 05:05:16 PM PDT 24
Finished Jul 07 05:05:20 PM PDT 24
Peak memory 217396 kb
Host smart-8ab8516a-e716-426f-8cd9-35f6c2c3c19a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079343350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3079343350
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1961422857
Short name T447
Test name
Test status
Simulation time 4737260203 ps
CPU time 13.42 seconds
Started Jul 07 05:05:15 PM PDT 24
Finished Jul 07 05:05:29 PM PDT 24
Peak memory 211100 kb
Host smart-f81934e7-9000-419f-a778-e8dde41a2a0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961422857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1961422857
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2067216602
Short name T376
Test name
Test status
Simulation time 3774245375 ps
CPU time 15.05 seconds
Started Jul 07 05:05:16 PM PDT 24
Finished Jul 07 05:05:31 PM PDT 24
Peak memory 219312 kb
Host smart-dc81221c-1fa8-49e5-8729-a4aa321b7e43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067216602 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2067216602
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2932809487
Short name T399
Test name
Test status
Simulation time 1782117803 ps
CPU time 12.84 seconds
Started Jul 07 05:05:16 PM PDT 24
Finished Jul 07 05:05:29 PM PDT 24
Peak memory 218536 kb
Host smart-c8be3ac2-1190-4aa0-8ffb-73bc6a7d805f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932809487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2932809487
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2119364750
Short name T389
Test name
Test status
Simulation time 2397251778 ps
CPU time 11.8 seconds
Started Jul 07 05:05:11 PM PDT 24
Finished Jul 07 05:05:23 PM PDT 24
Peak memory 210596 kb
Host smart-860eadf9-39bd-414e-b940-192f6b1e40d7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119364750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2119364750
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1302965501
Short name T383
Test name
Test status
Simulation time 3149659037 ps
CPU time 9.43 seconds
Started Jul 07 05:05:11 PM PDT 24
Finished Jul 07 05:05:21 PM PDT 24
Peak memory 210588 kb
Host smart-32f5bc11-453b-4918-a893-dc06f838330d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302965501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1302965501
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2213286644
Short name T406
Test name
Test status
Simulation time 9615372357 ps
CPU time 30.6 seconds
Started Jul 07 05:05:08 PM PDT 24
Finished Jul 07 05:05:39 PM PDT 24
Peak memory 210680 kb
Host smart-0c33de31-38d8-464b-a43b-592153920fb9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213286644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2213286644
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3594419108
Short name T85
Test name
Test status
Simulation time 4289583269 ps
CPU time 11.84 seconds
Started Jul 07 05:05:15 PM PDT 24
Finished Jul 07 05:05:27 PM PDT 24
Peak memory 218852 kb
Host smart-73434258-010e-4e96-a2d3-520d01cec7f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594419108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3594419108
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.974953620
Short name T449
Test name
Test status
Simulation time 279969358 ps
CPU time 9.79 seconds
Started Jul 07 05:05:10 PM PDT 24
Finished Jul 07 05:05:20 PM PDT 24
Peak memory 218904 kb
Host smart-83d31ab7-3467-4070-a52f-a21c8812880c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974953620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.974953620
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.897072987
Short name T432
Test name
Test status
Simulation time 778486269 ps
CPU time 7.55 seconds
Started Jul 07 05:05:41 PM PDT 24
Finished Jul 07 05:05:49 PM PDT 24
Peak memory 218916 kb
Host smart-a4498141-2f9f-4c26-a2b7-b8b7a418f86e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897072987 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.897072987
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3108398581
Short name T75
Test name
Test status
Simulation time 3188966002 ps
CPU time 15.02 seconds
Started Jul 07 05:05:43 PM PDT 24
Finished Jul 07 05:05:58 PM PDT 24
Peak memory 210624 kb
Host smart-5960cfda-8b5d-42d9-b755-f7b19f89c97b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108398581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3108398581
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.883539260
Short name T455
Test name
Test status
Simulation time 5635182539 ps
CPU time 45.09 seconds
Started Jul 07 05:05:41 PM PDT 24
Finished Jul 07 05:06:26 PM PDT 24
Peak memory 210640 kb
Host smart-d9548354-523b-4617-881d-7cde648d1319
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883539260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.883539260
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2201386483
Short name T87
Test name
Test status
Simulation time 3000839968 ps
CPU time 10.65 seconds
Started Jul 07 05:05:41 PM PDT 24
Finished Jul 07 05:05:52 PM PDT 24
Peak memory 210812 kb
Host smart-76a73083-6337-4bd3-897e-ef478171430d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201386483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2201386483
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2219077125
Short name T404
Test name
Test status
Simulation time 5943597656 ps
CPU time 16.86 seconds
Started Jul 07 05:05:43 PM PDT 24
Finished Jul 07 05:06:00 PM PDT 24
Peak memory 219000 kb
Host smart-91c09ef2-effe-4f56-bc20-5c033d21cc55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219077125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2219077125
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3632947877
Short name T428
Test name
Test status
Simulation time 7654624385 ps
CPU time 75.12 seconds
Started Jul 07 05:05:41 PM PDT 24
Finished Jul 07 05:06:56 PM PDT 24
Peak memory 211652 kb
Host smart-7963055a-2884-4ad5-941b-e1de2435d0a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632947877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3632947877
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.164914670
Short name T417
Test name
Test status
Simulation time 1494059518 ps
CPU time 13.02 seconds
Started Jul 07 05:05:48 PM PDT 24
Finished Jul 07 05:06:01 PM PDT 24
Peak memory 218972 kb
Host smart-808cf8e5-3108-484e-9be6-1f4d55bdbf30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164914670 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.164914670
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.599994521
Short name T439
Test name
Test status
Simulation time 5378324009 ps
CPU time 11.87 seconds
Started Jul 07 05:05:46 PM PDT 24
Finished Jul 07 05:05:58 PM PDT 24
Peak memory 218760 kb
Host smart-52f02b02-56a6-4626-8c03-123c5a835063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599994521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.599994521
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.431685857
Short name T82
Test name
Test status
Simulation time 5331998416 ps
CPU time 35.52 seconds
Started Jul 07 05:05:41 PM PDT 24
Finished Jul 07 05:06:17 PM PDT 24
Peak memory 217852 kb
Host smart-36bc7101-c5f2-4694-9ee7-f482984c34f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431685857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.431685857
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3419441805
Short name T434
Test name
Test status
Simulation time 1599270639 ps
CPU time 7.01 seconds
Started Jul 07 05:05:46 PM PDT 24
Finished Jul 07 05:05:53 PM PDT 24
Peak memory 218192 kb
Host smart-e088ba43-28cb-400e-9462-c148c9c5f823
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419441805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3419441805
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1325766344
Short name T460
Test name
Test status
Simulation time 7890804134 ps
CPU time 16.4 seconds
Started Jul 07 05:05:40 PM PDT 24
Finished Jul 07 05:05:57 PM PDT 24
Peak memory 219012 kb
Host smart-3e123bfd-aa98-4323-a7e6-6efa61a0f5b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325766344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1325766344
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2962135846
Short name T382
Test name
Test status
Simulation time 3974243640 ps
CPU time 16.47 seconds
Started Jul 07 05:06:00 PM PDT 24
Finished Jul 07 05:06:17 PM PDT 24
Peak memory 218976 kb
Host smart-9e140f95-fb94-46a9-b7ea-f46f13b50cc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962135846 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2962135846
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1434081505
Short name T388
Test name
Test status
Simulation time 1568254634 ps
CPU time 13.01 seconds
Started Jul 07 05:05:48 PM PDT 24
Finished Jul 07 05:06:01 PM PDT 24
Peak memory 210664 kb
Host smart-f18a1387-988c-429a-846d-f6383783bfcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434081505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1434081505
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3311322385
Short name T467
Test name
Test status
Simulation time 4581864145 ps
CPU time 53.46 seconds
Started Jul 07 05:05:45 PM PDT 24
Finished Jul 07 05:06:39 PM PDT 24
Peak memory 210640 kb
Host smart-d86d591b-8b04-45ed-8f14-fcc5be9375f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311322385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3311322385
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3866644726
Short name T407
Test name
Test status
Simulation time 8460656550 ps
CPU time 18.06 seconds
Started Jul 07 05:05:45 PM PDT 24
Finished Jul 07 05:06:03 PM PDT 24
Peak memory 210852 kb
Host smart-445881a1-4988-47ba-a608-3039f1e6c64b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866644726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3866644726
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.811997448
Short name T395
Test name
Test status
Simulation time 27762689621 ps
CPU time 20.94 seconds
Started Jul 07 05:05:46 PM PDT 24
Finished Jul 07 05:06:07 PM PDT 24
Peak memory 219000 kb
Host smart-8ac147a6-c923-4f4b-b6dd-6308ec0ecd06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811997448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.811997448
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3936745535
Short name T106
Test name
Test status
Simulation time 3512739201 ps
CPU time 77.38 seconds
Started Jul 07 05:05:47 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 219000 kb
Host smart-d4303824-f09d-4860-982f-347a77237752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936745535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3936745535
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1349328811
Short name T414
Test name
Test status
Simulation time 704465811 ps
CPU time 8.91 seconds
Started Jul 07 05:05:51 PM PDT 24
Finished Jul 07 05:06:00 PM PDT 24
Peak memory 218956 kb
Host smart-9091c16d-040b-4357-90a0-4401147da040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349328811 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1349328811
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2291994725
Short name T453
Test name
Test status
Simulation time 12303190477 ps
CPU time 16.88 seconds
Started Jul 07 05:05:46 PM PDT 24
Finished Jul 07 05:06:03 PM PDT 24
Peak memory 218816 kb
Host smart-2b08d171-4df9-41ff-9571-c01b724ecf36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291994725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2291994725
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2368205977
Short name T451
Test name
Test status
Simulation time 6362532341 ps
CPU time 15.5 seconds
Started Jul 07 05:05:46 PM PDT 24
Finished Jul 07 05:06:02 PM PDT 24
Peak memory 210780 kb
Host smart-56b2d58f-15d2-4bcf-9474-70536417f41c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368205977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2368205977
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1412182879
Short name T445
Test name
Test status
Simulation time 150466782 ps
CPU time 9.96 seconds
Started Jul 07 05:05:46 PM PDT 24
Finished Jul 07 05:05:56 PM PDT 24
Peak memory 218844 kb
Host smart-56c3ed7f-96b6-444d-a6eb-ee2df59c6063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412182879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1412182879
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1385811986
Short name T437
Test name
Test status
Simulation time 324260841 ps
CPU time 40.26 seconds
Started Jul 07 05:05:46 PM PDT 24
Finished Jul 07 05:06:26 PM PDT 24
Peak memory 212848 kb
Host smart-70e9d0d6-d863-4575-b901-ecd914206de4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385811986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1385811986
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3243122346
Short name T410
Test name
Test status
Simulation time 3672726735 ps
CPU time 14.94 seconds
Started Jul 07 05:05:51 PM PDT 24
Finished Jul 07 05:06:06 PM PDT 24
Peak memory 219020 kb
Host smart-8a70476e-09f9-4986-b5f0-96ae30cca5de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243122346 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3243122346
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.622322622
Short name T73
Test name
Test status
Simulation time 85588798 ps
CPU time 4.31 seconds
Started Jul 07 05:05:50 PM PDT 24
Finished Jul 07 05:05:55 PM PDT 24
Peak memory 210652 kb
Host smart-305488ec-ff49-4704-8f52-6550be10ff9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622322622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.622322622
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1781891649
Short name T57
Test name
Test status
Simulation time 139585519432 ps
CPU time 71.05 seconds
Started Jul 07 05:05:51 PM PDT 24
Finished Jul 07 05:07:03 PM PDT 24
Peak memory 210692 kb
Host smart-9a9b8716-91cd-4bec-8ead-4b2a8f897516
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781891649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1781891649
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.153647785
Short name T450
Test name
Test status
Simulation time 5912291409 ps
CPU time 8.66 seconds
Started Jul 07 05:05:51 PM PDT 24
Finished Jul 07 05:06:00 PM PDT 24
Peak memory 218968 kb
Host smart-4a03c7ab-c539-48ae-afbf-b40e984560db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153647785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.153647785
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2447257614
Short name T372
Test name
Test status
Simulation time 515215038 ps
CPU time 9.13 seconds
Started Jul 07 05:05:50 PM PDT 24
Finished Jul 07 05:06:00 PM PDT 24
Peak memory 218824 kb
Host smart-7873e687-9ef7-4c31-8d4e-ac8d14c1ecc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447257614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2447257614
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3582182611
Short name T429
Test name
Test status
Simulation time 5997412668 ps
CPU time 13.33 seconds
Started Jul 07 05:05:59 PM PDT 24
Finished Jul 07 05:06:13 PM PDT 24
Peak memory 219000 kb
Host smart-e2f48c87-1c00-44bc-99b7-104f902c7d9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582182611 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3582182611
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1962547732
Short name T94
Test name
Test status
Simulation time 3987939020 ps
CPU time 15.74 seconds
Started Jul 07 05:06:00 PM PDT 24
Finished Jul 07 05:06:16 PM PDT 24
Peak memory 210708 kb
Host smart-04f0bf6b-e8ca-4218-b5fa-73f762010488
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962547732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1962547732
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1713578494
Short name T68
Test name
Test status
Simulation time 35941244633 ps
CPU time 69.34 seconds
Started Jul 07 05:05:50 PM PDT 24
Finished Jul 07 05:07:00 PM PDT 24
Peak memory 210756 kb
Host smart-b6940df2-4426-40e0-8e7c-798e383b41e8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713578494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1713578494
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3541706823
Short name T411
Test name
Test status
Simulation time 6346123775 ps
CPU time 14.83 seconds
Started Jul 07 05:05:55 PM PDT 24
Finished Jul 07 05:06:10 PM PDT 24
Peak memory 218912 kb
Host smart-d38cd2b6-1ea1-4d78-a1b3-942002463679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541706823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3541706823
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3089723087
Short name T397
Test name
Test status
Simulation time 1935734761 ps
CPU time 17.22 seconds
Started Jul 07 05:05:50 PM PDT 24
Finished Jul 07 05:06:08 PM PDT 24
Peak memory 218872 kb
Host smart-c4cb72ea-a3e7-49c4-b43b-d87948938d88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089723087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3089723087
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2846193097
Short name T109
Test name
Test status
Simulation time 4189830101 ps
CPU time 44.13 seconds
Started Jul 07 05:05:55 PM PDT 24
Finished Jul 07 05:06:39 PM PDT 24
Peak memory 218948 kb
Host smart-96050a4f-7abc-423b-b21c-a562d2b461bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846193097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2846193097
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2241493335
Short name T390
Test name
Test status
Simulation time 2216101999 ps
CPU time 10.84 seconds
Started Jul 07 05:05:59 PM PDT 24
Finished Jul 07 05:06:10 PM PDT 24
Peak memory 218996 kb
Host smart-6414ab9c-33ba-4399-9212-3cebf2e9fb28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241493335 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2241493335
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2053012660
Short name T55
Test name
Test status
Simulation time 984121640 ps
CPU time 10.33 seconds
Started Jul 07 05:05:56 PM PDT 24
Finished Jul 07 05:06:06 PM PDT 24
Peak memory 218520 kb
Host smart-d492d4b5-44c5-4bc0-9d04-d6a3728b479b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053012660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2053012660
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3686506169
Short name T452
Test name
Test status
Simulation time 23941540246 ps
CPU time 45.96 seconds
Started Jul 07 05:05:55 PM PDT 24
Finished Jul 07 05:06:42 PM PDT 24
Peak memory 210800 kb
Host smart-1a285d98-b24e-4b31-a1ea-69fe6bf25f35
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686506169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3686506169
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.351419484
Short name T456
Test name
Test status
Simulation time 1719479983 ps
CPU time 7.09 seconds
Started Jul 07 05:05:55 PM PDT 24
Finished Jul 07 05:06:02 PM PDT 24
Peak memory 210768 kb
Host smart-475b7335-eb45-491c-b0df-e613557f9c06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351419484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.351419484
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1238834742
Short name T401
Test name
Test status
Simulation time 1263484312 ps
CPU time 16.03 seconds
Started Jul 07 05:05:57 PM PDT 24
Finished Jul 07 05:06:13 PM PDT 24
Peak memory 218920 kb
Host smart-32f60b4d-2fa2-46dc-a46c-a9d05d867e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238834742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1238834742
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2902126438
Short name T99
Test name
Test status
Simulation time 6096069276 ps
CPU time 44.1 seconds
Started Jul 07 05:05:57 PM PDT 24
Finished Jul 07 05:06:41 PM PDT 24
Peak memory 218952 kb
Host smart-3ea74303-5d11-4112-a500-989c73550f95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902126438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2902126438
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1304998437
Short name T444
Test name
Test status
Simulation time 179422969 ps
CPU time 4.46 seconds
Started Jul 07 05:06:04 PM PDT 24
Finished Jul 07 05:06:08 PM PDT 24
Peak memory 218824 kb
Host smart-398d3972-8945-498b-a838-bec3f964574c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304998437 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1304998437
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2734151711
Short name T78
Test name
Test status
Simulation time 321775500 ps
CPU time 4.2 seconds
Started Jul 07 05:05:56 PM PDT 24
Finished Jul 07 05:06:00 PM PDT 24
Peak memory 217632 kb
Host smart-d65bda29-7627-4ce0-9de4-dbc83647344b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734151711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2734151711
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.233586584
Short name T97
Test name
Test status
Simulation time 3344908241 ps
CPU time 30.12 seconds
Started Jul 07 05:06:00 PM PDT 24
Finished Jul 07 05:06:31 PM PDT 24
Peak memory 210716 kb
Host smart-f8c4961e-7986-4dff-b4b6-5f8b803c6c8f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233586584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.233586584
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4216710263
Short name T448
Test name
Test status
Simulation time 2477511453 ps
CPU time 13.65 seconds
Started Jul 07 05:05:56 PM PDT 24
Finished Jul 07 05:06:10 PM PDT 24
Peak memory 218956 kb
Host smart-89b8807e-de89-477e-908a-c132a165f17b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216710263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4216710263
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4188880062
Short name T371
Test name
Test status
Simulation time 2471766192 ps
CPU time 13.53 seconds
Started Jul 07 05:05:56 PM PDT 24
Finished Jul 07 05:06:10 PM PDT 24
Peak memory 218980 kb
Host smart-cc8c3139-67fd-4b27-8bfb-327da411cac7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188880062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4188880062
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.57599920
Short name T108
Test name
Test status
Simulation time 2276259884 ps
CPU time 72.76 seconds
Started Jul 07 05:05:55 PM PDT 24
Finished Jul 07 05:07:08 PM PDT 24
Peak memory 218968 kb
Host smart-b3bedb09-5184-49d6-b4db-e290be7c001b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57599920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_int
g_err.57599920
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2537296959
Short name T409
Test name
Test status
Simulation time 2576885139 ps
CPU time 14.9 seconds
Started Jul 07 05:06:01 PM PDT 24
Finished Jul 07 05:06:17 PM PDT 24
Peak memory 219020 kb
Host smart-b11e996d-0fd5-44e6-8447-cd359e766b14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537296959 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2537296959
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.177706128
Short name T418
Test name
Test status
Simulation time 8922247489 ps
CPU time 13.14 seconds
Started Jul 07 05:06:00 PM PDT 24
Finished Jul 07 05:06:13 PM PDT 24
Peak memory 210680 kb
Host smart-83d7d520-f6de-4b1a-947f-e59163704226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177706128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.177706128
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4186126064
Short name T412
Test name
Test status
Simulation time 19118075539 ps
CPU time 48.06 seconds
Started Jul 07 05:06:01 PM PDT 24
Finished Jul 07 05:06:50 PM PDT 24
Peak memory 210760 kb
Host smart-ca2d6c9b-6e03-46fa-8d8a-7098c30e607c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186126064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4186126064
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3018686223
Short name T89
Test name
Test status
Simulation time 1656246438 ps
CPU time 4.23 seconds
Started Jul 07 05:06:02 PM PDT 24
Finished Jul 07 05:06:07 PM PDT 24
Peak memory 218192 kb
Host smart-42953215-9b47-4bc2-8346-64adba92829d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018686223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3018686223
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3342721867
Short name T438
Test name
Test status
Simulation time 3578084423 ps
CPU time 20.27 seconds
Started Jul 07 05:06:02 PM PDT 24
Finished Jul 07 05:06:23 PM PDT 24
Peak memory 218976 kb
Host smart-1a2232b7-d97c-42b7-97b6-46817f7b3b32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342721867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3342721867
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3750421020
Short name T416
Test name
Test status
Simulation time 106743150 ps
CPU time 5.15 seconds
Started Jul 07 05:06:00 PM PDT 24
Finished Jul 07 05:06:06 PM PDT 24
Peak memory 218964 kb
Host smart-813ac5ab-d177-47a9-abda-d2c59540a8c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750421020 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3750421020
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.182701237
Short name T425
Test name
Test status
Simulation time 978658880 ps
CPU time 10.22 seconds
Started Jul 07 05:06:04 PM PDT 24
Finished Jul 07 05:06:14 PM PDT 24
Peak memory 210528 kb
Host smart-eb4dcb7c-9c3a-4568-bce0-5892103f56e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182701237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.182701237
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3767688780
Short name T76
Test name
Test status
Simulation time 2024131582 ps
CPU time 28.41 seconds
Started Jul 07 05:06:02 PM PDT 24
Finished Jul 07 05:06:30 PM PDT 24
Peak memory 210692 kb
Host smart-8d714c68-c2cc-4f00-abe9-e25cc8570756
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767688780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3767688780
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4141076574
Short name T90
Test name
Test status
Simulation time 347954966 ps
CPU time 5.46 seconds
Started Jul 07 05:06:01 PM PDT 24
Finished Jul 07 05:06:07 PM PDT 24
Peak memory 217732 kb
Host smart-69b38040-0dfd-47ee-b019-fc235b5b75ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141076574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4141076574
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2613072283
Short name T392
Test name
Test status
Simulation time 5966566494 ps
CPU time 9.99 seconds
Started Jul 07 05:06:01 PM PDT 24
Finished Jul 07 05:06:12 PM PDT 24
Peak memory 219012 kb
Host smart-9d761261-7685-405f-a3b9-fa6033997ef3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613072283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2613072283
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2255900160
Short name T111
Test name
Test status
Simulation time 1793646254 ps
CPU time 41.77 seconds
Started Jul 07 05:06:01 PM PDT 24
Finished Jul 07 05:06:43 PM PDT 24
Peak memory 218904 kb
Host smart-a87d89a6-a215-4e84-af4b-bfdbd5ee37cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255900160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2255900160
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1833302920
Short name T461
Test name
Test status
Simulation time 3904727868 ps
CPU time 14.84 seconds
Started Jul 07 05:05:24 PM PDT 24
Finished Jul 07 05:05:39 PM PDT 24
Peak memory 218856 kb
Host smart-fd4df2d4-5b75-4765-8940-9af36855b99e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833302920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1833302920
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2748019550
Short name T454
Test name
Test status
Simulation time 2577134552 ps
CPU time 13.71 seconds
Started Jul 07 05:05:22 PM PDT 24
Finished Jul 07 05:05:36 PM PDT 24
Peak memory 210768 kb
Host smart-49aeaecd-ca90-40b4-8ebe-37ecf1ae5c38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748019550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2748019550
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3217554778
Short name T77
Test name
Test status
Simulation time 4339223212 ps
CPU time 15.58 seconds
Started Jul 07 05:05:20 PM PDT 24
Finished Jul 07 05:05:36 PM PDT 24
Peak memory 210648 kb
Host smart-4f76348d-bd49-44c3-b96f-07a056ff4462
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217554778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3217554778
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1109532982
Short name T381
Test name
Test status
Simulation time 333714715 ps
CPU time 6.2 seconds
Started Jul 07 05:05:20 PM PDT 24
Finished Jul 07 05:05:26 PM PDT 24
Peak memory 213324 kb
Host smart-a6d88d04-7560-4e49-b875-b47f04ba5339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109532982 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1109532982
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.539660644
Short name T426
Test name
Test status
Simulation time 346426610 ps
CPU time 4.25 seconds
Started Jul 07 05:05:21 PM PDT 24
Finished Jul 07 05:05:26 PM PDT 24
Peak memory 210580 kb
Host smart-333c4c28-3ed6-4b04-9174-a7c2c7422165
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539660644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.539660644
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3535604417
Short name T403
Test name
Test status
Simulation time 1376351091 ps
CPU time 6.63 seconds
Started Jul 07 05:05:21 PM PDT 24
Finished Jul 07 05:05:28 PM PDT 24
Peak memory 210492 kb
Host smart-a3b4ac10-9f03-429e-8cff-5f32edace3df
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535604417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3535604417
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3628019954
Short name T405
Test name
Test status
Simulation time 3780342045 ps
CPU time 16.21 seconds
Started Jul 07 05:05:15 PM PDT 24
Finished Jul 07 05:05:32 PM PDT 24
Peak memory 210612 kb
Host smart-4fbbcbcc-d2dc-4890-8fb7-f208e3a25b36
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628019954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3628019954
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.740514805
Short name T79
Test name
Test status
Simulation time 27788852401 ps
CPU time 65.99 seconds
Started Jul 07 05:05:40 PM PDT 24
Finished Jul 07 05:06:46 PM PDT 24
Peak memory 210760 kb
Host smart-647e4c5e-1109-4d27-930c-dc128dd769d7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740514805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.740514805
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3999463957
Short name T91
Test name
Test status
Simulation time 535250434 ps
CPU time 7.73 seconds
Started Jul 07 05:05:22 PM PDT 24
Finished Jul 07 05:05:30 PM PDT 24
Peak memory 210772 kb
Host smart-ecb4315f-d3e3-4ba0-8d85-d78ea5c8b409
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999463957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3999463957
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.588234607
Short name T393
Test name
Test status
Simulation time 8672288783 ps
CPU time 20.94 seconds
Started Jul 07 05:05:16 PM PDT 24
Finished Jul 07 05:05:37 PM PDT 24
Peak memory 218992 kb
Host smart-63aa276c-2781-41d0-ac08-b2098d6eafd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588234607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.588234607
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1625696074
Short name T102
Test name
Test status
Simulation time 2020737254 ps
CPU time 48.19 seconds
Started Jul 07 05:05:15 PM PDT 24
Finished Jul 07 05:06:03 PM PDT 24
Peak memory 212056 kb
Host smart-2cfdae01-bb9d-423f-b327-b30a0cdd0290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625696074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1625696074
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2432777389
Short name T66
Test name
Test status
Simulation time 973477021 ps
CPU time 9.71 seconds
Started Jul 07 05:05:20 PM PDT 24
Finished Jul 07 05:05:30 PM PDT 24
Peak memory 217540 kb
Host smart-7a2c25f3-8031-4714-8513-ff659210a86a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432777389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2432777389
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3589940475
Short name T413
Test name
Test status
Simulation time 1082173239 ps
CPU time 7.71 seconds
Started Jul 07 05:05:22 PM PDT 24
Finished Jul 07 05:05:30 PM PDT 24
Peak memory 210592 kb
Host smart-398ffb57-c23b-4d8f-b29d-91078d58757e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589940475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3589940475
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2906053838
Short name T64
Test name
Test status
Simulation time 1046425833 ps
CPU time 5.59 seconds
Started Jul 07 05:05:22 PM PDT 24
Finished Jul 07 05:05:28 PM PDT 24
Peak memory 217320 kb
Host smart-4c321042-715b-41d6-be97-8996b97069b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906053838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2906053838
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1325383813
Short name T374
Test name
Test status
Simulation time 2706107257 ps
CPU time 11.23 seconds
Started Jul 07 05:05:25 PM PDT 24
Finished Jul 07 05:05:36 PM PDT 24
Peak memory 219052 kb
Host smart-b33b2fad-10da-4ee5-a096-1f84bddfd1da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325383813 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1325383813
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2238891988
Short name T427
Test name
Test status
Simulation time 2028986892 ps
CPU time 15.27 seconds
Started Jul 07 05:05:23 PM PDT 24
Finished Jul 07 05:05:38 PM PDT 24
Peak memory 210604 kb
Host smart-1c5673e3-e2f7-49d9-81c0-fdf8c805fb8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238891988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2238891988
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1682136798
Short name T373
Test name
Test status
Simulation time 2680199534 ps
CPU time 12.12 seconds
Started Jul 07 05:05:22 PM PDT 24
Finished Jul 07 05:05:34 PM PDT 24
Peak memory 210532 kb
Host smart-b2d9703f-66c3-4040-9ea9-75f6f9ac460a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682136798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1682136798
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1590694829
Short name T457
Test name
Test status
Simulation time 85705901 ps
CPU time 4.3 seconds
Started Jul 07 05:05:20 PM PDT 24
Finished Jul 07 05:05:25 PM PDT 24
Peak memory 210556 kb
Host smart-657e3b6e-70d1-4309-b9fa-e17a5d20539e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590694829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1590694829
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2596560316
Short name T436
Test name
Test status
Simulation time 21300009571 ps
CPU time 51.1 seconds
Started Jul 07 05:05:20 PM PDT 24
Finished Jul 07 05:06:12 PM PDT 24
Peak memory 210664 kb
Host smart-3b95f1b9-2cd4-4e80-8fe1-a3e8757f451e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596560316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2596560316
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2510423725
Short name T423
Test name
Test status
Simulation time 6439048208 ps
CPU time 13.18 seconds
Started Jul 07 05:05:24 PM PDT 24
Finished Jul 07 05:05:38 PM PDT 24
Peak memory 218940 kb
Host smart-180e36d8-88b9-4054-bf8a-44b3e22aef2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510423725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2510423725
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1900117636
Short name T386
Test name
Test status
Simulation time 792774441 ps
CPU time 13.74 seconds
Started Jul 07 05:05:19 PM PDT 24
Finished Jul 07 05:05:33 PM PDT 24
Peak memory 218840 kb
Host smart-d37ca1fe-9bc4-488e-a414-23f0835e530d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900117636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1900117636
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1806470595
Short name T52
Test name
Test status
Simulation time 325790723 ps
CPU time 37.46 seconds
Started Jul 07 05:05:23 PM PDT 24
Finished Jul 07 05:06:00 PM PDT 24
Peak memory 212220 kb
Host smart-10402375-a056-4809-be71-7bd4b9a7c0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806470595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1806470595
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3207476173
Short name T74
Test name
Test status
Simulation time 3973594151 ps
CPU time 15.29 seconds
Started Jul 07 05:05:26 PM PDT 24
Finished Jul 07 05:05:42 PM PDT 24
Peak memory 218840 kb
Host smart-4ef89c67-bdda-4592-9eb5-c640a13b501f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207476173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3207476173
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.340501375
Short name T387
Test name
Test status
Simulation time 174949504 ps
CPU time 4.52 seconds
Started Jul 07 05:05:25 PM PDT 24
Finished Jul 07 05:05:30 PM PDT 24
Peak memory 210592 kb
Host smart-e0456958-b214-4a2d-988b-3447729bc19c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340501375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.340501375
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4170735149
Short name T415
Test name
Test status
Simulation time 306015223 ps
CPU time 5.68 seconds
Started Jul 07 05:05:28 PM PDT 24
Finished Jul 07 05:05:34 PM PDT 24
Peak memory 210636 kb
Host smart-c24c9155-01f1-4519-853a-6e9f3bc4cffe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170735149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4170735149
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.321419503
Short name T463
Test name
Test status
Simulation time 5052072677 ps
CPU time 10.2 seconds
Started Jul 07 05:05:25 PM PDT 24
Finished Jul 07 05:05:36 PM PDT 24
Peak memory 219020 kb
Host smart-b5c9aa2a-b3cf-4a93-b8a0-627aeb44742a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321419503 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.321419503
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.980197670
Short name T443
Test name
Test status
Simulation time 16468404991 ps
CPU time 9.93 seconds
Started Jul 07 05:05:28 PM PDT 24
Finished Jul 07 05:05:38 PM PDT 24
Peak memory 210700 kb
Host smart-1eb0ceaa-7166-4f8f-8336-bf526f8ceafe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980197670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.980197670
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.48427019
Short name T377
Test name
Test status
Simulation time 15657495396 ps
CPU time 15.51 seconds
Started Jul 07 05:05:25 PM PDT 24
Finished Jul 07 05:05:40 PM PDT 24
Peak memory 210496 kb
Host smart-6c4b811c-3b05-4b7d-be6f-a01ef2afeb2a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48427019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_
mem_partial_access.48427019
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2661033516
Short name T400
Test name
Test status
Simulation time 1752731211 ps
CPU time 14.3 seconds
Started Jul 07 05:05:24 PM PDT 24
Finished Jul 07 05:05:39 PM PDT 24
Peak memory 210548 kb
Host smart-426f924e-7fdd-4d52-b4f4-85f7d101298b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661033516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2661033516
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.202245891
Short name T63
Test name
Test status
Simulation time 16552752172 ps
CPU time 57.34 seconds
Started Jul 07 05:05:26 PM PDT 24
Finished Jul 07 05:06:24 PM PDT 24
Peak memory 210856 kb
Host smart-8cbfb7ac-2ad3-4816-bd6e-53d8a7c20b1e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202245891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.202245891
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.56551870
Short name T408
Test name
Test status
Simulation time 1458047388 ps
CPU time 8.84 seconds
Started Jul 07 05:05:25 PM PDT 24
Finished Jul 07 05:05:35 PM PDT 24
Peak memory 210684 kb
Host smart-66c3ef89-9913-4dbd-a6b9-5725e7dab9a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56551870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_same_csr_outstanding.56551870
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3098667296
Short name T424
Test name
Test status
Simulation time 2296461227 ps
CPU time 11.45 seconds
Started Jul 07 05:05:26 PM PDT 24
Finished Jul 07 05:05:38 PM PDT 24
Peak memory 218988 kb
Host smart-eb4c937a-0322-4bf6-801f-3069f30f1e16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098667296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3098667296
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1301635515
Short name T110
Test name
Test status
Simulation time 1846691230 ps
CPU time 78.34 seconds
Started Jul 07 05:05:25 PM PDT 24
Finished Jul 07 05:06:44 PM PDT 24
Peak memory 212296 kb
Host smart-6cd753b8-e9bb-4985-b3ac-9815008dd215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301635515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1301635515
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2779429915
Short name T378
Test name
Test status
Simulation time 206454730 ps
CPU time 5.18 seconds
Started Jul 07 05:05:31 PM PDT 24
Finished Jul 07 05:05:36 PM PDT 24
Peak memory 219000 kb
Host smart-0770633b-2669-447a-a9f2-9e36ec309a35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779429915 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2779429915
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3725752255
Short name T466
Test name
Test status
Simulation time 1905276585 ps
CPU time 7.54 seconds
Started Jul 07 05:05:32 PM PDT 24
Finished Jul 07 05:05:39 PM PDT 24
Peak memory 217556 kb
Host smart-136c3c69-b511-4b12-ab26-4a0555a1a027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725752255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3725752255
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4271779286
Short name T462
Test name
Test status
Simulation time 6239908446 ps
CPU time 49.33 seconds
Started Jul 07 05:05:25 PM PDT 24
Finished Jul 07 05:06:15 PM PDT 24
Peak memory 210740 kb
Host smart-a6d5db4b-84ab-4e37-a57b-42facbe4319c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271779286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4271779286
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.307427875
Short name T435
Test name
Test status
Simulation time 1453043213 ps
CPU time 12.65 seconds
Started Jul 07 05:05:31 PM PDT 24
Finished Jul 07 05:05:44 PM PDT 24
Peak memory 210760 kb
Host smart-5d85b0e1-c2e3-4c70-93bb-2556dc525af8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307427875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.307427875
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2151987212
Short name T396
Test name
Test status
Simulation time 1164304981 ps
CPU time 15 seconds
Started Jul 07 05:05:31 PM PDT 24
Finished Jul 07 05:05:46 PM PDT 24
Peak memory 218940 kb
Host smart-56259463-2839-4f23-a190-3429c2dfd6e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151987212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2151987212
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.624540131
Short name T54
Test name
Test status
Simulation time 4756574903 ps
CPU time 74.92 seconds
Started Jul 07 05:05:31 PM PDT 24
Finished Jul 07 05:06:46 PM PDT 24
Peak memory 212620 kb
Host smart-87f066ae-98c1-4c87-8ea7-a1d629b483ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624540131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.624540131
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3228025143
Short name T398
Test name
Test status
Simulation time 5110256409 ps
CPU time 10.12 seconds
Started Jul 07 05:05:35 PM PDT 24
Finished Jul 07 05:05:46 PM PDT 24
Peak memory 219012 kb
Host smart-e4820a62-7235-4903-988c-de8ed6e64633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228025143 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3228025143
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3885863608
Short name T420
Test name
Test status
Simulation time 1291733229 ps
CPU time 11.84 seconds
Started Jul 07 05:05:37 PM PDT 24
Finished Jul 07 05:05:49 PM PDT 24
Peak memory 218712 kb
Host smart-d715e2b1-6a35-499a-b04a-16aa1d067422
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885863608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3885863608
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3843447497
Short name T80
Test name
Test status
Simulation time 34250699331 ps
CPU time 67.51 seconds
Started Jul 07 05:05:31 PM PDT 24
Finished Jul 07 05:06:38 PM PDT 24
Peak memory 210632 kb
Host smart-ac1576e8-4fd7-40bc-9281-2ff4883a5fa5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843447497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3843447497
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1051347910
Short name T61
Test name
Test status
Simulation time 729119917 ps
CPU time 8.61 seconds
Started Jul 07 05:05:37 PM PDT 24
Finished Jul 07 05:05:46 PM PDT 24
Peak memory 210744 kb
Host smart-a588201d-57af-475a-8b3d-bb93c5066245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051347910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1051347910
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.350453212
Short name T422
Test name
Test status
Simulation time 476890272 ps
CPU time 9.92 seconds
Started Jul 07 05:05:34 PM PDT 24
Finished Jul 07 05:05:44 PM PDT 24
Peak memory 218920 kb
Host smart-870b07ae-0ad1-45db-b010-49f5db58490c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350453212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.350453212
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2363524093
Short name T464
Test name
Test status
Simulation time 894130124 ps
CPU time 40.03 seconds
Started Jul 07 05:05:38 PM PDT 24
Finished Jul 07 05:06:18 PM PDT 24
Peak memory 218904 kb
Host smart-3aacfc74-402a-429c-a8a9-0cbdcf5b0d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363524093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2363524093
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3831423947
Short name T384
Test name
Test status
Simulation time 8933075027 ps
CPU time 8.8 seconds
Started Jul 07 05:05:35 PM PDT 24
Finished Jul 07 05:05:44 PM PDT 24
Peak memory 218988 kb
Host smart-4d0f6270-4f21-44a4-93ef-31e8206cf2d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831423947 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3831423947
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3568795223
Short name T88
Test name
Test status
Simulation time 88997890 ps
CPU time 4.18 seconds
Started Jul 07 05:05:35 PM PDT 24
Finished Jul 07 05:05:40 PM PDT 24
Peak memory 210684 kb
Host smart-3281d5cb-f3c6-4059-b43d-ce687e5c0b92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568795223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3568795223
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1990876628
Short name T67
Test name
Test status
Simulation time 4428420723 ps
CPU time 25.67 seconds
Started Jul 07 05:05:35 PM PDT 24
Finished Jul 07 05:06:01 PM PDT 24
Peak memory 210660 kb
Host smart-1073c6b0-41f4-48b2-a4f6-0c2b7f3860f0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990876628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1990876628
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4166078734
Short name T458
Test name
Test status
Simulation time 1787852756 ps
CPU time 14.42 seconds
Started Jul 07 05:05:35 PM PDT 24
Finished Jul 07 05:05:50 PM PDT 24
Peak memory 210748 kb
Host smart-6ee6b494-1014-45d3-84a6-7d30cffbba82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166078734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.4166078734
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.607254553
Short name T385
Test name
Test status
Simulation time 595412768 ps
CPU time 10.38 seconds
Started Jul 07 05:05:35 PM PDT 24
Finished Jul 07 05:05:46 PM PDT 24
Peak memory 218836 kb
Host smart-1397cc21-a2af-4cc0-99c8-c3bda6f02842
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607254553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.607254553
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1043118410
Short name T442
Test name
Test status
Simulation time 1995809383 ps
CPU time 15.07 seconds
Started Jul 07 05:05:42 PM PDT 24
Finished Jul 07 05:05:57 PM PDT 24
Peak memory 218936 kb
Host smart-f5f0ec0f-52e5-4658-b570-5036869899d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043118410 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1043118410
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3714183410
Short name T419
Test name
Test status
Simulation time 1983776011 ps
CPU time 15.24 seconds
Started Jul 07 05:05:35 PM PDT 24
Finished Jul 07 05:05:51 PM PDT 24
Peak memory 210588 kb
Host smart-1fa149d7-0c89-4257-b486-dbb1c8a1fc44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714183410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3714183410
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1446201655
Short name T65
Test name
Test status
Simulation time 4819971361 ps
CPU time 46.36 seconds
Started Jul 07 05:05:37 PM PDT 24
Finished Jul 07 05:06:23 PM PDT 24
Peak memory 210752 kb
Host smart-6be268a5-6abd-4a22-a90c-bfe31f98f31d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446201655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1446201655
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2929398632
Short name T86
Test name
Test status
Simulation time 1280573820 ps
CPU time 9.39 seconds
Started Jul 07 05:05:37 PM PDT 24
Finished Jul 07 05:05:46 PM PDT 24
Peak memory 219228 kb
Host smart-9e0f96a3-f0ff-4de9-b3f4-968b8e769820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929398632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2929398632
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1741759717
Short name T441
Test name
Test status
Simulation time 1196653396 ps
CPU time 14.36 seconds
Started Jul 07 05:05:36 PM PDT 24
Finished Jul 07 05:05:51 PM PDT 24
Peak memory 218924 kb
Host smart-b42053e7-b5af-44b0-bf3e-1d732e7e5f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741759717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1741759717
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.721579528
Short name T101
Test name
Test status
Simulation time 368728370 ps
CPU time 38.13 seconds
Started Jul 07 05:05:36 PM PDT 24
Finished Jul 07 05:06:14 PM PDT 24
Peak memory 218888 kb
Host smart-2dd0c636-61df-464d-8f75-ae82116c0a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721579528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.721579528
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2597786708
Short name T375
Test name
Test status
Simulation time 2086383954 ps
CPU time 6.18 seconds
Started Jul 07 05:05:42 PM PDT 24
Finished Jul 07 05:05:48 PM PDT 24
Peak memory 218760 kb
Host smart-6c16a6e1-44e0-4376-8f0b-a806df6ba87c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597786708 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2597786708
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2535832774
Short name T431
Test name
Test status
Simulation time 1965058222 ps
CPU time 15.85 seconds
Started Jul 07 05:05:41 PM PDT 24
Finished Jul 07 05:05:57 PM PDT 24
Peak memory 218704 kb
Host smart-65869e4a-d2d2-4f65-ad21-50c11ba0c65c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535832774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2535832774
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1651384916
Short name T459
Test name
Test status
Simulation time 1838281865 ps
CPU time 30.32 seconds
Started Jul 07 05:05:42 PM PDT 24
Finished Jul 07 05:06:12 PM PDT 24
Peak memory 210624 kb
Host smart-7f38984f-e93e-4411-bc78-12e4d7816713
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651384916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1651384916
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2130947612
Short name T446
Test name
Test status
Simulation time 1286997377 ps
CPU time 10.1 seconds
Started Jul 07 05:05:41 PM PDT 24
Finished Jul 07 05:05:51 PM PDT 24
Peak memory 218848 kb
Host smart-5869b495-d375-4748-b5da-5273a25e06d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130947612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2130947612
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4014065691
Short name T430
Test name
Test status
Simulation time 1349812201 ps
CPU time 15.94 seconds
Started Jul 07 05:05:42 PM PDT 24
Finished Jul 07 05:05:58 PM PDT 24
Peak memory 218912 kb
Host smart-86471d36-5df3-4c00-9930-79f482e91561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014065691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4014065691
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3864429913
Short name T151
Test name
Test status
Simulation time 944940360 ps
CPU time 10.37 seconds
Started Jul 07 05:01:40 PM PDT 24
Finished Jul 07 05:01:50 PM PDT 24
Peak memory 211288 kb
Host smart-b326d7a8-d346-47d7-a47b-99460ede9e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864429913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3864429913
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2918589300
Short name T31
Test name
Test status
Simulation time 14194413151 ps
CPU time 208.52 seconds
Started Jul 07 05:01:38 PM PDT 24
Finished Jul 07 05:05:07 PM PDT 24
Peak memory 238600 kb
Host smart-82539b2a-eb35-4c03-968e-3de4c5cbe696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918589300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2918589300
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2127543413
Short name T293
Test name
Test status
Simulation time 5182642014 ps
CPU time 26.42 seconds
Started Jul 07 05:01:41 PM PDT 24
Finished Jul 07 05:02:08 PM PDT 24
Peak memory 211344 kb
Host smart-6d34236c-a1ef-48d9-b31c-b956cbd8e5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127543413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2127543413
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4092824050
Short name T208
Test name
Test status
Simulation time 4286480520 ps
CPU time 11.52 seconds
Started Jul 07 05:01:40 PM PDT 24
Finished Jul 07 05:01:52 PM PDT 24
Peak memory 211320 kb
Host smart-30f02ce5-20b5-436b-a619-de8e4d4786ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092824050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4092824050
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2364710486
Short name T312
Test name
Test status
Simulation time 361063262 ps
CPU time 10.18 seconds
Started Jul 07 05:01:35 PM PDT 24
Finished Jul 07 05:01:45 PM PDT 24
Peak memory 213040 kb
Host smart-256940c8-adc7-4049-9b94-1c8d5f6c908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364710486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2364710486
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1304148017
Short name T119
Test name
Test status
Simulation time 17733874196 ps
CPU time 34.96 seconds
Started Jul 07 05:01:40 PM PDT 24
Finished Jul 07 05:02:15 PM PDT 24
Peak memory 219280 kb
Host smart-d0818b56-3b4b-460d-a3b3-319edb358948
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304148017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1304148017
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.397582064
Short name T187
Test name
Test status
Simulation time 1240127865 ps
CPU time 9.75 seconds
Started Jul 07 05:01:47 PM PDT 24
Finished Jul 07 05:01:57 PM PDT 24
Peak memory 211308 kb
Host smart-3c9b04fc-ed54-43b4-9339-7bcfb9f73ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397582064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.397582064
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2148288769
Short name T42
Test name
Test status
Simulation time 3652963242 ps
CPU time 63.32 seconds
Started Jul 07 05:01:43 PM PDT 24
Finished Jul 07 05:02:46 PM PDT 24
Peak memory 236720 kb
Host smart-d3206de2-e242-4537-b1fd-5c05372c6226
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148288769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2148288769
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2837040254
Short name T285
Test name
Test status
Simulation time 3917822410 ps
CPU time 16.3 seconds
Started Jul 07 05:01:43 PM PDT 24
Finished Jul 07 05:02:00 PM PDT 24
Peak memory 212076 kb
Host smart-5930017f-96cb-4ac2-8e90-aea64be62956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837040254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2837040254
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2794122448
Short name T298
Test name
Test status
Simulation time 102171157 ps
CPU time 5.87 seconds
Started Jul 07 05:01:41 PM PDT 24
Finished Jul 07 05:01:47 PM PDT 24
Peak memory 211288 kb
Host smart-32b5a39b-08f5-4ce6-83f5-695ca021d6b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2794122448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2794122448
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.999896644
Short name T4
Test name
Test status
Simulation time 698127687 ps
CPU time 54.7 seconds
Started Jul 07 05:01:48 PM PDT 24
Finished Jul 07 05:02:42 PM PDT 24
Peak memory 236752 kb
Host smart-085308aa-c614-4ebb-94ec-c817bc3a8545
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999896644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.999896644
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.96379604
Short name T203
Test name
Test status
Simulation time 2466703665 ps
CPU time 18.94 seconds
Started Jul 07 05:01:39 PM PDT 24
Finished Jul 07 05:01:58 PM PDT 24
Peak memory 213784 kb
Host smart-b017bfb0-04c0-47f3-8e7f-c014977078dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96379604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.96379604
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2753624911
Short name T192
Test name
Test status
Simulation time 884368096 ps
CPU time 21.74 seconds
Started Jul 07 05:01:42 PM PDT 24
Finished Jul 07 05:02:04 PM PDT 24
Peak memory 215084 kb
Host smart-5d812346-e34b-4a3b-b0e6-13c154754be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753624911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2753624911
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3782826288
Short name T125
Test name
Test status
Simulation time 4775190274 ps
CPU time 11.61 seconds
Started Jul 07 05:02:35 PM PDT 24
Finished Jul 07 05:02:47 PM PDT 24
Peak memory 211304 kb
Host smart-87765376-fe48-49e5-96ba-d32801e1eb08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782826288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3782826288
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.372020166
Short name T302
Test name
Test status
Simulation time 1829631316 ps
CPU time 106.7 seconds
Started Jul 07 05:02:30 PM PDT 24
Finished Jul 07 05:04:17 PM PDT 24
Peak memory 212540 kb
Host smart-f42defc5-5875-4092-b726-0d6625a4f527
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372020166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.372020166
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3871885220
Short name T284
Test name
Test status
Simulation time 4167112197 ps
CPU time 11.76 seconds
Started Jul 07 05:02:31 PM PDT 24
Finished Jul 07 05:02:43 PM PDT 24
Peak memory 211340 kb
Host smart-60b4bb9c-3b34-42ac-b670-a7be52dfd6be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871885220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3871885220
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.54264938
Short name T17
Test name
Test status
Simulation time 382408700 ps
CPU time 10.44 seconds
Started Jul 07 05:02:31 PM PDT 24
Finished Jul 07 05:02:42 PM PDT 24
Peak memory 213512 kb
Host smart-9ca481c6-c41f-4667-980c-0bdb2783ce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54264938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.54264938
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1536721626
Short name T360
Test name
Test status
Simulation time 714116348 ps
CPU time 10.74 seconds
Started Jul 07 05:02:31 PM PDT 24
Finished Jul 07 05:02:42 PM PDT 24
Peak memory 211212 kb
Host smart-27ec07d4-40b3-46de-84e0-6800e8ab4e42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536721626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1536721626
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.828030519
Short name T180
Test name
Test status
Simulation time 1974544989 ps
CPU time 10.07 seconds
Started Jul 07 05:02:40 PM PDT 24
Finished Jul 07 05:02:51 PM PDT 24
Peak memory 211296 kb
Host smart-8bdb2331-35c2-4cfb-b001-5fa961d38389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828030519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.828030519
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1572463953
Short name T207
Test name
Test status
Simulation time 45604832319 ps
CPU time 132.73 seconds
Started Jul 07 05:02:33 PM PDT 24
Finished Jul 07 05:04:46 PM PDT 24
Peak memory 237760 kb
Host smart-4d7837fa-c75f-46a0-b9e8-3c386fbfb68e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572463953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1572463953
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.293897999
Short name T38
Test name
Test status
Simulation time 2471289398 ps
CPU time 23.72 seconds
Started Jul 07 05:02:38 PM PDT 24
Finished Jul 07 05:03:02 PM PDT 24
Peak memory 213788 kb
Host smart-d6679204-b460-409f-8bae-55e8e617b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293897999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.293897999
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.63227499
Short name T237
Test name
Test status
Simulation time 1081916788 ps
CPU time 12.26 seconds
Started Jul 07 05:02:34 PM PDT 24
Finished Jul 07 05:02:47 PM PDT 24
Peak memory 211256 kb
Host smart-0e036e03-f689-4385-a35e-58560b3d4463
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=63227499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.63227499
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2231285208
Short name T369
Test name
Test status
Simulation time 4202248946 ps
CPU time 24.04 seconds
Started Jul 07 05:02:34 PM PDT 24
Finished Jul 07 05:02:58 PM PDT 24
Peak memory 213676 kb
Host smart-321ee6a0-5b6f-40a9-ab76-b779809a68c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231285208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2231285208
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1248460172
Short name T115
Test name
Test status
Simulation time 2821871382 ps
CPU time 27.25 seconds
Started Jul 07 05:02:33 PM PDT 24
Finished Jul 07 05:03:01 PM PDT 24
Peak memory 213660 kb
Host smart-d3475a0d-7074-43fc-bf55-ed72fecf396f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248460172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1248460172
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4246971888
Short name T305
Test name
Test status
Simulation time 270011102 ps
CPU time 4.26 seconds
Started Jul 07 05:02:42 PM PDT 24
Finished Jul 07 05:02:47 PM PDT 24
Peak memory 211288 kb
Host smart-a8f62a9e-92e5-47f6-b30c-07c3fe1fd54a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246971888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4246971888
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3226447522
Short name T194
Test name
Test status
Simulation time 103253403222 ps
CPU time 237.39 seconds
Started Jul 07 05:02:40 PM PDT 24
Finished Jul 07 05:06:37 PM PDT 24
Peak memory 212588 kb
Host smart-f89cbffd-77c9-4ace-8fed-7462cbc5b298
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226447522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3226447522
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3634584520
Short name T272
Test name
Test status
Simulation time 15008339597 ps
CPU time 31.79 seconds
Started Jul 07 05:02:41 PM PDT 24
Finished Jul 07 05:03:13 PM PDT 24
Peak memory 212156 kb
Host smart-46495141-fc34-4b2c-b32a-292e6b1f57ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634584520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3634584520
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2015510422
Short name T329
Test name
Test status
Simulation time 485160737 ps
CPU time 5.45 seconds
Started Jul 07 05:02:42 PM PDT 24
Finished Jul 07 05:02:48 PM PDT 24
Peak memory 211296 kb
Host smart-a711e7ff-13d6-4413-b4bc-73fb3a622f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015510422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2015510422
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2556598316
Short name T261
Test name
Test status
Simulation time 6823422932 ps
CPU time 27.16 seconds
Started Jul 07 05:02:39 PM PDT 24
Finished Jul 07 05:03:06 PM PDT 24
Peak memory 214500 kb
Host smart-caf9ae6f-f697-4c15-9923-6b6146bed46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556598316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2556598316
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1778780802
Short name T333
Test name
Test status
Simulation time 2600346377 ps
CPU time 8.17 seconds
Started Jul 07 05:02:42 PM PDT 24
Finished Jul 07 05:02:50 PM PDT 24
Peak memory 211364 kb
Host smart-bb5e3756-7e54-4687-9c23-fe25bab834d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778780802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1778780802
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3898567952
Short name T306
Test name
Test status
Simulation time 1594641333 ps
CPU time 13.31 seconds
Started Jul 07 05:02:47 PM PDT 24
Finished Jul 07 05:03:00 PM PDT 24
Peak memory 211252 kb
Host smart-63440bfc-8bba-485f-8a99-ad4bb22dc6bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898567952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3898567952
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1348411096
Short name T299
Test name
Test status
Simulation time 11839780440 ps
CPU time 148.42 seconds
Started Jul 07 05:02:49 PM PDT 24
Finished Jul 07 05:05:17 PM PDT 24
Peak memory 237796 kb
Host smart-c8291221-d1f2-40d8-936c-f94bd155a511
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348411096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1348411096
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.776288402
Short name T262
Test name
Test status
Simulation time 5455931826 ps
CPU time 18.41 seconds
Started Jul 07 05:02:48 PM PDT 24
Finished Jul 07 05:03:06 PM PDT 24
Peak memory 212120 kb
Host smart-4ef88d24-7cf7-407f-9006-0fc60f899fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776288402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.776288402
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1015631307
Short name T146
Test name
Test status
Simulation time 1826678550 ps
CPU time 14.59 seconds
Started Jul 07 05:02:49 PM PDT 24
Finished Jul 07 05:03:04 PM PDT 24
Peak memory 211332 kb
Host smart-8ee31e5d-4a58-4ce1-aad2-8db069e2fdb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015631307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1015631307
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2530097857
Short name T322
Test name
Test status
Simulation time 3086695801 ps
CPU time 18.29 seconds
Started Jul 07 05:02:44 PM PDT 24
Finished Jul 07 05:03:02 PM PDT 24
Peak memory 213488 kb
Host smart-a73c1e17-1736-45f9-8bb0-8ed99f74ba4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530097857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2530097857
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3885933545
Short name T248
Test name
Test status
Simulation time 4210237613 ps
CPU time 47.43 seconds
Started Jul 07 05:02:49 PM PDT 24
Finished Jul 07 05:03:37 PM PDT 24
Peak memory 216868 kb
Host smart-517be789-e20e-4aa9-857c-e347313bc5db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885933545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3885933545
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1850734334
Short name T47
Test name
Test status
Simulation time 24586127682 ps
CPU time 1035.4 seconds
Started Jul 07 05:02:47 PM PDT 24
Finished Jul 07 05:20:03 PM PDT 24
Peak memory 230704 kb
Host smart-e2e02aba-943e-48c4-9d75-6de7b1e1fd17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850734334 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1850734334
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1159521973
Short name T167
Test name
Test status
Simulation time 7831529541 ps
CPU time 15.93 seconds
Started Jul 07 05:02:52 PM PDT 24
Finished Jul 07 05:03:09 PM PDT 24
Peak memory 211300 kb
Host smart-df421c9b-008a-4dbe-b177-e53c62df84eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159521973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1159521973
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.487044817
Short name T338
Test name
Test status
Simulation time 56754672261 ps
CPU time 229.58 seconds
Started Jul 07 05:02:52 PM PDT 24
Finished Jul 07 05:06:42 PM PDT 24
Peak memory 224628 kb
Host smart-a5176f98-23e7-4e91-87fe-9b74bcc0a600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487044817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.487044817
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3922378393
Short name T211
Test name
Test status
Simulation time 2607932482 ps
CPU time 24.8 seconds
Started Jul 07 05:02:53 PM PDT 24
Finished Jul 07 05:03:18 PM PDT 24
Peak memory 211924 kb
Host smart-6217bc51-b2ce-4f3f-b0a6-ecbb9ae45d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922378393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3922378393
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1626520938
Short name T205
Test name
Test status
Simulation time 937560663 ps
CPU time 8.78 seconds
Started Jul 07 05:02:54 PM PDT 24
Finished Jul 07 05:03:03 PM PDT 24
Peak memory 211288 kb
Host smart-92314add-1fd7-481c-83d4-666a57bd1f34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626520938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1626520938
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1091760512
Short name T195
Test name
Test status
Simulation time 811024974 ps
CPU time 10.1 seconds
Started Jul 07 05:02:47 PM PDT 24
Finished Jul 07 05:02:57 PM PDT 24
Peak memory 213404 kb
Host smart-cc4113c3-7fc1-495e-ad90-693afdc36e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091760512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1091760512
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1206091954
Short name T163
Test name
Test status
Simulation time 1407760663 ps
CPU time 22.24 seconds
Started Jul 07 05:02:52 PM PDT 24
Finished Jul 07 05:03:15 PM PDT 24
Peak memory 214672 kb
Host smart-b03dace6-a50f-4ce8-86a4-1762639b0930
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206091954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1206091954
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.146499153
Short name T200
Test name
Test status
Simulation time 346599906 ps
CPU time 4.26 seconds
Started Jul 07 05:03:00 PM PDT 24
Finished Jul 07 05:03:04 PM PDT 24
Peak memory 211244 kb
Host smart-edce704a-6dbe-4498-bd37-e02469975c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146499153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.146499153
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4071181427
Short name T35
Test name
Test status
Simulation time 36602473729 ps
CPU time 387.03 seconds
Started Jul 07 05:03:02 PM PDT 24
Finished Jul 07 05:09:29 PM PDT 24
Peak memory 233684 kb
Host smart-9c47bb9e-5b77-4068-8d44-bb370cad9524
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071181427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4071181427
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2687169117
Short name T350
Test name
Test status
Simulation time 2406420552 ps
CPU time 24.16 seconds
Started Jul 07 05:03:02 PM PDT 24
Finished Jul 07 05:03:27 PM PDT 24
Peak memory 211404 kb
Host smart-afb68c76-ffcc-4f50-a3d9-2dc407a4321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687169117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2687169117
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.544907075
Short name T273
Test name
Test status
Simulation time 94267045 ps
CPU time 5.5 seconds
Started Jul 07 05:02:57 PM PDT 24
Finished Jul 07 05:03:02 PM PDT 24
Peak memory 211300 kb
Host smart-e3c5ee5e-322a-404e-b77b-64e7a4ba6326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544907075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.544907075
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3290986498
Short name T313
Test name
Test status
Simulation time 909491102 ps
CPU time 10.23 seconds
Started Jul 07 05:02:57 PM PDT 24
Finished Jul 07 05:03:08 PM PDT 24
Peak memory 213440 kb
Host smart-2e8efc2f-11e8-4ee1-817a-5ad9c1ecaf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290986498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3290986498
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1704019220
Short name T8
Test name
Test status
Simulation time 154301441 ps
CPU time 7.06 seconds
Started Jul 07 05:02:57 PM PDT 24
Finished Jul 07 05:03:05 PM PDT 24
Peak memory 211208 kb
Host smart-0a00b6ab-1b4a-4414-baea-f418fde84338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704019220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1704019220
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.416530623
Short name T324
Test name
Test status
Simulation time 28969455756 ps
CPU time 763.82 seconds
Started Jul 07 05:03:01 PM PDT 24
Finished Jul 07 05:15:46 PM PDT 24
Peak memory 235796 kb
Host smart-e7eedb02-778b-4551-a452-b7e4564fffdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416530623 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.416530623
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3938019826
Short name T337
Test name
Test status
Simulation time 1105020782 ps
CPU time 11.12 seconds
Started Jul 07 05:03:06 PM PDT 24
Finished Jul 07 05:03:17 PM PDT 24
Peak memory 211288 kb
Host smart-5f5511f1-cd76-4a5e-9f33-44b47d036e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938019826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3938019826
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1539013294
Short name T316
Test name
Test status
Simulation time 8842372166 ps
CPU time 102.23 seconds
Started Jul 07 05:03:02 PM PDT 24
Finished Jul 07 05:04:44 PM PDT 24
Peak memory 224692 kb
Host smart-a8694cf8-4e66-41cb-ac63-082703643690
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539013294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1539013294
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2240475622
Short name T323
Test name
Test status
Simulation time 991875629 ps
CPU time 11.33 seconds
Started Jul 07 05:03:06 PM PDT 24
Finished Jul 07 05:03:17 PM PDT 24
Peak memory 211876 kb
Host smart-163416f2-5dd7-4801-8bff-df3144af3699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240475622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2240475622
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2271485234
Short name T188
Test name
Test status
Simulation time 435155988 ps
CPU time 8.65 seconds
Started Jul 07 05:03:02 PM PDT 24
Finished Jul 07 05:03:11 PM PDT 24
Peak memory 211332 kb
Host smart-e86d9653-8dac-4d69-a546-a02f5cc44b1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2271485234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2271485234
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2804333830
Short name T279
Test name
Test status
Simulation time 11838479902 ps
CPU time 25.57 seconds
Started Jul 07 05:03:01 PM PDT 24
Finished Jul 07 05:03:27 PM PDT 24
Peak memory 214420 kb
Host smart-a3a347cb-dcec-461b-8571-5f1ef169406c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804333830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2804333830
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3161423110
Short name T249
Test name
Test status
Simulation time 5999827164 ps
CPU time 38.13 seconds
Started Jul 07 05:03:06 PM PDT 24
Finished Jul 07 05:03:44 PM PDT 24
Peak memory 214968 kb
Host smart-3e757f25-a063-4228-a4a2-9e0112b94559
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161423110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3161423110
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3851854399
Short name T60
Test name
Test status
Simulation time 3884398357 ps
CPU time 10.21 seconds
Started Jul 07 05:03:06 PM PDT 24
Finished Jul 07 05:03:17 PM PDT 24
Peak memory 211328 kb
Host smart-8f08ba6d-1b72-492d-9ca9-1205edfaddbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851854399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3851854399
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.419126080
Short name T243
Test name
Test status
Simulation time 45921457393 ps
CPU time 390.03 seconds
Started Jul 07 05:03:07 PM PDT 24
Finished Jul 07 05:09:37 PM PDT 24
Peak memory 234672 kb
Host smart-c3030379-2cdf-4a86-a44b-82ea9b8f8505
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419126080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.419126080
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3966857709
Short name T229
Test name
Test status
Simulation time 1275938348 ps
CPU time 17.19 seconds
Started Jul 07 05:03:06 PM PDT 24
Finished Jul 07 05:03:23 PM PDT 24
Peak memory 212292 kb
Host smart-bc3831b7-e678-4092-a5cb-49b4c1c70391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966857709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3966857709
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.633220189
Short name T336
Test name
Test status
Simulation time 2434560822 ps
CPU time 8.16 seconds
Started Jul 07 05:03:04 PM PDT 24
Finished Jul 07 05:03:12 PM PDT 24
Peak memory 211396 kb
Host smart-f92c2d7a-2780-4eb2-a967-a5fb6297f1b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633220189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.633220189
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3420273231
Short name T252
Test name
Test status
Simulation time 2088434538 ps
CPU time 19.32 seconds
Started Jul 07 05:03:05 PM PDT 24
Finished Jul 07 05:03:25 PM PDT 24
Peak memory 213884 kb
Host smart-7067e025-8652-467e-8a97-4e33f1b14dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420273231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3420273231
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1431022231
Short name T282
Test name
Test status
Simulation time 2052609058 ps
CPU time 24.68 seconds
Started Jul 07 05:03:06 PM PDT 24
Finished Jul 07 05:03:31 PM PDT 24
Peak memory 214008 kb
Host smart-9247ae16-e61f-4b32-91d1-803067941651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431022231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1431022231
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.632493474
Short name T365
Test name
Test status
Simulation time 1663063684 ps
CPU time 13.44 seconds
Started Jul 07 05:03:12 PM PDT 24
Finished Jul 07 05:03:26 PM PDT 24
Peak memory 211212 kb
Host smart-f174763e-d023-490f-861d-642b45ad3020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632493474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.632493474
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1244329312
Short name T33
Test name
Test status
Simulation time 36198357120 ps
CPU time 222.67 seconds
Started Jul 07 05:03:11 PM PDT 24
Finished Jul 07 05:06:54 PM PDT 24
Peak memory 212100 kb
Host smart-2a3314b8-58a3-4afb-8327-3a021c5f6e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244329312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1244329312
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4292613470
Short name T339
Test name
Test status
Simulation time 11268900616 ps
CPU time 25.97 seconds
Started Jul 07 05:03:10 PM PDT 24
Finished Jul 07 05:03:36 PM PDT 24
Peak memory 212440 kb
Host smart-25c7cf49-ee82-4321-901a-da901cfb882b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292613470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4292613470
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1759612113
Short name T178
Test name
Test status
Simulation time 12642465534 ps
CPU time 31.86 seconds
Started Jul 07 05:03:12 PM PDT 24
Finished Jul 07 05:03:44 PM PDT 24
Peak memory 214464 kb
Host smart-7a075ad0-2f78-4725-ba72-556df578cdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759612113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1759612113
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3113406843
Short name T176
Test name
Test status
Simulation time 7803060330 ps
CPU time 26.84 seconds
Started Jul 07 05:03:11 PM PDT 24
Finished Jul 07 05:03:38 PM PDT 24
Peak memory 214360 kb
Host smart-2a4a5072-a4f0-4dc9-a5e0-2950b086c591
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113406843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3113406843
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3405675570
Short name T45
Test name
Test status
Simulation time 101842332498 ps
CPU time 987.39 seconds
Started Jul 07 05:03:11 PM PDT 24
Finished Jul 07 05:19:39 PM PDT 24
Peak memory 230864 kb
Host smart-d91a0c4a-ebd3-47f9-8772-47b86a24c32d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405675570 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3405675570
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3780605746
Short name T268
Test name
Test status
Simulation time 168711297 ps
CPU time 5.59 seconds
Started Jul 07 05:03:16 PM PDT 24
Finished Jul 07 05:03:21 PM PDT 24
Peak memory 211320 kb
Host smart-25f5c5e0-960b-4588-8c1a-41fdd79ccc95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780605746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3780605746
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3114935419
Short name T246
Test name
Test status
Simulation time 109580908920 ps
CPU time 527.5 seconds
Started Jul 07 05:03:21 PM PDT 24
Finished Jul 07 05:12:09 PM PDT 24
Peak memory 227820 kb
Host smart-5a596df6-1d9f-4de5-b026-042bb7a95506
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114935419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3114935419
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1363330604
Short name T266
Test name
Test status
Simulation time 3870800517 ps
CPU time 31.97 seconds
Started Jul 07 05:03:16 PM PDT 24
Finished Jul 07 05:03:48 PM PDT 24
Peak memory 212044 kb
Host smart-91c1a5ad-a18e-445f-ba38-cd88c4cb1a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363330604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1363330604
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2521252483
Short name T51
Test name
Test status
Simulation time 1397986256 ps
CPU time 9.74 seconds
Started Jul 07 05:03:16 PM PDT 24
Finished Jul 07 05:03:26 PM PDT 24
Peak memory 211332 kb
Host smart-94b7cf03-e154-4333-b495-7f86ba341971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521252483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2521252483
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1317247846
Short name T177
Test name
Test status
Simulation time 16027262094 ps
CPU time 35.65 seconds
Started Jul 07 05:03:16 PM PDT 24
Finished Jul 07 05:03:52 PM PDT 24
Peak memory 214104 kb
Host smart-e68bb904-9698-4bb1-951a-a9db28c683c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317247846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1317247846
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1039542293
Short name T10
Test name
Test status
Simulation time 1822990883 ps
CPU time 25.29 seconds
Started Jul 07 05:03:17 PM PDT 24
Finished Jul 07 05:03:42 PM PDT 24
Peak memory 213272 kb
Host smart-7ca67803-f48b-4f28-875d-2a5d6eb4e3cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039542293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1039542293
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.756828298
Short name T48
Test name
Test status
Simulation time 49889535927 ps
CPU time 974.44 seconds
Started Jul 07 05:03:20 PM PDT 24
Finished Jul 07 05:19:35 PM PDT 24
Peak memory 235232 kb
Host smart-f296814e-347c-4263-bda9-748c70cba641
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756828298 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.756828298
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3318609945
Short name T351
Test name
Test status
Simulation time 3263844552 ps
CPU time 9.87 seconds
Started Jul 07 05:01:52 PM PDT 24
Finished Jul 07 05:02:03 PM PDT 24
Peak memory 211356 kb
Host smart-57169edb-f25b-4cf2-8a3f-314b11a005bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318609945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3318609945
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2437420382
Short name T254
Test name
Test status
Simulation time 4619742706 ps
CPU time 87.33 seconds
Started Jul 07 05:01:51 PM PDT 24
Finished Jul 07 05:03:19 PM PDT 24
Peak memory 237856 kb
Host smart-987bf952-a98e-4e60-90a0-e767939a4932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437420382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2437420382
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.721514715
Short name T307
Test name
Test status
Simulation time 321420491 ps
CPU time 9.69 seconds
Started Jul 07 05:01:52 PM PDT 24
Finished Jul 07 05:02:02 PM PDT 24
Peak memory 211808 kb
Host smart-b205fa15-9b64-4340-b90b-c58641982993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721514715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.721514715
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.154027556
Short name T296
Test name
Test status
Simulation time 372209906 ps
CPU time 5.73 seconds
Started Jul 07 05:01:52 PM PDT 24
Finished Jul 07 05:01:58 PM PDT 24
Peak memory 211332 kb
Host smart-56189e88-179b-4d7f-8ec4-4778a230647b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154027556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.154027556
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2847092549
Short name T30
Test name
Test status
Simulation time 1120289768 ps
CPU time 103.18 seconds
Started Jul 07 05:01:51 PM PDT 24
Finished Jul 07 05:03:35 PM PDT 24
Peak memory 236860 kb
Host smart-777f6eb0-ac13-460f-a310-e056418eff1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847092549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2847092549
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2802740576
Short name T185
Test name
Test status
Simulation time 22591396550 ps
CPU time 40.77 seconds
Started Jul 07 05:01:48 PM PDT 24
Finished Jul 07 05:02:29 PM PDT 24
Peak memory 214300 kb
Host smart-3b7a22f1-9a7e-4c5e-8b19-f71a8803653f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802740576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2802740576
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3668637358
Short name T135
Test name
Test status
Simulation time 1797673441 ps
CPU time 18.55 seconds
Started Jul 07 05:01:46 PM PDT 24
Finished Jul 07 05:02:05 PM PDT 24
Peak memory 213792 kb
Host smart-8d88a8b8-1374-4bc3-afce-8a9e79d0ab04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668637358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3668637358
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4156058350
Short name T320
Test name
Test status
Simulation time 1332365645 ps
CPU time 7.34 seconds
Started Jul 07 05:03:21 PM PDT 24
Finished Jul 07 05:03:29 PM PDT 24
Peak memory 211312 kb
Host smart-28c819c1-dc49-411c-a03a-f8ee594b8270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156058350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4156058350
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3297014725
Short name T153
Test name
Test status
Simulation time 5158776134 ps
CPU time 103.63 seconds
Started Jul 07 05:03:21 PM PDT 24
Finished Jul 07 05:05:05 PM PDT 24
Peak memory 213568 kb
Host smart-60d90c8d-5494-431b-befa-ac9fe368ef81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297014725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3297014725
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1289947688
Short name T28
Test name
Test status
Simulation time 1637642798 ps
CPU time 19.11 seconds
Started Jul 07 05:03:19 PM PDT 24
Finished Jul 07 05:03:38 PM PDT 24
Peak memory 211848 kb
Host smart-2568c028-c0f5-406e-a653-af6dd64df96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289947688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1289947688
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3595962083
Short name T160
Test name
Test status
Simulation time 20203921612 ps
CPU time 15.65 seconds
Started Jul 07 05:03:16 PM PDT 24
Finished Jul 07 05:03:32 PM PDT 24
Peak memory 211340 kb
Host smart-52cbb5ef-2aae-447f-a5c1-acdfecf176bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595962083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3595962083
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.55696144
Short name T364
Test name
Test status
Simulation time 13666451177 ps
CPU time 30.65 seconds
Started Jul 07 05:03:20 PM PDT 24
Finished Jul 07 05:03:51 PM PDT 24
Peak memory 214204 kb
Host smart-351330dc-fc6e-4234-ae39-30fc57819f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55696144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.55696144
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.777713781
Short name T234
Test name
Test status
Simulation time 441823081 ps
CPU time 10.61 seconds
Started Jul 07 05:03:20 PM PDT 24
Finished Jul 07 05:03:31 PM PDT 24
Peak memory 214356 kb
Host smart-77614223-3d04-4cba-88a9-674e81873b23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777713781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.777713781
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3900952314
Short name T255
Test name
Test status
Simulation time 6316641240 ps
CPU time 13.87 seconds
Started Jul 07 05:03:20 PM PDT 24
Finished Jul 07 05:03:34 PM PDT 24
Peak memory 211360 kb
Host smart-a69d61b7-f793-4da2-9378-36b99780a886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900952314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3900952314
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3149030296
Short name T41
Test name
Test status
Simulation time 213844330314 ps
CPU time 502 seconds
Started Jul 07 05:03:20 PM PDT 24
Finished Jul 07 05:11:43 PM PDT 24
Peak memory 212588 kb
Host smart-1e27880c-62a9-41ff-bd03-f2793d476107
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149030296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3149030296
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1907246288
Short name T232
Test name
Test status
Simulation time 179332432 ps
CPU time 9.38 seconds
Started Jul 07 05:03:21 PM PDT 24
Finished Jul 07 05:03:31 PM PDT 24
Peak memory 211288 kb
Host smart-47ff59e3-36a0-4548-bdcc-c95ae0bc8e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907246288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1907246288
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3634826195
Short name T132
Test name
Test status
Simulation time 7549808558 ps
CPU time 15.47 seconds
Started Jul 07 05:03:21 PM PDT 24
Finished Jul 07 05:03:37 PM PDT 24
Peak memory 211408 kb
Host smart-02dac477-686a-4d20-98a2-5ed9440c4610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3634826195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3634826195
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2724958020
Short name T325
Test name
Test status
Simulation time 361849786 ps
CPU time 10.23 seconds
Started Jul 07 05:03:20 PM PDT 24
Finished Jul 07 05:03:31 PM PDT 24
Peak memory 213416 kb
Host smart-b1da3fe6-cec9-4ab0-a9fe-823d5afd74c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724958020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2724958020
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.382519224
Short name T204
Test name
Test status
Simulation time 225248683 ps
CPU time 12.06 seconds
Started Jul 07 05:03:21 PM PDT 24
Finished Jul 07 05:03:34 PM PDT 24
Peak memory 211128 kb
Host smart-5fe6d043-c47c-410e-abd5-4139a41be6be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382519224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.382519224
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3821953501
Short name T202
Test name
Test status
Simulation time 2066060475 ps
CPU time 6.83 seconds
Started Jul 07 05:03:25 PM PDT 24
Finished Jul 07 05:03:33 PM PDT 24
Peak memory 211236 kb
Host smart-9caf9291-59e8-454b-8c42-b5bd255dbd17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821953501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3821953501
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2460012897
Short name T326
Test name
Test status
Simulation time 43243169783 ps
CPU time 294.41 seconds
Started Jul 07 05:03:25 PM PDT 24
Finished Jul 07 05:08:20 PM PDT 24
Peak memory 237696 kb
Host smart-30318c38-0c9b-4ba8-977a-353602f3f1c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460012897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2460012897
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4052029361
Short name T276
Test name
Test status
Simulation time 2034617635 ps
CPU time 15.03 seconds
Started Jul 07 05:03:25 PM PDT 24
Finished Jul 07 05:03:41 PM PDT 24
Peak memory 211260 kb
Host smart-35909797-d252-4268-8010-4dee3cea4d6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4052029361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4052029361
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.797064634
Short name T274
Test name
Test status
Simulation time 1295545447 ps
CPU time 14.83 seconds
Started Jul 07 05:03:21 PM PDT 24
Finished Jul 07 05:03:36 PM PDT 24
Peak memory 213472 kb
Host smart-d1c1f263-2057-4e78-9743-7d9945e50104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797064634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.797064634
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3022290457
Short name T346
Test name
Test status
Simulation time 1248613948 ps
CPU time 16.52 seconds
Started Jul 07 05:03:22 PM PDT 24
Finished Jul 07 05:03:39 PM PDT 24
Peak memory 214904 kb
Host smart-0e4321d9-72a0-4dc5-aa53-6cda40c2a62e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022290457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3022290457
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3761710457
Short name T335
Test name
Test status
Simulation time 26141716853 ps
CPU time 921.11 seconds
Started Jul 07 05:03:26 PM PDT 24
Finished Jul 07 05:18:47 PM PDT 24
Peak memory 229448 kb
Host smart-7a548570-1766-4d61-9318-b706370aa5bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761710457 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3761710457
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2368597068
Short name T321
Test name
Test status
Simulation time 1366401544 ps
CPU time 12.34 seconds
Started Jul 07 05:03:30 PM PDT 24
Finished Jul 07 05:03:43 PM PDT 24
Peak memory 211248 kb
Host smart-c5db7c69-ef7f-4f4b-869e-68dbbaf2c5ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368597068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2368597068
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1719124744
Short name T40
Test name
Test status
Simulation time 153963852957 ps
CPU time 386.02 seconds
Started Jul 07 05:03:26 PM PDT 24
Finished Jul 07 05:09:52 PM PDT 24
Peak memory 213564 kb
Host smart-2278f8b5-9213-4bdc-b428-c2dc961cab93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719124744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1719124744
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1868139468
Short name T168
Test name
Test status
Simulation time 3828765174 ps
CPU time 32.67 seconds
Started Jul 07 05:03:25 PM PDT 24
Finished Jul 07 05:03:58 PM PDT 24
Peak memory 211808 kb
Host smart-a6a3804a-f052-4980-985f-e7df20d153ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868139468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1868139468
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1125134594
Short name T303
Test name
Test status
Simulation time 2969031060 ps
CPU time 13.52 seconds
Started Jul 07 05:03:24 PM PDT 24
Finished Jul 07 05:03:38 PM PDT 24
Peak memory 211356 kb
Host smart-85235445-c991-40c1-8032-1546c43e1709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125134594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1125134594
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2041266502
Short name T155
Test name
Test status
Simulation time 375699690 ps
CPU time 10.06 seconds
Started Jul 07 05:03:25 PM PDT 24
Finished Jul 07 05:03:36 PM PDT 24
Peak memory 213104 kb
Host smart-f1ac53aa-ed37-453d-8f8e-1efeca437f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041266502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2041266502
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.329034809
Short name T114
Test name
Test status
Simulation time 21430090225 ps
CPU time 87.09 seconds
Started Jul 07 05:03:25 PM PDT 24
Finished Jul 07 05:04:53 PM PDT 24
Peak memory 217992 kb
Host smart-d0e945f7-8ba8-49da-8403-3c024b120194
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329034809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.329034809
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1468458264
Short name T241
Test name
Test status
Simulation time 14077343209 ps
CPU time 14.07 seconds
Started Jul 07 05:03:30 PM PDT 24
Finished Jul 07 05:03:44 PM PDT 24
Peak memory 211312 kb
Host smart-885d70d1-0b8b-4d2a-a210-15e9d03a63f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468458264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1468458264
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.704098242
Short name T196
Test name
Test status
Simulation time 102585009575 ps
CPU time 319.61 seconds
Started Jul 07 05:03:30 PM PDT 24
Finished Jul 07 05:08:50 PM PDT 24
Peak memory 225960 kb
Host smart-b7ff2ccc-b4f3-48ee-9e4a-b156b49507e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704098242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.704098242
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3602406042
Short name T295
Test name
Test status
Simulation time 4291578333 ps
CPU time 35.28 seconds
Started Jul 07 05:03:30 PM PDT 24
Finished Jul 07 05:04:05 PM PDT 24
Peak memory 211960 kb
Host smart-4b30e667-c731-4e2d-b649-390993c6d153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602406042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3602406042
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4086114452
Short name T242
Test name
Test status
Simulation time 599433254 ps
CPU time 8.96 seconds
Started Jul 07 05:03:30 PM PDT 24
Finished Jul 07 05:03:39 PM PDT 24
Peak memory 211300 kb
Host smart-f9a6aa39-a90e-4073-8b0a-1a293f4dd56a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086114452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.4086114452
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4023330380
Short name T71
Test name
Test status
Simulation time 2810892485 ps
CPU time 22.75 seconds
Started Jul 07 05:03:30 PM PDT 24
Finished Jul 07 05:03:53 PM PDT 24
Peak memory 213692 kb
Host smart-5831282e-6fab-4a4c-b838-86f8fb258e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023330380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4023330380
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3196278250
Short name T16
Test name
Test status
Simulation time 5548884090 ps
CPU time 60.63 seconds
Started Jul 07 05:03:31 PM PDT 24
Finished Jul 07 05:04:32 PM PDT 24
Peak memory 216924 kb
Host smart-0428ba93-47f2-4f03-84c4-eae4d98d8e71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196278250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3196278250
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1938382081
Short name T359
Test name
Test status
Simulation time 431700052 ps
CPU time 5.75 seconds
Started Jul 07 05:03:34 PM PDT 24
Finished Jul 07 05:03:40 PM PDT 24
Peak memory 211272 kb
Host smart-1cd2558c-3e79-48f6-9f37-03a6f572f2c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938382081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1938382081
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3920261478
Short name T156
Test name
Test status
Simulation time 270173231068 ps
CPU time 198.21 seconds
Started Jul 07 05:03:35 PM PDT 24
Finished Jul 07 05:06:53 PM PDT 24
Peak memory 237156 kb
Host smart-f1bf7717-476c-4db6-9666-1d00407a5ab1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920261478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3920261478
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1749414994
Short name T327
Test name
Test status
Simulation time 26927544877 ps
CPU time 26.71 seconds
Started Jul 07 05:03:34 PM PDT 24
Finished Jul 07 05:04:01 PM PDT 24
Peak memory 212220 kb
Host smart-ea60fc96-be2f-4f04-b349-9debd9651962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749414994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1749414994
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3240350689
Short name T366
Test name
Test status
Simulation time 1243833490 ps
CPU time 7.59 seconds
Started Jul 07 05:03:36 PM PDT 24
Finished Jul 07 05:03:44 PM PDT 24
Peak memory 211260 kb
Host smart-782a8bf9-808f-46b4-857b-adf5df1387b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240350689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3240350689
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1694308408
Short name T164
Test name
Test status
Simulation time 6915379570 ps
CPU time 36.11 seconds
Started Jul 07 05:03:35 PM PDT 24
Finished Jul 07 05:04:11 PM PDT 24
Peak memory 213636 kb
Host smart-79e14a66-5570-4236-977b-eb9504faeb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694308408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1694308408
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1673515804
Short name T131
Test name
Test status
Simulation time 32255120540 ps
CPU time 80.37 seconds
Started Jul 07 05:03:36 PM PDT 24
Finished Jul 07 05:04:57 PM PDT 24
Peak memory 219280 kb
Host smart-dc2a85bf-a7bf-48f6-8858-6d0966d01ae0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673515804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1673515804
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1073494886
Short name T244
Test name
Test status
Simulation time 28087054678 ps
CPU time 234.9 seconds
Started Jul 07 05:03:40 PM PDT 24
Finished Jul 07 05:07:35 PM PDT 24
Peak memory 236968 kb
Host smart-063d6e02-6c25-4ba0-9d49-5e05e659b9d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073494886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1073494886
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.148992811
Short name T220
Test name
Test status
Simulation time 3263970933 ps
CPU time 19.46 seconds
Started Jul 07 05:03:39 PM PDT 24
Finished Jul 07 05:03:58 PM PDT 24
Peak memory 211984 kb
Host smart-05cfbd78-f377-4dfa-ba40-df68548b007f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148992811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.148992811
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2771306303
Short name T122
Test name
Test status
Simulation time 1332785038 ps
CPU time 12.96 seconds
Started Jul 07 05:03:40 PM PDT 24
Finished Jul 07 05:03:53 PM PDT 24
Peak memory 211296 kb
Host smart-9371a215-c373-47be-b58e-73409e0956ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771306303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2771306303
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.702987656
Short name T225
Test name
Test status
Simulation time 2934677950 ps
CPU time 30.03 seconds
Started Jul 07 05:03:35 PM PDT 24
Finished Jul 07 05:04:05 PM PDT 24
Peak memory 213388 kb
Host smart-5710200c-874e-4185-8d93-ac18a8bc7588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702987656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.702987656
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2352921633
Short name T222
Test name
Test status
Simulation time 5035790076 ps
CPU time 35.98 seconds
Started Jul 07 05:03:39 PM PDT 24
Finished Jul 07 05:04:15 PM PDT 24
Peak memory 218008 kb
Host smart-c8b1f39d-53a4-44b0-a646-49da1633ec11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352921633 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2352921633
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.75111459
Short name T363
Test name
Test status
Simulation time 462480589 ps
CPU time 4.2 seconds
Started Jul 07 05:03:45 PM PDT 24
Finished Jul 07 05:03:50 PM PDT 24
Peak memory 211240 kb
Host smart-d81b5b67-7aa2-4e3a-828e-8871172ba029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75111459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.75111459
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3592504134
Short name T186
Test name
Test status
Simulation time 67492766838 ps
CPU time 241.62 seconds
Started Jul 07 05:03:38 PM PDT 24
Finished Jul 07 05:07:40 PM PDT 24
Peak memory 237740 kb
Host smart-b3cf6940-9e58-4ab0-9f4e-dfc638f5e295
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592504134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3592504134
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2399971258
Short name T253
Test name
Test status
Simulation time 4748712888 ps
CPU time 25.18 seconds
Started Jul 07 05:03:39 PM PDT 24
Finished Jul 07 05:04:04 PM PDT 24
Peak memory 212248 kb
Host smart-93f791e1-2bf0-4e04-80d0-29e8cc727573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399971258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2399971258
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1648430343
Short name T128
Test name
Test status
Simulation time 95715912 ps
CPU time 5.45 seconds
Started Jul 07 05:03:38 PM PDT 24
Finished Jul 07 05:03:44 PM PDT 24
Peak memory 211280 kb
Host smart-76f9ec45-efe1-49ee-8d91-c4a4613a4b69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1648430343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1648430343
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2412000075
Short name T224
Test name
Test status
Simulation time 3480936606 ps
CPU time 17.07 seconds
Started Jul 07 05:03:41 PM PDT 24
Finished Jul 07 05:03:58 PM PDT 24
Peak memory 214108 kb
Host smart-11517a19-55de-4b64-92bc-650abcaf137c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412000075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2412000075
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2496988655
Short name T175
Test name
Test status
Simulation time 17429968840 ps
CPU time 39.55 seconds
Started Jul 07 05:03:38 PM PDT 24
Finished Jul 07 05:04:17 PM PDT 24
Peak memory 214720 kb
Host smart-9dbed4ea-bafe-4a66-a78a-0e005830a370
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496988655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2496988655
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.329095136
Short name T356
Test name
Test status
Simulation time 7625523880 ps
CPU time 15.17 seconds
Started Jul 07 05:03:45 PM PDT 24
Finished Jul 07 05:04:01 PM PDT 24
Peak memory 211352 kb
Host smart-0d6749c5-375d-4d7b-baca-51a169e6f981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329095136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.329095136
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2431494291
Short name T123
Test name
Test status
Simulation time 9167092445 ps
CPU time 23.99 seconds
Started Jul 07 05:03:45 PM PDT 24
Finished Jul 07 05:04:09 PM PDT 24
Peak memory 211348 kb
Host smart-a0f1ef77-8d56-4ebc-9521-7886af3d5dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431494291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2431494291
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.967212377
Short name T353
Test name
Test status
Simulation time 21096491509 ps
CPU time 13.78 seconds
Started Jul 07 05:03:45 PM PDT 24
Finished Jul 07 05:03:59 PM PDT 24
Peak memory 211352 kb
Host smart-4392ff58-89ed-4dc3-8019-c84fb68d1080
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967212377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.967212377
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2944847067
Short name T11
Test name
Test status
Simulation time 38446216070 ps
CPU time 43.12 seconds
Started Jul 07 05:03:44 PM PDT 24
Finished Jul 07 05:04:27 PM PDT 24
Peak memory 214284 kb
Host smart-6cf08c98-6447-4951-b556-d69cc5d57c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944847067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2944847067
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2546969370
Short name T159
Test name
Test status
Simulation time 646755595 ps
CPU time 18.13 seconds
Started Jul 07 05:03:45 PM PDT 24
Finished Jul 07 05:04:03 PM PDT 24
Peak memory 213444 kb
Host smart-c8726c63-f758-4292-ac56-730c0a7e6381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546969370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2546969370
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3261647288
Short name T349
Test name
Test status
Simulation time 111505290485 ps
CPU time 1861.07 seconds
Started Jul 07 05:03:44 PM PDT 24
Finished Jul 07 05:34:45 PM PDT 24
Peak memory 239744 kb
Host smart-f9bce19b-c791-4eb5-a855-43c4aa97443f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261647288 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3261647288
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.589288142
Short name T257
Test name
Test status
Simulation time 690613410 ps
CPU time 8.6 seconds
Started Jul 07 05:03:50 PM PDT 24
Finished Jul 07 05:03:58 PM PDT 24
Peak memory 211216 kb
Host smart-b6b519ed-c5d1-4617-bfe2-0ab78432dcf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589288142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.589288142
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3651851000
Short name T275
Test name
Test status
Simulation time 2109978267 ps
CPU time 118 seconds
Started Jul 07 05:03:49 PM PDT 24
Finished Jul 07 05:05:47 PM PDT 24
Peak memory 233580 kb
Host smart-6eef7d15-e2f3-472a-8332-4e354e0bb12c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651851000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3651851000
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2792035521
Short name T191
Test name
Test status
Simulation time 3514767863 ps
CPU time 29.69 seconds
Started Jul 07 05:03:49 PM PDT 24
Finished Jul 07 05:04:19 PM PDT 24
Peak memory 211980 kb
Host smart-2a0c4b5b-62a8-4747-883a-ba21ba9158e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792035521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2792035521
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1754318756
Short name T292
Test name
Test status
Simulation time 4113781277 ps
CPU time 11.35 seconds
Started Jul 07 05:03:48 PM PDT 24
Finished Jul 07 05:04:00 PM PDT 24
Peak memory 211408 kb
Host smart-1858e5f3-bebd-4e5f-ad70-7a6d11d960cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1754318756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1754318756
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2650314568
Short name T239
Test name
Test status
Simulation time 5162382451 ps
CPU time 28.78 seconds
Started Jul 07 05:03:46 PM PDT 24
Finished Jul 07 05:04:15 PM PDT 24
Peak memory 213644 kb
Host smart-05098bcb-bba4-4e2f-ae46-c31faf8f3e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650314568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2650314568
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2801327512
Short name T136
Test name
Test status
Simulation time 12096771326 ps
CPU time 64.41 seconds
Started Jul 07 05:03:45 PM PDT 24
Finished Jul 07 05:04:50 PM PDT 24
Peak memory 217692 kb
Host smart-919be909-de3c-437b-9617-a6967c69bac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801327512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2801327512
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.276816480
Short name T343
Test name
Test status
Simulation time 2226581787 ps
CPU time 7.75 seconds
Started Jul 07 05:02:03 PM PDT 24
Finished Jul 07 05:02:11 PM PDT 24
Peak memory 211268 kb
Host smart-17b0c833-c193-48fb-850c-9681fb1d51a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276816480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.276816480
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2216037087
Short name T20
Test name
Test status
Simulation time 12210567114 ps
CPU time 153.61 seconds
Started Jul 07 05:01:55 PM PDT 24
Finished Jul 07 05:04:29 PM PDT 24
Peak memory 234096 kb
Host smart-e05495f1-aa6c-4cb0-8ffe-af4df894c170
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216037087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2216037087
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3817544471
Short name T152
Test name
Test status
Simulation time 397441027 ps
CPU time 9.52 seconds
Started Jul 07 05:01:55 PM PDT 24
Finished Jul 07 05:02:04 PM PDT 24
Peak memory 211928 kb
Host smart-999d5e6f-e6d3-4975-95b1-c67eefb503c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817544471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3817544471
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2691878043
Short name T265
Test name
Test status
Simulation time 384189442 ps
CPU time 5.46 seconds
Started Jul 07 05:01:56 PM PDT 24
Finished Jul 07 05:02:01 PM PDT 24
Peak memory 211328 kb
Host smart-b807f978-0977-4cb0-b05b-e466e03fba8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691878043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2691878043
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4008572807
Short name T29
Test name
Test status
Simulation time 214465011 ps
CPU time 100.95 seconds
Started Jul 07 05:02:02 PM PDT 24
Finished Jul 07 05:03:43 PM PDT 24
Peak memory 238080 kb
Host smart-a6dc2680-3d80-4dc2-b28e-35ca10a0a551
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008572807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4008572807
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3545862606
Short name T161
Test name
Test status
Simulation time 12746605773 ps
CPU time 33.35 seconds
Started Jul 07 05:01:52 PM PDT 24
Finished Jul 07 05:02:26 PM PDT 24
Peak memory 214432 kb
Host smart-d6b8a91f-8699-4dc8-ab65-5ba9281820f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545862606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3545862606
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.328556219
Short name T2
Test name
Test status
Simulation time 16061740772 ps
CPU time 32.64 seconds
Started Jul 07 05:01:56 PM PDT 24
Finished Jul 07 05:02:29 PM PDT 24
Peak memory 214364 kb
Host smart-10d97e4c-c454-4625-bb11-30ca55ac0c77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328556219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.328556219
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2059807881
Short name T58
Test name
Test status
Simulation time 2088565242 ps
CPU time 16.39 seconds
Started Jul 07 05:03:55 PM PDT 24
Finished Jul 07 05:04:11 PM PDT 24
Peak memory 211308 kb
Host smart-795db114-0b25-44ac-a5af-9740e47a880b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059807881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2059807881
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2848696364
Short name T309
Test name
Test status
Simulation time 4852870074 ps
CPU time 135.13 seconds
Started Jul 07 05:03:56 PM PDT 24
Finished Jul 07 05:06:11 PM PDT 24
Peak memory 238448 kb
Host smart-0481d995-abdb-4077-8fdf-19897c29b8c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848696364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2848696364
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.737231659
Short name T258
Test name
Test status
Simulation time 424472437 ps
CPU time 12.31 seconds
Started Jul 07 05:03:52 PM PDT 24
Finished Jul 07 05:04:05 PM PDT 24
Peak memory 211792 kb
Host smart-d8fb8d8e-fafd-46f2-8c4c-608f2ffa7f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737231659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.737231659
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.593761607
Short name T18
Test name
Test status
Simulation time 194313203 ps
CPU time 5.52 seconds
Started Jul 07 05:03:56 PM PDT 24
Finished Jul 07 05:04:02 PM PDT 24
Peak memory 211232 kb
Host smart-e7650900-0c8a-416f-90a7-6d3a9d3c14f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593761607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.593761607
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.635538676
Short name T283
Test name
Test status
Simulation time 3869152468 ps
CPU time 38.25 seconds
Started Jul 07 05:03:49 PM PDT 24
Finished Jul 07 05:04:27 PM PDT 24
Peak memory 213316 kb
Host smart-675ef0c0-8510-4e6c-9254-ebcf66fe49fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635538676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.635538676
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.454701882
Short name T19
Test name
Test status
Simulation time 10115791832 ps
CPU time 87.82 seconds
Started Jul 07 05:03:53 PM PDT 24
Finished Jul 07 05:05:21 PM PDT 24
Peak memory 215952 kb
Host smart-b76f7fac-08f5-4573-b420-1107a486e849
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454701882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.454701882
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1284223738
Short name T44
Test name
Test status
Simulation time 97541612406 ps
CPU time 4141.16 seconds
Started Jul 07 05:03:56 PM PDT 24
Finished Jul 07 06:12:57 PM PDT 24
Peak memory 255248 kb
Host smart-6e9ba8f5-7e8b-4218-ae0a-9cd02d19738b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284223738 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1284223738
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1775995913
Short name T269
Test name
Test status
Simulation time 362079897 ps
CPU time 4.22 seconds
Started Jul 07 05:03:59 PM PDT 24
Finished Jul 07 05:04:03 PM PDT 24
Peak memory 211256 kb
Host smart-075e382c-eccd-4b75-8189-964af7e84c5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775995913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1775995913
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1922494957
Short name T348
Test name
Test status
Simulation time 12262282284 ps
CPU time 151.34 seconds
Started Jul 07 05:03:58 PM PDT 24
Finished Jul 07 05:06:30 PM PDT 24
Peak memory 228608 kb
Host smart-49cf374d-d9f9-4e70-845b-397201d62eb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922494957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1922494957
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2454469558
Short name T116
Test name
Test status
Simulation time 1540452742 ps
CPU time 19 seconds
Started Jul 07 05:03:58 PM PDT 24
Finished Jul 07 05:04:17 PM PDT 24
Peak memory 211864 kb
Host smart-0fc022dc-d925-490e-94e5-035dfe0a09df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454469558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2454469558
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1418895854
Short name T95
Test name
Test status
Simulation time 1524270776 ps
CPU time 14.55 seconds
Started Jul 07 05:03:57 PM PDT 24
Finished Jul 07 05:04:12 PM PDT 24
Peak memory 211336 kb
Host smart-451f2330-e58e-4ae7-8f1a-693774080307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418895854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1418895854
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3040812536
Short name T235
Test name
Test status
Simulation time 7933388009 ps
CPU time 21.83 seconds
Started Jul 07 05:03:56 PM PDT 24
Finished Jul 07 05:04:19 PM PDT 24
Peak memory 213584 kb
Host smart-84e80407-710b-4676-bf90-512aec7c4d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040812536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3040812536
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1641606613
Short name T218
Test name
Test status
Simulation time 5951989822 ps
CPU time 51.57 seconds
Started Jul 07 05:03:58 PM PDT 24
Finished Jul 07 05:04:50 PM PDT 24
Peak memory 216552 kb
Host smart-1a27e87c-81ec-467e-be9b-eada291b0dd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641606613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1641606613
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2660701275
Short name T260
Test name
Test status
Simulation time 32206687333 ps
CPU time 2723.54 seconds
Started Jul 07 05:03:58 PM PDT 24
Finished Jul 07 05:49:22 PM PDT 24
Peak memory 235796 kb
Host smart-540effd2-987a-41e7-b970-fb79606574ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660701275 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2660701275
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1159641686
Short name T332
Test name
Test status
Simulation time 2198983843 ps
CPU time 16.35 seconds
Started Jul 07 05:04:02 PM PDT 24
Finished Jul 07 05:04:19 PM PDT 24
Peak memory 211668 kb
Host smart-daefdf33-319e-4470-87ef-1ebfeacf6d26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159641686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1159641686
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1740841302
Short name T34
Test name
Test status
Simulation time 12002127042 ps
CPU time 193.46 seconds
Started Jul 07 05:04:09 PM PDT 24
Finished Jul 07 05:07:23 PM PDT 24
Peak memory 228596 kb
Host smart-2368db8f-c2d1-4cce-8ad6-0c5f9a1c8416
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740841302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1740841302
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3338661375
Short name T345
Test name
Test status
Simulation time 48497306467 ps
CPU time 34.95 seconds
Started Jul 07 05:04:01 PM PDT 24
Finished Jul 07 05:04:36 PM PDT 24
Peak memory 212216 kb
Host smart-7ef08999-ea40-446b-99b7-71f908c276e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338661375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3338661375
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.988597462
Short name T150
Test name
Test status
Simulation time 1165825008 ps
CPU time 12.92 seconds
Started Jul 07 05:04:01 PM PDT 24
Finished Jul 07 05:04:15 PM PDT 24
Peak memory 211256 kb
Host smart-1832da22-c08e-414d-b577-75f570910c35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988597462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.988597462
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.539985078
Short name T137
Test name
Test status
Simulation time 374080472 ps
CPU time 10.29 seconds
Started Jul 07 05:04:09 PM PDT 24
Finished Jul 07 05:04:20 PM PDT 24
Peak memory 213536 kb
Host smart-e97cb113-9a56-45ab-9590-0afe177083e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539985078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.539985078
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3895855430
Short name T173
Test name
Test status
Simulation time 3061266215 ps
CPU time 26.86 seconds
Started Jul 07 05:04:04 PM PDT 24
Finished Jul 07 05:04:31 PM PDT 24
Peak memory 216808 kb
Host smart-43e747de-72f3-454c-8f82-1dd9ebb87994
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895855430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3895855430
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2815757658
Short name T328
Test name
Test status
Simulation time 1560073523 ps
CPU time 13.77 seconds
Started Jul 07 05:04:11 PM PDT 24
Finished Jul 07 05:04:26 PM PDT 24
Peak memory 211236 kb
Host smart-88499405-5bcc-40ed-9f02-c2e47bbace6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815757658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2815757658
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1864596505
Short name T247
Test name
Test status
Simulation time 19015141878 ps
CPU time 261.14 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 05:08:33 PM PDT 24
Peak memory 237712 kb
Host smart-e2386625-2b48-4707-ad4f-104eb199b56b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864596505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1864596505
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.699282898
Short name T158
Test name
Test status
Simulation time 18753812265 ps
CPU time 28.93 seconds
Started Jul 07 05:04:16 PM PDT 24
Finished Jul 07 05:04:45 PM PDT 24
Peak memory 212280 kb
Host smart-daa51aca-2021-42f7-97e1-e5539072dc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699282898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.699282898
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1247756149
Short name T130
Test name
Test status
Simulation time 94976395 ps
CPU time 5.69 seconds
Started Jul 07 05:04:13 PM PDT 24
Finished Jul 07 05:04:19 PM PDT 24
Peak memory 211344 kb
Host smart-61e1b70a-bd82-4500-a6aa-ee018f1ae9ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247756149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1247756149
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1609910449
Short name T6
Test name
Test status
Simulation time 3912263487 ps
CPU time 36.43 seconds
Started Jul 07 05:04:09 PM PDT 24
Finished Jul 07 05:04:45 PM PDT 24
Peak memory 213056 kb
Host smart-73b63164-dc98-4119-897e-fe75190fe13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609910449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1609910449
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3842808222
Short name T212
Test name
Test status
Simulation time 762739961 ps
CPU time 11.31 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 05:04:24 PM PDT 24
Peak memory 212236 kb
Host smart-87c65aa7-7049-40ba-9193-c463b5c1b2ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842808222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3842808222
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2171896383
Short name T25
Test name
Test status
Simulation time 15440515353 ps
CPU time 11.6 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 05:04:24 PM PDT 24
Peak memory 211348 kb
Host smart-935fb79e-8e52-4ea6-9a5c-814efb676443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171896383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2171896383
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3535994969
Short name T344
Test name
Test status
Simulation time 72641745883 ps
CPU time 347.72 seconds
Started Jul 07 05:04:11 PM PDT 24
Finished Jul 07 05:09:59 PM PDT 24
Peak memory 228580 kb
Host smart-abd26dd3-ceae-46a5-ad1c-64968f646f77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535994969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3535994969
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1101852155
Short name T311
Test name
Test status
Simulation time 11140238210 ps
CPU time 24.8 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 05:04:38 PM PDT 24
Peak memory 212300 kb
Host smart-a82224c0-286c-419a-91a1-27ef61decf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101852155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1101852155
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1966905780
Short name T145
Test name
Test status
Simulation time 7378741905 ps
CPU time 15.38 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 05:04:28 PM PDT 24
Peak memory 211332 kb
Host smart-f366e546-d569-4e57-8169-70c4915ca3f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966905780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1966905780
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4244421399
Short name T251
Test name
Test status
Simulation time 17112769342 ps
CPU time 38.63 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 05:04:51 PM PDT 24
Peak memory 214268 kb
Host smart-782cf78c-fd85-41dc-bfbc-badc410211e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244421399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4244421399
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1426805548
Short name T271
Test name
Test status
Simulation time 233433579 ps
CPU time 14.47 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 05:04:26 PM PDT 24
Peak memory 213072 kb
Host smart-cb0c747f-aab5-4d89-9387-aa1cd73f1032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426805548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1426805548
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4220622213
Short name T24
Test name
Test status
Simulation time 1356104645 ps
CPU time 12.06 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 05:04:24 PM PDT 24
Peak memory 211324 kb
Host smart-5d5b3bb1-5145-4aba-a85c-a8be5dc35d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220622213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4220622213
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.317388124
Short name T358
Test name
Test status
Simulation time 17954427003 ps
CPU time 160.29 seconds
Started Jul 07 05:04:13 PM PDT 24
Finished Jul 07 05:06:53 PM PDT 24
Peak memory 212568 kb
Host smart-92f9ab40-f27f-4fa6-bcf1-605d3f740e81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317388124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.317388124
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.900945562
Short name T297
Test name
Test status
Simulation time 6414188492 ps
CPU time 30.05 seconds
Started Jul 07 05:04:11 PM PDT 24
Finished Jul 07 05:04:41 PM PDT 24
Peak memory 212432 kb
Host smart-3d2439a2-61fd-45c8-823e-0d9274e5d722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900945562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.900945562
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1942619756
Short name T294
Test name
Test status
Simulation time 458375597 ps
CPU time 7.29 seconds
Started Jul 07 05:04:13 PM PDT 24
Finished Jul 07 05:04:21 PM PDT 24
Peak memory 211356 kb
Host smart-0279b502-d4a0-4140-8b92-225d090ddec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1942619756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1942619756
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2516003731
Short name T83
Test name
Test status
Simulation time 718995588 ps
CPU time 10.11 seconds
Started Jul 07 05:04:10 PM PDT 24
Finished Jul 07 05:04:21 PM PDT 24
Peak memory 213344 kb
Host smart-08280a82-e504-43c7-99ec-433a5fc86f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516003731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2516003731
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3685978153
Short name T227
Test name
Test status
Simulation time 25835629704 ps
CPU time 68.12 seconds
Started Jul 07 05:04:16 PM PDT 24
Finished Jul 07 05:05:24 PM PDT 24
Peak memory 216932 kb
Host smart-d6256f6f-9793-4b3d-acd1-b945b12ca277
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685978153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3685978153
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1400681663
Short name T46
Test name
Test status
Simulation time 755467497158 ps
CPU time 3594.31 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 06:04:07 PM PDT 24
Peak memory 252172 kb
Host smart-5b9c3b9d-d7c4-4b3d-949b-9dae653ce409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400681663 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1400681663
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.283482958
Short name T226
Test name
Test status
Simulation time 6143242229 ps
CPU time 13.34 seconds
Started Jul 07 05:04:13 PM PDT 24
Finished Jul 07 05:04:27 PM PDT 24
Peak memory 211316 kb
Host smart-028bac84-b10c-4382-9d7d-8fcc726703b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283482958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.283482958
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1443550538
Short name T238
Test name
Test status
Simulation time 5470189451 ps
CPU time 76.57 seconds
Started Jul 07 05:04:17 PM PDT 24
Finished Jul 07 05:05:33 PM PDT 24
Peak memory 237832 kb
Host smart-c070b0dd-fecd-46a6-aeb0-e652229a1a14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443550538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1443550538
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3173255540
Short name T263
Test name
Test status
Simulation time 22626624265 ps
CPU time 20.98 seconds
Started Jul 07 05:04:14 PM PDT 24
Finished Jul 07 05:04:36 PM PDT 24
Peak memory 212228 kb
Host smart-7dc88eeb-0231-44e7-ade8-7d07ae25086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173255540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3173255540
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3590972870
Short name T141
Test name
Test status
Simulation time 3851946283 ps
CPU time 16.64 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 05:04:29 PM PDT 24
Peak memory 211432 kb
Host smart-21d3de69-02b8-47d1-af8f-2c91b881b4cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590972870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3590972870
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.777506332
Short name T319
Test name
Test status
Simulation time 4819981335 ps
CPU time 17.3 seconds
Started Jul 07 05:04:12 PM PDT 24
Finished Jul 07 05:04:30 PM PDT 24
Peak memory 213988 kb
Host smart-d233f6ba-ec9e-46b1-8921-0cf5da064c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777506332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.777506332
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2142311355
Short name T172
Test name
Test status
Simulation time 17923204180 ps
CPU time 19.65 seconds
Started Jul 07 05:04:10 PM PDT 24
Finished Jul 07 05:04:30 PM PDT 24
Peak memory 212360 kb
Host smart-8bb0509a-023d-46dc-87d9-ba09d1f2df39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142311355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2142311355
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3281739519
Short name T221
Test name
Test status
Simulation time 12245074687 ps
CPU time 14.58 seconds
Started Jul 07 05:04:21 PM PDT 24
Finished Jul 07 05:04:36 PM PDT 24
Peak memory 211364 kb
Host smart-5e47c8ce-228b-4eda-80b1-9994ca1ab877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281739519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3281739519
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3252877593
Short name T32
Test name
Test status
Simulation time 209436531885 ps
CPU time 482.64 seconds
Started Jul 07 05:04:17 PM PDT 24
Finished Jul 07 05:12:20 PM PDT 24
Peak memory 233724 kb
Host smart-e052591f-8a6f-49d9-b6a1-02e59a50e7e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252877593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3252877593
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1504430865
Short name T304
Test name
Test status
Simulation time 3076760949 ps
CPU time 26.62 seconds
Started Jul 07 05:04:19 PM PDT 24
Finished Jul 07 05:04:46 PM PDT 24
Peak memory 211996 kb
Host smart-3273996b-b277-4786-bcc9-56fe1c0013fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504430865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1504430865
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1062780026
Short name T210
Test name
Test status
Simulation time 8637133816 ps
CPU time 10.49 seconds
Started Jul 07 05:04:15 PM PDT 24
Finished Jul 07 05:04:25 PM PDT 24
Peak memory 211312 kb
Host smart-90573fa7-e1c1-4363-8903-14e48e88d406
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062780026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1062780026
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1632010506
Short name T129
Test name
Test status
Simulation time 14812402479 ps
CPU time 34.01 seconds
Started Jul 07 05:04:15 PM PDT 24
Finished Jul 07 05:04:50 PM PDT 24
Peak memory 213976 kb
Host smart-a2d55adc-3bdc-4b1e-bed8-7b431a7d495b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632010506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1632010506
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3756960799
Short name T233
Test name
Test status
Simulation time 14038913333 ps
CPU time 60.27 seconds
Started Jul 07 05:04:15 PM PDT 24
Finished Jul 07 05:05:16 PM PDT 24
Peak memory 217516 kb
Host smart-b830f6c5-e0d1-4ce4-b3d5-2222dbfcad01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756960799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3756960799
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1413107214
Short name T59
Test name
Test status
Simulation time 5733585821 ps
CPU time 12.76 seconds
Started Jul 07 05:04:25 PM PDT 24
Finished Jul 07 05:04:38 PM PDT 24
Peak memory 211272 kb
Host smart-d3decf3f-4608-4bf8-9153-fa863144c736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413107214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1413107214
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.927117769
Short name T317
Test name
Test status
Simulation time 62860224424 ps
CPU time 302.93 seconds
Started Jul 07 05:04:26 PM PDT 24
Finished Jul 07 05:09:29 PM PDT 24
Peak memory 237804 kb
Host smart-7df68bb9-8741-40d8-853b-ab92f1f5f87a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927117769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.927117769
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4184318974
Short name T27
Test name
Test status
Simulation time 3960860501 ps
CPU time 32.51 seconds
Started Jul 07 05:04:23 PM PDT 24
Finished Jul 07 05:04:56 PM PDT 24
Peak memory 211964 kb
Host smart-a8e8791e-2bce-4896-b175-eecac1ca9369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184318974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4184318974
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1626783159
Short name T117
Test name
Test status
Simulation time 2418874365 ps
CPU time 9.19 seconds
Started Jul 07 05:04:21 PM PDT 24
Finished Jul 07 05:04:30 PM PDT 24
Peak memory 211396 kb
Host smart-43999f0b-3542-40e9-89e5-036056e18657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626783159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1626783159
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.75679457
Short name T70
Test name
Test status
Simulation time 4704031847 ps
CPU time 35.58 seconds
Started Jul 07 05:04:20 PM PDT 24
Finished Jul 07 05:04:55 PM PDT 24
Peak memory 213536 kb
Host smart-d7ecc6ac-e5af-49ed-8e2d-af72b9303230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75679457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.75679457
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2889253133
Short name T96
Test name
Test status
Simulation time 25608182490 ps
CPU time 51.33 seconds
Started Jul 07 05:04:21 PM PDT 24
Finished Jul 07 05:05:12 PM PDT 24
Peak memory 213844 kb
Host smart-e8036ae5-bd50-4041-9800-0ac98b3351bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889253133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2889253133
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1289085960
Short name T126
Test name
Test status
Simulation time 2176260995 ps
CPU time 16.48 seconds
Started Jul 07 05:04:31 PM PDT 24
Finished Jul 07 05:04:48 PM PDT 24
Peak memory 211364 kb
Host smart-ff623845-a518-40a2-8a7c-fa754fecdb7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289085960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1289085960
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3922202386
Short name T250
Test name
Test status
Simulation time 26894861514 ps
CPU time 136.4 seconds
Started Jul 07 05:04:28 PM PDT 24
Finished Jul 07 05:06:45 PM PDT 24
Peak memory 227852 kb
Host smart-a7585244-e53d-41d5-8bb7-1afaf5a4dce2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922202386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3922202386
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.989519910
Short name T179
Test name
Test status
Simulation time 4200897377 ps
CPU time 33.67 seconds
Started Jul 07 05:04:28 PM PDT 24
Finished Jul 07 05:05:02 PM PDT 24
Peak memory 211924 kb
Host smart-86a86344-689d-4f80-9c28-ff1c739fee24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989519910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.989519910
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1577254489
Short name T223
Test name
Test status
Simulation time 371478866 ps
CPU time 5.71 seconds
Started Jul 07 05:04:28 PM PDT 24
Finished Jul 07 05:04:34 PM PDT 24
Peak memory 211296 kb
Host smart-de177aff-499e-493d-bef8-0828af5b3145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577254489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1577254489
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4182360230
Short name T157
Test name
Test status
Simulation time 1977261843 ps
CPU time 23.75 seconds
Started Jul 07 05:04:24 PM PDT 24
Finished Jul 07 05:04:48 PM PDT 24
Peak memory 213204 kb
Host smart-84029816-8876-40bb-9738-a92b3e619227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182360230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4182360230
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4280945721
Short name T148
Test name
Test status
Simulation time 6110450671 ps
CPU time 31.9 seconds
Started Jul 07 05:04:26 PM PDT 24
Finished Jul 07 05:04:58 PM PDT 24
Peak memory 216296 kb
Host smart-d662deaa-482d-4d43-b766-96cc4aa88fd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280945721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4280945721
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2415663102
Short name T5
Test name
Test status
Simulation time 2004013304 ps
CPU time 16.92 seconds
Started Jul 07 05:02:04 PM PDT 24
Finished Jul 07 05:02:21 PM PDT 24
Peak memory 211288 kb
Host smart-931562c1-1599-47df-ad85-4282cf14ea96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415663102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2415663102
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.856440341
Short name T291
Test name
Test status
Simulation time 10083754170 ps
CPU time 119.63 seconds
Started Jul 07 05:02:00 PM PDT 24
Finished Jul 07 05:04:00 PM PDT 24
Peak memory 234868 kb
Host smart-c5eec8fe-fc21-4cd4-bce3-185b1a8887c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856440341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.856440341
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2365706611
Short name T144
Test name
Test status
Simulation time 5491750394 ps
CPU time 18.4 seconds
Started Jul 07 05:02:01 PM PDT 24
Finished Jul 07 05:02:19 PM PDT 24
Peak memory 212228 kb
Host smart-b3eee688-c6ed-434c-8697-159844e61bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365706611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2365706611
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1457476295
Short name T340
Test name
Test status
Simulation time 2090955437 ps
CPU time 17.01 seconds
Started Jul 07 05:02:01 PM PDT 24
Finished Jul 07 05:02:18 PM PDT 24
Peak memory 211324 kb
Host smart-62033d15-7c69-49a2-b6fc-d50829a01d40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1457476295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1457476295
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3056897091
Short name T23
Test name
Test status
Simulation time 19920765911 ps
CPU time 111.05 seconds
Started Jul 07 05:02:05 PM PDT 24
Finished Jul 07 05:03:57 PM PDT 24
Peak memory 235732 kb
Host smart-5a0ebf3c-3681-4675-9955-097e8fd43ee7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056897091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3056897091
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4176666607
Short name T270
Test name
Test status
Simulation time 15924483046 ps
CPU time 26.89 seconds
Started Jul 07 05:02:01 PM PDT 24
Finished Jul 07 05:02:28 PM PDT 24
Peak memory 213948 kb
Host smart-fc7e6ab8-8f74-4da4-8fda-fa6a6efafc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176666607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4176666607
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2702127188
Short name T72
Test name
Test status
Simulation time 4113065973 ps
CPU time 55 seconds
Started Jul 07 05:02:00 PM PDT 24
Finished Jul 07 05:02:55 PM PDT 24
Peak memory 216752 kb
Host smart-b681de27-5266-4a6d-968b-b463a860c017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702127188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2702127188
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2729924553
Short name T149
Test name
Test status
Simulation time 372441886 ps
CPU time 6.84 seconds
Started Jul 07 05:04:34 PM PDT 24
Finished Jul 07 05:04:41 PM PDT 24
Peak memory 211300 kb
Host smart-6a124dce-3ae7-43dd-bda6-a57def8efbef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729924553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2729924553
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3035749268
Short name T189
Test name
Test status
Simulation time 7122178129 ps
CPU time 107.14 seconds
Started Jul 07 05:04:33 PM PDT 24
Finished Jul 07 05:06:20 PM PDT 24
Peak memory 236788 kb
Host smart-a8d517e0-4d57-4c3a-82a5-af313147b15b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035749268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3035749268
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3852816150
Short name T197
Test name
Test status
Simulation time 994430717 ps
CPU time 11.17 seconds
Started Jul 07 05:04:35 PM PDT 24
Finished Jul 07 05:04:46 PM PDT 24
Peak memory 212064 kb
Host smart-17d61cc0-8ab7-449b-a5d7-3adf965e71d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852816150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3852816150
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.559361149
Short name T84
Test name
Test status
Simulation time 97813235 ps
CPU time 5.28 seconds
Started Jul 07 05:04:32 PM PDT 24
Finished Jul 07 05:04:38 PM PDT 24
Peak memory 211332 kb
Host smart-bb490a63-326d-4c52-a7ab-acaa94d53570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559361149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.559361149
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.368122638
Short name T310
Test name
Test status
Simulation time 3498639072 ps
CPU time 29.23 seconds
Started Jul 07 05:04:34 PM PDT 24
Finished Jul 07 05:05:03 PM PDT 24
Peak memory 213036 kb
Host smart-99d4d457-ccfb-4a14-a397-b5b5e1ede87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368122638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.368122638
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.310665499
Short name T289
Test name
Test status
Simulation time 8339392304 ps
CPU time 24.64 seconds
Started Jul 07 05:04:32 PM PDT 24
Finished Jul 07 05:04:58 PM PDT 24
Peak memory 214608 kb
Host smart-62b051c9-7d91-4829-9a6f-a0d56992c089
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310665499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.310665499
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.42091014
Short name T209
Test name
Test status
Simulation time 3531233607 ps
CPU time 9.46 seconds
Started Jul 07 05:04:32 PM PDT 24
Finished Jul 07 05:04:42 PM PDT 24
Peak memory 211308 kb
Host smart-beb02016-abe2-4fae-8322-ef1d274f3251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42091014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.42091014
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2829923712
Short name T342
Test name
Test status
Simulation time 1700193058 ps
CPU time 112.08 seconds
Started Jul 07 05:04:35 PM PDT 24
Finished Jul 07 05:06:27 PM PDT 24
Peak memory 236892 kb
Host smart-fa1ebbcb-93ce-4c33-a4c0-0de261a2740c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829923712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2829923712
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1415916144
Short name T166
Test name
Test status
Simulation time 6354433390 ps
CPU time 29.11 seconds
Started Jul 07 05:04:34 PM PDT 24
Finished Jul 07 05:05:04 PM PDT 24
Peak memory 212200 kb
Host smart-8160f250-7fae-4a46-9ddd-9213a9708011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415916144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1415916144
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1504419046
Short name T50
Test name
Test status
Simulation time 4302999695 ps
CPU time 16.79 seconds
Started Jul 07 05:04:33 PM PDT 24
Finished Jul 07 05:04:50 PM PDT 24
Peak memory 211392 kb
Host smart-e1d2f0c7-d980-4f94-94b8-893421a1d4d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504419046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1504419046
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1011790819
Short name T230
Test name
Test status
Simulation time 6883721768 ps
CPU time 35.19 seconds
Started Jul 07 05:04:32 PM PDT 24
Finished Jul 07 05:05:08 PM PDT 24
Peak memory 214284 kb
Host smart-69bcfa98-2cf0-468e-9d52-d7d9567a1666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011790819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1011790819
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2766695972
Short name T49
Test name
Test status
Simulation time 996052673 ps
CPU time 10.63 seconds
Started Jul 07 05:04:34 PM PDT 24
Finished Jul 07 05:04:45 PM PDT 24
Peak memory 215004 kb
Host smart-2c731062-79e5-4776-99ee-063a32944a1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766695972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2766695972
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1075662624
Short name T256
Test name
Test status
Simulation time 2955499557 ps
CPU time 12.89 seconds
Started Jul 07 05:04:39 PM PDT 24
Finished Jul 07 05:04:53 PM PDT 24
Peak memory 211348 kb
Host smart-bd54ca4d-a4a7-489d-a31a-9d3bb39e829c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075662624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1075662624
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1134084213
Short name T183
Test name
Test status
Simulation time 3172474952 ps
CPU time 110.71 seconds
Started Jul 07 05:04:39 PM PDT 24
Finished Jul 07 05:06:31 PM PDT 24
Peak memory 237816 kb
Host smart-74aa64b7-3563-446d-abd0-a380dbc5d1c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134084213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1134084213
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1522601832
Short name T118
Test name
Test status
Simulation time 43650524626 ps
CPU time 26.15 seconds
Started Jul 07 05:04:37 PM PDT 24
Finished Jul 07 05:05:04 PM PDT 24
Peak memory 212500 kb
Host smart-7713b6ec-f224-4c5a-8e3b-3d28b1326b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522601832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1522601832
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.531922920
Short name T198
Test name
Test status
Simulation time 357509286 ps
CPU time 5.39 seconds
Started Jul 07 05:04:37 PM PDT 24
Finished Jul 07 05:04:42 PM PDT 24
Peak memory 211252 kb
Host smart-5d646f83-dde1-48a1-8d1b-6d9e92421a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531922920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.531922920
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3882386563
Short name T171
Test name
Test status
Simulation time 183252473 ps
CPU time 10.58 seconds
Started Jul 07 05:04:37 PM PDT 24
Finished Jul 07 05:04:49 PM PDT 24
Peak memory 213052 kb
Host smart-1ce20094-8ef8-430a-9638-55461f41b45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882386563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3882386563
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1182262331
Short name T355
Test name
Test status
Simulation time 785912315 ps
CPU time 8.88 seconds
Started Jul 07 05:04:38 PM PDT 24
Finished Jul 07 05:04:47 PM PDT 24
Peak memory 211304 kb
Host smart-c2478760-ccd7-4b16-8870-5403e08997d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182262331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1182262331
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2819331607
Short name T43
Test name
Test status
Simulation time 110258080573 ps
CPU time 1760.39 seconds
Started Jul 07 05:04:37 PM PDT 24
Finished Jul 07 05:33:59 PM PDT 24
Peak memory 235996 kb
Host smart-71704db7-6ff8-46be-80b9-bbd03cd90b19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819331607 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2819331607
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2177655776
Short name T193
Test name
Test status
Simulation time 3522306537 ps
CPU time 14.66 seconds
Started Jul 07 05:04:41 PM PDT 24
Finished Jul 07 05:04:56 PM PDT 24
Peak memory 211372 kb
Host smart-7c563622-716c-420a-b080-0313967d71cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177655776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2177655776
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1308395680
Short name T330
Test name
Test status
Simulation time 31716036552 ps
CPU time 186.94 seconds
Started Jul 07 05:04:39 PM PDT 24
Finished Jul 07 05:07:47 PM PDT 24
Peak memory 228488 kb
Host smart-3bdac07d-1a6b-4485-a08f-2d7f522f029a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308395680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1308395680
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.965610194
Short name T154
Test name
Test status
Simulation time 5336882223 ps
CPU time 24.34 seconds
Started Jul 07 05:04:43 PM PDT 24
Finished Jul 07 05:05:08 PM PDT 24
Peak memory 212320 kb
Host smart-9b0dc1c2-8d31-4ee7-98a9-86f5c9c25d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965610194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.965610194
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.14173081
Short name T281
Test name
Test status
Simulation time 1273139951 ps
CPU time 12.53 seconds
Started Jul 07 05:04:37 PM PDT 24
Finished Jul 07 05:04:51 PM PDT 24
Peak memory 211336 kb
Host smart-17e32bb8-18a4-41aa-bc5a-1e5ac2497262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14173081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.14173081
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3391662341
Short name T277
Test name
Test status
Simulation time 431825514 ps
CPU time 13.22 seconds
Started Jul 07 05:04:38 PM PDT 24
Finished Jul 07 05:04:51 PM PDT 24
Peak memory 213208 kb
Host smart-a72fa2c0-20c3-4537-91ce-acd81192d33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391662341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3391662341
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2876979136
Short name T69
Test name
Test status
Simulation time 7134702431 ps
CPU time 28.82 seconds
Started Jul 07 05:04:38 PM PDT 24
Finished Jul 07 05:05:07 PM PDT 24
Peak memory 216952 kb
Host smart-33e4c4da-098a-4f38-af41-0b59332fbe7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876979136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2876979136
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1071754778
Short name T264
Test name
Test status
Simulation time 7590833534 ps
CPU time 14.42 seconds
Started Jul 07 05:04:52 PM PDT 24
Finished Jul 07 05:05:07 PM PDT 24
Peak memory 211360 kb
Host smart-3b2198fa-d891-494c-a2f2-eab04d5ec5ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071754778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1071754778
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2862336882
Short name T228
Test name
Test status
Simulation time 16375590206 ps
CPU time 107.09 seconds
Started Jul 07 05:04:47 PM PDT 24
Finished Jul 07 05:06:35 PM PDT 24
Peak memory 234428 kb
Host smart-604370b0-3af0-42a7-9370-27858518978a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862336882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2862336882
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.983761974
Short name T140
Test name
Test status
Simulation time 2922868590 ps
CPU time 27.48 seconds
Started Jul 07 05:04:47 PM PDT 24
Finished Jul 07 05:05:14 PM PDT 24
Peak memory 211820 kb
Host smart-b0f00113-19b0-4749-a481-72ed35a1367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983761974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.983761974
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.490832452
Short name T362
Test name
Test status
Simulation time 177649644 ps
CPU time 5.25 seconds
Started Jul 07 05:04:47 PM PDT 24
Finished Jul 07 05:04:52 PM PDT 24
Peak memory 211372 kb
Host smart-91951527-45c5-469c-85f6-508326612ed5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=490832452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.490832452
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.32637899
Short name T278
Test name
Test status
Simulation time 3650610966 ps
CPU time 24.86 seconds
Started Jul 07 05:04:42 PM PDT 24
Finished Jul 07 05:05:08 PM PDT 24
Peak memory 213352 kb
Host smart-216dc3b3-e842-4675-a940-e8fd84b0b793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32637899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.32637899
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1780124383
Short name T259
Test name
Test status
Simulation time 959677459 ps
CPU time 17.87 seconds
Started Jul 07 05:04:48 PM PDT 24
Finished Jul 07 05:05:06 PM PDT 24
Peak memory 213092 kb
Host smart-cff76703-08e9-47dc-8cf3-e380e3f47399
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780124383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1780124383
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.970974309
Short name T290
Test name
Test status
Simulation time 3723880789 ps
CPU time 9.96 seconds
Started Jul 07 05:04:52 PM PDT 24
Finished Jul 07 05:05:02 PM PDT 24
Peak memory 211348 kb
Host smart-3b44de77-6715-43a8-821c-f177b46fa47e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970974309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.970974309
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3133850797
Short name T139
Test name
Test status
Simulation time 17947614232 ps
CPU time 105.49 seconds
Started Jul 07 05:04:51 PM PDT 24
Finished Jul 07 05:06:37 PM PDT 24
Peak memory 239776 kb
Host smart-1a712a0c-20ab-4e10-ab80-cb12de189642
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133850797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3133850797
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.777091149
Short name T357
Test name
Test status
Simulation time 15483973414 ps
CPU time 30.07 seconds
Started Jul 07 05:04:52 PM PDT 24
Finished Jul 07 05:05:22 PM PDT 24
Peak memory 212908 kb
Host smart-85a0ec88-7ee5-4ae6-86a9-ccde3574ce65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777091149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.777091149
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2527727372
Short name T93
Test name
Test status
Simulation time 1814468078 ps
CPU time 5.79 seconds
Started Jul 07 05:04:51 PM PDT 24
Finished Jul 07 05:04:57 PM PDT 24
Peak memory 211340 kb
Host smart-c5334a23-8c1b-4c55-9022-0c69ca7e4af6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2527727372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2527727372
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3472434948
Short name T181
Test name
Test status
Simulation time 716957908 ps
CPU time 10.33 seconds
Started Jul 07 05:04:51 PM PDT 24
Finished Jul 07 05:05:01 PM PDT 24
Peak memory 212752 kb
Host smart-5bce0952-6fcf-450e-9256-d5321325c4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472434948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3472434948
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1816447525
Short name T318
Test name
Test status
Simulation time 6470211099 ps
CPU time 53.06 seconds
Started Jul 07 05:04:52 PM PDT 24
Finished Jul 07 05:05:46 PM PDT 24
Peak memory 213100 kb
Host smart-f5e7b752-7c7c-4210-bc6f-acdec2637283
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816447525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1816447525
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2300758061
Short name T182
Test name
Test status
Simulation time 174957546 ps
CPU time 4.32 seconds
Started Jul 07 05:04:55 PM PDT 24
Finished Jul 07 05:05:00 PM PDT 24
Peak memory 211232 kb
Host smart-8c853cc6-bcc8-4d2b-a4c8-9a896e23e995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300758061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2300758061
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1469553075
Short name T334
Test name
Test status
Simulation time 11204737513 ps
CPU time 161.63 seconds
Started Jul 07 05:04:54 PM PDT 24
Finished Jul 07 05:07:36 PM PDT 24
Peak memory 225372 kb
Host smart-d9bfd08c-360e-4d1f-b235-fbe6c55f3e6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469553075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1469553075
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1328551865
Short name T341
Test name
Test status
Simulation time 721277751 ps
CPU time 13.67 seconds
Started Jul 07 05:04:52 PM PDT 24
Finished Jul 07 05:05:06 PM PDT 24
Peak memory 212036 kb
Host smart-d207fd05-a7fc-4004-9870-1b7bf5b4da49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328551865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1328551865
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1767085929
Short name T138
Test name
Test status
Simulation time 2313310808 ps
CPU time 12.58 seconds
Started Jul 07 05:04:50 PM PDT 24
Finished Jul 07 05:05:03 PM PDT 24
Peak memory 211404 kb
Host smart-5213a7bc-c0d3-43e4-9ac5-46388571bd69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767085929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1767085929
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3959245051
Short name T199
Test name
Test status
Simulation time 177009070 ps
CPU time 10.17 seconds
Started Jul 07 05:04:50 PM PDT 24
Finished Jul 07 05:05:01 PM PDT 24
Peak memory 212328 kb
Host smart-7db3f24e-a1d6-41f9-8057-57896168ce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959245051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3959245051
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.4251016078
Short name T124
Test name
Test status
Simulation time 892682938 ps
CPU time 12.14 seconds
Started Jul 07 05:04:51 PM PDT 24
Finished Jul 07 05:05:03 PM PDT 24
Peak memory 211288 kb
Host smart-69e38d0c-498f-46a4-8850-575750ad0845
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251016078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.4251016078
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1354062475
Short name T288
Test name
Test status
Simulation time 669532298 ps
CPU time 8.58 seconds
Started Jul 07 05:05:01 PM PDT 24
Finished Jul 07 05:05:10 PM PDT 24
Peak memory 211296 kb
Host smart-75bae606-2ec2-4dca-ad14-ff15835270ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354062475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1354062475
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.787366228
Short name T127
Test name
Test status
Simulation time 18031982943 ps
CPU time 162.26 seconds
Started Jul 07 05:05:01 PM PDT 24
Finished Jul 07 05:07:44 PM PDT 24
Peak memory 234840 kb
Host smart-1452d5b6-6724-41f1-9c3f-386195f77a82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787366228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.787366228
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3353370468
Short name T219
Test name
Test status
Simulation time 12695980952 ps
CPU time 26.75 seconds
Started Jul 07 05:05:00 PM PDT 24
Finished Jul 07 05:05:27 PM PDT 24
Peak memory 211408 kb
Host smart-fd3b5269-ac7f-4cd3-b87b-cf0cda373a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353370468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3353370468
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.330531870
Short name T133
Test name
Test status
Simulation time 1143058093 ps
CPU time 5.66 seconds
Started Jul 07 05:05:01 PM PDT 24
Finished Jul 07 05:05:08 PM PDT 24
Peak memory 211292 kb
Host smart-37771711-ab09-47aa-a9da-fdeb785a2fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330531870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.330531870
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4282912944
Short name T143
Test name
Test status
Simulation time 4772748569 ps
CPU time 23.26 seconds
Started Jul 07 05:04:57 PM PDT 24
Finished Jul 07 05:05:20 PM PDT 24
Peak memory 213632 kb
Host smart-303968a4-a498-42d0-b933-c672240c3f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282912944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4282912944
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3627100706
Short name T368
Test name
Test status
Simulation time 5710321588 ps
CPU time 56.65 seconds
Started Jul 07 05:04:55 PM PDT 24
Finished Jul 07 05:05:52 PM PDT 24
Peak memory 217272 kb
Host smart-6976ab73-fe0e-4fc9-b405-90ff4655bf35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627100706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3627100706
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1766630923
Short name T134
Test name
Test status
Simulation time 3545333727 ps
CPU time 7.84 seconds
Started Jul 07 05:05:07 PM PDT 24
Finished Jul 07 05:05:15 PM PDT 24
Peak memory 211304 kb
Host smart-ec609ccd-bbb2-4075-86c5-5b7bdac362e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766630923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1766630923
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3631399351
Short name T169
Test name
Test status
Simulation time 10588305841 ps
CPU time 20.33 seconds
Started Jul 07 05:05:01 PM PDT 24
Finished Jul 07 05:05:22 PM PDT 24
Peak memory 212212 kb
Host smart-804c1426-6ee7-4701-b558-965e9828499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631399351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3631399351
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2886470968
Short name T201
Test name
Test status
Simulation time 17770805806 ps
CPU time 14.66 seconds
Started Jul 07 05:05:00 PM PDT 24
Finished Jul 07 05:05:16 PM PDT 24
Peak memory 211316 kb
Host smart-1fd8e6c5-40d4-4801-bf75-f6fa77d80e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886470968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2886470968
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2075607280
Short name T1
Test name
Test status
Simulation time 995075663 ps
CPU time 10.4 seconds
Started Jul 07 05:04:59 PM PDT 24
Finished Jul 07 05:05:09 PM PDT 24
Peak memory 213268 kb
Host smart-38dd5c3f-5bdc-4bcd-a24e-b7fc56c77921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075607280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2075607280
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2536378925
Short name T301
Test name
Test status
Simulation time 5928847013 ps
CPU time 61.29 seconds
Started Jul 07 05:05:00 PM PDT 24
Finished Jul 07 05:06:02 PM PDT 24
Peak memory 215200 kb
Host smart-ce96dc79-531e-4fe6-8e16-7627e07e4464
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536378925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2536378925
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2029557650
Short name T300
Test name
Test status
Simulation time 72233366375 ps
CPU time 2332.82 seconds
Started Jul 07 05:05:01 PM PDT 24
Finished Jul 07 05:43:54 PM PDT 24
Peak memory 248772 kb
Host smart-63c55295-0956-4f5f-a9ec-2f553f223e63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029557650 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2029557650
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.216119060
Short name T216
Test name
Test status
Simulation time 6208036400 ps
CPU time 14.28 seconds
Started Jul 07 05:05:09 PM PDT 24
Finished Jul 07 05:05:24 PM PDT 24
Peak memory 211296 kb
Host smart-7388138e-2504-4a67-ac3a-b5e82f442b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216119060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.216119060
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3689029243
Short name T347
Test name
Test status
Simulation time 4265157919 ps
CPU time 132.51 seconds
Started Jul 07 05:05:09 PM PDT 24
Finished Jul 07 05:07:22 PM PDT 24
Peak memory 237748 kb
Host smart-b31c76fa-a710-4546-a4fa-cafee9487f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689029243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3689029243
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2660909605
Short name T37
Test name
Test status
Simulation time 665998606 ps
CPU time 9.51 seconds
Started Jul 07 05:05:07 PM PDT 24
Finished Jul 07 05:05:17 PM PDT 24
Peak memory 211956 kb
Host smart-e2524c78-d18b-4d91-a51d-8cbec39d6e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660909605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2660909605
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.140059929
Short name T120
Test name
Test status
Simulation time 99611734 ps
CPU time 5.71 seconds
Started Jul 07 05:05:07 PM PDT 24
Finished Jul 07 05:05:13 PM PDT 24
Peak memory 211364 kb
Host smart-0767cc43-84ec-4f17-9f8b-308063add72d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=140059929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.140059929
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.901104288
Short name T315
Test name
Test status
Simulation time 3926375401 ps
CPU time 37.44 seconds
Started Jul 07 05:05:07 PM PDT 24
Finished Jul 07 05:05:45 PM PDT 24
Peak memory 212840 kb
Host smart-fd67d7de-0481-4ad2-831a-39015c18a7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901104288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.901104288
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2881159951
Short name T286
Test name
Test status
Simulation time 1039089861 ps
CPU time 14.39 seconds
Started Jul 07 05:05:09 PM PDT 24
Finished Jul 07 05:05:24 PM PDT 24
Peak memory 212128 kb
Host smart-65ea12c3-d259-4669-8a89-722b35a647c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881159951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2881159951
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3697304598
Short name T280
Test name
Test status
Simulation time 4448070091 ps
CPU time 15.78 seconds
Started Jul 07 05:02:11 PM PDT 24
Finished Jul 07 05:02:27 PM PDT 24
Peak memory 211332 kb
Host smart-5ad61f4e-0ed0-4dd0-a229-e05f46639e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697304598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3697304598
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.780183271
Short name T170
Test name
Test status
Simulation time 5401088434 ps
CPU time 62.37 seconds
Started Jul 07 05:02:09 PM PDT 24
Finished Jul 07 05:03:12 PM PDT 24
Peak memory 212584 kb
Host smart-45e75a9f-20d0-4bb5-a78c-5e3bb9d75db2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780183271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.780183271
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1057145301
Short name T245
Test name
Test status
Simulation time 2129212259 ps
CPU time 22.64 seconds
Started Jul 07 05:02:11 PM PDT 24
Finished Jul 07 05:02:34 PM PDT 24
Peak memory 211796 kb
Host smart-5038aba2-2cea-4b14-913f-f4fcaa067894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057145301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1057145301
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3837553315
Short name T367
Test name
Test status
Simulation time 196780904 ps
CPU time 5.5 seconds
Started Jul 07 05:02:09 PM PDT 24
Finished Jul 07 05:02:14 PM PDT 24
Peak memory 211340 kb
Host smart-f7802d1a-a855-4e62-ae28-e653d0c2de5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837553315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3837553315
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2220983986
Short name T113
Test name
Test status
Simulation time 7764581246 ps
CPU time 36.77 seconds
Started Jul 07 05:02:05 PM PDT 24
Finished Jul 07 05:02:42 PM PDT 24
Peak memory 213548 kb
Host smart-e51a2667-22cd-4ae5-9c83-a5195f7ca481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220983986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2220983986
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1513101900
Short name T240
Test name
Test status
Simulation time 6949487980 ps
CPU time 34.49 seconds
Started Jul 07 05:02:04 PM PDT 24
Finished Jul 07 05:02:39 PM PDT 24
Peak memory 216292 kb
Host smart-40406d3e-1080-4dcd-8fef-d7d56d3aff18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513101900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1513101900
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3395272934
Short name T331
Test name
Test status
Simulation time 85643541 ps
CPU time 4.44 seconds
Started Jul 07 05:02:13 PM PDT 24
Finished Jul 07 05:02:18 PM PDT 24
Peak memory 211244 kb
Host smart-79477ae1-089c-49ea-998b-579fe040d67a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395272934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3395272934
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4108929362
Short name T206
Test name
Test status
Simulation time 26135296257 ps
CPU time 342.72 seconds
Started Jul 07 05:02:14 PM PDT 24
Finished Jul 07 05:07:57 PM PDT 24
Peak memory 240964 kb
Host smart-3d61ee3e-95c1-4823-8408-12db4e90ddb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108929362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4108929362
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1475553492
Short name T142
Test name
Test status
Simulation time 10019278930 ps
CPU time 23.6 seconds
Started Jul 07 05:02:12 PM PDT 24
Finished Jul 07 05:02:36 PM PDT 24
Peak memory 212168 kb
Host smart-a424885b-1677-43a9-aa42-8334d4618ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475553492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1475553492
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1453819257
Short name T215
Test name
Test status
Simulation time 4214187200 ps
CPU time 17.47 seconds
Started Jul 07 05:02:09 PM PDT 24
Finished Jul 07 05:02:26 PM PDT 24
Peak memory 211392 kb
Host smart-5a07e8d7-937a-4da0-8210-001e5558b753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1453819257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1453819257
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3965957195
Short name T190
Test name
Test status
Simulation time 1670819663 ps
CPU time 18.34 seconds
Started Jul 07 05:02:09 PM PDT 24
Finished Jul 07 05:02:27 PM PDT 24
Peak memory 213672 kb
Host smart-925ea894-cb9d-4136-a625-3ac67acddc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965957195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3965957195
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3535245016
Short name T213
Test name
Test status
Simulation time 1091878351 ps
CPU time 20.01 seconds
Started Jul 07 05:02:08 PM PDT 24
Finished Jul 07 05:02:28 PM PDT 24
Peak memory 213276 kb
Host smart-c2978416-d42f-45a0-89d4-fb8938bf31e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535245016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3535245016
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.456114978
Short name T184
Test name
Test status
Simulation time 1741057232 ps
CPU time 9.57 seconds
Started Jul 07 05:02:24 PM PDT 24
Finished Jul 07 05:02:34 PM PDT 24
Peak memory 211288 kb
Host smart-09962de1-2f7a-43c3-875a-ea7a932d96ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456114978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.456114978
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1771422917
Short name T147
Test name
Test status
Simulation time 63443785728 ps
CPU time 281.79 seconds
Started Jul 07 05:02:21 PM PDT 24
Finished Jul 07 05:07:03 PM PDT 24
Peak memory 237676 kb
Host smart-659ef561-2fae-4d9c-8cd5-4b36070f1a2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771422917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1771422917
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3768045539
Short name T165
Test name
Test status
Simulation time 3979533834 ps
CPU time 26.26 seconds
Started Jul 07 05:02:24 PM PDT 24
Finished Jul 07 05:02:51 PM PDT 24
Peak memory 211868 kb
Host smart-410a31bc-8ec6-401a-8ca8-a316bddf0b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768045539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3768045539
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4001887190
Short name T352
Test name
Test status
Simulation time 8376604520 ps
CPU time 16.92 seconds
Started Jul 07 05:02:16 PM PDT 24
Finished Jul 07 05:02:33 PM PDT 24
Peak memory 211348 kb
Host smart-0eee9890-5621-417a-8c20-8f96fb06647e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4001887190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4001887190
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3128899608
Short name T174
Test name
Test status
Simulation time 13649306243 ps
CPU time 33.96 seconds
Started Jul 07 05:02:17 PM PDT 24
Finished Jul 07 05:02:51 PM PDT 24
Peak memory 213636 kb
Host smart-ebb57b2a-57b8-48b2-8a78-f339d500c714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128899608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3128899608
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3350974593
Short name T267
Test name
Test status
Simulation time 22575361357 ps
CPU time 47.12 seconds
Started Jul 07 05:02:18 PM PDT 24
Finished Jul 07 05:03:06 PM PDT 24
Peak memory 215708 kb
Host smart-886f6e4c-359a-47fb-8a74-b6a3b0cc4c8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350974593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3350974593
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.850293229
Short name T370
Test name
Test status
Simulation time 85757544 ps
CPU time 4.27 seconds
Started Jul 07 05:02:25 PM PDT 24
Finished Jul 07 05:02:30 PM PDT 24
Peak memory 211216 kb
Host smart-42e4a33b-b355-4d97-874b-002aec0d9f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850293229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.850293229
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3984222891
Short name T21
Test name
Test status
Simulation time 13199947836 ps
CPU time 132.9 seconds
Started Jul 07 05:02:26 PM PDT 24
Finished Jul 07 05:04:39 PM PDT 24
Peak memory 236792 kb
Host smart-b5f7ddec-1569-4814-9cae-2c3ccfad1ffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984222891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3984222891
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.325002654
Short name T36
Test name
Test status
Simulation time 3234228060 ps
CPU time 14.75 seconds
Started Jul 07 05:02:26 PM PDT 24
Finished Jul 07 05:02:41 PM PDT 24
Peak memory 211944 kb
Host smart-9a6b9331-fae2-42a3-844c-e92f6ffcd9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325002654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.325002654
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2381069417
Short name T121
Test name
Test status
Simulation time 4461331839 ps
CPU time 11.51 seconds
Started Jul 07 05:02:27 PM PDT 24
Finished Jul 07 05:02:39 PM PDT 24
Peak memory 211340 kb
Host smart-c36ff41a-0dfa-41a7-ad9b-e958ff88b8e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2381069417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2381069417
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2861587714
Short name T162
Test name
Test status
Simulation time 731927687 ps
CPU time 10.45 seconds
Started Jul 07 05:02:20 PM PDT 24
Finished Jul 07 05:02:31 PM PDT 24
Peak memory 213596 kb
Host smart-1bc4ba01-b9bc-41ad-bf8a-dbe3086f25a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861587714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2861587714
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2478137606
Short name T217
Test name
Test status
Simulation time 2610264422 ps
CPU time 25.21 seconds
Started Jul 07 05:02:21 PM PDT 24
Finished Jul 07 05:02:46 PM PDT 24
Peak memory 213800 kb
Host smart-314d70a8-6287-4696-a194-4b77b0d23168
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478137606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2478137606
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4235633004
Short name T314
Test name
Test status
Simulation time 159586028605 ps
CPU time 1449.64 seconds
Started Jul 07 05:02:26 PM PDT 24
Finished Jul 07 05:26:36 PM PDT 24
Peak memory 233828 kb
Host smart-2845862c-af46-49cd-8c3a-1676cd7331e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235633004 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.4235633004
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.124270921
Short name T287
Test name
Test status
Simulation time 2097849455 ps
CPU time 10.9 seconds
Started Jul 07 05:02:32 PM PDT 24
Finished Jul 07 05:02:43 PM PDT 24
Peak memory 211244 kb
Host smart-6dfa7f5d-287b-4e3c-aecb-86d70bd97608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124270921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.124270921
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2157583327
Short name T231
Test name
Test status
Simulation time 241898080575 ps
CPU time 287.39 seconds
Started Jul 07 05:02:31 PM PDT 24
Finished Jul 07 05:07:19 PM PDT 24
Peak memory 238080 kb
Host smart-c6960747-0339-4dff-a855-3946fcd44c83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157583327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2157583327
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2065275633
Short name T354
Test name
Test status
Simulation time 8206282700 ps
CPU time 32.14 seconds
Started Jul 07 05:02:30 PM PDT 24
Finished Jul 07 05:03:03 PM PDT 24
Peak memory 212876 kb
Host smart-c3e930d2-327a-45ab-b380-de02863e2205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065275633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2065275633
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1902390546
Short name T308
Test name
Test status
Simulation time 2186372472 ps
CPU time 7.4 seconds
Started Jul 07 05:02:26 PM PDT 24
Finished Jul 07 05:02:34 PM PDT 24
Peak memory 211392 kb
Host smart-f4865f78-ff95-471a-950e-10eb180d38be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902390546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1902390546
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2505479697
Short name T361
Test name
Test status
Simulation time 696811231 ps
CPU time 14.79 seconds
Started Jul 07 05:02:26 PM PDT 24
Finished Jul 07 05:02:41 PM PDT 24
Peak memory 213516 kb
Host smart-ad9252e1-0e53-484c-8a95-43478fe7e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505479697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2505479697
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1516620910
Short name T236
Test name
Test status
Simulation time 2122383658 ps
CPU time 30.5 seconds
Started Jul 07 05:02:27 PM PDT 24
Finished Jul 07 05:02:57 PM PDT 24
Peak memory 216344 kb
Host smart-c78f730e-9832-49ae-8077-d39135f29f31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516620910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1516620910
Directory /workspace/9.rom_ctrl_stress_all/latest
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