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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.67 100.00 98.28 97.30 98.37


Total test records in report: 462
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T299 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1155854242 Jul 09 05:41:15 PM PDT 24 Jul 09 05:41:29 PM PDT 24 13839916708 ps
T300 /workspace/coverage/default/44.rom_ctrl_stress_all.2948557908 Jul 09 05:41:36 PM PDT 24 Jul 09 05:41:59 PM PDT 24 4385033515 ps
T301 /workspace/coverage/default/2.rom_ctrl_alert_test.2104511764 Jul 09 05:40:54 PM PDT 24 Jul 09 05:41:08 PM PDT 24 6962407717 ps
T55 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1353014038 Jul 09 05:41:13 PM PDT 24 Jul 09 06:14:08 PM PDT 24 52952142038 ps
T302 /workspace/coverage/default/42.rom_ctrl_smoke.1088548563 Jul 09 05:41:34 PM PDT 24 Jul 09 05:42:05 PM PDT 24 5409392118 ps
T303 /workspace/coverage/default/9.rom_ctrl_smoke.2669599832 Jul 09 05:41:03 PM PDT 24 Jul 09 05:41:18 PM PDT 24 930219646 ps
T304 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2383363158 Jul 09 05:40:49 PM PDT 24 Jul 09 05:45:29 PM PDT 24 84483176103 ps
T305 /workspace/coverage/default/22.rom_ctrl_alert_test.4148594753 Jul 09 05:41:06 PM PDT 24 Jul 09 05:41:16 PM PDT 24 795093327 ps
T306 /workspace/coverage/default/15.rom_ctrl_alert_test.4024576619 Jul 09 05:41:06 PM PDT 24 Jul 09 05:41:13 PM PDT 24 167164001 ps
T307 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3561712563 Jul 09 05:41:34 PM PDT 24 Jul 09 05:41:44 PM PDT 24 168398842 ps
T308 /workspace/coverage/default/14.rom_ctrl_smoke.3177806135 Jul 09 05:41:04 PM PDT 24 Jul 09 05:41:33 PM PDT 24 2318436294 ps
T309 /workspace/coverage/default/25.rom_ctrl_alert_test.2872191840 Jul 09 05:41:12 PM PDT 24 Jul 09 05:41:18 PM PDT 24 199999583 ps
T31 /workspace/coverage/default/3.rom_ctrl_sec_cm.1246391409 Jul 09 05:40:50 PM PDT 24 Jul 09 05:41:51 PM PDT 24 6273296244 ps
T310 /workspace/coverage/default/26.rom_ctrl_stress_all.1632505902 Jul 09 05:41:38 PM PDT 24 Jul 09 05:42:56 PM PDT 24 23070418570 ps
T311 /workspace/coverage/default/14.rom_ctrl_stress_all.2507480920 Jul 09 05:40:59 PM PDT 24 Jul 09 05:41:21 PM PDT 24 2983562053 ps
T312 /workspace/coverage/default/5.rom_ctrl_alert_test.2306813589 Jul 09 05:40:53 PM PDT 24 Jul 09 05:41:08 PM PDT 24 6663064379 ps
T313 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2378123440 Jul 09 05:40:51 PM PDT 24 Jul 09 05:41:07 PM PDT 24 5438277110 ps
T314 /workspace/coverage/default/15.rom_ctrl_stress_all.3501118825 Jul 09 05:41:02 PM PDT 24 Jul 09 05:41:16 PM PDT 24 2681081511 ps
T315 /workspace/coverage/default/19.rom_ctrl_smoke.3634302074 Jul 09 05:41:05 PM PDT 24 Jul 09 05:41:31 PM PDT 24 3541321031 ps
T316 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4013943831 Jul 09 05:41:04 PM PDT 24 Jul 09 05:44:10 PM PDT 24 50039161981 ps
T317 /workspace/coverage/default/1.rom_ctrl_stress_all.4098242485 Jul 09 05:40:50 PM PDT 24 Jul 09 05:41:58 PM PDT 24 8305536655 ps
T318 /workspace/coverage/default/27.rom_ctrl_smoke.1389643896 Jul 09 05:41:16 PM PDT 24 Jul 09 05:41:33 PM PDT 24 1200894384 ps
T319 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3792080311 Jul 09 05:40:58 PM PDT 24 Jul 09 05:44:42 PM PDT 24 21341037326 ps
T320 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1991625142 Jul 09 05:41:37 PM PDT 24 Jul 09 05:41:44 PM PDT 24 138067397 ps
T321 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.52247771 Jul 09 05:45:57 PM PDT 24 Jul 09 05:51:13 PM PDT 24 28761418938 ps
T322 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1109173010 Jul 09 05:40:46 PM PDT 24 Jul 09 05:44:44 PM PDT 24 71033576814 ps
T323 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.515278784 Jul 09 05:41:00 PM PDT 24 Jul 09 05:41:24 PM PDT 24 34233560440 ps
T324 /workspace/coverage/default/37.rom_ctrl_smoke.1998815892 Jul 09 05:41:26 PM PDT 24 Jul 09 05:41:51 PM PDT 24 2148963898 ps
T325 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3620941742 Jul 09 05:41:21 PM PDT 24 Jul 09 05:41:41 PM PDT 24 1465859478 ps
T326 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2459158365 Jul 09 05:41:09 PM PDT 24 Jul 09 05:41:15 PM PDT 24 220619684 ps
T327 /workspace/coverage/default/43.rom_ctrl_stress_all.714205006 Jul 09 05:41:40 PM PDT 24 Jul 09 05:42:30 PM PDT 24 15579236627 ps
T328 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4278951182 Jul 09 05:40:59 PM PDT 24 Jul 09 05:41:05 PM PDT 24 280279393 ps
T329 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3696136308 Jul 09 05:41:46 PM PDT 24 Jul 09 05:41:56 PM PDT 24 2444538515 ps
T330 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3551229809 Jul 09 05:41:32 PM PDT 24 Jul 09 05:47:51 PM PDT 24 296054366698 ps
T331 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.423583165 Jul 09 05:41:33 PM PDT 24 Jul 09 05:41:57 PM PDT 24 9211837255 ps
T332 /workspace/coverage/default/29.rom_ctrl_stress_all.1122626003 Jul 09 05:41:39 PM PDT 24 Jul 09 05:41:56 PM PDT 24 1993140172 ps
T333 /workspace/coverage/default/3.rom_ctrl_stress_all.2218287425 Jul 09 05:40:56 PM PDT 24 Jul 09 05:41:13 PM PDT 24 612598996 ps
T334 /workspace/coverage/default/27.rom_ctrl_alert_test.4208967284 Jul 09 05:41:17 PM PDT 24 Jul 09 05:41:26 PM PDT 24 1628739295 ps
T335 /workspace/coverage/default/16.rom_ctrl_alert_test.3812005548 Jul 09 05:41:01 PM PDT 24 Jul 09 05:41:06 PM PDT 24 332786224 ps
T336 /workspace/coverage/default/20.rom_ctrl_alert_test.3050111254 Jul 09 05:41:07 PM PDT 24 Jul 09 05:41:13 PM PDT 24 751890749 ps
T337 /workspace/coverage/default/35.rom_ctrl_smoke.4166864550 Jul 09 05:41:27 PM PDT 24 Jul 09 05:41:38 PM PDT 24 567157413 ps
T338 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2037407688 Jul 09 05:41:04 PM PDT 24 Jul 09 05:46:37 PM PDT 24 139361140959 ps
T339 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1887701515 Jul 09 05:41:42 PM PDT 24 Jul 09 06:48:46 PM PDT 24 406564235645 ps
T340 /workspace/coverage/default/45.rom_ctrl_stress_all.3227462240 Jul 09 05:41:37 PM PDT 24 Jul 09 05:42:15 PM PDT 24 14426484116 ps
T341 /workspace/coverage/default/26.rom_ctrl_smoke.2358368541 Jul 09 05:41:22 PM PDT 24 Jul 09 05:41:33 PM PDT 24 695612969 ps
T342 /workspace/coverage/default/32.rom_ctrl_alert_test.4214801589 Jul 09 05:41:36 PM PDT 24 Jul 09 05:41:41 PM PDT 24 309187074 ps
T343 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1029822465 Jul 09 05:41:08 PM PDT 24 Jul 09 07:05:29 PM PDT 24 55623634979 ps
T344 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1958541628 Jul 09 05:41:37 PM PDT 24 Jul 09 05:42:08 PM PDT 24 3402201733 ps
T345 /workspace/coverage/default/37.rom_ctrl_alert_test.2706949254 Jul 09 05:41:26 PM PDT 24 Jul 09 05:41:43 PM PDT 24 9005908056 ps
T346 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.608298139 Jul 09 05:41:24 PM PDT 24 Jul 09 05:41:35 PM PDT 24 638995020 ps
T347 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2206141904 Jul 09 05:41:34 PM PDT 24 Jul 09 05:41:45 PM PDT 24 834744272 ps
T348 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2176675140 Jul 09 05:41:30 PM PDT 24 Jul 09 05:41:54 PM PDT 24 9942753399 ps
T349 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3362243785 Jul 09 05:41:25 PM PDT 24 Jul 09 05:42:00 PM PDT 24 17024951867 ps
T350 /workspace/coverage/default/2.rom_ctrl_stress_all.4084020809 Jul 09 05:40:56 PM PDT 24 Jul 09 05:41:21 PM PDT 24 3850037439 ps
T351 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1748634862 Jul 09 05:41:13 PM PDT 24 Jul 09 05:48:12 PM PDT 24 45709133382 ps
T352 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.431229800 Jul 09 05:41:15 PM PDT 24 Jul 09 05:41:32 PM PDT 24 5262859504 ps
T353 /workspace/coverage/default/49.rom_ctrl_stress_all.3406348405 Jul 09 05:41:38 PM PDT 24 Jul 09 05:41:53 PM PDT 24 1862754565 ps
T354 /workspace/coverage/default/38.rom_ctrl_smoke.2444353313 Jul 09 05:41:30 PM PDT 24 Jul 09 05:41:41 PM PDT 24 824364503 ps
T355 /workspace/coverage/default/13.rom_ctrl_smoke.1705279845 Jul 09 05:40:57 PM PDT 24 Jul 09 05:41:08 PM PDT 24 192457950 ps
T356 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2042652402 Jul 09 05:40:57 PM PDT 24 Jul 09 05:43:10 PM PDT 24 84075933267 ps
T357 /workspace/coverage/default/3.rom_ctrl_smoke.860966740 Jul 09 05:40:53 PM PDT 24 Jul 09 05:41:25 PM PDT 24 13048419550 ps
T358 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2338467759 Jul 09 05:41:37 PM PDT 24 Jul 09 05:41:47 PM PDT 24 2659258129 ps
T359 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3889596636 Jul 09 05:41:09 PM PDT 24 Jul 09 06:56:19 PM PDT 24 26136702419 ps
T360 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.977849007 Jul 09 05:40:53 PM PDT 24 Jul 09 05:41:15 PM PDT 24 8199144504 ps
T361 /workspace/coverage/default/30.rom_ctrl_smoke.1746416138 Jul 09 05:41:17 PM PDT 24 Jul 09 05:41:28 PM PDT 24 215612061 ps
T362 /workspace/coverage/default/7.rom_ctrl_smoke.2414557111 Jul 09 05:40:50 PM PDT 24 Jul 09 05:41:17 PM PDT 24 11004644223 ps
T363 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1226841567 Jul 09 05:41:32 PM PDT 24 Jul 09 05:41:44 PM PDT 24 1984623233 ps
T60 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3853651561 Jul 09 05:41:48 PM PDT 24 Jul 09 05:41:53 PM PDT 24 138129261 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2921436955 Jul 09 05:41:53 PM PDT 24 Jul 09 05:41:58 PM PDT 24 830159096 ps
T57 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1300022958 Jul 09 05:42:04 PM PDT 24 Jul 09 05:42:47 PM PDT 24 4775274048 ps
T61 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3018559912 Jul 09 05:42:12 PM PDT 24 Jul 09 05:43:41 PM PDT 24 10228757038 ps
T58 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2589285770 Jul 09 05:42:01 PM PDT 24 Jul 09 05:42:40 PM PDT 24 324565584 ps
T66 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2754968560 Jul 09 05:42:00 PM PDT 24 Jul 09 05:43:12 PM PDT 24 14840905082 ps
T59 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.467656981 Jul 09 05:41:58 PM PDT 24 Jul 09 05:43:15 PM PDT 24 1639723848 ps
T365 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3235656653 Jul 09 05:42:04 PM PDT 24 Jul 09 05:42:20 PM PDT 24 7282961070 ps
T95 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2709525691 Jul 09 05:42:07 PM PDT 24 Jul 09 05:42:20 PM PDT 24 1917221658 ps
T103 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1865303686 Jul 09 05:42:01 PM PDT 24 Jul 09 05:43:19 PM PDT 24 17354235644 ps
T96 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.486369818 Jul 09 05:41:51 PM PDT 24 Jul 09 05:42:08 PM PDT 24 19374727770 ps
T366 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2029810421 Jul 09 05:41:46 PM PDT 24 Jul 09 05:42:01 PM PDT 24 3539556709 ps
T367 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2882360239 Jul 09 05:41:54 PM PDT 24 Jul 09 05:42:01 PM PDT 24 179627864 ps
T368 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.424353575 Jul 09 05:42:03 PM PDT 24 Jul 09 05:42:19 PM PDT 24 1783941658 ps
T67 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1945808660 Jul 09 05:42:01 PM PDT 24 Jul 09 05:42:12 PM PDT 24 995266629 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.751110258 Jul 09 05:41:47 PM PDT 24 Jul 09 05:41:53 PM PDT 24 136569928 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2838845251 Jul 09 05:41:50 PM PDT 24 Jul 09 05:41:57 PM PDT 24 446505713 ps
T97 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.675784740 Jul 09 05:42:04 PM PDT 24 Jul 09 05:42:21 PM PDT 24 4340328439 ps
T98 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1602598403 Jul 09 05:41:42 PM PDT 24 Jul 09 05:41:56 PM PDT 24 5328731196 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2442906130 Jul 09 05:41:57 PM PDT 24 Jul 09 05:42:11 PM PDT 24 6082065702 ps
T69 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1585890267 Jul 09 05:41:54 PM PDT 24 Jul 09 05:42:37 PM PDT 24 5310509393 ps
T371 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2455751575 Jul 09 05:42:04 PM PDT 24 Jul 09 05:42:19 PM PDT 24 1004071375 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2794466804 Jul 09 05:41:45 PM PDT 24 Jul 09 05:41:54 PM PDT 24 677719985 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4012572619 Jul 09 05:41:45 PM PDT 24 Jul 09 05:41:56 PM PDT 24 4127952753 ps
T104 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3763630557 Jul 09 05:42:06 PM PDT 24 Jul 09 05:43:25 PM PDT 24 4139327132 ps
T70 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2913260650 Jul 09 05:42:00 PM PDT 24 Jul 09 05:42:20 PM PDT 24 716823426 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1569118360 Jul 09 05:41:50 PM PDT 24 Jul 09 05:42:07 PM PDT 24 1627612048 ps
T110 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.913395433 Jul 09 05:41:55 PM PDT 24 Jul 09 05:43:14 PM PDT 24 4146580835 ps
T375 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.417972563 Jul 09 05:41:57 PM PDT 24 Jul 09 05:42:14 PM PDT 24 2190478794 ps
T71 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1577140380 Jul 09 05:42:00 PM PDT 24 Jul 09 05:42:14 PM PDT 24 25136082397 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.762148090 Jul 09 05:41:47 PM PDT 24 Jul 09 05:42:00 PM PDT 24 910164254 ps
T72 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1618452146 Jul 09 05:41:54 PM PDT 24 Jul 09 05:42:07 PM PDT 24 1357368695 ps
T377 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.935855719 Jul 09 05:42:02 PM PDT 24 Jul 09 05:42:13 PM PDT 24 1000983445 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.458498703 Jul 09 05:45:25 PM PDT 24 Jul 09 05:45:36 PM PDT 24 1622013704 ps
T74 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3873822224 Jul 09 05:42:00 PM PDT 24 Jul 09 05:42:16 PM PDT 24 6985493340 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2315773757 Jul 09 05:41:48 PM PDT 24 Jul 09 05:41:55 PM PDT 24 370887968 ps
T378 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.614182606 Jul 09 05:42:00 PM PDT 24 Jul 09 05:42:14 PM PDT 24 5019046040 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3189932862 Jul 09 05:41:49 PM PDT 24 Jul 09 05:41:58 PM PDT 24 3074886474 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2833148034 Jul 09 05:41:45 PM PDT 24 Jul 09 05:41:57 PM PDT 24 5742160206 ps
T381 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4293074981 Jul 09 05:41:48 PM PDT 24 Jul 09 05:42:03 PM PDT 24 1346271324 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2478980046 Jul 09 05:41:42 PM PDT 24 Jul 09 05:41:57 PM PDT 24 2672859053 ps
T83 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1839785325 Jul 09 05:41:59 PM PDT 24 Jul 09 05:42:16 PM PDT 24 8700167404 ps
T84 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2616642667 Jul 09 05:41:55 PM PDT 24 Jul 09 05:42:56 PM PDT 24 5374101708 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2871459807 Jul 09 05:42:00 PM PDT 24 Jul 09 05:42:09 PM PDT 24 1717840822 ps
T384 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1294324058 Jul 09 05:42:00 PM PDT 24 Jul 09 05:42:15 PM PDT 24 12939966184 ps
T107 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2386177746 Jul 09 05:42:12 PM PDT 24 Jul 09 05:43:30 PM PDT 24 1924417482 ps
T108 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3871802032 Jul 09 05:41:55 PM PDT 24 Jul 09 05:43:13 PM PDT 24 6497393827 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3170656723 Jul 09 05:41:41 PM PDT 24 Jul 09 05:42:32 PM PDT 24 10860548282 ps
T94 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1514639844 Jul 09 05:41:57 PM PDT 24 Jul 09 05:42:08 PM PDT 24 1854308851 ps
T86 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2404777472 Jul 09 05:42:01 PM PDT 24 Jul 09 05:43:34 PM PDT 24 56001818455 ps
T386 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.689130356 Jul 09 05:41:59 PM PDT 24 Jul 09 05:42:15 PM PDT 24 5322463109 ps
T113 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3161345583 Jul 09 05:41:52 PM PDT 24 Jul 09 05:42:39 PM PDT 24 5493222949 ps
T387 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3002770565 Jul 09 05:42:05 PM PDT 24 Jul 09 05:42:12 PM PDT 24 269868214 ps
T388 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3078927087 Jul 09 05:42:04 PM PDT 24 Jul 09 05:42:24 PM PDT 24 8651123089 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4257907950 Jul 09 05:41:53 PM PDT 24 Jul 09 05:42:07 PM PDT 24 6246057441 ps
T105 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.790471793 Jul 09 05:41:42 PM PDT 24 Jul 09 05:42:26 PM PDT 24 5404686948 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.307701590 Jul 09 05:41:50 PM PDT 24 Jul 09 05:42:03 PM PDT 24 1594643213 ps
T99 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3922035321 Jul 09 05:42:04 PM PDT 24 Jul 09 05:42:14 PM PDT 24 1482319606 ps
T391 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.396625354 Jul 09 05:42:03 PM PDT 24 Jul 09 05:42:08 PM PDT 24 209982530 ps
T392 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.835400864 Jul 09 05:41:54 PM PDT 24 Jul 09 05:41:59 PM PDT 24 96660580 ps
T393 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3359890281 Jul 09 05:42:00 PM PDT 24 Jul 09 05:42:20 PM PDT 24 7576042155 ps
T100 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3660130330 Jul 09 05:42:01 PM PDT 24 Jul 09 05:42:14 PM PDT 24 2377414360 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3784353492 Jul 09 05:41:49 PM PDT 24 Jul 09 05:42:00 PM PDT 24 9262433838 ps
T90 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3221255966 Jul 09 05:41:58 PM PDT 24 Jul 09 05:43:09 PM PDT 24 26737672636 ps
T91 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3009350406 Jul 09 05:42:04 PM PDT 24 Jul 09 05:42:09 PM PDT 24 321127733 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2140551152 Jul 09 05:41:51 PM PDT 24 Jul 09 05:42:07 PM PDT 24 2075411351 ps
T396 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.930086629 Jul 09 05:41:58 PM PDT 24 Jul 09 05:42:14 PM PDT 24 1938195222 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1362087715 Jul 09 05:41:51 PM PDT 24 Jul 09 05:42:00 PM PDT 24 643418476 ps
T398 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3221806275 Jul 09 05:42:00 PM PDT 24 Jul 09 05:42:08 PM PDT 24 2032940445 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2971739761 Jul 09 05:41:53 PM PDT 24 Jul 09 05:42:12 PM PDT 24 1336892944 ps
T400 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1227938433 Jul 09 05:42:06 PM PDT 24 Jul 09 05:42:13 PM PDT 24 334953426 ps
T401 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2661572182 Jul 09 05:42:03 PM PDT 24 Jul 09 05:42:15 PM PDT 24 3956046251 ps
T111 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1921282553 Jul 09 05:41:53 PM PDT 24 Jul 09 05:42:40 PM PDT 24 3374810321 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1416455997 Jul 09 05:41:49 PM PDT 24 Jul 09 05:41:53 PM PDT 24 347133962 ps
T92 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1198395897 Jul 09 05:41:52 PM PDT 24 Jul 09 05:41:57 PM PDT 24 1181470365 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1738353275 Jul 09 05:41:44 PM PDT 24 Jul 09 05:41:52 PM PDT 24 1989530889 ps
T404 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1752083103 Jul 09 05:42:04 PM PDT 24 Jul 09 05:42:11 PM PDT 24 1198530710 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.233106597 Jul 09 05:41:53 PM PDT 24 Jul 09 05:42:05 PM PDT 24 10713691095 ps
T109 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3291840036 Jul 09 05:41:56 PM PDT 24 Jul 09 05:43:15 PM PDT 24 2017582153 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3770469921 Jul 09 05:41:48 PM PDT 24 Jul 09 05:41:54 PM PDT 24 255379536 ps
T87 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1368265921 Jul 09 05:41:47 PM PDT 24 Jul 09 05:41:55 PM PDT 24 3785435580 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1713731643 Jul 09 05:41:51 PM PDT 24 Jul 09 05:41:56 PM PDT 24 87567643 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.408765684 Jul 09 05:42:02 PM PDT 24 Jul 09 05:42:16 PM PDT 24 9033870288 ps
T409 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1536281165 Jul 09 05:41:56 PM PDT 24 Jul 09 05:42:03 PM PDT 24 168470736 ps
T410 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3953571435 Jul 09 05:41:54 PM PDT 24 Jul 09 05:42:01 PM PDT 24 333783431 ps
T411 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1683403317 Jul 09 05:41:57 PM PDT 24 Jul 09 05:42:11 PM PDT 24 6440805131 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1955070115 Jul 09 05:41:42 PM PDT 24 Jul 09 05:41:47 PM PDT 24 691243278 ps
T102 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1517454792 Jul 09 05:41:50 PM PDT 24 Jul 09 05:42:48 PM PDT 24 18741351531 ps
T413 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1316763860 Jul 09 05:42:01 PM PDT 24 Jul 09 05:42:16 PM PDT 24 1578519275 ps
T414 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3695819979 Jul 09 05:41:55 PM PDT 24 Jul 09 05:42:04 PM PDT 24 1371052894 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2893163692 Jul 09 05:41:48 PM PDT 24 Jul 09 05:42:59 PM PDT 24 2668778046 ps
T416 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3290685830 Jul 09 05:42:01 PM PDT 24 Jul 09 05:42:23 PM PDT 24 4112804007 ps
T417 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2484364214 Jul 09 05:41:54 PM PDT 24 Jul 09 05:42:05 PM PDT 24 4153697429 ps
T418 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1093209058 Jul 09 05:41:52 PM PDT 24 Jul 09 05:42:09 PM PDT 24 1918952497 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.190456818 Jul 09 05:41:48 PM PDT 24 Jul 09 05:42:17 PM PDT 24 9384870422 ps
T419 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3483001399 Jul 09 05:41:56 PM PDT 24 Jul 09 05:43:07 PM PDT 24 1395328019 ps
T420 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3930525407 Jul 09 05:42:02 PM PDT 24 Jul 09 05:42:07 PM PDT 24 347416146 ps
T421 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1779831408 Jul 09 05:41:54 PM PDT 24 Jul 09 05:42:06 PM PDT 24 4645903319 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3705113346 Jul 09 05:41:51 PM PDT 24 Jul 09 05:42:05 PM PDT 24 14122024316 ps
T423 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2403935448 Jul 09 05:42:07 PM PDT 24 Jul 09 05:42:19 PM PDT 24 7439985637 ps
T424 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1589649118 Jul 09 05:42:01 PM PDT 24 Jul 09 05:42:21 PM PDT 24 1942647359 ps
T425 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1932330473 Jul 09 05:42:04 PM PDT 24 Jul 09 05:43:21 PM PDT 24 112760512751 ps
T426 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4046891780 Jul 09 05:41:41 PM PDT 24 Jul 09 05:41:52 PM PDT 24 3921703280 ps
T427 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2342790846 Jul 09 05:42:03 PM PDT 24 Jul 09 05:42:13 PM PDT 24 3466774950 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1007814337 Jul 09 05:41:42 PM PDT 24 Jul 09 05:42:01 PM PDT 24 381192283 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1369663305 Jul 09 05:41:51 PM PDT 24 Jul 09 05:42:06 PM PDT 24 6792462426 ps
T114 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1512131472 Jul 09 05:42:12 PM PDT 24 Jul 09 05:43:24 PM PDT 24 611295777 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3111898396 Jul 09 05:41:53 PM PDT 24 Jul 09 05:42:03 PM PDT 24 3194302806 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3809607831 Jul 09 05:41:53 PM PDT 24 Jul 09 05:42:11 PM PDT 24 4079208399 ps
T432 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4043931301 Jul 09 05:41:47 PM PDT 24 Jul 09 05:42:01 PM PDT 24 5093909287 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1070628950 Jul 09 05:41:42 PM PDT 24 Jul 09 05:41:52 PM PDT 24 2873218733 ps
T434 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3924914656 Jul 09 05:42:05 PM PDT 24 Jul 09 05:42:24 PM PDT 24 5155802473 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.729397699 Jul 09 05:41:46 PM PDT 24 Jul 09 05:42:00 PM PDT 24 2860824398 ps
T436 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4049837197 Jul 09 05:42:05 PM PDT 24 Jul 09 05:42:11 PM PDT 24 552243498 ps
T437 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3867832798 Jul 09 05:42:07 PM PDT 24 Jul 09 05:42:20 PM PDT 24 1064175597 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.968052877 Jul 09 05:41:43 PM PDT 24 Jul 09 05:42:03 PM PDT 24 9222068529 ps
T439 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2828531063 Jul 09 05:41:58 PM PDT 24 Jul 09 05:42:07 PM PDT 24 3390648553 ps
T440 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.325478093 Jul 09 05:41:55 PM PDT 24 Jul 09 05:42:15 PM PDT 24 384550566 ps
T441 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.360482240 Jul 09 05:41:58 PM PDT 24 Jul 09 05:42:15 PM PDT 24 4092841074 ps
T442 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.778298825 Jul 09 05:41:58 PM PDT 24 Jul 09 05:42:12 PM PDT 24 1176981661 ps
T112 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.565350705 Jul 09 05:41:51 PM PDT 24 Jul 09 05:43:03 PM PDT 24 6147305322 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1249765701 Jul 09 05:41:49 PM PDT 24 Jul 09 05:42:01 PM PDT 24 1209605054 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2859671797 Jul 09 05:41:45 PM PDT 24 Jul 09 05:42:30 PM PDT 24 1595268645 ps
T88 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2099146356 Jul 09 05:42:01 PM PDT 24 Jul 09 05:43:09 PM PDT 24 16387024504 ps
T85 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3298322448 Jul 09 05:42:06 PM PDT 24 Jul 09 05:42:10 PM PDT 24 828805277 ps
T445 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2599283281 Jul 09 05:41:57 PM PDT 24 Jul 09 05:43:44 PM PDT 24 53528104023 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1245796958 Jul 09 05:41:47 PM PDT 24 Jul 09 05:42:36 PM PDT 24 34343473568 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.481449438 Jul 09 05:41:50 PM PDT 24 Jul 09 05:42:06 PM PDT 24 2076818612 ps
T448 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.462492823 Jul 09 05:41:57 PM PDT 24 Jul 09 05:42:07 PM PDT 24 1933784420 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.509679354 Jul 09 05:42:02 PM PDT 24 Jul 09 05:42:08 PM PDT 24 689930904 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1637770872 Jul 09 05:42:00 PM PDT 24 Jul 09 05:43:18 PM PDT 24 3302705218 ps
T450 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1283471724 Jul 09 05:42:00 PM PDT 24 Jul 09 05:42:16 PM PDT 24 1965036055 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3027634399 Jul 09 05:41:42 PM PDT 24 Jul 09 05:41:55 PM PDT 24 1396248760 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1290265111 Jul 09 05:41:50 PM PDT 24 Jul 09 05:42:02 PM PDT 24 724333413 ps
T453 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1235520145 Jul 09 05:41:57 PM PDT 24 Jul 09 05:42:54 PM PDT 24 26805444901 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2455569397 Jul 09 05:41:50 PM PDT 24 Jul 09 05:41:55 PM PDT 24 921239310 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3165247650 Jul 09 05:41:51 PM PDT 24 Jul 09 05:41:56 PM PDT 24 462988604 ps
T455 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1989191699 Jul 09 05:41:58 PM PDT 24 Jul 09 05:42:12 PM PDT 24 1708521218 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.685466595 Jul 09 05:41:50 PM PDT 24 Jul 09 05:42:09 PM PDT 24 2687675406 ps
T457 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.94324787 Jul 09 05:41:54 PM PDT 24 Jul 09 05:42:01 PM PDT 24 267497480 ps
T458 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1168715315 Jul 09 05:41:50 PM PDT 24 Jul 09 05:41:55 PM PDT 24 85550739 ps
T459 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1777026093 Jul 09 05:41:50 PM PDT 24 Jul 09 05:42:16 PM PDT 24 1774781536 ps
T460 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2489653320 Jul 09 05:41:55 PM PDT 24 Jul 09 05:42:00 PM PDT 24 90706087 ps
T461 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3479620023 Jul 09 05:41:57 PM PDT 24 Jul 09 05:42:25 PM PDT 24 1502904228 ps
T462 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.926159206 Jul 09 05:41:53 PM PDT 24 Jul 09 05:42:31 PM PDT 24 335227872 ps

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3734597232
Short name T4
Test name
Test status
Simulation time 715184216 ps
CPU time 10.19 seconds
Started Jul 09 05:41:03 PM PDT 24
Finished Jul 09 05:41:15 PM PDT 24
Peak memory 213404 kb
Host smart-a79df7f3-1f43-4f7c-a376-414a70a4b56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734597232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3734597232
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.853999042
Short name T12
Test name
Test status
Simulation time 661228808721 ps
CPU time 3275.44 seconds
Started Jul 09 05:41:00 PM PDT 24
Finished Jul 09 06:35:37 PM PDT 24
Peak memory 244260 kb
Host smart-edb88612-acb8-4e87-a05a-715314220a3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853999042 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.853999042
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1619199546
Short name T18
Test name
Test status
Simulation time 105863107964 ps
CPU time 286.26 seconds
Started Jul 09 05:41:33 PM PDT 24
Finished Jul 09 05:46:20 PM PDT 24
Peak memory 237764 kb
Host smart-eb20eb70-26a0-4bb4-88d0-2fdbc63c2655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619199546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1619199546
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.421632753
Short name T11
Test name
Test status
Simulation time 7661043539 ps
CPU time 15.84 seconds
Started Jul 09 05:41:40 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 211440 kb
Host smart-766ea9ab-cd6b-4c64-8ebf-0d32edb0bb61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421632753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.421632753
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1865303686
Short name T103
Test name
Test status
Simulation time 17354235644 ps
CPU time 76.78 seconds
Started Jul 09 05:42:01 PM PDT 24
Finished Jul 09 05:43:19 PM PDT 24
Peak memory 219064 kb
Host smart-26d942f9-ec30-41cf-aaea-0d55d23851e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865303686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1865303686
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3998698602
Short name T22
Test name
Test status
Simulation time 2980804631 ps
CPU time 54.4 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:41:41 PM PDT 24
Peak memory 236940 kb
Host smart-87967120-e97e-4e4d-ab41-00259e1d3f07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998698602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3998698602
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2838845251
Short name T68
Test name
Test status
Simulation time 446505713 ps
CPU time 6.1 seconds
Started Jul 09 05:41:50 PM PDT 24
Finished Jul 09 05:41:57 PM PDT 24
Peak memory 210712 kb
Host smart-48fd09fb-8bed-4832-8bd3-8de0dd11a657
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838845251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2838845251
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.4023545581
Short name T14
Test name
Test status
Simulation time 30654291574 ps
CPU time 9295.77 seconds
Started Jul 09 05:41:18 PM PDT 24
Finished Jul 09 08:16:15 PM PDT 24
Peak memory 228740 kb
Host smart-ce84a0cd-266f-44a1-8c8b-2d6ae6373f82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023545581 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.4023545581
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.790471793
Short name T105
Test name
Test status
Simulation time 5404686948 ps
CPU time 43.88 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 05:42:26 PM PDT 24
Peak memory 212536 kb
Host smart-c8149cba-24e6-41be-a89f-78f7648b4071
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790471793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.790471793
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.565350705
Short name T112
Test name
Test status
Simulation time 6147305322 ps
CPU time 71.09 seconds
Started Jul 09 05:41:51 PM PDT 24
Finished Jul 09 05:43:03 PM PDT 24
Peak memory 218960 kb
Host smart-73bdd85e-e6ad-41e6-b6aa-63a3fd05e117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565350705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.565350705
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3705835997
Short name T2
Test name
Test status
Simulation time 18074452319 ps
CPU time 15.26 seconds
Started Jul 09 05:41:36 PM PDT 24
Finished Jul 09 05:41:51 PM PDT 24
Peak memory 211368 kb
Host smart-70a9afb9-c481-4501-a5fc-7428c3291e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705835997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3705835997
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3895751879
Short name T41
Test name
Test status
Simulation time 46872936867 ps
CPU time 305.4 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:45:57 PM PDT 24
Peak memory 235320 kb
Host smart-bd472686-b8c6-4497-8a7f-6bc2911df71b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895751879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3895751879
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3369048696
Short name T8
Test name
Test status
Simulation time 693690179 ps
CPU time 9.79 seconds
Started Jul 09 05:41:03 PM PDT 24
Finished Jul 09 05:41:13 PM PDT 24
Peak memory 211996 kb
Host smart-4e36a928-48f3-464e-811a-424139613f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369048696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3369048696
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1989208189
Short name T32
Test name
Test status
Simulation time 3557010214 ps
CPU time 29.55 seconds
Started Jul 09 05:41:04 PM PDT 24
Finished Jul 09 05:41:35 PM PDT 24
Peak memory 211972 kb
Host smart-e39f9a7b-f804-4f82-bed1-98e2a95df301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989208189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1989208189
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3221255966
Short name T90
Test name
Test status
Simulation time 26737672636 ps
CPU time 70.31 seconds
Started Jul 09 05:41:58 PM PDT 24
Finished Jul 09 05:43:09 PM PDT 24
Peak memory 210744 kb
Host smart-44f9eba1-fbc1-4990-9c3d-33bd78f75fcd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221255966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3221255966
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2094096484
Short name T130
Test name
Test status
Simulation time 3711077357 ps
CPU time 67.18 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:42:02 PM PDT 24
Peak memory 212648 kb
Host smart-79214eab-612e-4186-a58d-19f23d44358e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094096484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2094096484
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1602598403
Short name T98
Test name
Test status
Simulation time 5328731196 ps
CPU time 12.57 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 210904 kb
Host smart-2131f8dc-6030-40de-bc29-3987dbec31b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602598403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1602598403
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3139417129
Short name T80
Test name
Test status
Simulation time 27014402513 ps
CPU time 23.72 seconds
Started Jul 09 05:40:51 PM PDT 24
Finished Jul 09 05:41:16 PM PDT 24
Peak memory 213936 kb
Host smart-0a0c8969-ec8a-466d-bae9-3636ca5ab1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139417129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3139417129
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4046891780
Short name T426
Test name
Test status
Simulation time 3921703280 ps
CPU time 10.2 seconds
Started Jul 09 05:41:41 PM PDT 24
Finished Jul 09 05:41:52 PM PDT 24
Peak memory 218556 kb
Host smart-93f9d145-55ca-4648-b5cd-8fc9378ad37a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046891780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4046891780
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2833148034
Short name T380
Test name
Test status
Simulation time 5742160206 ps
CPU time 11.87 seconds
Started Jul 09 05:41:45 PM PDT 24
Finished Jul 09 05:41:57 PM PDT 24
Peak memory 218840 kb
Host smart-280480c9-5bad-4513-a915-8757d84aeb99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833148034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2833148034
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.968052877
Short name T438
Test name
Test status
Simulation time 9222068529 ps
CPU time 18.7 seconds
Started Jul 09 05:41:43 PM PDT 24
Finished Jul 09 05:42:03 PM PDT 24
Peak memory 218924 kb
Host smart-a78a126f-b23c-425c-b0f1-c710777ef7b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968052877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.968052877
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1738353275
Short name T403
Test name
Test status
Simulation time 1989530889 ps
CPU time 7.6 seconds
Started Jul 09 05:41:44 PM PDT 24
Finished Jul 09 05:41:52 PM PDT 24
Peak memory 218964 kb
Host smart-41c120c0-117a-4507-9112-ad57310e5f06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738353275 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1738353275
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3027634399
Short name T451
Test name
Test status
Simulation time 1396248760 ps
CPU time 12.56 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 05:41:55 PM PDT 24
Peak memory 218840 kb
Host smart-d1c7b502-1af6-4a28-bbec-e50f97933b35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027634399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3027634399
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1070628950
Short name T433
Test name
Test status
Simulation time 2873218733 ps
CPU time 8.55 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 05:41:52 PM PDT 24
Peak memory 210672 kb
Host smart-af420801-e269-4c26-8dfb-683f278c9c88
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070628950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1070628950
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1955070115
Short name T412
Test name
Test status
Simulation time 691243278 ps
CPU time 4.29 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 05:41:47 PM PDT 24
Peak memory 210628 kb
Host smart-8aefd9af-6cac-49b6-96e6-aacd87a300bc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955070115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1955070115
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3170656723
Short name T385
Test name
Test status
Simulation time 10860548282 ps
CPU time 50.34 seconds
Started Jul 09 05:41:41 PM PDT 24
Finished Jul 09 05:42:32 PM PDT 24
Peak memory 210788 kb
Host smart-43537267-9266-446b-aa29-4e27d64d6421
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170656723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3170656723
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2478980046
Short name T382
Test name
Test status
Simulation time 2672859053 ps
CPU time 14.35 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 05:41:57 PM PDT 24
Peak memory 219096 kb
Host smart-f4f8dc2d-f77c-4448-bdbd-11f6d3d6c232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478980046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2478980046
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1368265921
Short name T87
Test name
Test status
Simulation time 3785435580 ps
CPU time 7.72 seconds
Started Jul 09 05:41:47 PM PDT 24
Finished Jul 09 05:41:55 PM PDT 24
Peak memory 217936 kb
Host smart-99f04935-54f9-4529-85e1-bbf258a6a7f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368265921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1368265921
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4257907950
Short name T389
Test name
Test status
Simulation time 6246057441 ps
CPU time 13.7 seconds
Started Jul 09 05:41:53 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 211100 kb
Host smart-ffd5cdb9-ec66-4109-8589-d164c5a98fee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257907950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4257907950
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4043931301
Short name T432
Test name
Test status
Simulation time 5093909287 ps
CPU time 13.82 seconds
Started Jul 09 05:41:47 PM PDT 24
Finished Jul 09 05:42:01 PM PDT 24
Peak memory 210856 kb
Host smart-272de6a6-8d15-44a8-a6c4-c9485e612cb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043931301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4043931301
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4012572619
Short name T373
Test name
Test status
Simulation time 4127952753 ps
CPU time 10.54 seconds
Started Jul 09 05:41:45 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 219052 kb
Host smart-02739dac-1291-4b48-ae03-1fe53a337af3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012572619 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4012572619
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2315773757
Short name T82
Test name
Test status
Simulation time 370887968 ps
CPU time 6.87 seconds
Started Jul 09 05:41:48 PM PDT 24
Finished Jul 09 05:41:55 PM PDT 24
Peak memory 210776 kb
Host smart-e708db21-5134-4745-99c1-4d638faac404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315773757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2315773757
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2029810421
Short name T366
Test name
Test status
Simulation time 3539556709 ps
CPU time 14.35 seconds
Started Jul 09 05:41:46 PM PDT 24
Finished Jul 09 05:42:01 PM PDT 24
Peak memory 210692 kb
Host smart-d1484d4c-82bd-437e-921b-b9ed8bda1fab
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029810421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2029810421
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2921436955
Short name T364
Test name
Test status
Simulation time 830159096 ps
CPU time 4.16 seconds
Started Jul 09 05:41:53 PM PDT 24
Finished Jul 09 05:41:58 PM PDT 24
Peak memory 210612 kb
Host smart-5b778ab9-1b29-4bac-a154-3854b2c1a65b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921436955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2921436955
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1007814337
Short name T428
Test name
Test status
Simulation time 381192283 ps
CPU time 18.49 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 05:42:01 PM PDT 24
Peak memory 210800 kb
Host smart-3757b7a9-db75-4ef2-9b0f-c1461931f4ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007814337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1007814337
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.486369818
Short name T96
Test name
Test status
Simulation time 19374727770 ps
CPU time 16.47 seconds
Started Jul 09 05:41:51 PM PDT 24
Finished Jul 09 05:42:08 PM PDT 24
Peak memory 211312 kb
Host smart-00b264e3-7db9-4aa8-9124-04e504358bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486369818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.486369818
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.762148090
Short name T376
Test name
Test status
Simulation time 910164254 ps
CPU time 12.71 seconds
Started Jul 09 05:41:47 PM PDT 24
Finished Jul 09 05:42:00 PM PDT 24
Peak memory 219012 kb
Host smart-8bb1a4d2-2a38-4827-9042-ec55cbf5ecd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762148090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.762148090
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2859671797
Short name T444
Test name
Test status
Simulation time 1595268645 ps
CPU time 44.54 seconds
Started Jul 09 05:41:45 PM PDT 24
Finished Jul 09 05:42:30 PM PDT 24
Peak memory 218968 kb
Host smart-94897475-f49b-4fec-ad5f-b0410ab6bc3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859671797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2859671797
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.417972563
Short name T375
Test name
Test status
Simulation time 2190478794 ps
CPU time 16.82 seconds
Started Jul 09 05:41:57 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 219000 kb
Host smart-23b6c495-87be-45ef-858d-9ab3375a91bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417972563 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.417972563
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1514639844
Short name T94
Test name
Test status
Simulation time 1854308851 ps
CPU time 9.48 seconds
Started Jul 09 05:41:57 PM PDT 24
Finished Jul 09 05:42:08 PM PDT 24
Peak memory 210800 kb
Host smart-c7c965ec-435a-4e73-80df-93727b3ba308
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514639844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1514639844
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.930086629
Short name T396
Test name
Test status
Simulation time 1938195222 ps
CPU time 15.29 seconds
Started Jul 09 05:41:58 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 218912 kb
Host smart-29012795-0730-47eb-99c0-c2d68e87c951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930086629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.930086629
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.689130356
Short name T386
Test name
Test status
Simulation time 5322463109 ps
CPU time 14.65 seconds
Started Jul 09 05:41:59 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 219068 kb
Host smart-dc7e5bc1-4ad3-4ed7-aa2d-3748f204796d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689130356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.689130356
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.926159206
Short name T462
Test name
Test status
Simulation time 335227872 ps
CPU time 37.02 seconds
Started Jul 09 05:41:53 PM PDT 24
Finished Jul 09 05:42:31 PM PDT 24
Peak memory 218952 kb
Host smart-13e138b4-42f4-4805-b107-8611263533f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926159206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.926159206
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2442906130
Short name T370
Test name
Test status
Simulation time 6082065702 ps
CPU time 13.4 seconds
Started Jul 09 05:41:57 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 219060 kb
Host smart-edd2012d-44a9-4535-849a-c5a8b84f2505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442906130 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2442906130
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1989191699
Short name T455
Test name
Test status
Simulation time 1708521218 ps
CPU time 13.66 seconds
Started Jul 09 05:41:58 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 218812 kb
Host smart-a1301389-cf65-4634-a204-604788c81041
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989191699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1989191699
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1235520145
Short name T453
Test name
Test status
Simulation time 26805444901 ps
CPU time 57.49 seconds
Started Jul 09 05:41:57 PM PDT 24
Finished Jul 09 05:42:54 PM PDT 24
Peak memory 210768 kb
Host smart-a7665f59-96cf-4638-bece-da4ba6093f40
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235520145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1235520145
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1683403317
Short name T411
Test name
Test status
Simulation time 6440805131 ps
CPU time 12.66 seconds
Started Jul 09 05:41:57 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 219040 kb
Host smart-c88c4f80-4a19-46b9-804d-bfaf31c06736
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683403317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1683403317
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1536281165
Short name T409
Test name
Test status
Simulation time 168470736 ps
CPU time 6.44 seconds
Started Jul 09 05:41:56 PM PDT 24
Finished Jul 09 05:42:03 PM PDT 24
Peak memory 219040 kb
Host smart-cf87c11c-f933-4229-b497-1449aee7c016
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536281165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1536281165
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3483001399
Short name T419
Test name
Test status
Simulation time 1395328019 ps
CPU time 70.64 seconds
Started Jul 09 05:41:56 PM PDT 24
Finished Jul 09 05:43:07 PM PDT 24
Peak memory 212168 kb
Host smart-52191f54-180f-41db-ae2f-d99747c0da1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483001399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3483001399
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1316763860
Short name T413
Test name
Test status
Simulation time 1578519275 ps
CPU time 13.6 seconds
Started Jul 09 05:42:01 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 219048 kb
Host smart-81f9b155-b49b-472b-b95a-3ea429062951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316763860 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1316763860
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1839785325
Short name T83
Test name
Test status
Simulation time 8700167404 ps
CPU time 16.46 seconds
Started Jul 09 05:41:59 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 210792 kb
Host smart-9db1c055-a39b-4493-9faf-35b6fff61fe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839785325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1839785325
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2599283281
Short name T445
Test name
Test status
Simulation time 53528104023 ps
CPU time 106.4 seconds
Started Jul 09 05:41:57 PM PDT 24
Finished Jul 09 05:43:44 PM PDT 24
Peak memory 210868 kb
Host smart-8e9c63fc-19cf-44c8-8189-1ad18d927db9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599283281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2599283281
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3660130330
Short name T100
Test name
Test status
Simulation time 2377414360 ps
CPU time 11.6 seconds
Started Jul 09 05:42:01 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 210800 kb
Host smart-63286f23-45de-42a3-a968-529a7cf0b7d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660130330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3660130330
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.778298825
Short name T442
Test name
Test status
Simulation time 1176981661 ps
CPU time 13.4 seconds
Started Jul 09 05:41:58 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 218984 kb
Host smart-ee9ddf55-d8dc-4b33-b148-25d52caffd25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778298825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.778298825
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.467656981
Short name T59
Test name
Test status
Simulation time 1639723848 ps
CPU time 76.54 seconds
Started Jul 09 05:41:58 PM PDT 24
Finished Jul 09 05:43:15 PM PDT 24
Peak memory 212232 kb
Host smart-148af3fa-271a-4cdd-8f8a-e5870c790afd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467656981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.467656981
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1294324058
Short name T384
Test name
Test status
Simulation time 12939966184 ps
CPU time 14.01 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 219100 kb
Host smart-9578e937-efa7-4c4d-b840-f550ef774d99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294324058 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1294324058
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1577140380
Short name T71
Test name
Test status
Simulation time 25136082397 ps
CPU time 13.55 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 210712 kb
Host smart-7d07f08d-8751-405f-9c75-de191f775b75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577140380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1577140380
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2099146356
Short name T88
Test name
Test status
Simulation time 16387024504 ps
CPU time 67.03 seconds
Started Jul 09 05:42:01 PM PDT 24
Finished Jul 09 05:43:09 PM PDT 24
Peak memory 211716 kb
Host smart-a00ddc3c-2d46-4894-858d-495dbbe19ff9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099146356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2099146356
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2661572182
Short name T401
Test name
Test status
Simulation time 3956046251 ps
CPU time 10.76 seconds
Started Jul 09 05:42:03 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 210896 kb
Host smart-a893d108-077f-41a0-a14e-673a42485168
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661572182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2661572182
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3290685830
Short name T416
Test name
Test status
Simulation time 4112804007 ps
CPU time 20.28 seconds
Started Jul 09 05:42:01 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 219036 kb
Host smart-dcd2fac7-53ca-4354-a9c4-70f70506c4d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290685830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3290685830
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3221806275
Short name T398
Test name
Test status
Simulation time 2032940445 ps
CPU time 8.01 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:42:08 PM PDT 24
Peak memory 219000 kb
Host smart-0dfc72ac-f267-44e4-a999-f39f64924a72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221806275 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3221806275
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1945808660
Short name T67
Test name
Test status
Simulation time 995266629 ps
CPU time 10.09 seconds
Started Jul 09 05:42:01 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 210788 kb
Host smart-82144222-dc9f-43d2-bf76-a151f1a65d49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945808660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1945808660
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2913260650
Short name T70
Test name
Test status
Simulation time 716823426 ps
CPU time 18.58 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:42:20 PM PDT 24
Peak memory 210796 kb
Host smart-dbe9bbe0-c4a0-47e9-bc18-c7cde05e050f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913260650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2913260650
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.408765684
Short name T408
Test name
Test status
Simulation time 9033870288 ps
CPU time 13.29 seconds
Started Jul 09 05:42:02 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 211096 kb
Host smart-f95a478c-ce7c-482d-91c0-4b37eeeb308f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408765684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.408765684
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1589649118
Short name T424
Test name
Test status
Simulation time 1942647359 ps
CPU time 19.29 seconds
Started Jul 09 05:42:01 PM PDT 24
Finished Jul 09 05:42:21 PM PDT 24
Peak memory 219028 kb
Host smart-0f7eaf97-1efa-4f99-98fe-0190edcf0c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589649118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1589649118
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1637770872
Short name T106
Test name
Test status
Simulation time 3302705218 ps
CPU time 76.79 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:43:18 PM PDT 24
Peak memory 212396 kb
Host smart-719ad07d-b902-40d5-aa1e-ef43edd36622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637770872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1637770872
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2871459807
Short name T383
Test name
Test status
Simulation time 1717840822 ps
CPU time 7.63 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:42:09 PM PDT 24
Peak memory 218932 kb
Host smart-b6ed5d58-4f78-47e1-81e4-183579bea609
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871459807 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2871459807
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.396625354
Short name T391
Test name
Test status
Simulation time 209982530 ps
CPU time 4.21 seconds
Started Jul 09 05:42:03 PM PDT 24
Finished Jul 09 05:42:08 PM PDT 24
Peak memory 210704 kb
Host smart-ce6f61ea-0d6c-4447-9c31-d3b1fd2b2d38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396625354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.396625354
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2404777472
Short name T86
Test name
Test status
Simulation time 56001818455 ps
CPU time 92.26 seconds
Started Jul 09 05:42:01 PM PDT 24
Finished Jul 09 05:43:34 PM PDT 24
Peak memory 210740 kb
Host smart-76f367ad-572c-4881-ad8c-a1f2d8940112
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404777472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2404777472
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3930525407
Short name T420
Test name
Test status
Simulation time 347416146 ps
CPU time 4.27 seconds
Started Jul 09 05:42:02 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 218360 kb
Host smart-59c3e7a1-d4c9-46da-b0a4-eee064e01031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930525407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3930525407
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.509679354
Short name T449
Test name
Test status
Simulation time 689930904 ps
CPU time 6.01 seconds
Started Jul 09 05:42:02 PM PDT 24
Finished Jul 09 05:42:08 PM PDT 24
Peak memory 219012 kb
Host smart-4a788b5a-5e16-44f1-9e81-abb7d873c14d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509679354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.509679354
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2589285770
Short name T58
Test name
Test status
Simulation time 324565584 ps
CPU time 38.23 seconds
Started Jul 09 05:42:01 PM PDT 24
Finished Jul 09 05:42:40 PM PDT 24
Peak memory 211148 kb
Host smart-0f1ee6b8-c66a-4b3f-98e4-620602c68934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589285770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2589285770
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.935855719
Short name T377
Test name
Test status
Simulation time 1000983445 ps
CPU time 10.93 seconds
Started Jul 09 05:42:02 PM PDT 24
Finished Jul 09 05:42:13 PM PDT 24
Peak memory 218900 kb
Host smart-af92bdf3-4336-49c5-9a79-461e2f674474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935855719 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.935855719
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3009350406
Short name T91
Test name
Test status
Simulation time 321127733 ps
CPU time 4.34 seconds
Started Jul 09 05:42:04 PM PDT 24
Finished Jul 09 05:42:09 PM PDT 24
Peak memory 210540 kb
Host smart-9f624dca-fbfa-4559-bcfa-769153b52193
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009350406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3009350406
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2754968560
Short name T66
Test name
Test status
Simulation time 14840905082 ps
CPU time 71.36 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:43:12 PM PDT 24
Peak memory 210748 kb
Host smart-74473064-638b-46b6-90f6-f811ea697c79
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754968560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2754968560
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1283471724
Short name T450
Test name
Test status
Simulation time 1965036055 ps
CPU time 15.39 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 218848 kb
Host smart-2b76349e-50e7-483b-8661-2fa14f4242e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283471724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1283471724
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.424353575
Short name T368
Test name
Test status
Simulation time 1783941658 ps
CPU time 15.7 seconds
Started Jul 09 05:42:03 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 219004 kb
Host smart-ae7a09f2-cfdf-48de-b033-176551ef7730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424353575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.424353575
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1300022958
Short name T57
Test name
Test status
Simulation time 4775274048 ps
CPU time 42.21 seconds
Started Jul 09 05:42:04 PM PDT 24
Finished Jul 09 05:42:47 PM PDT 24
Peak memory 218884 kb
Host smart-9b44ed74-56db-4efe-9401-29ae90cd1702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300022958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1300022958
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4049837197
Short name T436
Test name
Test status
Simulation time 552243498 ps
CPU time 5.39 seconds
Started Jul 09 05:42:05 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 219008 kb
Host smart-fc064ea8-aea3-4596-9220-5c3ced721d12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049837197 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4049837197
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3922035321
Short name T99
Test name
Test status
Simulation time 1482319606 ps
CPU time 8.88 seconds
Started Jul 09 05:42:04 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 218852 kb
Host smart-5752e90c-0e75-4825-9e94-ef4521dcc888
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922035321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3922035321
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1932330473
Short name T425
Test name
Test status
Simulation time 112760512751 ps
CPU time 76.68 seconds
Started Jul 09 05:42:04 PM PDT 24
Finished Jul 09 05:43:21 PM PDT 24
Peak memory 210808 kb
Host smart-fd74649e-9af6-4bfe-9239-fda92fe9c309
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932330473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1932330473
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2403935448
Short name T423
Test name
Test status
Simulation time 7439985637 ps
CPU time 11.26 seconds
Started Jul 09 05:42:07 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 210904 kb
Host smart-5ac7bf2a-2400-4894-91dd-24898629661b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403935448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2403935448
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3078927087
Short name T388
Test name
Test status
Simulation time 8651123089 ps
CPU time 20.12 seconds
Started Jul 09 05:42:04 PM PDT 24
Finished Jul 09 05:42:24 PM PDT 24
Peak memory 219068 kb
Host smart-83d97f60-bd36-4c5e-80e3-d98b33508b79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078927087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3078927087
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2386177746
Short name T107
Test name
Test status
Simulation time 1924417482 ps
CPU time 78.13 seconds
Started Jul 09 05:42:12 PM PDT 24
Finished Jul 09 05:43:30 PM PDT 24
Peak memory 218980 kb
Host smart-1efd5a9d-2724-457f-b64f-22a9538195f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386177746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2386177746
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3235656653
Short name T365
Test name
Test status
Simulation time 7282961070 ps
CPU time 14.62 seconds
Started Jul 09 05:42:04 PM PDT 24
Finished Jul 09 05:42:20 PM PDT 24
Peak memory 219128 kb
Host smart-e6fbe554-f4b7-414a-a665-94525989b435
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235656653 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3235656653
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3298322448
Short name T85
Test name
Test status
Simulation time 828805277 ps
CPU time 4.27 seconds
Started Jul 09 05:42:06 PM PDT 24
Finished Jul 09 05:42:10 PM PDT 24
Peak memory 217300 kb
Host smart-41c972ea-d843-46e8-8d8c-42ea659f35d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298322448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3298322448
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3018559912
Short name T61
Test name
Test status
Simulation time 10228757038 ps
CPU time 89.03 seconds
Started Jul 09 05:42:12 PM PDT 24
Finished Jul 09 05:43:41 PM PDT 24
Peak memory 210812 kb
Host smart-284a5396-4825-4a90-99b7-60ed4c2512b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018559912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3018559912
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2342790846
Short name T427
Test name
Test status
Simulation time 3466774950 ps
CPU time 9.67 seconds
Started Jul 09 05:42:03 PM PDT 24
Finished Jul 09 05:42:13 PM PDT 24
Peak memory 210924 kb
Host smart-6db90514-4989-47e4-a2cc-a8527fc17159
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342790846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2342790846
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2455751575
Short name T371
Test name
Test status
Simulation time 1004071375 ps
CPU time 13.64 seconds
Started Jul 09 05:42:04 PM PDT 24
Finished Jul 09 05:42:19 PM PDT 24
Peak memory 214424 kb
Host smart-a7b7a9ac-3e92-4328-a762-39a88407948a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455751575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2455751575
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1512131472
Short name T114
Test name
Test status
Simulation time 611295777 ps
CPU time 71.76 seconds
Started Jul 09 05:42:12 PM PDT 24
Finished Jul 09 05:43:24 PM PDT 24
Peak memory 218944 kb
Host smart-8217763e-4797-4a01-ba37-c1649d1040f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512131472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1512131472
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3002770565
Short name T387
Test name
Test status
Simulation time 269868214 ps
CPU time 6.63 seconds
Started Jul 09 05:42:05 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 219032 kb
Host smart-3a7d4479-0879-4b8f-8094-3f7a3f4d49de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002770565 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3002770565
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1227938433
Short name T400
Test name
Test status
Simulation time 334953426 ps
CPU time 6.56 seconds
Started Jul 09 05:42:06 PM PDT 24
Finished Jul 09 05:42:13 PM PDT 24
Peak memory 217896 kb
Host smart-2d099988-98e8-4fe1-9144-1de53515b9fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227938433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1227938433
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3924914656
Short name T434
Test name
Test status
Simulation time 5155802473 ps
CPU time 18.88 seconds
Started Jul 09 05:42:05 PM PDT 24
Finished Jul 09 05:42:24 PM PDT 24
Peak memory 210860 kb
Host smart-5cbe0dc5-cb08-49c9-b38d-8267a03a9e83
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924914656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3924914656
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2709525691
Short name T95
Test name
Test status
Simulation time 1917221658 ps
CPU time 12.01 seconds
Started Jul 09 05:42:07 PM PDT 24
Finished Jul 09 05:42:20 PM PDT 24
Peak memory 210704 kb
Host smart-3a2a5134-ffc2-4745-bccf-860020809f91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709525691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2709525691
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3867832798
Short name T437
Test name
Test status
Simulation time 1064175597 ps
CPU time 12.96 seconds
Started Jul 09 05:42:07 PM PDT 24
Finished Jul 09 05:42:20 PM PDT 24
Peak memory 218920 kb
Host smart-6d39e43c-9cc7-43b2-aa8e-5cb60dcb2695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867832798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3867832798
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3763630557
Short name T104
Test name
Test status
Simulation time 4139327132 ps
CPU time 78.31 seconds
Started Jul 09 05:42:06 PM PDT 24
Finished Jul 09 05:43:25 PM PDT 24
Peak memory 218928 kb
Host smart-d51e8be4-6eeb-4719-bbb4-6c0e07fa51ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763630557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3763630557
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3784353492
Short name T394
Test name
Test status
Simulation time 9262433838 ps
CPU time 10.52 seconds
Started Jul 09 05:41:49 PM PDT 24
Finished Jul 09 05:42:00 PM PDT 24
Peak memory 218968 kb
Host smart-f6677a28-5885-43f3-bf69-ff92f5dfa945
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784353492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3784353492
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1290265111
Short name T452
Test name
Test status
Simulation time 724333413 ps
CPU time 11.85 seconds
Started Jul 09 05:41:50 PM PDT 24
Finished Jul 09 05:42:02 PM PDT 24
Peak memory 210656 kb
Host smart-734c15bc-8407-4f93-ab0a-feeafe202f76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290265111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1290265111
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2794466804
Short name T372
Test name
Test status
Simulation time 677719985 ps
CPU time 8.64 seconds
Started Jul 09 05:41:45 PM PDT 24
Finished Jul 09 05:41:54 PM PDT 24
Peak memory 219024 kb
Host smart-0fab4a9a-45de-46c3-afd6-40285c5c4d25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794466804 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2794466804
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3111898396
Short name T430
Test name
Test status
Simulation time 3194302806 ps
CPU time 10.08 seconds
Started Jul 09 05:41:53 PM PDT 24
Finished Jul 09 05:42:03 PM PDT 24
Peak memory 210776 kb
Host smart-8dc53450-c437-4497-b1d5-7e905c731025
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111898396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3111898396
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1416455997
Short name T402
Test name
Test status
Simulation time 347133962 ps
CPU time 4.1 seconds
Started Jul 09 05:41:49 PM PDT 24
Finished Jul 09 05:41:53 PM PDT 24
Peak memory 210660 kb
Host smart-60d99349-3320-42f4-8dfa-b49d9dee078f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416455997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1416455997
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.233106597
Short name T405
Test name
Test status
Simulation time 10713691095 ps
CPU time 11.69 seconds
Started Jul 09 05:41:53 PM PDT 24
Finished Jul 09 05:42:05 PM PDT 24
Peak memory 210932 kb
Host smart-57a597e7-fee1-419b-9138-884ef9b789a1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233106597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
233106597
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.190456818
Short name T93
Test name
Test status
Simulation time 9384870422 ps
CPU time 28.44 seconds
Started Jul 09 05:41:48 PM PDT 24
Finished Jul 09 05:42:17 PM PDT 24
Peak memory 210848 kb
Host smart-5775a6ad-4802-4a46-aba9-ebd1e500ecb7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190456818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.190456818
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.729397699
Short name T435
Test name
Test status
Simulation time 2860824398 ps
CPU time 12.8 seconds
Started Jul 09 05:41:46 PM PDT 24
Finished Jul 09 05:42:00 PM PDT 24
Peak memory 210796 kb
Host smart-f1e1edb3-c34b-4f3a-b071-c7d42dae3fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729397699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.729397699
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.751110258
Short name T369
Test name
Test status
Simulation time 136569928 ps
CPU time 6.09 seconds
Started Jul 09 05:41:47 PM PDT 24
Finished Jul 09 05:41:53 PM PDT 24
Peak memory 219012 kb
Host smart-43d90ff3-47b4-4efb-82ce-0c079580fea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751110258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.751110258
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2893163692
Short name T415
Test name
Test status
Simulation time 2668778046 ps
CPU time 70.98 seconds
Started Jul 09 05:41:48 PM PDT 24
Finished Jul 09 05:42:59 PM PDT 24
Peak memory 212444 kb
Host smart-fd164284-593e-43e0-81c6-d60395d731b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893163692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2893163692
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.458498703
Short name T73
Test name
Test status
Simulation time 1622013704 ps
CPU time 9.46 seconds
Started Jul 09 05:45:25 PM PDT 24
Finished Jul 09 05:45:36 PM PDT 24
Peak memory 218920 kb
Host smart-782bab81-279d-40ae-afe0-be9326454dfa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458498703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.458498703
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.481449438
Short name T447
Test name
Test status
Simulation time 2076818612 ps
CPU time 15.17 seconds
Started Jul 09 05:41:50 PM PDT 24
Finished Jul 09 05:42:06 PM PDT 24
Peak memory 217496 kb
Host smart-f6246d3b-82e7-4bb7-8b70-5ebb9095f849
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481449438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.481449438
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3705113346
Short name T422
Test name
Test status
Simulation time 14122024316 ps
CPU time 13.12 seconds
Started Jul 09 05:41:51 PM PDT 24
Finished Jul 09 05:42:05 PM PDT 24
Peak memory 218976 kb
Host smart-6b5593db-5794-4548-84a3-9b54559dda89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705113346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3705113346
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1369663305
Short name T429
Test name
Test status
Simulation time 6792462426 ps
CPU time 14.33 seconds
Started Jul 09 05:41:51 PM PDT 24
Finished Jul 09 05:42:06 PM PDT 24
Peak memory 219048 kb
Host smart-39d110f0-378a-488e-984c-5fc107d32fde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369663305 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1369663305
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1713731643
Short name T407
Test name
Test status
Simulation time 87567643 ps
CPU time 4.21 seconds
Started Jul 09 05:41:51 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 210768 kb
Host smart-32d07bca-c0d6-40e9-abe7-0ead75421c78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713731643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1713731643
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3189932862
Short name T379
Test name
Test status
Simulation time 3074886474 ps
CPU time 8.95 seconds
Started Jul 09 05:41:49 PM PDT 24
Finished Jul 09 05:41:58 PM PDT 24
Peak memory 210692 kb
Host smart-dcff22a8-b373-4243-adad-6f57d3ae72ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189932862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3189932862
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3770469921
Short name T406
Test name
Test status
Simulation time 255379536 ps
CPU time 5.98 seconds
Started Jul 09 05:41:48 PM PDT 24
Finished Jul 09 05:41:54 PM PDT 24
Peak memory 210660 kb
Host smart-ba2b3d9b-bfd8-45d6-914a-fa6669a74661
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770469921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3770469921
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2971739761
Short name T399
Test name
Test status
Simulation time 1336892944 ps
CPU time 18.9 seconds
Started Jul 09 05:41:53 PM PDT 24
Finished Jul 09 05:42:12 PM PDT 24
Peak memory 210784 kb
Host smart-563c71c6-3d48-47dc-a080-62502804b8a6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971739761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2971739761
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3853651561
Short name T60
Test name
Test status
Simulation time 138129261 ps
CPU time 4.26 seconds
Started Jul 09 05:41:48 PM PDT 24
Finished Jul 09 05:41:53 PM PDT 24
Peak memory 210772 kb
Host smart-f3cd18f1-adca-48ce-abfb-73aa30d1b16a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853651561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3853651561
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.307701590
Short name T390
Test name
Test status
Simulation time 1594643213 ps
CPU time 12.8 seconds
Started Jul 09 05:41:50 PM PDT 24
Finished Jul 09 05:42:03 PM PDT 24
Peak memory 218948 kb
Host smart-b7982c26-3076-4ca2-83a5-9cf6a2c0d07c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307701590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.307701590
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1245796958
Short name T446
Test name
Test status
Simulation time 34343473568 ps
CPU time 47.87 seconds
Started Jul 09 05:41:47 PM PDT 24
Finished Jul 09 05:42:36 PM PDT 24
Peak memory 218956 kb
Host smart-414faa05-bfa5-44a4-b46e-63c8fb2edca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245796958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1245796958
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3165247650
Short name T89
Test name
Test status
Simulation time 462988604 ps
CPU time 4.36 seconds
Started Jul 09 05:41:51 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 218040 kb
Host smart-97c83720-2f73-432f-bb1a-1833559be515
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165247650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3165247650
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3809607831
Short name T431
Test name
Test status
Simulation time 4079208399 ps
CPU time 17.3 seconds
Started Jul 09 05:41:53 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 210788 kb
Host smart-344d28d4-de3d-43ed-a2a5-b2fc032451de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809607831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3809607831
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1569118360
Short name T374
Test name
Test status
Simulation time 1627612048 ps
CPU time 16.76 seconds
Started Jul 09 05:41:50 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 210636 kb
Host smart-59d0e98a-7550-4940-b1a6-12b50b70bfb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569118360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1569118360
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1249765701
Short name T443
Test name
Test status
Simulation time 1209605054 ps
CPU time 11.26 seconds
Started Jul 09 05:41:49 PM PDT 24
Finished Jul 09 05:42:01 PM PDT 24
Peak memory 219084 kb
Host smart-9ff93f6f-c4da-4354-9239-82640b63c774
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249765701 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1249765701
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2140551152
Short name T395
Test name
Test status
Simulation time 2075411351 ps
CPU time 15.27 seconds
Started Jul 09 05:41:51 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 218812 kb
Host smart-2a1c6eac-89e0-46ba-8872-908c4a959088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140551152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2140551152
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2455569397
Short name T454
Test name
Test status
Simulation time 921239310 ps
CPU time 5.42 seconds
Started Jul 09 05:41:50 PM PDT 24
Finished Jul 09 05:41:55 PM PDT 24
Peak memory 210592 kb
Host smart-7ab82d05-8116-4978-b61f-e1df42929a77
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455569397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2455569397
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1168715315
Short name T458
Test name
Test status
Simulation time 85550739 ps
CPU time 4.22 seconds
Started Jul 09 05:41:50 PM PDT 24
Finished Jul 09 05:41:55 PM PDT 24
Peak memory 210632 kb
Host smart-28822c69-af68-4043-8ce2-7aa0a78b3bd9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168715315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1168715315
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1777026093
Short name T459
Test name
Test status
Simulation time 1774781536 ps
CPU time 24.69 seconds
Started Jul 09 05:41:50 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 210788 kb
Host smart-dbaf09fb-fad0-4502-880d-94ce8603ebe3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777026093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1777026093
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1362087715
Short name T397
Test name
Test status
Simulation time 643418476 ps
CPU time 8.41 seconds
Started Jul 09 05:41:51 PM PDT 24
Finished Jul 09 05:42:00 PM PDT 24
Peak memory 210628 kb
Host smart-9d5c821f-3660-4226-8e48-e5164c3a4b73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362087715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1362087715
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.685466595
Short name T456
Test name
Test status
Simulation time 2687675406 ps
CPU time 17.98 seconds
Started Jul 09 05:41:50 PM PDT 24
Finished Jul 09 05:42:09 PM PDT 24
Peak memory 219068 kb
Host smart-732c063b-75b8-41c9-b48d-1389d2b788d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685466595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.685466595
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.614182606
Short name T378
Test name
Test status
Simulation time 5019046040 ps
CPU time 12.67 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 219124 kb
Host smart-ab4daa9b-8906-48a7-bdfd-59afd4db1459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614182606 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.614182606
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1198395897
Short name T92
Test name
Test status
Simulation time 1181470365 ps
CPU time 4.31 seconds
Started Jul 09 05:41:52 PM PDT 24
Finished Jul 09 05:41:57 PM PDT 24
Peak memory 210720 kb
Host smart-0a96946f-fe74-4f46-9b3c-50d6aec33d20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198395897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1198395897
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1517454792
Short name T102
Test name
Test status
Simulation time 18741351531 ps
CPU time 57.66 seconds
Started Jul 09 05:41:50 PM PDT 24
Finished Jul 09 05:42:48 PM PDT 24
Peak memory 210940 kb
Host smart-460d024f-4ae3-4dfa-922e-167ab73785be
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517454792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1517454792
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3695819979
Short name T414
Test name
Test status
Simulation time 1371052894 ps
CPU time 8.28 seconds
Started Jul 09 05:41:55 PM PDT 24
Finished Jul 09 05:42:04 PM PDT 24
Peak memory 210828 kb
Host smart-7dd8d529-97a5-44e3-b114-6a9e504b5c37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695819979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3695819979
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4293074981
Short name T381
Test name
Test status
Simulation time 1346271324 ps
CPU time 14.12 seconds
Started Jul 09 05:41:48 PM PDT 24
Finished Jul 09 05:42:03 PM PDT 24
Peak memory 219044 kb
Host smart-3598e74b-81fd-45a1-aa07-98ce778eee24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293074981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4293074981
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3161345583
Short name T113
Test name
Test status
Simulation time 5493222949 ps
CPU time 46.78 seconds
Started Jul 09 05:41:52 PM PDT 24
Finished Jul 09 05:42:39 PM PDT 24
Peak memory 219072 kb
Host smart-d8ebf339-c762-4ef3-aed9-d7db554a8e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161345583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3161345583
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.94324787
Short name T457
Test name
Test status
Simulation time 267497480 ps
CPU time 7.02 seconds
Started Jul 09 05:41:54 PM PDT 24
Finished Jul 09 05:42:01 PM PDT 24
Peak memory 219080 kb
Host smart-8e1eb74f-8644-4d43-ba6f-c08d64284ed4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94324787 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.94324787
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2828531063
Short name T439
Test name
Test status
Simulation time 3390648553 ps
CPU time 8.81 seconds
Started Jul 09 05:41:58 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 218600 kb
Host smart-9cca4b33-640b-454d-819f-78b44bdb85ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828531063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2828531063
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.325478093
Short name T440
Test name
Test status
Simulation time 384550566 ps
CPU time 18.57 seconds
Started Jul 09 05:41:55 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 210796 kb
Host smart-0db8a15d-a8bf-4111-a653-c956965a72cf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325478093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.325478093
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.462492823
Short name T448
Test name
Test status
Simulation time 1933784420 ps
CPU time 9.65 seconds
Started Jul 09 05:41:57 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 218924 kb
Host smart-d0533389-e1bf-4e77-9782-9ab6a125ac4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462492823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.462492823
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.360482240
Short name T441
Test name
Test status
Simulation time 4092841074 ps
CPU time 17.1 seconds
Started Jul 09 05:41:58 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 218976 kb
Host smart-49d2f39b-a2f7-4368-915b-5eed9d06a574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360482240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.360482240
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1921282553
Short name T111
Test name
Test status
Simulation time 3374810321 ps
CPU time 46.04 seconds
Started Jul 09 05:41:53 PM PDT 24
Finished Jul 09 05:42:40 PM PDT 24
Peak memory 219088 kb
Host smart-723238f8-2cf3-41b9-8596-4a714c7a82fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921282553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1921282553
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2484364214
Short name T417
Test name
Test status
Simulation time 4153697429 ps
CPU time 10.46 seconds
Started Jul 09 05:41:54 PM PDT 24
Finished Jul 09 05:42:05 PM PDT 24
Peak memory 219028 kb
Host smart-8cd98cdc-4ae4-4d6c-8a55-42e91c5ebf3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484364214 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2484364214
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3873822224
Short name T74
Test name
Test status
Simulation time 6985493340 ps
CPU time 14.91 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 210832 kb
Host smart-1efc110d-a409-4ad8-b179-1484d0f76754
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873822224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3873822224
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1585890267
Short name T69
Test name
Test status
Simulation time 5310509393 ps
CPU time 41.97 seconds
Started Jul 09 05:41:54 PM PDT 24
Finished Jul 09 05:42:37 PM PDT 24
Peak memory 210808 kb
Host smart-585c3e37-02c1-49bf-b1d2-66f078983b6c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585890267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1585890267
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1618452146
Short name T72
Test name
Test status
Simulation time 1357368695 ps
CPU time 11.89 seconds
Started Jul 09 05:41:54 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 218968 kb
Host smart-11903d68-5c32-4b43-b57c-8955bb216e3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618452146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1618452146
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3359890281
Short name T393
Test name
Test status
Simulation time 7576042155 ps
CPU time 19 seconds
Started Jul 09 05:42:00 PM PDT 24
Finished Jul 09 05:42:20 PM PDT 24
Peak memory 219072 kb
Host smart-1b5a7869-1242-4a3c-9e37-bdfbe21ee845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359890281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3359890281
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3871802032
Short name T108
Test name
Test status
Simulation time 6497393827 ps
CPU time 76.79 seconds
Started Jul 09 05:41:55 PM PDT 24
Finished Jul 09 05:43:13 PM PDT 24
Peak memory 218956 kb
Host smart-d022e60d-50bb-497e-adb8-53922a7d123f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871802032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3871802032
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2882360239
Short name T367
Test name
Test status
Simulation time 179627864 ps
CPU time 6.16 seconds
Started Jul 09 05:41:54 PM PDT 24
Finished Jul 09 05:42:01 PM PDT 24
Peak memory 219040 kb
Host smart-592aace6-7b12-4b26-976b-b3b8aca58b5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882360239 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2882360239
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2489653320
Short name T460
Test name
Test status
Simulation time 90706087 ps
CPU time 4.21 seconds
Started Jul 09 05:41:55 PM PDT 24
Finished Jul 09 05:42:00 PM PDT 24
Peak memory 217444 kb
Host smart-97a5a75f-2308-4d5c-a764-e6dce0e39f27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489653320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2489653320
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2616642667
Short name T84
Test name
Test status
Simulation time 5374101708 ps
CPU time 60.35 seconds
Started Jul 09 05:41:55 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 210864 kb
Host smart-1ea68754-619e-4f7c-b668-0f968d5a58b5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616642667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2616642667
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.675784740
Short name T97
Test name
Test status
Simulation time 4340328439 ps
CPU time 16.95 seconds
Started Jul 09 05:42:04 PM PDT 24
Finished Jul 09 05:42:21 PM PDT 24
Peak memory 211016 kb
Host smart-f2397a7a-56df-4317-a274-a6aad1ea866f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675784740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.675784740
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3953571435
Short name T410
Test name
Test status
Simulation time 333783431 ps
CPU time 6.57 seconds
Started Jul 09 05:41:54 PM PDT 24
Finished Jul 09 05:42:01 PM PDT 24
Peak memory 219028 kb
Host smart-1bcb31dc-5d43-4e27-9de3-795f6e7381d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953571435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3953571435
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3291840036
Short name T109
Test name
Test status
Simulation time 2017582153 ps
CPU time 78.42 seconds
Started Jul 09 05:41:56 PM PDT 24
Finished Jul 09 05:43:15 PM PDT 24
Peak memory 219032 kb
Host smart-6217a66c-0d90-4520-a987-56e4508c0b5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291840036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3291840036
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.835400864
Short name T392
Test name
Test status
Simulation time 96660580 ps
CPU time 4.76 seconds
Started Jul 09 05:41:54 PM PDT 24
Finished Jul 09 05:41:59 PM PDT 24
Peak memory 218976 kb
Host smart-fb175d26-9116-42d3-be4e-3b807161eb66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835400864 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.835400864
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1779831408
Short name T421
Test name
Test status
Simulation time 4645903319 ps
CPU time 10.9 seconds
Started Jul 09 05:41:54 PM PDT 24
Finished Jul 09 05:42:06 PM PDT 24
Peak memory 210860 kb
Host smart-a4c9c668-18c9-4ee5-8c87-eee0a93f54e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779831408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1779831408
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3479620023
Short name T461
Test name
Test status
Simulation time 1502904228 ps
CPU time 27.64 seconds
Started Jul 09 05:41:57 PM PDT 24
Finished Jul 09 05:42:25 PM PDT 24
Peak memory 210680 kb
Host smart-a78c2f7e-f9dc-4922-861d-12305733a74a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479620023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3479620023
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1752083103
Short name T404
Test name
Test status
Simulation time 1198530710 ps
CPU time 6.2 seconds
Started Jul 09 05:42:04 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 218352 kb
Host smart-60124c3b-1551-4cfe-b9c4-67a1438190c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752083103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1752083103
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1093209058
Short name T418
Test name
Test status
Simulation time 1918952497 ps
CPU time 16.94 seconds
Started Jul 09 05:41:52 PM PDT 24
Finished Jul 09 05:42:09 PM PDT 24
Peak memory 219032 kb
Host smart-6fdd0ecb-026b-4eaf-a3a3-15e4ba49af78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093209058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1093209058
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.913395433
Short name T110
Test name
Test status
Simulation time 4146580835 ps
CPU time 78.25 seconds
Started Jul 09 05:41:55 PM PDT 24
Finished Jul 09 05:43:14 PM PDT 24
Peak memory 219012 kb
Host smart-d28b4432-653c-4997-bb42-6017ca86991c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913395433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.913395433
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3507978326
Short name T189
Test name
Test status
Simulation time 3701262276 ps
CPU time 16.46 seconds
Started Jul 09 05:40:47 PM PDT 24
Finished Jul 09 05:41:05 PM PDT 24
Peak memory 211392 kb
Host smart-2e7cc0d7-1080-4897-98d9-da3947d9e782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507978326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3507978326
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1109173010
Short name T322
Test name
Test status
Simulation time 71033576814 ps
CPU time 237.2 seconds
Started Jul 09 05:40:46 PM PDT 24
Finished Jul 09 05:44:44 PM PDT 24
Peak memory 236796 kb
Host smart-129e002d-6b5b-4dd8-846d-36a0e9802d77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109173010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1109173010
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3919975090
Short name T202
Test name
Test status
Simulation time 15024974388 ps
CPU time 30.51 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:41:25 PM PDT 24
Peak memory 212396 kb
Host smart-b0491b60-0fbc-4ec0-b3f0-7bf6572392e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919975090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3919975090
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3588837767
Short name T56
Test name
Test status
Simulation time 2709706776 ps
CPU time 9.91 seconds
Started Jul 09 05:40:48 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 211444 kb
Host smart-cb247fcc-4d6b-4c54-b24d-9ea4d1fd42bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588837767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3588837767
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2863674017
Short name T201
Test name
Test status
Simulation time 530366945 ps
CPU time 13.08 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:41:04 PM PDT 24
Peak memory 211284 kb
Host smart-a7092679-b602-4086-9d22-06721170e535
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863674017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2863674017
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1304412654
Short name T280
Test name
Test status
Simulation time 7351854291 ps
CPU time 14.86 seconds
Started Jul 09 05:40:47 PM PDT 24
Finished Jul 09 05:41:03 PM PDT 24
Peak memory 211360 kb
Host smart-ab0acde4-6815-4e9f-a7c6-dd110d613b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304412654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1304412654
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4195290109
Short name T227
Test name
Test status
Simulation time 994446891 ps
CPU time 14 seconds
Started Jul 09 05:40:57 PM PDT 24
Finished Jul 09 05:41:12 PM PDT 24
Peak memory 211980 kb
Host smart-916152ee-3ec4-4b41-acd1-eb29fc04191e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195290109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4195290109
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3696136308
Short name T329
Test name
Test status
Simulation time 2444538515 ps
CPU time 9.34 seconds
Started Jul 09 05:41:46 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 211368 kb
Host smart-ea1596f2-df13-494a-a84a-0d271b18ba0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3696136308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3696136308
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1733430523
Short name T24
Test name
Test status
Simulation time 964587439 ps
CPU time 102.53 seconds
Started Jul 09 05:40:51 PM PDT 24
Finished Jul 09 05:42:35 PM PDT 24
Peak memory 234032 kb
Host smart-4eeeb5d6-ffbe-4624-96d6-fac4a86c1588
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733430523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1733430523
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.898709927
Short name T252
Test name
Test status
Simulation time 191980076 ps
CPU time 10.13 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:06 PM PDT 24
Peak memory 213148 kb
Host smart-813afccd-5764-4222-8357-60faac512e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898709927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.898709927
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4098242485
Short name T317
Test name
Test status
Simulation time 8305536655 ps
CPU time 65.91 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:41:58 PM PDT 24
Peak memory 219424 kb
Host smart-2ea0a69e-1b77-4ea5-b8ba-843155564899
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098242485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4098242485
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2417060326
Short name T208
Test name
Test status
Simulation time 89123231 ps
CPU time 4.52 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:00 PM PDT 24
Peak memory 211320 kb
Host smart-4b1e7766-ebd9-4ef4-aa88-d63d30296162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417060326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2417060326
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.973458903
Short name T198
Test name
Test status
Simulation time 107331041419 ps
CPU time 408.7 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:47:44 PM PDT 24
Peak memory 235172 kb
Host smart-073d8786-c963-4610-ad84-a0db0da156e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973458903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.973458903
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.977849007
Short name T360
Test name
Test status
Simulation time 8199144504 ps
CPU time 21.06 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:41:15 PM PDT 24
Peak memory 214316 kb
Host smart-ea0a87b5-bc04-48c6-9be1-3e86e7c3b57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977849007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.977849007
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.288144477
Short name T247
Test name
Test status
Simulation time 1829460745 ps
CPU time 15.49 seconds
Started Jul 09 05:40:55 PM PDT 24
Finished Jul 09 05:41:12 PM PDT 24
Peak memory 211392 kb
Host smart-4f4890ec-83a6-4409-bbc6-91a7e1afac42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288144477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.288144477
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3912936303
Short name T35
Test name
Test status
Simulation time 13923245402 ps
CPU time 23.07 seconds
Started Jul 09 05:41:04 PM PDT 24
Finished Jul 09 05:41:28 PM PDT 24
Peak memory 214036 kb
Host smart-62671117-965a-47cf-a23f-d0edc490ec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912936303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3912936303
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1323155465
Short name T218
Test name
Test status
Simulation time 112812955 ps
CPU time 5.73 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:01 PM PDT 24
Peak memory 211332 kb
Host smart-f677c035-b764-4a4b-afb4-e8ac5ca74423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323155465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1323155465
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4294576398
Short name T151
Test name
Test status
Simulation time 2144593837 ps
CPU time 11.05 seconds
Started Jul 09 05:40:58 PM PDT 24
Finished Jul 09 05:41:11 PM PDT 24
Peak memory 211348 kb
Host smart-f9f2a991-5f7f-4554-ad3c-e6bef3c2b45f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294576398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4294576398
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3778015097
Short name T129
Test name
Test status
Simulation time 504931023 ps
CPU time 5.56 seconds
Started Jul 09 05:41:03 PM PDT 24
Finished Jul 09 05:41:09 PM PDT 24
Peak memory 211312 kb
Host smart-60a73b53-2925-4f3d-a475-8ea1ff58d4a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778015097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3778015097
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1376129229
Short name T78
Test name
Test status
Simulation time 6236011291 ps
CPU time 33.4 seconds
Started Jul 09 05:41:03 PM PDT 24
Finished Jul 09 05:41:37 PM PDT 24
Peak memory 214068 kb
Host smart-3e0a436b-d71a-4fa4-aa72-f626b738e73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376129229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1376129229
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3296341889
Short name T138
Test name
Test status
Simulation time 4770387907 ps
CPU time 20.64 seconds
Started Jul 09 05:40:59 PM PDT 24
Finished Jul 09 05:41:21 PM PDT 24
Peak memory 213564 kb
Host smart-7efaf27b-a530-4532-a10c-83542da337cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296341889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3296341889
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1118776407
Short name T51
Test name
Test status
Simulation time 34232796346 ps
CPU time 1384.4 seconds
Started Jul 09 05:45:03 PM PDT 24
Finished Jul 09 06:08:09 PM PDT 24
Peak memory 235896 kb
Host smart-f2202e56-ae75-4ed1-b230-75938f5c8f1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118776407 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1118776407
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2954919870
Short name T62
Test name
Test status
Simulation time 346714799 ps
CPU time 4.16 seconds
Started Jul 09 05:40:56 PM PDT 24
Finished Jul 09 05:41:01 PM PDT 24
Peak memory 211356 kb
Host smart-5e5193f6-b602-450b-bb2f-42dd00679066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954919870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2954919870
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.753490876
Short name T43
Test name
Test status
Simulation time 10179194633 ps
CPU time 139.31 seconds
Started Jul 09 05:41:02 PM PDT 24
Finished Jul 09 05:43:22 PM PDT 24
Peak memory 227776 kb
Host smart-ed987a6d-9c05-4b66-85bd-cd2e92672ff0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753490876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.753490876
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4097213808
Short name T236
Test name
Test status
Simulation time 19686289945 ps
CPU time 32.41 seconds
Started Jul 09 05:41:01 PM PDT 24
Finished Jul 09 05:41:34 PM PDT 24
Peak memory 212196 kb
Host smart-7d7b36af-84f9-4057-93b0-be52f90ab870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097213808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4097213808
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1849503173
Short name T141
Test name
Test status
Simulation time 1352654925 ps
CPU time 7.73 seconds
Started Jul 09 05:40:59 PM PDT 24
Finished Jul 09 05:41:07 PM PDT 24
Peak memory 211452 kb
Host smart-b9fd6782-4592-4233-8e1e-1bf4cf2ca8cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849503173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1849503173
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4249938984
Short name T248
Test name
Test status
Simulation time 9394666177 ps
CPU time 25.09 seconds
Started Jul 09 05:41:00 PM PDT 24
Finished Jul 09 05:41:26 PM PDT 24
Peak memory 213996 kb
Host smart-9a4ea373-57b9-4e3b-b8fc-51113ddedbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249938984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4249938984
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3718264604
Short name T242
Test name
Test status
Simulation time 1567487002 ps
CPU time 13.13 seconds
Started Jul 09 05:40:58 PM PDT 24
Finished Jul 09 05:41:11 PM PDT 24
Peak memory 211336 kb
Host smart-cfa98342-3ed4-42e7-828f-627bceb89ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718264604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3718264604
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1529632948
Short name T44
Test name
Test status
Simulation time 36579650891 ps
CPU time 234.83 seconds
Started Jul 09 05:40:59 PM PDT 24
Finished Jul 09 05:44:55 PM PDT 24
Peak memory 233748 kb
Host smart-92f0699d-180b-4fad-9c22-2823d6f8caff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529632948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1529632948
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.515278784
Short name T323
Test name
Test status
Simulation time 34233560440 ps
CPU time 23 seconds
Started Jul 09 05:41:00 PM PDT 24
Finished Jul 09 05:41:24 PM PDT 24
Peak memory 212184 kb
Host smart-011f6460-0161-4477-8e99-b1677658921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515278784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.515278784
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1376093583
Short name T123
Test name
Test status
Simulation time 532531133 ps
CPU time 7.22 seconds
Started Jul 09 05:41:03 PM PDT 24
Finished Jul 09 05:41:11 PM PDT 24
Peak memory 211396 kb
Host smart-782d1fba-2859-4216-99b1-df5456f4ac8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376093583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1376093583
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1705279845
Short name T355
Test name
Test status
Simulation time 192457950 ps
CPU time 10.18 seconds
Started Jul 09 05:40:57 PM PDT 24
Finished Jul 09 05:41:08 PM PDT 24
Peak memory 213412 kb
Host smart-dc01ca97-e8c2-4de4-80f8-9952ddba0ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705279845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1705279845
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1146384494
Short name T216
Test name
Test status
Simulation time 9630090377 ps
CPU time 85.85 seconds
Started Jul 09 05:41:00 PM PDT 24
Finished Jul 09 05:42:26 PM PDT 24
Peak memory 216112 kb
Host smart-949576de-a49c-4a2d-b217-0f0b336c9166
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146384494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1146384494
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2720837758
Short name T255
Test name
Test status
Simulation time 3098667322 ps
CPU time 9.02 seconds
Started Jul 09 05:41:03 PM PDT 24
Finished Jul 09 05:41:14 PM PDT 24
Peak memory 211412 kb
Host smart-501a925e-00b4-4b39-9e3d-2e8fb60cd109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720837758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2720837758
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3995051562
Short name T122
Test name
Test status
Simulation time 2228533743 ps
CPU time 52.39 seconds
Started Jul 09 05:40:59 PM PDT 24
Finished Jul 09 05:41:53 PM PDT 24
Peak memory 228268 kb
Host smart-d3c73c05-0952-4cf7-9dee-76c9eeef748b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995051562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3995051562
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1437912580
Short name T231
Test name
Test status
Simulation time 2368273472 ps
CPU time 9.81 seconds
Started Jul 09 05:40:57 PM PDT 24
Finished Jul 09 05:41:07 PM PDT 24
Peak memory 212072 kb
Host smart-047045b5-5b83-4136-b886-15f39e81ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437912580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1437912580
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3177806135
Short name T308
Test name
Test status
Simulation time 2318436294 ps
CPU time 27.66 seconds
Started Jul 09 05:41:04 PM PDT 24
Finished Jul 09 05:41:33 PM PDT 24
Peak memory 214028 kb
Host smart-61386acb-00ab-453e-b9d7-372cb72f4943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177806135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3177806135
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2507480920
Short name T311
Test name
Test status
Simulation time 2983562053 ps
CPU time 20.86 seconds
Started Jul 09 05:40:59 PM PDT 24
Finished Jul 09 05:41:21 PM PDT 24
Peak memory 214068 kb
Host smart-fe4df2ca-a214-46aa-9584-df156391be79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507480920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2507480920
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4024576619
Short name T306
Test name
Test status
Simulation time 167164001 ps
CPU time 5.35 seconds
Started Jul 09 05:41:06 PM PDT 24
Finished Jul 09 05:41:13 PM PDT 24
Peak memory 211268 kb
Host smart-ace071b5-dd94-424c-a23c-217a1a874199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024576619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4024576619
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2037407688
Short name T338
Test name
Test status
Simulation time 139361140959 ps
CPU time 332.04 seconds
Started Jul 09 05:41:04 PM PDT 24
Finished Jul 09 05:46:37 PM PDT 24
Peak memory 236948 kb
Host smart-3a4bbb82-f85d-4394-93c1-d21ad57a810c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037407688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2037407688
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2721138505
Short name T126
Test name
Test status
Simulation time 191263843 ps
CPU time 9.61 seconds
Started Jul 09 05:41:02 PM PDT 24
Finished Jul 09 05:41:12 PM PDT 24
Peak memory 211976 kb
Host smart-dd470b8e-a146-4404-b4bf-97c2af08e100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721138505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2721138505
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1592934731
Short name T1
Test name
Test status
Simulation time 1902017280 ps
CPU time 16.13 seconds
Started Jul 09 05:41:02 PM PDT 24
Finished Jul 09 05:41:19 PM PDT 24
Peak memory 211296 kb
Host smart-31c1c1ba-b062-4c50-b848-51bac72d1fe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592934731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1592934731
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1316824952
Short name T15
Test name
Test status
Simulation time 7869955916 ps
CPU time 34.64 seconds
Started Jul 09 05:41:01 PM PDT 24
Finished Jul 09 05:41:37 PM PDT 24
Peak memory 214240 kb
Host smart-23999a41-1a25-4923-aea8-87729983a88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316824952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1316824952
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3501118825
Short name T314
Test name
Test status
Simulation time 2681081511 ps
CPU time 13.19 seconds
Started Jul 09 05:41:02 PM PDT 24
Finished Jul 09 05:41:16 PM PDT 24
Peak memory 213268 kb
Host smart-c910a2c0-a1a8-43cd-ab9b-0edb64efa527
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501118825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3501118825
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3812005548
Short name T335
Test name
Test status
Simulation time 332786224 ps
CPU time 4.24 seconds
Started Jul 09 05:41:01 PM PDT 24
Finished Jul 09 05:41:06 PM PDT 24
Peak memory 211352 kb
Host smart-6efc6e4e-cb0b-4b8f-b9df-c38eefdcb7c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812005548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3812005548
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.245145635
Short name T135
Test name
Test status
Simulation time 24089079832 ps
CPU time 257.9 seconds
Started Jul 09 05:41:02 PM PDT 24
Finished Jul 09 05:45:20 PM PDT 24
Peak memory 238048 kb
Host smart-cced35c1-cfab-4174-b348-137710de67cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245145635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.245145635
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1420167974
Short name T134
Test name
Test status
Simulation time 2282675223 ps
CPU time 17.02 seconds
Started Jul 09 05:41:06 PM PDT 24
Finished Jul 09 05:41:24 PM PDT 24
Peak memory 211372 kb
Host smart-ffd4bcab-1620-4edb-bb4c-905832ae86fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420167974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1420167974
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1885517706
Short name T9
Test name
Test status
Simulation time 4525028061 ps
CPU time 12.74 seconds
Started Jul 09 05:41:01 PM PDT 24
Finished Jul 09 05:41:15 PM PDT 24
Peak memory 211280 kb
Host smart-dbdc7841-061c-41b4-a837-4bf11ea6273e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885517706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1885517706
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2234727878
Short name T249
Test name
Test status
Simulation time 1181816513 ps
CPU time 8.44 seconds
Started Jul 09 05:41:01 PM PDT 24
Finished Jul 09 05:41:10 PM PDT 24
Peak memory 211244 kb
Host smart-d0eb62de-2fbd-4619-90b1-075068d2fcd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234727878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2234727878
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.255118907
Short name T161
Test name
Test status
Simulation time 9435245677 ps
CPU time 190.27 seconds
Started Jul 09 05:41:02 PM PDT 24
Finished Jul 09 05:44:13 PM PDT 24
Peak memory 236760 kb
Host smart-d8f7e11c-ce47-419e-84f0-4b8922624a1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255118907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.255118907
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1398411076
Short name T168
Test name
Test status
Simulation time 1893626507 ps
CPU time 13.94 seconds
Started Jul 09 05:41:01 PM PDT 24
Finished Jul 09 05:41:16 PM PDT 24
Peak memory 211912 kb
Host smart-a269d4f5-6cc8-46a3-b2c8-b6fe4c1fc64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398411076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1398411076
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2866034651
Short name T6
Test name
Test status
Simulation time 3461410438 ps
CPU time 15 seconds
Started Jul 09 05:41:01 PM PDT 24
Finished Jul 09 05:41:16 PM PDT 24
Peak memory 211412 kb
Host smart-c1e08a36-6d07-41a3-bd49-ecfefc3b35a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866034651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2866034651
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2385615128
Short name T251
Test name
Test status
Simulation time 1778399029 ps
CPU time 24.29 seconds
Started Jul 09 05:41:04 PM PDT 24
Finished Jul 09 05:41:30 PM PDT 24
Peak memory 211836 kb
Host smart-95232e4c-8abf-43a8-b057-4dc6bbef7c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385615128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2385615128
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3446155952
Short name T39
Test name
Test status
Simulation time 564637097 ps
CPU time 9.21 seconds
Started Jul 09 05:41:03 PM PDT 24
Finished Jul 09 05:41:14 PM PDT 24
Peak memory 211380 kb
Host smart-fb3f7cc2-e314-4553-bfaf-380afa5be86c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446155952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3446155952
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2972909719
Short name T172
Test name
Test status
Simulation time 9365284234 ps
CPU time 16.57 seconds
Started Jul 09 05:41:07 PM PDT 24
Finished Jul 09 05:41:25 PM PDT 24
Peak memory 211356 kb
Host smart-fab1fbf7-bd0f-4ac2-a456-b30e7d3da22f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972909719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2972909719
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3250754109
Short name T174
Test name
Test status
Simulation time 54626909929 ps
CPU time 507.48 seconds
Started Jul 09 05:41:02 PM PDT 24
Finished Jul 09 05:49:30 PM PDT 24
Peak memory 237816 kb
Host smart-a390c003-795f-47be-af0e-d5a875de93e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250754109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3250754109
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1586096002
Short name T49
Test name
Test status
Simulation time 26338135672 ps
CPU time 24.47 seconds
Started Jul 09 05:41:09 PM PDT 24
Finished Jul 09 05:41:35 PM PDT 24
Peak memory 212348 kb
Host smart-6321dc45-3bd9-419c-b4f3-56453dd18329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586096002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1586096002
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3787156436
Short name T3
Test name
Test status
Simulation time 853549927 ps
CPU time 6.8 seconds
Started Jul 09 05:41:04 PM PDT 24
Finished Jul 09 05:41:12 PM PDT 24
Peak memory 211396 kb
Host smart-933ae063-bd8f-4f32-afdc-e6286eb5816a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787156436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3787156436
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3551823130
Short name T20
Test name
Test status
Simulation time 30975384928 ps
CPU time 34.06 seconds
Started Jul 09 05:41:01 PM PDT 24
Finished Jul 09 05:41:36 PM PDT 24
Peak memory 212692 kb
Host smart-fb48c2ab-506b-41fb-8897-6306d987e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551823130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3551823130
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.294506228
Short name T284
Test name
Test status
Simulation time 6464105651 ps
CPU time 23.17 seconds
Started Jul 09 05:41:06 PM PDT 24
Finished Jul 09 05:41:30 PM PDT 24
Peak memory 216492 kb
Host smart-e3d3add8-080d-4b41-9d08-633a8a143abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294506228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.294506228
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2468993939
Short name T17
Test name
Test status
Simulation time 40558099621 ps
CPU time 1613.06 seconds
Started Jul 09 05:41:05 PM PDT 24
Finished Jul 09 06:08:00 PM PDT 24
Peak memory 235792 kb
Host smart-877db9bf-f733-47ba-a399-af1fa02f1726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468993939 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2468993939
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1133068589
Short name T191
Test name
Test status
Simulation time 1236651104 ps
CPU time 11.66 seconds
Started Jul 09 05:41:13 PM PDT 24
Finished Jul 09 05:41:26 PM PDT 24
Peak memory 211276 kb
Host smart-d407bd18-5636-4720-8dbc-5fcf16ea76a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133068589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1133068589
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3736253162
Short name T237
Test name
Test status
Simulation time 123843955579 ps
CPU time 392.8 seconds
Started Jul 09 05:41:08 PM PDT 24
Finished Jul 09 05:47:42 PM PDT 24
Peak memory 238024 kb
Host smart-01617d23-869e-4a38-8185-6e8c791eb96d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736253162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3736253162
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1517912424
Short name T10
Test name
Test status
Simulation time 8585664852 ps
CPU time 22.3 seconds
Started Jul 09 05:41:06 PM PDT 24
Finished Jul 09 05:41:30 PM PDT 24
Peak memory 212340 kb
Host smart-19b054ed-6af1-4fbf-a688-97c97b147cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517912424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1517912424
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2034294014
Short name T48
Test name
Test status
Simulation time 6556645422 ps
CPU time 14.34 seconds
Started Jul 09 05:41:06 PM PDT 24
Finished Jul 09 05:41:21 PM PDT 24
Peak memory 211440 kb
Host smart-a1e284e2-d119-49b4-82ac-fac4368c2210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2034294014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2034294014
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3634302074
Short name T315
Test name
Test status
Simulation time 3541321031 ps
CPU time 24.85 seconds
Started Jul 09 05:41:05 PM PDT 24
Finished Jul 09 05:41:31 PM PDT 24
Peak memory 213572 kb
Host smart-1ee63ffa-70cc-4243-8934-53a001c201e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634302074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3634302074
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2908801122
Short name T147
Test name
Test status
Simulation time 33668085601 ps
CPU time 81.59 seconds
Started Jul 09 05:41:04 PM PDT 24
Finished Jul 09 05:42:26 PM PDT 24
Peak memory 217208 kb
Host smart-12d93829-a980-4455-9672-c4e1d7a6b4df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908801122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2908801122
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1029822465
Short name T343
Test name
Test status
Simulation time 55623634979 ps
CPU time 5058.99 seconds
Started Jul 09 05:41:08 PM PDT 24
Finished Jul 09 07:05:29 PM PDT 24
Peak memory 236844 kb
Host smart-cf2a6e2a-0c5e-4f8c-8dc0-21653425ee62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029822465 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1029822465
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2104511764
Short name T301
Test name
Test status
Simulation time 6962407717 ps
CPU time 13.19 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:08 PM PDT 24
Peak memory 211324 kb
Host smart-0d88c823-5cc8-43f1-8a11-4b2b73337d3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104511764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2104511764
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2042652402
Short name T356
Test name
Test status
Simulation time 84075933267 ps
CPU time 131.9 seconds
Started Jul 09 05:40:57 PM PDT 24
Finished Jul 09 05:43:10 PM PDT 24
Peak memory 233452 kb
Host smart-122db15e-9620-4adf-b998-64ebcabd852b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042652402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2042652402
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2104661771
Short name T221
Test name
Test status
Simulation time 691609044 ps
CPU time 9.24 seconds
Started Jul 09 05:40:49 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 211896 kb
Host smart-a6b4f5c2-b7c6-4948-9858-903582fa76a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104661771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2104661771
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1385011774
Short name T272
Test name
Test status
Simulation time 15651721045 ps
CPU time 14.48 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:41:06 PM PDT 24
Peak memory 211456 kb
Host smart-de264cb7-95c8-47ac-a29b-fce9ab203ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385011774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1385011774
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2645830945
Short name T23
Test name
Test status
Simulation time 1248604696 ps
CPU time 103.96 seconds
Started Jul 09 05:40:58 PM PDT 24
Finished Jul 09 05:42:43 PM PDT 24
Peak memory 237944 kb
Host smart-2960042b-cccc-404e-b6ad-a43da80d0387
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645830945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2645830945
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3544403187
Short name T225
Test name
Test status
Simulation time 4323573390 ps
CPU time 41.11 seconds
Started Jul 09 05:40:56 PM PDT 24
Finished Jul 09 05:41:38 PM PDT 24
Peak memory 213468 kb
Host smart-72c87ee8-68be-4f2a-8532-52f8af2be3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544403187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3544403187
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4084020809
Short name T350
Test name
Test status
Simulation time 3850037439 ps
CPU time 23.71 seconds
Started Jul 09 05:40:56 PM PDT 24
Finished Jul 09 05:41:21 PM PDT 24
Peak memory 215000 kb
Host smart-9bc072d0-7eb9-4567-89f1-719f6fff9621
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084020809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4084020809
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3050111254
Short name T336
Test name
Test status
Simulation time 751890749 ps
CPU time 4.24 seconds
Started Jul 09 05:41:07 PM PDT 24
Finished Jul 09 05:41:13 PM PDT 24
Peak memory 211356 kb
Host smart-be1460d4-2c53-4b62-83a9-65bf01448d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050111254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3050111254
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4013943831
Short name T316
Test name
Test status
Simulation time 50039161981 ps
CPU time 185.16 seconds
Started Jul 09 05:41:04 PM PDT 24
Finished Jul 09 05:44:10 PM PDT 24
Peak memory 237816 kb
Host smart-bd6f7126-edab-4f58-b07b-ba465be2e76a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013943831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4013943831
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.806399452
Short name T37
Test name
Test status
Simulation time 8652379689 ps
CPU time 20.16 seconds
Started Jul 09 05:41:06 PM PDT 24
Finished Jul 09 05:41:27 PM PDT 24
Peak memory 212156 kb
Host smart-ae18688c-77bd-4ed9-b4c0-d8a2b1c37605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806399452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.806399452
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.922450570
Short name T148
Test name
Test status
Simulation time 5046616517 ps
CPU time 9.11 seconds
Started Jul 09 05:41:09 PM PDT 24
Finished Jul 09 05:41:19 PM PDT 24
Peak memory 211460 kb
Host smart-6d78a2a6-2f50-4cd5-ac74-907ad01a39c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922450570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.922450570
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2183007114
Short name T167
Test name
Test status
Simulation time 13305472763 ps
CPU time 31.7 seconds
Started Jul 09 05:41:05 PM PDT 24
Finished Jul 09 05:41:38 PM PDT 24
Peak memory 213720 kb
Host smart-f515f5ed-549e-4af3-8ef3-bd1356933cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183007114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2183007114
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.560718622
Short name T296
Test name
Test status
Simulation time 12153660913 ps
CPU time 17.75 seconds
Started Jul 09 05:41:08 PM PDT 24
Finished Jul 09 05:41:27 PM PDT 24
Peak memory 211292 kb
Host smart-9c70a30f-cdd4-4969-ad63-3ceee84734ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560718622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.560718622
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3076987887
Short name T64
Test name
Test status
Simulation time 4052552111 ps
CPU time 16.61 seconds
Started Jul 09 05:41:06 PM PDT 24
Finished Jul 09 05:41:24 PM PDT 24
Peak memory 211124 kb
Host smart-d3f8d12f-ddec-4415-ba88-6b4f3bb60622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076987887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3076987887
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4088695523
Short name T175
Test name
Test status
Simulation time 59941137158 ps
CPU time 298.99 seconds
Started Jul 09 05:41:08 PM PDT 24
Finished Jul 09 05:46:08 PM PDT 24
Peak memory 237856 kb
Host smart-a5183bd0-2d9e-4617-aa64-31795ca5892a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088695523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4088695523
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3167241092
Short name T214
Test name
Test status
Simulation time 6572828595 ps
CPU time 27.62 seconds
Started Jul 09 05:41:05 PM PDT 24
Finished Jul 09 05:41:34 PM PDT 24
Peak memory 212224 kb
Host smart-f52f8ca8-67bf-485e-a937-541546f9e6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167241092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3167241092
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4127010514
Short name T267
Test name
Test status
Simulation time 2309462246 ps
CPU time 12.65 seconds
Started Jul 09 05:41:06 PM PDT 24
Finished Jul 09 05:41:20 PM PDT 24
Peak memory 211444 kb
Host smart-a6ae7b2d-9cad-49eb-96fe-8e2e079588c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4127010514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4127010514
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.250980686
Short name T223
Test name
Test status
Simulation time 2813737314 ps
CPU time 35.7 seconds
Started Jul 09 05:41:05 PM PDT 24
Finished Jul 09 05:41:42 PM PDT 24
Peak memory 213604 kb
Host smart-53feaffa-a812-40b2-93b5-0ec8d40ea506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250980686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.250980686
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1326243405
Short name T217
Test name
Test status
Simulation time 193831649 ps
CPU time 13.62 seconds
Started Jul 09 05:41:04 PM PDT 24
Finished Jul 09 05:41:19 PM PDT 24
Peak memory 213772 kb
Host smart-8a5d949b-fa31-4058-b231-942bf9457cb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326243405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1326243405
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1190738424
Short name T50
Test name
Test status
Simulation time 69547532545 ps
CPU time 687.36 seconds
Started Jul 09 05:41:09 PM PDT 24
Finished Jul 09 05:52:37 PM PDT 24
Peak memory 235796 kb
Host smart-add8a248-2747-4f5a-8442-21c075fbfc7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190738424 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1190738424
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4148594753
Short name T305
Test name
Test status
Simulation time 795093327 ps
CPU time 8.9 seconds
Started Jul 09 05:41:06 PM PDT 24
Finished Jul 09 05:41:16 PM PDT 24
Peak memory 211316 kb
Host smart-1fdddef9-7ee8-4341-b4e5-67b7ad76dc99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148594753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4148594753
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.834728058
Short name T261
Test name
Test status
Simulation time 627353661901 ps
CPU time 423.16 seconds
Started Jul 09 05:41:13 PM PDT 24
Finished Jul 09 05:48:18 PM PDT 24
Peak memory 237848 kb
Host smart-52d28de1-2d8f-4edf-9dc4-c79ad5b5e23c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834728058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.834728058
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3129127521
Short name T298
Test name
Test status
Simulation time 11587217033 ps
CPU time 30.95 seconds
Started Jul 09 05:41:07 PM PDT 24
Finished Jul 09 05:41:39 PM PDT 24
Peak memory 212240 kb
Host smart-9d0077ac-ceb1-43ce-9af9-efd7f0915c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129127521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3129127521
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1090430018
Short name T263
Test name
Test status
Simulation time 10113444031 ps
CPU time 17.03 seconds
Started Jul 09 05:41:07 PM PDT 24
Finished Jul 09 05:41:25 PM PDT 24
Peak memory 211408 kb
Host smart-93bb260b-1337-49c3-a00a-46a167e6f7fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090430018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1090430018
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1701812915
Short name T204
Test name
Test status
Simulation time 371856434 ps
CPU time 9.84 seconds
Started Jul 09 05:41:07 PM PDT 24
Finished Jul 09 05:41:18 PM PDT 24
Peak memory 213272 kb
Host smart-abd5104c-8135-4e29-9343-9cafb8473319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701812915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1701812915
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1587781163
Short name T260
Test name
Test status
Simulation time 11969032695 ps
CPU time 34.64 seconds
Started Jul 09 05:41:07 PM PDT 24
Finished Jul 09 05:41:43 PM PDT 24
Peak memory 216864 kb
Host smart-363c356d-32b8-4e55-aada-a64a264d9d56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587781163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1587781163
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3764569992
Short name T222
Test name
Test status
Simulation time 7075924786 ps
CPU time 14.31 seconds
Started Jul 09 05:41:10 PM PDT 24
Finished Jul 09 05:41:25 PM PDT 24
Peak memory 211404 kb
Host smart-61f8a24e-bcfc-4caf-a5b0-d709710769d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764569992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3764569992
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2109855769
Short name T140
Test name
Test status
Simulation time 5183848502 ps
CPU time 112.6 seconds
Started Jul 09 05:41:08 PM PDT 24
Finished Jul 09 05:43:02 PM PDT 24
Peak memory 237428 kb
Host smart-c2d22e39-db64-4566-be13-ac3726d97344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109855769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2109855769
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3362243785
Short name T349
Test name
Test status
Simulation time 17024951867 ps
CPU time 33.65 seconds
Started Jul 09 05:41:25 PM PDT 24
Finished Jul 09 05:42:00 PM PDT 24
Peak memory 212288 kb
Host smart-cc4432af-e09d-420d-bc1c-9887aa8b4469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362243785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3362243785
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.431229800
Short name T352
Test name
Test status
Simulation time 5262859504 ps
CPU time 16.63 seconds
Started Jul 09 05:41:15 PM PDT 24
Finished Jul 09 05:41:32 PM PDT 24
Peak memory 211460 kb
Host smart-8c3e918a-f465-4787-9295-38eb17ceb211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431229800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.431229800
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.460182654
Short name T194
Test name
Test status
Simulation time 3649816719 ps
CPU time 19.02 seconds
Started Jul 09 05:41:20 PM PDT 24
Finished Jul 09 05:41:40 PM PDT 24
Peak memory 213408 kb
Host smart-93f0f297-831f-4769-8803-af80aaed3ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460182654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.460182654
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.41046339
Short name T270
Test name
Test status
Simulation time 8252832085 ps
CPU time 76.53 seconds
Started Jul 09 05:41:11 PM PDT 24
Finished Jul 09 05:42:28 PM PDT 24
Peak memory 217288 kb
Host smart-249c15f9-3356-4701-8028-868b02669cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41046339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.rom_ctrl_stress_all.41046339
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.807776587
Short name T292
Test name
Test status
Simulation time 986912377 ps
CPU time 6.01 seconds
Started Jul 09 05:41:15 PM PDT 24
Finished Jul 09 05:41:21 PM PDT 24
Peak memory 211344 kb
Host smart-d9efc49b-0307-4bca-a130-9e1bc7e1f39e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807776587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.807776587
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.968035058
Short name T213
Test name
Test status
Simulation time 10353261261 ps
CPU time 110.65 seconds
Started Jul 09 05:41:09 PM PDT 24
Finished Jul 09 05:43:00 PM PDT 24
Peak memory 237708 kb
Host smart-5e12029d-588a-4dc8-8717-85340e6e5737
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968035058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.968035058
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2723172408
Short name T210
Test name
Test status
Simulation time 13019010435 ps
CPU time 19.46 seconds
Started Jul 09 05:41:08 PM PDT 24
Finished Jul 09 05:41:29 PM PDT 24
Peak memory 212304 kb
Host smart-c336f22a-5ef2-4309-827e-65977da287b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723172408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2723172408
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2459158365
Short name T326
Test name
Test status
Simulation time 220619684 ps
CPU time 5.48 seconds
Started Jul 09 05:41:09 PM PDT 24
Finished Jul 09 05:41:15 PM PDT 24
Peak memory 211400 kb
Host smart-225767b7-9a56-40ad-946a-eae2e57f2567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459158365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2459158365
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2252700753
Short name T220
Test name
Test status
Simulation time 184571603 ps
CPU time 10.18 seconds
Started Jul 09 05:41:08 PM PDT 24
Finished Jul 09 05:41:19 PM PDT 24
Peak memory 212680 kb
Host smart-059ef5d0-1126-47b2-8bb5-55991895d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252700753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2252700753
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.55915438
Short name T238
Test name
Test status
Simulation time 437570711 ps
CPU time 14.24 seconds
Started Jul 09 05:41:26 PM PDT 24
Finished Jul 09 05:41:42 PM PDT 24
Peak memory 214676 kb
Host smart-6e2741a7-2b3f-4052-91b0-77d6e0b1c042
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55915438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 24.rom_ctrl_stress_all.55915438
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3889596636
Short name T359
Test name
Test status
Simulation time 26136702419 ps
CPU time 4508.73 seconds
Started Jul 09 05:41:09 PM PDT 24
Finished Jul 09 06:56:19 PM PDT 24
Peak memory 235820 kb
Host smart-aad97b93-03c6-4ccf-9f7d-1395ca4f1e9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889596636 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3889596636
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2872191840
Short name T309
Test name
Test status
Simulation time 199999583 ps
CPU time 4.52 seconds
Started Jul 09 05:41:12 PM PDT 24
Finished Jul 09 05:41:18 PM PDT 24
Peak memory 211352 kb
Host smart-a9c89148-4c95-4812-ba1d-87bdb2575b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872191840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2872191840
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1748634862
Short name T351
Test name
Test status
Simulation time 45709133382 ps
CPU time 416.84 seconds
Started Jul 09 05:41:13 PM PDT 24
Finished Jul 09 05:48:12 PM PDT 24
Peak memory 233772 kb
Host smart-efdb8519-6b17-4903-99bb-832dd49c422e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748634862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1748634862
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3311568138
Short name T159
Test name
Test status
Simulation time 1033612891 ps
CPU time 16.38 seconds
Started Jul 09 05:41:14 PM PDT 24
Finished Jul 09 05:41:31 PM PDT 24
Peak memory 211976 kb
Host smart-db08d5d9-b919-48e8-a340-e8f3792d8795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311568138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3311568138
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.742436241
Short name T128
Test name
Test status
Simulation time 8302923316 ps
CPU time 17.1 seconds
Started Jul 09 05:41:13 PM PDT 24
Finished Jul 09 05:41:31 PM PDT 24
Peak memory 211444 kb
Host smart-872f69d5-12c2-48a3-bb9a-8c85517ef5ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=742436241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.742436241
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2732384120
Short name T153
Test name
Test status
Simulation time 9009538726 ps
CPU time 24.5 seconds
Started Jul 09 05:41:16 PM PDT 24
Finished Jul 09 05:41:41 PM PDT 24
Peak memory 214432 kb
Host smart-eb8b4bf6-18bb-47ec-96b3-a48219513c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732384120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2732384120
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3281066865
Short name T187
Test name
Test status
Simulation time 6081098055 ps
CPU time 66.01 seconds
Started Jul 09 05:41:16 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 217224 kb
Host smart-03ce639a-80ce-4715-8f1c-3ed8486b4a1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281066865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3281066865
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2906435912
Short name T169
Test name
Test status
Simulation time 175616946 ps
CPU time 4.27 seconds
Started Jul 09 05:41:13 PM PDT 24
Finished Jul 09 05:41:19 PM PDT 24
Peak memory 211308 kb
Host smart-a9495c48-080f-43ad-9e7f-dd004a599192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906435912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2906435912
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2395563873
Short name T294
Test name
Test status
Simulation time 194072189412 ps
CPU time 487.47 seconds
Started Jul 09 05:41:27 PM PDT 24
Finished Jul 09 05:49:36 PM PDT 24
Peak memory 237848 kb
Host smart-685ac4d8-f7a9-4d50-b125-bf3f8997a045
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395563873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2395563873
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2339997003
Short name T127
Test name
Test status
Simulation time 594792629 ps
CPU time 9.49 seconds
Started Jul 09 05:41:16 PM PDT 24
Finished Jul 09 05:41:27 PM PDT 24
Peak memory 211864 kb
Host smart-49497047-4fce-451c-af9a-4761ea179e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339997003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2339997003
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2038339197
Short name T244
Test name
Test status
Simulation time 25652082980 ps
CPU time 17.44 seconds
Started Jul 09 05:41:17 PM PDT 24
Finished Jul 09 05:41:35 PM PDT 24
Peak memory 211452 kb
Host smart-685f1595-17d1-4a12-853e-9073dcc8d578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038339197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2038339197
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2358368541
Short name T341
Test name
Test status
Simulation time 695612969 ps
CPU time 10.27 seconds
Started Jul 09 05:41:22 PM PDT 24
Finished Jul 09 05:41:33 PM PDT 24
Peak memory 213188 kb
Host smart-9e0dae85-3a3f-43aa-b473-80ce01b8a996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358368541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2358368541
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1632505902
Short name T310
Test name
Test status
Simulation time 23070418570 ps
CPU time 77.35 seconds
Started Jul 09 05:41:38 PM PDT 24
Finished Jul 09 05:42:56 PM PDT 24
Peak memory 218172 kb
Host smart-e79bd966-0ecc-4c70-b6ff-a008988d570e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632505902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1632505902
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1353014038
Short name T55
Test name
Test status
Simulation time 52952142038 ps
CPU time 1974.43 seconds
Started Jul 09 05:41:13 PM PDT 24
Finished Jul 09 06:14:08 PM PDT 24
Peak memory 235816 kb
Host smart-b9a62718-04f4-4ec6-9af4-6f03f9bf9989
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353014038 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1353014038
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4208967284
Short name T334
Test name
Test status
Simulation time 1628739295 ps
CPU time 8.76 seconds
Started Jul 09 05:41:17 PM PDT 24
Finished Jul 09 05:41:26 PM PDT 24
Peak memory 211352 kb
Host smart-c97a6b65-6ce4-4f14-83d4-108c2c1b9367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208967284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4208967284
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1921700091
Short name T181
Test name
Test status
Simulation time 1466971777 ps
CPU time 75.98 seconds
Started Jul 09 05:41:28 PM PDT 24
Finished Jul 09 05:42:45 PM PDT 24
Peak memory 213308 kb
Host smart-7063c67f-e070-4776-aa15-a2bbee8baa48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921700091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1921700091
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3228378597
Short name T183
Test name
Test status
Simulation time 5980771786 ps
CPU time 19.61 seconds
Started Jul 09 05:41:16 PM PDT 24
Finished Jul 09 05:41:36 PM PDT 24
Peak memory 212536 kb
Host smart-6e67a135-c29c-4398-a6f7-52f027e96381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228378597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3228378597
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2173200040
Short name T184
Test name
Test status
Simulation time 2528538151 ps
CPU time 12.2 seconds
Started Jul 09 05:41:30 PM PDT 24
Finished Jul 09 05:41:43 PM PDT 24
Peak memory 211404 kb
Host smart-d1876c7c-ca5b-4df3-8908-8e650415cdb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173200040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2173200040
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1389643896
Short name T318
Test name
Test status
Simulation time 1200894384 ps
CPU time 15.66 seconds
Started Jul 09 05:41:16 PM PDT 24
Finished Jul 09 05:41:33 PM PDT 24
Peak memory 213184 kb
Host smart-418677ef-0093-4755-892c-403126df2328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389643896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1389643896
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2569906313
Short name T287
Test name
Test status
Simulation time 10448639391 ps
CPU time 53.33 seconds
Started Jul 09 05:41:16 PM PDT 24
Finished Jul 09 05:42:10 PM PDT 24
Peak memory 216856 kb
Host smart-43748c3d-152d-410d-9f57-091c66abdd2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569906313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2569906313
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1419263405
Short name T258
Test name
Test status
Simulation time 2999479315 ps
CPU time 16.01 seconds
Started Jul 09 05:41:16 PM PDT 24
Finished Jul 09 05:41:33 PM PDT 24
Peak memory 211328 kb
Host smart-1f75932d-cc01-47df-b650-baeeb5a924ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419263405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1419263405
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1701599325
Short name T115
Test name
Test status
Simulation time 2549120822 ps
CPU time 74.49 seconds
Started Jul 09 05:41:15 PM PDT 24
Finished Jul 09 05:42:30 PM PDT 24
Peak memory 213620 kb
Host smart-12ef2875-6706-4c35-ab35-25283b359f77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701599325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1701599325
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3620941742
Short name T325
Test name
Test status
Simulation time 1465859478 ps
CPU time 18.82 seconds
Started Jul 09 05:41:21 PM PDT 24
Finished Jul 09 05:41:41 PM PDT 24
Peak memory 211832 kb
Host smart-d43b618e-dc5b-4a28-a308-e00b4e63cbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620941742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3620941742
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.816402104
Short name T199
Test name
Test status
Simulation time 1278143891 ps
CPU time 12.58 seconds
Started Jul 09 05:41:16 PM PDT 24
Finished Jul 09 05:41:29 PM PDT 24
Peak memory 211372 kb
Host smart-19b115d8-33fe-4ed5-83d5-22df17492024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=816402104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.816402104
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.969975568
Short name T235
Test name
Test status
Simulation time 364778766 ps
CPU time 10.43 seconds
Started Jul 09 05:41:12 PM PDT 24
Finished Jul 09 05:41:23 PM PDT 24
Peak memory 213748 kb
Host smart-e6f27d88-0510-41e3-b1fb-df6bb1a6c529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969975568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.969975568
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2068918832
Short name T158
Test name
Test status
Simulation time 5885638452 ps
CPU time 31.04 seconds
Started Jul 09 05:41:13 PM PDT 24
Finished Jul 09 05:41:46 PM PDT 24
Peak memory 213008 kb
Host smart-567d4be0-b87b-43d8-b5e5-8451a3065375
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068918832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2068918832
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2336437795
Short name T54
Test name
Test status
Simulation time 36003465850 ps
CPU time 2268.52 seconds
Started Jul 09 05:41:32 PM PDT 24
Finished Jul 09 06:19:22 PM PDT 24
Peak memory 235860 kb
Host smart-ee9a73fe-f2fd-4a5b-81a7-6e9b87b17809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336437795 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2336437795
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1530102004
Short name T276
Test name
Test status
Simulation time 1998719417 ps
CPU time 11.75 seconds
Started Jul 09 05:41:24 PM PDT 24
Finished Jul 09 05:41:36 PM PDT 24
Peak memory 211356 kb
Host smart-369cd3a4-176b-4411-b5bc-8b71a68a5fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530102004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1530102004
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.616366895
Short name T178
Test name
Test status
Simulation time 36101087305 ps
CPU time 317.9 seconds
Started Jul 09 05:41:22 PM PDT 24
Finished Jul 09 05:46:41 PM PDT 24
Peak memory 233092 kb
Host smart-231b4530-8925-40bf-9497-d02dd5945f13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616366895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.616366895
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3823486275
Short name T166
Test name
Test status
Simulation time 172266675 ps
CPU time 9.85 seconds
Started Jul 09 05:41:15 PM PDT 24
Finished Jul 09 05:41:25 PM PDT 24
Peak memory 212288 kb
Host smart-371058c2-89f8-47bb-998b-7d26c3d15e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823486275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3823486275
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1155854242
Short name T299
Test name
Test status
Simulation time 13839916708 ps
CPU time 13.02 seconds
Started Jul 09 05:41:15 PM PDT 24
Finished Jul 09 05:41:29 PM PDT 24
Peak memory 211396 kb
Host smart-f909525c-1be4-49fe-a6dd-3385dd49bfc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155854242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1155854242
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.65055474
Short name T273
Test name
Test status
Simulation time 11180543879 ps
CPU time 26.53 seconds
Started Jul 09 05:41:24 PM PDT 24
Finished Jul 09 05:41:51 PM PDT 24
Peak memory 214220 kb
Host smart-e2303911-a44f-4d06-97b8-c17f05245822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65055474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.65055474
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1122626003
Short name T332
Test name
Test status
Simulation time 1993140172 ps
CPU time 16.69 seconds
Started Jul 09 05:41:39 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 211412 kb
Host smart-7e2dac5c-f254-48d3-9230-d1e8a204d229
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122626003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1122626003
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1374510367
Short name T149
Test name
Test status
Simulation time 3769542970 ps
CPU time 10.18 seconds
Started Jul 09 05:40:56 PM PDT 24
Finished Jul 09 05:41:07 PM PDT 24
Peak memory 211384 kb
Host smart-4c0af251-84cd-4209-93f6-41097b6b80ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374510367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1374510367
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2903067464
Short name T269
Test name
Test status
Simulation time 4239695658 ps
CPU time 152.01 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:43:24 PM PDT 24
Peak memory 225216 kb
Host smart-f46708b4-2d76-4b99-bfbe-c8319d71dd1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903067464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2903067464
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1348806316
Short name T283
Test name
Test status
Simulation time 16719311605 ps
CPU time 33.36 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:41:25 PM PDT 24
Peak memory 212460 kb
Host smart-3de5eff1-a0b7-424a-b259-50c8220902c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348806316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1348806316
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.423239732
Short name T150
Test name
Test status
Simulation time 3402511193 ps
CPU time 16.16 seconds
Started Jul 09 05:40:49 PM PDT 24
Finished Jul 09 05:41:06 PM PDT 24
Peak memory 211420 kb
Host smart-afffcfd4-c537-4245-84e1-20bf1d34de81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423239732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.423239732
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1246391409
Short name T31
Test name
Test status
Simulation time 6273296244 ps
CPU time 59.79 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:41:51 PM PDT 24
Peak memory 235968 kb
Host smart-ac4e2a1c-25ef-42f8-a5b1-313b0ef4db8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246391409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1246391409
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.860966740
Short name T357
Test name
Test status
Simulation time 13048419550 ps
CPU time 31.1 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:41:25 PM PDT 24
Peak memory 214516 kb
Host smart-3ca2655e-18be-402f-95cb-ad1a76c998ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860966740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.860966740
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2218287425
Short name T333
Test name
Test status
Simulation time 612598996 ps
CPU time 15.78 seconds
Started Jul 09 05:40:56 PM PDT 24
Finished Jul 09 05:41:13 PM PDT 24
Peak memory 213688 kb
Host smart-b8022953-ae37-4a86-bfa4-76e523fc9f13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218287425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2218287425
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.4275673226
Short name T179
Test name
Test status
Simulation time 1830816768 ps
CPU time 7.5 seconds
Started Jul 09 05:41:27 PM PDT 24
Finished Jul 09 05:41:36 PM PDT 24
Peak memory 211288 kb
Host smart-1f46ace0-3108-4990-8010-8da7d2c84745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275673226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4275673226
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4139251755
Short name T144
Test name
Test status
Simulation time 723472413 ps
CPU time 9.45 seconds
Started Jul 09 05:41:32 PM PDT 24
Finished Jul 09 05:41:42 PM PDT 24
Peak memory 211952 kb
Host smart-cdafaa8c-8dc1-46d4-94ff-76b63a5025dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139251755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4139251755
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1388933947
Short name T163
Test name
Test status
Simulation time 4014502938 ps
CPU time 12.72 seconds
Started Jul 09 05:41:26 PM PDT 24
Finished Jul 09 05:41:39 PM PDT 24
Peak memory 211512 kb
Host smart-acc44948-3fda-4011-aec3-780a6d06ee81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388933947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1388933947
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1746416138
Short name T361
Test name
Test status
Simulation time 215612061 ps
CPU time 10.25 seconds
Started Jul 09 05:41:17 PM PDT 24
Finished Jul 09 05:41:28 PM PDT 24
Peak memory 213236 kb
Host smart-f738c7d6-de07-41dc-9e1d-5ff597b6d667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746416138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1746416138
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1564560078
Short name T274
Test name
Test status
Simulation time 3452844944 ps
CPU time 43.23 seconds
Started Jul 09 05:41:25 PM PDT 24
Finished Jul 09 05:42:09 PM PDT 24
Peak memory 213148 kb
Host smart-b170484d-1cb8-4b75-a06c-f86d3f719e4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564560078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1564560078
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1136650916
Short name T26
Test name
Test status
Simulation time 8188375540 ps
CPU time 15.35 seconds
Started Jul 09 05:41:27 PM PDT 24
Finished Jul 09 05:41:43 PM PDT 24
Peak memory 211408 kb
Host smart-27189db4-2b01-4ae2-91d2-113b1055e810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136650916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1136650916
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1368667176
Short name T118
Test name
Test status
Simulation time 2309611684 ps
CPU time 141.09 seconds
Started Jul 09 05:41:20 PM PDT 24
Finished Jul 09 05:43:42 PM PDT 24
Peak memory 236816 kb
Host smart-91e16371-a90a-4bd5-a6d1-ea84f66ed9f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368667176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1368667176
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2688379211
Short name T27
Test name
Test status
Simulation time 172009867 ps
CPU time 9.71 seconds
Started Jul 09 05:41:21 PM PDT 24
Finished Jul 09 05:41:31 PM PDT 24
Peak memory 211928 kb
Host smart-462184c9-b21a-4687-ad2d-08299284dded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688379211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2688379211
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.512576481
Short name T293
Test name
Test status
Simulation time 100026963 ps
CPU time 6.06 seconds
Started Jul 09 05:41:33 PM PDT 24
Finished Jul 09 05:41:40 PM PDT 24
Peak memory 211396 kb
Host smart-a64dda71-84cc-435c-a7b2-d4b2b577930a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512576481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.512576481
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2343663807
Short name T207
Test name
Test status
Simulation time 530563757 ps
CPU time 13.12 seconds
Started Jul 09 05:41:18 PM PDT 24
Finished Jul 09 05:41:32 PM PDT 24
Peak memory 213076 kb
Host smart-dce18788-1f45-4883-add8-aa4bb7b41d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343663807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2343663807
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.479598632
Short name T76
Test name
Test status
Simulation time 4676391521 ps
CPU time 48.36 seconds
Started Jul 09 05:41:27 PM PDT 24
Finished Jul 09 05:42:16 PM PDT 24
Peak memory 215448 kb
Host smart-7a8878c2-7671-46cb-92cc-5edc5d67de48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479598632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.479598632
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4214801589
Short name T342
Test name
Test status
Simulation time 309187074 ps
CPU time 4.33 seconds
Started Jul 09 05:41:36 PM PDT 24
Finished Jul 09 05:41:41 PM PDT 24
Peak memory 211300 kb
Host smart-063637b4-ec02-469a-ac19-9c8f35b8c82a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214801589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4214801589
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3551229809
Short name T330
Test name
Test status
Simulation time 296054366698 ps
CPU time 379.24 seconds
Started Jul 09 05:41:32 PM PDT 24
Finished Jul 09 05:47:51 PM PDT 24
Peak memory 238080 kb
Host smart-5fab17d8-d6f3-4b55-95a6-79e31f4d2a89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551229809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3551229809
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1188212828
Short name T157
Test name
Test status
Simulation time 18720652940 ps
CPU time 22.05 seconds
Started Jul 09 05:41:21 PM PDT 24
Finished Jul 09 05:41:44 PM PDT 24
Peak memory 212272 kb
Host smart-e3f21897-286e-42ef-9822-03366c793401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188212828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1188212828
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.168444732
Short name T289
Test name
Test status
Simulation time 6821794082 ps
CPU time 12.24 seconds
Started Jul 09 05:41:21 PM PDT 24
Finished Jul 09 05:41:34 PM PDT 24
Peak memory 211460 kb
Host smart-89b95f39-b42d-44b2-8183-aa234621ef3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=168444732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.168444732
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2712315058
Short name T266
Test name
Test status
Simulation time 8408983781 ps
CPU time 43.02 seconds
Started Jul 09 05:41:19 PM PDT 24
Finished Jul 09 05:42:03 PM PDT 24
Peak memory 214184 kb
Host smart-83ba834a-f03a-4cb9-8460-de77c92cfc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712315058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2712315058
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3617416165
Short name T81
Test name
Test status
Simulation time 31874536471 ps
CPU time 51.97 seconds
Started Jul 09 05:41:30 PM PDT 24
Finished Jul 09 05:42:23 PM PDT 24
Peak memory 217584 kb
Host smart-3f623f8d-8e97-4641-a28c-110945674869
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617416165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3617416165
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2507483856
Short name T286
Test name
Test status
Simulation time 88042020 ps
CPU time 4.25 seconds
Started Jul 09 05:41:29 PM PDT 24
Finished Jul 09 05:41:34 PM PDT 24
Peak memory 211404 kb
Host smart-3ca6ea8c-a66e-42e8-8db1-ec0b4f44e16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507483856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2507483856
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2084908174
Short name T219
Test name
Test status
Simulation time 59997115431 ps
CPU time 176.81 seconds
Started Jul 09 05:41:34 PM PDT 24
Finished Jul 09 05:44:31 PM PDT 24
Peak memory 235936 kb
Host smart-36afbb12-14ae-464a-a921-1ab9277568b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084908174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2084908174
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4060658816
Short name T136
Test name
Test status
Simulation time 8392470440 ps
CPU time 35.1 seconds
Started Jul 09 05:41:35 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 212392 kb
Host smart-aecca1af-ccb6-449f-b8cc-c35d57a5175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060658816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4060658816
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.968155994
Short name T101
Test name
Test status
Simulation time 191830690 ps
CPU time 5.67 seconds
Started Jul 09 05:41:27 PM PDT 24
Finished Jul 09 05:41:34 PM PDT 24
Peak memory 211336 kb
Host smart-48df9dc7-c13e-49ff-94d3-45408c42d550
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968155994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.968155994
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3280124990
Short name T288
Test name
Test status
Simulation time 8629914581 ps
CPU time 23.99 seconds
Started Jul 09 05:41:29 PM PDT 24
Finished Jul 09 05:41:54 PM PDT 24
Peak memory 214408 kb
Host smart-db92b267-e9b5-4cb7-992a-bcc7b4bcd7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280124990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3280124990
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2085619520
Short name T77
Test name
Test status
Simulation time 2911259678 ps
CPU time 16.34 seconds
Started Jul 09 05:41:32 PM PDT 24
Finished Jul 09 05:41:48 PM PDT 24
Peak memory 212380 kb
Host smart-df83efe3-3870-4fb6-8c7b-9202f5eea569
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085619520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2085619520
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1467203429
Short name T53
Test name
Test status
Simulation time 243297284815 ps
CPU time 2003.02 seconds
Started Jul 09 05:41:35 PM PDT 24
Finished Jul 09 06:14:59 PM PDT 24
Peak memory 236044 kb
Host smart-fde30ccc-0ec7-48f3-ba2b-7440b7c7a9bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467203429 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1467203429
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1224124842
Short name T195
Test name
Test status
Simulation time 787651962 ps
CPU time 9.15 seconds
Started Jul 09 05:41:27 PM PDT 24
Finished Jul 09 05:41:37 PM PDT 24
Peak memory 211292 kb
Host smart-497106e0-ca32-41bd-9e3f-9f21dd6af7f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224124842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1224124842
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2088120205
Short name T152
Test name
Test status
Simulation time 85191251412 ps
CPU time 225.71 seconds
Started Jul 09 05:41:35 PM PDT 24
Finished Jul 09 05:45:21 PM PDT 24
Peak memory 213676 kb
Host smart-0ec27a59-fea8-48e1-8d6c-f81498d20f3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088120205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2088120205
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.608298139
Short name T346
Test name
Test status
Simulation time 638995020 ps
CPU time 9.61 seconds
Started Jul 09 05:41:24 PM PDT 24
Finished Jul 09 05:41:35 PM PDT 24
Peak memory 211932 kb
Host smart-83cbfffd-3e6c-4a50-be37-42a5dda47c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608298139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.608298139
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2206141904
Short name T347
Test name
Test status
Simulation time 834744272 ps
CPU time 10.02 seconds
Started Jul 09 05:41:34 PM PDT 24
Finished Jul 09 05:41:45 PM PDT 24
Peak memory 211396 kb
Host smart-87aa70e2-8b12-4198-b8de-01c1e6af8ae9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206141904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2206141904
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3053541198
Short name T139
Test name
Test status
Simulation time 8619617789 ps
CPU time 22.56 seconds
Started Jul 09 05:41:32 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 214200 kb
Host smart-9b20c2f6-7cb6-4b69-846f-579adc75ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053541198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3053541198
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2492326378
Short name T165
Test name
Test status
Simulation time 2744419477 ps
CPU time 23.79 seconds
Started Jul 09 05:41:29 PM PDT 24
Finished Jul 09 05:41:54 PM PDT 24
Peak memory 216464 kb
Host smart-c7fcc901-93db-41a4-a1c9-568003bcc32a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492326378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2492326378
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3546956264
Short name T52
Test name
Test status
Simulation time 33664986641 ps
CPU time 641.72 seconds
Started Jul 09 05:41:33 PM PDT 24
Finished Jul 09 05:52:15 PM PDT 24
Peak memory 234728 kb
Host smart-761a59e4-39fa-4b75-acc1-de9a00258a99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546956264 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3546956264
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2748772293
Short name T226
Test name
Test status
Simulation time 333202000 ps
CPU time 4.35 seconds
Started Jul 09 05:41:25 PM PDT 24
Finished Jul 09 05:41:30 PM PDT 24
Peak memory 211320 kb
Host smart-c2e0ae74-46d7-4037-b0f8-6a7bf5a2211d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748772293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2748772293
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3221373257
Short name T21
Test name
Test status
Simulation time 1611175141 ps
CPU time 96.38 seconds
Started Jul 09 05:41:24 PM PDT 24
Finished Jul 09 05:43:01 PM PDT 24
Peak memory 236772 kb
Host smart-17af5669-8e70-4422-8571-80f6d05c91fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221373257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3221373257
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2939552705
Short name T253
Test name
Test status
Simulation time 4293563864 ps
CPU time 33.56 seconds
Started Jul 09 05:41:24 PM PDT 24
Finished Jul 09 05:41:58 PM PDT 24
Peak memory 212332 kb
Host smart-6d138259-904e-4db7-86f7-f1b640484e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939552705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2939552705
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.216089624
Short name T205
Test name
Test status
Simulation time 1199810743 ps
CPU time 12.04 seconds
Started Jul 09 05:41:38 PM PDT 24
Finished Jul 09 05:41:51 PM PDT 24
Peak memory 211628 kb
Host smart-5fa01f5b-1809-45d2-b6f4-cec74ba1e10c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216089624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.216089624
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4166864550
Short name T337
Test name
Test status
Simulation time 567157413 ps
CPU time 9.84 seconds
Started Jul 09 05:41:27 PM PDT 24
Finished Jul 09 05:41:38 PM PDT 24
Peak memory 213004 kb
Host smart-ea076467-cb79-457c-bcea-dffbd73f4de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166864550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4166864550
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2491552583
Short name T234
Test name
Test status
Simulation time 6108165026 ps
CPU time 60.89 seconds
Started Jul 09 05:41:24 PM PDT 24
Finished Jul 09 05:42:25 PM PDT 24
Peak memory 216860 kb
Host smart-b2f72c37-5875-4b51-bb63-a7ee87224603
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491552583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2491552583
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1165092095
Short name T282
Test name
Test status
Simulation time 659115347 ps
CPU time 8.53 seconds
Started Jul 09 05:41:28 PM PDT 24
Finished Jul 09 05:41:37 PM PDT 24
Peak memory 211292 kb
Host smart-3a3e245d-ce00-41a4-95fd-03bb6a4f03b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165092095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1165092095
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1251779936
Short name T119
Test name
Test status
Simulation time 83279555403 ps
CPU time 199.26 seconds
Started Jul 09 05:41:36 PM PDT 24
Finished Jul 09 05:44:55 PM PDT 24
Peak memory 236980 kb
Host smart-af5fd93c-5b80-42f2-a8e1-9c3d4e726465
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251779936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1251779936
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3796224329
Short name T186
Test name
Test status
Simulation time 3504723425 ps
CPU time 28.53 seconds
Started Jul 09 05:41:30 PM PDT 24
Finished Jul 09 05:41:59 PM PDT 24
Peak memory 213504 kb
Host smart-df9c01f6-763b-41d8-9710-b2ced9aa8017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796224329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3796224329
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1730314219
Short name T170
Test name
Test status
Simulation time 1262341693 ps
CPU time 9.34 seconds
Started Jul 09 05:41:28 PM PDT 24
Finished Jul 09 05:41:38 PM PDT 24
Peak memory 211288 kb
Host smart-9b8dee2b-177b-4754-b861-0ce3b6de4c7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730314219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1730314219
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2337154460
Short name T265
Test name
Test status
Simulation time 2407165788 ps
CPU time 27.39 seconds
Started Jul 09 05:41:26 PM PDT 24
Finished Jul 09 05:41:54 PM PDT 24
Peak memory 212988 kb
Host smart-d06537bb-25d3-4ac3-b327-797d2687eb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337154460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2337154460
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3825754018
Short name T209
Test name
Test status
Simulation time 61542369050 ps
CPU time 39.34 seconds
Started Jul 09 05:41:29 PM PDT 24
Finished Jul 09 05:42:09 PM PDT 24
Peak memory 213108 kb
Host smart-399cd995-2d05-49cb-9bfc-fc3afe7ab882
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825754018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3825754018
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2706949254
Short name T345
Test name
Test status
Simulation time 9005908056 ps
CPU time 15.44 seconds
Started Jul 09 05:41:26 PM PDT 24
Finished Jul 09 05:41:43 PM PDT 24
Peak memory 211440 kb
Host smart-24a3173e-aecb-4874-848d-bb3103ee7759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706949254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2706949254
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2728493423
Short name T155
Test name
Test status
Simulation time 4013417822 ps
CPU time 139.56 seconds
Started Jul 09 05:41:29 PM PDT 24
Finished Jul 09 05:43:50 PM PDT 24
Peak memory 234852 kb
Host smart-d4bd9dce-d37d-45f6-9898-084b9bc4b6c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728493423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2728493423
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1237044163
Short name T278
Test name
Test status
Simulation time 2237596293 ps
CPU time 17.7 seconds
Started Jul 09 05:41:27 PM PDT 24
Finished Jul 09 05:41:46 PM PDT 24
Peak memory 211996 kb
Host smart-1eeff6c7-4f93-4e06-b29c-2698f680bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237044163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1237044163
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3702599259
Short name T190
Test name
Test status
Simulation time 5080459963 ps
CPU time 12.73 seconds
Started Jul 09 05:41:33 PM PDT 24
Finished Jul 09 05:41:46 PM PDT 24
Peak memory 211320 kb
Host smart-138c3c3f-a025-4f93-a0a1-06ba0f846e82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3702599259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3702599259
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1998815892
Short name T324
Test name
Test status
Simulation time 2148963898 ps
CPU time 24.32 seconds
Started Jul 09 05:41:26 PM PDT 24
Finished Jul 09 05:41:51 PM PDT 24
Peak memory 213312 kb
Host smart-20811fde-12be-4093-ad6f-e58c1e70b762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998815892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1998815892
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.878424315
Short name T268
Test name
Test status
Simulation time 969084279 ps
CPU time 18.91 seconds
Started Jul 09 05:41:28 PM PDT 24
Finished Jul 09 05:41:48 PM PDT 24
Peak memory 213324 kb
Host smart-2bd66301-fd60-4c6b-b791-e1785008d62e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878424315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.878424315
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4050650274
Short name T256
Test name
Test status
Simulation time 3203102633 ps
CPU time 13.09 seconds
Started Jul 09 05:41:27 PM PDT 24
Finished Jul 09 05:41:41 PM PDT 24
Peak memory 211416 kb
Host smart-c0d69fac-0f6d-46be-ba9d-24872d710d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050650274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4050650274
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3217397862
Short name T40
Test name
Test status
Simulation time 71915641881 ps
CPU time 186.01 seconds
Started Jul 09 05:41:28 PM PDT 24
Finished Jul 09 05:44:35 PM PDT 24
Peak memory 238852 kb
Host smart-52f8c9b7-2326-4907-a090-f643570ad749
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217397862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3217397862
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2944639858
Short name T180
Test name
Test status
Simulation time 6892926724 ps
CPU time 29.5 seconds
Started Jul 09 05:41:37 PM PDT 24
Finished Jul 09 05:42:08 PM PDT 24
Peak memory 212276 kb
Host smart-8c067a7e-0fdb-4347-9f4c-9153a209a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944639858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2944639858
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1921511240
Short name T245
Test name
Test status
Simulation time 1408199224 ps
CPU time 12.99 seconds
Started Jul 09 05:41:27 PM PDT 24
Finished Jul 09 05:41:41 PM PDT 24
Peak memory 211384 kb
Host smart-c9d0d1e2-5a15-49f8-bf9c-c6ccd3e7ec18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921511240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1921511240
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2444353313
Short name T354
Test name
Test status
Simulation time 824364503 ps
CPU time 10.22 seconds
Started Jul 09 05:41:30 PM PDT 24
Finished Jul 09 05:41:41 PM PDT 24
Peak memory 213732 kb
Host smart-27bbadff-47a7-4284-988a-ff8d87c16c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444353313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2444353313
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.117813703
Short name T262
Test name
Test status
Simulation time 743405412 ps
CPU time 18.5 seconds
Started Jul 09 05:41:34 PM PDT 24
Finished Jul 09 05:41:53 PM PDT 24
Peak memory 214288 kb
Host smart-dfeb34cd-423c-400e-8e03-e8830f444e50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117813703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.117813703
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2358573994
Short name T63
Test name
Test status
Simulation time 848250727 ps
CPU time 10.31 seconds
Started Jul 09 05:41:26 PM PDT 24
Finished Jul 09 05:41:38 PM PDT 24
Peak memory 211316 kb
Host smart-846d8d84-f322-4f11-8f5f-f49edc6d9b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358573994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2358573994
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2833156084
Short name T45
Test name
Test status
Simulation time 26209587532 ps
CPU time 252.17 seconds
Started Jul 09 05:41:38 PM PDT 24
Finished Jul 09 05:45:51 PM PDT 24
Peak memory 212848 kb
Host smart-cd08b05c-9324-4de3-9c18-7c6b51e4eda5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833156084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2833156084
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2176675140
Short name T348
Test name
Test status
Simulation time 9942753399 ps
CPU time 23.38 seconds
Started Jul 09 05:41:30 PM PDT 24
Finished Jul 09 05:41:54 PM PDT 24
Peak memory 211440 kb
Host smart-dc11910e-dbbc-4813-b299-27e97ed31886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176675140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2176675140
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1226841567
Short name T363
Test name
Test status
Simulation time 1984623233 ps
CPU time 11.7 seconds
Started Jul 09 05:41:32 PM PDT 24
Finished Jul 09 05:41:44 PM PDT 24
Peak memory 211428 kb
Host smart-ad58532e-9a5f-49ca-801a-76845864dc23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226841567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1226841567
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1796656974
Short name T285
Test name
Test status
Simulation time 4957659404 ps
CPU time 18.06 seconds
Started Jul 09 05:41:28 PM PDT 24
Finished Jul 09 05:41:47 PM PDT 24
Peak memory 214152 kb
Host smart-c95eb276-e721-4589-935f-e43e023dc80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796656974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1796656974
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2096417958
Short name T171
Test name
Test status
Simulation time 752076476 ps
CPU time 10.82 seconds
Started Jul 09 05:41:33 PM PDT 24
Finished Jul 09 05:41:44 PM PDT 24
Peak memory 211248 kb
Host smart-4ab4f01d-6558-476c-94d2-643ba7c3041b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096417958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2096417958
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2439891056
Short name T188
Test name
Test status
Simulation time 1793045453 ps
CPU time 10.1 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:06 PM PDT 24
Peak memory 211276 kb
Host smart-8dba0d06-2556-4790-8d18-8546a520c7d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439891056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2439891056
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2890505726
Short name T275
Test name
Test status
Simulation time 1583512340 ps
CPU time 90.33 seconds
Started Jul 09 05:40:49 PM PDT 24
Finished Jul 09 05:42:21 PM PDT 24
Peak memory 212512 kb
Host smart-f01f213f-6ef0-498a-b536-7878e9e12c05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890505726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2890505726
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1809516888
Short name T246
Test name
Test status
Simulation time 1913627238 ps
CPU time 20.84 seconds
Started Jul 09 05:40:49 PM PDT 24
Finished Jul 09 05:41:11 PM PDT 24
Peak memory 212084 kb
Host smart-3f04d194-2b26-4131-934d-ad995dd7a783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809516888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1809516888
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1267475511
Short name T120
Test name
Test status
Simulation time 1843143858 ps
CPU time 5.38 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:41:00 PM PDT 24
Peak memory 211400 kb
Host smart-2638c3ce-3467-40d7-b203-95b9a9799fa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267475511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1267475511
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3710894047
Short name T30
Test name
Test status
Simulation time 9189316393 ps
CPU time 62.46 seconds
Started Jul 09 05:40:51 PM PDT 24
Finished Jul 09 05:41:54 PM PDT 24
Peak memory 238068 kb
Host smart-cda280d8-f4ac-495e-9eaf-75b95591f159
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710894047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3710894047
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2502122033
Short name T16
Test name
Test status
Simulation time 2188861211 ps
CPU time 22.97 seconds
Started Jul 09 05:40:56 PM PDT 24
Finished Jul 09 05:41:20 PM PDT 24
Peak memory 213732 kb
Host smart-94bb3f3c-9ef4-489e-afb9-7c041cd1ae98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502122033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2502122033
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4034947603
Short name T173
Test name
Test status
Simulation time 33648753437 ps
CPU time 131.19 seconds
Started Jul 09 05:40:52 PM PDT 24
Finished Jul 09 05:43:04 PM PDT 24
Peak memory 219384 kb
Host smart-2ca4f560-58fd-4fd7-b0b6-c76cc2ad95a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034947603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4034947603
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2281679774
Short name T13
Test name
Test status
Simulation time 239413352048 ps
CPU time 1058.46 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:58:32 PM PDT 24
Peak memory 231988 kb
Host smart-79211154-6d71-4dca-a9ab-57e051afd5fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281679774 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2281679774
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3555769714
Short name T145
Test name
Test status
Simulation time 1431368159 ps
CPU time 12.05 seconds
Started Jul 09 05:41:34 PM PDT 24
Finished Jul 09 05:41:47 PM PDT 24
Peak memory 211404 kb
Host smart-dbaa5ebc-f0d2-44fa-acac-dd5b2c67ef96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555769714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3555769714
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4262002660
Short name T154
Test name
Test status
Simulation time 8680862641 ps
CPU time 145.02 seconds
Started Jul 09 05:41:40 PM PDT 24
Finished Jul 09 05:44:06 PM PDT 24
Peak memory 236724 kb
Host smart-aa6c2e61-22bb-4fa8-818b-9447bfceac23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262002660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4262002660
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.423583165
Short name T331
Test name
Test status
Simulation time 9211837255 ps
CPU time 23.93 seconds
Started Jul 09 05:41:33 PM PDT 24
Finished Jul 09 05:41:57 PM PDT 24
Peak memory 212232 kb
Host smart-d9504b63-9349-4326-85c5-fe742842315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423583165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.423583165
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2253559806
Short name T125
Test name
Test status
Simulation time 375255675 ps
CPU time 5.36 seconds
Started Jul 09 05:41:40 PM PDT 24
Finished Jul 09 05:41:46 PM PDT 24
Peak memory 211260 kb
Host smart-d128864b-117c-4239-8992-e0bafee12d63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253559806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2253559806
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3904052029
Short name T38
Test name
Test status
Simulation time 3206964391 ps
CPU time 31.51 seconds
Started Jul 09 05:41:30 PM PDT 24
Finished Jul 09 05:42:02 PM PDT 24
Peak memory 213744 kb
Host smart-7b4d22b1-c7e1-4b36-880a-fbd8ea7f0ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904052029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3904052029
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1312534304
Short name T177
Test name
Test status
Simulation time 1368168843 ps
CPU time 30.81 seconds
Started Jul 09 05:41:35 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 214696 kb
Host smart-55ff20de-2859-4e71-b00a-eccb627f50ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312534304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1312534304
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.271180530
Short name T295
Test name
Test status
Simulation time 347011436 ps
CPU time 4.22 seconds
Started Jul 09 05:41:38 PM PDT 24
Finished Jul 09 05:41:43 PM PDT 24
Peak memory 211360 kb
Host smart-a174a785-cadc-4940-8f6c-6c0f8585a4b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271180530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.271180530
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1305311330
Short name T200
Test name
Test status
Simulation time 53089356581 ps
CPU time 195.95 seconds
Started Jul 09 05:41:31 PM PDT 24
Finished Jul 09 05:44:47 PM PDT 24
Peak memory 225708 kb
Host smart-84cc1688-7933-418c-99bc-02046194716d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305311330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1305311330
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1394244740
Short name T7
Test name
Test status
Simulation time 1101746603 ps
CPU time 16.53 seconds
Started Jul 09 05:41:32 PM PDT 24
Finished Jul 09 05:41:49 PM PDT 24
Peak memory 212012 kb
Host smart-351bba79-61e7-484e-b84c-04fb61336961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394244740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1394244740
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1991625142
Short name T320
Test name
Test status
Simulation time 138067397 ps
CPU time 6.23 seconds
Started Jul 09 05:41:37 PM PDT 24
Finished Jul 09 05:41:44 PM PDT 24
Peak memory 211300 kb
Host smart-43e91361-8b6d-46cc-aa2b-6c37326828f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991625142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1991625142
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3401251172
Short name T75
Test name
Test status
Simulation time 6494581350 ps
CPU time 32.23 seconds
Started Jul 09 05:41:40 PM PDT 24
Finished Jul 09 05:42:13 PM PDT 24
Peak memory 213672 kb
Host smart-2208fbbd-fa40-40bb-afd9-2b21ea7f731a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401251172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3401251172
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.159253078
Short name T46
Test name
Test status
Simulation time 2422498081 ps
CPU time 29.13 seconds
Started Jul 09 05:41:37 PM PDT 24
Finished Jul 09 05:42:07 PM PDT 24
Peak memory 215556 kb
Host smart-5348cd7d-ed68-4175-ac5c-6142dce7c956
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159253078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.159253078
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3873529196
Short name T233
Test name
Test status
Simulation time 5319745087 ps
CPU time 11.54 seconds
Started Jul 09 05:41:43 PM PDT 24
Finished Jul 09 05:41:55 PM PDT 24
Peak memory 211400 kb
Host smart-bba0ed85-1796-462b-a808-7306cd96b911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873529196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3873529196
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.52247771
Short name T321
Test name
Test status
Simulation time 28761418938 ps
CPU time 314.14 seconds
Started Jul 09 05:45:57 PM PDT 24
Finished Jul 09 05:51:13 PM PDT 24
Peak memory 212636 kb
Host smart-df0f21b0-ea12-4d52-a0ff-50a764652637
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52247771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_co
rrupt_sig_fatal_chk.52247771
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2845860480
Short name T29
Test name
Test status
Simulation time 7790260904 ps
CPU time 19.12 seconds
Started Jul 09 05:41:37 PM PDT 24
Finished Jul 09 05:41:57 PM PDT 24
Peak memory 212368 kb
Host smart-2b952606-63a0-4aa8-97cf-6b41dae7a7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845860480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2845860480
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2991782337
Short name T36
Test name
Test status
Simulation time 2795714459 ps
CPU time 13.81 seconds
Started Jul 09 05:41:37 PM PDT 24
Finished Jul 09 05:41:51 PM PDT 24
Peak memory 211364 kb
Host smart-26c39562-b260-4b43-98d6-e329cbd859e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991782337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2991782337
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1088548563
Short name T302
Test name
Test status
Simulation time 5409392118 ps
CPU time 30.88 seconds
Started Jul 09 05:41:34 PM PDT 24
Finished Jul 09 05:42:05 PM PDT 24
Peak memory 213728 kb
Host smart-3b77855c-6f3d-41c4-9f06-08469d86cadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088548563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1088548563
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.533696795
Short name T230
Test name
Test status
Simulation time 388825016 ps
CPU time 23.15 seconds
Started Jul 09 05:41:34 PM PDT 24
Finished Jul 09 05:41:58 PM PDT 24
Peak memory 215024 kb
Host smart-2862f298-5c6d-4a19-9646-7c4b4a90ede5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533696795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.533696795
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1475143837
Short name T228
Test name
Test status
Simulation time 660061253 ps
CPU time 8.14 seconds
Started Jul 09 05:41:40 PM PDT 24
Finished Jul 09 05:41:49 PM PDT 24
Peak memory 211264 kb
Host smart-75405c86-c4e3-401f-892e-1122a1c6e8b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475143837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1475143837
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3028706352
Short name T156
Test name
Test status
Simulation time 322261742422 ps
CPU time 242.36 seconds
Started Jul 09 05:41:37 PM PDT 24
Finished Jul 09 05:45:40 PM PDT 24
Peak memory 212644 kb
Host smart-993b95bc-572a-4ce0-a314-cdbe9624fb2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028706352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3028706352
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1450209145
Short name T131
Test name
Test status
Simulation time 15780642666 ps
CPU time 24.05 seconds
Started Jul 09 05:41:36 PM PDT 24
Finished Jul 09 05:42:01 PM PDT 24
Peak memory 212256 kb
Host smart-c1ab1555-1df1-4bca-b48e-c930acee6091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450209145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1450209145
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3775650729
Short name T142
Test name
Test status
Simulation time 865317985 ps
CPU time 6.8 seconds
Started Jul 09 05:41:38 PM PDT 24
Finished Jul 09 05:41:46 PM PDT 24
Peak memory 211348 kb
Host smart-5dca0de8-2164-419c-adce-d0c3c232e2aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3775650729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3775650729
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.396539831
Short name T146
Test name
Test status
Simulation time 6816759780 ps
CPU time 32.77 seconds
Started Jul 09 05:41:36 PM PDT 24
Finished Jul 09 05:42:09 PM PDT 24
Peak memory 214156 kb
Host smart-0ed2e1d2-ae6f-43c7-a775-1758315e095e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396539831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.396539831
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.714205006
Short name T327
Test name
Test status
Simulation time 15579236627 ps
CPU time 49.29 seconds
Started Jul 09 05:41:40 PM PDT 24
Finished Jul 09 05:42:30 PM PDT 24
Peak memory 218564 kb
Host smart-a7d77d37-c152-4411-8b26-dd83b78aba3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714205006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.714205006
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.275678693
Short name T243
Test name
Test status
Simulation time 9093314952 ps
CPU time 224.37 seconds
Started Jul 09 05:41:39 PM PDT 24
Finished Jul 09 05:45:24 PM PDT 24
Peak memory 228636 kb
Host smart-78c7d619-65f6-482a-8065-5c721576cb0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275678693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.275678693
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3561712563
Short name T307
Test name
Test status
Simulation time 168398842 ps
CPU time 9.48 seconds
Started Jul 09 05:41:34 PM PDT 24
Finished Jul 09 05:41:44 PM PDT 24
Peak memory 211964 kb
Host smart-e0daf675-523d-4193-a8dc-45ec51340d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561712563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3561712563
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1036154038
Short name T240
Test name
Test status
Simulation time 1004749106 ps
CPU time 5.44 seconds
Started Jul 09 05:41:43 PM PDT 24
Finished Jul 09 05:41:49 PM PDT 24
Peak memory 211380 kb
Host smart-c393ec73-a8b0-46ba-8045-0c26996020e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1036154038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1036154038
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1470180557
Short name T19
Test name
Test status
Simulation time 725188651 ps
CPU time 9.9 seconds
Started Jul 09 05:41:36 PM PDT 24
Finished Jul 09 05:41:47 PM PDT 24
Peak memory 213340 kb
Host smart-b8bba933-1cb4-4638-b723-490b1a38281c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470180557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1470180557
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2948557908
Short name T300
Test name
Test status
Simulation time 4385033515 ps
CPU time 22.54 seconds
Started Jul 09 05:41:36 PM PDT 24
Finished Jul 09 05:41:59 PM PDT 24
Peak memory 214584 kb
Host smart-7aada23f-3006-4a7e-8706-17f3d7d6b1a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948557908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2948557908
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3588214764
Short name T185
Test name
Test status
Simulation time 7847454436 ps
CPU time 16.48 seconds
Started Jul 09 05:41:43 PM PDT 24
Finished Jul 09 05:42:00 PM PDT 24
Peak memory 211400 kb
Host smart-18a4077d-f00c-4954-a7f9-433e99b6a5f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588214764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3588214764
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.209835475
Short name T42
Test name
Test status
Simulation time 76380806963 ps
CPU time 404.63 seconds
Started Jul 09 05:41:38 PM PDT 24
Finished Jul 09 05:48:23 PM PDT 24
Peak memory 225696 kb
Host smart-5e351ecf-34f3-4790-985c-dbfba13cb09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209835475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.209835475
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4228423406
Short name T121
Test name
Test status
Simulation time 13003025299 ps
CPU time 26.8 seconds
Started Jul 09 05:41:34 PM PDT 24
Finished Jul 09 05:42:02 PM PDT 24
Peak memory 212364 kb
Host smart-89f5b771-8679-4e3a-8bb7-f991c809bb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228423406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4228423406
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.262290985
Short name T203
Test name
Test status
Simulation time 1975841944 ps
CPU time 11.04 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 05:41:54 PM PDT 24
Peak memory 211344 kb
Host smart-3cbad5cb-ba6b-430d-98d2-4ba9ffd231b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=262290985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.262290985
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.328863419
Short name T79
Test name
Test status
Simulation time 12382969888 ps
CPU time 36.18 seconds
Started Jul 09 05:41:41 PM PDT 24
Finished Jul 09 05:42:18 PM PDT 24
Peak memory 213316 kb
Host smart-ecab12ff-c715-4c65-9bcc-c804c3bb0cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328863419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.328863419
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3227462240
Short name T340
Test name
Test status
Simulation time 14426484116 ps
CPU time 36.77 seconds
Started Jul 09 05:41:37 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 214676 kb
Host smart-aa3c209a-2c8b-4df7-9ada-da4583a9daff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227462240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3227462240
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1887701515
Short name T339
Test name
Test status
Simulation time 406564235645 ps
CPU time 4022.51 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 06:48:46 PM PDT 24
Peak memory 247228 kb
Host smart-a69af29b-7f98-472b-9738-6f49c802cca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887701515 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1887701515
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3128131991
Short name T192
Test name
Test status
Simulation time 1459474703 ps
CPU time 8.72 seconds
Started Jul 09 05:41:36 PM PDT 24
Finished Jul 09 05:41:46 PM PDT 24
Peak memory 211352 kb
Host smart-37c74e94-2909-4ca6-b64a-3fcebb487d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128131991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3128131991
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.403019893
Short name T257
Test name
Test status
Simulation time 16462223891 ps
CPU time 274.36 seconds
Started Jul 09 05:41:40 PM PDT 24
Finished Jul 09 05:46:16 PM PDT 24
Peak memory 224740 kb
Host smart-a4d4214e-de47-48d9-a748-14692cef7329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403019893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.403019893
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1226899775
Short name T211
Test name
Test status
Simulation time 270639785 ps
CPU time 9.55 seconds
Started Jul 09 05:41:41 PM PDT 24
Finished Jul 09 05:41:52 PM PDT 24
Peak memory 212352 kb
Host smart-624a319b-af5d-45bf-95f4-3c9082a87b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226899775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1226899775
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1853944689
Short name T259
Test name
Test status
Simulation time 179729681 ps
CPU time 5.42 seconds
Started Jul 09 05:41:43 PM PDT 24
Finished Jul 09 05:41:49 PM PDT 24
Peak memory 211384 kb
Host smart-004892b4-5f97-4960-93e6-a94e6af4ed2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853944689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1853944689
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3279739059
Short name T33
Test name
Test status
Simulation time 7060599566 ps
CPU time 37.46 seconds
Started Jul 09 05:41:36 PM PDT 24
Finished Jul 09 05:42:14 PM PDT 24
Peak memory 213784 kb
Host smart-5688b46c-abb1-48fa-93b9-b2ee26c9510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279739059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3279739059
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3077580648
Short name T291
Test name
Test status
Simulation time 6554269852 ps
CPU time 34.81 seconds
Started Jul 09 05:41:40 PM PDT 24
Finished Jul 09 05:42:15 PM PDT 24
Peak memory 217948 kb
Host smart-cad3c79e-c386-4043-909e-650aeff1d739
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077580648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3077580648
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.108476937
Short name T264
Test name
Test status
Simulation time 254686892 ps
CPU time 6.35 seconds
Started Jul 09 05:41:43 PM PDT 24
Finished Jul 09 05:41:51 PM PDT 24
Peak memory 211352 kb
Host smart-aaa75f26-d3e1-4efc-935e-9328d34f0483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108476937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.108476937
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2929171780
Short name T164
Test name
Test status
Simulation time 35990898572 ps
CPU time 154.85 seconds
Started Jul 09 05:41:40 PM PDT 24
Finished Jul 09 05:44:15 PM PDT 24
Peak memory 213944 kb
Host smart-47a920f6-ca8a-4280-9359-d59b30ce6558
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929171780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2929171780
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1958541628
Short name T344
Test name
Test status
Simulation time 3402201733 ps
CPU time 29.51 seconds
Started Jul 09 05:41:37 PM PDT 24
Finished Jul 09 05:42:08 PM PDT 24
Peak memory 211888 kb
Host smart-1a99e240-8e44-45af-bec6-52d2e73bf0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958541628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1958541628
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2338467759
Short name T358
Test name
Test status
Simulation time 2659258129 ps
CPU time 9.44 seconds
Started Jul 09 05:41:37 PM PDT 24
Finished Jul 09 05:41:47 PM PDT 24
Peak memory 211444 kb
Host smart-02405016-7aeb-4491-92b9-1c9dfe642ae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338467759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2338467759
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.393067882
Short name T34
Test name
Test status
Simulation time 3086269430 ps
CPU time 18.83 seconds
Started Jul 09 05:41:41 PM PDT 24
Finished Jul 09 05:42:01 PM PDT 24
Peak memory 213836 kb
Host smart-f16b4dad-240d-4ed9-8b33-72f6e0b97551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393067882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.393067882
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2136489443
Short name T117
Test name
Test status
Simulation time 844973087 ps
CPU time 17.45 seconds
Started Jul 09 05:41:37 PM PDT 24
Finished Jul 09 05:41:55 PM PDT 24
Peak memory 214560 kb
Host smart-bad176d6-6405-4e0b-af17-ef0f729154f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136489443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2136489443
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4176790423
Short name T279
Test name
Test status
Simulation time 903848327 ps
CPU time 9.67 seconds
Started Jul 09 05:41:43 PM PDT 24
Finished Jul 09 05:41:53 PM PDT 24
Peak memory 211340 kb
Host smart-5e4f46d8-502f-443f-bff2-3fe97e4d7083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176790423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4176790423
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.827053722
Short name T277
Test name
Test status
Simulation time 2749608909 ps
CPU time 87.69 seconds
Started Jul 09 05:41:45 PM PDT 24
Finished Jul 09 05:43:13 PM PDT 24
Peak memory 227296 kb
Host smart-b55b2b15-93cf-4f82-ae88-3c860595b4da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827053722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.827053722
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.675172946
Short name T124
Test name
Test status
Simulation time 1841362578 ps
CPU time 9.52 seconds
Started Jul 09 05:41:41 PM PDT 24
Finished Jul 09 05:41:51 PM PDT 24
Peak memory 211120 kb
Host smart-70742a82-226e-4618-a4aa-29f8205929d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675172946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.675172946
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1552050197
Short name T241
Test name
Test status
Simulation time 1262791666 ps
CPU time 13.26 seconds
Started Jul 09 05:41:38 PM PDT 24
Finished Jul 09 05:41:52 PM PDT 24
Peak memory 211400 kb
Host smart-57d2df30-81aa-4041-8879-1a0e1d23fd79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552050197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1552050197
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3845101446
Short name T254
Test name
Test status
Simulation time 8909736319 ps
CPU time 23.24 seconds
Started Jul 09 05:41:41 PM PDT 24
Finished Jul 09 05:42:05 PM PDT 24
Peak memory 213900 kb
Host smart-83b24706-4719-4832-b7fc-08da9a327a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845101446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3845101446
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.478684155
Short name T196
Test name
Test status
Simulation time 2650680020 ps
CPU time 26.67 seconds
Started Jul 09 05:41:39 PM PDT 24
Finished Jul 09 05:42:06 PM PDT 24
Peak memory 213096 kb
Host smart-680558d5-b944-4220-a7d5-e781b24465c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478684155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.478684155
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3507784991
Short name T25
Test name
Test status
Simulation time 3991276691 ps
CPU time 12.31 seconds
Started Jul 09 05:41:43 PM PDT 24
Finished Jul 09 05:41:56 PM PDT 24
Peak memory 211388 kb
Host smart-d959f28f-8ad6-4ea9-9df8-c6a4c31474f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507784991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3507784991
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1899193892
Short name T232
Test name
Test status
Simulation time 7174318053 ps
CPU time 114.65 seconds
Started Jul 09 05:41:43 PM PDT 24
Finished Jul 09 05:43:38 PM PDT 24
Peak memory 237868 kb
Host smart-ba5d9394-f62f-4d8c-8de0-b58b89f1d13e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899193892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1899193892
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3878052827
Short name T182
Test name
Test status
Simulation time 14282685166 ps
CPU time 28.41 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 05:42:11 PM PDT 24
Peak memory 211456 kb
Host smart-c921d3cc-2bc3-42e0-8d32-b6cba1a95e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878052827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3878052827
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3485600870
Short name T116
Test name
Test status
Simulation time 1769538043 ps
CPU time 15.04 seconds
Started Jul 09 05:41:41 PM PDT 24
Finished Jul 09 05:41:57 PM PDT 24
Peak memory 211400 kb
Host smart-d5b471ef-39e1-4147-a91a-fc52dc87f2d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485600870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3485600870
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.643889306
Short name T193
Test name
Test status
Simulation time 8203018599 ps
CPU time 23.36 seconds
Started Jul 09 05:41:42 PM PDT 24
Finished Jul 09 05:42:06 PM PDT 24
Peak memory 214876 kb
Host smart-16b9671d-4eb8-45ef-9dc9-d16fcc5242ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643889306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.643889306
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3406348405
Short name T353
Test name
Test status
Simulation time 1862754565 ps
CPU time 14.37 seconds
Started Jul 09 05:41:38 PM PDT 24
Finished Jul 09 05:41:53 PM PDT 24
Peak memory 211952 kb
Host smart-cc211cbd-9a20-4d3a-8a56-96a1e0c6de17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406348405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3406348405
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2306813589
Short name T312
Test name
Test status
Simulation time 6663064379 ps
CPU time 14.08 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:41:08 PM PDT 24
Peak memory 211404 kb
Host smart-f5b1fa7b-2ab5-469e-9bfe-747665b4ddec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306813589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2306813589
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3792080311
Short name T319
Test name
Test status
Simulation time 21341037326 ps
CPU time 223.52 seconds
Started Jul 09 05:40:58 PM PDT 24
Finished Jul 09 05:44:42 PM PDT 24
Peak memory 236776 kb
Host smart-9f14c85c-8ed5-4996-b166-40e0c8302c52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792080311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3792080311
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.225198151
Short name T224
Test name
Test status
Simulation time 27338598982 ps
CPU time 30.98 seconds
Started Jul 09 05:40:58 PM PDT 24
Finished Jul 09 05:41:29 PM PDT 24
Peak memory 212240 kb
Host smart-1aa41f08-cf38-427d-b2e0-087644a5a9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225198151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.225198151
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2099439424
Short name T197
Test name
Test status
Simulation time 188437840 ps
CPU time 5.64 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:40:57 PM PDT 24
Peak memory 211388 kb
Host smart-d35dafab-3b2b-47ba-8f78-aa2f4d3955d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099439424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2099439424
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3172087220
Short name T215
Test name
Test status
Simulation time 185139963 ps
CPU time 10.23 seconds
Started Jul 09 05:40:51 PM PDT 24
Finished Jul 09 05:41:02 PM PDT 24
Peak memory 213472 kb
Host smart-17903e06-ecae-41ab-af87-153c7e5e3b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172087220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3172087220
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.389586848
Short name T132
Test name
Test status
Simulation time 3798417917 ps
CPU time 22.65 seconds
Started Jul 09 05:40:52 PM PDT 24
Finished Jul 09 05:41:15 PM PDT 24
Peak memory 214624 kb
Host smart-0ca968e8-e53c-456f-93e3-03039f8e8956
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389586848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.389586848
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1732972216
Short name T281
Test name
Test status
Simulation time 89896575 ps
CPU time 4.33 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:00 PM PDT 24
Peak memory 211240 kb
Host smart-98f9185a-d703-4d8d-b818-e98262077f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732972216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1732972216
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.486329781
Short name T206
Test name
Test status
Simulation time 1589413877 ps
CPU time 107.09 seconds
Started Jul 09 05:40:52 PM PDT 24
Finished Jul 09 05:42:40 PM PDT 24
Peak memory 228572 kb
Host smart-46e2dc1d-21fc-4f02-bd43-68df05b25b87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486329781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.486329781
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.395823759
Short name T239
Test name
Test status
Simulation time 5963648984 ps
CPU time 26.27 seconds
Started Jul 09 05:40:52 PM PDT 24
Finished Jul 09 05:41:19 PM PDT 24
Peak memory 212556 kb
Host smart-bbe0e0f3-76a0-4510-b28b-a788d192afd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395823759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.395823759
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2378123440
Short name T313
Test name
Test status
Simulation time 5438277110 ps
CPU time 14.88 seconds
Started Jul 09 05:40:51 PM PDT 24
Finished Jul 09 05:41:07 PM PDT 24
Peak memory 211460 kb
Host smart-25d3f236-523a-463f-b65b-2e0a52c7abc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2378123440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2378123440
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1277363840
Short name T212
Test name
Test status
Simulation time 4636985584 ps
CPU time 17.36 seconds
Started Jul 09 05:40:53 PM PDT 24
Finished Jul 09 05:41:12 PM PDT 24
Peak memory 213968 kb
Host smart-3c53eab3-32d6-41d4-b0c3-25734d37b50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277363840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1277363840
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3583754053
Short name T290
Test name
Test status
Simulation time 8502098838 ps
CPU time 29.98 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:26 PM PDT 24
Peak memory 215316 kb
Host smart-41f68d55-a3d9-4c68-9132-ae7d77b7db47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583754053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3583754053
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2768570845
Short name T65
Test name
Test status
Simulation time 1896671111 ps
CPU time 9.82 seconds
Started Jul 09 05:40:59 PM PDT 24
Finished Jul 09 05:41:10 PM PDT 24
Peak memory 211300 kb
Host smart-f624828a-b4c8-4fee-9def-0f04da015629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768570845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2768570845
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2383363158
Short name T304
Test name
Test status
Simulation time 84483176103 ps
CPU time 278.66 seconds
Started Jul 09 05:40:49 PM PDT 24
Finished Jul 09 05:45:29 PM PDT 24
Peak memory 236812 kb
Host smart-93a7a38d-f6e6-48cb-a4c7-4afad7f8f57e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383363158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2383363158
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4111419857
Short name T28
Test name
Test status
Simulation time 874281431 ps
CPU time 9.37 seconds
Started Jul 09 05:40:58 PM PDT 24
Finished Jul 09 05:41:09 PM PDT 24
Peak memory 211864 kb
Host smart-33e9b0ec-3ad2-46bb-acc3-2c8ea8349c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111419857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4111419857
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1408088828
Short name T133
Test name
Test status
Simulation time 233379966 ps
CPU time 7.05 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:40:59 PM PDT 24
Peak memory 211396 kb
Host smart-d817f891-ed2d-46c9-9c4e-229458316ff8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408088828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1408088828
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2414557111
Short name T362
Test name
Test status
Simulation time 11004644223 ps
CPU time 25.67 seconds
Started Jul 09 05:40:50 PM PDT 24
Finished Jul 09 05:41:17 PM PDT 24
Peak memory 214172 kb
Host smart-75283f2e-2be0-49dd-a6c5-4867cb5b45de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414557111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2414557111
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2811667085
Short name T143
Test name
Test status
Simulation time 2898599385 ps
CPU time 52.66 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:48 PM PDT 24
Peak memory 217392 kb
Host smart-30fa5e57-4867-4f1e-b5c3-2c3dbb1dfd16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811667085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2811667085
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3020690126
Short name T297
Test name
Test status
Simulation time 334346489 ps
CPU time 4.26 seconds
Started Jul 09 05:40:57 PM PDT 24
Finished Jul 09 05:41:02 PM PDT 24
Peak memory 211352 kb
Host smart-66ced1ea-a3fc-4958-bcd6-0476c49fa396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020690126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3020690126
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3724838207
Short name T5
Test name
Test status
Simulation time 17738065649 ps
CPU time 151.31 seconds
Started Jul 09 05:40:56 PM PDT 24
Finished Jul 09 05:43:28 PM PDT 24
Peak memory 237068 kb
Host smart-f6f72633-80c4-4bf5-847b-ca5132ba572a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724838207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3724838207
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2218728359
Short name T162
Test name
Test status
Simulation time 1741508926 ps
CPU time 19.15 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:14 PM PDT 24
Peak memory 212192 kb
Host smart-2dd55174-0494-4ffc-bd2d-cda3ba935a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218728359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2218728359
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4278951182
Short name T328
Test name
Test status
Simulation time 280279393 ps
CPU time 5.3 seconds
Started Jul 09 05:40:59 PM PDT 24
Finished Jul 09 05:41:05 PM PDT 24
Peak memory 210924 kb
Host smart-8f89bf2c-918f-4579-8fae-46cd8444e311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4278951182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4278951182
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2933258969
Short name T160
Test name
Test status
Simulation time 8194316582 ps
CPU time 27.45 seconds
Started Jul 09 05:40:52 PM PDT 24
Finished Jul 09 05:41:20 PM PDT 24
Peak memory 214292 kb
Host smart-73a8c8d2-fdfb-41cf-aec6-2369d1f1c579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933258969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2933258969
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2013506459
Short name T229
Test name
Test status
Simulation time 2691527421 ps
CPU time 29.75 seconds
Started Jul 09 05:40:57 PM PDT 24
Finished Jul 09 05:41:28 PM PDT 24
Peak memory 213988 kb
Host smart-dae357ac-dbd6-4121-a61c-a8e3614835df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013506459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2013506459
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3743246128
Short name T176
Test name
Test status
Simulation time 5448705761 ps
CPU time 14.86 seconds
Started Jul 09 05:40:56 PM PDT 24
Finished Jul 09 05:41:11 PM PDT 24
Peak memory 211396 kb
Host smart-c9e82f98-22e1-493f-8475-8cc6fe85fbb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743246128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3743246128
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2730622191
Short name T271
Test name
Test status
Simulation time 48656388720 ps
CPU time 444.88 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:48:20 PM PDT 24
Peak memory 224796 kb
Host smart-19ca6e66-4d49-4785-80f0-144b94703d67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730622191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2730622191
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1623602787
Short name T250
Test name
Test status
Simulation time 4228213445 ps
CPU time 32.89 seconds
Started Jul 09 05:40:59 PM PDT 24
Finished Jul 09 05:41:33 PM PDT 24
Peak memory 212016 kb
Host smart-60b01968-7926-4988-8806-a636516a365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623602787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1623602787
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1640707083
Short name T47
Test name
Test status
Simulation time 15619121263 ps
CPU time 14.41 seconds
Started Jul 09 05:40:56 PM PDT 24
Finished Jul 09 05:41:11 PM PDT 24
Peak memory 211392 kb
Host smart-1c19bdeb-1ea0-4d2b-9c3d-9ecf410ba80b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640707083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1640707083
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2669599832
Short name T303
Test name
Test status
Simulation time 930219646 ps
CPU time 15.02 seconds
Started Jul 09 05:41:03 PM PDT 24
Finished Jul 09 05:41:18 PM PDT 24
Peak memory 213256 kb
Host smart-e5da3c09-0202-43db-af72-6f9415b5147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669599832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2669599832
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2940025242
Short name T137
Test name
Test status
Simulation time 11681440035 ps
CPU time 26.52 seconds
Started Jul 09 05:40:54 PM PDT 24
Finished Jul 09 05:41:22 PM PDT 24
Peak memory 214052 kb
Host smart-aa0c3bd9-2ffc-4fca-8963-eee154969d2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940025242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2940025242
Directory /workspace/9.rom_ctrl_stress_all/latest
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