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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.67 100.00 98.28 97.45 98.37


Total test records in report: 461
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T299 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.985311830 Jul 10 06:02:28 PM PDT 24 Jul 10 06:02:41 PM PDT 24 2288853546 ps
T300 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3155753554 Jul 10 06:02:44 PM PDT 24 Jul 10 06:03:01 PM PDT 24 4148896023 ps
T50 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2226790396 Jul 10 06:02:52 PM PDT 24 Jul 10 08:38:51 PM PDT 24 295470098279 ps
T301 /workspace/coverage/default/32.rom_ctrl_stress_all.3338725150 Jul 10 06:02:43 PM PDT 24 Jul 10 06:03:17 PM PDT 24 12923054489 ps
T302 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3510956416 Jul 10 06:02:24 PM PDT 24 Jul 10 06:02:35 PM PDT 24 793316280 ps
T303 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3448790357 Jul 10 06:02:22 PM PDT 24 Jul 10 06:02:33 PM PDT 24 172511512 ps
T304 /workspace/coverage/default/4.rom_ctrl_stress_all.603067616 Jul 10 06:02:12 PM PDT 24 Jul 10 06:02:49 PM PDT 24 12738528289 ps
T305 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2958300603 Jul 10 06:03:07 PM PDT 24 Jul 10 06:04:27 PM PDT 24 26407528820 ps
T306 /workspace/coverage/default/37.rom_ctrl_stress_all.4169816687 Jul 10 06:03:00 PM PDT 24 Jul 10 06:03:22 PM PDT 24 10927845250 ps
T307 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.723675317 Jul 10 06:02:11 PM PDT 24 Jul 10 06:02:36 PM PDT 24 2728742951 ps
T308 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3664067702 Jul 10 06:02:33 PM PDT 24 Jul 10 06:03:09 PM PDT 24 12612123526 ps
T309 /workspace/coverage/default/38.rom_ctrl_alert_test.4131050567 Jul 10 06:03:10 PM PDT 24 Jul 10 06:03:24 PM PDT 24 2815303665 ps
T310 /workspace/coverage/default/35.rom_ctrl_smoke.523292335 Jul 10 06:02:54 PM PDT 24 Jul 10 06:03:30 PM PDT 24 15249890610 ps
T311 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1976292527 Jul 10 06:02:38 PM PDT 24 Jul 10 06:05:46 PM PDT 24 58495919024 ps
T312 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3250491264 Jul 10 06:02:14 PM PDT 24 Jul 10 06:04:48 PM PDT 24 59462969071 ps
T313 /workspace/coverage/default/49.rom_ctrl_stress_all.973373037 Jul 10 06:03:24 PM PDT 24 Jul 10 06:04:01 PM PDT 24 11496723015 ps
T314 /workspace/coverage/default/23.rom_ctrl_smoke.3259497313 Jul 10 06:02:37 PM PDT 24 Jul 10 06:03:02 PM PDT 24 3979189879 ps
T315 /workspace/coverage/default/11.rom_ctrl_smoke.1465931171 Jul 10 06:02:24 PM PDT 24 Jul 10 06:02:49 PM PDT 24 4477491084 ps
T316 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1949484923 Jul 10 06:02:17 PM PDT 24 Jul 10 06:02:28 PM PDT 24 2615271036 ps
T317 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3546448343 Jul 10 06:02:53 PM PDT 24 Jul 10 06:03:09 PM PDT 24 6699750106 ps
T318 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3683447859 Jul 10 06:03:00 PM PDT 24 Jul 10 06:10:11 PM PDT 24 80039758513 ps
T319 /workspace/coverage/default/12.rom_ctrl_alert_test.1247355089 Jul 10 06:02:31 PM PDT 24 Jul 10 06:02:46 PM PDT 24 1612559567 ps
T320 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1085087380 Jul 10 06:02:31 PM PDT 24 Jul 10 06:02:47 PM PDT 24 1610587432 ps
T321 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2382339180 Jul 10 06:03:18 PM PDT 24 Jul 10 06:06:45 PM PDT 24 9822552216 ps
T322 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2029432923 Jul 10 06:02:30 PM PDT 24 Jul 10 06:02:50 PM PDT 24 5269159757 ps
T323 /workspace/coverage/default/36.rom_ctrl_smoke.1061681760 Jul 10 06:03:01 PM PDT 24 Jul 10 06:03:13 PM PDT 24 188323778 ps
T324 /workspace/coverage/default/9.rom_ctrl_stress_all.437951288 Jul 10 06:02:27 PM PDT 24 Jul 10 06:02:39 PM PDT 24 545012618 ps
T325 /workspace/coverage/default/17.rom_ctrl_alert_test.1610730310 Jul 10 06:02:30 PM PDT 24 Jul 10 06:02:43 PM PDT 24 2222007306 ps
T326 /workspace/coverage/default/2.rom_ctrl_smoke.3741823213 Jul 10 06:02:08 PM PDT 24 Jul 10 06:02:38 PM PDT 24 12480616467 ps
T327 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2893521270 Jul 10 06:02:37 PM PDT 24 Jul 10 06:02:57 PM PDT 24 1568259200 ps
T328 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.694103288 Jul 10 06:02:25 PM PDT 24 Jul 10 06:04:43 PM PDT 24 10381242558 ps
T329 /workspace/coverage/default/23.rom_ctrl_alert_test.289359266 Jul 10 06:02:41 PM PDT 24 Jul 10 06:02:54 PM PDT 24 4993231969 ps
T330 /workspace/coverage/default/25.rom_ctrl_alert_test.1122814510 Jul 10 06:02:45 PM PDT 24 Jul 10 06:02:59 PM PDT 24 5410093323 ps
T15 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3122605817 Jul 10 06:02:32 PM PDT 24 Jul 10 06:23:58 PM PDT 24 77852029987 ps
T331 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.41087281 Jul 10 06:03:24 PM PDT 24 Jul 10 06:03:40 PM PDT 24 5663522229 ps
T332 /workspace/coverage/default/45.rom_ctrl_alert_test.1132019770 Jul 10 06:03:17 PM PDT 24 Jul 10 06:03:22 PM PDT 24 346822390 ps
T333 /workspace/coverage/default/34.rom_ctrl_stress_all.3013232894 Jul 10 06:02:55 PM PDT 24 Jul 10 06:03:33 PM PDT 24 6831329587 ps
T334 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4128037962 Jul 10 06:03:21 PM PDT 24 Jul 10 06:05:31 PM PDT 24 1881429623 ps
T335 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2179754614 Jul 10 06:03:11 PM PDT 24 Jul 10 06:08:24 PM PDT 24 68796937925 ps
T336 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.904861919 Jul 10 06:02:27 PM PDT 24 Jul 10 06:07:45 PM PDT 24 28438842003 ps
T337 /workspace/coverage/default/21.rom_ctrl_alert_test.2505582456 Jul 10 06:02:39 PM PDT 24 Jul 10 06:02:46 PM PDT 24 92855977 ps
T338 /workspace/coverage/default/24.rom_ctrl_smoke.2271150394 Jul 10 06:02:35 PM PDT 24 Jul 10 06:03:00 PM PDT 24 4812727309 ps
T339 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.174579275 Jul 10 06:02:44 PM PDT 24 Jul 10 06:03:10 PM PDT 24 9613806233 ps
T340 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.922651326 Jul 10 06:03:11 PM PDT 24 Jul 10 06:04:43 PM PDT 24 6062611995 ps
T341 /workspace/coverage/default/19.rom_ctrl_alert_test.3812929476 Jul 10 06:02:38 PM PDT 24 Jul 10 06:02:47 PM PDT 24 1745879650 ps
T342 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.511978740 Jul 10 06:02:36 PM PDT 24 Jul 10 06:02:58 PM PDT 24 2784267791 ps
T343 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.625854206 Jul 10 06:03:16 PM PDT 24 Jul 10 06:03:23 PM PDT 24 428741472 ps
T344 /workspace/coverage/default/24.rom_ctrl_stress_all.2583870113 Jul 10 06:02:38 PM PDT 24 Jul 10 06:03:26 PM PDT 24 828981641 ps
T345 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1589008243 Jul 10 06:02:42 PM PDT 24 Jul 10 06:02:58 PM PDT 24 2639865289 ps
T346 /workspace/coverage/default/13.rom_ctrl_alert_test.126210225 Jul 10 06:02:31 PM PDT 24 Jul 10 06:02:41 PM PDT 24 375365047 ps
T347 /workspace/coverage/default/36.rom_ctrl_stress_all.3155400205 Jul 10 06:03:00 PM PDT 24 Jul 10 06:03:09 PM PDT 24 756919058 ps
T348 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3860503741 Jul 10 06:03:07 PM PDT 24 Jul 10 06:03:14 PM PDT 24 193064910 ps
T349 /workspace/coverage/default/26.rom_ctrl_smoke.2257113908 Jul 10 06:02:45 PM PDT 24 Jul 10 06:03:21 PM PDT 24 13840790765 ps
T350 /workspace/coverage/default/27.rom_ctrl_alert_test.3645194906 Jul 10 06:02:43 PM PDT 24 Jul 10 06:02:50 PM PDT 24 129069372 ps
T351 /workspace/coverage/default/19.rom_ctrl_smoke.36771077 Jul 10 06:02:38 PM PDT 24 Jul 10 06:02:54 PM PDT 24 2913067022 ps
T352 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.655326124 Jul 10 06:02:24 PM PDT 24 Jul 10 06:36:21 PM PDT 24 57456306509 ps
T28 /workspace/coverage/default/1.rom_ctrl_sec_cm.3782087086 Jul 10 06:02:09 PM PDT 24 Jul 10 06:03:57 PM PDT 24 1467002319 ps
T353 /workspace/coverage/default/28.rom_ctrl_stress_all.101294433 Jul 10 06:03:00 PM PDT 24 Jul 10 06:03:22 PM PDT 24 2115020840 ps
T354 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3192081006 Jul 10 06:02:09 PM PDT 24 Jul 10 06:07:06 PM PDT 24 135904726686 ps
T355 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4041285348 Jul 10 06:02:43 PM PDT 24 Jul 10 06:02:58 PM PDT 24 1564140058 ps
T356 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.234343146 Jul 10 06:02:35 PM PDT 24 Jul 10 06:04:27 PM PDT 24 33993107292 ps
T357 /workspace/coverage/default/1.rom_ctrl_smoke.2636404308 Jul 10 06:02:07 PM PDT 24 Jul 10 06:02:45 PM PDT 24 7861766546 ps
T358 /workspace/coverage/default/15.rom_ctrl_stress_all.2155644019 Jul 10 06:02:28 PM PDT 24 Jul 10 06:03:20 PM PDT 24 16583491425 ps
T359 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.7701965 Jul 10 06:02:40 PM PDT 24 Jul 10 06:03:13 PM PDT 24 7471822519 ps
T360 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1718069205 Jul 10 06:02:43 PM PDT 24 Jul 10 06:02:51 PM PDT 24 374807712 ps
T361 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2108656967 Jul 10 06:03:02 PM PDT 24 Jul 10 06:03:18 PM PDT 24 3003343209 ps
T362 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2069265634 Jul 10 06:36:44 PM PDT 24 Jul 10 06:37:01 PM PDT 24 7167289029 ps
T56 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1053023463 Jul 10 06:37:04 PM PDT 24 Jul 10 06:38:00 PM PDT 24 29729242889 ps
T57 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2931404694 Jul 10 06:36:36 PM PDT 24 Jul 10 06:36:51 PM PDT 24 3278849186 ps
T53 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.96697764 Jul 10 06:36:50 PM PDT 24 Jul 10 06:38:06 PM PDT 24 5210978030 ps
T54 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1551925404 Jul 10 06:36:12 PM PDT 24 Jul 10 06:37:31 PM PDT 24 1712082629 ps
T363 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2735802744 Jul 10 06:37:22 PM PDT 24 Jul 10 06:37:38 PM PDT 24 374042230 ps
T64 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3034714115 Jul 10 06:36:30 PM PDT 24 Jul 10 06:36:44 PM PDT 24 2743563007 ps
T65 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1208347332 Jul 10 06:37:23 PM PDT 24 Jul 10 06:38:51 PM PDT 24 36930981409 ps
T66 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4122016091 Jul 10 06:36:17 PM PDT 24 Jul 10 06:36:23 PM PDT 24 329725990 ps
T67 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1092617033 Jul 10 06:36:58 PM PDT 24 Jul 10 06:37:39 PM PDT 24 6749264715 ps
T92 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.811639037 Jul 10 06:37:09 PM PDT 24 Jul 10 06:37:22 PM PDT 24 1965928707 ps
T55 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.597592480 Jul 10 06:37:11 PM PDT 24 Jul 10 06:37:55 PM PDT 24 393438832 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1341542873 Jul 10 06:36:17 PM PDT 24 Jul 10 06:36:34 PM PDT 24 4589130107 ps
T93 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3023775836 Jul 10 06:36:51 PM PDT 24 Jul 10 06:37:07 PM PDT 24 2064648283 ps
T365 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.615552172 Jul 10 06:37:13 PM PDT 24 Jul 10 06:37:26 PM PDT 24 88859783 ps
T94 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1596071985 Jul 10 06:37:24 PM PDT 24 Jul 10 06:38:13 PM PDT 24 7400044351 ps
T96 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2717426825 Jul 10 06:37:10 PM PDT 24 Jul 10 06:37:51 PM PDT 24 624472611 ps
T85 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3403440454 Jul 10 06:37:05 PM PDT 24 Jul 10 06:37:23 PM PDT 24 1889396339 ps
T68 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1910424959 Jul 10 06:37:02 PM PDT 24 Jul 10 06:38:41 PM PDT 24 14765178440 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3549188358 Jul 10 06:36:44 PM PDT 24 Jul 10 06:36:54 PM PDT 24 335781904 ps
T367 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1449778255 Jul 10 06:37:17 PM PDT 24 Jul 10 06:37:34 PM PDT 24 2322594327 ps
T69 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2776280791 Jul 10 06:36:31 PM PDT 24 Jul 10 06:36:40 PM PDT 24 371146082 ps
T70 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1026568561 Jul 10 06:37:18 PM PDT 24 Jul 10 06:38:33 PM PDT 24 74551843322 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.827262483 Jul 10 06:36:43 PM PDT 24 Jul 10 06:37:25 PM PDT 24 4695501615 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.193245561 Jul 10 06:36:23 PM PDT 24 Jul 10 06:36:40 PM PDT 24 7433558074 ps
T71 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.323886843 Jul 10 06:37:24 PM PDT 24 Jul 10 06:37:51 PM PDT 24 34201853395 ps
T72 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1825101866 Jul 10 06:36:52 PM PDT 24 Jul 10 06:37:34 PM PDT 24 8848190777 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.561650112 Jul 10 06:36:19 PM PDT 24 Jul 10 06:36:25 PM PDT 24 348065887 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1617392997 Jul 10 06:36:23 PM PDT 24 Jul 10 06:36:33 PM PDT 24 413793844 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.65770683 Jul 10 06:36:10 PM PDT 24 Jul 10 06:36:27 PM PDT 24 4375025640 ps
T73 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.539331609 Jul 10 06:37:22 PM PDT 24 Jul 10 06:37:59 PM PDT 24 1089374950 ps
T86 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3032165552 Jul 10 06:37:12 PM PDT 24 Jul 10 06:38:18 PM PDT 24 8104654189 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3119357443 Jul 10 06:36:23 PM PDT 24 Jul 10 06:36:33 PM PDT 24 15560319683 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4002455429 Jul 10 06:36:31 PM PDT 24 Jul 10 06:36:42 PM PDT 24 12329366212 ps
T374 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2345716868 Jul 10 06:37:24 PM PDT 24 Jul 10 06:37:46 PM PDT 24 3745416539 ps
T375 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.92688038 Jul 10 06:37:16 PM PDT 24 Jul 10 06:37:36 PM PDT 24 9194340988 ps
T87 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3991748358 Jul 10 06:37:22 PM PDT 24 Jul 10 06:37:45 PM PDT 24 23930180668 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1577374350 Jul 10 06:36:44 PM PDT 24 Jul 10 06:37:32 PM PDT 24 9113472031 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2546464984 Jul 10 06:36:44 PM PDT 24 Jul 10 06:37:01 PM PDT 24 4721704680 ps
T88 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3433159927 Jul 10 06:37:12 PM PDT 24 Jul 10 06:37:27 PM PDT 24 536549420 ps
T89 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.578966304 Jul 10 06:37:11 PM PDT 24 Jul 10 06:37:31 PM PDT 24 4012510359 ps
T378 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1874886464 Jul 10 06:37:05 PM PDT 24 Jul 10 06:37:28 PM PDT 24 2078419970 ps
T379 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2434916304 Jul 10 06:36:57 PM PDT 24 Jul 10 06:37:07 PM PDT 24 944498028 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4147906133 Jul 10 06:36:19 PM PDT 24 Jul 10 06:36:33 PM PDT 24 5840488433 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.352869173 Jul 10 06:37:22 PM PDT 24 Jul 10 06:37:43 PM PDT 24 2966220110 ps
T100 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4234151340 Jul 10 06:37:17 PM PDT 24 Jul 10 06:38:11 PM PDT 24 2368913222 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2404762153 Jul 10 06:36:51 PM PDT 24 Jul 10 06:37:00 PM PDT 24 1309300868 ps
T382 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3131081560 Jul 10 06:37:05 PM PDT 24 Jul 10 06:37:21 PM PDT 24 1318876799 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1005197317 Jul 10 06:36:40 PM PDT 24 Jul 10 06:36:52 PM PDT 24 263842925 ps
T384 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3788488002 Jul 10 06:37:06 PM PDT 24 Jul 10 06:37:15 PM PDT 24 102364046 ps
T80 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3881219802 Jul 10 06:37:11 PM PDT 24 Jul 10 06:37:19 PM PDT 24 85790505 ps
T385 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1972147001 Jul 10 06:37:16 PM PDT 24 Jul 10 06:38:22 PM PDT 24 7254464635 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3034508302 Jul 10 06:37:31 PM PDT 24 Jul 10 06:37:42 PM PDT 24 643774547 ps
T98 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.534745580 Jul 10 06:36:18 PM PDT 24 Jul 10 06:37:30 PM PDT 24 7089535320 ps
T387 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3263217040 Jul 10 06:37:24 PM PDT 24 Jul 10 06:37:52 PM PDT 24 8703649634 ps
T388 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.368809094 Jul 10 06:37:18 PM PDT 24 Jul 10 06:37:36 PM PDT 24 1129076835 ps
T81 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2092497886 Jul 10 06:37:26 PM PDT 24 Jul 10 06:37:47 PM PDT 24 1311052436 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2233009769 Jul 10 06:36:17 PM PDT 24 Jul 10 06:36:39 PM PDT 24 1945720709 ps
T91 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1957610178 Jul 10 06:37:56 PM PDT 24 Jul 10 06:38:11 PM PDT 24 14071728015 ps
T101 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1814355299 Jul 10 06:37:17 PM PDT 24 Jul 10 06:38:30 PM PDT 24 474165860 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2652944257 Jul 10 06:36:51 PM PDT 24 Jul 10 06:36:58 PM PDT 24 518322019 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.371152118 Jul 10 06:36:43 PM PDT 24 Jul 10 06:36:52 PM PDT 24 126215509 ps
T106 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3256821369 Jul 10 06:36:51 PM PDT 24 Jul 10 06:38:09 PM PDT 24 6879405275 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.722736489 Jul 10 06:36:36 PM PDT 24 Jul 10 06:36:52 PM PDT 24 36786233376 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1488430084 Jul 10 06:36:19 PM PDT 24 Jul 10 06:36:30 PM PDT 24 1748166915 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2219414172 Jul 10 06:36:34 PM PDT 24 Jul 10 06:37:20 PM PDT 24 1404884979 ps
T394 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.872585593 Jul 10 06:37:04 PM PDT 24 Jul 10 06:37:24 PM PDT 24 1890069616 ps
T395 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.918034431 Jul 10 06:37:04 PM PDT 24 Jul 10 06:37:14 PM PDT 24 543065307 ps
T396 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4110272632 Jul 10 06:36:52 PM PDT 24 Jul 10 06:36:59 PM PDT 24 100392197 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1456894373 Jul 10 06:36:50 PM PDT 24 Jul 10 06:37:04 PM PDT 24 1811403633 ps
T84 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.894851008 Jul 10 06:36:52 PM PDT 24 Jul 10 06:37:09 PM PDT 24 11549838625 ps
T398 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.784515025 Jul 10 06:37:09 PM PDT 24 Jul 10 06:37:21 PM PDT 24 1501840303 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.399860593 Jul 10 06:37:13 PM PDT 24 Jul 10 06:38:25 PM PDT 24 96768417284 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1564409067 Jul 10 06:36:36 PM PDT 24 Jul 10 06:37:47 PM PDT 24 122721193010 ps
T400 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2806856888 Jul 10 06:37:03 PM PDT 24 Jul 10 06:38:05 PM PDT 24 21714951431 ps
T401 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3686859460 Jul 10 06:36:40 PM PDT 24 Jul 10 06:36:59 PM PDT 24 2000820759 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2630979960 Jul 10 06:36:18 PM PDT 24 Jul 10 06:36:30 PM PDT 24 1534830895 ps
T102 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.104270458 Jul 10 06:37:06 PM PDT 24 Jul 10 06:38:19 PM PDT 24 508638177 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.493778260 Jul 10 06:37:03 PM PDT 24 Jul 10 06:37:10 PM PDT 24 99906386 ps
T108 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4250813152 Jul 10 06:37:11 PM PDT 24 Jul 10 06:38:35 PM PDT 24 7743580081 ps
T404 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2048561735 Jul 10 06:37:11 PM PDT 24 Jul 10 06:37:20 PM PDT 24 1038879727 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2854815915 Jul 10 06:36:29 PM PDT 24 Jul 10 06:36:35 PM PDT 24 108838296 ps
T406 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2115266973 Jul 10 06:36:49 PM PDT 24 Jul 10 06:36:59 PM PDT 24 121191611 ps
T107 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3218160058 Jul 10 06:37:05 PM PDT 24 Jul 10 06:37:52 PM PDT 24 9057858473 ps
T407 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3971572273 Jul 10 06:37:22 PM PDT 24 Jul 10 06:37:42 PM PDT 24 1259041178 ps
T408 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1607149759 Jul 10 06:37:24 PM PDT 24 Jul 10 06:38:10 PM PDT 24 313603519 ps
T409 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.996022249 Jul 10 06:36:34 PM PDT 24 Jul 10 06:36:40 PM PDT 24 691751232 ps
T410 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2096795064 Jul 10 06:37:10 PM PDT 24 Jul 10 06:37:28 PM PDT 24 7902777819 ps
T411 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3657621633 Jul 10 06:36:58 PM PDT 24 Jul 10 06:37:05 PM PDT 24 174684087 ps
T412 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2144890982 Jul 10 06:37:05 PM PDT 24 Jul 10 06:37:14 PM PDT 24 1370363532 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1984140834 Jul 10 06:36:19 PM PDT 24 Jul 10 06:36:25 PM PDT 24 100961714 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2483361566 Jul 10 06:37:22 PM PDT 24 Jul 10 06:37:40 PM PDT 24 7733938792 ps
T415 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1667596782 Jul 10 06:37:21 PM PDT 24 Jul 10 06:37:43 PM PDT 24 1640817640 ps
T416 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2069976865 Jul 10 06:36:59 PM PDT 24 Jul 10 06:37:15 PM PDT 24 6180708898 ps
T417 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1041966385 Jul 10 06:37:11 PM PDT 24 Jul 10 06:37:24 PM PDT 24 129162570 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.154937 Jul 10 06:36:11 PM PDT 24 Jul 10 06:36:31 PM PDT 24 1444126120 ps
T419 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.189589210 Jul 10 06:37:24 PM PDT 24 Jul 10 06:37:47 PM PDT 24 6595874434 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3699451941 Jul 10 06:36:24 PM PDT 24 Jul 10 06:36:30 PM PDT 24 111069650 ps
T421 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2123331585 Jul 10 06:37:10 PM PDT 24 Jul 10 06:37:21 PM PDT 24 510211731 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3101386353 Jul 10 06:36:16 PM PDT 24 Jul 10 06:36:36 PM PDT 24 2100242082 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.227582756 Jul 10 06:36:24 PM PDT 24 Jul 10 06:36:40 PM PDT 24 1849045529 ps
T82 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3904395103 Jul 10 06:36:43 PM PDT 24 Jul 10 06:37:01 PM PDT 24 11595881927 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3782075617 Jul 10 06:36:32 PM PDT 24 Jul 10 06:36:48 PM PDT 24 4204504658 ps
T425 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2430268677 Jul 10 06:37:23 PM PDT 24 Jul 10 06:37:45 PM PDT 24 1550072978 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.327889814 Jul 10 06:37:00 PM PDT 24 Jul 10 06:37:07 PM PDT 24 95221675 ps
T427 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2544960955 Jul 10 06:37:23 PM PDT 24 Jul 10 06:37:38 PM PDT 24 426116375 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.668451885 Jul 10 06:36:37 PM PDT 24 Jul 10 06:36:51 PM PDT 24 1574320115 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2333367054 Jul 10 06:36:19 PM PDT 24 Jul 10 06:36:28 PM PDT 24 630081448 ps
T430 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1754042095 Jul 10 06:37:12 PM PDT 24 Jul 10 06:37:32 PM PDT 24 1877656239 ps
T431 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.179359948 Jul 10 06:37:04 PM PDT 24 Jul 10 06:37:11 PM PDT 24 1378426154 ps
T432 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1001376359 Jul 10 06:36:11 PM PDT 24 Jul 10 06:36:24 PM PDT 24 5108449859 ps
T433 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4118071419 Jul 10 06:36:49 PM PDT 24 Jul 10 06:37:06 PM PDT 24 2394510688 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4239169718 Jul 10 06:37:02 PM PDT 24 Jul 10 06:37:09 PM PDT 24 291596948 ps
T83 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.400235751 Jul 10 06:36:50 PM PDT 24 Jul 10 06:37:50 PM PDT 24 6577733679 ps
T435 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.941221484 Jul 10 06:36:43 PM PDT 24 Jul 10 06:36:59 PM PDT 24 12182528928 ps
T436 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3220443006 Jul 10 06:36:57 PM PDT 24 Jul 10 06:37:11 PM PDT 24 1425602487 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1650359130 Jul 10 06:36:34 PM PDT 24 Jul 10 06:37:26 PM PDT 24 5449655906 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2756289950 Jul 10 06:36:44 PM PDT 24 Jul 10 06:36:56 PM PDT 24 3245541461 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.105784707 Jul 10 06:36:30 PM PDT 24 Jul 10 06:36:41 PM PDT 24 1957000409 ps
T440 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4018727154 Jul 10 06:37:11 PM PDT 24 Jul 10 06:37:23 PM PDT 24 504687650 ps
T441 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.60158616 Jul 10 06:37:12 PM PDT 24 Jul 10 06:37:33 PM PDT 24 1721052776 ps
T442 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1087103161 Jul 10 06:37:16 PM PDT 24 Jul 10 06:38:18 PM PDT 24 4807983101 ps
T443 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.569614184 Jul 10 06:36:50 PM PDT 24 Jul 10 06:36:57 PM PDT 24 195397703 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3790486429 Jul 10 06:36:52 PM PDT 24 Jul 10 06:37:08 PM PDT 24 6342214196 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2432832875 Jul 10 06:36:51 PM PDT 24 Jul 10 06:36:58 PM PDT 24 1270828085 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4194826089 Jul 10 06:37:23 PM PDT 24 Jul 10 06:37:46 PM PDT 24 7371299182 ps
T447 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1617448143 Jul 10 06:37:17 PM PDT 24 Jul 10 06:37:33 PM PDT 24 148127456 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2291354042 Jul 10 06:36:23 PM PDT 24 Jul 10 06:36:37 PM PDT 24 8855506183 ps
T449 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1924001381 Jul 10 06:37:10 PM PDT 24 Jul 10 06:37:27 PM PDT 24 1504676609 ps
T450 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.305828248 Jul 10 06:37:21 PM PDT 24 Jul 10 06:37:40 PM PDT 24 783157965 ps
T103 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2647927747 Jul 10 06:36:50 PM PDT 24 Jul 10 06:38:07 PM PDT 24 1521735974 ps
T109 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2472101696 Jul 10 06:37:05 PM PDT 24 Jul 10 06:37:54 PM PDT 24 6888575414 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.363089937 Jul 10 06:36:30 PM PDT 24 Jul 10 06:36:45 PM PDT 24 1642943561 ps
T452 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1797186302 Jul 10 06:37:04 PM PDT 24 Jul 10 06:37:14 PM PDT 24 2687133388 ps
T453 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3170322929 Jul 10 06:37:26 PM PDT 24 Jul 10 06:37:48 PM PDT 24 1163437069 ps
T104 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2752111415 Jul 10 06:37:22 PM PDT 24 Jul 10 06:38:06 PM PDT 24 594210365 ps
T454 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3913744615 Jul 10 06:37:16 PM PDT 24 Jul 10 06:37:28 PM PDT 24 362604892 ps
T455 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3825989346 Jul 10 06:37:24 PM PDT 24 Jul 10 06:38:46 PM PDT 24 1548944845 ps
T456 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1475459829 Jul 10 06:37:11 PM PDT 24 Jul 10 06:37:52 PM PDT 24 6214487466 ps
T457 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1985684262 Jul 10 06:37:26 PM PDT 24 Jul 10 06:38:15 PM PDT 24 1914573601 ps
T458 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.733851888 Jul 10 06:37:17 PM PDT 24 Jul 10 06:37:36 PM PDT 24 5988705322 ps
T105 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2070970027 Jul 10 06:36:58 PM PDT 24 Jul 10 06:38:11 PM PDT 24 16982487355 ps
T459 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1002936412 Jul 10 06:36:38 PM PDT 24 Jul 10 06:36:47 PM PDT 24 341098735 ps
T460 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.351010869 Jul 10 06:36:24 PM PDT 24 Jul 10 06:36:41 PM PDT 24 1554301939 ps
T461 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1517043016 Jul 10 06:36:50 PM PDT 24 Jul 10 06:37:05 PM PDT 24 17793811296 ps

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1112864428
Short name T8
Test name
Test status
Simulation time 41055605460 ps
CPU time 408.26 seconds
Started Jul 10 06:02:44 PM PDT 24
Finished Jul 10 06:09:35 PM PDT 24
Peak memory 213644 kb
Host smart-dbb725d1-c4c4-4c0e-a212-ca7f9e64168e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112864428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1112864428
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2956220754
Short name T12
Test name
Test status
Simulation time 19385919276 ps
CPU time 755.75 seconds
Started Jul 10 06:02:13 PM PDT 24
Finished Jul 10 06:14:50 PM PDT 24
Peak memory 227680 kb
Host smart-d9e8649a-722a-4644-bb30-a0ab24bc612b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956220754 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2956220754
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.362936561
Short name T17
Test name
Test status
Simulation time 3514818583 ps
CPU time 31.67 seconds
Started Jul 10 06:03:12 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 215280 kb
Host smart-7d84eb77-1fb2-45b7-bf5b-b6ab05d823ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362936561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.362936561
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1551925404
Short name T54
Test name
Test status
Simulation time 1712082629 ps
CPU time 77.36 seconds
Started Jul 10 06:36:12 PM PDT 24
Finished Jul 10 06:37:31 PM PDT 24
Peak memory 212400 kb
Host smart-a81d7fe7-cb84-44e8-8440-5588cc52eb98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551925404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1551925404
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3511792499
Short name T36
Test name
Test status
Simulation time 7223998989 ps
CPU time 169.09 seconds
Started Jul 10 06:02:17 PM PDT 24
Finished Jul 10 06:05:08 PM PDT 24
Peak memory 238100 kb
Host smart-17197bf0-6cda-42cf-8969-a4134d57b711
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511792499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3511792499
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.577220416
Short name T14
Test name
Test status
Simulation time 46069196247 ps
CPU time 1913.06 seconds
Started Jul 10 06:02:46 PM PDT 24
Finished Jul 10 06:34:41 PM PDT 24
Peak memory 237452 kb
Host smart-715af159-cd76-4bf4-a37d-2e1b2c3060e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577220416 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.577220416
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.328959911
Short name T20
Test name
Test status
Simulation time 1687187629 ps
CPU time 100.63 seconds
Started Jul 10 06:02:12 PM PDT 24
Finished Jul 10 06:03:54 PM PDT 24
Peak memory 237988 kb
Host smart-87bd05d7-3ee2-47cd-9c7a-6e4c2d2d75c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328959911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.328959911
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3974610778
Short name T74
Test name
Test status
Simulation time 15949537697 ps
CPU time 162.58 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:05:17 PM PDT 24
Peak memory 219424 kb
Host smart-e8b3629a-66e6-4cae-b8a5-ccfd11d59ca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974610778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3974610778
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1825101866
Short name T72
Test name
Test status
Simulation time 8848190777 ps
CPU time 39.12 seconds
Started Jul 10 06:36:52 PM PDT 24
Finished Jul 10 06:37:34 PM PDT 24
Peak memory 210836 kb
Host smart-d0db2f76-b528-424d-9548-89478e6bd6af
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825101866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1825101866
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1192746545
Short name T23
Test name
Test status
Simulation time 3957111127 ps
CPU time 10.5 seconds
Started Jul 10 06:02:54 PM PDT 24
Finished Jul 10 06:03:05 PM PDT 24
Peak memory 211392 kb
Host smart-312d9b97-3fdb-45e6-baca-27d138ecae3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192746545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1192746545
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.534745580
Short name T98
Test name
Test status
Simulation time 7089535320 ps
CPU time 70.68 seconds
Started Jul 10 06:36:18 PM PDT 24
Finished Jul 10 06:37:30 PM PDT 24
Peak memory 219116 kb
Host smart-65c6bc9d-cf87-4467-9209-716f82466275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534745580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.534745580
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4085847809
Short name T7
Test name
Test status
Simulation time 11372205832 ps
CPU time 19.57 seconds
Started Jul 10 06:02:54 PM PDT 24
Finished Jul 10 06:03:14 PM PDT 24
Peak memory 212284 kb
Host smart-6f192467-e6a9-48d1-913b-71c849a3b8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085847809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4085847809
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3565217282
Short name T239
Test name
Test status
Simulation time 719801638 ps
CPU time 11.98 seconds
Started Jul 10 06:02:17 PM PDT 24
Finished Jul 10 06:02:31 PM PDT 24
Peak memory 211864 kb
Host smart-3fdbd553-7f62-4498-b881-0eda11956279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565217282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3565217282
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2647927747
Short name T103
Test name
Test status
Simulation time 1521735974 ps
CPU time 75.62 seconds
Started Jul 10 06:36:50 PM PDT 24
Finished Jul 10 06:38:07 PM PDT 24
Peak memory 212336 kb
Host smart-dac74ae2-d3b5-40f6-9942-08afe225daba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647927747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2647927747
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1208347332
Short name T65
Test name
Test status
Simulation time 36930981409 ps
CPU time 78.19 seconds
Started Jul 10 06:37:23 PM PDT 24
Finished Jul 10 06:38:51 PM PDT 24
Peak memory 210772 kb
Host smart-e3126d37-8cc1-4858-a3eb-f50f43ea17f3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208347332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1208347332
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3218160058
Short name T107
Test name
Test status
Simulation time 9057858473 ps
CPU time 44.02 seconds
Started Jul 10 06:37:05 PM PDT 24
Finished Jul 10 06:37:52 PM PDT 24
Peak memory 219060 kb
Host smart-cdf1060d-7b36-44d0-9746-5ce4b7745fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218160058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3218160058
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.104270458
Short name T102
Test name
Test status
Simulation time 508638177 ps
CPU time 70.7 seconds
Started Jul 10 06:37:06 PM PDT 24
Finished Jul 10 06:38:19 PM PDT 24
Peak memory 218980 kb
Host smart-c15e8e1e-22a7-486f-b3e7-e0ff3e0b63a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104270458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.104270458
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4196061116
Short name T29
Test name
Test status
Simulation time 1018755646 ps
CPU time 5.39 seconds
Started Jul 10 06:03:05 PM PDT 24
Finished Jul 10 06:03:13 PM PDT 24
Peak memory 211392 kb
Host smart-1a92173a-cc69-4495-9318-acc0f58eb845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4196061116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4196061116
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3122605817
Short name T15
Test name
Test status
Simulation time 77852029987 ps
CPU time 1284.29 seconds
Started Jul 10 06:02:32 PM PDT 24
Finished Jul 10 06:23:58 PM PDT 24
Peak memory 229464 kb
Host smart-e6bf12ac-ab73-4b19-8ac2-a170f1cffae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122605817 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3122605817
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2630979960
Short name T402
Test name
Test status
Simulation time 1534830895 ps
CPU time 11.18 seconds
Started Jul 10 06:36:18 PM PDT 24
Finished Jul 10 06:36:30 PM PDT 24
Peak memory 210776 kb
Host smart-706f1fe7-fd4a-4fe1-9276-8747687ed815
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630979960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2630979960
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.561650112
Short name T369
Test name
Test status
Simulation time 348065887 ps
CPU time 4.45 seconds
Started Jul 10 06:36:19 PM PDT 24
Finished Jul 10 06:36:25 PM PDT 24
Peak memory 217780 kb
Host smart-c76d52d8-45fd-4d3a-bb2d-e957ebca43ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561650112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.561650112
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4122016091
Short name T66
Test name
Test status
Simulation time 329725990 ps
CPU time 5.82 seconds
Started Jul 10 06:36:17 PM PDT 24
Finished Jul 10 06:36:23 PM PDT 24
Peak memory 218608 kb
Host smart-e63f9580-0d9b-412b-b0cc-8c8fc6b2f373
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122016091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4122016091
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1984140834
Short name T413
Test name
Test status
Simulation time 100961714 ps
CPU time 4.94 seconds
Started Jul 10 06:36:19 PM PDT 24
Finished Jul 10 06:36:25 PM PDT 24
Peak memory 214728 kb
Host smart-ed804fb1-2e86-4238-a2fd-3d8d9f427563
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984140834 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1984140834
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1488430084
Short name T393
Test name
Test status
Simulation time 1748166915 ps
CPU time 9.61 seconds
Started Jul 10 06:36:19 PM PDT 24
Finished Jul 10 06:36:30 PM PDT 24
Peak memory 210740 kb
Host smart-4a08ce17-d5f8-4932-882b-db174a6b7fa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488430084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1488430084
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3782075617
Short name T424
Test name
Test status
Simulation time 4204504658 ps
CPU time 15.27 seconds
Started Jul 10 06:36:32 PM PDT 24
Finished Jul 10 06:36:48 PM PDT 24
Peak memory 210688 kb
Host smart-3a6202b4-ded0-436e-b235-1a48f5ea36b0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782075617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3782075617
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1001376359
Short name T432
Test name
Test status
Simulation time 5108449859 ps
CPU time 11.35 seconds
Started Jul 10 06:36:11 PM PDT 24
Finished Jul 10 06:36:24 PM PDT 24
Peak memory 210604 kb
Host smart-bfa1152c-44a6-4e44-bdec-75a482737c5d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001376359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1001376359
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.154937
Short name T418
Test name
Test status
Simulation time 1444126120 ps
CPU time 18.8 seconds
Started Jul 10 06:36:11 PM PDT 24
Finished Jul 10 06:36:31 PM PDT 24
Peak memory 210728 kb
Host smart-e8e4906b-efdf-4ee6-aa5b-948c61286359
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passth
ru_mem_tl_intg_err.154937
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3101386353
Short name T422
Test name
Test status
Simulation time 2100242082 ps
CPU time 18.64 seconds
Started Jul 10 06:36:16 PM PDT 24
Finished Jul 10 06:36:36 PM PDT 24
Peak memory 218968 kb
Host smart-e0d53d29-361e-488f-8be5-2bc55f29c4a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101386353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3101386353
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.65770683
Short name T371
Test name
Test status
Simulation time 4375025640 ps
CPU time 15.3 seconds
Started Jul 10 06:36:10 PM PDT 24
Finished Jul 10 06:36:27 PM PDT 24
Peak memory 219088 kb
Host smart-838739f0-0b57-41b2-9597-77d24f5b9461
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65770683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.65770683
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.227582756
Short name T423
Test name
Test status
Simulation time 1849045529 ps
CPU time 15.15 seconds
Started Jul 10 06:36:24 PM PDT 24
Finished Jul 10 06:36:40 PM PDT 24
Peak memory 210764 kb
Host smart-bfaceea7-556a-4aa3-8fd6-65b4c3549d31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227582756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.227582756
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.193245561
Short name T368
Test name
Test status
Simulation time 7433558074 ps
CPU time 14.94 seconds
Started Jul 10 06:36:23 PM PDT 24
Finished Jul 10 06:36:40 PM PDT 24
Peak memory 210832 kb
Host smart-d4b33496-7cd5-4604-bafc-5f47ece6d4de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193245561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.193245561
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.351010869
Short name T460
Test name
Test status
Simulation time 1554301939 ps
CPU time 16.16 seconds
Started Jul 10 06:36:24 PM PDT 24
Finished Jul 10 06:36:41 PM PDT 24
Peak memory 218596 kb
Host smart-12c4386b-026f-43a4-81fc-426a845192d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351010869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.351010869
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3699451941
Short name T420
Test name
Test status
Simulation time 111069650 ps
CPU time 4.83 seconds
Started Jul 10 06:36:24 PM PDT 24
Finished Jul 10 06:36:30 PM PDT 24
Peak memory 218980 kb
Host smart-32820f8b-43cd-451d-a7e4-8f0efe34549e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699451941 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3699451941
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.996022249
Short name T409
Test name
Test status
Simulation time 691751232 ps
CPU time 4.26 seconds
Started Jul 10 06:36:34 PM PDT 24
Finished Jul 10 06:36:40 PM PDT 24
Peak memory 217664 kb
Host smart-9daa49a0-4e31-4eaf-8bef-926546ce7d78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996022249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.996022249
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4147906133
Short name T380
Test name
Test status
Simulation time 5840488433 ps
CPU time 13.08 seconds
Started Jul 10 06:36:19 PM PDT 24
Finished Jul 10 06:36:33 PM PDT 24
Peak memory 210720 kb
Host smart-f8f2756e-2cdc-4077-a095-4d3f0fc39b54
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147906133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4147906133
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2333367054
Short name T429
Test name
Test status
Simulation time 630081448 ps
CPU time 8.37 seconds
Started Jul 10 06:36:19 PM PDT 24
Finished Jul 10 06:36:28 PM PDT 24
Peak memory 210652 kb
Host smart-b56b8565-a545-4133-9794-26a71f29476f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333367054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2333367054
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2233009769
Short name T389
Test name
Test status
Simulation time 1945720709 ps
CPU time 21.28 seconds
Started Jul 10 06:36:17 PM PDT 24
Finished Jul 10 06:36:39 PM PDT 24
Peak memory 210752 kb
Host smart-b5567baa-794c-435c-ab7c-c0ac109b69e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233009769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2233009769
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2291354042
Short name T448
Test name
Test status
Simulation time 8855506183 ps
CPU time 12.7 seconds
Started Jul 10 06:36:23 PM PDT 24
Finished Jul 10 06:36:37 PM PDT 24
Peak memory 219032 kb
Host smart-03744c2a-1209-469c-8f44-8f8b80b364ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291354042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2291354042
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1341542873
Short name T364
Test name
Test status
Simulation time 4589130107 ps
CPU time 15.79 seconds
Started Jul 10 06:36:17 PM PDT 24
Finished Jul 10 06:36:34 PM PDT 24
Peak memory 219068 kb
Host smart-3418daa0-112b-4fda-bf5e-14bbe2cd0429
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341542873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1341542873
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1754042095
Short name T430
Test name
Test status
Simulation time 1877656239 ps
CPU time 14.63 seconds
Started Jul 10 06:37:12 PM PDT 24
Finished Jul 10 06:37:32 PM PDT 24
Peak memory 219064 kb
Host smart-7bac52d8-0756-4c94-b800-94744ddbbbe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754042095 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1754042095
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2144890982
Short name T412
Test name
Test status
Simulation time 1370363532 ps
CPU time 6.43 seconds
Started Jul 10 06:37:05 PM PDT 24
Finished Jul 10 06:37:14 PM PDT 24
Peak memory 217708 kb
Host smart-d41be372-1992-4116-9e9a-46e053bdcebb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144890982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2144890982
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2806856888
Short name T400
Test name
Test status
Simulation time 21714951431 ps
CPU time 60.28 seconds
Started Jul 10 06:37:03 PM PDT 24
Finished Jul 10 06:38:05 PM PDT 24
Peak memory 217908 kb
Host smart-4a0e6159-8423-4915-9f02-747d7b1ab2a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806856888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2806856888
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.578966304
Short name T89
Test name
Test status
Simulation time 4012510359 ps
CPU time 15.47 seconds
Started Jul 10 06:37:11 PM PDT 24
Finished Jul 10 06:37:31 PM PDT 24
Peak memory 210880 kb
Host smart-63d8bbab-39b8-4abf-adb8-10415cb6efdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578966304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.578966304
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3131081560
Short name T382
Test name
Test status
Simulation time 1318876799 ps
CPU time 13.26 seconds
Started Jul 10 06:37:05 PM PDT 24
Finished Jul 10 06:37:21 PM PDT 24
Peak memory 219020 kb
Host smart-f7faba3f-6bea-4691-9a6b-81247756f683
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131081560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3131081560
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2123331585
Short name T421
Test name
Test status
Simulation time 510211731 ps
CPU time 7.77 seconds
Started Jul 10 06:37:10 PM PDT 24
Finished Jul 10 06:37:21 PM PDT 24
Peak memory 212724 kb
Host smart-8a6582c4-97c9-4f71-ab46-161178596d4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123331585 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2123331585
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4018727154
Short name T440
Test name
Test status
Simulation time 504687650 ps
CPU time 5.94 seconds
Started Jul 10 06:37:11 PM PDT 24
Finished Jul 10 06:37:23 PM PDT 24
Peak memory 210784 kb
Host smart-d755eea9-ce20-4865-9fd7-432d9bbde626
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018727154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4018727154
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1475459829
Short name T456
Test name
Test status
Simulation time 6214487466 ps
CPU time 36.94 seconds
Started Jul 10 06:37:11 PM PDT 24
Finished Jul 10 06:37:52 PM PDT 24
Peak memory 210836 kb
Host smart-c0b46c39-be27-48f5-b4cc-4a1703838f6f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475459829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1475459829
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1924001381
Short name T449
Test name
Test status
Simulation time 1504676609 ps
CPU time 13.84 seconds
Started Jul 10 06:37:10 PM PDT 24
Finished Jul 10 06:37:27 PM PDT 24
Peak memory 210840 kb
Host smart-fb113f4f-1c10-41ba-950d-533ab4d02ba8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924001381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1924001381
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1041966385
Short name T417
Test name
Test status
Simulation time 129162570 ps
CPU time 8.97 seconds
Started Jul 10 06:37:11 PM PDT 24
Finished Jul 10 06:37:24 PM PDT 24
Peak memory 219036 kb
Host smart-b70f9a06-0883-41f9-b21f-e275f0a97160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041966385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1041966385
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2717426825
Short name T96
Test name
Test status
Simulation time 624472611 ps
CPU time 36.82 seconds
Started Jul 10 06:37:10 PM PDT 24
Finished Jul 10 06:37:51 PM PDT 24
Peak memory 210908 kb
Host smart-662dc681-7bfe-46e9-b96e-d87ce640b516
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717426825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2717426825
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.784515025
Short name T398
Test name
Test status
Simulation time 1501840303 ps
CPU time 9.09 seconds
Started Jul 10 06:37:09 PM PDT 24
Finished Jul 10 06:37:21 PM PDT 24
Peak memory 219052 kb
Host smart-6edb122d-ca65-4b27-96f5-292752609b20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784515025 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.784515025
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3881219802
Short name T80
Test name
Test status
Simulation time 85790505 ps
CPU time 4.34 seconds
Started Jul 10 06:37:11 PM PDT 24
Finished Jul 10 06:37:19 PM PDT 24
Peak memory 210768 kb
Host smart-015bb8a8-1cef-4be7-9646-9fc5354ae6d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881219802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3881219802
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.399860593
Short name T399
Test name
Test status
Simulation time 96768417284 ps
CPU time 65.86 seconds
Started Jul 10 06:37:13 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 210844 kb
Host smart-69e4ca25-d05b-4c24-9cfc-22a3f546eeaf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399860593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.399860593
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2048561735
Short name T404
Test name
Test status
Simulation time 1038879727 ps
CPU time 4.54 seconds
Started Jul 10 06:37:11 PM PDT 24
Finished Jul 10 06:37:20 PM PDT 24
Peak memory 210828 kb
Host smart-414734ab-94cb-437e-bf16-78028a0498f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048561735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2048561735
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.615552172
Short name T365
Test name
Test status
Simulation time 88859783 ps
CPU time 6.66 seconds
Started Jul 10 06:37:13 PM PDT 24
Finished Jul 10 06:37:26 PM PDT 24
Peak memory 219016 kb
Host smart-1f2b8634-c54e-4086-8268-bd658267a2db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615552172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.615552172
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.597592480
Short name T55
Test name
Test status
Simulation time 393438832 ps
CPU time 39.68 seconds
Started Jul 10 06:37:11 PM PDT 24
Finished Jul 10 06:37:55 PM PDT 24
Peak memory 211928 kb
Host smart-64ecf4f7-c607-4248-b5d0-b90596723745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597592480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.597592480
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2096795064
Short name T410
Test name
Test status
Simulation time 7902777819 ps
CPU time 15.86 seconds
Started Jul 10 06:37:10 PM PDT 24
Finished Jul 10 06:37:28 PM PDT 24
Peak memory 219120 kb
Host smart-29bd7d09-6f1b-495a-90be-561d1fdabf51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096795064 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2096795064
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.811639037
Short name T92
Test name
Test status
Simulation time 1965928707 ps
CPU time 9.96 seconds
Started Jul 10 06:37:09 PM PDT 24
Finished Jul 10 06:37:22 PM PDT 24
Peak memory 218604 kb
Host smart-693157e2-fad3-449e-9f41-c4b19beb860d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811639037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.811639037
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3032165552
Short name T86
Test name
Test status
Simulation time 8104654189 ps
CPU time 59.39 seconds
Started Jul 10 06:37:12 PM PDT 24
Finished Jul 10 06:38:18 PM PDT 24
Peak memory 210900 kb
Host smart-ebd97b3a-dc4b-45cf-9a5b-0ad7e996a8f0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032165552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3032165552
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3433159927
Short name T88
Test name
Test status
Simulation time 536549420 ps
CPU time 9.36 seconds
Started Jul 10 06:37:12 PM PDT 24
Finished Jul 10 06:37:27 PM PDT 24
Peak memory 218944 kb
Host smart-8b568921-ee16-480e-a3e1-f002ef32b3bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433159927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3433159927
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.60158616
Short name T441
Test name
Test status
Simulation time 1721052776 ps
CPU time 14.88 seconds
Started Jul 10 06:37:12 PM PDT 24
Finished Jul 10 06:37:33 PM PDT 24
Peak memory 215804 kb
Host smart-6799be84-035b-4d6a-8426-af702d06c16e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60158616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.60158616
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4250813152
Short name T108
Test name
Test status
Simulation time 7743580081 ps
CPU time 80.11 seconds
Started Jul 10 06:37:11 PM PDT 24
Finished Jul 10 06:38:35 PM PDT 24
Peak memory 219068 kb
Host smart-3282260a-4eae-4345-baf0-13b50312f979
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250813152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4250813152
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.368809094
Short name T388
Test name
Test status
Simulation time 1129076835 ps
CPU time 11.24 seconds
Started Jul 10 06:37:18 PM PDT 24
Finished Jul 10 06:37:36 PM PDT 24
Peak memory 219036 kb
Host smart-a4db6a40-a5be-4786-b037-26707364054f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368809094 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.368809094
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1957610178
Short name T91
Test name
Test status
Simulation time 14071728015 ps
CPU time 12.78 seconds
Started Jul 10 06:37:56 PM PDT 24
Finished Jul 10 06:38:11 PM PDT 24
Peak memory 210768 kb
Host smart-50063f53-fa99-40a3-b744-09ce9e6b0c34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957610178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1957610178
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1026568561
Short name T70
Test name
Test status
Simulation time 74551843322 ps
CPU time 69.48 seconds
Started Jul 10 06:37:18 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 210836 kb
Host smart-8b82d106-3ade-4a34-9f16-89286ee70bcc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026568561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1026568561
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.733851888
Short name T458
Test name
Test status
Simulation time 5988705322 ps
CPU time 13.35 seconds
Started Jul 10 06:37:17 PM PDT 24
Finished Jul 10 06:37:36 PM PDT 24
Peak memory 211064 kb
Host smart-d3e51201-a328-45d3-b3ae-ea70c53c9c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733851888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.733851888
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1617448143
Short name T447
Test name
Test status
Simulation time 148127456 ps
CPU time 10.06 seconds
Started Jul 10 06:37:17 PM PDT 24
Finished Jul 10 06:37:33 PM PDT 24
Peak memory 219024 kb
Host smart-3742c097-ab73-42d8-b75e-9f00e5df7c82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617448143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1617448143
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4234151340
Short name T100
Test name
Test status
Simulation time 2368913222 ps
CPU time 47.54 seconds
Started Jul 10 06:37:17 PM PDT 24
Finished Jul 10 06:38:11 PM PDT 24
Peak memory 212328 kb
Host smart-618c7eed-24bf-4245-b87d-70f9b6c4de98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234151340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4234151340
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.305828248
Short name T450
Test name
Test status
Simulation time 783157965 ps
CPU time 10.22 seconds
Started Jul 10 06:37:21 PM PDT 24
Finished Jul 10 06:37:40 PM PDT 24
Peak memory 218996 kb
Host smart-6fd48897-db30-47e2-8f20-203d3f2d64bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305828248 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.305828248
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1449778255
Short name T367
Test name
Test status
Simulation time 2322594327 ps
CPU time 11.54 seconds
Started Jul 10 06:37:17 PM PDT 24
Finished Jul 10 06:37:34 PM PDT 24
Peak memory 210776 kb
Host smart-9993edde-14b5-412f-aed0-397725fdb59d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449778255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1449778255
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1972147001
Short name T385
Test name
Test status
Simulation time 7254464635 ps
CPU time 59.88 seconds
Started Jul 10 06:37:16 PM PDT 24
Finished Jul 10 06:38:22 PM PDT 24
Peak memory 210800 kb
Host smart-af2bc728-6859-4e50-b4bb-0a21bdd286d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972147001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1972147001
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3971572273
Short name T407
Test name
Test status
Simulation time 1259041178 ps
CPU time 11.76 seconds
Started Jul 10 06:37:22 PM PDT 24
Finished Jul 10 06:37:42 PM PDT 24
Peak memory 218952 kb
Host smart-85a5c193-8619-46b9-a816-878ea59132a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971572273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3971572273
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.92688038
Short name T375
Test name
Test status
Simulation time 9194340988 ps
CPU time 13.58 seconds
Started Jul 10 06:37:16 PM PDT 24
Finished Jul 10 06:37:36 PM PDT 24
Peak memory 219072 kb
Host smart-ed6b69a3-677b-4dd7-9fe1-734e0a5e93ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92688038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.92688038
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2752111415
Short name T104
Test name
Test status
Simulation time 594210365 ps
CPU time 35.91 seconds
Started Jul 10 06:37:22 PM PDT 24
Finished Jul 10 06:38:06 PM PDT 24
Peak memory 218972 kb
Host smart-f4afc682-aa52-4bad-b602-8409b6226706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752111415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2752111415
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4194826089
Short name T446
Test name
Test status
Simulation time 7371299182 ps
CPU time 14.2 seconds
Started Jul 10 06:37:23 PM PDT 24
Finished Jul 10 06:37:46 PM PDT 24
Peak memory 219128 kb
Host smart-3b372b02-2b00-4373-a4f6-babb5b28b537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194826089 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4194826089
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.323886843
Short name T71
Test name
Test status
Simulation time 34201853395 ps
CPU time 17.52 seconds
Started Jul 10 06:37:24 PM PDT 24
Finished Jul 10 06:37:51 PM PDT 24
Peak memory 218912 kb
Host smart-d5950b34-e937-4d80-891f-c67b8421fb18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323886843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.323886843
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1087103161
Short name T442
Test name
Test status
Simulation time 4807983101 ps
CPU time 55.77 seconds
Started Jul 10 06:37:16 PM PDT 24
Finished Jul 10 06:38:18 PM PDT 24
Peak memory 210852 kb
Host smart-53574b8c-926f-43e8-9c82-838e820ab41f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087103161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1087103161
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3170322929
Short name T453
Test name
Test status
Simulation time 1163437069 ps
CPU time 13.31 seconds
Started Jul 10 06:37:26 PM PDT 24
Finished Jul 10 06:37:48 PM PDT 24
Peak memory 210824 kb
Host smart-74da39af-876f-44c3-ad43-c16b15049f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170322929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3170322929
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3913744615
Short name T454
Test name
Test status
Simulation time 362604892 ps
CPU time 6.32 seconds
Started Jul 10 06:37:16 PM PDT 24
Finished Jul 10 06:37:28 PM PDT 24
Peak memory 219020 kb
Host smart-e869b10e-fd89-4809-bcd6-80f2504e784d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913744615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3913744615
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1814355299
Short name T101
Test name
Test status
Simulation time 474165860 ps
CPU time 67.63 seconds
Started Jul 10 06:37:17 PM PDT 24
Finished Jul 10 06:38:30 PM PDT 24
Peak memory 218952 kb
Host smart-46a391b4-b65b-4a1c-a9da-0e1ca337c5e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814355299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1814355299
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2735802744
Short name T363
Test name
Test status
Simulation time 374042230 ps
CPU time 7.49 seconds
Started Jul 10 06:37:22 PM PDT 24
Finished Jul 10 06:37:38 PM PDT 24
Peak memory 218948 kb
Host smart-1c42da2e-fa30-4c5f-b185-c1d329c28b64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735802744 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2735802744
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1667596782
Short name T415
Test name
Test status
Simulation time 1640817640 ps
CPU time 13.88 seconds
Started Jul 10 06:37:21 PM PDT 24
Finished Jul 10 06:37:43 PM PDT 24
Peak memory 210768 kb
Host smart-981ad305-07ca-4d1c-aff7-d50bef9f787c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667596782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1667596782
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1596071985
Short name T94
Test name
Test status
Simulation time 7400044351 ps
CPU time 38.85 seconds
Started Jul 10 06:37:24 PM PDT 24
Finished Jul 10 06:38:13 PM PDT 24
Peak memory 219000 kb
Host smart-9009c380-dea6-40b4-9a1e-cb2f43bb5313
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596071985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1596071985
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.189589210
Short name T419
Test name
Test status
Simulation time 6595874434 ps
CPU time 13.48 seconds
Started Jul 10 06:37:24 PM PDT 24
Finished Jul 10 06:37:47 PM PDT 24
Peak memory 219024 kb
Host smart-bb91fb65-eb22-4a4b-989b-755d6c1c7c29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189589210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.189589210
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.352869173
Short name T381
Test name
Test status
Simulation time 2966220110 ps
CPU time 12.48 seconds
Started Jul 10 06:37:22 PM PDT 24
Finished Jul 10 06:37:43 PM PDT 24
Peak memory 219060 kb
Host smart-d7e5b4ea-37c7-43bf-99b2-2c1dc250fb21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352869173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.352869173
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1985684262
Short name T457
Test name
Test status
Simulation time 1914573601 ps
CPU time 40.21 seconds
Started Jul 10 06:37:26 PM PDT 24
Finished Jul 10 06:38:15 PM PDT 24
Peak memory 219004 kb
Host smart-d29ad6dd-7c9c-4974-9c49-b909c1661330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985684262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1985684262
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2430268677
Short name T425
Test name
Test status
Simulation time 1550072978 ps
CPU time 12.11 seconds
Started Jul 10 06:37:23 PM PDT 24
Finished Jul 10 06:37:45 PM PDT 24
Peak memory 219068 kb
Host smart-4650482b-4b9a-4288-b642-fa28d279b493
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430268677 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2430268677
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2483361566
Short name T414
Test name
Test status
Simulation time 7733938792 ps
CPU time 8.88 seconds
Started Jul 10 06:37:22 PM PDT 24
Finished Jul 10 06:37:40 PM PDT 24
Peak memory 218956 kb
Host smart-f5fb9800-3a6e-4a57-8dfa-c2ee8f833233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483361566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2483361566
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.539331609
Short name T73
Test name
Test status
Simulation time 1089374950 ps
CPU time 27.3 seconds
Started Jul 10 06:37:22 PM PDT 24
Finished Jul 10 06:37:59 PM PDT 24
Peak memory 210768 kb
Host smart-09295810-8c1f-45cb-8a8c-8ebda9ec2441
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539331609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.539331609
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2544960955
Short name T427
Test name
Test status
Simulation time 426116375 ps
CPU time 5.88 seconds
Started Jul 10 06:37:23 PM PDT 24
Finished Jul 10 06:37:38 PM PDT 24
Peak memory 210848 kb
Host smart-94d48823-2ef4-427f-bfec-5adbfc1f9b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544960955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2544960955
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3263217040
Short name T387
Test name
Test status
Simulation time 8703649634 ps
CPU time 18.13 seconds
Started Jul 10 06:37:24 PM PDT 24
Finished Jul 10 06:37:52 PM PDT 24
Peak memory 219108 kb
Host smart-167ab8b5-2fa5-465a-9c6b-91fc682192bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263217040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3263217040
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3825989346
Short name T455
Test name
Test status
Simulation time 1548944845 ps
CPU time 71.99 seconds
Started Jul 10 06:37:24 PM PDT 24
Finished Jul 10 06:38:46 PM PDT 24
Peak memory 212416 kb
Host smart-c20709a0-b7c4-4bf0-8177-04e50049c1cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825989346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3825989346
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3034508302
Short name T386
Test name
Test status
Simulation time 643774547 ps
CPU time 5.1 seconds
Started Jul 10 06:37:31 PM PDT 24
Finished Jul 10 06:37:42 PM PDT 24
Peak memory 218968 kb
Host smart-4e521fee-ae84-4b65-9210-04ba890416c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034508302 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3034508302
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2092497886
Short name T81
Test name
Test status
Simulation time 1311052436 ps
CPU time 12.03 seconds
Started Jul 10 06:37:26 PM PDT 24
Finished Jul 10 06:37:47 PM PDT 24
Peak memory 217772 kb
Host smart-8ca4611e-cd06-4814-bbde-8497cc316d14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092497886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2092497886
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3991748358
Short name T87
Test name
Test status
Simulation time 23930180668 ps
CPU time 14.78 seconds
Started Jul 10 06:37:22 PM PDT 24
Finished Jul 10 06:37:45 PM PDT 24
Peak memory 210980 kb
Host smart-cdae7340-2e73-42aa-958b-ca87b4139509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991748358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3991748358
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2345716868
Short name T374
Test name
Test status
Simulation time 3745416539 ps
CPU time 13.56 seconds
Started Jul 10 06:37:24 PM PDT 24
Finished Jul 10 06:37:46 PM PDT 24
Peak memory 219080 kb
Host smart-697656c8-e39d-4f74-a8dd-dd8ec413ac25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345716868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2345716868
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1607149759
Short name T408
Test name
Test status
Simulation time 313603519 ps
CPU time 36.59 seconds
Started Jul 10 06:37:24 PM PDT 24
Finished Jul 10 06:38:10 PM PDT 24
Peak memory 218988 kb
Host smart-331edf24-7c15-4c5e-b947-ee8dab648d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607149759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1607149759
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4002455429
Short name T373
Test name
Test status
Simulation time 12329366212 ps
CPU time 9.47 seconds
Started Jul 10 06:36:31 PM PDT 24
Finished Jul 10 06:36:42 PM PDT 24
Peak memory 210832 kb
Host smart-b5db1547-0527-4e83-a0aa-ea2832fd10e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002455429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4002455429
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2854815915
Short name T405
Test name
Test status
Simulation time 108838296 ps
CPU time 4.86 seconds
Started Jul 10 06:36:29 PM PDT 24
Finished Jul 10 06:36:35 PM PDT 24
Peak memory 217616 kb
Host smart-b537e557-9806-466b-aa01-0986f28390ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854815915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2854815915
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2776280791
Short name T69
Test name
Test status
Simulation time 371146082 ps
CPU time 8.37 seconds
Started Jul 10 06:36:31 PM PDT 24
Finished Jul 10 06:36:40 PM PDT 24
Peak memory 217912 kb
Host smart-5f5367b3-353a-49ed-8cbd-634c66d57841
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776280791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2776280791
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3686859460
Short name T401
Test name
Test status
Simulation time 2000820759 ps
CPU time 15.82 seconds
Started Jul 10 06:36:40 PM PDT 24
Finished Jul 10 06:36:59 PM PDT 24
Peak memory 213928 kb
Host smart-9eb16159-0b07-4671-89c9-adf6228d1958
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686859460 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3686859460
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.363089937
Short name T451
Test name
Test status
Simulation time 1642943561 ps
CPU time 14.15 seconds
Started Jul 10 06:36:30 PM PDT 24
Finished Jul 10 06:36:45 PM PDT 24
Peak memory 210720 kb
Host smart-9facd653-fa69-429e-8745-220047421891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363089937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.363089937
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.105784707
Short name T439
Test name
Test status
Simulation time 1957000409 ps
CPU time 9.99 seconds
Started Jul 10 06:36:30 PM PDT 24
Finished Jul 10 06:36:41 PM PDT 24
Peak memory 210632 kb
Host smart-ccd56f73-82b1-4474-af71-982a7d269640
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105784707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.105784707
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3119357443
Short name T372
Test name
Test status
Simulation time 15560319683 ps
CPU time 9.34 seconds
Started Jul 10 06:36:23 PM PDT 24
Finished Jul 10 06:36:33 PM PDT 24
Peak memory 210704 kb
Host smart-b70d5f47-4a79-4c68-90e2-7aa4f0d7aaa2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119357443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3119357443
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1650359130
Short name T437
Test name
Test status
Simulation time 5449655906 ps
CPU time 51.11 seconds
Started Jul 10 06:36:34 PM PDT 24
Finished Jul 10 06:37:26 PM PDT 24
Peak memory 210856 kb
Host smart-b4e6ced6-dd97-41dc-bde2-cbc1af1cf6e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650359130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1650359130
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3034714115
Short name T64
Test name
Test status
Simulation time 2743563007 ps
CPU time 12.9 seconds
Started Jul 10 06:36:30 PM PDT 24
Finished Jul 10 06:36:44 PM PDT 24
Peak memory 210892 kb
Host smart-1b056f6c-245b-4488-a491-2a5ef377fbd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034714115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3034714115
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1617392997
Short name T370
Test name
Test status
Simulation time 413793844 ps
CPU time 8.74 seconds
Started Jul 10 06:36:23 PM PDT 24
Finished Jul 10 06:36:33 PM PDT 24
Peak memory 218984 kb
Host smart-4e1369c5-30da-4739-b10a-cf7a83b273ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617392997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1617392997
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2219414172
Short name T99
Test name
Test status
Simulation time 1404884979 ps
CPU time 44.43 seconds
Started Jul 10 06:36:34 PM PDT 24
Finished Jul 10 06:37:20 PM PDT 24
Peak memory 212212 kb
Host smart-d2e667ce-dbdd-4c9d-85c5-84d225e99208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219414172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2219414172
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2652944257
Short name T390
Test name
Test status
Simulation time 518322019 ps
CPU time 4.25 seconds
Started Jul 10 06:36:51 PM PDT 24
Finished Jul 10 06:36:58 PM PDT 24
Peak memory 210788 kb
Host smart-1e7de880-53ee-47cb-b834-2070b7bb5076
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652944257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2652944257
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2931404694
Short name T57
Test name
Test status
Simulation time 3278849186 ps
CPU time 14.06 seconds
Started Jul 10 06:36:36 PM PDT 24
Finished Jul 10 06:36:51 PM PDT 24
Peak memory 218512 kb
Host smart-31b58252-fcd4-4771-bb42-81e4a386c499
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931404694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2931404694
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1002936412
Short name T459
Test name
Test status
Simulation time 341098735 ps
CPU time 5.95 seconds
Started Jul 10 06:36:38 PM PDT 24
Finished Jul 10 06:36:47 PM PDT 24
Peak memory 218864 kb
Host smart-7360cc29-c47b-4558-8223-7616c47c4dad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002936412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1002936412
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4118071419
Short name T433
Test name
Test status
Simulation time 2394510688 ps
CPU time 15.73 seconds
Started Jul 10 06:36:49 PM PDT 24
Finished Jul 10 06:37:06 PM PDT 24
Peak memory 219048 kb
Host smart-276cf504-2cd0-430c-b5ec-785845436c1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118071419 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4118071419
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3023775836
Short name T93
Test name
Test status
Simulation time 2064648283 ps
CPU time 14.43 seconds
Started Jul 10 06:36:51 PM PDT 24
Finished Jul 10 06:37:07 PM PDT 24
Peak memory 210720 kb
Host smart-25c4d264-51cc-4571-a434-3d681492b653
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023775836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3023775836
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.722736489
Short name T392
Test name
Test status
Simulation time 36786233376 ps
CPU time 15.57 seconds
Started Jul 10 06:36:36 PM PDT 24
Finished Jul 10 06:36:52 PM PDT 24
Peak memory 210700 kb
Host smart-ba08fd75-99ae-42c2-93ee-27f49037d068
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722736489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.722736489
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.668451885
Short name T428
Test name
Test status
Simulation time 1574320115 ps
CPU time 13.17 seconds
Started Jul 10 06:36:37 PM PDT 24
Finished Jul 10 06:36:51 PM PDT 24
Peak memory 210636 kb
Host smart-e33e21bf-5fa3-4b19-857b-b6de9fea33a5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668451885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
668451885
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1564409067
Short name T95
Test name
Test status
Simulation time 122721193010 ps
CPU time 70.32 seconds
Started Jul 10 06:36:36 PM PDT 24
Finished Jul 10 06:37:47 PM PDT 24
Peak memory 210744 kb
Host smart-12154390-8dd8-417d-80eb-0e821145b76f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564409067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1564409067
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2404762153
Short name T90
Test name
Test status
Simulation time 1309300868 ps
CPU time 6.32 seconds
Started Jul 10 06:36:51 PM PDT 24
Finished Jul 10 06:37:00 PM PDT 24
Peak memory 210848 kb
Host smart-fd39c429-b3de-4f75-8e5f-af529756a0fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404762153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2404762153
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1005197317
Short name T383
Test name
Test status
Simulation time 263842925 ps
CPU time 9.87 seconds
Started Jul 10 06:36:40 PM PDT 24
Finished Jul 10 06:36:52 PM PDT 24
Peak memory 219020 kb
Host smart-e4e0d0d7-7e0d-4405-aba2-ad5d339f709b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005197317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1005197317
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3256821369
Short name T106
Test name
Test status
Simulation time 6879405275 ps
CPU time 75.59 seconds
Started Jul 10 06:36:51 PM PDT 24
Finished Jul 10 06:38:09 PM PDT 24
Peak memory 219076 kb
Host smart-5e6c3fec-2f1f-496d-8fdd-68081ac96db6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256821369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3256821369
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2756289950
Short name T438
Test name
Test status
Simulation time 3245541461 ps
CPU time 9.11 seconds
Started Jul 10 06:36:44 PM PDT 24
Finished Jul 10 06:36:56 PM PDT 24
Peak memory 210832 kb
Host smart-36a86112-0d85-42b2-80c0-dcc7a05e0b84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756289950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2756289950
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.371152118
Short name T391
Test name
Test status
Simulation time 126215509 ps
CPU time 5.43 seconds
Started Jul 10 06:36:43 PM PDT 24
Finished Jul 10 06:36:52 PM PDT 24
Peak memory 210768 kb
Host smart-ab1482f1-1c03-42ae-9ecd-f1e97b73dd1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371152118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.371152118
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3549188358
Short name T366
Test name
Test status
Simulation time 335781904 ps
CPU time 7.33 seconds
Started Jul 10 06:36:44 PM PDT 24
Finished Jul 10 06:36:54 PM PDT 24
Peak memory 210768 kb
Host smart-64bbd0cc-cd7e-4529-9ca6-fa14cf6482dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549188358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3549188358
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2432832875
Short name T445
Test name
Test status
Simulation time 1270828085 ps
CPU time 4.7 seconds
Started Jul 10 06:36:51 PM PDT 24
Finished Jul 10 06:36:58 PM PDT 24
Peak memory 219004 kb
Host smart-81abf314-446b-4d23-8941-b64ec2516b45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432832875 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2432832875
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3904395103
Short name T82
Test name
Test status
Simulation time 11595881927 ps
CPU time 15.06 seconds
Started Jul 10 06:36:43 PM PDT 24
Finished Jul 10 06:37:01 PM PDT 24
Peak memory 210828 kb
Host smart-c65f594e-e0c1-40c9-a5ea-7f31c5026be6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904395103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3904395103
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.941221484
Short name T435
Test name
Test status
Simulation time 12182528928 ps
CPU time 13.27 seconds
Started Jul 10 06:36:43 PM PDT 24
Finished Jul 10 06:36:59 PM PDT 24
Peak memory 210704 kb
Host smart-f2202c5a-d20c-4eb3-af93-3c5bf1140078
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941221484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.941221484
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2069265634
Short name T362
Test name
Test status
Simulation time 7167289029 ps
CPU time 14.31 seconds
Started Jul 10 06:36:44 PM PDT 24
Finished Jul 10 06:37:01 PM PDT 24
Peak memory 210664 kb
Host smart-0c1ccede-28d7-47b7-8317-38bce60e28f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069265634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2069265634
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1577374350
Short name T376
Test name
Test status
Simulation time 9113472031 ps
CPU time 44.89 seconds
Started Jul 10 06:36:44 PM PDT 24
Finished Jul 10 06:37:32 PM PDT 24
Peak memory 210848 kb
Host smart-e17c8720-4cc3-4b8e-bf47-c5f8790f140f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577374350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1577374350
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3790486429
Short name T444
Test name
Test status
Simulation time 6342214196 ps
CPU time 14.1 seconds
Started Jul 10 06:36:52 PM PDT 24
Finished Jul 10 06:37:08 PM PDT 24
Peak memory 219204 kb
Host smart-2fa4a978-48f3-48ed-80d5-39702f50c917
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790486429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3790486429
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2546464984
Short name T377
Test name
Test status
Simulation time 4721704680 ps
CPU time 14.31 seconds
Started Jul 10 06:36:44 PM PDT 24
Finished Jul 10 06:37:01 PM PDT 24
Peak memory 219072 kb
Host smart-5e700ffb-b7d6-40ce-93b0-183ec57339b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546464984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2546464984
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.827262483
Short name T97
Test name
Test status
Simulation time 4695501615 ps
CPU time 41.02 seconds
Started Jul 10 06:36:43 PM PDT 24
Finished Jul 10 06:37:25 PM PDT 24
Peak memory 219088 kb
Host smart-d2ac0439-6c9e-4280-b874-0f9b4f3ffb12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827262483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.827262483
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4110272632
Short name T396
Test name
Test status
Simulation time 100392197 ps
CPU time 5.03 seconds
Started Jul 10 06:36:52 PM PDT 24
Finished Jul 10 06:36:59 PM PDT 24
Peak memory 214756 kb
Host smart-19de4f71-23b6-4f20-8050-b0d0306bbe9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110272632 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4110272632
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.894851008
Short name T84
Test name
Test status
Simulation time 11549838625 ps
CPU time 15.51 seconds
Started Jul 10 06:36:52 PM PDT 24
Finished Jul 10 06:37:09 PM PDT 24
Peak memory 210824 kb
Host smart-2f61987a-1c0d-459e-a3cf-3a7bf76dc9cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894851008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.894851008
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.400235751
Short name T83
Test name
Test status
Simulation time 6577733679 ps
CPU time 57.66 seconds
Started Jul 10 06:36:50 PM PDT 24
Finished Jul 10 06:37:50 PM PDT 24
Peak memory 210832 kb
Host smart-627e7062-8b10-4cfd-95c3-6e4d720c96b5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400235751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.400235751
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1517043016
Short name T461
Test name
Test status
Simulation time 17793811296 ps
CPU time 14.17 seconds
Started Jul 10 06:36:50 PM PDT 24
Finished Jul 10 06:37:05 PM PDT 24
Peak memory 210900 kb
Host smart-b4398efd-4acf-49f1-a595-96bc637a9d53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517043016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1517043016
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1456894373
Short name T397
Test name
Test status
Simulation time 1811403633 ps
CPU time 12.08 seconds
Started Jul 10 06:36:50 PM PDT 24
Finished Jul 10 06:37:04 PM PDT 24
Peak memory 219004 kb
Host smart-e4188e5f-1c49-4bf2-b667-ac20a380884f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456894373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1456894373
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.327889814
Short name T426
Test name
Test status
Simulation time 95221675 ps
CPU time 4.97 seconds
Started Jul 10 06:37:00 PM PDT 24
Finished Jul 10 06:37:07 PM PDT 24
Peak memory 218980 kb
Host smart-54d30b95-40dd-486c-a6bc-c47a26dc3ea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327889814 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.327889814
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.569614184
Short name T443
Test name
Test status
Simulation time 195397703 ps
CPU time 4.26 seconds
Started Jul 10 06:36:50 PM PDT 24
Finished Jul 10 06:36:57 PM PDT 24
Peak memory 210760 kb
Host smart-ecf4375f-7898-42c5-9764-d9f41c9ab971
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569614184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.569614184
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2069976865
Short name T416
Test name
Test status
Simulation time 6180708898 ps
CPU time 13.65 seconds
Started Jul 10 06:36:59 PM PDT 24
Finished Jul 10 06:37:15 PM PDT 24
Peak memory 210996 kb
Host smart-0da5e511-6a68-4dbf-b14a-a6f5b0cac0ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069976865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2069976865
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2115266973
Short name T406
Test name
Test status
Simulation time 121191611 ps
CPU time 8.58 seconds
Started Jul 10 06:36:49 PM PDT 24
Finished Jul 10 06:36:59 PM PDT 24
Peak memory 216648 kb
Host smart-eb7f6688-8fee-4c70-96f2-a42854457655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115266973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2115266973
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.96697764
Short name T53
Test name
Test status
Simulation time 5210978030 ps
CPU time 74.2 seconds
Started Jul 10 06:36:50 PM PDT 24
Finished Jul 10 06:38:06 PM PDT 24
Peak memory 219088 kb
Host smart-a6ccb25e-c581-4dcc-ac53-ce4a42a1a422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96697764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg
_err.96697764
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4239169718
Short name T434
Test name
Test status
Simulation time 291596948 ps
CPU time 4.87 seconds
Started Jul 10 06:37:02 PM PDT 24
Finished Jul 10 06:37:09 PM PDT 24
Peak memory 219068 kb
Host smart-279bb106-4823-4b2d-97ad-9fdd6b501734
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239169718 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4239169718
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2434916304
Short name T379
Test name
Test status
Simulation time 944498028 ps
CPU time 7.14 seconds
Started Jul 10 06:36:57 PM PDT 24
Finished Jul 10 06:37:07 PM PDT 24
Peak memory 210692 kb
Host smart-498d4e77-abd3-4975-85a3-391b28bbf72e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434916304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2434916304
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1092617033
Short name T67
Test name
Test status
Simulation time 6749264715 ps
CPU time 39.41 seconds
Started Jul 10 06:36:58 PM PDT 24
Finished Jul 10 06:37:39 PM PDT 24
Peak memory 217892 kb
Host smart-6c673b0d-5024-4b05-9194-2f389270cac2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092617033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1092617033
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3657621633
Short name T411
Test name
Test status
Simulation time 174684087 ps
CPU time 4.46 seconds
Started Jul 10 06:36:58 PM PDT 24
Finished Jul 10 06:37:05 PM PDT 24
Peak memory 210828 kb
Host smart-dae25402-b304-4375-bee1-2e7544dcd2d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657621633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3657621633
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3220443006
Short name T436
Test name
Test status
Simulation time 1425602487 ps
CPU time 11.67 seconds
Started Jul 10 06:36:57 PM PDT 24
Finished Jul 10 06:37:11 PM PDT 24
Peak memory 219000 kb
Host smart-7045e38d-6cea-440a-8f4d-d7c331db53ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220443006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3220443006
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2070970027
Short name T105
Test name
Test status
Simulation time 16982487355 ps
CPU time 71.04 seconds
Started Jul 10 06:36:58 PM PDT 24
Finished Jul 10 06:38:11 PM PDT 24
Peak memory 219084 kb
Host smart-c0c5c46a-b953-49a3-a1af-efea456f9845
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070970027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2070970027
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.493778260
Short name T403
Test name
Test status
Simulation time 99906386 ps
CPU time 4.86 seconds
Started Jul 10 06:37:03 PM PDT 24
Finished Jul 10 06:37:10 PM PDT 24
Peak memory 219028 kb
Host smart-735a9d41-b8bf-44c7-a7d1-c5f1ef77a1cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493778260 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.493778260
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.179359948
Short name T431
Test name
Test status
Simulation time 1378426154 ps
CPU time 4.32 seconds
Started Jul 10 06:37:04 PM PDT 24
Finished Jul 10 06:37:11 PM PDT 24
Peak memory 210756 kb
Host smart-74a3e7fb-19cb-4199-9375-54a1c7d4a077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179359948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.179359948
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1053023463
Short name T56
Test name
Test status
Simulation time 29729242889 ps
CPU time 53.92 seconds
Started Jul 10 06:37:04 PM PDT 24
Finished Jul 10 06:38:00 PM PDT 24
Peak memory 210852 kb
Host smart-45a7ce9c-8db5-4280-804a-d5ed6a0e006a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053023463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1053023463
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3403440454
Short name T85
Test name
Test status
Simulation time 1889396339 ps
CPU time 15.61 seconds
Started Jul 10 06:37:05 PM PDT 24
Finished Jul 10 06:37:23 PM PDT 24
Peak memory 210824 kb
Host smart-1e2f5c95-09f4-40b4-84e6-063ea9711b2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403440454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3403440454
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.872585593
Short name T394
Test name
Test status
Simulation time 1890069616 ps
CPU time 17.22 seconds
Started Jul 10 06:37:04 PM PDT 24
Finished Jul 10 06:37:24 PM PDT 24
Peak memory 218916 kb
Host smart-2d2767d6-ea09-4e6a-91f3-ee1c5ab17f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872585593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.872585593
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3788488002
Short name T384
Test name
Test status
Simulation time 102364046 ps
CPU time 5.07 seconds
Started Jul 10 06:37:06 PM PDT 24
Finished Jul 10 06:37:15 PM PDT 24
Peak memory 219068 kb
Host smart-a4ddbbed-64c1-4dc5-8172-4ce9c776e25f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788488002 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3788488002
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.918034431
Short name T395
Test name
Test status
Simulation time 543065307 ps
CPU time 7.85 seconds
Started Jul 10 06:37:04 PM PDT 24
Finished Jul 10 06:37:14 PM PDT 24
Peak memory 218192 kb
Host smart-b3126b33-facc-495f-ad3f-37db82ecb4ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918034431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.918034431
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1910424959
Short name T68
Test name
Test status
Simulation time 14765178440 ps
CPU time 96.31 seconds
Started Jul 10 06:37:02 PM PDT 24
Finished Jul 10 06:38:41 PM PDT 24
Peak memory 210908 kb
Host smart-3891cd1c-6948-4312-aa9c-c4a30dbaffaf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910424959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1910424959
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1797186302
Short name T452
Test name
Test status
Simulation time 2687133388 ps
CPU time 8.39 seconds
Started Jul 10 06:37:04 PM PDT 24
Finished Jul 10 06:37:14 PM PDT 24
Peak memory 211068 kb
Host smart-15528fa1-b709-42fb-a4f8-f324e8617465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797186302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1797186302
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1874886464
Short name T378
Test name
Test status
Simulation time 2078419970 ps
CPU time 20.34 seconds
Started Jul 10 06:37:05 PM PDT 24
Finished Jul 10 06:37:28 PM PDT 24
Peak memory 219004 kb
Host smart-2c15fce9-a41d-452a-a411-19bdd0e3f9b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874886464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1874886464
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2472101696
Short name T109
Test name
Test status
Simulation time 6888575414 ps
CPU time 46.57 seconds
Started Jul 10 06:37:05 PM PDT 24
Finished Jul 10 06:37:54 PM PDT 24
Peak memory 219032 kb
Host smart-614c7f70-dce5-4421-87c7-f6536563db76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472101696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2472101696
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1396410378
Short name T224
Test name
Test status
Simulation time 918565077 ps
CPU time 4.27 seconds
Started Jul 10 06:02:17 PM PDT 24
Finished Jul 10 06:02:23 PM PDT 24
Peak memory 211172 kb
Host smart-6e8f19c4-117b-43a2-8282-965f1754765e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396410378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1396410378
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3192081006
Short name T354
Test name
Test status
Simulation time 135904726686 ps
CPU time 296.53 seconds
Started Jul 10 06:02:09 PM PDT 24
Finished Jul 10 06:07:06 PM PDT 24
Peak memory 232924 kb
Host smart-f3e99f9a-346f-471d-b32b-a633b8a57c5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192081006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3192081006
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.723675317
Short name T307
Test name
Test status
Simulation time 2728742951 ps
CPU time 24.11 seconds
Started Jul 10 06:02:11 PM PDT 24
Finished Jul 10 06:02:36 PM PDT 24
Peak memory 211468 kb
Host smart-3632e85b-644c-49ca-bb88-1ffd28acf79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723675317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.723675317
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2801075578
Short name T145
Test name
Test status
Simulation time 3252074468 ps
CPU time 18.08 seconds
Started Jul 10 06:02:09 PM PDT 24
Finished Jul 10 06:02:28 PM PDT 24
Peak memory 211408 kb
Host smart-d9828944-c909-47e1-aef9-db92b67b2f6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2801075578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2801075578
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1823816802
Short name T27
Test name
Test status
Simulation time 10168094725 ps
CPU time 109.29 seconds
Started Jul 10 06:02:09 PM PDT 24
Finished Jul 10 06:03:59 PM PDT 24
Peak memory 236608 kb
Host smart-5baf6f2a-afe4-49a2-9a8c-0e2313803072
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823816802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1823816802
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3494576571
Short name T203
Test name
Test status
Simulation time 18580878494 ps
CPU time 33.78 seconds
Started Jul 10 06:02:09 PM PDT 24
Finished Jul 10 06:02:43 PM PDT 24
Peak memory 214100 kb
Host smart-b75721d5-5473-436f-9034-c4c94f7b7630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494576571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3494576571
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1320077988
Short name T264
Test name
Test status
Simulation time 13975919391 ps
CPU time 67.99 seconds
Started Jul 10 06:02:11 PM PDT 24
Finished Jul 10 06:03:19 PM PDT 24
Peak memory 217132 kb
Host smart-6764ce6a-16d1-49bd-9c0b-c64be56ec427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320077988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1320077988
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1592725440
Short name T241
Test name
Test status
Simulation time 6931449186 ps
CPU time 15.39 seconds
Started Jul 10 06:02:08 PM PDT 24
Finished Jul 10 06:02:25 PM PDT 24
Peak memory 211428 kb
Host smart-a1427eaf-9dd2-492a-81b8-27768a905233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592725440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1592725440
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.114533675
Short name T132
Test name
Test status
Simulation time 544767110 ps
CPU time 5.5 seconds
Started Jul 10 06:02:16 PM PDT 24
Finished Jul 10 06:02:23 PM PDT 24
Peak memory 211392 kb
Host smart-4cf56ed2-4a97-4a68-ad6c-9ea949695076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114533675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.114533675
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3782087086
Short name T28
Test name
Test status
Simulation time 1467002319 ps
CPU time 107.27 seconds
Started Jul 10 06:02:09 PM PDT 24
Finished Jul 10 06:03:57 PM PDT 24
Peak memory 237628 kb
Host smart-633fb9d2-6ad6-4986-a485-5c0d8d9b2138
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782087086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3782087086
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2636404308
Short name T357
Test name
Test status
Simulation time 7861766546 ps
CPU time 37.22 seconds
Started Jul 10 06:02:07 PM PDT 24
Finished Jul 10 06:02:45 PM PDT 24
Peak memory 214172 kb
Host smart-cb93ffb2-ee1a-46bb-8ca2-a8ab8697f870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636404308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2636404308
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2352333827
Short name T218
Test name
Test status
Simulation time 40638237159 ps
CPU time 107.76 seconds
Started Jul 10 06:02:08 PM PDT 24
Finished Jul 10 06:03:57 PM PDT 24
Peak memory 217448 kb
Host smart-c3ed908b-18f4-4735-ae57-8624bcb0cc0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352333827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2352333827
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.316507606
Short name T22
Test name
Test status
Simulation time 347405704 ps
CPU time 4.4 seconds
Started Jul 10 06:02:23 PM PDT 24
Finished Jul 10 06:02:29 PM PDT 24
Peak memory 211340 kb
Host smart-2488ebff-6344-4c1b-bca4-0e5897a41c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316507606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.316507606
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.904861919
Short name T336
Test name
Test status
Simulation time 28438842003 ps
CPU time 316.81 seconds
Started Jul 10 06:02:27 PM PDT 24
Finished Jul 10 06:07:45 PM PDT 24
Peak memory 236876 kb
Host smart-1681885e-e329-4f8a-9ca7-38ab451822bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904861919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.904861919
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.330904161
Short name T233
Test name
Test status
Simulation time 990187426 ps
CPU time 16.56 seconds
Started Jul 10 06:02:26 PM PDT 24
Finished Jul 10 06:02:44 PM PDT 24
Peak memory 212032 kb
Host smart-10e7ed2b-33b3-46a8-9847-c59c775e302e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330904161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.330904161
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.5474174
Short name T9
Test name
Test status
Simulation time 678752423 ps
CPU time 5.82 seconds
Started Jul 10 06:02:24 PM PDT 24
Finished Jul 10 06:02:31 PM PDT 24
Peak memory 211380 kb
Host smart-baa8f398-18f4-4cc4-ba48-b023988de041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5474174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.5474174
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2808200616
Short name T281
Test name
Test status
Simulation time 15807322882 ps
CPU time 36.17 seconds
Started Jul 10 06:02:26 PM PDT 24
Finished Jul 10 06:03:04 PM PDT 24
Peak memory 212556 kb
Host smart-6916b70b-9025-4f64-bc3b-98093c7d7195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808200616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2808200616
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1638751675
Short name T193
Test name
Test status
Simulation time 2134364380 ps
CPU time 44.88 seconds
Started Jul 10 06:02:25 PM PDT 24
Finished Jul 10 06:03:11 PM PDT 24
Peak memory 215564 kb
Host smart-574325d1-f17c-4217-83b5-b432b330b95d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638751675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1638751675
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2190078683
Short name T240
Test name
Test status
Simulation time 990257872 ps
CPU time 6.24 seconds
Started Jul 10 06:02:24 PM PDT 24
Finished Jul 10 06:02:32 PM PDT 24
Peak memory 211364 kb
Host smart-c0cae7de-0438-4111-95d9-aa1bf30a3ac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190078683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2190078683
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.91685028
Short name T251
Test name
Test status
Simulation time 56199948000 ps
CPU time 248 seconds
Started Jul 10 06:02:26 PM PDT 24
Finished Jul 10 06:06:35 PM PDT 24
Peak memory 213676 kb
Host smart-8a289dd8-5686-4880-b89f-95de6bba0d8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91685028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_co
rrupt_sig_fatal_chk.91685028
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.92025822
Short name T178
Test name
Test status
Simulation time 2384998592 ps
CPU time 24.82 seconds
Started Jul 10 06:02:25 PM PDT 24
Finished Jul 10 06:02:51 PM PDT 24
Peak memory 212048 kb
Host smart-a0e77df3-71ae-43a3-949c-c3bf318bda5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92025822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.92025822
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3510956416
Short name T302
Test name
Test status
Simulation time 793316280 ps
CPU time 10.32 seconds
Started Jul 10 06:02:24 PM PDT 24
Finished Jul 10 06:02:35 PM PDT 24
Peak memory 211348 kb
Host smart-d69f4b04-d080-4b0f-ab4c-dd60e02dcb0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510956416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3510956416
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1465931171
Short name T315
Test name
Test status
Simulation time 4477491084 ps
CPU time 23.88 seconds
Started Jul 10 06:02:24 PM PDT 24
Finished Jul 10 06:02:49 PM PDT 24
Peak memory 213940 kb
Host smart-64284b89-60cc-44d9-b7f4-706f192b091e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465931171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1465931171
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2883906441
Short name T51
Test name
Test status
Simulation time 4102203249 ps
CPU time 16.3 seconds
Started Jul 10 06:02:26 PM PDT 24
Finished Jul 10 06:02:43 PM PDT 24
Peak memory 211352 kb
Host smart-763ffc6e-7354-4844-9768-defdd20797f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883906441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2883906441
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1247355089
Short name T319
Test name
Test status
Simulation time 1612559567 ps
CPU time 13.28 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:02:46 PM PDT 24
Peak memory 211356 kb
Host smart-5738a03a-a035-4c59-8d3d-2a3649d02b8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247355089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1247355089
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2710761946
Short name T150
Test name
Test status
Simulation time 2552649060 ps
CPU time 70.34 seconds
Started Jul 10 06:02:26 PM PDT 24
Finished Jul 10 06:03:37 PM PDT 24
Peak memory 224700 kb
Host smart-1fb32fa8-1ff4-466e-a15f-a1a328dc2438
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710761946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2710761946
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2957800571
Short name T223
Test name
Test status
Simulation time 8030779335 ps
CPU time 27.85 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:03:01 PM PDT 24
Peak memory 212836 kb
Host smart-bd504031-2997-49a2-8d1d-d43d3f53eba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957800571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2957800571
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4097224845
Short name T201
Test name
Test status
Simulation time 1110940605 ps
CPU time 12.03 seconds
Started Jul 10 06:02:25 PM PDT 24
Finished Jul 10 06:02:38 PM PDT 24
Peak memory 211368 kb
Host smart-5db2f5d5-d614-4e89-96bc-d40b8a2bd6fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097224845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4097224845
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3268427917
Short name T212
Test name
Test status
Simulation time 4107436950 ps
CPU time 34.14 seconds
Started Jul 10 06:02:27 PM PDT 24
Finished Jul 10 06:03:02 PM PDT 24
Peak memory 213160 kb
Host smart-845c48f4-7f6e-4dd9-8779-21373067d059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268427917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3268427917
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1083885257
Short name T156
Test name
Test status
Simulation time 6625556304 ps
CPU time 70.85 seconds
Started Jul 10 06:02:30 PM PDT 24
Finished Jul 10 06:03:42 PM PDT 24
Peak memory 219424 kb
Host smart-80884523-3316-4e7a-979a-3a6140a3dde1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083885257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1083885257
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.126210225
Short name T346
Test name
Test status
Simulation time 375365047 ps
CPU time 6.92 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:02:41 PM PDT 24
Peak memory 211304 kb
Host smart-282e971d-2d03-4901-80da-bc5447117789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126210225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.126210225
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2254899443
Short name T33
Test name
Test status
Simulation time 32466744941 ps
CPU time 302.3 seconds
Started Jul 10 06:02:29 PM PDT 24
Finished Jul 10 06:07:32 PM PDT 24
Peak memory 237868 kb
Host smart-bf4807c7-271d-4e0b-8b26-130fb77219bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254899443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2254899443
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2029432923
Short name T322
Test name
Test status
Simulation time 5269159757 ps
CPU time 18.42 seconds
Started Jul 10 06:02:30 PM PDT 24
Finished Jul 10 06:02:50 PM PDT 24
Peak memory 212208 kb
Host smart-c2765e9a-54d9-457c-9728-ad2e4ac26656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029432923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2029432923
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3920146482
Short name T11
Test name
Test status
Simulation time 1677973385 ps
CPU time 14.66 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:02:48 PM PDT 24
Peak memory 211404 kb
Host smart-3483a8f8-5fbd-433e-87e6-073e39ceff00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920146482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3920146482
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.969178498
Short name T232
Test name
Test status
Simulation time 3683519653 ps
CPU time 20.28 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:02:53 PM PDT 24
Peak memory 213140 kb
Host smart-b7bb5b3b-1126-4241-b499-424ba5e02782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969178498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.969178498
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3038787030
Short name T192
Test name
Test status
Simulation time 5599330600 ps
CPU time 51.48 seconds
Started Jul 10 06:02:32 PM PDT 24
Finished Jul 10 06:03:26 PM PDT 24
Peak memory 215792 kb
Host smart-23a59753-e9e9-464d-bebd-8711c7999624
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038787030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3038787030
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3932505231
Short name T231
Test name
Test status
Simulation time 657366587 ps
CPU time 8.35 seconds
Started Jul 10 06:02:32 PM PDT 24
Finished Jul 10 06:02:43 PM PDT 24
Peak memory 211376 kb
Host smart-e56b7450-1f31-489e-89f2-63964bf2f147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932505231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3932505231
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4085102096
Short name T113
Test name
Test status
Simulation time 42725204722 ps
CPU time 415.76 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:09:29 PM PDT 24
Peak memory 228528 kb
Host smart-b98661fa-92d0-4a66-be51-e50eb1fca25d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085102096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4085102096
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1878666081
Short name T180
Test name
Test status
Simulation time 2670260298 ps
CPU time 17.59 seconds
Started Jul 10 06:02:29 PM PDT 24
Finished Jul 10 06:02:47 PM PDT 24
Peak memory 212024 kb
Host smart-9122ef47-14bf-427b-bcfd-13c3cc98e0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878666081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1878666081
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4109930698
Short name T146
Test name
Test status
Simulation time 7526658443 ps
CPU time 16.45 seconds
Started Jul 10 06:02:30 PM PDT 24
Finished Jul 10 06:02:48 PM PDT 24
Peak memory 211456 kb
Host smart-3cd8a66b-2e42-4cbb-b7e4-bc10c796acf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4109930698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4109930698
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.494253451
Short name T52
Test name
Test status
Simulation time 750787745 ps
CPU time 9.95 seconds
Started Jul 10 06:02:29 PM PDT 24
Finished Jul 10 06:02:40 PM PDT 24
Peak memory 213540 kb
Host smart-8bef9f6f-cd0e-4d90-a7b9-707da9e96760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494253451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.494253451
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2761806306
Short name T63
Test name
Test status
Simulation time 4230298720 ps
CPU time 11.08 seconds
Started Jul 10 06:02:32 PM PDT 24
Finished Jul 10 06:02:45 PM PDT 24
Peak memory 211572 kb
Host smart-2eaf21ea-ac82-4436-87ba-91869c4877cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761806306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2761806306
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.693550800
Short name T217
Test name
Test status
Simulation time 2888449028 ps
CPU time 91.79 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:04:05 PM PDT 24
Peak memory 225072 kb
Host smart-63063f57-0d50-4548-ab34-37b3e7627e82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693550800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.693550800
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3664067702
Short name T308
Test name
Test status
Simulation time 12612123526 ps
CPU time 34.57 seconds
Started Jul 10 06:02:33 PM PDT 24
Finished Jul 10 06:03:09 PM PDT 24
Peak memory 212292 kb
Host smart-e8b9e578-835e-490b-84be-253571dd2035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664067702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3664067702
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3841517938
Short name T172
Test name
Test status
Simulation time 3380097325 ps
CPU time 14.31 seconds
Started Jul 10 06:02:32 PM PDT 24
Finished Jul 10 06:02:48 PM PDT 24
Peak memory 211460 kb
Host smart-26633925-fa88-48a2-a5b8-0cae7136b079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3841517938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3841517938
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2359137995
Short name T79
Test name
Test status
Simulation time 2769234012 ps
CPU time 30 seconds
Started Jul 10 06:02:29 PM PDT 24
Finished Jul 10 06:03:00 PM PDT 24
Peak memory 213044 kb
Host smart-71496fd8-4d10-418a-bb06-f5142f63adba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359137995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2359137995
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2155644019
Short name T358
Test name
Test status
Simulation time 16583491425 ps
CPU time 51.31 seconds
Started Jul 10 06:02:28 PM PDT 24
Finished Jul 10 06:03:20 PM PDT 24
Peak memory 216676 kb
Host smart-5ae174a1-68a9-4865-b95c-f2ec65471a2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155644019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2155644019
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1264109231
Short name T194
Test name
Test status
Simulation time 2122334494 ps
CPU time 16.16 seconds
Started Jul 10 06:02:33 PM PDT 24
Finished Jul 10 06:02:51 PM PDT 24
Peak memory 211332 kb
Host smart-1857196c-8e9e-4c1e-b1fa-5bebf86ed487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264109231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1264109231
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3887701896
Short name T42
Test name
Test status
Simulation time 8053222569 ps
CPU time 136.6 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:04:51 PM PDT 24
Peak memory 237868 kb
Host smart-aa3d6972-880c-4dac-87da-c0f336124316
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887701896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3887701896
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1390019282
Short name T198
Test name
Test status
Simulation time 2202518284 ps
CPU time 23.22 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:02:56 PM PDT 24
Peak memory 212076 kb
Host smart-e541222f-e127-47ec-90b9-4ff5abde257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390019282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1390019282
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2410120648
Short name T274
Test name
Test status
Simulation time 2411537128 ps
CPU time 12.26 seconds
Started Jul 10 06:02:34 PM PDT 24
Finished Jul 10 06:02:47 PM PDT 24
Peak memory 211448 kb
Host smart-238c43f8-1434-4ee6-8850-ed6097251eee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410120648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2410120648
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1792397584
Short name T196
Test name
Test status
Simulation time 4765911897 ps
CPU time 23.61 seconds
Started Jul 10 06:02:30 PM PDT 24
Finished Jul 10 06:02:55 PM PDT 24
Peak memory 212492 kb
Host smart-45780b98-1f04-4285-beca-a3e815ae9f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792397584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1792397584
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2985464880
Short name T170
Test name
Test status
Simulation time 3158168518 ps
CPU time 25.24 seconds
Started Jul 10 06:02:30 PM PDT 24
Finished Jul 10 06:02:56 PM PDT 24
Peak memory 216652 kb
Host smart-35008e8f-5a48-4ffd-b56b-304524a6bb03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985464880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2985464880
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1610730310
Short name T325
Test name
Test status
Simulation time 2222007306 ps
CPU time 11.26 seconds
Started Jul 10 06:02:30 PM PDT 24
Finished Jul 10 06:02:43 PM PDT 24
Peak memory 211432 kb
Host smart-5bc8d465-616c-465b-99fe-9ae2144cd0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610730310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1610730310
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.234343146
Short name T356
Test name
Test status
Simulation time 33993107292 ps
CPU time 111.37 seconds
Started Jul 10 06:02:35 PM PDT 24
Finished Jul 10 06:04:27 PM PDT 24
Peak memory 225148 kb
Host smart-9d511369-3e59-4c16-9056-bc52eba0ca93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234343146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.234343146
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1343377075
Short name T30
Test name
Test status
Simulation time 2656397074 ps
CPU time 24.48 seconds
Started Jul 10 06:02:30 PM PDT 24
Finished Jul 10 06:02:56 PM PDT 24
Peak memory 211936 kb
Host smart-46af6135-c9a2-4d5c-83ff-3e8abbc07c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343377075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1343377075
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2799405982
Short name T111
Test name
Test status
Simulation time 938765888 ps
CPU time 8.28 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:02:42 PM PDT 24
Peak memory 211400 kb
Host smart-e9f1127c-f5c4-49c2-ba52-5c9ae745463d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799405982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2799405982
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.505550791
Short name T75
Test name
Test status
Simulation time 14019398812 ps
CPU time 40.89 seconds
Started Jul 10 06:02:28 PM PDT 24
Finished Jul 10 06:03:10 PM PDT 24
Peak memory 214160 kb
Host smart-8c51f1da-ddab-4476-bf72-25451836ffd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505550791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.505550791
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4276560801
Short name T26
Test name
Test status
Simulation time 9191804252 ps
CPU time 70.11 seconds
Started Jul 10 06:02:30 PM PDT 24
Finished Jul 10 06:03:41 PM PDT 24
Peak memory 219416 kb
Host smart-c33cf6c0-8d45-425c-abc3-03305306a623
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276560801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4276560801
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1026986895
Short name T122
Test name
Test status
Simulation time 951947809 ps
CPU time 10.03 seconds
Started Jul 10 06:02:39 PM PDT 24
Finished Jul 10 06:02:51 PM PDT 24
Peak memory 211348 kb
Host smart-16330175-3634-4b45-916d-304083483400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026986895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1026986895
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1249459455
Short name T213
Test name
Test status
Simulation time 70379766232 ps
CPU time 133.59 seconds
Started Jul 10 06:02:37 PM PDT 24
Finished Jul 10 06:04:52 PM PDT 24
Peak memory 212604 kb
Host smart-0c00708e-178c-4f01-8cb1-2b080ab9290b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249459455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1249459455
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2125998038
Short name T179
Test name
Test status
Simulation time 173504523 ps
CPU time 9.51 seconds
Started Jul 10 06:02:40 PM PDT 24
Finished Jul 10 06:02:51 PM PDT 24
Peak memory 212048 kb
Host smart-c71572fb-228b-4a3c-9ab5-fa7c3189dd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125998038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2125998038
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1085087380
Short name T320
Test name
Test status
Simulation time 1610587432 ps
CPU time 14.67 seconds
Started Jul 10 06:02:31 PM PDT 24
Finished Jul 10 06:02:47 PM PDT 24
Peak memory 211408 kb
Host smart-83c62c7c-748e-44ff-a6e0-936d7eab878d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085087380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1085087380
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1361307557
Short name T246
Test name
Test status
Simulation time 1579805528 ps
CPU time 12.84 seconds
Started Jul 10 06:02:35 PM PDT 24
Finished Jul 10 06:02:49 PM PDT 24
Peak memory 213988 kb
Host smart-735fcc91-54a7-442b-b191-173cddc357ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361307557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1361307557
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3534691895
Short name T229
Test name
Test status
Simulation time 7215195778 ps
CPU time 76.33 seconds
Started Jul 10 06:02:29 PM PDT 24
Finished Jul 10 06:03:46 PM PDT 24
Peak memory 218544 kb
Host smart-503906d1-467c-4cd2-9aa1-20cc7534fa0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534691895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3534691895
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3812929476
Short name T341
Test name
Test status
Simulation time 1745879650 ps
CPU time 6.84 seconds
Started Jul 10 06:02:38 PM PDT 24
Finished Jul 10 06:02:47 PM PDT 24
Peak memory 211304 kb
Host smart-d45d372e-1ee9-473b-a050-e2d685575269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812929476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3812929476
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1976292527
Short name T311
Test name
Test status
Simulation time 58495919024 ps
CPU time 185.93 seconds
Started Jul 10 06:02:38 PM PDT 24
Finished Jul 10 06:05:46 PM PDT 24
Peak memory 212652 kb
Host smart-b2da1720-68e4-4a7f-9e15-ed4bd6c6eb7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976292527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1976292527
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2310508293
Short name T244
Test name
Test status
Simulation time 2518096220 ps
CPU time 13.79 seconds
Started Jul 10 06:02:41 PM PDT 24
Finished Jul 10 06:02:57 PM PDT 24
Peak memory 212192 kb
Host smart-cbaeeed6-9480-4249-b294-e1dffcf942d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310508293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2310508293
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.647768803
Short name T110
Test name
Test status
Simulation time 7720554524 ps
CPU time 16.13 seconds
Started Jul 10 06:02:37 PM PDT 24
Finished Jul 10 06:02:54 PM PDT 24
Peak memory 211408 kb
Host smart-013114c2-4eb9-4bb2-9cc5-71a47ab60df8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647768803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.647768803
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.36771077
Short name T351
Test name
Test status
Simulation time 2913067022 ps
CPU time 14.67 seconds
Started Jul 10 06:02:38 PM PDT 24
Finished Jul 10 06:02:54 PM PDT 24
Peak memory 213856 kb
Host smart-e18d5e12-5070-4e32-ab7e-a03277e0c013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36771077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.36771077
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2968778396
Short name T128
Test name
Test status
Simulation time 1002877792 ps
CPU time 13.3 seconds
Started Jul 10 06:02:41 PM PDT 24
Finished Jul 10 06:02:56 PM PDT 24
Peak memory 212428 kb
Host smart-b98556b4-7a84-4256-b75c-23b2bd0d49b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968778396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2968778396
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2185018352
Short name T45
Test name
Test status
Simulation time 48937924599 ps
CPU time 657.69 seconds
Started Jul 10 06:02:39 PM PDT 24
Finished Jul 10 06:13:38 PM PDT 24
Peak memory 232224 kb
Host smart-1dac3196-fbc9-4260-9bc3-6c000d3823dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185018352 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2185018352
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.515671063
Short name T168
Test name
Test status
Simulation time 2871082448 ps
CPU time 13.98 seconds
Started Jul 10 06:02:15 PM PDT 24
Finished Jul 10 06:02:29 PM PDT 24
Peak memory 211572 kb
Host smart-dddf61e2-ebc3-4633-b17e-db730d3c5ae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515671063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.515671063
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4204742579
Short name T43
Test name
Test status
Simulation time 115871504304 ps
CPU time 288.85 seconds
Started Jul 10 06:02:12 PM PDT 24
Finished Jul 10 06:07:02 PM PDT 24
Peak memory 237908 kb
Host smart-71b5f78f-5924-4acc-b090-2cc92d1c2709
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204742579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4204742579
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3369329548
Short name T163
Test name
Test status
Simulation time 4381760916 ps
CPU time 35.7 seconds
Started Jul 10 06:02:14 PM PDT 24
Finished Jul 10 06:02:51 PM PDT 24
Peak memory 212336 kb
Host smart-c78130be-b0f9-4114-8ebf-88e8562a25c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369329548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3369329548
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1518662367
Short name T173
Test name
Test status
Simulation time 100009774 ps
CPU time 5.68 seconds
Started Jul 10 06:02:13 PM PDT 24
Finished Jul 10 06:02:20 PM PDT 24
Peak memory 211400 kb
Host smart-b4212a3c-cc3c-4d02-8c5e-6136847aac83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518662367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1518662367
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3741823213
Short name T326
Test name
Test status
Simulation time 12480616467 ps
CPU time 28.97 seconds
Started Jul 10 06:02:08 PM PDT 24
Finished Jul 10 06:02:38 PM PDT 24
Peak memory 213848 kb
Host smart-dc2685dd-53ea-456a-ab99-1e58e017f19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741823213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3741823213
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.913794126
Short name T6
Test name
Test status
Simulation time 4379566419 ps
CPU time 42 seconds
Started Jul 10 06:02:12 PM PDT 24
Finished Jul 10 06:02:55 PM PDT 24
Peak memory 217076 kb
Host smart-7dddea66-251b-46bd-b898-8b91d03745be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913794126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.913794126
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2084967037
Short name T119
Test name
Test status
Simulation time 2121238179 ps
CPU time 7.95 seconds
Started Jul 10 06:02:38 PM PDT 24
Finished Jul 10 06:02:48 PM PDT 24
Peak memory 211304 kb
Host smart-59008932-e1f4-444c-8274-67cb510e3668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084967037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2084967037
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2439011831
Short name T209
Test name
Test status
Simulation time 13079501388 ps
CPU time 149.22 seconds
Started Jul 10 06:02:35 PM PDT 24
Finished Jul 10 06:05:05 PM PDT 24
Peak memory 228012 kb
Host smart-aae4fb3c-c3b1-4f7c-9ba0-446bda6328dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439011831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2439011831
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4019519250
Short name T153
Test name
Test status
Simulation time 439072350 ps
CPU time 9.52 seconds
Started Jul 10 06:02:41 PM PDT 24
Finished Jul 10 06:02:52 PM PDT 24
Peak memory 211992 kb
Host smart-0293b8f7-e570-4063-8fd4-c9b15e5f96ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019519250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4019519250
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3065031592
Short name T142
Test name
Test status
Simulation time 1986509196 ps
CPU time 11.02 seconds
Started Jul 10 06:02:37 PM PDT 24
Finished Jul 10 06:02:49 PM PDT 24
Peak memory 211416 kb
Host smart-f365eac1-5824-44d7-8a73-13737d3ea635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065031592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3065031592
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2874099075
Short name T294
Test name
Test status
Simulation time 9233195727 ps
CPU time 28.47 seconds
Started Jul 10 06:02:36 PM PDT 24
Finished Jul 10 06:03:05 PM PDT 24
Peak memory 213900 kb
Host smart-c5689c40-a74e-4bbf-ae16-cc969a44cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874099075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2874099075
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2230166339
Short name T242
Test name
Test status
Simulation time 2851848511 ps
CPU time 31.43 seconds
Started Jul 10 06:02:42 PM PDT 24
Finished Jul 10 06:03:15 PM PDT 24
Peak memory 214132 kb
Host smart-35a44d82-829e-4a40-ad34-2c4ef78ebfec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230166339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2230166339
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.4109833745
Short name T49
Test name
Test status
Simulation time 199057562460 ps
CPU time 6532.51 seconds
Started Jul 10 06:02:40 PM PDT 24
Finished Jul 10 07:51:35 PM PDT 24
Peak memory 238276 kb
Host smart-3516d401-19f0-41a8-8c13-9a9d07d2fe0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109833745 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.4109833745
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2505582456
Short name T337
Test name
Test status
Simulation time 92855977 ps
CPU time 4.41 seconds
Started Jul 10 06:02:39 PM PDT 24
Finished Jul 10 06:02:46 PM PDT 24
Peak memory 211372 kb
Host smart-f22d752b-eb51-46bc-a45e-3053eaefc726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505582456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2505582456
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2818959264
Short name T226
Test name
Test status
Simulation time 14373301523 ps
CPU time 167.19 seconds
Started Jul 10 06:02:36 PM PDT 24
Finished Jul 10 06:05:24 PM PDT 24
Peak memory 238248 kb
Host smart-fedef113-01b0-4847-8d14-8134269b082f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818959264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2818959264
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2893521270
Short name T327
Test name
Test status
Simulation time 1568259200 ps
CPU time 19.07 seconds
Started Jul 10 06:02:37 PM PDT 24
Finished Jul 10 06:02:57 PM PDT 24
Peak memory 212040 kb
Host smart-34698932-4860-4491-a8f1-d32e35a91cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893521270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2893521270
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.764248184
Short name T148
Test name
Test status
Simulation time 2142993558 ps
CPU time 17.43 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:03:03 PM PDT 24
Peak memory 211372 kb
Host smart-32702b62-e4d1-4e9a-9ab7-5122f62f2e83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764248184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.764248184
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1237105172
Short name T230
Test name
Test status
Simulation time 185305860 ps
CPU time 10.65 seconds
Started Jul 10 06:02:37 PM PDT 24
Finished Jul 10 06:02:50 PM PDT 24
Peak memory 213488 kb
Host smart-1dd6d4a5-b66f-47bf-9eee-b77811476aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237105172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1237105172
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2162805883
Short name T118
Test name
Test status
Simulation time 15018500080 ps
CPU time 37.5 seconds
Started Jul 10 06:02:38 PM PDT 24
Finished Jul 10 06:03:18 PM PDT 24
Peak memory 214284 kb
Host smart-29248770-4456-4e02-a5fc-b4840c46f138
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162805883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2162805883
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3913300869
Short name T272
Test name
Test status
Simulation time 89217306 ps
CPU time 4.44 seconds
Started Jul 10 06:02:38 PM PDT 24
Finished Jul 10 06:02:44 PM PDT 24
Peak memory 211332 kb
Host smart-7aecf2f8-c1a0-4891-b004-d0ea42a651fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913300869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3913300869
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3983016609
Short name T273
Test name
Test status
Simulation time 48401263092 ps
CPU time 376.95 seconds
Started Jul 10 06:02:38 PM PDT 24
Finished Jul 10 06:08:57 PM PDT 24
Peak memory 233820 kb
Host smart-2b92808f-14c4-4d0f-8a9f-42ff9d30015a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983016609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3983016609
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1150237312
Short name T259
Test name
Test status
Simulation time 10128408189 ps
CPU time 27.93 seconds
Started Jul 10 06:02:38 PM PDT 24
Finished Jul 10 06:03:08 PM PDT 24
Peak memory 212272 kb
Host smart-ce5dff95-abe2-45ee-ac17-ff9901fa8400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150237312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1150237312
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2986724873
Short name T175
Test name
Test status
Simulation time 613271835 ps
CPU time 9.33 seconds
Started Jul 10 06:02:36 PM PDT 24
Finished Jul 10 06:02:46 PM PDT 24
Peak memory 211400 kb
Host smart-dfd9c63c-e0ec-41c5-9133-e2f89cdf0a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986724873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2986724873
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.943654924
Short name T77
Test name
Test status
Simulation time 743422889 ps
CPU time 10.39 seconds
Started Jul 10 06:02:37 PM PDT 24
Finished Jul 10 06:02:49 PM PDT 24
Peak memory 213500 kb
Host smart-a93af1ad-0c9c-4d8a-8f97-7899e90e824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943654924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.943654924
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.357574920
Short name T206
Test name
Test status
Simulation time 1587813803 ps
CPU time 18.3 seconds
Started Jul 10 06:02:38 PM PDT 24
Finished Jul 10 06:02:58 PM PDT 24
Peak memory 212060 kb
Host smart-2f583ba3-326d-4188-8bab-24cabbae2334
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357574920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.357574920
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.289359266
Short name T329
Test name
Test status
Simulation time 4993231969 ps
CPU time 11.96 seconds
Started Jul 10 06:02:41 PM PDT 24
Finished Jul 10 06:02:54 PM PDT 24
Peak memory 211464 kb
Host smart-31d6a2c7-add7-48e7-9fe9-b0ede88a249a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289359266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.289359266
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3828122314
Short name T162
Test name
Test status
Simulation time 92244258584 ps
CPU time 236.65 seconds
Started Jul 10 06:02:36 PM PDT 24
Finished Jul 10 06:06:33 PM PDT 24
Peak memory 236448 kb
Host smart-886a175e-c7da-4d55-903b-7f29d727af63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828122314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3828122314
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.511978740
Short name T342
Test name
Test status
Simulation time 2784267791 ps
CPU time 21.39 seconds
Started Jul 10 06:02:36 PM PDT 24
Finished Jul 10 06:02:58 PM PDT 24
Peak memory 211936 kb
Host smart-223d51cd-a521-4bcf-9fe4-279a3769144f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511978740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.511978740
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3204688933
Short name T247
Test name
Test status
Simulation time 190975502 ps
CPU time 5.6 seconds
Started Jul 10 06:02:36 PM PDT 24
Finished Jul 10 06:02:43 PM PDT 24
Peak memory 211440 kb
Host smart-d198c992-ce3c-40ff-8061-8a76cb396f57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204688933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3204688933
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3259497313
Short name T314
Test name
Test status
Simulation time 3979189879 ps
CPU time 24.04 seconds
Started Jul 10 06:02:37 PM PDT 24
Finished Jul 10 06:03:02 PM PDT 24
Peak memory 213420 kb
Host smart-93c6890f-5e3c-4427-8a8b-a77526d02fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259497313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3259497313
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3202444943
Short name T10
Test name
Test status
Simulation time 24918966228 ps
CPU time 18.56 seconds
Started Jul 10 06:02:36 PM PDT 24
Finished Jul 10 06:02:56 PM PDT 24
Peak memory 211468 kb
Host smart-31c3cd3a-3ea3-4a5d-8a6f-7364a24ccb1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202444943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3202444943
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3330302501
Short name T167
Test name
Test status
Simulation time 1026460373 ps
CPU time 10.71 seconds
Started Jul 10 06:02:47 PM PDT 24
Finished Jul 10 06:03:00 PM PDT 24
Peak memory 211264 kb
Host smart-c9777b8b-8845-404c-bdca-12e52e3f62a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330302501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3330302501
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3806217658
Short name T243
Test name
Test status
Simulation time 4341660367 ps
CPU time 94.85 seconds
Started Jul 10 06:02:39 PM PDT 24
Finished Jul 10 06:04:16 PM PDT 24
Peak memory 227700 kb
Host smart-d303370e-0211-4714-a27a-f7439e2ff974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806217658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3806217658
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.7701965
Short name T359
Test name
Test status
Simulation time 7471822519 ps
CPU time 31.36 seconds
Started Jul 10 06:02:40 PM PDT 24
Finished Jul 10 06:03:13 PM PDT 24
Peak memory 212652 kb
Host smart-ec1cc270-136b-449d-9db8-fe7bae14ce84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7701965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.7701965
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2275612123
Short name T255
Test name
Test status
Simulation time 691710997 ps
CPU time 9.57 seconds
Started Jul 10 06:02:41 PM PDT 24
Finished Jul 10 06:02:52 PM PDT 24
Peak memory 211416 kb
Host smart-cdd32533-1025-41eb-8634-96ed9bde5a11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275612123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2275612123
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2271150394
Short name T338
Test name
Test status
Simulation time 4812727309 ps
CPU time 24.24 seconds
Started Jul 10 06:02:35 PM PDT 24
Finished Jul 10 06:03:00 PM PDT 24
Peak memory 212820 kb
Host smart-f6692c93-3528-4e13-b392-93471416a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271150394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2271150394
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2583870113
Short name T344
Test name
Test status
Simulation time 828981641 ps
CPU time 46.23 seconds
Started Jul 10 06:02:38 PM PDT 24
Finished Jul 10 06:03:26 PM PDT 24
Peak memory 216304 kb
Host smart-1b89478b-2974-41e9-9bde-4080c6dfbeda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583870113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2583870113
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1122814510
Short name T330
Test name
Test status
Simulation time 5410093323 ps
CPU time 12.23 seconds
Started Jul 10 06:02:45 PM PDT 24
Finished Jul 10 06:02:59 PM PDT 24
Peak memory 211612 kb
Host smart-2f58858c-4a29-4369-a958-7efe9cb29a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122814510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1122814510
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1069332220
Short name T124
Test name
Test status
Simulation time 118264733400 ps
CPU time 157.38 seconds
Started Jul 10 06:02:47 PM PDT 24
Finished Jul 10 06:05:26 PM PDT 24
Peak memory 213660 kb
Host smart-69c697da-48f4-4502-b43d-b6156e8e8c9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069332220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1069332220
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.174579275
Short name T339
Test name
Test status
Simulation time 9613806233 ps
CPU time 24.02 seconds
Started Jul 10 06:02:44 PM PDT 24
Finished Jul 10 06:03:10 PM PDT 24
Peak memory 212312 kb
Host smart-898901f5-b1f8-4b42-8869-9d3e90fa6a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174579275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.174579275
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4041285348
Short name T355
Test name
Test status
Simulation time 1564140058 ps
CPU time 12.95 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:02:58 PM PDT 24
Peak memory 211416 kb
Host smart-a0e03af7-2e58-46cd-8ac6-11c68e4dca72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4041285348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4041285348
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.522661157
Short name T219
Test name
Test status
Simulation time 192055688 ps
CPU time 10.24 seconds
Started Jul 10 06:02:42 PM PDT 24
Finished Jul 10 06:02:54 PM PDT 24
Peak memory 214164 kb
Host smart-14221543-1a0e-4399-8571-17bba9f36b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522661157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.522661157
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1247760529
Short name T292
Test name
Test status
Simulation time 3307957487 ps
CPU time 27.56 seconds
Started Jul 10 06:02:45 PM PDT 24
Finished Jul 10 06:03:15 PM PDT 24
Peak memory 212692 kb
Host smart-a3eb6d60-3ba4-40f3-bafa-e61d24ea796c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247760529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1247760529
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1487021182
Short name T187
Test name
Test status
Simulation time 8137857404 ps
CPU time 15.72 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:03:01 PM PDT 24
Peak memory 211444 kb
Host smart-352eddad-d9d0-4c0f-b557-8e423d986466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487021182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1487021182
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.320499225
Short name T236
Test name
Test status
Simulation time 3070870843 ps
CPU time 113.69 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:04:56 PM PDT 24
Peak memory 233804 kb
Host smart-eb859c3a-5e0b-4b59-9545-0073bc53b390
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320499225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.320499225
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.586262534
Short name T222
Test name
Test status
Simulation time 667616743 ps
CPU time 9.32 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:02:55 PM PDT 24
Peak memory 212552 kb
Host smart-ffefac7f-2426-48a2-b9f1-d9364986eb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586262534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.586262534
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2974502765
Short name T151
Test name
Test status
Simulation time 4313152935 ps
CPU time 11.73 seconds
Started Jul 10 06:02:42 PM PDT 24
Finished Jul 10 06:02:55 PM PDT 24
Peak memory 211476 kb
Host smart-280f7852-12b6-4e6c-9562-e1d94bc261c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974502765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2974502765
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2257113908
Short name T349
Test name
Test status
Simulation time 13840790765 ps
CPU time 33.79 seconds
Started Jul 10 06:02:45 PM PDT 24
Finished Jul 10 06:03:21 PM PDT 24
Peak memory 214408 kb
Host smart-8ea35a78-1dcf-480a-beca-accadb1f9d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257113908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2257113908
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1608403976
Short name T253
Test name
Test status
Simulation time 407773022 ps
CPU time 5.58 seconds
Started Jul 10 06:02:47 PM PDT 24
Finished Jul 10 06:02:55 PM PDT 24
Peak memory 211396 kb
Host smart-f86f9294-3ae3-47f6-8138-9cccce494341
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608403976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1608403976
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3645194906
Short name T350
Test name
Test status
Simulation time 129069372 ps
CPU time 5.11 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:02:50 PM PDT 24
Peak memory 211356 kb
Host smart-61679caf-0692-40a7-9b21-0c763c1b1411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645194906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3645194906
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.357385399
Short name T3
Test name
Test status
Simulation time 13632127029 ps
CPU time 73.12 seconds
Started Jul 10 06:02:45 PM PDT 24
Finished Jul 10 06:04:01 PM PDT 24
Peak memory 237440 kb
Host smart-83205b02-60a0-4919-a73f-dc514c50621d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357385399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.357385399
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3155753554
Short name T300
Test name
Test status
Simulation time 4148896023 ps
CPU time 14.28 seconds
Started Jul 10 06:02:44 PM PDT 24
Finished Jul 10 06:03:01 PM PDT 24
Peak memory 212060 kb
Host smart-b6d7b669-cbbe-49f6-9e26-a15139dbf0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155753554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3155753554
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3631621999
Short name T171
Test name
Test status
Simulation time 1922257735 ps
CPU time 8.03 seconds
Started Jul 10 06:02:47 PM PDT 24
Finished Jul 10 06:02:57 PM PDT 24
Peak memory 211312 kb
Host smart-93d1cf15-8d6a-499d-8563-b4c96315147b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631621999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3631621999
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3756898165
Short name T289
Test name
Test status
Simulation time 1914464472 ps
CPU time 15.98 seconds
Started Jul 10 06:02:42 PM PDT 24
Finished Jul 10 06:03:00 PM PDT 24
Peak memory 213164 kb
Host smart-0bd9ea5f-d3de-4e98-931b-8d5c4793497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756898165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3756898165
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.368490143
Short name T127
Test name
Test status
Simulation time 1252018557 ps
CPU time 15.62 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:03:00 PM PDT 24
Peak memory 216352 kb
Host smart-ee13e6ab-4f98-4f31-b12b-6722ff5f104e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368490143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.368490143
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.945936894
Short name T293
Test name
Test status
Simulation time 2949021692 ps
CPU time 8.93 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:02:55 PM PDT 24
Peak memory 211416 kb
Host smart-4c223655-ae6f-448e-8a64-a6fb6dba902a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945936894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.945936894
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1589008243
Short name T345
Test name
Test status
Simulation time 2639865289 ps
CPU time 14.16 seconds
Started Jul 10 06:02:42 PM PDT 24
Finished Jul 10 06:02:58 PM PDT 24
Peak memory 212200 kb
Host smart-3b27feea-518d-455d-afcd-52c0a8d2abd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589008243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1589008243
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1718069205
Short name T360
Test name
Test status
Simulation time 374807712 ps
CPU time 5.72 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:02:51 PM PDT 24
Peak memory 211404 kb
Host smart-549a95af-eacb-40c0-9888-55f358ead86e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1718069205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1718069205
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3481942923
Short name T267
Test name
Test status
Simulation time 1018345358 ps
CPU time 10.31 seconds
Started Jul 10 06:02:47 PM PDT 24
Finished Jul 10 06:02:59 PM PDT 24
Peak memory 213596 kb
Host smart-9bb1d639-7e85-4b70-adc0-89c5cf106e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481942923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3481942923
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.101294433
Short name T353
Test name
Test status
Simulation time 2115020840 ps
CPU time 19.6 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:03:22 PM PDT 24
Peak memory 212132 kb
Host smart-39c11773-1cfe-4298-9be9-3630f99bd5ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101294433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.101294433
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.58987100
Short name T221
Test name
Test status
Simulation time 5112636748 ps
CPU time 12.11 seconds
Started Jul 10 06:02:45 PM PDT 24
Finished Jul 10 06:03:00 PM PDT 24
Peak memory 211412 kb
Host smart-8b630cae-871b-45e0-a8cb-aa2891b0c37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58987100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.58987100
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1903991067
Short name T199
Test name
Test status
Simulation time 60534746363 ps
CPU time 310.49 seconds
Started Jul 10 06:02:47 PM PDT 24
Finished Jul 10 06:07:59 PM PDT 24
Peak memory 234852 kb
Host smart-2a41cbe5-6b31-4bec-9d8f-17a0d4b49f72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903991067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1903991067
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2686598302
Short name T144
Test name
Test status
Simulation time 4423471311 ps
CPU time 19.94 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:03:22 PM PDT 24
Peak memory 212180 kb
Host smart-e4201690-728a-4e51-a8fd-44fcd6e2e604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686598302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2686598302
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3854436427
Short name T16
Test name
Test status
Simulation time 113506144 ps
CPU time 5.34 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:02:50 PM PDT 24
Peak memory 211436 kb
Host smart-a946204b-846e-48a7-bdea-99199e7e436b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854436427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3854436427
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2545621383
Short name T149
Test name
Test status
Simulation time 757467884 ps
CPU time 10.31 seconds
Started Jul 10 06:02:46 PM PDT 24
Finished Jul 10 06:02:58 PM PDT 24
Peak memory 213940 kb
Host smart-a4b8e3a4-47c6-4f3f-8283-03c8d9106c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545621383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2545621383
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2123248494
Short name T126
Test name
Test status
Simulation time 5094915330 ps
CPU time 26.98 seconds
Started Jul 10 06:02:41 PM PDT 24
Finished Jul 10 06:03:10 PM PDT 24
Peak memory 213640 kb
Host smart-7deda516-a620-4f3f-afa8-6b0e6a8e528a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123248494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2123248494
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2550859794
Short name T210
Test name
Test status
Simulation time 6336549102 ps
CPU time 14.68 seconds
Started Jul 10 06:02:14 PM PDT 24
Finished Jul 10 06:02:30 PM PDT 24
Peak memory 211416 kb
Host smart-6d8d4f98-0ee3-4c37-82b1-74bd18716b04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550859794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2550859794
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1719167768
Short name T41
Test name
Test status
Simulation time 67118276741 ps
CPU time 175.15 seconds
Started Jul 10 06:02:15 PM PDT 24
Finished Jul 10 06:05:11 PM PDT 24
Peak memory 228372 kb
Host smart-ae6b38a6-6d46-469e-a54a-7edb1e709ee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719167768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1719167768
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3978148316
Short name T31
Test name
Test status
Simulation time 5604819452 ps
CPU time 18.89 seconds
Started Jul 10 06:02:15 PM PDT 24
Finished Jul 10 06:02:35 PM PDT 24
Peak memory 212252 kb
Host smart-d1c0067a-5fbc-46d1-a0f6-45babb75def9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978148316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3978148316
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1342539255
Short name T5
Test name
Test status
Simulation time 8423628922 ps
CPU time 16.82 seconds
Started Jul 10 06:02:14 PM PDT 24
Finished Jul 10 06:02:32 PM PDT 24
Peak memory 211472 kb
Host smart-d71369c9-f220-4a26-aaa1-bd81cd879870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342539255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1342539255
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1135058034
Short name T21
Test name
Test status
Simulation time 221516488 ps
CPU time 53.83 seconds
Started Jul 10 06:02:12 PM PDT 24
Finished Jul 10 06:03:07 PM PDT 24
Peak memory 233784 kb
Host smart-9bc7a16e-5e0b-4d88-a4ec-24f3ec8a4407
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135058034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1135058034
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.531016242
Short name T32
Test name
Test status
Simulation time 5223855575 ps
CPU time 21.78 seconds
Started Jul 10 06:02:11 PM PDT 24
Finished Jul 10 06:02:34 PM PDT 24
Peak memory 214452 kb
Host smart-d47ae09c-0a08-44bc-beeb-ea5b4bc5a254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531016242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.531016242
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.737979706
Short name T152
Test name
Test status
Simulation time 13403707029 ps
CPU time 60.04 seconds
Started Jul 10 06:02:14 PM PDT 24
Finished Jul 10 06:03:15 PM PDT 24
Peak memory 213704 kb
Host smart-77baa9b7-d7b5-422b-b644-256529246106
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737979706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.737979706
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1241196606
Short name T220
Test name
Test status
Simulation time 25945431467 ps
CPU time 13.67 seconds
Started Jul 10 06:02:44 PM PDT 24
Finished Jul 10 06:03:00 PM PDT 24
Peak memory 211612 kb
Host smart-04b57f40-3857-463b-bdb9-f8483284f190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241196606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1241196606
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.522267777
Short name T295
Test name
Test status
Simulation time 14217424053 ps
CPU time 226.5 seconds
Started Jul 10 06:02:41 PM PDT 24
Finished Jul 10 06:06:29 PM PDT 24
Peak memory 232764 kb
Host smart-7c3794a7-6bbe-41d6-9be2-c2d6dc0b4f5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522267777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.522267777
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2078692392
Short name T158
Test name
Test status
Simulation time 2913971389 ps
CPU time 17.74 seconds
Started Jul 10 06:02:45 PM PDT 24
Finished Jul 10 06:03:06 PM PDT 24
Peak memory 212068 kb
Host smart-6a354f3c-234f-4ecc-84d3-94af6dcadba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078692392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2078692392
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.771334098
Short name T279
Test name
Test status
Simulation time 3600805304 ps
CPU time 14.91 seconds
Started Jul 10 06:02:47 PM PDT 24
Finished Jul 10 06:03:04 PM PDT 24
Peak memory 211448 kb
Host smart-668a80a3-1d55-44d4-a521-9e19985354d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=771334098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.771334098
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1973450002
Short name T227
Test name
Test status
Simulation time 2476847703 ps
CPU time 27.57 seconds
Started Jul 10 06:02:46 PM PDT 24
Finished Jul 10 06:03:16 PM PDT 24
Peak memory 213568 kb
Host smart-67ca78d2-a743-426b-b512-39c89d5d709a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973450002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1973450002
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.587124
Short name T256
Test name
Test status
Simulation time 370105052 ps
CPU time 19.73 seconds
Started Jul 10 06:02:45 PM PDT 24
Finished Jul 10 06:03:07 PM PDT 24
Peak memory 214612 kb
Host smart-ac2d3698-1bc4-40fb-b17c-ebc2e3c51d70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.rom_ctrl_stress_all.587124
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.716646803
Short name T271
Test name
Test status
Simulation time 431454481 ps
CPU time 7 seconds
Started Jul 10 06:02:44 PM PDT 24
Finished Jul 10 06:02:54 PM PDT 24
Peak memory 211372 kb
Host smart-6eea5160-9d1e-455c-9210-c9bc335642cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716646803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.716646803
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3972865824
Short name T290
Test name
Test status
Simulation time 25178645512 ps
CPU time 289.48 seconds
Started Jul 10 06:02:44 PM PDT 24
Finished Jul 10 06:07:35 PM PDT 24
Peak memory 213604 kb
Host smart-e1b162b7-723f-4e30-8bd2-aa45a6035094
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972865824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3972865824
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2512785188
Short name T276
Test name
Test status
Simulation time 175043703 ps
CPU time 9.31 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:03:11 PM PDT 24
Peak memory 211808 kb
Host smart-048cc32a-7931-415d-88b6-3536f819022f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512785188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2512785188
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3455247204
Short name T189
Test name
Test status
Simulation time 193809898 ps
CPU time 5.4 seconds
Started Jul 10 06:02:47 PM PDT 24
Finished Jul 10 06:02:55 PM PDT 24
Peak memory 211388 kb
Host smart-5d40f668-9957-4e47-a4d3-c11edc44c7ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455247204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3455247204
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2857023085
Short name T283
Test name
Test status
Simulation time 792958900 ps
CPU time 10.59 seconds
Started Jul 10 06:02:46 PM PDT 24
Finished Jul 10 06:02:59 PM PDT 24
Peak memory 213788 kb
Host smart-3c865711-5501-4f54-b29a-5b676e2c9074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857023085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2857023085
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.4230205751
Short name T140
Test name
Test status
Simulation time 10440294622 ps
CPU time 33.88 seconds
Started Jul 10 06:02:46 PM PDT 24
Finished Jul 10 06:03:22 PM PDT 24
Peak memory 216896 kb
Host smart-5d0a0bcd-9911-4500-b30d-d0b6ed7b9519
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230205751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.4230205751
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3983489341
Short name T252
Test name
Test status
Simulation time 8579014483 ps
CPU time 16.26 seconds
Started Jul 10 06:02:51 PM PDT 24
Finished Jul 10 06:03:08 PM PDT 24
Peak memory 211428 kb
Host smart-dc8076ae-0b6d-4f68-9bf0-ffde0e49d64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983489341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3983489341
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3683447859
Short name T318
Test name
Test status
Simulation time 80039758513 ps
CPU time 428.46 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:10:11 PM PDT 24
Peak memory 237884 kb
Host smart-33baff76-2f2d-4271-b133-ee057432671a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683447859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3683447859
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2791480095
Short name T160
Test name
Test status
Simulation time 270176106 ps
CPU time 7.49 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:02:53 PM PDT 24
Peak memory 211432 kb
Host smart-00c3eadc-b3cd-48aa-ada7-a4e7c33d1e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791480095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2791480095
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4050170196
Short name T116
Test name
Test status
Simulation time 1806941736 ps
CPU time 24.48 seconds
Started Jul 10 06:02:44 PM PDT 24
Finished Jul 10 06:03:11 PM PDT 24
Peak memory 213556 kb
Host smart-99131098-95d9-4384-a214-518e3d24e0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050170196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4050170196
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3338725150
Short name T301
Test name
Test status
Simulation time 12923054489 ps
CPU time 30.91 seconds
Started Jul 10 06:02:43 PM PDT 24
Finished Jul 10 06:03:17 PM PDT 24
Peak memory 215044 kb
Host smart-7eb2218f-7f82-4917-833d-71570ad2c9ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338725150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3338725150
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2363765529
Short name T18
Test name
Test status
Simulation time 12023325618 ps
CPU time 240.84 seconds
Started Jul 10 06:02:51 PM PDT 24
Finished Jul 10 06:06:53 PM PDT 24
Peak memory 225184 kb
Host smart-f754da38-1081-4142-a163-55dbfa679704
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363765529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2363765529
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2239742341
Short name T25
Test name
Test status
Simulation time 170546594 ps
CPU time 9.49 seconds
Started Jul 10 06:02:54 PM PDT 24
Finished Jul 10 06:03:05 PM PDT 24
Peak memory 212220 kb
Host smart-00d6d426-b0b0-44eb-adec-930eba27cb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239742341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2239742341
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3546448343
Short name T317
Test name
Test status
Simulation time 6699750106 ps
CPU time 15.52 seconds
Started Jul 10 06:02:53 PM PDT 24
Finished Jul 10 06:03:09 PM PDT 24
Peak memory 211448 kb
Host smart-7cf76f73-0834-486a-a313-cd9689efcbc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546448343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3546448343
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.4095423855
Short name T245
Test name
Test status
Simulation time 11913290380 ps
CPU time 30.34 seconds
Started Jul 10 06:02:51 PM PDT 24
Finished Jul 10 06:03:22 PM PDT 24
Peak memory 213940 kb
Host smart-c8014c1b-93e7-4b72-9688-1b3922e8b7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095423855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.4095423855
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4054575281
Short name T181
Test name
Test status
Simulation time 19089892260 ps
CPU time 53.94 seconds
Started Jul 10 06:02:52 PM PDT 24
Finished Jul 10 06:03:47 PM PDT 24
Peak memory 219420 kb
Host smart-32465e24-8819-4c6d-8ed9-043a85540486
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054575281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4054575281
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2226790396
Short name T50
Test name
Test status
Simulation time 295470098279 ps
CPU time 9356.4 seconds
Started Jul 10 06:02:52 PM PDT 24
Finished Jul 10 08:38:51 PM PDT 24
Peak memory 235344 kb
Host smart-c01ee394-e7f1-463d-8a92-b90dc82a48e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226790396 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2226790396
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.912435802
Short name T208
Test name
Test status
Simulation time 4494729074 ps
CPU time 13.04 seconds
Started Jul 10 06:02:54 PM PDT 24
Finished Jul 10 06:03:08 PM PDT 24
Peak memory 211432 kb
Host smart-d9d29fb8-f68e-4013-8a00-26b1ab1f2db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912435802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.912435802
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2780052507
Short name T234
Test name
Test status
Simulation time 1084687025 ps
CPU time 70.25 seconds
Started Jul 10 06:02:59 PM PDT 24
Finished Jul 10 06:04:10 PM PDT 24
Peak memory 233768 kb
Host smart-537d053b-4658-48d9-a4a7-b783bd1dc662
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780052507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2780052507
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.727141611
Short name T134
Test name
Test status
Simulation time 5038126283 ps
CPU time 24.6 seconds
Started Jul 10 06:02:54 PM PDT 24
Finished Jul 10 06:03:19 PM PDT 24
Peak memory 212276 kb
Host smart-a2d20afa-2698-46cd-a06e-e8f0346c72d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727141611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.727141611
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3260442021
Short name T228
Test name
Test status
Simulation time 98039014 ps
CPU time 5.48 seconds
Started Jul 10 06:02:52 PM PDT 24
Finished Jul 10 06:02:59 PM PDT 24
Peak memory 211420 kb
Host smart-39ec734e-9f80-4c2a-8a46-07949e707800
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260442021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3260442021
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2687259404
Short name T257
Test name
Test status
Simulation time 13885492609 ps
CPU time 31.46 seconds
Started Jul 10 06:02:56 PM PDT 24
Finished Jul 10 06:03:29 PM PDT 24
Peak memory 214232 kb
Host smart-e49f8ee6-f268-4a80-9e14-40b1c9299145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687259404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2687259404
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3013232894
Short name T333
Test name
Test status
Simulation time 6831329587 ps
CPU time 37.74 seconds
Started Jul 10 06:02:55 PM PDT 24
Finished Jul 10 06:03:33 PM PDT 24
Peak memory 216172 kb
Host smart-f1bdaaee-9822-42ea-9be2-3cb27e2e57c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013232894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3013232894
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3269997576
Short name T121
Test name
Test status
Simulation time 89119351 ps
CPU time 4.46 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:03:07 PM PDT 24
Peak memory 211372 kb
Host smart-50fa5ea7-72fb-435c-968f-c3dd07578a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269997576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3269997576
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3349456981
Short name T284
Test name
Test status
Simulation time 17977695260 ps
CPU time 255.64 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:07:18 PM PDT 24
Peak memory 212604 kb
Host smart-01542a33-d3b2-46b1-9aca-b74f1ab68985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349456981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3349456981
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.481513923
Short name T298
Test name
Test status
Simulation time 19728774607 ps
CPU time 28.92 seconds
Started Jul 10 06:03:01 PM PDT 24
Finished Jul 10 06:03:32 PM PDT 24
Peak memory 212224 kb
Host smart-9f3a2fd0-af29-4ea8-a6ee-beb2d92075e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481513923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.481513923
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2108656967
Short name T361
Test name
Test status
Simulation time 3003343209 ps
CPU time 13.63 seconds
Started Jul 10 06:03:02 PM PDT 24
Finished Jul 10 06:03:18 PM PDT 24
Peak memory 211520 kb
Host smart-0fdbdec2-53dd-4a4e-a6c8-ce7b44ff8b40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108656967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2108656967
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.523292335
Short name T310
Test name
Test status
Simulation time 15249890610 ps
CPU time 34.88 seconds
Started Jul 10 06:02:54 PM PDT 24
Finished Jul 10 06:03:30 PM PDT 24
Peak memory 214568 kb
Host smart-c94def48-7873-491d-a915-8bcd621a42dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523292335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.523292335
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2944972001
Short name T174
Test name
Test status
Simulation time 18679754004 ps
CPU time 37.27 seconds
Started Jul 10 06:03:06 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 215036 kb
Host smart-98d970e3-7174-4d3f-91a7-683e74a101db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944972001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2944972001
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4073964954
Short name T61
Test name
Test status
Simulation time 819305995 ps
CPU time 7.88 seconds
Started Jul 10 06:03:32 PM PDT 24
Finished Jul 10 06:03:41 PM PDT 24
Peak memory 211272 kb
Host smart-32c40b38-b8c4-4810-960d-a49eb8227f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073964954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4073964954
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1774892783
Short name T44
Test name
Test status
Simulation time 175071029186 ps
CPU time 251.41 seconds
Started Jul 10 06:02:59 PM PDT 24
Finished Jul 10 06:07:12 PM PDT 24
Peak memory 225740 kb
Host smart-26991bc1-207a-425b-a8bb-ef58921a688d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774892783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1774892783
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3541221306
Short name T123
Test name
Test status
Simulation time 61435932673 ps
CPU time 33.24 seconds
Started Jul 10 06:03:04 PM PDT 24
Finished Jul 10 06:03:38 PM PDT 24
Peak memory 212204 kb
Host smart-3627eacd-a0b9-4441-902f-fbe42aedd300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541221306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3541221306
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2663059820
Short name T139
Test name
Test status
Simulation time 2502280398 ps
CPU time 12.62 seconds
Started Jul 10 06:03:02 PM PDT 24
Finished Jul 10 06:03:16 PM PDT 24
Peak memory 211520 kb
Host smart-f7268e19-408e-47dc-ba2f-98a96cd6576f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663059820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2663059820
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1061681760
Short name T323
Test name
Test status
Simulation time 188323778 ps
CPU time 10.06 seconds
Started Jul 10 06:03:01 PM PDT 24
Finished Jul 10 06:03:13 PM PDT 24
Peak memory 213056 kb
Host smart-31d23b17-4156-433e-a3fa-150cbdc25b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061681760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1061681760
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3155400205
Short name T347
Test name
Test status
Simulation time 756919058 ps
CPU time 6.9 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:03:09 PM PDT 24
Peak memory 211256 kb
Host smart-2e74e9e1-4e0c-4e35-8879-f31a94845f50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155400205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3155400205
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2167882616
Short name T195
Test name
Test status
Simulation time 1678042305 ps
CPU time 13.52 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:03:16 PM PDT 24
Peak memory 211356 kb
Host smart-1847d084-a49a-4c7e-9532-3a4db45b3050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167882616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2167882616
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.130166276
Short name T176
Test name
Test status
Simulation time 102767019346 ps
CPU time 186.34 seconds
Started Jul 10 06:03:05 PM PDT 24
Finished Jul 10 06:06:14 PM PDT 24
Peak memory 233788 kb
Host smart-fa49d94a-057f-4a68-9f5c-e177861b047d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130166276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.130166276
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1036685932
Short name T262
Test name
Test status
Simulation time 380543784 ps
CPU time 9.55 seconds
Started Jul 10 06:03:01 PM PDT 24
Finished Jul 10 06:03:13 PM PDT 24
Peak memory 212488 kb
Host smart-8677ff47-3778-4e90-8cef-75140643c7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036685932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1036685932
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.395412224
Short name T285
Test name
Test status
Simulation time 2370989353 ps
CPU time 24.27 seconds
Started Jul 10 06:03:01 PM PDT 24
Finished Jul 10 06:03:27 PM PDT 24
Peak memory 213772 kb
Host smart-c7203cad-d6f2-4776-b2ae-52bc8a3dc099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395412224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.395412224
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4169816687
Short name T306
Test name
Test status
Simulation time 10927845250 ps
CPU time 19.68 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:03:22 PM PDT 24
Peak memory 214220 kb
Host smart-82a3bef0-576a-416d-bc48-a3c92e102bbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169816687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4169816687
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4131050567
Short name T309
Test name
Test status
Simulation time 2815303665 ps
CPU time 13.24 seconds
Started Jul 10 06:03:10 PM PDT 24
Finished Jul 10 06:03:24 PM PDT 24
Peak memory 211408 kb
Host smart-a03a21c4-ba5c-4e23-819f-e3e13088c124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131050567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4131050567
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3305283196
Short name T37
Test name
Test status
Simulation time 174066439404 ps
CPU time 414.2 seconds
Started Jul 10 06:03:06 PM PDT 24
Finished Jul 10 06:10:02 PM PDT 24
Peak memory 212668 kb
Host smart-228a8d84-ca82-4e68-9d98-49cf3d3729c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305283196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3305283196
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2078057462
Short name T261
Test name
Test status
Simulation time 2393211620 ps
CPU time 24.36 seconds
Started Jul 10 06:03:07 PM PDT 24
Finished Jul 10 06:03:33 PM PDT 24
Peak memory 211460 kb
Host smart-a663ac9b-fc22-4cb4-840f-b1c10ae4d6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078057462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2078057462
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.941543780
Short name T164
Test name
Test status
Simulation time 1974381745 ps
CPU time 16.19 seconds
Started Jul 10 06:03:01 PM PDT 24
Finished Jul 10 06:03:19 PM PDT 24
Peak memory 211412 kb
Host smart-9745fde0-3519-4d43-b89c-b55a031c3ec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=941543780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.941543780
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3177401877
Short name T254
Test name
Test status
Simulation time 1735344191 ps
CPU time 25.89 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:03:28 PM PDT 24
Peak memory 213728 kb
Host smart-0f22464b-6cde-45f1-9974-1491e77f15a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177401877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3177401877
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.423075197
Short name T114
Test name
Test status
Simulation time 333113942 ps
CPU time 6.19 seconds
Started Jul 10 06:03:00 PM PDT 24
Finished Jul 10 06:03:08 PM PDT 24
Peak memory 211408 kb
Host smart-422ddf09-49b1-4f5c-937f-102d5d6cc036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423075197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.423075197
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3074807853
Short name T13
Test name
Test status
Simulation time 262602845118 ps
CPU time 2490.68 seconds
Started Jul 10 06:03:05 PM PDT 24
Finished Jul 10 06:44:37 PM PDT 24
Peak memory 236296 kb
Host smart-31efaf25-ed80-4bc3-9b0a-90903c94d0a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074807853 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3074807853
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3975476053
Short name T275
Test name
Test status
Simulation time 85722816 ps
CPU time 4.45 seconds
Started Jul 10 06:03:04 PM PDT 24
Finished Jul 10 06:03:10 PM PDT 24
Peak memory 211368 kb
Host smart-897a12af-5493-471d-b305-1626fd8541e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975476053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3975476053
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.851943276
Short name T183
Test name
Test status
Simulation time 44389842041 ps
CPU time 162.16 seconds
Started Jul 10 06:03:05 PM PDT 24
Finished Jul 10 06:05:48 PM PDT 24
Peak memory 213660 kb
Host smart-370b4ae8-6fb7-43e7-a9df-b690161f80c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851943276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.851943276
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3158713537
Short name T157
Test name
Test status
Simulation time 15333165794 ps
CPU time 16.36 seconds
Started Jul 10 06:03:06 PM PDT 24
Finished Jul 10 06:03:24 PM PDT 24
Peak memory 212428 kb
Host smart-c7fa2e10-a058-4dff-8302-aa32ecf39c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158713537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3158713537
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2784492439
Short name T165
Test name
Test status
Simulation time 100190468 ps
CPU time 5.76 seconds
Started Jul 10 06:03:05 PM PDT 24
Finished Jul 10 06:03:13 PM PDT 24
Peak memory 211404 kb
Host smart-b819292a-239c-4ebc-8d1b-e69b6650e302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784492439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2784492439
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2731528591
Short name T188
Test name
Test status
Simulation time 2600307616 ps
CPU time 24.64 seconds
Started Jul 10 06:03:06 PM PDT 24
Finished Jul 10 06:03:32 PM PDT 24
Peak memory 213568 kb
Host smart-fa5a74b1-2219-42ed-be9e-f33330d28eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731528591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2731528591
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.756770775
Short name T282
Test name
Test status
Simulation time 581466076 ps
CPU time 16.83 seconds
Started Jul 10 06:03:05 PM PDT 24
Finished Jul 10 06:03:24 PM PDT 24
Peak memory 215436 kb
Host smart-540e08e0-ee1d-4ef4-8d90-1ce8490efbc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756770775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.756770775
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3509446196
Short name T62
Test name
Test status
Simulation time 1186235265 ps
CPU time 11.37 seconds
Started Jul 10 06:02:12 PM PDT 24
Finished Jul 10 06:02:25 PM PDT 24
Peak memory 211352 kb
Host smart-f50e1929-c422-4af7-9c72-564ac6e626d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509446196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3509446196
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3250491264
Short name T312
Test name
Test status
Simulation time 59462969071 ps
CPU time 153.47 seconds
Started Jul 10 06:02:14 PM PDT 24
Finished Jul 10 06:04:48 PM PDT 24
Peak memory 228288 kb
Host smart-bf10a115-0c76-47c7-9e3d-2f2911b45df7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250491264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3250491264
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3467027954
Short name T39
Test name
Test status
Simulation time 343248900 ps
CPU time 9.66 seconds
Started Jul 10 06:02:15 PM PDT 24
Finished Jul 10 06:02:26 PM PDT 24
Peak memory 211404 kb
Host smart-aef1fab9-9a7e-45e8-ac65-5ce16fee3fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467027954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3467027954
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.262132737
Short name T182
Test name
Test status
Simulation time 2041859018 ps
CPU time 17.24 seconds
Started Jul 10 06:02:18 PM PDT 24
Finished Jul 10 06:02:36 PM PDT 24
Peak memory 211420 kb
Host smart-3d3eea1a-d1d0-4611-9a70-1f90543d60a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=262132737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.262132737
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1146067900
Short name T19
Test name
Test status
Simulation time 6006263820 ps
CPU time 106.94 seconds
Started Jul 10 06:02:11 PM PDT 24
Finished Jul 10 06:03:59 PM PDT 24
Peak memory 236212 kb
Host smart-aca7cd66-d582-4231-9b7a-b3c8e3fcf155
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146067900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1146067900
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4271013534
Short name T78
Test name
Test status
Simulation time 1951503780 ps
CPU time 13.85 seconds
Started Jul 10 06:02:14 PM PDT 24
Finished Jul 10 06:02:28 PM PDT 24
Peak memory 213780 kb
Host smart-95606314-4041-4448-9a4e-faa898dcfafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271013534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4271013534
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.603067616
Short name T304
Test name
Test status
Simulation time 12738528289 ps
CPU time 35.57 seconds
Started Jul 10 06:02:12 PM PDT 24
Finished Jul 10 06:02:49 PM PDT 24
Peak memory 214484 kb
Host smart-0501bf9c-3ed0-47d2-a7b6-e28d36b992e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603067616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.603067616
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.351082527
Short name T263
Test name
Test status
Simulation time 4619363230 ps
CPU time 11.68 seconds
Started Jul 10 06:03:07 PM PDT 24
Finished Jul 10 06:03:20 PM PDT 24
Peak memory 211412 kb
Host smart-95a57a82-cd79-4f90-962c-bf6df6de20b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351082527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.351082527
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.549355700
Short name T38
Test name
Test status
Simulation time 32322522054 ps
CPU time 232.3 seconds
Started Jul 10 06:03:05 PM PDT 24
Finished Jul 10 06:06:59 PM PDT 24
Peak memory 237392 kb
Host smart-63bc3944-0487-4fc1-89bb-3a1298d28b7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549355700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.549355700
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2972421332
Short name T258
Test name
Test status
Simulation time 5231794543 ps
CPU time 18.06 seconds
Started Jul 10 06:03:06 PM PDT 24
Finished Jul 10 06:03:26 PM PDT 24
Peak memory 212476 kb
Host smart-37086ced-6120-4ee9-ac6a-3ddcb83eca4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972421332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2972421332
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2054526251
Short name T135
Test name
Test status
Simulation time 1608950197 ps
CPU time 14.14 seconds
Started Jul 10 06:03:05 PM PDT 24
Finished Jul 10 06:03:20 PM PDT 24
Peak memory 211400 kb
Host smart-a6a70319-68f3-4b40-bfaf-cf04d5fd1148
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054526251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2054526251
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3720255997
Short name T117
Test name
Test status
Simulation time 19433884326 ps
CPU time 23.78 seconds
Started Jul 10 06:03:06 PM PDT 24
Finished Jul 10 06:03:31 PM PDT 24
Peak memory 211940 kb
Host smart-471ee155-041a-4789-9488-a6c7ed9f7217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720255997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3720255997
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2038171285
Short name T202
Test name
Test status
Simulation time 6136860634 ps
CPU time 67.78 seconds
Started Jul 10 06:03:10 PM PDT 24
Finished Jul 10 06:04:19 PM PDT 24
Peak memory 216984 kb
Host smart-c9569e33-e24e-4b04-bc1b-6165ebca8aed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038171285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2038171285
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4089043719
Short name T216
Test name
Test status
Simulation time 1538974511 ps
CPU time 12.96 seconds
Started Jul 10 06:03:11 PM PDT 24
Finished Jul 10 06:03:26 PM PDT 24
Peak memory 211332 kb
Host smart-1e1055fa-34a3-44f4-bf7b-3ee48cc376f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089043719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4089043719
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2958300603
Short name T305
Test name
Test status
Simulation time 26407528820 ps
CPU time 78.85 seconds
Started Jul 10 06:03:07 PM PDT 24
Finished Jul 10 06:04:27 PM PDT 24
Peak memory 236892 kb
Host smart-17186eac-4b85-4782-9f1b-0e7a6ccfd6f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958300603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2958300603
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.91807910
Short name T248
Test name
Test status
Simulation time 8877006243 ps
CPU time 23.57 seconds
Started Jul 10 06:03:05 PM PDT 24
Finished Jul 10 06:03:30 PM PDT 24
Peak memory 211484 kb
Host smart-69ea8149-591d-45a7-9ccf-7efdc0fb537f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91807910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.91807910
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3860503741
Short name T348
Test name
Test status
Simulation time 193064910 ps
CPU time 5.42 seconds
Started Jul 10 06:03:07 PM PDT 24
Finished Jul 10 06:03:14 PM PDT 24
Peak memory 211416 kb
Host smart-97b719db-2d0e-49bf-8dc3-534c94483779
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860503741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3860503741
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1007351873
Short name T291
Test name
Test status
Simulation time 2533275155 ps
CPU time 9.97 seconds
Started Jul 10 06:03:08 PM PDT 24
Finished Jul 10 06:03:19 PM PDT 24
Peak memory 213992 kb
Host smart-437f91c6-8ec8-41db-975b-9f2488475d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007351873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1007351873
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3828244942
Short name T112
Test name
Test status
Simulation time 4524680853 ps
CPU time 37.5 seconds
Started Jul 10 06:03:07 PM PDT 24
Finished Jul 10 06:03:46 PM PDT 24
Peak memory 213956 kb
Host smart-d3f649e0-16f7-429f-b8fd-effaeb3e054a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828244942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3828244942
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.553822950
Short name T169
Test name
Test status
Simulation time 831168912 ps
CPU time 4.27 seconds
Started Jul 10 06:03:14 PM PDT 24
Finished Jul 10 06:03:19 PM PDT 24
Peak memory 211304 kb
Host smart-5953394b-1b30-4de5-908c-3e9314ce2543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553822950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.553822950
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.922651326
Short name T340
Test name
Test status
Simulation time 6062611995 ps
CPU time 90.04 seconds
Started Jul 10 06:03:11 PM PDT 24
Finished Jul 10 06:04:43 PM PDT 24
Peak memory 212536 kb
Host smart-8675231e-7692-43a9-9c66-38ca29327a38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922651326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.922651326
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1619944634
Short name T154
Test name
Test status
Simulation time 9871891366 ps
CPU time 23.72 seconds
Started Jul 10 06:03:10 PM PDT 24
Finished Jul 10 06:03:35 PM PDT 24
Peak memory 212320 kb
Host smart-489159d7-cf82-484c-8361-518c42ac64a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619944634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1619944634
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2569578967
Short name T143
Test name
Test status
Simulation time 2759617381 ps
CPU time 13.34 seconds
Started Jul 10 06:03:11 PM PDT 24
Finished Jul 10 06:03:25 PM PDT 24
Peak memory 211468 kb
Host smart-2d6289de-82d1-49e7-87c1-d7ab64cee8f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569578967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2569578967
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1997307439
Short name T268
Test name
Test status
Simulation time 7819692637 ps
CPU time 33.69 seconds
Started Jul 10 06:03:10 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 213672 kb
Host smart-388ddf03-e891-4521-b76e-8b2e7c0e0afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997307439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1997307439
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3283390791
Short name T215
Test name
Test status
Simulation time 4391168811 ps
CPU time 31.58 seconds
Started Jul 10 06:03:12 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 217164 kb
Host smart-af9e90e0-4126-43a6-8c9f-32fa7825fedf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283390791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3283390791
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1803870434
Short name T249
Test name
Test status
Simulation time 800320335 ps
CPU time 9.46 seconds
Started Jul 10 06:03:11 PM PDT 24
Finished Jul 10 06:03:22 PM PDT 24
Peak memory 211384 kb
Host smart-a7211ac1-730d-467b-8386-164b410952e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803870434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1803870434
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2179754614
Short name T335
Test name
Test status
Simulation time 68796937925 ps
CPU time 311.75 seconds
Started Jul 10 06:03:11 PM PDT 24
Finished Jul 10 06:08:24 PM PDT 24
Peak memory 213708 kb
Host smart-264ec233-735a-4a7e-9313-70f65f4c8de7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179754614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2179754614
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1715086190
Short name T297
Test name
Test status
Simulation time 266131761 ps
CPU time 9.39 seconds
Started Jul 10 06:03:17 PM PDT 24
Finished Jul 10 06:03:28 PM PDT 24
Peak memory 211416 kb
Host smart-0916b353-f239-4fe2-9709-6bc176fa5919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715086190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1715086190
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2167049677
Short name T137
Test name
Test status
Simulation time 5935978638 ps
CPU time 13.9 seconds
Started Jul 10 06:03:14 PM PDT 24
Finished Jul 10 06:03:29 PM PDT 24
Peak memory 211480 kb
Host smart-d87c8048-2648-44ef-968b-0f741b28a46c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167049677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2167049677
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3887494206
Short name T260
Test name
Test status
Simulation time 1258096233 ps
CPU time 12.54 seconds
Started Jul 10 06:03:17 PM PDT 24
Finished Jul 10 06:03:31 PM PDT 24
Peak memory 213332 kb
Host smart-f79d1ae4-29a8-4ad2-bd5a-cc598bcaf0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887494206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3887494206
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1095926908
Short name T161
Test name
Test status
Simulation time 889109269 ps
CPU time 30.56 seconds
Started Jul 10 06:03:17 PM PDT 24
Finished Jul 10 06:03:49 PM PDT 24
Peak memory 215608 kb
Host smart-a5173ed5-6a16-4501-8e5c-4a172d6deccc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095926908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1095926908
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2731322728
Short name T184
Test name
Test status
Simulation time 3761228267 ps
CPU time 14.8 seconds
Started Jul 10 06:03:10 PM PDT 24
Finished Jul 10 06:03:26 PM PDT 24
Peak memory 211404 kb
Host smart-7a4dbb71-24d5-4602-ad81-b9de06796e10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731322728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2731322728
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.324098829
Short name T159
Test name
Test status
Simulation time 52550811100 ps
CPU time 470.07 seconds
Started Jul 10 06:03:12 PM PDT 24
Finished Jul 10 06:11:03 PM PDT 24
Peak memory 234924 kb
Host smart-3131820a-f8c0-4aa8-9060-eabeb4f2d838
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324098829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.324098829
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.31204238
Short name T265
Test name
Test status
Simulation time 1811289361 ps
CPU time 15.7 seconds
Started Jul 10 06:03:11 PM PDT 24
Finished Jul 10 06:03:28 PM PDT 24
Peak memory 211972 kb
Host smart-1086328b-46ec-4fec-a023-8c4d25541c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31204238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.31204238
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.625854206
Short name T343
Test name
Test status
Simulation time 428741472 ps
CPU time 5.97 seconds
Started Jul 10 06:03:16 PM PDT 24
Finished Jul 10 06:03:23 PM PDT 24
Peak memory 211348 kb
Host smart-88b855b4-f2f6-4976-811e-72d8cdc8636e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625854206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.625854206
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1190018990
Short name T250
Test name
Test status
Simulation time 8946373722 ps
CPU time 25.01 seconds
Started Jul 10 06:03:13 PM PDT 24
Finished Jul 10 06:03:39 PM PDT 24
Peak memory 214548 kb
Host smart-dca02e44-c0b1-4144-aa39-ee409a16de0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190018990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1190018990
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1460461291
Short name T270
Test name
Test status
Simulation time 10369810628 ps
CPU time 30.29 seconds
Started Jul 10 06:03:10 PM PDT 24
Finished Jul 10 06:03:42 PM PDT 24
Peak memory 215160 kb
Host smart-deddc58f-7c08-43d3-b866-c5aa943022de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460461291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1460461291
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1648518733
Short name T47
Test name
Test status
Simulation time 52024701544 ps
CPU time 971.18 seconds
Started Jul 10 06:03:11 PM PDT 24
Finished Jul 10 06:19:24 PM PDT 24
Peak memory 228824 kb
Host smart-f3ed8d5e-6ae0-4a7b-a37a-5420e760b9e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648518733 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1648518733
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1132019770
Short name T332
Test name
Test status
Simulation time 346822390 ps
CPU time 4.22 seconds
Started Jul 10 06:03:17 PM PDT 24
Finished Jul 10 06:03:22 PM PDT 24
Peak memory 211332 kb
Host smart-0901cf58-f8c3-47e9-adbd-fce780473776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132019770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1132019770
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1605307236
Short name T35
Test name
Test status
Simulation time 97185976205 ps
CPU time 521.34 seconds
Started Jul 10 06:03:19 PM PDT 24
Finished Jul 10 06:12:01 PM PDT 24
Peak memory 237976 kb
Host smart-aa22d188-9123-4903-97ee-495a34ed5b2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605307236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1605307236
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.41087281
Short name T331
Test name
Test status
Simulation time 5663522229 ps
CPU time 14.59 seconds
Started Jul 10 06:03:24 PM PDT 24
Finished Jul 10 06:03:40 PM PDT 24
Peak memory 212784 kb
Host smart-14e2cc30-4429-4b5b-9d6d-b7bbdd0af1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41087281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.41087281
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.151518448
Short name T166
Test name
Test status
Simulation time 850450394 ps
CPU time 10.22 seconds
Started Jul 10 06:03:10 PM PDT 24
Finished Jul 10 06:03:21 PM PDT 24
Peak memory 211400 kb
Host smart-38781272-0088-4ccf-bd1e-27bf35e40a67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151518448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.151518448
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2849643613
Short name T214
Test name
Test status
Simulation time 729704593 ps
CPU time 9.87 seconds
Started Jul 10 06:03:11 PM PDT 24
Finished Jul 10 06:03:22 PM PDT 24
Peak memory 213500 kb
Host smart-4113e355-3cf3-4396-8758-f8cedc5838e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849643613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2849643613
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2979537445
Short name T186
Test name
Test status
Simulation time 1302854739 ps
CPU time 12.4 seconds
Started Jul 10 06:03:21 PM PDT 24
Finished Jul 10 06:03:34 PM PDT 24
Peak memory 211348 kb
Host smart-c9801d4d-d6b6-429d-bfa2-13e0ead9e906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979537445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2979537445
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4128037962
Short name T334
Test name
Test status
Simulation time 1881429623 ps
CPU time 129.18 seconds
Started Jul 10 06:03:21 PM PDT 24
Finished Jul 10 06:05:31 PM PDT 24
Peak memory 236936 kb
Host smart-50dc434c-4b1a-446c-9dde-b7ee97851a44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128037962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4128037962
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2652622642
Short name T277
Test name
Test status
Simulation time 11497707929 ps
CPU time 26.71 seconds
Started Jul 10 06:03:17 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 212220 kb
Host smart-4b644475-ff46-4c4a-8cb4-7e87dab25305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652622642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2652622642
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.655670661
Short name T269
Test name
Test status
Simulation time 7234487111 ps
CPU time 16.15 seconds
Started Jul 10 06:03:19 PM PDT 24
Finished Jul 10 06:03:36 PM PDT 24
Peak memory 211444 kb
Host smart-96559a5f-81dd-4b47-8bf6-5d3ea06c53b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=655670661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.655670661
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3614858089
Short name T131
Test name
Test status
Simulation time 4304506514 ps
CPU time 16.67 seconds
Started Jul 10 06:03:17 PM PDT 24
Finished Jul 10 06:03:35 PM PDT 24
Peak memory 213784 kb
Host smart-0d91cc00-b1bf-4cdc-9b6a-fe100d5f10e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614858089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3614858089
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.843310802
Short name T296
Test name
Test status
Simulation time 2852380619 ps
CPU time 25.02 seconds
Started Jul 10 06:03:22 PM PDT 24
Finished Jul 10 06:03:48 PM PDT 24
Peak memory 216600 kb
Host smart-6bbbca18-670b-46b4-9e4b-9660f108ea22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843310802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.843310802
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1678380444
Short name T58
Test name
Test status
Simulation time 6299870165 ps
CPU time 13.03 seconds
Started Jul 10 06:03:21 PM PDT 24
Finished Jul 10 06:03:35 PM PDT 24
Peak memory 211436 kb
Host smart-b3528a7c-a4f8-450e-879f-1ded1aa6917c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678380444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1678380444
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2382339180
Short name T321
Test name
Test status
Simulation time 9822552216 ps
CPU time 205.88 seconds
Started Jul 10 06:03:18 PM PDT 24
Finished Jul 10 06:06:45 PM PDT 24
Peak memory 234900 kb
Host smart-a6f101e6-4140-4fd7-bfac-bda47ce22b3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382339180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2382339180
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.655147556
Short name T40
Test name
Test status
Simulation time 175334014 ps
CPU time 9.58 seconds
Started Jul 10 06:03:20 PM PDT 24
Finished Jul 10 06:03:30 PM PDT 24
Peak memory 211980 kb
Host smart-d043b2ad-b31f-4541-85d6-ec23234523d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655147556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.655147556
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.933601474
Short name T207
Test name
Test status
Simulation time 7257249387 ps
CPU time 15.29 seconds
Started Jul 10 06:03:19 PM PDT 24
Finished Jul 10 06:03:35 PM PDT 24
Peak memory 211444 kb
Host smart-9af22586-cbaa-416b-980e-b04736730a79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933601474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.933601474
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.687827723
Short name T205
Test name
Test status
Simulation time 4227018849 ps
CPU time 32.9 seconds
Started Jul 10 06:03:16 PM PDT 24
Finished Jul 10 06:03:50 PM PDT 24
Peak memory 213876 kb
Host smart-2c3951b6-2ef2-4fb3-a7f3-c5056d316491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687827723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.687827723
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3616688707
Short name T120
Test name
Test status
Simulation time 9560393336 ps
CPU time 13.11 seconds
Started Jul 10 06:03:17 PM PDT 24
Finished Jul 10 06:03:32 PM PDT 24
Peak memory 211468 kb
Host smart-1e8e6f92-a520-431c-83bd-f169e6863d97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616688707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3616688707
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3460224294
Short name T288
Test name
Test status
Simulation time 175253918 ps
CPU time 4.43 seconds
Started Jul 10 06:03:24 PM PDT 24
Finished Jul 10 06:03:30 PM PDT 24
Peak memory 211328 kb
Host smart-4c7cead0-ae34-4e14-81d0-3ce8fc928a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460224294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3460224294
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.13945821
Short name T197
Test name
Test status
Simulation time 187513611906 ps
CPU time 336.94 seconds
Started Jul 10 06:03:26 PM PDT 24
Finished Jul 10 06:09:04 PM PDT 24
Peak memory 225020 kb
Host smart-cdce7ac6-c863-47ac-9551-4e3433f44c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13945821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_co
rrupt_sig_fatal_chk.13945821
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.979504994
Short name T1
Test name
Test status
Simulation time 1621054302 ps
CPU time 15.42 seconds
Started Jul 10 06:03:22 PM PDT 24
Finished Jul 10 06:03:39 PM PDT 24
Peak memory 212060 kb
Host smart-e6a490d1-153a-470b-898b-c1111da97128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979504994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.979504994
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3003158376
Short name T133
Test name
Test status
Simulation time 1263902797 ps
CPU time 12.59 seconds
Started Jul 10 06:03:17 PM PDT 24
Finished Jul 10 06:03:31 PM PDT 24
Peak memory 211416 kb
Host smart-b6ececcf-de57-46b9-816d-23db31f64ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003158376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3003158376
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2875923658
Short name T191
Test name
Test status
Simulation time 34011442895 ps
CPU time 23.69 seconds
Started Jul 10 06:03:17 PM PDT 24
Finished Jul 10 06:03:42 PM PDT 24
Peak memory 213952 kb
Host smart-55e273e2-6911-4a0a-97b6-e55ec56a1077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875923658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2875923658
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4248963616
Short name T115
Test name
Test status
Simulation time 136694990 ps
CPU time 6.79 seconds
Started Jul 10 06:03:17 PM PDT 24
Finished Jul 10 06:03:25 PM PDT 24
Peak memory 211408 kb
Host smart-881becae-b23c-40bb-b3e6-e458772b1dd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248963616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4248963616
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.311665433
Short name T24
Test name
Test status
Simulation time 5979911049 ps
CPU time 13.35 seconds
Started Jul 10 06:03:22 PM PDT 24
Finished Jul 10 06:03:36 PM PDT 24
Peak memory 211416 kb
Host smart-48a3249b-a75e-4a8b-91a4-0c20f438e129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311665433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.311665433
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1229051750
Short name T204
Test name
Test status
Simulation time 16747992535 ps
CPU time 184.34 seconds
Started Jul 10 06:03:21 PM PDT 24
Finished Jul 10 06:06:26 PM PDT 24
Peak memory 237856 kb
Host smart-c5e52e21-a17e-44ef-b998-0ca9eeeca8be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229051750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1229051750
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2924339785
Short name T266
Test name
Test status
Simulation time 4752913704 ps
CPU time 22.91 seconds
Started Jul 10 06:03:25 PM PDT 24
Finished Jul 10 06:03:49 PM PDT 24
Peak memory 212596 kb
Host smart-fa2b36a5-4c5e-46f2-a593-2a2d0627ba1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924339785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2924339785
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1450396273
Short name T200
Test name
Test status
Simulation time 1770804939 ps
CPU time 15.91 seconds
Started Jul 10 06:03:26 PM PDT 24
Finished Jul 10 06:03:43 PM PDT 24
Peak memory 211412 kb
Host smart-d6ed30b9-cbe4-4f01-9c47-283c585b1f18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450396273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1450396273
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3261294788
Short name T4
Test name
Test status
Simulation time 13854361207 ps
CPU time 29.62 seconds
Started Jul 10 06:03:22 PM PDT 24
Finished Jul 10 06:03:53 PM PDT 24
Peak memory 214048 kb
Host smart-9999d206-725b-4c07-85c1-1f120853b40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261294788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3261294788
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.973373037
Short name T313
Test name
Test status
Simulation time 11496723015 ps
CPU time 36.1 seconds
Started Jul 10 06:03:24 PM PDT 24
Finished Jul 10 06:04:01 PM PDT 24
Peak memory 219444 kb
Host smart-a4e55b9c-db0c-4e8c-83c3-530cb0002784
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973373037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.973373037
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1801633346
Short name T48
Test name
Test status
Simulation time 103616403028 ps
CPU time 4019.52 seconds
Started Jul 10 06:03:29 PM PDT 24
Finished Jul 10 07:10:30 PM PDT 24
Peak memory 235812 kb
Host smart-7f1304e6-ebf9-4e28-bd83-70059a1aeaf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801633346 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1801633346
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3296969847
Short name T190
Test name
Test status
Simulation time 89016232 ps
CPU time 4.42 seconds
Started Jul 10 06:02:21 PM PDT 24
Finished Jul 10 06:02:26 PM PDT 24
Peak memory 211340 kb
Host smart-42794ab0-f5fa-4720-ba7d-1829fdacfbfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296969847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3296969847
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3822319425
Short name T211
Test name
Test status
Simulation time 29461190059 ps
CPU time 327.84 seconds
Started Jul 10 06:02:24 PM PDT 24
Finished Jul 10 06:07:53 PM PDT 24
Peak memory 233860 kb
Host smart-6690103b-e790-4a37-a9fc-b12587f612b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822319425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3822319425
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2641889856
Short name T238
Test name
Test status
Simulation time 171971214 ps
CPU time 9.64 seconds
Started Jul 10 06:02:18 PM PDT 24
Finished Jul 10 06:02:28 PM PDT 24
Peak memory 211972 kb
Host smart-85ad4fd9-db8d-4f1d-82f6-d11244307398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641889856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2641889856
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1949484923
Short name T316
Test name
Test status
Simulation time 2615271036 ps
CPU time 10.07 seconds
Started Jul 10 06:02:17 PM PDT 24
Finished Jul 10 06:02:28 PM PDT 24
Peak memory 211456 kb
Host smart-71d4f9ba-d7c7-4623-8b75-2ee8b26fabbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1949484923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1949484923
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1825289084
Short name T225
Test name
Test status
Simulation time 22316536948 ps
CPU time 38.91 seconds
Started Jul 10 06:02:22 PM PDT 24
Finished Jul 10 06:03:02 PM PDT 24
Peak memory 214148 kb
Host smart-25c87711-9a54-4cc6-8cd6-f119b79c2c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825289084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1825289084
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.911378712
Short name T155
Test name
Test status
Simulation time 3614688043 ps
CPU time 19.33 seconds
Started Jul 10 06:02:21 PM PDT 24
Finished Jul 10 06:02:42 PM PDT 24
Peak memory 211332 kb
Host smart-5e6ba2b3-c8d3-4197-9786-0b6563d0cd8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911378712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.911378712
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2329120266
Short name T125
Test name
Test status
Simulation time 3210873673 ps
CPU time 11.37 seconds
Started Jul 10 06:02:21 PM PDT 24
Finished Jul 10 06:02:33 PM PDT 24
Peak memory 211452 kb
Host smart-95ac3e61-14a9-4866-97bb-72ea071c0edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329120266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2329120266
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3749943541
Short name T34
Test name
Test status
Simulation time 219229260862 ps
CPU time 231.63 seconds
Started Jul 10 06:02:16 PM PDT 24
Finished Jul 10 06:06:08 PM PDT 24
Peak memory 237220 kb
Host smart-3f9951ba-3192-496d-af10-94815df2f8ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749943541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3749943541
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.10388152
Short name T141
Test name
Test status
Simulation time 11299358382 ps
CPU time 27.35 seconds
Started Jul 10 06:02:17 PM PDT 24
Finished Jul 10 06:02:45 PM PDT 24
Peak memory 212304 kb
Host smart-e74934e3-03e9-4436-aad1-8fe052a06f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10388152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.10388152
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3240931866
Short name T138
Test name
Test status
Simulation time 417870268 ps
CPU time 5.64 seconds
Started Jul 10 06:02:17 PM PDT 24
Finished Jul 10 06:02:24 PM PDT 24
Peak memory 211400 kb
Host smart-805a8c6a-eb49-45f0-b544-7d091cea78dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240931866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3240931866
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1537354430
Short name T278
Test name
Test status
Simulation time 34021276419 ps
CPU time 29.92 seconds
Started Jul 10 06:02:20 PM PDT 24
Finished Jul 10 06:02:51 PM PDT 24
Peak memory 214332 kb
Host smart-8ba14705-47a9-446d-af9b-ce123a35763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537354430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1537354430
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2932529924
Short name T76
Test name
Test status
Simulation time 1096812473 ps
CPU time 33.24 seconds
Started Jul 10 06:02:20 PM PDT 24
Finished Jul 10 06:02:54 PM PDT 24
Peak memory 215944 kb
Host smart-790acba3-d944-49c8-91a0-d077ac02b4c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932529924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2932529924
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1960835217
Short name T59
Test name
Test status
Simulation time 2473415151 ps
CPU time 8.34 seconds
Started Jul 10 06:02:20 PM PDT 24
Finished Jul 10 06:02:29 PM PDT 24
Peak memory 211412 kb
Host smart-82b297bb-0ed3-4c1e-aad8-6b370615b83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960835217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1960835217
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3677995810
Short name T237
Test name
Test status
Simulation time 115603094622 ps
CPU time 290.51 seconds
Started Jul 10 06:02:18 PM PDT 24
Finished Jul 10 06:07:10 PM PDT 24
Peak memory 236872 kb
Host smart-fbc57212-0149-4042-bcfb-42f812cfb529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677995810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3677995810
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.218915779
Short name T286
Test name
Test status
Simulation time 692337052 ps
CPU time 14.8 seconds
Started Jul 10 06:02:19 PM PDT 24
Finished Jul 10 06:02:35 PM PDT 24
Peak memory 211892 kb
Host smart-b1f25550-d9c0-4998-9d9c-8250c985a09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218915779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.218915779
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3646137344
Short name T136
Test name
Test status
Simulation time 1587208433 ps
CPU time 7.4 seconds
Started Jul 10 06:02:20 PM PDT 24
Finished Jul 10 06:02:29 PM PDT 24
Peak memory 211400 kb
Host smart-41469454-eccc-409a-8bbd-45c2352ebc72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646137344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3646137344
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3642374355
Short name T129
Test name
Test status
Simulation time 12589817812 ps
CPU time 24.43 seconds
Started Jul 10 06:02:21 PM PDT 24
Finished Jul 10 06:02:47 PM PDT 24
Peak memory 214240 kb
Host smart-02e05d28-12a2-4999-94ad-738f22826715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642374355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3642374355
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3650444661
Short name T2
Test name
Test status
Simulation time 213019305 ps
CPU time 6.69 seconds
Started Jul 10 06:02:19 PM PDT 24
Finished Jul 10 06:02:27 PM PDT 24
Peak memory 211356 kb
Host smart-220d0d41-aa82-4e81-9416-284a25694324
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650444661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3650444661
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2063536480
Short name T60
Test name
Test status
Simulation time 303583663 ps
CPU time 6.22 seconds
Started Jul 10 06:02:22 PM PDT 24
Finished Jul 10 06:02:29 PM PDT 24
Peak memory 211368 kb
Host smart-31f8d4ff-bc12-452f-ab27-844673763962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063536480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2063536480
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.718743343
Short name T130
Test name
Test status
Simulation time 73683522137 ps
CPU time 261.03 seconds
Started Jul 10 06:02:22 PM PDT 24
Finished Jul 10 06:06:44 PM PDT 24
Peak memory 234512 kb
Host smart-9878650d-5656-42bc-85af-5bc26cd68fdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718743343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.718743343
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3448790357
Short name T303
Test name
Test status
Simulation time 172511512 ps
CPU time 9.29 seconds
Started Jul 10 06:02:22 PM PDT 24
Finished Jul 10 06:02:33 PM PDT 24
Peak memory 213108 kb
Host smart-d90cf3aa-c829-4ba7-9d66-ff2ce5cd4124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448790357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3448790357
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1671207324
Short name T147
Test name
Test status
Simulation time 1114059004 ps
CPU time 8.72 seconds
Started Jul 10 06:02:17 PM PDT 24
Finished Jul 10 06:02:27 PM PDT 24
Peak memory 211400 kb
Host smart-2663c6b5-6e2f-4385-8cf9-84fcc4e3d87f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671207324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1671207324
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3956306983
Short name T235
Test name
Test status
Simulation time 192800863 ps
CPU time 9.88 seconds
Started Jul 10 06:02:20 PM PDT 24
Finished Jul 10 06:02:31 PM PDT 24
Peak memory 212904 kb
Host smart-b7abc93b-6880-4bb3-b042-5d4550059f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956306983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3956306983
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1839649725
Short name T287
Test name
Test status
Simulation time 10663375385 ps
CPU time 43.13 seconds
Started Jul 10 06:02:21 PM PDT 24
Finished Jul 10 06:03:05 PM PDT 24
Peak memory 217100 kb
Host smart-07482208-f9ba-46d8-b0a5-37a56d25786f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839649725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1839649725
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3636813096
Short name T46
Test name
Test status
Simulation time 130094753136 ps
CPU time 7278.08 seconds
Started Jul 10 06:02:18 PM PDT 24
Finished Jul 10 08:03:39 PM PDT 24
Peak memory 231144 kb
Host smart-b24625bb-d73d-424d-9b2a-518674988eb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636813096 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3636813096
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4040072400
Short name T185
Test name
Test status
Simulation time 348089526 ps
CPU time 4.28 seconds
Started Jul 10 06:02:25 PM PDT 24
Finished Jul 10 06:02:31 PM PDT 24
Peak memory 211272 kb
Host smart-b2ce25e5-070e-4842-a6cf-7ae8967e51ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040072400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4040072400
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.694103288
Short name T328
Test name
Test status
Simulation time 10381242558 ps
CPU time 136.4 seconds
Started Jul 10 06:02:25 PM PDT 24
Finished Jul 10 06:04:43 PM PDT 24
Peak memory 236860 kb
Host smart-6f4f8c81-2f35-4c01-80d9-9f32d0edf0fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694103288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.694103288
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1325691568
Short name T280
Test name
Test status
Simulation time 183210194 ps
CPU time 9.58 seconds
Started Jul 10 06:02:27 PM PDT 24
Finished Jul 10 06:02:37 PM PDT 24
Peak memory 211920 kb
Host smart-6719e036-ca13-4b99-ae1f-c12789a6b5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325691568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1325691568
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.985311830
Short name T299
Test name
Test status
Simulation time 2288853546 ps
CPU time 11.13 seconds
Started Jul 10 06:02:28 PM PDT 24
Finished Jul 10 06:02:41 PM PDT 24
Peak memory 211460 kb
Host smart-b988fb6b-2167-4b0c-badc-da1e9373f4ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985311830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.985311830
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3985058642
Short name T177
Test name
Test status
Simulation time 7663704731 ps
CPU time 25.03 seconds
Started Jul 10 06:02:24 PM PDT 24
Finished Jul 10 06:02:50 PM PDT 24
Peak memory 213308 kb
Host smart-a9941cca-cc9d-4c06-b6cd-dd8a0f9ad7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985058642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3985058642
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.437951288
Short name T324
Test name
Test status
Simulation time 545012618 ps
CPU time 10.93 seconds
Started Jul 10 06:02:27 PM PDT 24
Finished Jul 10 06:02:39 PM PDT 24
Peak memory 212028 kb
Host smart-578b91b2-922b-4d22-997a-9a9d40f32035
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437951288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.437951288
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.655326124
Short name T352
Test name
Test status
Simulation time 57456306509 ps
CPU time 2035.86 seconds
Started Jul 10 06:02:24 PM PDT 24
Finished Jul 10 06:36:21 PM PDT 24
Peak memory 235816 kb
Host smart-111a9670-5a2e-423d-83d7-555842ba528c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655326124 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.655326124
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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