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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 96.89 91.85 97.67 100.00 98.28 97.30 99.07


Total test records in report: 469
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T294 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4014165631 Jul 11 05:32:11 PM PDT 24 Jul 11 05:35:16 PM PDT 24 13319951207 ps
T295 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3976050556 Jul 11 05:31:24 PM PDT 24 Jul 11 05:31:44 PM PDT 24 3665107254 ps
T296 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.414748937 Jul 11 05:32:46 PM PDT 24 Jul 11 06:00:05 PM PDT 24 167990685775 ps
T297 /workspace/coverage/default/22.rom_ctrl_stress_all.2939448601 Jul 11 05:32:11 PM PDT 24 Jul 11 05:32:36 PM PDT 24 7031161386 ps
T298 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2222066444 Jul 11 05:32:11 PM PDT 24 Jul 11 05:32:40 PM PDT 24 11194029309 ps
T299 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2152781343 Jul 11 05:31:35 PM PDT 24 Jul 11 06:30:40 PM PDT 24 33912591357 ps
T300 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.951021656 Jul 11 05:32:55 PM PDT 24 Jul 11 05:33:19 PM PDT 24 3944247879 ps
T301 /workspace/coverage/default/1.rom_ctrl_alert_test.4070518188 Jul 11 05:31:24 PM PDT 24 Jul 11 05:31:41 PM PDT 24 7052735687 ps
T302 /workspace/coverage/default/16.rom_ctrl_stress_all.1072019477 Jul 11 05:31:52 PM PDT 24 Jul 11 05:32:30 PM PDT 24 2468441031 ps
T303 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3266874875 Jul 11 05:31:45 PM PDT 24 Jul 11 05:31:55 PM PDT 24 1319931012 ps
T304 /workspace/coverage/default/43.rom_ctrl_alert_test.595942933 Jul 11 05:32:46 PM PDT 24 Jul 11 05:32:57 PM PDT 24 1254626036 ps
T305 /workspace/coverage/default/15.rom_ctrl_alert_test.2276754617 Jul 11 05:31:53 PM PDT 24 Jul 11 05:32:11 PM PDT 24 12332267976 ps
T306 /workspace/coverage/default/3.rom_ctrl_stress_all.1003207739 Jul 11 05:31:17 PM PDT 24 Jul 11 05:31:56 PM PDT 24 8350689955 ps
T307 /workspace/coverage/default/7.rom_ctrl_alert_test.2765121115 Jul 11 05:31:34 PM PDT 24 Jul 11 05:31:41 PM PDT 24 348232662 ps
T308 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1961708257 Jul 11 05:31:47 PM PDT 24 Jul 11 05:34:48 PM PDT 24 65506143865 ps
T309 /workspace/coverage/default/5.rom_ctrl_stress_all.2868829253 Jul 11 05:31:32 PM PDT 24 Jul 11 05:32:07 PM PDT 24 548274277 ps
T310 /workspace/coverage/default/23.rom_ctrl_smoke.3161067884 Jul 11 05:32:05 PM PDT 24 Jul 11 05:32:35 PM PDT 24 3743038200 ps
T311 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.700890176 Jul 11 05:32:13 PM PDT 24 Jul 11 05:35:22 PM PDT 24 32513728840 ps
T312 /workspace/coverage/default/14.rom_ctrl_stress_all.3947678068 Jul 11 05:31:46 PM PDT 24 Jul 11 05:32:19 PM PDT 24 11710551651 ps
T313 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2096666255 Jul 11 05:31:52 PM PDT 24 Jul 11 05:32:24 PM PDT 24 3842194471 ps
T314 /workspace/coverage/default/26.rom_ctrl_alert_test.2730589917 Jul 11 05:32:08 PM PDT 24 Jul 11 05:32:26 PM PDT 24 1705486977 ps
T315 /workspace/coverage/default/5.rom_ctrl_alert_test.3371408580 Jul 11 05:31:35 PM PDT 24 Jul 11 05:31:42 PM PDT 24 333811716 ps
T316 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3883084958 Jul 11 05:31:50 PM PDT 24 Jul 11 05:32:02 PM PDT 24 2744177571 ps
T317 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1783897049 Jul 11 05:32:45 PM PDT 24 Jul 11 05:35:50 PM PDT 24 36847221495 ps
T318 /workspace/coverage/default/43.rom_ctrl_stress_all.614225709 Jul 11 05:32:44 PM PDT 24 Jul 11 05:33:47 PM PDT 24 111454131768 ps
T319 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3968091336 Jul 11 05:32:33 PM PDT 24 Jul 11 06:41:10 PM PDT 24 23841115436 ps
T320 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3511919506 Jul 11 05:32:27 PM PDT 24 Jul 11 05:36:41 PM PDT 24 46785955186 ps
T321 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1999171227 Jul 11 05:32:34 PM PDT 24 Jul 11 05:34:04 PM PDT 24 4612865519 ps
T322 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3766525339 Jul 11 05:31:41 PM PDT 24 Jul 11 05:31:56 PM PDT 24 5878936242 ps
T323 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2386668071 Jul 11 05:31:44 PM PDT 24 Jul 11 05:36:51 PM PDT 24 86824452893 ps
T324 /workspace/coverage/default/27.rom_ctrl_stress_all.1760519837 Jul 11 05:32:15 PM PDT 24 Jul 11 05:33:08 PM PDT 24 29250468595 ps
T325 /workspace/coverage/default/12.rom_ctrl_stress_all.3871048503 Jul 11 05:31:49 PM PDT 24 Jul 11 05:32:21 PM PDT 24 5208329829 ps
T326 /workspace/coverage/default/13.rom_ctrl_smoke.3602598091 Jul 11 05:31:54 PM PDT 24 Jul 11 05:32:12 PM PDT 24 855550129 ps
T327 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3416231425 Jul 11 05:31:23 PM PDT 24 Jul 11 05:31:35 PM PDT 24 334832962 ps
T328 /workspace/coverage/default/46.rom_ctrl_stress_all.2405863000 Jul 11 05:32:47 PM PDT 24 Jul 11 05:33:09 PM PDT 24 2491878556 ps
T329 /workspace/coverage/default/6.rom_ctrl_alert_test.3013055245 Jul 11 05:31:33 PM PDT 24 Jul 11 05:31:45 PM PDT 24 3126336303 ps
T330 /workspace/coverage/default/48.rom_ctrl_alert_test.1639737392 Jul 11 05:32:53 PM PDT 24 Jul 11 05:33:00 PM PDT 24 168119036 ps
T331 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3401422776 Jul 11 05:32:44 PM PDT 24 Jul 11 05:34:56 PM PDT 24 40735484980 ps
T332 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2592966212 Jul 11 05:31:51 PM PDT 24 Jul 11 05:35:13 PM PDT 24 89302678514 ps
T333 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.274812118 Jul 11 05:32:34 PM PDT 24 Jul 11 05:32:42 PM PDT 24 151690304 ps
T334 /workspace/coverage/default/22.rom_ctrl_alert_test.3321713970 Jul 11 05:32:17 PM PDT 24 Jul 11 05:32:33 PM PDT 24 1910570985 ps
T335 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1751569430 Jul 11 05:32:52 PM PDT 24 Jul 11 05:33:00 PM PDT 24 95905129 ps
T336 /workspace/coverage/default/45.rom_ctrl_alert_test.2447362063 Jul 11 05:32:55 PM PDT 24 Jul 11 05:33:02 PM PDT 24 414975209 ps
T337 /workspace/coverage/default/37.rom_ctrl_smoke.1326903880 Jul 11 05:32:29 PM PDT 24 Jul 11 05:32:58 PM PDT 24 8844564646 ps
T338 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3239970775 Jul 11 05:32:06 PM PDT 24 Jul 11 05:32:28 PM PDT 24 42026548949 ps
T339 /workspace/coverage/default/38.rom_ctrl_stress_all.889468964 Jul 11 05:32:34 PM PDT 24 Jul 11 05:34:24 PM PDT 24 55809379103 ps
T340 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4096067851 Jul 11 05:32:22 PM PDT 24 Jul 11 05:32:29 PM PDT 24 99384550 ps
T24 /workspace/coverage/default/3.rom_ctrl_sec_cm.1893241196 Jul 11 05:31:25 PM PDT 24 Jul 11 05:33:10 PM PDT 24 1464183045 ps
T341 /workspace/coverage/default/1.rom_ctrl_stress_all.2490240765 Jul 11 05:31:17 PM PDT 24 Jul 11 05:31:36 PM PDT 24 1761841988 ps
T342 /workspace/coverage/default/0.rom_ctrl_alert_test.1288568678 Jul 11 05:31:22 PM PDT 24 Jul 11 05:31:37 PM PDT 24 5549575686 ps
T343 /workspace/coverage/default/35.rom_ctrl_smoke.704689656 Jul 11 05:32:32 PM PDT 24 Jul 11 05:33:00 PM PDT 24 11245702308 ps
T344 /workspace/coverage/default/9.rom_ctrl_smoke.3337095561 Jul 11 05:31:44 PM PDT 24 Jul 11 05:32:02 PM PDT 24 921506102 ps
T345 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2867053204 Jul 11 05:32:08 PM PDT 24 Jul 11 05:32:23 PM PDT 24 1215780259 ps
T346 /workspace/coverage/default/31.rom_ctrl_stress_all.2322658256 Jul 11 05:32:24 PM PDT 24 Jul 11 05:32:38 PM PDT 24 196287220 ps
T347 /workspace/coverage/default/29.rom_ctrl_alert_test.3037639160 Jul 11 05:32:20 PM PDT 24 Jul 11 05:32:26 PM PDT 24 88323841 ps
T348 /workspace/coverage/default/1.rom_ctrl_smoke.2983026142 Jul 11 05:31:17 PM PDT 24 Jul 11 05:31:30 PM PDT 24 702435325 ps
T349 /workspace/coverage/default/27.rom_ctrl_smoke.3828877259 Jul 11 05:32:13 PM PDT 24 Jul 11 05:32:52 PM PDT 24 4193714011 ps
T350 /workspace/coverage/default/24.rom_ctrl_alert_test.683250253 Jul 11 05:32:15 PM PDT 24 Jul 11 05:32:24 PM PDT 24 468834458 ps
T351 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2597103753 Jul 11 05:32:32 PM PDT 24 Jul 11 05:33:51 PM PDT 24 3104561502 ps
T352 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1439293701 Jul 11 05:31:16 PM PDT 24 Jul 11 06:37:45 PM PDT 24 33771863228 ps
T353 /workspace/coverage/default/38.rom_ctrl_smoke.3851786361 Jul 11 05:32:33 PM PDT 24 Jul 11 05:32:45 PM PDT 24 751399947 ps
T354 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3410700244 Jul 11 05:31:33 PM PDT 24 Jul 11 05:32:08 PM PDT 24 16731131370 ps
T111 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2520610828 Jul 11 05:31:44 PM PDT 24 Jul 11 07:25:45 PM PDT 24 351087535817 ps
T355 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2371575419 Jul 11 05:32:14 PM PDT 24 Jul 11 05:32:32 PM PDT 24 1761911114 ps
T356 /workspace/coverage/default/17.rom_ctrl_smoke.1440126950 Jul 11 05:31:54 PM PDT 24 Jul 11 05:32:05 PM PDT 24 842263836 ps
T357 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1986372131 Jul 11 05:31:48 PM PDT 24 Jul 11 05:31:59 PM PDT 24 730540816 ps
T358 /workspace/coverage/default/7.rom_ctrl_smoke.3456634884 Jul 11 05:31:40 PM PDT 24 Jul 11 05:32:10 PM PDT 24 7804296140 ps
T359 /workspace/coverage/default/0.rom_ctrl_smoke.1611856863 Jul 11 05:31:26 PM PDT 24 Jul 11 05:31:48 PM PDT 24 4994984791 ps
T360 /workspace/coverage/default/46.rom_ctrl_smoke.1923535696 Jul 11 05:32:47 PM PDT 24 Jul 11 05:33:25 PM PDT 24 5751651244 ps
T361 /workspace/coverage/default/48.rom_ctrl_stress_all.3717839709 Jul 11 05:32:53 PM PDT 24 Jul 11 05:33:11 PM PDT 24 1367018602 ps
T362 /workspace/coverage/default/5.rom_ctrl_smoke.2313304478 Jul 11 05:31:35 PM PDT 24 Jul 11 05:32:07 PM PDT 24 7127627860 ps
T363 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.287075311 Jul 11 05:32:09 PM PDT 24 Jul 11 05:32:19 PM PDT 24 176723017 ps
T364 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1245294319 Jul 11 05:32:07 PM PDT 24 Jul 11 05:32:42 PM PDT 24 18416231034 ps
T365 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4102730219 Jul 11 05:32:05 PM PDT 24 Jul 11 05:34:25 PM PDT 24 56948961348 ps
T55 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.269471763 Jul 11 05:31:02 PM PDT 24 Jul 11 05:31:11 PM PDT 24 1138393628 ps
T56 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2584644757 Jul 11 05:31:05 PM PDT 24 Jul 11 05:31:13 PM PDT 24 860569775 ps
T57 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1214653782 Jul 11 05:30:51 PM PDT 24 Jul 11 05:31:49 PM PDT 24 6582514741 ps
T60 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4261076846 Jul 11 05:31:11 PM PDT 24 Jul 11 05:32:05 PM PDT 24 21645951771 ps
T61 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2435920237 Jul 11 05:31:02 PM PDT 24 Jul 11 05:32:00 PM PDT 24 9430969001 ps
T366 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3817378683 Jul 11 05:31:27 PM PDT 24 Jul 11 05:31:42 PM PDT 24 1449265175 ps
T62 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4158938334 Jul 11 05:31:14 PM PDT 24 Jul 11 05:31:31 PM PDT 24 2327555458 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3245206240 Jul 11 05:30:57 PM PDT 24 Jul 11 05:31:10 PM PDT 24 1310768361 ps
T367 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3805681265 Jul 11 05:31:03 PM PDT 24 Jul 11 05:31:10 PM PDT 24 896517196 ps
T63 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1296971202 Jul 11 05:31:00 PM PDT 24 Jul 11 05:31:21 PM PDT 24 1204203494 ps
T64 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.431653382 Jul 11 05:31:15 PM PDT 24 Jul 11 05:31:22 PM PDT 24 161671203 ps
T65 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3649215447 Jul 11 05:31:11 PM PDT 24 Jul 11 05:31:22 PM PDT 24 4091064662 ps
T98 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3840266246 Jul 11 05:30:55 PM PDT 24 Jul 11 05:32:12 PM PDT 24 21969239327 ps
T66 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1305728140 Jul 11 05:31:05 PM PDT 24 Jul 11 05:31:14 PM PDT 24 983070937 ps
T67 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3388204576 Jul 11 05:31:09 PM PDT 24 Jul 11 05:31:26 PM PDT 24 12091629328 ps
T76 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4198277047 Jul 11 05:31:04 PM PDT 24 Jul 11 05:31:36 PM PDT 24 8974105753 ps
T52 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1322981017 Jul 11 05:31:11 PM PDT 24 Jul 11 05:32:27 PM PDT 24 1152188379 ps
T368 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1302062539 Jul 11 05:31:10 PM PDT 24 Jul 11 05:31:25 PM PDT 24 1820636176 ps
T53 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2725330853 Jul 11 05:31:05 PM PDT 24 Jul 11 05:31:55 PM PDT 24 4223542987 ps
T369 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3521358763 Jul 11 05:30:59 PM PDT 24 Jul 11 05:31:06 PM PDT 24 517934017 ps
T77 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4085923926 Jul 11 05:31:14 PM PDT 24 Jul 11 05:31:44 PM PDT 24 1536090644 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1603266789 Jul 11 05:30:55 PM PDT 24 Jul 11 05:31:12 PM PDT 24 1928361577 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.634977522 Jul 11 05:30:50 PM PDT 24 Jul 11 05:31:01 PM PDT 24 783869511 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1395824530 Jul 11 05:30:47 PM PDT 24 Jul 11 05:30:58 PM PDT 24 2811976968 ps
T54 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3973156749 Jul 11 05:31:17 PM PDT 24 Jul 11 05:31:57 PM PDT 24 553785778 ps
T79 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1290384979 Jul 11 05:30:47 PM PDT 24 Jul 11 05:30:57 PM PDT 24 2247956500 ps
T89 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3858394291 Jul 11 05:31:12 PM PDT 24 Jul 11 05:31:23 PM PDT 24 2138392713 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2197291811 Jul 11 05:31:02 PM PDT 24 Jul 11 05:31:14 PM PDT 24 1128746553 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.578576053 Jul 11 05:30:55 PM PDT 24 Jul 11 05:31:03 PM PDT 24 98952412 ps
T84 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.146220349 Jul 11 05:31:03 PM PDT 24 Jul 11 05:31:31 PM PDT 24 1094387671 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4017922608 Jul 11 05:30:55 PM PDT 24 Jul 11 05:32:04 PM PDT 24 455192667 ps
T374 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.384360355 Jul 11 05:31:05 PM PDT 24 Jul 11 05:31:20 PM PDT 24 790756200 ps
T90 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1024403283 Jul 11 05:30:59 PM PDT 24 Jul 11 05:31:14 PM PDT 24 1759909914 ps
T80 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1215795604 Jul 11 05:31:09 PM PDT 24 Jul 11 05:32:03 PM PDT 24 16929670750 ps
T101 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.938227064 Jul 11 05:31:06 PM PDT 24 Jul 11 05:32:19 PM PDT 24 619446062 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.681980523 Jul 11 05:30:54 PM PDT 24 Jul 11 05:31:01 PM PDT 24 115027423 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2713900999 Jul 11 05:30:56 PM PDT 24 Jul 11 05:31:07 PM PDT 24 2390159863 ps
T377 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1014464661 Jul 11 05:31:20 PM PDT 24 Jul 11 05:31:30 PM PDT 24 1524335256 ps
T378 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.246897708 Jul 11 05:31:16 PM PDT 24 Jul 11 05:31:23 PM PDT 24 88994527 ps
T379 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.359617388 Jul 11 05:31:00 PM PDT 24 Jul 11 05:31:10 PM PDT 24 722909410 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3053034244 Jul 11 05:31:06 PM PDT 24 Jul 11 05:31:18 PM PDT 24 2976347366 ps
T81 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1673993892 Jul 11 05:31:16 PM PDT 24 Jul 11 05:31:23 PM PDT 24 168425320 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.780502424 Jul 11 05:30:46 PM PDT 24 Jul 11 05:30:52 PM PDT 24 175631987 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3870277765 Jul 11 05:30:43 PM PDT 24 Jul 11 05:30:57 PM PDT 24 3942549555 ps
T383 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1726830243 Jul 11 05:31:16 PM PDT 24 Jul 11 05:31:35 PM PDT 24 3833328251 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2662957939 Jul 11 05:30:46 PM PDT 24 Jul 11 05:31:03 PM PDT 24 1874388007 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.339307979 Jul 11 05:30:40 PM PDT 24 Jul 11 05:32:13 PM PDT 24 18044945335 ps
T386 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2114992805 Jul 11 05:31:09 PM PDT 24 Jul 11 05:31:25 PM PDT 24 5366081166 ps
T86 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3239706979 Jul 11 05:31:16 PM PDT 24 Jul 11 05:32:43 PM PDT 24 172674700856 ps
T387 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.31507155 Jul 11 05:31:12 PM PDT 24 Jul 11 05:31:25 PM PDT 24 3614046906 ps
T388 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3824853361 Jul 11 05:31:17 PM PDT 24 Jul 11 05:31:25 PM PDT 24 308589098 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1545839083 Jul 11 05:30:45 PM PDT 24 Jul 11 05:30:59 PM PDT 24 14715401695 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2159684921 Jul 11 05:30:56 PM PDT 24 Jul 11 05:31:04 PM PDT 24 259022586 ps
T391 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3048234715 Jul 11 05:31:20 PM PDT 24 Jul 11 05:31:39 PM PDT 24 1877410748 ps
T392 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.43260955 Jul 11 05:31:14 PM PDT 24 Jul 11 05:31:30 PM PDT 24 1655421710 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4257194459 Jul 11 05:31:07 PM PDT 24 Jul 11 05:31:19 PM PDT 24 4321328232 ps
T394 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2169144687 Jul 11 05:31:10 PM PDT 24 Jul 11 05:31:44 PM PDT 24 2087006981 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4101396770 Jul 11 05:30:58 PM PDT 24 Jul 11 05:31:12 PM PDT 24 17747066753 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2083415704 Jul 11 05:30:49 PM PDT 24 Jul 11 05:31:01 PM PDT 24 6565607561 ps
T107 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3383475562 Jul 11 05:31:01 PM PDT 24 Jul 11 05:32:16 PM PDT 24 19153946424 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2160519092 Jul 11 05:30:54 PM PDT 24 Jul 11 05:31:43 PM PDT 24 4037073916 ps
T398 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1079758230 Jul 11 05:31:03 PM PDT 24 Jul 11 05:31:14 PM PDT 24 4543400956 ps
T399 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3333158500 Jul 11 05:30:57 PM PDT 24 Jul 11 05:31:15 PM PDT 24 1154800525 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3372600174 Jul 11 05:30:57 PM PDT 24 Jul 11 05:31:42 PM PDT 24 2559218811 ps
T401 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1378489900 Jul 11 05:31:11 PM PDT 24 Jul 11 05:31:31 PM PDT 24 3971700434 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3131663020 Jul 11 05:30:55 PM PDT 24 Jul 11 05:31:14 PM PDT 24 8616109624 ps
T403 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2380949771 Jul 11 05:31:15 PM PDT 24 Jul 11 05:31:36 PM PDT 24 2140139939 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3192058105 Jul 11 05:31:12 PM PDT 24 Jul 11 05:31:19 PM PDT 24 308715648 ps
T405 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1077023028 Jul 11 05:31:21 PM PDT 24 Jul 11 05:31:28 PM PDT 24 209284722 ps
T106 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2632435519 Jul 11 05:30:57 PM PDT 24 Jul 11 05:32:07 PM PDT 24 1229760625 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3535495630 Jul 11 05:30:52 PM PDT 24 Jul 11 05:31:05 PM PDT 24 9614896639 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.662586891 Jul 11 05:31:15 PM PDT 24 Jul 11 05:31:30 PM PDT 24 1112614457 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.671583736 Jul 11 05:30:53 PM PDT 24 Jul 11 05:31:03 PM PDT 24 336352326 ps
T87 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1075410084 Jul 11 05:31:21 PM PDT 24 Jul 11 05:31:52 PM PDT 24 700870028 ps
T409 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1006345990 Jul 11 05:31:15 PM PDT 24 Jul 11 05:31:34 PM PDT 24 1907578718 ps
T410 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2274937575 Jul 11 05:31:15 PM PDT 24 Jul 11 05:31:33 PM PDT 24 1684767853 ps
T411 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1106613679 Jul 11 05:31:14 PM PDT 24 Jul 11 05:31:29 PM PDT 24 1562364256 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.819410165 Jul 11 05:31:08 PM PDT 24 Jul 11 05:31:23 PM PDT 24 6150282450 ps
T109 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.747960631 Jul 11 05:30:49 PM PDT 24 Jul 11 05:31:27 PM PDT 24 1504421131 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1141968738 Jul 11 05:30:56 PM PDT 24 Jul 11 05:31:12 PM PDT 24 8587417529 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.582069562 Jul 11 05:31:09 PM PDT 24 Jul 11 05:31:26 PM PDT 24 2086538629 ps
T415 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.378901031 Jul 11 05:31:00 PM PDT 24 Jul 11 05:31:12 PM PDT 24 872307371 ps
T416 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3648837221 Jul 11 05:31:12 PM PDT 24 Jul 11 05:31:33 PM PDT 24 8060458179 ps
T102 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2190458926 Jul 11 05:31:14 PM PDT 24 Jul 11 05:32:04 PM PDT 24 9208802047 ps
T417 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3486811770 Jul 11 05:31:17 PM PDT 24 Jul 11 05:32:00 PM PDT 24 3460424842 ps
T418 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1121538708 Jul 11 05:30:59 PM PDT 24 Jul 11 05:31:09 PM PDT 24 586919626 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4252345134 Jul 11 05:30:47 PM PDT 24 Jul 11 05:30:59 PM PDT 24 6881340908 ps
T420 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1003841961 Jul 11 05:31:00 PM PDT 24 Jul 11 05:31:15 PM PDT 24 1275704920 ps
T421 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2134430636 Jul 11 05:31:04 PM PDT 24 Jul 11 05:31:13 PM PDT 24 1864557143 ps
T422 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2706934360 Jul 11 05:31:27 PM PDT 24 Jul 11 05:31:37 PM PDT 24 1079692565 ps
T423 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1229041819 Jul 11 05:31:27 PM PDT 24 Jul 11 05:31:41 PM PDT 24 20580632986 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.98421851 Jul 11 05:30:46 PM PDT 24 Jul 11 05:30:55 PM PDT 24 178369014 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2582480265 Jul 11 05:30:53 PM PDT 24 Jul 11 05:31:51 PM PDT 24 4522808667 ps
T426 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2255551917 Jul 11 05:31:16 PM PDT 24 Jul 11 05:31:33 PM PDT 24 1694429571 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1220766393 Jul 11 05:30:52 PM PDT 24 Jul 11 05:30:58 PM PDT 24 339885454 ps
T428 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.640503859 Jul 11 05:31:07 PM PDT 24 Jul 11 05:31:20 PM PDT 24 3961274848 ps
T429 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3081986901 Jul 11 05:31:15 PM PDT 24 Jul 11 05:31:25 PM PDT 24 554547504 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3970168456 Jul 11 05:30:50 PM PDT 24 Jul 11 05:30:59 PM PDT 24 450501802 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3607939782 Jul 11 05:30:47 PM PDT 24 Jul 11 05:30:54 PM PDT 24 126903469 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3752822154 Jul 11 05:31:11 PM PDT 24 Jul 11 05:31:25 PM PDT 24 2133588641 ps
T433 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3666828809 Jul 11 05:30:52 PM PDT 24 Jul 11 05:30:57 PM PDT 24 348132038 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2913718467 Jul 11 05:30:56 PM PDT 24 Jul 11 05:31:13 PM PDT 24 3194745406 ps
T434 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4264002757 Jul 11 05:31:27 PM PDT 24 Jul 11 05:31:49 PM PDT 24 8488827896 ps
T435 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.25858956 Jul 11 05:31:12 PM PDT 24 Jul 11 05:31:21 PM PDT 24 378743914 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3196759815 Jul 11 05:30:53 PM PDT 24 Jul 11 05:31:13 PM PDT 24 1988689922 ps
T437 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2349246718 Jul 11 05:30:51 PM PDT 24 Jul 11 05:31:02 PM PDT 24 690802733 ps
T438 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3582861632 Jul 11 05:31:19 PM PDT 24 Jul 11 05:31:27 PM PDT 24 512132497 ps
T439 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1171513599 Jul 11 05:31:05 PM PDT 24 Jul 11 05:31:11 PM PDT 24 90205798 ps
T85 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.310994685 Jul 11 05:31:10 PM PDT 24 Jul 11 05:31:31 PM PDT 24 1513970789 ps
T440 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1630964928 Jul 11 05:31:09 PM PDT 24 Jul 11 05:31:15 PM PDT 24 195880892 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2359239127 Jul 11 05:31:08 PM PDT 24 Jul 11 05:31:17 PM PDT 24 2238266629 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3527322767 Jul 11 05:30:56 PM PDT 24 Jul 11 05:31:08 PM PDT 24 3753455821 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2009897884 Jul 11 05:30:49 PM PDT 24 Jul 11 05:31:03 PM PDT 24 1387471471 ps
T444 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4119677827 Jul 11 05:31:14 PM PDT 24 Jul 11 05:31:23 PM PDT 24 388150983 ps
T445 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2454545802 Jul 11 05:31:17 PM PDT 24 Jul 11 05:33:04 PM PDT 24 13114595308 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1758069551 Jul 11 05:30:53 PM PDT 24 Jul 11 05:31:09 PM PDT 24 1731735552 ps
T108 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.921103021 Jul 11 05:31:12 PM PDT 24 Jul 11 05:32:26 PM PDT 24 412240509 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1661292360 Jul 11 05:30:53 PM PDT 24 Jul 11 05:31:06 PM PDT 24 1286662962 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4231630670 Jul 11 05:31:00 PM PDT 24 Jul 11 05:31:15 PM PDT 24 1489384218 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1755064023 Jul 11 05:30:55 PM PDT 24 Jul 11 05:32:12 PM PDT 24 3012560931 ps
T449 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2238902946 Jul 11 05:31:01 PM PDT 24 Jul 11 05:31:10 PM PDT 24 426715564 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3139643454 Jul 11 05:30:56 PM PDT 24 Jul 11 05:31:04 PM PDT 24 406360313 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3096696801 Jul 11 05:30:47 PM PDT 24 Jul 11 05:31:05 PM PDT 24 2060576872 ps
T452 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3797393544 Jul 11 05:31:00 PM PDT 24 Jul 11 05:31:41 PM PDT 24 1850249873 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3743830744 Jul 11 05:31:08 PM PDT 24 Jul 11 05:31:13 PM PDT 24 172062243 ps
T454 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1233221158 Jul 11 05:31:17 PM PDT 24 Jul 11 05:32:34 PM PDT 24 5061674903 ps
T104 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2024076801 Jul 11 05:31:14 PM PDT 24 Jul 11 05:32:30 PM PDT 24 1016814963 ps
T455 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1844633741 Jul 11 05:31:11 PM PDT 24 Jul 11 05:32:26 PM PDT 24 1560463248 ps
T456 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2113086593 Jul 11 05:31:02 PM PDT 24 Jul 11 05:32:21 PM PDT 24 35561663621 ps
T457 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2862778551 Jul 11 05:30:55 PM PDT 24 Jul 11 05:31:10 PM PDT 24 1605364338 ps
T458 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1599583792 Jul 11 05:31:15 PM PDT 24 Jul 11 05:31:31 PM PDT 24 1268356526 ps
T459 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2605864521 Jul 11 05:30:49 PM PDT 24 Jul 11 05:30:58 PM PDT 24 451679927 ps
T460 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2050183618 Jul 11 05:30:51 PM PDT 24 Jul 11 05:31:01 PM PDT 24 1935712818 ps
T461 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.872458131 Jul 11 05:31:03 PM PDT 24 Jul 11 05:31:22 PM PDT 24 1966430875 ps
T462 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3950032760 Jul 11 05:30:50 PM PDT 24 Jul 11 05:31:04 PM PDT 24 1264418056 ps
T463 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2586110345 Jul 11 05:30:48 PM PDT 24 Jul 11 05:31:08 PM PDT 24 6666897234 ps
T105 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3792110102 Jul 11 05:31:07 PM PDT 24 Jul 11 05:31:46 PM PDT 24 207322699 ps
T464 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2578950232 Jul 11 05:31:15 PM PDT 24 Jul 11 05:31:26 PM PDT 24 1060376393 ps
T465 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1346321820 Jul 11 05:31:01 PM PDT 24 Jul 11 05:32:17 PM PDT 24 2521672574 ps
T466 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.538721958 Jul 11 05:31:08 PM PDT 24 Jul 11 05:32:07 PM PDT 24 7304431160 ps
T467 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2006678717 Jul 11 05:31:06 PM PDT 24 Jul 11 05:31:29 PM PDT 24 8282808125 ps
T82 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2986341813 Jul 11 05:30:48 PM PDT 24 Jul 11 05:31:32 PM PDT 24 2382821295 ps
T468 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3543806906 Jul 11 05:31:14 PM PDT 24 Jul 11 05:32:00 PM PDT 24 1313283223 ps
T469 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2161685203 Jul 11 05:31:14 PM PDT 24 Jul 11 05:31:27 PM PDT 24 4461206950 ps
T83 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3225802127 Jul 11 05:31:16 PM PDT 24 Jul 11 05:31:24 PM PDT 24 497087927 ps

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2242005758
Short name T4
Test name
Test status
Simulation time 52798497598 ps
CPU time 526.11 seconds
Started Jul 11 05:31:50 PM PDT 24
Finished Jul 11 05:40:38 PM PDT 24
Peak memory 235736 kb
Host smart-74323be7-b584-4633-a6e8-6dfd47942a28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242005758 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2242005758
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4148109606
Short name T5
Test name
Test status
Simulation time 5094653026 ps
CPU time 156.52 seconds
Started Jul 11 05:32:54 PM PDT 24
Finished Jul 11 05:35:33 PM PDT 24
Peak memory 212640 kb
Host smart-b9bc596b-f3b5-4294-b9f4-322104a12585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148109606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4148109606
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.938227064
Short name T101
Test name
Test status
Simulation time 619446062 ps
CPU time 71.27 seconds
Started Jul 11 05:31:06 PM PDT 24
Finished Jul 11 05:32:19 PM PDT 24
Peak memory 218908 kb
Host smart-8bdb96e3-c04e-4dd8-b39d-5dd9aeca44a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938227064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.938227064
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.716708670
Short name T3
Test name
Test status
Simulation time 15758669590 ps
CPU time 43.35 seconds
Started Jul 11 05:31:49 PM PDT 24
Finished Jul 11 05:32:33 PM PDT 24
Peak memory 217340 kb
Host smart-f3dc459f-3440-43a7-b6f6-fbfab28ea656
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716708670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.716708670
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3447628054
Short name T18
Test name
Test status
Simulation time 3444384161 ps
CPU time 56.19 seconds
Started Jul 11 05:31:19 PM PDT 24
Finished Jul 11 05:32:18 PM PDT 24
Peak memory 236632 kb
Host smart-adb80f93-3678-4e72-8a1a-b82f6af94f31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447628054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3447628054
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1214653782
Short name T57
Test name
Test status
Simulation time 6582514741 ps
CPU time 55.75 seconds
Started Jul 11 05:30:51 PM PDT 24
Finished Jul 11 05:31:49 PM PDT 24
Peak memory 210672 kb
Host smart-7690d74c-0ffc-4de2-b77f-c2b5bb305b05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214653782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1214653782
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1755064023
Short name T103
Test name
Test status
Simulation time 3012560931 ps
CPU time 75.33 seconds
Started Jul 11 05:30:55 PM PDT 24
Finished Jul 11 05:32:12 PM PDT 24
Peak memory 211172 kb
Host smart-c750eb40-a710-4365-af71-6d79b1f9adb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755064023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1755064023
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.614308378
Short name T35
Test name
Test status
Simulation time 1697509879 ps
CPU time 94.45 seconds
Started Jul 11 05:31:50 PM PDT 24
Finished Jul 11 05:33:25 PM PDT 24
Peak memory 237768 kb
Host smart-917f5738-a8f5-49d4-b1f3-7155cf405509
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614308378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.614308378
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3099827980
Short name T7
Test name
Test status
Simulation time 397503146 ps
CPU time 4.3 seconds
Started Jul 11 05:32:00 PM PDT 24
Finished Jul 11 05:32:06 PM PDT 24
Peak memory 211360 kb
Host smart-ab271b08-c711-49b0-9135-a4d614b26bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099827980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3099827980
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2520610828
Short name T111
Test name
Test status
Simulation time 351087535817 ps
CPU time 6838.81 seconds
Started Jul 11 05:31:44 PM PDT 24
Finished Jul 11 07:25:45 PM PDT 24
Peak memory 232176 kb
Host smart-9acde4c3-6b06-4ccc-9080-5d06ff7cda61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520610828 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2520610828
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2660168413
Short name T22
Test name
Test status
Simulation time 34042481472 ps
CPU time 25.18 seconds
Started Jul 11 05:32:34 PM PDT 24
Finished Jul 11 05:33:02 PM PDT 24
Peak memory 212312 kb
Host smart-afe6a66f-51c1-4179-bf68-3db4f9d2420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660168413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2660168413
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1234968992
Short name T139
Test name
Test status
Simulation time 169000848 ps
CPU time 9.43 seconds
Started Jul 11 05:32:29 PM PDT 24
Finished Jul 11 05:32:41 PM PDT 24
Peak memory 211956 kb
Host smart-10661521-5217-479f-b592-ff4261de77e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234968992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1234968992
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1215795604
Short name T80
Test name
Test status
Simulation time 16929670750 ps
CPU time 53.75 seconds
Started Jul 11 05:31:09 PM PDT 24
Finished Jul 11 05:32:03 PM PDT 24
Peak memory 210676 kb
Host smart-b244544d-ee9e-4cbc-a96a-bc82e47368a6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215795604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1215795604
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3923792576
Short name T47
Test name
Test status
Simulation time 96389256379 ps
CPU time 705.4 seconds
Started Jul 11 05:32:12 PM PDT 24
Finished Jul 11 05:44:00 PM PDT 24
Peak memory 235852 kb
Host smart-872dd5ea-91ba-457f-99d6-c863be2ac757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923792576 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3923792576
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4017922608
Short name T100
Test name
Test status
Simulation time 455192667 ps
CPU time 67.88 seconds
Started Jul 11 05:30:55 PM PDT 24
Finished Jul 11 05:32:04 PM PDT 24
Peak memory 212324 kb
Host smart-914bfeef-7c61-4f01-a42a-7b372fc99439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017922608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4017922608
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1322981017
Short name T52
Test name
Test status
Simulation time 1152188379 ps
CPU time 73.37 seconds
Started Jul 11 05:31:11 PM PDT 24
Finished Jul 11 05:32:27 PM PDT 24
Peak memory 218956 kb
Host smart-c1ea73d5-84db-466f-ba3b-f50709e52ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322981017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1322981017
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1603266789
Short name T370
Test name
Test status
Simulation time 1928361577 ps
CPU time 15.44 seconds
Started Jul 11 05:30:55 PM PDT 24
Finished Jul 11 05:31:12 PM PDT 24
Peak memory 218448 kb
Host smart-1a5c477b-2307-4a47-8586-8dc5e6ea0ac4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603266789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1603266789
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1395824530
Short name T371
Test name
Test status
Simulation time 2811976968 ps
CPU time 8.41 seconds
Started Jul 11 05:30:47 PM PDT 24
Finished Jul 11 05:30:58 PM PDT 24
Peak memory 217540 kb
Host smart-db848d64-9044-4907-bf20-f7b2f65df404
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395824530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1395824530
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.578576053
Short name T373
Test name
Test status
Simulation time 98952412 ps
CPU time 5.96 seconds
Started Jul 11 05:30:55 PM PDT 24
Finished Jul 11 05:31:03 PM PDT 24
Peak memory 210564 kb
Host smart-e94777f9-5285-4b5c-879c-0f774904d817
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578576053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.578576053
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2349246718
Short name T437
Test name
Test status
Simulation time 690802733 ps
CPU time 8.78 seconds
Started Jul 11 05:30:51 PM PDT 24
Finished Jul 11 05:31:02 PM PDT 24
Peak memory 212916 kb
Host smart-fb415f59-45cb-4e67-8017-f000fab365a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349246718 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2349246718
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1290384979
Short name T79
Test name
Test status
Simulation time 2247956500 ps
CPU time 7.95 seconds
Started Jul 11 05:30:47 PM PDT 24
Finished Jul 11 05:30:57 PM PDT 24
Peak memory 218916 kb
Host smart-3e196118-b33d-4379-a5b2-965dfb17282c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290384979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1290384979
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4252345134
Short name T419
Test name
Test status
Simulation time 6881340908 ps
CPU time 9.15 seconds
Started Jul 11 05:30:47 PM PDT 24
Finished Jul 11 05:30:59 PM PDT 24
Peak memory 210568 kb
Host smart-ff7fb340-73de-4c08-a140-59414d5a1e2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252345134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4252345134
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1545839083
Short name T389
Test name
Test status
Simulation time 14715401695 ps
CPU time 12.75 seconds
Started Jul 11 05:30:45 PM PDT 24
Finished Jul 11 05:30:59 PM PDT 24
Peak memory 210608 kb
Host smart-193882d7-779e-4954-a8a0-eed9ec4ef937
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545839083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1545839083
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.339307979
Short name T385
Test name
Test status
Simulation time 18044945335 ps
CPU time 91.59 seconds
Started Jul 11 05:30:40 PM PDT 24
Finished Jul 11 05:32:13 PM PDT 24
Peak memory 210868 kb
Host smart-2767d353-2700-4c80-98ee-450615fbc241
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339307979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.339307979
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3950032760
Short name T462
Test name
Test status
Simulation time 1264418056 ps
CPU time 11.94 seconds
Started Jul 11 05:30:50 PM PDT 24
Finished Jul 11 05:31:04 PM PDT 24
Peak memory 218820 kb
Host smart-83970bca-722a-4972-bbaa-bf68704ee13f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950032760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3950032760
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3870277765
Short name T382
Test name
Test status
Simulation time 3942549555 ps
CPU time 12.35 seconds
Started Jul 11 05:30:43 PM PDT 24
Finished Jul 11 05:30:57 PM PDT 24
Peak memory 219036 kb
Host smart-8db035d0-4b5e-438f-abac-cc083ccf595c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870277765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3870277765
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.747960631
Short name T109
Test name
Test status
Simulation time 1504421131 ps
CPU time 36.16 seconds
Started Jul 11 05:30:49 PM PDT 24
Finished Jul 11 05:31:27 PM PDT 24
Peak memory 210844 kb
Host smart-3de0e325-262a-4d75-8c8d-4cd31e6d935c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747960631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.747960631
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2862778551
Short name T457
Test name
Test status
Simulation time 1605364338 ps
CPU time 13.26 seconds
Started Jul 11 05:30:55 PM PDT 24
Finished Jul 11 05:31:10 PM PDT 24
Peak memory 218528 kb
Host smart-4966e68f-d25b-477e-8892-bb3255ed9f5b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862778551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2862778551
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3245206240
Short name T91
Test name
Test status
Simulation time 1310768361 ps
CPU time 11.57 seconds
Started Jul 11 05:30:57 PM PDT 24
Finished Jul 11 05:31:10 PM PDT 24
Peak memory 210564 kb
Host smart-1ecddb0d-cb75-4533-a109-3b4660482c02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245206240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3245206240
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2913718467
Short name T88
Test name
Test status
Simulation time 3194745406 ps
CPU time 15.22 seconds
Started Jul 11 05:30:56 PM PDT 24
Finished Jul 11 05:31:13 PM PDT 24
Peak memory 218584 kb
Host smart-5f45ede3-d95a-4468-8e3a-1d5d7d95581d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913718467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2913718467
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2050183618
Short name T460
Test name
Test status
Simulation time 1935712818 ps
CPU time 7.94 seconds
Started Jul 11 05:30:51 PM PDT 24
Finished Jul 11 05:31:01 PM PDT 24
Peak memory 218908 kb
Host smart-d09f16c1-5b3c-4c60-8fe3-cd40d99bdf0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050183618 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2050183618
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.634977522
Short name T78
Test name
Test status
Simulation time 783869511 ps
CPU time 8.69 seconds
Started Jul 11 05:30:50 PM PDT 24
Finished Jul 11 05:31:01 PM PDT 24
Peak memory 210576 kb
Host smart-0b5a1ad3-b8c4-4878-9d90-cd93617b125c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634977522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.634977522
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2662957939
Short name T384
Test name
Test status
Simulation time 1874388007 ps
CPU time 14.98 seconds
Started Jul 11 05:30:46 PM PDT 24
Finished Jul 11 05:31:03 PM PDT 24
Peak memory 210536 kb
Host smart-5a5b0870-97ba-4296-a505-53b1191b6f57
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662957939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2662957939
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1220766393
Short name T427
Test name
Test status
Simulation time 339885454 ps
CPU time 5.01 seconds
Started Jul 11 05:30:52 PM PDT 24
Finished Jul 11 05:30:58 PM PDT 24
Peak memory 210588 kb
Host smart-879ebd96-17ef-4f3e-88c1-eb72d8c30edd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220766393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1220766393
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3840266246
Short name T98
Test name
Test status
Simulation time 21969239327 ps
CPU time 75.19 seconds
Started Jul 11 05:30:55 PM PDT 24
Finished Jul 11 05:32:12 PM PDT 24
Peak memory 210632 kb
Host smart-2b47fb78-5649-4d09-a273-db1b91ffe90b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840266246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3840266246
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.780502424
Short name T381
Test name
Test status
Simulation time 175631987 ps
CPU time 4.41 seconds
Started Jul 11 05:30:46 PM PDT 24
Finished Jul 11 05:30:52 PM PDT 24
Peak memory 210780 kb
Host smart-b15eab8f-9c76-4af7-8194-1e9acd508e76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780502424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.780502424
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.98421851
Short name T424
Test name
Test status
Simulation time 178369014 ps
CPU time 6.66 seconds
Started Jul 11 05:30:46 PM PDT 24
Finished Jul 11 05:30:55 PM PDT 24
Peak memory 218852 kb
Host smart-5d8e2e90-779b-426a-be8a-8711ea4bcea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98421851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.98421851
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4257194459
Short name T393
Test name
Test status
Simulation time 4321328232 ps
CPU time 10.68 seconds
Started Jul 11 05:31:07 PM PDT 24
Finished Jul 11 05:31:19 PM PDT 24
Peak memory 218940 kb
Host smart-ae8ce78e-6e53-4cab-8bfb-bd0d77227449
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257194459 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4257194459
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.582069562
Short name T414
Test name
Test status
Simulation time 2086538629 ps
CPU time 15.59 seconds
Started Jul 11 05:31:09 PM PDT 24
Finished Jul 11 05:31:26 PM PDT 24
Peak memory 210636 kb
Host smart-aa76c58f-e9b9-47b7-b3e8-fdcc1e7a17ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582069562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.582069562
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4085923926
Short name T77
Test name
Test status
Simulation time 1536090644 ps
CPU time 26.87 seconds
Started Jul 11 05:31:14 PM PDT 24
Finished Jul 11 05:31:44 PM PDT 24
Peak memory 210720 kb
Host smart-5c21ea8f-1dff-43df-bad9-99374303a5b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085923926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4085923926
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.662586891
Short name T407
Test name
Test status
Simulation time 1112614457 ps
CPU time 12.29 seconds
Started Jul 11 05:31:15 PM PDT 24
Finished Jul 11 05:31:30 PM PDT 24
Peak memory 219152 kb
Host smart-042e87d3-faa5-4399-ac95-9ad7aed7fb77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662586891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.662586891
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.384360355
Short name T374
Test name
Test status
Simulation time 790756200 ps
CPU time 13.18 seconds
Started Jul 11 05:31:05 PM PDT 24
Finished Jul 11 05:31:20 PM PDT 24
Peak memory 218948 kb
Host smart-da99527f-1923-4c6d-9a63-494a6339dfea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384360355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.384360355
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3792110102
Short name T105
Test name
Test status
Simulation time 207322699 ps
CPU time 37.72 seconds
Started Jul 11 05:31:07 PM PDT 24
Finished Jul 11 05:31:46 PM PDT 24
Peak memory 213088 kb
Host smart-97191345-afeb-488a-a582-35100ec62044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792110102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3792110102
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1599583792
Short name T458
Test name
Test status
Simulation time 1268356526 ps
CPU time 12.26 seconds
Started Jul 11 05:31:15 PM PDT 24
Finished Jul 11 05:31:31 PM PDT 24
Peak memory 219020 kb
Host smart-d51d9657-b45e-46c9-9019-8161aa7fc5ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599583792 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1599583792
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2578950232
Short name T464
Test name
Test status
Simulation time 1060376393 ps
CPU time 7.64 seconds
Started Jul 11 05:31:15 PM PDT 24
Finished Jul 11 05:31:26 PM PDT 24
Peak memory 218048 kb
Host smart-428cf3e8-841a-4fd2-b687-05aed0b98c67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578950232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2578950232
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.538721958
Short name T466
Test name
Test status
Simulation time 7304431160 ps
CPU time 57.56 seconds
Started Jul 11 05:31:08 PM PDT 24
Finished Jul 11 05:32:07 PM PDT 24
Peak memory 210684 kb
Host smart-cf1b821d-8a2b-4290-b88f-44890d3f95c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538721958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.538721958
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.246897708
Short name T378
Test name
Test status
Simulation time 88994527 ps
CPU time 4.24 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 05:31:23 PM PDT 24
Peak memory 211024 kb
Host smart-c208bf5c-45d5-4136-9d3a-a295d9d5bcb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246897708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.246897708
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3081986901
Short name T429
Test name
Test status
Simulation time 554547504 ps
CPU time 6.93 seconds
Started Jul 11 05:31:15 PM PDT 24
Finished Jul 11 05:31:25 PM PDT 24
Peak memory 218972 kb
Host smart-28c87ab0-cf7f-45ff-bed5-76e04db0a827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081986901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3081986901
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3543806906
Short name T468
Test name
Test status
Simulation time 1313283223 ps
CPU time 42.81 seconds
Started Jul 11 05:31:14 PM PDT 24
Finished Jul 11 05:32:00 PM PDT 24
Peak memory 212432 kb
Host smart-9dd4d562-ed6b-4e13-bf57-ce5c1f38e9cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543806906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3543806906
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2134430636
Short name T421
Test name
Test status
Simulation time 1864557143 ps
CPU time 8.03 seconds
Started Jul 11 05:31:04 PM PDT 24
Finished Jul 11 05:31:13 PM PDT 24
Peak memory 218928 kb
Host smart-4b58ca42-e2fc-43cf-8e6d-4368b3a7c55e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134430636 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2134430636
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.431653382
Short name T64
Test name
Test status
Simulation time 161671203 ps
CPU time 4.25 seconds
Started Jul 11 05:31:15 PM PDT 24
Finished Jul 11 05:31:22 PM PDT 24
Peak memory 210956 kb
Host smart-382ccae8-12ab-4b8c-8719-764b6b39b05e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431653382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.431653382
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.310994685
Short name T85
Test name
Test status
Simulation time 1513970789 ps
CPU time 19.2 seconds
Started Jul 11 05:31:10 PM PDT 24
Finished Jul 11 05:31:31 PM PDT 24
Peak memory 210728 kb
Host smart-5e8b2839-97c8-4715-9832-ec0ac257f7b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310994685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.310994685
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.640503859
Short name T428
Test name
Test status
Simulation time 3961274848 ps
CPU time 11.96 seconds
Started Jul 11 05:31:07 PM PDT 24
Finished Jul 11 05:31:20 PM PDT 24
Peak memory 218884 kb
Host smart-f2e3ac92-4fcc-4c4b-8884-5b52472cf6d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640503859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.640503859
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2114992805
Short name T386
Test name
Test status
Simulation time 5366081166 ps
CPU time 14.85 seconds
Started Jul 11 05:31:09 PM PDT 24
Finished Jul 11 05:31:25 PM PDT 24
Peak memory 218932 kb
Host smart-ae98b27b-98e9-42ce-899b-c125d2095a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114992805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2114992805
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2190458926
Short name T102
Test name
Test status
Simulation time 9208802047 ps
CPU time 47.46 seconds
Started Jul 11 05:31:14 PM PDT 24
Finished Jul 11 05:32:04 PM PDT 24
Peak memory 218992 kb
Host smart-50e0bef5-a17e-4e68-9163-f8f2cf7f9b47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190458926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2190458926
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1630964928
Short name T440
Test name
Test status
Simulation time 195880892 ps
CPU time 4.85 seconds
Started Jul 11 05:31:09 PM PDT 24
Finished Jul 11 05:31:15 PM PDT 24
Peak memory 218936 kb
Host smart-5803da9a-16c2-4e48-94cb-d9a56af0d26e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630964928 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1630964928
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1673993892
Short name T81
Test name
Test status
Simulation time 168425320 ps
CPU time 4.23 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 05:31:23 PM PDT 24
Peak memory 219096 kb
Host smart-0a59c02a-5c46-4417-8dd6-3952418518c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673993892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1673993892
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2584644757
Short name T56
Test name
Test status
Simulation time 860569775 ps
CPU time 6.01 seconds
Started Jul 11 05:31:05 PM PDT 24
Finished Jul 11 05:31:13 PM PDT 24
Peak memory 218280 kb
Host smart-94f7ac12-520e-441e-a87f-9f20059508a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584644757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2584644757
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2006678717
Short name T467
Test name
Test status
Simulation time 8282808125 ps
CPU time 20.82 seconds
Started Jul 11 05:31:06 PM PDT 24
Finished Jul 11 05:31:29 PM PDT 24
Peak memory 219032 kb
Host smart-88ee7b29-4410-47ea-980c-bfb28ff3edd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006678717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2006678717
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2274937575
Short name T410
Test name
Test status
Simulation time 1684767853 ps
CPU time 14.87 seconds
Started Jul 11 05:31:15 PM PDT 24
Finished Jul 11 05:31:33 PM PDT 24
Peak memory 219008 kb
Host smart-8e9d1e2f-c9b3-4b9a-bec7-8c399dee3582
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274937575 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2274937575
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2161685203
Short name T469
Test name
Test status
Simulation time 4461206950 ps
CPU time 10.53 seconds
Started Jul 11 05:31:14 PM PDT 24
Finished Jul 11 05:31:27 PM PDT 24
Peak memory 218928 kb
Host smart-5471a783-1bb2-4eb1-a493-c7fbb11749c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161685203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2161685203
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2169144687
Short name T394
Test name
Test status
Simulation time 2087006981 ps
CPU time 31.67 seconds
Started Jul 11 05:31:10 PM PDT 24
Finished Jul 11 05:31:44 PM PDT 24
Peak memory 211612 kb
Host smart-ce2e52a8-3d14-4b9b-8697-616d623e79c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169144687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2169144687
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1229041819
Short name T423
Test name
Test status
Simulation time 20580632986 ps
CPU time 12.35 seconds
Started Jul 11 05:31:27 PM PDT 24
Finished Jul 11 05:31:41 PM PDT 24
Peak memory 210868 kb
Host smart-13f5fc94-d3c3-4784-b7bf-5fe7b04206fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229041819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1229041819
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2380949771
Short name T403
Test name
Test status
Simulation time 2140139939 ps
CPU time 18.02 seconds
Started Jul 11 05:31:15 PM PDT 24
Finished Jul 11 05:31:36 PM PDT 24
Peak memory 219192 kb
Host smart-b910b7de-896f-409b-a298-359342552e29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380949771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2380949771
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2024076801
Short name T104
Test name
Test status
Simulation time 1016814963 ps
CPU time 72.71 seconds
Started Jul 11 05:31:14 PM PDT 24
Finished Jul 11 05:32:30 PM PDT 24
Peak memory 218848 kb
Host smart-e77e370d-b6c1-47f9-8abf-d2910c5eba75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024076801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2024076801
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3582861632
Short name T438
Test name
Test status
Simulation time 512132497 ps
CPU time 4.94 seconds
Started Jul 11 05:31:19 PM PDT 24
Finished Jul 11 05:31:27 PM PDT 24
Peak memory 219020 kb
Host smart-3b270d2e-ec7d-43fe-ac4f-b63d0ba5de36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582861632 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3582861632
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4119677827
Short name T444
Test name
Test status
Simulation time 388150983 ps
CPU time 6.4 seconds
Started Jul 11 05:31:14 PM PDT 24
Finished Jul 11 05:31:23 PM PDT 24
Peak memory 210616 kb
Host smart-ad6c0093-fdb6-4051-a318-607c043ca51b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119677827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4119677827
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3239706979
Short name T86
Test name
Test status
Simulation time 172674700856 ps
CPU time 83.75 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 05:32:43 PM PDT 24
Peak memory 210688 kb
Host smart-dbc489a9-905c-4b8a-bffd-9e70eaf0db63
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239706979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3239706979
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1077023028
Short name T405
Test name
Test status
Simulation time 209284722 ps
CPU time 4.45 seconds
Started Jul 11 05:31:21 PM PDT 24
Finished Jul 11 05:31:28 PM PDT 24
Peak memory 210676 kb
Host smart-a5ac2fcc-2bc5-4c55-b0a3-f02317b7e5fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077023028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1077023028
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3817378683
Short name T366
Test name
Test status
Simulation time 1449265175 ps
CPU time 14.03 seconds
Started Jul 11 05:31:27 PM PDT 24
Finished Jul 11 05:31:42 PM PDT 24
Peak memory 218928 kb
Host smart-813d1bfb-2b4a-431e-b903-ad0592e5630f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817378683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3817378683
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.43260955
Short name T392
Test name
Test status
Simulation time 1655421710 ps
CPU time 13.74 seconds
Started Jul 11 05:31:14 PM PDT 24
Finished Jul 11 05:31:30 PM PDT 24
Peak memory 218908 kb
Host smart-bda7f0f0-853a-48b5-bb8c-8b7c3b7b3fbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43260955 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.43260955
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3824853361
Short name T388
Test name
Test status
Simulation time 308589098 ps
CPU time 4.25 seconds
Started Jul 11 05:31:17 PM PDT 24
Finished Jul 11 05:31:25 PM PDT 24
Peak memory 210552 kb
Host smart-9a23c948-45d1-48f8-a309-ccde7dd81eae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824853361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3824853361
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1075410084
Short name T87
Test name
Test status
Simulation time 700870028 ps
CPU time 28.12 seconds
Started Jul 11 05:31:21 PM PDT 24
Finished Jul 11 05:31:52 PM PDT 24
Peak memory 210616 kb
Host smart-540ea2c4-e9b5-47d3-b733-a49390ceea5f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075410084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1075410084
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3858394291
Short name T89
Test name
Test status
Simulation time 2138392713 ps
CPU time 8.04 seconds
Started Jul 11 05:31:12 PM PDT 24
Finished Jul 11 05:31:23 PM PDT 24
Peak memory 210764 kb
Host smart-41c1e7e3-a25c-42b0-af57-d499d35f5828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858394291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3858394291
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1378489900
Short name T401
Test name
Test status
Simulation time 3971700434 ps
CPU time 17.84 seconds
Started Jul 11 05:31:11 PM PDT 24
Finished Jul 11 05:31:31 PM PDT 24
Peak memory 218952 kb
Host smart-76a034bd-c28d-4de0-9f3b-664071fa0e0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378489900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1378489900
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1233221158
Short name T454
Test name
Test status
Simulation time 5061674903 ps
CPU time 73.46 seconds
Started Jul 11 05:31:17 PM PDT 24
Finished Jul 11 05:32:34 PM PDT 24
Peak memory 219024 kb
Host smart-940ef4eb-bf1d-44ca-baff-6471f2afcdc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233221158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1233221158
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1014464661
Short name T377
Test name
Test status
Simulation time 1524335256 ps
CPU time 7.32 seconds
Started Jul 11 05:31:20 PM PDT 24
Finished Jul 11 05:31:30 PM PDT 24
Peak memory 218936 kb
Host smart-e22d53b4-f3e9-4ba5-9f20-29f6d3aed584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014464661 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1014464661
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4158938334
Short name T62
Test name
Test status
Simulation time 2327555458 ps
CPU time 14.82 seconds
Started Jul 11 05:31:14 PM PDT 24
Finished Jul 11 05:31:31 PM PDT 24
Peak memory 210672 kb
Host smart-61bdafe5-c137-4f8c-b386-15ca5c45882a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158938334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4158938334
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4261076846
Short name T60
Test name
Test status
Simulation time 21645951771 ps
CPU time 52.45 seconds
Started Jul 11 05:31:11 PM PDT 24
Finished Jul 11 05:32:05 PM PDT 24
Peak memory 217804 kb
Host smart-ebec03a7-f703-4e3c-b093-c51bb0d3f6eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261076846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4261076846
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3192058105
Short name T404
Test name
Test status
Simulation time 308715648 ps
CPU time 4.41 seconds
Started Jul 11 05:31:12 PM PDT 24
Finished Jul 11 05:31:19 PM PDT 24
Peak memory 218236 kb
Host smart-8f8770b3-9312-4722-ba65-62d095575ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192058105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3192058105
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4264002757
Short name T434
Test name
Test status
Simulation time 8488827896 ps
CPU time 20.22 seconds
Started Jul 11 05:31:27 PM PDT 24
Finished Jul 11 05:31:49 PM PDT 24
Peak memory 218992 kb
Host smart-3869e581-337f-4539-99b5-ea7bd0daa99a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264002757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4264002757
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3973156749
Short name T54
Test name
Test status
Simulation time 553785778 ps
CPU time 35.65 seconds
Started Jul 11 05:31:17 PM PDT 24
Finished Jul 11 05:31:57 PM PDT 24
Peak memory 218912 kb
Host smart-109b68d3-6765-4a1d-8898-19cb4b82db2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973156749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3973156749
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1106613679
Short name T411
Test name
Test status
Simulation time 1562364256 ps
CPU time 12.74 seconds
Started Jul 11 05:31:14 PM PDT 24
Finished Jul 11 05:31:29 PM PDT 24
Peak memory 218828 kb
Host smart-4c4eb146-4086-48f9-962c-38dab20b7be0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106613679 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1106613679
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2255551917
Short name T426
Test name
Test status
Simulation time 1694429571 ps
CPU time 14.12 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 05:31:33 PM PDT 24
Peak memory 218752 kb
Host smart-3431140a-f285-433b-a370-5ebe25016e91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255551917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2255551917
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3486811770
Short name T417
Test name
Test status
Simulation time 3460424842 ps
CPU time 38.62 seconds
Started Jul 11 05:31:17 PM PDT 24
Finished Jul 11 05:32:00 PM PDT 24
Peak memory 210656 kb
Host smart-7b9872ee-a555-49c4-9b50-9f135ba353cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486811770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3486811770
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3648837221
Short name T416
Test name
Test status
Simulation time 8060458179 ps
CPU time 17.83 seconds
Started Jul 11 05:31:12 PM PDT 24
Finished Jul 11 05:31:33 PM PDT 24
Peak memory 218968 kb
Host smart-3e9ad8ea-06a8-4aa4-97d5-1662e2f1d5e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648837221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3648837221
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.25858956
Short name T435
Test name
Test status
Simulation time 378743914 ps
CPU time 6.68 seconds
Started Jul 11 05:31:12 PM PDT 24
Finished Jul 11 05:31:21 PM PDT 24
Peak memory 218876 kb
Host smart-c8678f8d-1c03-4e73-9bdb-8a8dacbd3097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25858956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.25858956
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.921103021
Short name T108
Test name
Test status
Simulation time 412240509 ps
CPU time 71.02 seconds
Started Jul 11 05:31:12 PM PDT 24
Finished Jul 11 05:32:26 PM PDT 24
Peak memory 218956 kb
Host smart-f3f6fd1b-c836-4f98-9c12-1a1e75f94191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921103021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.921103021
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.31507155
Short name T387
Test name
Test status
Simulation time 3614046906 ps
CPU time 9.59 seconds
Started Jul 11 05:31:12 PM PDT 24
Finished Jul 11 05:31:25 PM PDT 24
Peak memory 218892 kb
Host smart-698cd6d4-c48e-4d10-8ce5-ef17735d239c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31507155 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.31507155
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1006345990
Short name T409
Test name
Test status
Simulation time 1907578718 ps
CPU time 15.69 seconds
Started Jul 11 05:31:15 PM PDT 24
Finished Jul 11 05:31:34 PM PDT 24
Peak memory 210616 kb
Host smart-3d714344-1346-4fbb-b905-9a1663fb7cfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006345990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1006345990
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2454545802
Short name T445
Test name
Test status
Simulation time 13114595308 ps
CPU time 103.7 seconds
Started Jul 11 05:31:17 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 210792 kb
Host smart-03d73ace-82f4-4865-8839-eb2116acba1d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454545802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2454545802
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1726830243
Short name T383
Test name
Test status
Simulation time 3833328251 ps
CPU time 15.22 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 05:31:35 PM PDT 24
Peak memory 211132 kb
Host smart-cb78b8ea-f930-46df-8470-012af790aff1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726830243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1726830243
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2706934360
Short name T422
Test name
Test status
Simulation time 1079692565 ps
CPU time 8.13 seconds
Started Jul 11 05:31:27 PM PDT 24
Finished Jul 11 05:31:37 PM PDT 24
Peak memory 215420 kb
Host smart-996d48c3-24e0-4f80-a074-d20679793e93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706934360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2706934360
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1844633741
Short name T455
Test name
Test status
Simulation time 1560463248 ps
CPU time 71.92 seconds
Started Jul 11 05:31:11 PM PDT 24
Finished Jul 11 05:32:26 PM PDT 24
Peak memory 218956 kb
Host smart-be9efa20-e6d4-43f5-805c-9170f1ebb28b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844633741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1844633741
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2605864521
Short name T459
Test name
Test status
Simulation time 451679927 ps
CPU time 6.95 seconds
Started Jul 11 05:30:49 PM PDT 24
Finished Jul 11 05:30:58 PM PDT 24
Peak memory 210576 kb
Host smart-a02d9164-af7c-44d7-a29e-59317dff7d33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605864521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2605864521
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2009897884
Short name T443
Test name
Test status
Simulation time 1387471471 ps
CPU time 12.24 seconds
Started Jul 11 05:30:49 PM PDT 24
Finished Jul 11 05:31:03 PM PDT 24
Peak memory 218232 kb
Host smart-5de4fb66-56d2-44d6-9db9-6b856eb45d1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009897884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2009897884
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3096696801
Short name T451
Test name
Test status
Simulation time 2060576872 ps
CPU time 16.03 seconds
Started Jul 11 05:30:47 PM PDT 24
Finished Jul 11 05:31:05 PM PDT 24
Peak memory 218820 kb
Host smart-57689bd0-01be-4837-b8a5-4ebf6019cbd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096696801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3096696801
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3131663020
Short name T402
Test name
Test status
Simulation time 8616109624 ps
CPU time 17.12 seconds
Started Jul 11 05:30:55 PM PDT 24
Finished Jul 11 05:31:14 PM PDT 24
Peak memory 218856 kb
Host smart-b9cd4e02-45c8-4aca-aef3-7ca44b1a9680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131663020 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3131663020
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3970168456
Short name T430
Test name
Test status
Simulation time 450501802 ps
CPU time 7.25 seconds
Started Jul 11 05:30:50 PM PDT 24
Finished Jul 11 05:30:59 PM PDT 24
Peak memory 217836 kb
Host smart-c0b68ccc-27a1-4d7f-949b-b5d010bc7f40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970168456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3970168456
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1661292360
Short name T447
Test name
Test status
Simulation time 1286662962 ps
CPU time 11.73 seconds
Started Jul 11 05:30:53 PM PDT 24
Finished Jul 11 05:31:06 PM PDT 24
Peak memory 210484 kb
Host smart-49fb5bdb-f105-4f78-8a20-3bbc17654832
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661292360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1661292360
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3535495630
Short name T406
Test name
Test status
Simulation time 9614896639 ps
CPU time 11.5 seconds
Started Jul 11 05:30:52 PM PDT 24
Finished Jul 11 05:31:05 PM PDT 24
Peak memory 210548 kb
Host smart-fb3d7bbc-d6a4-4be7-b02e-124a06114fa1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535495630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3535495630
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3607939782
Short name T431
Test name
Test status
Simulation time 126903469 ps
CPU time 5.26 seconds
Started Jul 11 05:30:47 PM PDT 24
Finished Jul 11 05:30:54 PM PDT 24
Peak memory 210676 kb
Host smart-763b2797-8df1-4fd0-82a0-2c093c6e3bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607939782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3607939782
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2083415704
Short name T396
Test name
Test status
Simulation time 6565607561 ps
CPU time 10.65 seconds
Started Jul 11 05:30:49 PM PDT 24
Finished Jul 11 05:31:01 PM PDT 24
Peak memory 218944 kb
Host smart-d1763e04-e6fa-4d03-bed2-97d8acd1f066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083415704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2083415704
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3139643454
Short name T450
Test name
Test status
Simulation time 406360313 ps
CPU time 6.76 seconds
Started Jul 11 05:30:56 PM PDT 24
Finished Jul 11 05:31:04 PM PDT 24
Peak memory 210660 kb
Host smart-5499d07b-6073-4c2d-8724-246f7e3f45d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139643454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3139643454
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2713900999
Short name T376
Test name
Test status
Simulation time 2390159863 ps
CPU time 9.68 seconds
Started Jul 11 05:30:56 PM PDT 24
Finished Jul 11 05:31:07 PM PDT 24
Peak memory 217488 kb
Host smart-6ae11dd2-6a91-4dcc-b826-9fda7475ac3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713900999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2713900999
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.681980523
Short name T375
Test name
Test status
Simulation time 115027423 ps
CPU time 5.69 seconds
Started Jul 11 05:30:54 PM PDT 24
Finished Jul 11 05:31:01 PM PDT 24
Peak memory 218364 kb
Host smart-b59388f4-5d55-4d19-8e84-907e54d194a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681980523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.681980523
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1141968738
Short name T413
Test name
Test status
Simulation time 8587417529 ps
CPU time 14.19 seconds
Started Jul 11 05:30:56 PM PDT 24
Finished Jul 11 05:31:12 PM PDT 24
Peak memory 218856 kb
Host smart-8f85e0e5-ac1f-4276-b6cc-9243df0bdbf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141968738 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1141968738
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2197291811
Short name T372
Test name
Test status
Simulation time 1128746553 ps
CPU time 10.95 seconds
Started Jul 11 05:31:02 PM PDT 24
Finished Jul 11 05:31:14 PM PDT 24
Peak memory 218676 kb
Host smart-f0da37c8-ce23-445d-b176-c62b0bd1b998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197291811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2197291811
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4101396770
Short name T395
Test name
Test status
Simulation time 17747066753 ps
CPU time 12.27 seconds
Started Jul 11 05:30:58 PM PDT 24
Finished Jul 11 05:31:12 PM PDT 24
Peak memory 210620 kb
Host smart-44f17268-0009-4392-96ea-a33d9299eb96
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101396770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4101396770
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3743830744
Short name T453
Test name
Test status
Simulation time 172062243 ps
CPU time 4.16 seconds
Started Jul 11 05:31:08 PM PDT 24
Finished Jul 11 05:31:13 PM PDT 24
Peak memory 210556 kb
Host smart-51d6bee7-6f39-4acb-8df8-389d970b366c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743830744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3743830744
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2986341813
Short name T82
Test name
Test status
Simulation time 2382821295 ps
CPU time 42.72 seconds
Started Jul 11 05:30:48 PM PDT 24
Finished Jul 11 05:31:32 PM PDT 24
Peak memory 210792 kb
Host smart-6767442e-c7c2-46ac-92dc-32122b76550c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986341813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2986341813
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3527322767
Short name T442
Test name
Test status
Simulation time 3753455821 ps
CPU time 9.94 seconds
Started Jul 11 05:30:56 PM PDT 24
Finished Jul 11 05:31:08 PM PDT 24
Peak memory 218016 kb
Host smart-17b57361-b2ae-465f-8d26-c306c73e2079
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527322767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3527322767
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2586110345
Short name T463
Test name
Test status
Simulation time 6666897234 ps
CPU time 17.61 seconds
Started Jul 11 05:30:48 PM PDT 24
Finished Jul 11 05:31:08 PM PDT 24
Peak memory 218928 kb
Host smart-211fc581-794c-4fb2-a9d3-27d06db5c997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586110345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2586110345
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3372600174
Short name T400
Test name
Test status
Simulation time 2559218811 ps
CPU time 43.74 seconds
Started Jul 11 05:30:57 PM PDT 24
Finished Jul 11 05:31:42 PM PDT 24
Peak memory 211124 kb
Host smart-ac549444-0f19-4ebd-8df9-f395fc1b70eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372600174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3372600174
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1305728140
Short name T66
Test name
Test status
Simulation time 983070937 ps
CPU time 7.28 seconds
Started Jul 11 05:31:05 PM PDT 24
Finished Jul 11 05:31:14 PM PDT 24
Peak memory 217344 kb
Host smart-c3e923eb-ef92-43f4-962d-eb4b973fda0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305728140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1305728140
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.819410165
Short name T412
Test name
Test status
Simulation time 6150282450 ps
CPU time 13.81 seconds
Started Jul 11 05:31:08 PM PDT 24
Finished Jul 11 05:31:23 PM PDT 24
Peak memory 210788 kb
Host smart-8a16a009-73c9-4c56-b5fc-164062f8c605
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819410165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.819410165
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.671583736
Short name T408
Test name
Test status
Simulation time 336352326 ps
CPU time 7.78 seconds
Started Jul 11 05:30:53 PM PDT 24
Finished Jul 11 05:31:03 PM PDT 24
Peak memory 210600 kb
Host smart-0df55231-36f0-42a5-9cb8-d6230afc6027
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671583736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.671583736
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4231630670
Short name T448
Test name
Test status
Simulation time 1489384218 ps
CPU time 13.41 seconds
Started Jul 11 05:31:00 PM PDT 24
Finished Jul 11 05:31:15 PM PDT 24
Peak memory 218992 kb
Host smart-dfdbee03-b474-402d-b30e-b5aa53d85533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231630670 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4231630670
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1758069551
Short name T446
Test name
Test status
Simulation time 1731735552 ps
CPU time 14.38 seconds
Started Jul 11 05:30:53 PM PDT 24
Finished Jul 11 05:31:09 PM PDT 24
Peak memory 210656 kb
Host smart-7704b222-a49b-4bc5-84d6-d0ca2d0dd17c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758069551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1758069551
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2159684921
Short name T390
Test name
Test status
Simulation time 259022586 ps
CPU time 6.14 seconds
Started Jul 11 05:30:56 PM PDT 24
Finished Jul 11 05:31:04 PM PDT 24
Peak memory 210596 kb
Host smart-a841245d-9a6c-466d-b295-493ac7195c48
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159684921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2159684921
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2359239127
Short name T441
Test name
Test status
Simulation time 2238266629 ps
CPU time 7.72 seconds
Started Jul 11 05:31:08 PM PDT 24
Finished Jul 11 05:31:17 PM PDT 24
Peak memory 210652 kb
Host smart-0cc65c87-dd62-4aa0-87de-4891e3a4cf6a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359239127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2359239127
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2582480265
Short name T425
Test name
Test status
Simulation time 4522808667 ps
CPU time 56.46 seconds
Started Jul 11 05:30:53 PM PDT 24
Finished Jul 11 05:31:51 PM PDT 24
Peak memory 218944 kb
Host smart-4ba25179-4cb1-4d97-a1b5-1d897b997e63
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582480265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2582480265
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3053034244
Short name T380
Test name
Test status
Simulation time 2976347366 ps
CPU time 10.55 seconds
Started Jul 11 05:31:06 PM PDT 24
Finished Jul 11 05:31:18 PM PDT 24
Peak memory 218988 kb
Host smart-85fd222f-e7d7-4a06-978a-f64ab724c514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053034244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3053034244
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3196759815
Short name T436
Test name
Test status
Simulation time 1988689922 ps
CPU time 18.95 seconds
Started Jul 11 05:30:53 PM PDT 24
Finished Jul 11 05:31:13 PM PDT 24
Peak memory 218968 kb
Host smart-c840bf15-8ae6-40e2-9171-317093e0c2a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196759815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3196759815
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2160519092
Short name T397
Test name
Test status
Simulation time 4037073916 ps
CPU time 47.61 seconds
Started Jul 11 05:30:54 PM PDT 24
Finished Jul 11 05:31:43 PM PDT 24
Peak memory 212032 kb
Host smart-c7942ec9-f266-4d19-94f2-6f9b4bb379a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160519092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2160519092
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.359617388
Short name T379
Test name
Test status
Simulation time 722909410 ps
CPU time 9.1 seconds
Started Jul 11 05:31:00 PM PDT 24
Finished Jul 11 05:31:10 PM PDT 24
Peak memory 218892 kb
Host smart-a7978d95-8b30-4e62-999b-c2064989d17a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359617388 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.359617388
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3666828809
Short name T433
Test name
Test status
Simulation time 348132038 ps
CPU time 4.07 seconds
Started Jul 11 05:30:52 PM PDT 24
Finished Jul 11 05:30:57 PM PDT 24
Peak memory 217152 kb
Host smart-60898522-6bcd-4045-b85d-ce2e24466901
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666828809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3666828809
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2113086593
Short name T456
Test name
Test status
Simulation time 35561663621 ps
CPU time 77.68 seconds
Started Jul 11 05:31:02 PM PDT 24
Finished Jul 11 05:32:21 PM PDT 24
Peak memory 210724 kb
Host smart-94b80d10-1f31-41ae-87e8-74a5ec57032d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113086593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2113086593
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.269471763
Short name T55
Test name
Test status
Simulation time 1138393628 ps
CPU time 7.95 seconds
Started Jul 11 05:31:02 PM PDT 24
Finished Jul 11 05:31:11 PM PDT 24
Peak memory 210748 kb
Host smart-308a6935-c2ab-43c8-86b4-9019e66a8161
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269471763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.269471763
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3333158500
Short name T399
Test name
Test status
Simulation time 1154800525 ps
CPU time 15.91 seconds
Started Jul 11 05:30:57 PM PDT 24
Finished Jul 11 05:31:15 PM PDT 24
Peak memory 218968 kb
Host smart-ee115352-4858-4dfb-b809-662ebd809322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333158500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3333158500
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2632435519
Short name T106
Test name
Test status
Simulation time 1229760625 ps
CPU time 68.26 seconds
Started Jul 11 05:30:57 PM PDT 24
Finished Jul 11 05:32:07 PM PDT 24
Peak memory 218820 kb
Host smart-56ea3209-e794-48ec-aac8-b446ce3f2d84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632435519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2632435519
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3521358763
Short name T369
Test name
Test status
Simulation time 517934017 ps
CPU time 6.11 seconds
Started Jul 11 05:30:59 PM PDT 24
Finished Jul 11 05:31:06 PM PDT 24
Peak memory 212208 kb
Host smart-ecaaf86e-69d1-4488-930f-d94f3978fee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521358763 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3521358763
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3388204576
Short name T67
Test name
Test status
Simulation time 12091629328 ps
CPU time 15.94 seconds
Started Jul 11 05:31:09 PM PDT 24
Finished Jul 11 05:31:26 PM PDT 24
Peak memory 218912 kb
Host smart-d745fcce-1283-4ae1-a9ae-c902abf0855a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388204576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3388204576
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2435920237
Short name T61
Test name
Test status
Simulation time 9430969001 ps
CPU time 56.7 seconds
Started Jul 11 05:31:02 PM PDT 24
Finished Jul 11 05:32:00 PM PDT 24
Peak memory 210780 kb
Host smart-67c3675c-73aa-458c-8bff-d4661be60ceb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435920237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2435920237
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3048234715
Short name T391
Test name
Test status
Simulation time 1877410748 ps
CPU time 16.21 seconds
Started Jul 11 05:31:20 PM PDT 24
Finished Jul 11 05:31:39 PM PDT 24
Peak memory 218924 kb
Host smart-9031b1f3-ab87-4329-8de6-6c396151acd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048234715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3048234715
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.378901031
Short name T415
Test name
Test status
Simulation time 872307371 ps
CPU time 11.02 seconds
Started Jul 11 05:31:00 PM PDT 24
Finished Jul 11 05:31:12 PM PDT 24
Peak memory 218964 kb
Host smart-aeb9343b-95fa-4245-92eb-7360cd5d27b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378901031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.378901031
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3383475562
Short name T107
Test name
Test status
Simulation time 19153946424 ps
CPU time 73.57 seconds
Started Jul 11 05:31:01 PM PDT 24
Finished Jul 11 05:32:16 PM PDT 24
Peak memory 219024 kb
Host smart-e8cf6f5b-aa57-4df2-9518-91e3deeff550
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383475562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3383475562
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2238902946
Short name T449
Test name
Test status
Simulation time 426715564 ps
CPU time 7.03 seconds
Started Jul 11 05:31:01 PM PDT 24
Finished Jul 11 05:31:10 PM PDT 24
Peak memory 212824 kb
Host smart-afd7af33-a2a8-4f5c-9d58-fee70e142a83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238902946 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2238902946
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3649215447
Short name T65
Test name
Test status
Simulation time 4091064662 ps
CPU time 7.88 seconds
Started Jul 11 05:31:11 PM PDT 24
Finished Jul 11 05:31:22 PM PDT 24
Peak memory 210780 kb
Host smart-98a19a55-8979-404e-a291-e52a22b258d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649215447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3649215447
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4198277047
Short name T76
Test name
Test status
Simulation time 8974105753 ps
CPU time 31.63 seconds
Started Jul 11 05:31:04 PM PDT 24
Finished Jul 11 05:31:36 PM PDT 24
Peak memory 210800 kb
Host smart-5fb2ce4a-8141-45ca-b736-18d8c6767a29
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198277047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.4198277047
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1079758230
Short name T398
Test name
Test status
Simulation time 4543400956 ps
CPU time 9.4 seconds
Started Jul 11 05:31:03 PM PDT 24
Finished Jul 11 05:31:14 PM PDT 24
Peak memory 210956 kb
Host smart-cc8e4df1-9ad9-484c-9651-d220f66d8275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079758230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1079758230
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.872458131
Short name T461
Test name
Test status
Simulation time 1966430875 ps
CPU time 17.54 seconds
Started Jul 11 05:31:03 PM PDT 24
Finished Jul 11 05:31:22 PM PDT 24
Peak memory 218852 kb
Host smart-03349e88-f0b4-4a57-bab5-8936e9c77bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872458131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.872458131
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2725330853
Short name T53
Test name
Test status
Simulation time 4223542987 ps
CPU time 48.27 seconds
Started Jul 11 05:31:05 PM PDT 24
Finished Jul 11 05:31:55 PM PDT 24
Peak memory 210976 kb
Host smart-473cbd9f-d4e3-4975-b5f1-ba4f40a32e91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725330853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2725330853
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3805681265
Short name T367
Test name
Test status
Simulation time 896517196 ps
CPU time 5.56 seconds
Started Jul 11 05:31:03 PM PDT 24
Finished Jul 11 05:31:10 PM PDT 24
Peak memory 218908 kb
Host smart-bdb0651c-c788-4a5e-b94a-8176058d7d86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805681265 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3805681265
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1024403283
Short name T90
Test name
Test status
Simulation time 1759909914 ps
CPU time 13.97 seconds
Started Jul 11 05:30:59 PM PDT 24
Finished Jul 11 05:31:14 PM PDT 24
Peak memory 218576 kb
Host smart-fadfda79-c02f-4eb9-b4c0-f4976f4a2c5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024403283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1024403283
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1296971202
Short name T63
Test name
Test status
Simulation time 1204203494 ps
CPU time 19.04 seconds
Started Jul 11 05:31:00 PM PDT 24
Finished Jul 11 05:31:21 PM PDT 24
Peak memory 210736 kb
Host smart-23bd7b07-382d-42ef-afbf-0f1f48ceb2d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296971202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1296971202
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1121538708
Short name T418
Test name
Test status
Simulation time 586919626 ps
CPU time 8.21 seconds
Started Jul 11 05:30:59 PM PDT 24
Finished Jul 11 05:31:09 PM PDT 24
Peak memory 210764 kb
Host smart-7b961903-20b3-4238-bbe5-a412c439361b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121538708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1121538708
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1003841961
Short name T420
Test name
Test status
Simulation time 1275704920 ps
CPU time 13.51 seconds
Started Jul 11 05:31:00 PM PDT 24
Finished Jul 11 05:31:15 PM PDT 24
Peak memory 218860 kb
Host smart-7a4d7c5c-f718-44d2-b6f3-a1252263739f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003841961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1003841961
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1346321820
Short name T465
Test name
Test status
Simulation time 2521672574 ps
CPU time 74.4 seconds
Started Jul 11 05:31:01 PM PDT 24
Finished Jul 11 05:32:17 PM PDT 24
Peak memory 219024 kb
Host smart-bf6f2723-0b73-43c4-9812-f705c41b76a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346321820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1346321820
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1302062539
Short name T368
Test name
Test status
Simulation time 1820636176 ps
CPU time 13.99 seconds
Started Jul 11 05:31:10 PM PDT 24
Finished Jul 11 05:31:25 PM PDT 24
Peak memory 219012 kb
Host smart-f13e92c7-a474-46d6-a6a7-3cb82c3d9261
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302062539 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1302062539
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3225802127
Short name T83
Test name
Test status
Simulation time 497087927 ps
CPU time 5.03 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 05:31:24 PM PDT 24
Peak memory 217716 kb
Host smart-a7d1a37a-0a2e-4277-9a22-08b9ab043f9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225802127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3225802127
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.146220349
Short name T84
Test name
Test status
Simulation time 1094387671 ps
CPU time 27.14 seconds
Started Jul 11 05:31:03 PM PDT 24
Finished Jul 11 05:31:31 PM PDT 24
Peak memory 210728 kb
Host smart-65c320c9-64e0-4865-a888-270fea280de2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146220349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.146220349
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1171513599
Short name T439
Test name
Test status
Simulation time 90205798 ps
CPU time 4.41 seconds
Started Jul 11 05:31:05 PM PDT 24
Finished Jul 11 05:31:11 PM PDT 24
Peak memory 210720 kb
Host smart-d3133fc6-2a60-4d9c-8b6d-15376b773dc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171513599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1171513599
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3752822154
Short name T432
Test name
Test status
Simulation time 2133588641 ps
CPU time 11.95 seconds
Started Jul 11 05:31:11 PM PDT 24
Finished Jul 11 05:31:25 PM PDT 24
Peak memory 219192 kb
Host smart-4ad02a70-37f3-4e9a-8c44-27071bda1084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752822154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3752822154
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3797393544
Short name T452
Test name
Test status
Simulation time 1850249873 ps
CPU time 39.45 seconds
Started Jul 11 05:31:00 PM PDT 24
Finished Jul 11 05:31:41 PM PDT 24
Peak memory 218936 kb
Host smart-ea270ea7-5c6b-4387-ba2d-b86b9cdfc96f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797393544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3797393544
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1288568678
Short name T342
Test name
Test status
Simulation time 5549575686 ps
CPU time 12.82 seconds
Started Jul 11 05:31:22 PM PDT 24
Finished Jul 11 05:31:37 PM PDT 24
Peak memory 211332 kb
Host smart-81fdc1da-8c92-4bb6-a25a-6eb34ec1996f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288568678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1288568678
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2596364955
Short name T37
Test name
Test status
Simulation time 176460394235 ps
CPU time 429.45 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 05:38:29 PM PDT 24
Peak memory 233756 kb
Host smart-41069af8-fc10-495f-8362-1340dd4a2e7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596364955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2596364955
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3970701189
Short name T162
Test name
Test status
Simulation time 676920655 ps
CPU time 12.04 seconds
Started Jul 11 05:31:24 PM PDT 24
Finished Jul 11 05:31:38 PM PDT 24
Peak memory 211864 kb
Host smart-0a467965-ee61-4ea7-aab4-81ebacbe0413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970701189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3970701189
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3927417497
Short name T232
Test name
Test status
Simulation time 1872079102 ps
CPU time 16.27 seconds
Started Jul 11 05:31:20 PM PDT 24
Finished Jul 11 05:31:40 PM PDT 24
Peak memory 211308 kb
Host smart-2608c2eb-83ae-4dc3-b265-6e7cd100dd93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927417497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3927417497
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.190102409
Short name T16
Test name
Test status
Simulation time 1569630139 ps
CPU time 61.07 seconds
Started Jul 11 05:31:18 PM PDT 24
Finished Jul 11 05:32:22 PM PDT 24
Peak memory 237612 kb
Host smart-473a0e67-95bc-40f9-b246-23c8fc6426ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190102409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.190102409
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1611856863
Short name T359
Test name
Test status
Simulation time 4994984791 ps
CPU time 19.87 seconds
Started Jul 11 05:31:26 PM PDT 24
Finished Jul 11 05:31:48 PM PDT 24
Peak memory 214008 kb
Host smart-a43dec1c-42e2-4535-9d36-f9d80b6e7896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611856863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1611856863
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3236524649
Short name T202
Test name
Test status
Simulation time 2600048675 ps
CPU time 30.13 seconds
Started Jul 11 05:31:19 PM PDT 24
Finished Jul 11 05:31:52 PM PDT 24
Peak memory 213416 kb
Host smart-e286985b-abd2-4986-a689-c8f0796ef1ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236524649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3236524649
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4070518188
Short name T301
Test name
Test status
Simulation time 7052735687 ps
CPU time 15.36 seconds
Started Jul 11 05:31:24 PM PDT 24
Finished Jul 11 05:31:41 PM PDT 24
Peak memory 211276 kb
Host smart-18fab901-ee73-48e3-8bb6-27f23f4218a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070518188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4070518188
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2796976251
Short name T38
Test name
Test status
Simulation time 16555751077 ps
CPU time 197.04 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 05:34:36 PM PDT 24
Peak memory 237836 kb
Host smart-43b89e88-b3df-4d1d-b278-d6642786e0c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796976251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2796976251
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3075396072
Short name T256
Test name
Test status
Simulation time 1208993129 ps
CPU time 17.42 seconds
Started Jul 11 05:31:21 PM PDT 24
Finished Jul 11 05:31:41 PM PDT 24
Peak memory 211788 kb
Host smart-f6a32a24-6662-4d08-8237-82da4de82f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075396072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3075396072
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2004927075
Short name T291
Test name
Test status
Simulation time 1348673609 ps
CPU time 13.11 seconds
Started Jul 11 05:31:19 PM PDT 24
Finished Jul 11 05:31:35 PM PDT 24
Peak memory 211392 kb
Host smart-d496c7c9-4c3f-403b-896e-6a1347e3e6f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004927075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2004927075
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.862463789
Short name T17
Test name
Test status
Simulation time 889843078 ps
CPU time 97.8 seconds
Started Jul 11 05:31:23 PM PDT 24
Finished Jul 11 05:33:03 PM PDT 24
Peak memory 236824 kb
Host smart-31b5e07b-9157-433c-9223-bf220bb52941
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862463789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.862463789
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2983026142
Short name T348
Test name
Test status
Simulation time 702435325 ps
CPU time 10.21 seconds
Started Jul 11 05:31:17 PM PDT 24
Finished Jul 11 05:31:30 PM PDT 24
Peak memory 213556 kb
Host smart-bae27a71-f3bf-4765-8f29-30159fdb692c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983026142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2983026142
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2490240765
Short name T341
Test name
Test status
Simulation time 1761841988 ps
CPU time 15.74 seconds
Started Jul 11 05:31:17 PM PDT 24
Finished Jul 11 05:31:36 PM PDT 24
Peak memory 211404 kb
Host smart-471c9e03-6531-4c5b-9f99-6d28b946cd65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490240765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2490240765
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1439293701
Short name T352
Test name
Test status
Simulation time 33771863228 ps
CPU time 3984.67 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 06:37:45 PM PDT 24
Peak memory 235824 kb
Host smart-95a0a13d-9044-4557-af85-8b339fb7bfc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439293701 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1439293701
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1740803304
Short name T33
Test name
Test status
Simulation time 1675299671 ps
CPU time 13.5 seconds
Started Jul 11 05:31:41 PM PDT 24
Finished Jul 11 05:31:56 PM PDT 24
Peak memory 211216 kb
Host smart-061fa29e-0731-46d1-b276-6003a42030ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740803304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1740803304
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3956381979
Short name T246
Test name
Test status
Simulation time 8078671104 ps
CPU time 139.95 seconds
Started Jul 11 05:31:41 PM PDT 24
Finished Jul 11 05:34:03 PM PDT 24
Peak memory 228644 kb
Host smart-938ae436-eeb8-41ac-9571-1ce76881222b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956381979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3956381979
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.41597563
Short name T253
Test name
Test status
Simulation time 5472154943 ps
CPU time 17.76 seconds
Started Jul 11 05:31:40 PM PDT 24
Finished Jul 11 05:31:59 PM PDT 24
Peak memory 212308 kb
Host smart-e59227ce-6159-40de-838f-73f7e761dbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41597563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.41597563
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1969208775
Short name T131
Test name
Test status
Simulation time 29952570745 ps
CPU time 18.23 seconds
Started Jul 11 05:31:42 PM PDT 24
Finished Jul 11 05:32:02 PM PDT 24
Peak memory 211348 kb
Host smart-b1a99a60-582a-4f8e-bf29-13caf5e12261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969208775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1969208775
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2889159814
Short name T28
Test name
Test status
Simulation time 12031836097 ps
CPU time 32.91 seconds
Started Jul 11 05:31:40 PM PDT 24
Finished Jul 11 05:32:15 PM PDT 24
Peak memory 213852 kb
Host smart-b7916475-b3e1-493a-b3fe-4b960a0e2a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889159814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2889159814
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2351923915
Short name T72
Test name
Test status
Simulation time 8272578696 ps
CPU time 26.07 seconds
Started Jul 11 05:31:49 PM PDT 24
Finished Jul 11 05:32:16 PM PDT 24
Peak memory 214332 kb
Host smart-e99ca9cd-c527-4f23-890d-21cdd773180d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351923915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2351923915
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1537284214
Short name T211
Test name
Test status
Simulation time 1743914216 ps
CPU time 14.43 seconds
Started Jul 11 05:31:48 PM PDT 24
Finished Jul 11 05:32:03 PM PDT 24
Peak memory 211292 kb
Host smart-353536a2-08ab-4a39-a39d-590280713f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537284214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1537284214
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2386668071
Short name T323
Test name
Test status
Simulation time 86824452893 ps
CPU time 306.11 seconds
Started Jul 11 05:31:44 PM PDT 24
Finished Jul 11 05:36:51 PM PDT 24
Peak memory 238888 kb
Host smart-61b0d44a-2ea6-40d6-ad85-6e6cf4882d7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386668071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2386668071
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1986372131
Short name T357
Test name
Test status
Simulation time 730540816 ps
CPU time 9.59 seconds
Started Jul 11 05:31:48 PM PDT 24
Finished Jul 11 05:31:59 PM PDT 24
Peak memory 213972 kb
Host smart-a3c10a0c-58da-4ce1-b94b-c19ee191379e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986372131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1986372131
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1090847478
Short name T216
Test name
Test status
Simulation time 515764754 ps
CPU time 7.46 seconds
Started Jul 11 05:31:40 PM PDT 24
Finished Jul 11 05:31:48 PM PDT 24
Peak memory 211340 kb
Host smart-cb6d1ad6-1bca-4e02-8889-c9d12e5a7c21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090847478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1090847478
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4212196496
Short name T151
Test name
Test status
Simulation time 3869073304 ps
CPU time 31.94 seconds
Started Jul 11 05:31:39 PM PDT 24
Finished Jul 11 05:32:12 PM PDT 24
Peak memory 212924 kb
Host smart-d6a78bd2-397b-4b79-a446-ca41f2b48559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212196496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4212196496
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2310197117
Short name T125
Test name
Test status
Simulation time 13069748173 ps
CPU time 39.23 seconds
Started Jul 11 05:31:43 PM PDT 24
Finished Jul 11 05:32:24 PM PDT 24
Peak memory 219320 kb
Host smart-184fc1ea-65d5-46c0-8d10-a1720b69b0b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310197117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2310197117
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1406287355
Short name T1
Test name
Test status
Simulation time 2483988681 ps
CPU time 8 seconds
Started Jul 11 05:31:51 PM PDT 24
Finished Jul 11 05:32:01 PM PDT 24
Peak memory 210088 kb
Host smart-7c3501d1-6d44-453a-bae0-a415a5023dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406287355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1406287355
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2377058921
Short name T274
Test name
Test status
Simulation time 1509397834 ps
CPU time 9.4 seconds
Started Jul 11 05:31:44 PM PDT 24
Finished Jul 11 05:31:55 PM PDT 24
Peak memory 211932 kb
Host smart-bc3863c7-9557-4ee1-82c2-ebc53ebb0edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377058921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2377058921
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2281244515
Short name T30
Test name
Test status
Simulation time 1325414634 ps
CPU time 13.28 seconds
Started Jul 11 05:31:51 PM PDT 24
Finished Jul 11 05:32:07 PM PDT 24
Peak memory 210196 kb
Host smart-8f47e17d-9524-497e-81c1-04c6134dafde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281244515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2281244515
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1660825048
Short name T240
Test name
Test status
Simulation time 3621726076 ps
CPU time 37.42 seconds
Started Jul 11 05:31:52 PM PDT 24
Finished Jul 11 05:32:32 PM PDT 24
Peak memory 213660 kb
Host smart-543cab03-741e-4868-a06d-65fe121c5078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660825048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1660825048
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3871048503
Short name T325
Test name
Test status
Simulation time 5208329829 ps
CPU time 30.41 seconds
Started Jul 11 05:31:49 PM PDT 24
Finished Jul 11 05:32:21 PM PDT 24
Peak memory 214596 kb
Host smart-a17467a4-cce6-4521-8889-0a908f68e44e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871048503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3871048503
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2963569414
Short name T160
Test name
Test status
Simulation time 87981715 ps
CPU time 4.3 seconds
Started Jul 11 05:31:46 PM PDT 24
Finished Jul 11 05:31:51 PM PDT 24
Peak memory 211260 kb
Host smart-2b88999c-fa51-4929-8c8c-aab8736e9995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963569414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2963569414
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1961708257
Short name T308
Test name
Test status
Simulation time 65506143865 ps
CPU time 180.24 seconds
Started Jul 11 05:31:47 PM PDT 24
Finished Jul 11 05:34:48 PM PDT 24
Peak memory 233724 kb
Host smart-ee950987-3872-46c9-9764-f4708fd30360
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961708257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1961708257
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2159841372
Short name T284
Test name
Test status
Simulation time 8074161132 ps
CPU time 33.89 seconds
Started Jul 11 05:31:46 PM PDT 24
Finished Jul 11 05:32:21 PM PDT 24
Peak memory 212372 kb
Host smart-110a148d-852c-4c49-ad7f-d828a18daf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159841372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2159841372
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3266874875
Short name T303
Test name
Test status
Simulation time 1319931012 ps
CPU time 8.04 seconds
Started Jul 11 05:31:45 PM PDT 24
Finished Jul 11 05:31:55 PM PDT 24
Peak memory 211336 kb
Host smart-a2ff80c7-6027-44e4-91cd-83c171c15e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266874875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3266874875
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3602598091
Short name T326
Test name
Test status
Simulation time 855550129 ps
CPU time 15.94 seconds
Started Jul 11 05:31:54 PM PDT 24
Finished Jul 11 05:32:12 PM PDT 24
Peak memory 212872 kb
Host smart-eee4fa69-3c2e-4ecf-ac0a-a3d12067206e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602598091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3602598091
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2402513525
Short name T13
Test name
Test status
Simulation time 5329645207 ps
CPU time 47.56 seconds
Started Jul 11 05:31:51 PM PDT 24
Finished Jul 11 05:32:41 PM PDT 24
Peak memory 215472 kb
Host smart-c28dcd34-af3c-43c4-aabd-9df636112d47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402513525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2402513525
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1335407536
Short name T118
Test name
Test status
Simulation time 295335362 ps
CPU time 6.27 seconds
Started Jul 11 05:31:54 PM PDT 24
Finished Jul 11 05:32:02 PM PDT 24
Peak memory 211308 kb
Host smart-e7eb0a44-322d-4506-ae7f-f9efc1777ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335407536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1335407536
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.47365655
Short name T184
Test name
Test status
Simulation time 4222793795 ps
CPU time 16.69 seconds
Started Jul 11 05:31:51 PM PDT 24
Finished Jul 11 05:32:09 PM PDT 24
Peak memory 212060 kb
Host smart-9ba6a923-b69e-4260-a0a3-d9bc8e071ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47365655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.47365655
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1817285744
Short name T221
Test name
Test status
Simulation time 7700365292 ps
CPU time 15.41 seconds
Started Jul 11 05:31:51 PM PDT 24
Finished Jul 11 05:32:09 PM PDT 24
Peak memory 211400 kb
Host smart-818ef024-af02-4ca9-b79d-1c36a92916dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817285744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1817285744
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.930851721
Short name T32
Test name
Test status
Simulation time 188300849 ps
CPU time 10.24 seconds
Started Jul 11 05:31:49 PM PDT 24
Finished Jul 11 05:32:00 PM PDT 24
Peak memory 213556 kb
Host smart-78c6f984-fd54-4c6b-992d-ffb3ede9e57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930851721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.930851721
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3947678068
Short name T312
Test name
Test status
Simulation time 11710551651 ps
CPU time 31.42 seconds
Started Jul 11 05:31:46 PM PDT 24
Finished Jul 11 05:32:19 PM PDT 24
Peak memory 213616 kb
Host smart-b1cc8026-30c2-42f4-9cb3-c11c6e9f9a22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947678068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3947678068
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2276754617
Short name T305
Test name
Test status
Simulation time 12332267976 ps
CPU time 16.09 seconds
Started Jul 11 05:31:53 PM PDT 24
Finished Jul 11 05:32:11 PM PDT 24
Peak memory 211304 kb
Host smart-5656b4b5-1cba-4bf0-bfc9-d6369bc048ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276754617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2276754617
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2592966212
Short name T332
Test name
Test status
Simulation time 89302678514 ps
CPU time 199.77 seconds
Started Jul 11 05:31:51 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 237800 kb
Host smart-e71fccf7-1b12-47ae-87a4-5e9afdeeefb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592966212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2592966212
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1231096326
Short name T219
Test name
Test status
Simulation time 333911085 ps
CPU time 9.25 seconds
Started Jul 11 05:31:53 PM PDT 24
Finished Jul 11 05:32:04 PM PDT 24
Peak memory 211912 kb
Host smart-c3238946-38c9-4e57-b39c-781dfca239fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231096326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1231096326
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3883084958
Short name T316
Test name
Test status
Simulation time 2744177571 ps
CPU time 9.58 seconds
Started Jul 11 05:31:50 PM PDT 24
Finished Jul 11 05:32:02 PM PDT 24
Peak memory 211392 kb
Host smart-dedd56d7-e351-4ecd-a2d1-21b9faf66709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883084958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3883084958
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.228411524
Short name T70
Test name
Test status
Simulation time 535725339 ps
CPU time 14.55 seconds
Started Jul 11 05:32:19 PM PDT 24
Finished Jul 11 05:32:35 PM PDT 24
Peak memory 212272 kb
Host smart-b155d211-18ae-4df0-a543-860c80640fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228411524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.228411524
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2646557640
Short name T264
Test name
Test status
Simulation time 4981214442 ps
CPU time 59.85 seconds
Started Jul 11 05:31:51 PM PDT 24
Finished Jul 11 05:32:53 PM PDT 24
Peak memory 213656 kb
Host smart-1cba02d9-6337-400d-9fcc-373a2102ef5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646557640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2646557640
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2768527211
Short name T58
Test name
Test status
Simulation time 348020262 ps
CPU time 4.26 seconds
Started Jul 11 05:31:50 PM PDT 24
Finished Jul 11 05:31:56 PM PDT 24
Peak memory 211276 kb
Host smart-829f6a9f-684a-4b39-910f-f65c9492aba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768527211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2768527211
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2464220623
Short name T239
Test name
Test status
Simulation time 5415902890 ps
CPU time 87.19 seconds
Started Jul 11 05:31:52 PM PDT 24
Finished Jul 11 05:33:22 PM PDT 24
Peak memory 237780 kb
Host smart-1a7330fe-ecfa-4171-b3eb-32d6f16141eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464220623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2464220623
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2096666255
Short name T313
Test name
Test status
Simulation time 3842194471 ps
CPU time 29.64 seconds
Started Jul 11 05:31:52 PM PDT 24
Finished Jul 11 05:32:24 PM PDT 24
Peak memory 211924 kb
Host smart-279e4cfb-f083-4328-a7f3-a74dbcffd5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096666255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2096666255
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1660923124
Short name T193
Test name
Test status
Simulation time 967793589 ps
CPU time 10.4 seconds
Started Jul 11 05:31:55 PM PDT 24
Finished Jul 11 05:32:07 PM PDT 24
Peak memory 211408 kb
Host smart-d1dac6a4-3c98-415f-b15f-d6d8d7147529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1660923124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1660923124
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3045658457
Short name T203
Test name
Test status
Simulation time 32898028007 ps
CPU time 24.42 seconds
Started Jul 11 05:31:51 PM PDT 24
Finished Jul 11 05:32:17 PM PDT 24
Peak memory 214484 kb
Host smart-d4901a9f-fcb8-4bed-a003-ccdc8ca5be43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045658457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3045658457
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1072019477
Short name T302
Test name
Test status
Simulation time 2468441031 ps
CPU time 36.27 seconds
Started Jul 11 05:31:52 PM PDT 24
Finished Jul 11 05:32:30 PM PDT 24
Peak memory 216228 kb
Host smart-7c9416e9-c48f-4f99-9f37-157ca020d713
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072019477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1072019477
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2730381872
Short name T237
Test name
Test status
Simulation time 88991313 ps
CPU time 4.32 seconds
Started Jul 11 05:32:03 PM PDT 24
Finished Jul 11 05:32:10 PM PDT 24
Peak memory 211336 kb
Host smart-ecbbb8ba-00cc-4aa0-946c-901e3a46ac4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730381872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2730381872
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2851290844
Short name T36
Test name
Test status
Simulation time 5798286213 ps
CPU time 110.19 seconds
Started Jul 11 05:31:53 PM PDT 24
Finished Jul 11 05:33:46 PM PDT 24
Peak memory 237792 kb
Host smart-80173007-b908-450f-a2ad-a822121c6084
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851290844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2851290844
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3052602863
Short name T123
Test name
Test status
Simulation time 3155287688 ps
CPU time 27.09 seconds
Started Jul 11 05:31:58 PM PDT 24
Finished Jul 11 05:32:27 PM PDT 24
Peak memory 212352 kb
Host smart-50f6e231-6d41-4be5-bad2-9f03251b3053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052602863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3052602863
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3474548449
Short name T141
Test name
Test status
Simulation time 1605003346 ps
CPU time 14.63 seconds
Started Jul 11 05:31:52 PM PDT 24
Finished Jul 11 05:32:09 PM PDT 24
Peak memory 211288 kb
Host smart-b4484c05-36f9-4af9-8434-20b8f54e4de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474548449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3474548449
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1440126950
Short name T356
Test name
Test status
Simulation time 842263836 ps
CPU time 9.91 seconds
Started Jul 11 05:31:54 PM PDT 24
Finished Jul 11 05:32:05 PM PDT 24
Peak memory 213064 kb
Host smart-ba3d7ba5-61b7-4c58-b6dd-3e4e4a6c0ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440126950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1440126950
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3119151709
Short name T138
Test name
Test status
Simulation time 11740291252 ps
CPU time 21.68 seconds
Started Jul 11 05:31:55 PM PDT 24
Finished Jul 11 05:32:19 PM PDT 24
Peak memory 215044 kb
Host smart-d998adb0-24dc-4ed5-912d-35383141a69a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119151709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3119151709
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1664850629
Short name T99
Test name
Test status
Simulation time 23931143113 ps
CPU time 1004.84 seconds
Started Jul 11 05:31:51 PM PDT 24
Finished Jul 11 05:48:38 PM PDT 24
Peak memory 230280 kb
Host smart-ae59088d-761d-4c45-bccd-6da31f564365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664850629 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1664850629
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3011525743
Short name T117
Test name
Test status
Simulation time 1955234652 ps
CPU time 15.07 seconds
Started Jul 11 05:32:01 PM PDT 24
Finished Jul 11 05:32:18 PM PDT 24
Peak memory 211240 kb
Host smart-70ee5fe7-0445-4682-8681-afd4243bc12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011525743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3011525743
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.418782866
Short name T132
Test name
Test status
Simulation time 6195812664 ps
CPU time 143.15 seconds
Started Jul 11 05:32:02 PM PDT 24
Finished Jul 11 05:34:28 PM PDT 24
Peak memory 236812 kb
Host smart-00e7a5b1-dbf0-4aa3-8110-bf6baa98fa83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418782866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.418782866
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3254344750
Short name T229
Test name
Test status
Simulation time 1320927135 ps
CPU time 14.07 seconds
Started Jul 11 05:31:59 PM PDT 24
Finished Jul 11 05:32:15 PM PDT 24
Peak memory 211992 kb
Host smart-a7b43358-4a35-4576-b753-adfb2716ce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254344750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3254344750
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3999569183
Short name T114
Test name
Test status
Simulation time 743831713 ps
CPU time 7.58 seconds
Started Jul 11 05:31:57 PM PDT 24
Finished Jul 11 05:32:06 PM PDT 24
Peak memory 211368 kb
Host smart-a8ad7121-96f0-46d8-9729-c94f2dd1777e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999569183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3999569183
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2263510699
Short name T74
Test name
Test status
Simulation time 3649812998 ps
CPU time 32.57 seconds
Started Jul 11 05:32:08 PM PDT 24
Finished Jul 11 05:32:44 PM PDT 24
Peak memory 213628 kb
Host smart-92539037-dd8f-4542-8480-b80c745ef621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263510699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2263510699
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1415895721
Short name T110
Test name
Test status
Simulation time 1109008913 ps
CPU time 19.43 seconds
Started Jul 11 05:31:57 PM PDT 24
Finished Jul 11 05:32:18 PM PDT 24
Peak memory 213788 kb
Host smart-c5cf07a4-d020-4154-9fc1-747489e1e022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415895721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1415895721
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3782298115
Short name T248
Test name
Test status
Simulation time 135663550113 ps
CPU time 342.73 seconds
Started Jul 11 05:31:59 PM PDT 24
Finished Jul 11 05:37:44 PM PDT 24
Peak memory 237756 kb
Host smart-e9aa255d-f3f9-4d09-a02b-d089bcd6bd2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782298115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3782298115
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.437584095
Short name T280
Test name
Test status
Simulation time 3017986517 ps
CPU time 19.94 seconds
Started Jul 11 05:31:59 PM PDT 24
Finished Jul 11 05:32:20 PM PDT 24
Peak memory 212076 kb
Host smart-b6d8579e-aebf-454c-a571-bf82a7af420e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437584095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.437584095
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.982593968
Short name T241
Test name
Test status
Simulation time 6136202253 ps
CPU time 14.62 seconds
Started Jul 11 05:32:03 PM PDT 24
Finished Jul 11 05:32:20 PM PDT 24
Peak memory 211440 kb
Host smart-10068395-cd46-43f9-9af8-4b6346fce72c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=982593968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.982593968
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1601110194
Short name T270
Test name
Test status
Simulation time 14010589254 ps
CPU time 29.11 seconds
Started Jul 11 05:32:01 PM PDT 24
Finished Jul 11 05:32:32 PM PDT 24
Peak memory 214224 kb
Host smart-88a1b93b-36ed-4708-b238-e5bba7906fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601110194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1601110194
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2274261589
Short name T42
Test name
Test status
Simulation time 4582834334 ps
CPU time 26.59 seconds
Started Jul 11 05:32:00 PM PDT 24
Finished Jul 11 05:32:28 PM PDT 24
Peak memory 217196 kb
Host smart-60ab500b-4849-47ec-a205-84ea227086a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274261589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2274261589
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.788503979
Short name T242
Test name
Test status
Simulation time 15028079806 ps
CPU time 575.67 seconds
Started Jul 11 05:32:02 PM PDT 24
Finished Jul 11 05:41:39 PM PDT 24
Peak memory 232484 kb
Host smart-91d8ab4b-a648-452b-9444-37a3af06d9a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788503979 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.788503979
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1881972170
Short name T19
Test name
Test status
Simulation time 553284117 ps
CPU time 4.32 seconds
Started Jul 11 05:31:18 PM PDT 24
Finished Jul 11 05:31:26 PM PDT 24
Peak memory 211308 kb
Host smart-fdfba9d7-4d1a-48bb-bbfe-86c661d0b40e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881972170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1881972170
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1549378472
Short name T226
Test name
Test status
Simulation time 262263656913 ps
CPU time 384.15 seconds
Started Jul 11 05:31:19 PM PDT 24
Finished Jul 11 05:37:46 PM PDT 24
Peak memory 228524 kb
Host smart-3092a968-1831-4029-89ec-f68b42bafca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549378472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1549378472
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.715325989
Short name T41
Test name
Test status
Simulation time 1108764243 ps
CPU time 9.68 seconds
Started Jul 11 05:31:18 PM PDT 24
Finished Jul 11 05:31:31 PM PDT 24
Peak memory 211820 kb
Host smart-ffebdaa6-f085-4a8a-91a8-daeb44cd9707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715325989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.715325989
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.767850996
Short name T115
Test name
Test status
Simulation time 1209726028 ps
CPU time 11.74 seconds
Started Jul 11 05:31:20 PM PDT 24
Finished Jul 11 05:31:34 PM PDT 24
Peak memory 211384 kb
Host smart-564359d1-70ba-490f-8eab-729dbac0c6e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767850996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.767850996
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.852585350
Short name T163
Test name
Test status
Simulation time 4027411692 ps
CPU time 32.18 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 05:31:52 PM PDT 24
Peak memory 212948 kb
Host smart-cc572ea7-a78f-427d-a33c-433b17b6f70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852585350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.852585350
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.764382468
Short name T285
Test name
Test status
Simulation time 15536317885 ps
CPU time 38.51 seconds
Started Jul 11 05:31:16 PM PDT 24
Finished Jul 11 05:31:58 PM PDT 24
Peak memory 213996 kb
Host smart-8dce4cf3-bc1a-4408-95a8-0646327d8475
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764382468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.764382468
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4097374084
Short name T135
Test name
Test status
Simulation time 856127863 ps
CPU time 9.69 seconds
Started Jul 11 05:32:04 PM PDT 24
Finished Jul 11 05:32:16 PM PDT 24
Peak memory 211280 kb
Host smart-0a3d8d7e-0164-456b-90e4-95150d39a358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097374084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4097374084
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1701992584
Short name T134
Test name
Test status
Simulation time 32374738034 ps
CPU time 299.59 seconds
Started Jul 11 05:32:09 PM PDT 24
Finished Jul 11 05:37:11 PM PDT 24
Peak memory 236808 kb
Host smart-354c78cb-2860-4c9d-87bc-855bb026be1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701992584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1701992584
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.187939185
Short name T230
Test name
Test status
Simulation time 10386399063 ps
CPU time 25.83 seconds
Started Jul 11 05:32:07 PM PDT 24
Finished Jul 11 05:32:36 PM PDT 24
Peak memory 211408 kb
Host smart-83313d81-82ed-4301-a7aa-26ea160a3f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187939185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.187939185
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3325926154
Short name T224
Test name
Test status
Simulation time 142617380 ps
CPU time 6.06 seconds
Started Jul 11 05:32:06 PM PDT 24
Finished Jul 11 05:32:15 PM PDT 24
Peak memory 211280 kb
Host smart-d27db0e4-5cfc-4e05-9b65-dbf57f5ffe93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325926154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3325926154
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2595431638
Short name T182
Test name
Test status
Simulation time 663465838 ps
CPU time 10.02 seconds
Started Jul 11 05:31:59 PM PDT 24
Finished Jul 11 05:32:11 PM PDT 24
Peak memory 213872 kb
Host smart-0aed4f82-019d-4c78-9733-5471a0595a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595431638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2595431638
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2161778347
Short name T127
Test name
Test status
Simulation time 3983918182 ps
CPU time 31.59 seconds
Started Jul 11 05:32:03 PM PDT 24
Finished Jul 11 05:32:37 PM PDT 24
Peak memory 213736 kb
Host smart-349ee9c5-64b4-40ce-813e-f08a2f03ad09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161778347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2161778347
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3776653282
Short name T50
Test name
Test status
Simulation time 351632302428 ps
CPU time 1930.04 seconds
Started Jul 11 05:32:12 PM PDT 24
Finished Jul 11 06:04:25 PM PDT 24
Peak memory 244020 kb
Host smart-aba030d4-6904-4fba-98f7-3488d1b7bb37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776653282 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3776653282
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.157324496
Short name T113
Test name
Test status
Simulation time 171173993 ps
CPU time 4.47 seconds
Started Jul 11 05:32:07 PM PDT 24
Finished Jul 11 05:32:14 PM PDT 24
Peak memory 211348 kb
Host smart-2f12f383-8abe-44cb-872b-11f2d87713e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157324496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.157324496
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2644185788
Short name T14
Test name
Test status
Simulation time 9330977440 ps
CPU time 149.18 seconds
Started Jul 11 05:32:17 PM PDT 24
Finished Jul 11 05:34:48 PM PDT 24
Peak memory 235008 kb
Host smart-9432e33d-927c-46fe-b364-ae780e4ce1d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644185788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2644185788
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3472614624
Short name T148
Test name
Test status
Simulation time 693744955 ps
CPU time 9.37 seconds
Started Jul 11 05:32:09 PM PDT 24
Finished Jul 11 05:32:21 PM PDT 24
Peak memory 211872 kb
Host smart-0b8a6349-db74-4e86-b25e-32a40d467b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472614624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3472614624
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4145184910
Short name T95
Test name
Test status
Simulation time 8453813339 ps
CPU time 17.9 seconds
Started Jul 11 05:32:07 PM PDT 24
Finished Jul 11 05:32:28 PM PDT 24
Peak memory 211420 kb
Host smart-02a3c8cd-64f9-40bd-99e8-53ebebff2b2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145184910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4145184910
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2987208799
Short name T146
Test name
Test status
Simulation time 710803581 ps
CPU time 10.06 seconds
Started Jul 11 05:32:06 PM PDT 24
Finished Jul 11 05:32:18 PM PDT 24
Peak memory 213156 kb
Host smart-e9e4e469-756c-49c3-8452-565e7005f183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987208799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2987208799
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2500218913
Short name T188
Test name
Test status
Simulation time 5464681018 ps
CPU time 32.36 seconds
Started Jul 11 05:32:11 PM PDT 24
Finished Jul 11 05:32:46 PM PDT 24
Peak memory 216868 kb
Host smart-aa7ca615-b27a-41da-bd49-bb222ccefefc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500218913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2500218913
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3321713970
Short name T334
Test name
Test status
Simulation time 1910570985 ps
CPU time 14.27 seconds
Started Jul 11 05:32:17 PM PDT 24
Finished Jul 11 05:32:33 PM PDT 24
Peak memory 211244 kb
Host smart-a61b5cbe-dc54-46fc-bb2a-1368e5a65a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321713970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3321713970
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4102730219
Short name T365
Test name
Test status
Simulation time 56948961348 ps
CPU time 136.54 seconds
Started Jul 11 05:32:05 PM PDT 24
Finished Jul 11 05:34:25 PM PDT 24
Peak memory 236784 kb
Host smart-39e80b29-821c-4917-8ac5-683a6753d34b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102730219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4102730219
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1245294319
Short name T364
Test name
Test status
Simulation time 18416231034 ps
CPU time 32.12 seconds
Started Jul 11 05:32:07 PM PDT 24
Finished Jul 11 05:32:42 PM PDT 24
Peak memory 212004 kb
Host smart-a0c1ef72-4c23-4a51-bafb-83c39c5a88c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245294319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1245294319
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2371575419
Short name T355
Test name
Test status
Simulation time 1761911114 ps
CPU time 15.47 seconds
Started Jul 11 05:32:14 PM PDT 24
Finished Jul 11 05:32:32 PM PDT 24
Peak memory 211320 kb
Host smart-cd9608db-841f-4fc5-bab0-457e4a5e6907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371575419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2371575419
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.871865491
Short name T92
Test name
Test status
Simulation time 13440753972 ps
CPU time 19.11 seconds
Started Jul 11 05:32:09 PM PDT 24
Finished Jul 11 05:32:31 PM PDT 24
Peak memory 214368 kb
Host smart-4b75a7fa-38a7-42db-a3a1-38362a8bbd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871865491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.871865491
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2939448601
Short name T297
Test name
Test status
Simulation time 7031161386 ps
CPU time 22.1 seconds
Started Jul 11 05:32:11 PM PDT 24
Finished Jul 11 05:32:36 PM PDT 24
Peak memory 214040 kb
Host smart-439b3ca9-a2a2-4ee3-ba5b-07e7e9719c43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939448601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2939448601
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2985170791
Short name T194
Test name
Test status
Simulation time 7954891197 ps
CPU time 16.3 seconds
Started Jul 11 05:32:05 PM PDT 24
Finished Jul 11 05:32:25 PM PDT 24
Peak memory 211296 kb
Host smart-2b413960-972a-445b-9f81-a14a00b88594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985170791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2985170791
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1256285269
Short name T161
Test name
Test status
Simulation time 59173589510 ps
CPU time 197.28 seconds
Started Jul 11 05:32:03 PM PDT 24
Finished Jul 11 05:35:23 PM PDT 24
Peak memory 237896 kb
Host smart-c4a4e804-98ff-419a-9c94-374ed0276eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256285269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1256285269
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2849758077
Short name T31
Test name
Test status
Simulation time 13225255967 ps
CPU time 30.59 seconds
Started Jul 11 05:32:14 PM PDT 24
Finished Jul 11 05:32:47 PM PDT 24
Peak memory 212208 kb
Host smart-ae8e5dac-91b7-48a4-a684-4b21a5c074aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849758077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2849758077
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3239970775
Short name T338
Test name
Test status
Simulation time 42026548949 ps
CPU time 19.16 seconds
Started Jul 11 05:32:06 PM PDT 24
Finished Jul 11 05:32:28 PM PDT 24
Peak memory 211456 kb
Host smart-d64376e5-3628-42d4-906e-5d96dc745c81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239970775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3239970775
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3161067884
Short name T310
Test name
Test status
Simulation time 3743038200 ps
CPU time 26.8 seconds
Started Jul 11 05:32:05 PM PDT 24
Finished Jul 11 05:32:35 PM PDT 24
Peak memory 213172 kb
Host smart-29cfea4d-a5ea-4402-97cf-36e85c645f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161067884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3161067884
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1207252057
Short name T154
Test name
Test status
Simulation time 10650666954 ps
CPU time 26.38 seconds
Started Jul 11 05:32:11 PM PDT 24
Finished Jul 11 05:32:40 PM PDT 24
Peak memory 215108 kb
Host smart-eed9ce5f-6292-408f-beb2-f5cc7ebfe1f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207252057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1207252057
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.683250253
Short name T350
Test name
Test status
Simulation time 468834458 ps
CPU time 7.19 seconds
Started Jul 11 05:32:15 PM PDT 24
Finished Jul 11 05:32:24 PM PDT 24
Peak memory 211308 kb
Host smart-578b2265-4489-4be5-aa79-e1fb55b01132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683250253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.683250253
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4089277837
Short name T228
Test name
Test status
Simulation time 22044544926 ps
CPU time 163.19 seconds
Started Jul 11 05:32:14 PM PDT 24
Finished Jul 11 05:34:59 PM PDT 24
Peak memory 234012 kb
Host smart-19b1dc5f-9bc9-4525-b245-aa20eac41c3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089277837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4089277837
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2396454330
Short name T261
Test name
Test status
Simulation time 170195727 ps
CPU time 9.63 seconds
Started Jul 11 05:32:09 PM PDT 24
Finished Jul 11 05:32:22 PM PDT 24
Peak memory 211868 kb
Host smart-ab40bded-2a50-4a03-81c3-8a99f1cf03eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396454330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2396454330
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.56456632
Short name T287
Test name
Test status
Simulation time 2517731823 ps
CPU time 8.19 seconds
Started Jul 11 05:32:17 PM PDT 24
Finished Jul 11 05:32:27 PM PDT 24
Peak memory 211416 kb
Host smart-af8c847a-1b9a-4c30-b55b-d7b488db0546
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56456632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.56456632
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.732804790
Short name T209
Test name
Test status
Simulation time 41091138755 ps
CPU time 28.96 seconds
Started Jul 11 05:32:11 PM PDT 24
Finished Jul 11 05:32:43 PM PDT 24
Peak memory 214416 kb
Host smart-48ce0b57-a0ec-435e-8fa9-cbcd312d2ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732804790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.732804790
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3259230664
Short name T189
Test name
Test status
Simulation time 11929009602 ps
CPU time 33.44 seconds
Started Jul 11 05:32:09 PM PDT 24
Finished Jul 11 05:32:46 PM PDT 24
Peak memory 215472 kb
Host smart-72a890bb-e9bb-4790-9313-6beabc400367
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259230664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3259230664
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1033385916
Short name T200
Test name
Test status
Simulation time 701307734124 ps
CPU time 4016.9 seconds
Started Jul 11 05:32:06 PM PDT 24
Finished Jul 11 06:39:06 PM PDT 24
Peak memory 246288 kb
Host smart-f3ead315-43e0-4559-a507-8ab7c41f8ca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033385916 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1033385916
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3444994477
Short name T172
Test name
Test status
Simulation time 1142087316 ps
CPU time 11.74 seconds
Started Jul 11 05:32:08 PM PDT 24
Finished Jul 11 05:32:23 PM PDT 24
Peak memory 211304 kb
Host smart-4f70929a-4a8a-4cfe-8d31-9cc361005d33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444994477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3444994477
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3746560935
Short name T10
Test name
Test status
Simulation time 7245918746 ps
CPU time 112.83 seconds
Started Jul 11 05:32:15 PM PDT 24
Finished Jul 11 05:34:10 PM PDT 24
Peak memory 237848 kb
Host smart-680f90fb-63b4-4c0c-a331-03afe4065df1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746560935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3746560935
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3037613808
Short name T289
Test name
Test status
Simulation time 8139902654 ps
CPU time 21.48 seconds
Started Jul 11 05:32:11 PM PDT 24
Finished Jul 11 05:32:35 PM PDT 24
Peak memory 211456 kb
Host smart-e35e4819-6cb3-454a-a6bf-f681f1cadbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037613808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3037613808
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2867053204
Short name T345
Test name
Test status
Simulation time 1215780259 ps
CPU time 12.48 seconds
Started Jul 11 05:32:08 PM PDT 24
Finished Jul 11 05:32:23 PM PDT 24
Peak memory 211356 kb
Host smart-dc071566-0539-4c73-ab78-60bf8b784966
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2867053204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2867053204
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2149706082
Short name T272
Test name
Test status
Simulation time 4471167846 ps
CPU time 25.32 seconds
Started Jul 11 05:32:07 PM PDT 24
Finished Jul 11 05:32:35 PM PDT 24
Peak memory 213820 kb
Host smart-c772fd7b-d02f-42db-9966-b6fc087bbfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149706082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2149706082
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1735585734
Short name T165
Test name
Test status
Simulation time 7769892288 ps
CPU time 67.7 seconds
Started Jul 11 05:32:12 PM PDT 24
Finished Jul 11 05:33:23 PM PDT 24
Peak memory 216440 kb
Host smart-663e4e98-b025-4104-9a1a-4b1a49d87a8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735585734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1735585734
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2730589917
Short name T314
Test name
Test status
Simulation time 1705486977 ps
CPU time 14.11 seconds
Started Jul 11 05:32:08 PM PDT 24
Finished Jul 11 05:32:26 PM PDT 24
Peak memory 211288 kb
Host smart-dd320eaf-0b8c-47f3-9155-8cee98b96f7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730589917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2730589917
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2662420970
Short name T34
Test name
Test status
Simulation time 143848056515 ps
CPU time 245.45 seconds
Started Jul 11 05:32:19 PM PDT 24
Finished Jul 11 05:36:26 PM PDT 24
Peak memory 234276 kb
Host smart-5aabcd8b-c4f6-4219-8536-8698401bbf49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662420970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2662420970
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2222066444
Short name T298
Test name
Test status
Simulation time 11194029309 ps
CPU time 26.23 seconds
Started Jul 11 05:32:11 PM PDT 24
Finished Jul 11 05:32:40 PM PDT 24
Peak memory 212212 kb
Host smart-834cc4ce-4590-4c3b-9876-7aedd396a8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222066444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2222066444
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1969594972
Short name T152
Test name
Test status
Simulation time 21072001242 ps
CPU time 17.01 seconds
Started Jul 11 05:32:14 PM PDT 24
Finished Jul 11 05:32:33 PM PDT 24
Peak memory 211348 kb
Host smart-91bf8bd7-0ef0-4b9c-a951-17cf4e31ffd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969594972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1969594972
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.233772745
Short name T176
Test name
Test status
Simulation time 7444996682 ps
CPU time 33.83 seconds
Started Jul 11 05:32:12 PM PDT 24
Finished Jul 11 05:32:49 PM PDT 24
Peak memory 214800 kb
Host smart-f1ae956d-7ec3-4716-9bd3-9fd93e895f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233772745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.233772745
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.506114223
Short name T210
Test name
Test status
Simulation time 12876247162 ps
CPU time 24.73 seconds
Started Jul 11 05:32:10 PM PDT 24
Finished Jul 11 05:32:38 PM PDT 24
Peak memory 214676 kb
Host smart-708da28c-1244-4dde-aa66-6763545e9347
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506114223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.506114223
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3188590814
Short name T116
Test name
Test status
Simulation time 6048463078 ps
CPU time 14.39 seconds
Started Jul 11 05:32:11 PM PDT 24
Finished Jul 11 05:32:28 PM PDT 24
Peak memory 211312 kb
Host smart-09ba1049-7229-4b90-a11a-5c9b1661ab2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188590814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3188590814
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.700890176
Short name T311
Test name
Test status
Simulation time 32513728840 ps
CPU time 186.22 seconds
Started Jul 11 05:32:13 PM PDT 24
Finished Jul 11 05:35:22 PM PDT 24
Peak memory 236228 kb
Host smart-907e13f7-17e4-4969-a64f-d86f35bc8096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700890176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.700890176
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.794156868
Short name T44
Test name
Test status
Simulation time 978595493 ps
CPU time 15.9 seconds
Started Jul 11 05:32:19 PM PDT 24
Finished Jul 11 05:32:37 PM PDT 24
Peak memory 211880 kb
Host smart-b4c17d32-cf87-425a-b298-33d8690dea52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794156868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.794156868
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3442117276
Short name T156
Test name
Test status
Simulation time 1499174961 ps
CPU time 12.74 seconds
Started Jul 11 05:32:18 PM PDT 24
Finished Jul 11 05:32:32 PM PDT 24
Peak memory 211360 kb
Host smart-5da1e197-d4c5-497a-b822-c2cfc826e993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3442117276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3442117276
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3828877259
Short name T349
Test name
Test status
Simulation time 4193714011 ps
CPU time 36.45 seconds
Started Jul 11 05:32:13 PM PDT 24
Finished Jul 11 05:32:52 PM PDT 24
Peak memory 211936 kb
Host smart-3ce35397-9311-42d4-86d4-8a3f1a3015eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828877259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3828877259
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1760519837
Short name T324
Test name
Test status
Simulation time 29250468595 ps
CPU time 50.84 seconds
Started Jul 11 05:32:15 PM PDT 24
Finished Jul 11 05:33:08 PM PDT 24
Peak memory 216376 kb
Host smart-8f77b35a-fc2e-4c38-854a-82bbf5e530f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760519837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1760519837
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1004523571
Short name T238
Test name
Test status
Simulation time 108853478 ps
CPU time 4.22 seconds
Started Jul 11 05:32:11 PM PDT 24
Finished Jul 11 05:32:18 PM PDT 24
Peak memory 211272 kb
Host smart-252153a8-9151-408b-ae82-f5be68bae058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004523571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1004523571
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4014165631
Short name T294
Test name
Test status
Simulation time 13319951207 ps
CPU time 181.81 seconds
Started Jul 11 05:32:11 PM PDT 24
Finished Jul 11 05:35:16 PM PDT 24
Peak memory 228556 kb
Host smart-9446927e-3c36-432b-8889-df00506500ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014165631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4014165631
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3515297313
Short name T21
Test name
Test status
Simulation time 1382696400 ps
CPU time 9.4 seconds
Started Jul 11 05:32:13 PM PDT 24
Finished Jul 11 05:32:25 PM PDT 24
Peak memory 211996 kb
Host smart-b3c2a783-5beb-4736-886e-2b27c2f5d7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515297313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3515297313
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.287075311
Short name T363
Test name
Test status
Simulation time 176723017 ps
CPU time 6.72 seconds
Started Jul 11 05:32:09 PM PDT 24
Finished Jul 11 05:32:19 PM PDT 24
Peak memory 211356 kb
Host smart-84bd4eca-a6d5-4844-9d42-4a74cf541144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287075311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.287075311
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1055242324
Short name T75
Test name
Test status
Simulation time 360117905 ps
CPU time 10.44 seconds
Started Jul 11 05:32:12 PM PDT 24
Finished Jul 11 05:32:25 PM PDT 24
Peak memory 213616 kb
Host smart-f63260ae-5f72-4e55-8167-9b546e9290df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055242324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1055242324
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3736817632
Short name T43
Test name
Test status
Simulation time 6532622636 ps
CPU time 57.16 seconds
Started Jul 11 05:32:11 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 215384 kb
Host smart-8f94f634-0601-417b-ae69-288f8037ef7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736817632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3736817632
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3037639160
Short name T347
Test name
Test status
Simulation time 88323841 ps
CPU time 4.39 seconds
Started Jul 11 05:32:20 PM PDT 24
Finished Jul 11 05:32:26 PM PDT 24
Peak memory 211344 kb
Host smart-c9a411ef-7d12-46ca-9021-a07c330e0711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037639160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3037639160
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2351890085
Short name T126
Test name
Test status
Simulation time 62258333809 ps
CPU time 89.41 seconds
Started Jul 11 05:32:22 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 236856 kb
Host smart-1d0c9848-442e-439e-ad39-8f38ce93648e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351890085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2351890085
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1911305659
Short name T268
Test name
Test status
Simulation time 7629574265 ps
CPU time 21.7 seconds
Started Jul 11 05:32:21 PM PDT 24
Finished Jul 11 05:32:44 PM PDT 24
Peak memory 212524 kb
Host smart-6c78f40d-2515-4a0f-8a99-94e6dd0f31a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911305659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1911305659
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1773300326
Short name T276
Test name
Test status
Simulation time 1554488316 ps
CPU time 8.84 seconds
Started Jul 11 05:32:22 PM PDT 24
Finished Jul 11 05:32:33 PM PDT 24
Peak memory 211408 kb
Host smart-daa48bac-331e-43e0-996e-7326964b4e12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773300326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1773300326
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1468751725
Short name T278
Test name
Test status
Simulation time 1648728524 ps
CPU time 19.86 seconds
Started Jul 11 05:32:22 PM PDT 24
Finished Jul 11 05:32:43 PM PDT 24
Peak memory 212836 kb
Host smart-7bad3e54-1f6a-487a-923c-d3e496d9c4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468751725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1468751725
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1787771270
Short name T223
Test name
Test status
Simulation time 5786033565 ps
CPU time 65.82 seconds
Started Jul 11 05:32:20 PM PDT 24
Finished Jul 11 05:33:28 PM PDT 24
Peak memory 216584 kb
Host smart-b526d743-a664-4e3d-8519-316dccdedf51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787771270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1787771270
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3209043067
Short name T26
Test name
Test status
Simulation time 34750904112 ps
CPU time 2339.19 seconds
Started Jul 11 05:32:19 PM PDT 24
Finished Jul 11 06:11:20 PM PDT 24
Peak memory 235788 kb
Host smart-202e7dd2-d8e9-4e37-990d-82f71a719da9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209043067 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3209043067
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3028552778
Short name T271
Test name
Test status
Simulation time 397576496 ps
CPU time 4.28 seconds
Started Jul 11 05:31:25 PM PDT 24
Finished Jul 11 05:31:31 PM PDT 24
Peak memory 211344 kb
Host smart-4fdbb49e-22ce-4d0b-93ed-e210c2abe78b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028552778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3028552778
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3283625845
Short name T257
Test name
Test status
Simulation time 4510003509 ps
CPU time 114.98 seconds
Started Jul 11 05:31:22 PM PDT 24
Finished Jul 11 05:33:20 PM PDT 24
Peak memory 225476 kb
Host smart-b8a0fe6b-74bf-4be7-b1e7-428d4da3576e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283625845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3283625845
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3416231425
Short name T327
Test name
Test status
Simulation time 334832962 ps
CPU time 9.33 seconds
Started Jul 11 05:31:23 PM PDT 24
Finished Jul 11 05:31:35 PM PDT 24
Peak memory 212032 kb
Host smart-ac7d4fcf-9fb0-4e67-9eb6-46aba8b8d87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416231425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3416231425
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2712061421
Short name T192
Test name
Test status
Simulation time 96721625 ps
CPU time 5.61 seconds
Started Jul 11 05:31:26 PM PDT 24
Finished Jul 11 05:31:34 PM PDT 24
Peak memory 211356 kb
Host smart-5eda1835-97a3-4842-add9-de57d444ec33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712061421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2712061421
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1893241196
Short name T24
Test name
Test status
Simulation time 1464183045 ps
CPU time 103.78 seconds
Started Jul 11 05:31:25 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 237920 kb
Host smart-ca4bc368-d348-410b-b7db-45e12173fba5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893241196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1893241196
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.462698115
Short name T128
Test name
Test status
Simulation time 319162170 ps
CPU time 10.04 seconds
Started Jul 11 05:31:20 PM PDT 24
Finished Jul 11 05:31:33 PM PDT 24
Peak memory 213276 kb
Host smart-327ec33c-d9f3-4ee2-aa94-5e3d335c33a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462698115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.462698115
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1003207739
Short name T306
Test name
Test status
Simulation time 8350689955 ps
CPU time 35.77 seconds
Started Jul 11 05:31:17 PM PDT 24
Finished Jul 11 05:31:56 PM PDT 24
Peak memory 214724 kb
Host smart-77a81c3d-deeb-414a-8fe5-8432f6e0b4b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003207739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1003207739
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.414055757
Short name T164
Test name
Test status
Simulation time 8188411171 ps
CPU time 15.3 seconds
Started Jul 11 05:32:26 PM PDT 24
Finished Jul 11 05:32:44 PM PDT 24
Peak memory 211368 kb
Host smart-5dbaa1e3-320e-4aee-ac60-d1862bb19d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414055757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.414055757
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3511919506
Short name T320
Test name
Test status
Simulation time 46785955186 ps
CPU time 250.66 seconds
Started Jul 11 05:32:27 PM PDT 24
Finished Jul 11 05:36:41 PM PDT 24
Peak memory 237872 kb
Host smart-30da934f-d55e-497f-90f3-4450eec135f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511919506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3511919506
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.637515683
Short name T142
Test name
Test status
Simulation time 349814699 ps
CPU time 9.37 seconds
Started Jul 11 05:32:21 PM PDT 24
Finished Jul 11 05:32:32 PM PDT 24
Peak memory 211744 kb
Host smart-b274b82a-09e9-4aea-bed8-e9f5bbceafe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637515683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.637515683
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3891610434
Short name T183
Test name
Test status
Simulation time 3725126701 ps
CPU time 15.5 seconds
Started Jul 11 05:32:22 PM PDT 24
Finished Jul 11 05:32:39 PM PDT 24
Peak memory 211468 kb
Host smart-5c4080e7-7e1c-4a17-a573-efa57b354039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891610434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3891610434
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3648114153
Short name T155
Test name
Test status
Simulation time 4233071494 ps
CPU time 24.98 seconds
Started Jul 11 05:32:21 PM PDT 24
Finished Jul 11 05:32:48 PM PDT 24
Peak memory 212804 kb
Host smart-480660e7-56ef-4bd7-8a87-9cc355a54782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648114153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3648114153
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.653327453
Short name T227
Test name
Test status
Simulation time 650571892 ps
CPU time 15.05 seconds
Started Jul 11 05:32:20 PM PDT 24
Finished Jul 11 05:32:37 PM PDT 24
Peak memory 213912 kb
Host smart-3488ba25-b1fe-41b6-8105-c5616fd38681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653327453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.653327453
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2009926726
Short name T27
Test name
Test status
Simulation time 6700797936 ps
CPU time 8.78 seconds
Started Jul 11 05:32:22 PM PDT 24
Finished Jul 11 05:32:32 PM PDT 24
Peak memory 211300 kb
Host smart-5fe50669-f9d6-4ec7-9b62-d969c76a272a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009926726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2009926726
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1505135408
Short name T244
Test name
Test status
Simulation time 38911343780 ps
CPU time 180.81 seconds
Started Jul 11 05:32:23 PM PDT 24
Finished Jul 11 05:35:25 PM PDT 24
Peak memory 237880 kb
Host smart-169d65b4-cab8-4baf-a310-873944dcef36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505135408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1505135408
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4037972709
Short name T215
Test name
Test status
Simulation time 193058912 ps
CPU time 5.38 seconds
Started Jul 11 05:32:21 PM PDT 24
Finished Jul 11 05:32:28 PM PDT 24
Peak memory 211244 kb
Host smart-cc314c1c-56bb-4d16-98d9-28c5ed04f7fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037972709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4037972709
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.67282583
Short name T71
Test name
Test status
Simulation time 696314414 ps
CPU time 10.35 seconds
Started Jul 11 05:32:24 PM PDT 24
Finished Jul 11 05:32:37 PM PDT 24
Peak memory 213476 kb
Host smart-0251ee15-6edc-4a5c-bf05-16a3451307f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67282583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.67282583
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2322658256
Short name T346
Test name
Test status
Simulation time 196287220 ps
CPU time 10.8 seconds
Started Jul 11 05:32:24 PM PDT 24
Finished Jul 11 05:32:38 PM PDT 24
Peak memory 215192 kb
Host smart-34c52acb-9b92-4d31-b830-ff8438a8e4b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322658256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2322658256
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2750861268
Short name T153
Test name
Test status
Simulation time 6775877044 ps
CPU time 14.49 seconds
Started Jul 11 05:32:25 PM PDT 24
Finished Jul 11 05:32:42 PM PDT 24
Peak memory 211332 kb
Host smart-f7f4ef8c-dbb3-491e-804f-6c88cb674d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750861268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2750861268
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2790522688
Short name T169
Test name
Test status
Simulation time 2368142357 ps
CPU time 147.46 seconds
Started Jul 11 05:32:34 PM PDT 24
Finished Jul 11 05:35:04 PM PDT 24
Peak memory 237824 kb
Host smart-40039f07-5735-4154-b499-7035defe8ded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790522688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2790522688
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.556705207
Short name T179
Test name
Test status
Simulation time 3805020998 ps
CPU time 31.67 seconds
Started Jul 11 05:32:24 PM PDT 24
Finished Jul 11 05:32:59 PM PDT 24
Peak memory 211912 kb
Host smart-3fb923db-88d6-4aae-b4fe-ae6dcc007d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556705207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.556705207
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2517539407
Short name T96
Test name
Test status
Simulation time 3462353874 ps
CPU time 10.87 seconds
Started Jul 11 05:32:34 PM PDT 24
Finished Jul 11 05:32:48 PM PDT 24
Peak memory 211384 kb
Host smart-31236737-648a-4d15-9a03-59c365ceff2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517539407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2517539407
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2114458590
Short name T159
Test name
Test status
Simulation time 4016158701 ps
CPU time 18.05 seconds
Started Jul 11 05:32:22 PM PDT 24
Finished Jul 11 05:32:42 PM PDT 24
Peak memory 213812 kb
Host smart-c82d4445-6822-4c9c-aabb-a222d0d0d2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114458590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2114458590
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1948742557
Short name T94
Test name
Test status
Simulation time 208845687 ps
CPU time 12.33 seconds
Started Jul 11 05:32:26 PM PDT 24
Finished Jul 11 05:32:41 PM PDT 24
Peak memory 214892 kb
Host smart-76053d91-4fbc-4765-bcda-65d5559a08f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948742557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1948742557
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2259640559
Short name T49
Test name
Test status
Simulation time 261312500890 ps
CPU time 9938.53 seconds
Started Jul 11 05:32:25 PM PDT 24
Finished Jul 11 08:18:08 PM PDT 24
Peak memory 231316 kb
Host smart-bbcf9c03-0705-4672-b2b7-1e646ad7a547
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259640559 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2259640559
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1450373532
Short name T286
Test name
Test status
Simulation time 86228306 ps
CPU time 4.33 seconds
Started Jul 11 05:32:32 PM PDT 24
Finished Jul 11 05:32:38 PM PDT 24
Peak memory 211312 kb
Host smart-ab680751-0e44-4719-96d6-c520b6750b19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450373532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1450373532
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2138934540
Short name T9
Test name
Test status
Simulation time 9514536183 ps
CPU time 82.36 seconds
Started Jul 11 05:32:29 PM PDT 24
Finished Jul 11 05:33:54 PM PDT 24
Peak memory 237868 kb
Host smart-bce4c23a-dc5c-405e-b8ee-455e5948d0de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138934540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2138934540
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2155358044
Short name T206
Test name
Test status
Simulation time 12780657665 ps
CPU time 29.12 seconds
Started Jul 11 05:32:34 PM PDT 24
Finished Jul 11 05:33:06 PM PDT 24
Peak memory 212220 kb
Host smart-f8ab0347-de30-4161-a971-383d86adbe51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155358044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2155358044
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1317308949
Short name T191
Test name
Test status
Simulation time 236088537 ps
CPU time 5.76 seconds
Started Jul 11 05:32:23 PM PDT 24
Finished Jul 11 05:32:30 PM PDT 24
Peak memory 211388 kb
Host smart-77094b30-d493-4690-ab0a-ec8c10b703bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317308949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1317308949
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2156714986
Short name T136
Test name
Test status
Simulation time 5787064174 ps
CPU time 40.39 seconds
Started Jul 11 05:32:27 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 213972 kb
Host smart-f5e63a40-386e-47fe-8e90-05a37edc185e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156714986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2156714986
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3145486885
Short name T262
Test name
Test status
Simulation time 1677597404 ps
CPU time 21.28 seconds
Started Jul 11 05:32:29 PM PDT 24
Finished Jul 11 05:32:53 PM PDT 24
Peak memory 211248 kb
Host smart-028a85d9-9af1-4797-9cff-7d55954faaf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145486885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3145486885
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2931291660
Short name T124
Test name
Test status
Simulation time 13753440179 ps
CPU time 13.2 seconds
Started Jul 11 05:32:29 PM PDT 24
Finished Jul 11 05:32:45 PM PDT 24
Peak memory 211384 kb
Host smart-dda1f2c4-12e3-4428-ab88-7d2fcc1d11be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931291660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2931291660
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3405249800
Short name T213
Test name
Test status
Simulation time 33895616949 ps
CPU time 374.76 seconds
Started Jul 11 05:32:22 PM PDT 24
Finished Jul 11 05:38:38 PM PDT 24
Peak memory 212604 kb
Host smart-83b6980a-7973-4183-9554-984d4defef2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405249800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3405249800
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1633390798
Short name T147
Test name
Test status
Simulation time 4065477384 ps
CPU time 34.19 seconds
Started Jul 11 05:32:32 PM PDT 24
Finished Jul 11 05:33:08 PM PDT 24
Peak memory 211876 kb
Host smart-57aaf2f7-33ec-4468-98cf-4c7947400d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633390798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1633390798
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4096067851
Short name T340
Test name
Test status
Simulation time 99384550 ps
CPU time 5.39 seconds
Started Jul 11 05:32:22 PM PDT 24
Finished Jul 11 05:32:29 PM PDT 24
Peak memory 211288 kb
Host smart-146f0c78-f8c9-46e9-b263-cb31ae9224c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4096067851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4096067851
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4166940837
Short name T6
Test name
Test status
Simulation time 747021746 ps
CPU time 10.4 seconds
Started Jul 11 05:32:25 PM PDT 24
Finished Jul 11 05:32:38 PM PDT 24
Peak memory 213332 kb
Host smart-784ad333-b7a6-4e72-a0cd-fcd57e3b93a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166940837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4166940837
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3484763550
Short name T214
Test name
Test status
Simulation time 30842265971 ps
CPU time 64.98 seconds
Started Jul 11 05:32:29 PM PDT 24
Finished Jul 11 05:33:36 PM PDT 24
Peak memory 219392 kb
Host smart-5f36ad4f-709d-48d0-a77e-7b280b747fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484763550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3484763550
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2546699245
Short name T247
Test name
Test status
Simulation time 2774402142 ps
CPU time 8.14 seconds
Started Jul 11 05:32:33 PM PDT 24
Finished Jul 11 05:32:44 PM PDT 24
Peak memory 211404 kb
Host smart-b0995732-d243-4ba8-ae66-d9ce4ef509f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546699245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2546699245
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.868896210
Short name T39
Test name
Test status
Simulation time 147624623022 ps
CPU time 302.08 seconds
Started Jul 11 05:32:28 PM PDT 24
Finished Jul 11 05:37:33 PM PDT 24
Peak memory 237772 kb
Host smart-59dc18c6-2d3c-43e9-a705-290c2a18efeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868896210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.868896210
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.490053071
Short name T233
Test name
Test status
Simulation time 7730067079 ps
CPU time 33.45 seconds
Started Jul 11 05:32:28 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 212544 kb
Host smart-25620875-85f3-44eb-a24d-ac95e2f40913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490053071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.490053071
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.535427576
Short name T273
Test name
Test status
Simulation time 189776265 ps
CPU time 5.69 seconds
Started Jul 11 05:32:31 PM PDT 24
Finished Jul 11 05:32:39 PM PDT 24
Peak memory 211260 kb
Host smart-83b6a4cd-0c3a-43d9-87a9-792d0fc6a464
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535427576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.535427576
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.704689656
Short name T343
Test name
Test status
Simulation time 11245702308 ps
CPU time 26.55 seconds
Started Jul 11 05:32:32 PM PDT 24
Finished Jul 11 05:33:00 PM PDT 24
Peak memory 214580 kb
Host smart-553b68b8-6c40-4b39-ba18-dfd661585b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704689656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.704689656
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3237730861
Short name T205
Test name
Test status
Simulation time 1383640044 ps
CPU time 29.19 seconds
Started Jul 11 05:32:29 PM PDT 24
Finished Jul 11 05:33:01 PM PDT 24
Peak memory 215148 kb
Host smart-7b2a4f38-4c19-44a5-95ab-25743339be34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237730861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3237730861
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2638165269
Short name T175
Test name
Test status
Simulation time 2001711013 ps
CPU time 14.76 seconds
Started Jul 11 05:32:29 PM PDT 24
Finished Jul 11 05:32:46 PM PDT 24
Peak memory 211228 kb
Host smart-b9613f52-ff5f-44eb-a1c5-e24091436947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638165269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2638165269
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2597103753
Short name T351
Test name
Test status
Simulation time 3104561502 ps
CPU time 76.21 seconds
Started Jul 11 05:32:32 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 212604 kb
Host smart-7442673a-4083-412f-abb1-a9066f54d736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597103753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2597103753
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3840901127
Short name T254
Test name
Test status
Simulation time 11698317504 ps
CPU time 27.65 seconds
Started Jul 11 05:32:33 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 212384 kb
Host smart-d2332856-53cd-4202-9376-0cd3bd846b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840901127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3840901127
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2184301528
Short name T279
Test name
Test status
Simulation time 360006185 ps
CPU time 5.34 seconds
Started Jul 11 05:32:27 PM PDT 24
Finished Jul 11 05:32:36 PM PDT 24
Peak memory 211336 kb
Host smart-69eef9c8-589e-478b-9bcf-130d9340bd80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184301528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2184301528
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.307042871
Short name T140
Test name
Test status
Simulation time 3351989114 ps
CPU time 29.97 seconds
Started Jul 11 05:32:33 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 213256 kb
Host smart-fb96b6aa-92c6-44ed-a78b-483fea75e202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307042871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.307042871
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2124768489
Short name T196
Test name
Test status
Simulation time 6356847957 ps
CPU time 16.73 seconds
Started Jul 11 05:32:28 PM PDT 24
Finished Jul 11 05:32:47 PM PDT 24
Peak memory 212696 kb
Host smart-f13416e9-3d6b-4a4b-84f5-6f4eaca4d8dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124768489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2124768489
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1036768333
Short name T51
Test name
Test status
Simulation time 139251579844 ps
CPU time 5183.15 seconds
Started Jul 11 05:32:26 PM PDT 24
Finished Jul 11 06:58:52 PM PDT 24
Peak memory 233540 kb
Host smart-75218838-4a2b-4618-832e-6fa603dee1af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036768333 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1036768333
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2239783956
Short name T121
Test name
Test status
Simulation time 387710485 ps
CPU time 6.84 seconds
Started Jul 11 05:32:35 PM PDT 24
Finished Jul 11 05:32:45 PM PDT 24
Peak memory 211312 kb
Host smart-5223775a-1bd3-433e-8153-130088b43752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239783956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2239783956
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1999171227
Short name T321
Test name
Test status
Simulation time 4612865519 ps
CPU time 87.98 seconds
Started Jul 11 05:32:34 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 238792 kb
Host smart-36d6d76d-a4ee-4049-b8be-512b10a8f346
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999171227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1999171227
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3763262808
Short name T137
Test name
Test status
Simulation time 175527084 ps
CPU time 9.69 seconds
Started Jul 11 05:32:35 PM PDT 24
Finished Jul 11 05:32:48 PM PDT 24
Peak memory 211836 kb
Host smart-4e75299d-3837-4c60-9716-d1e155a5a32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763262808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3763262808
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3425582795
Short name T93
Test name
Test status
Simulation time 1134338204 ps
CPU time 11.9 seconds
Started Jul 11 05:32:33 PM PDT 24
Finished Jul 11 05:32:47 PM PDT 24
Peak memory 211408 kb
Host smart-91f617fb-2540-475e-8345-89c08ca1d15b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425582795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3425582795
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1326903880
Short name T337
Test name
Test status
Simulation time 8844564646 ps
CPU time 25.81 seconds
Started Jul 11 05:32:29 PM PDT 24
Finished Jul 11 05:32:58 PM PDT 24
Peak memory 213900 kb
Host smart-b6f6baf8-99ea-4e41-a043-436b55daedd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326903880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1326903880
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1508766631
Short name T73
Test name
Test status
Simulation time 4981638445 ps
CPU time 53.32 seconds
Started Jul 11 05:32:32 PM PDT 24
Finished Jul 11 05:33:28 PM PDT 24
Peak memory 216460 kb
Host smart-abf9d9e0-c21c-4f9c-8f40-b0929b1db24e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508766631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1508766631
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3123050927
Short name T290
Test name
Test status
Simulation time 86481797 ps
CPU time 4.37 seconds
Started Jul 11 05:32:35 PM PDT 24
Finished Jul 11 05:32:42 PM PDT 24
Peak memory 211196 kb
Host smart-a9738071-04de-4654-83a3-b16dcbc4e1f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123050927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3123050927
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3596360726
Short name T259
Test name
Test status
Simulation time 34300546194 ps
CPU time 181.12 seconds
Started Jul 11 05:32:34 PM PDT 24
Finished Jul 11 05:35:38 PM PDT 24
Peak memory 225076 kb
Host smart-662858a7-7425-4e6b-804d-3447997dc0b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596360726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3596360726
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1295956898
Short name T180
Test name
Test status
Simulation time 1029108989 ps
CPU time 11.56 seconds
Started Jul 11 05:32:35 PM PDT 24
Finished Jul 11 05:32:50 PM PDT 24
Peak memory 211396 kb
Host smart-90acbe19-9490-4e23-b72e-0fe941831649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295956898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1295956898
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3851786361
Short name T353
Test name
Test status
Simulation time 751399947 ps
CPU time 10.2 seconds
Started Jul 11 05:32:33 PM PDT 24
Finished Jul 11 05:32:45 PM PDT 24
Peak memory 214028 kb
Host smart-a5838811-c978-44b2-8c96-fe9d447b039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851786361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3851786361
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.889468964
Short name T339
Test name
Test status
Simulation time 55809379103 ps
CPU time 107.87 seconds
Started Jul 11 05:32:34 PM PDT 24
Finished Jul 11 05:34:24 PM PDT 24
Peak memory 217716 kb
Host smart-b0d6484d-e091-46f1-9518-a7de7721c6fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889468964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.889468964
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3968091336
Short name T319
Test name
Test status
Simulation time 23841115436 ps
CPU time 4113.63 seconds
Started Jul 11 05:32:33 PM PDT 24
Finished Jul 11 06:41:10 PM PDT 24
Peak memory 235216 kb
Host smart-766e8b8b-be39-4c87-8895-33e854bf6e73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968091336 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3968091336
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.712787940
Short name T266
Test name
Test status
Simulation time 1849234384 ps
CPU time 10.06 seconds
Started Jul 11 05:32:34 PM PDT 24
Finished Jul 11 05:32:46 PM PDT 24
Peak memory 211288 kb
Host smart-7aac6d7f-765e-45da-ac36-65643783421e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712787940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.712787940
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.569424849
Short name T174
Test name
Test status
Simulation time 2441721960 ps
CPU time 79.76 seconds
Started Jul 11 05:32:39 PM PDT 24
Finished Jul 11 05:34:00 PM PDT 24
Peak memory 237796 kb
Host smart-e6f67bfb-86f6-482a-8fa6-73e7842ca227
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569424849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.569424849
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.683889170
Short name T119
Test name
Test status
Simulation time 414323246 ps
CPU time 12.86 seconds
Started Jul 11 05:32:36 PM PDT 24
Finished Jul 11 05:32:51 PM PDT 24
Peak memory 212048 kb
Host smart-224a2963-1711-444c-b4c5-0c99db477a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683889170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.683889170
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.274812118
Short name T333
Test name
Test status
Simulation time 151690304 ps
CPU time 5.13 seconds
Started Jul 11 05:32:34 PM PDT 24
Finished Jul 11 05:32:42 PM PDT 24
Peak memory 211356 kb
Host smart-87679dcb-6579-481a-87d5-fadcd0538162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=274812118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.274812118
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.961577656
Short name T282
Test name
Test status
Simulation time 2028897096 ps
CPU time 13.57 seconds
Started Jul 11 05:32:38 PM PDT 24
Finished Jul 11 05:32:53 PM PDT 24
Peak memory 213088 kb
Host smart-bffdd461-d2cd-41b1-b01b-51d5046c223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961577656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.961577656
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4191875500
Short name T263
Test name
Test status
Simulation time 9411806886 ps
CPU time 31.17 seconds
Started Jul 11 05:32:34 PM PDT 24
Finished Jul 11 05:33:08 PM PDT 24
Peak memory 215284 kb
Host smart-b2e7ea51-c398-4098-a6d3-a346552fae44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191875500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4191875500
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2968653762
Short name T129
Test name
Test status
Simulation time 168417385 ps
CPU time 4.33 seconds
Started Jul 11 05:31:35 PM PDT 24
Finished Jul 11 05:31:42 PM PDT 24
Peak memory 211308 kb
Host smart-088d97a8-86ac-46bb-a3f0-0229c2572093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968653762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2968653762
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1260969783
Short name T167
Test name
Test status
Simulation time 23145257697 ps
CPU time 255.84 seconds
Started Jul 11 05:31:23 PM PDT 24
Finished Jul 11 05:35:41 PM PDT 24
Peak memory 233756 kb
Host smart-015decce-b841-481e-95fa-f44811b02d75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260969783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1260969783
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3976050556
Short name T295
Test name
Test status
Simulation time 3665107254 ps
CPU time 18.17 seconds
Started Jul 11 05:31:24 PM PDT 24
Finished Jul 11 05:31:44 PM PDT 24
Peak memory 211876 kb
Host smart-71191886-a8fa-4386-89c5-25e7fefa43fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976050556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3976050556
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3397509889
Short name T157
Test name
Test status
Simulation time 97931735 ps
CPU time 5.61 seconds
Started Jul 11 05:31:25 PM PDT 24
Finished Jul 11 05:31:32 PM PDT 24
Peak memory 211284 kb
Host smart-acc09e62-1281-43ae-947e-f6f6be6ef338
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397509889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3397509889
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.886091909
Short name T23
Test name
Test status
Simulation time 1064932524 ps
CPU time 101.58 seconds
Started Jul 11 05:31:30 PM PDT 24
Finished Jul 11 05:33:14 PM PDT 24
Peak memory 235964 kb
Host smart-43d13747-f517-4477-8fd3-eaf6b723cc93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886091909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.886091909
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1107043405
Short name T207
Test name
Test status
Simulation time 16117361193 ps
CPU time 33.02 seconds
Started Jul 11 05:31:25 PM PDT 24
Finished Jul 11 05:31:59 PM PDT 24
Peak memory 214268 kb
Host smart-2f19263e-d2f3-49ff-9c56-38dfbd077782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107043405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1107043405
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1466028432
Short name T220
Test name
Test status
Simulation time 2609118785 ps
CPU time 32.41 seconds
Started Jul 11 05:31:24 PM PDT 24
Finished Jul 11 05:31:58 PM PDT 24
Peak memory 214280 kb
Host smart-2a49e164-15b3-4c4a-9abd-f791ed8912b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466028432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1466028432
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1468965416
Short name T201
Test name
Test status
Simulation time 3270107180 ps
CPU time 9.1 seconds
Started Jul 11 05:32:40 PM PDT 24
Finished Jul 11 05:32:50 PM PDT 24
Peak memory 211408 kb
Host smart-adeb7237-5fc6-4710-a673-45e3e90d24cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468965416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1468965416
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3401422776
Short name T331
Test name
Test status
Simulation time 40735484980 ps
CPU time 128.53 seconds
Started Jul 11 05:32:44 PM PDT 24
Finished Jul 11 05:34:56 PM PDT 24
Peak memory 237300 kb
Host smart-79fcb442-5c6f-4a84-9bde-73d9531d8002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401422776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3401422776
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.378830541
Short name T288
Test name
Test status
Simulation time 2748139667 ps
CPU time 13.66 seconds
Started Jul 11 05:32:43 PM PDT 24
Finished Jul 11 05:32:59 PM PDT 24
Peak memory 212072 kb
Host smart-efe16e3a-a99c-40c9-8dfc-12fb05000431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378830541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.378830541
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.848098070
Short name T25
Test name
Test status
Simulation time 893775925 ps
CPU time 6.95 seconds
Started Jul 11 05:32:40 PM PDT 24
Finished Jul 11 05:32:48 PM PDT 24
Peak memory 211392 kb
Host smart-51e342f1-7bb3-4c0d-9acd-43c4121eca93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=848098070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.848098070
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2212539587
Short name T187
Test name
Test status
Simulation time 7217985429 ps
CPU time 29.95 seconds
Started Jul 11 05:32:35 PM PDT 24
Finished Jul 11 05:33:08 PM PDT 24
Peak memory 212504 kb
Host smart-a85b2bdd-083e-4254-91f1-4cd07855816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212539587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2212539587
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1242954034
Short name T69
Test name
Test status
Simulation time 36304496893 ps
CPU time 56.9 seconds
Started Jul 11 05:32:41 PM PDT 24
Finished Jul 11 05:33:40 PM PDT 24
Peak memory 214296 kb
Host smart-aa8d9249-a381-4eac-a1cd-3b9fd828fd26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242954034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1242954034
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.414748937
Short name T296
Test name
Test status
Simulation time 167990685775 ps
CPU time 1634.72 seconds
Started Jul 11 05:32:46 PM PDT 24
Finished Jul 11 06:00:05 PM PDT 24
Peak memory 235816 kb
Host smart-0227b9f3-2d51-415a-b65f-179d5ee4fb61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414748937 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.414748937
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.108070289
Short name T144
Test name
Test status
Simulation time 11913062008 ps
CPU time 14.89 seconds
Started Jul 11 05:32:43 PM PDT 24
Finished Jul 11 05:33:00 PM PDT 24
Peak memory 211404 kb
Host smart-66ff72a0-a732-4566-bb05-3e2eb0132fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108070289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.108070289
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1783897049
Short name T317
Test name
Test status
Simulation time 36847221495 ps
CPU time 181.37 seconds
Started Jul 11 05:32:45 PM PDT 24
Finished Jul 11 05:35:50 PM PDT 24
Peak memory 233196 kb
Host smart-5363eb68-76f0-4a6c-8f2e-f9936684209c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783897049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1783897049
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.379702656
Short name T197
Test name
Test status
Simulation time 839690180 ps
CPU time 14.92 seconds
Started Jul 11 05:32:41 PM PDT 24
Finished Jul 11 05:32:58 PM PDT 24
Peak memory 212300 kb
Host smart-7a079dc1-a305-4e1c-a006-4e1ae50132c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379702656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.379702656
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2160956932
Short name T243
Test name
Test status
Simulation time 3861038530 ps
CPU time 11.35 seconds
Started Jul 11 05:32:43 PM PDT 24
Finished Jul 11 05:32:57 PM PDT 24
Peak memory 211432 kb
Host smart-87db843e-1d9b-46ed-bc08-edbadf868d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2160956932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2160956932
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1352494219
Short name T145
Test name
Test status
Simulation time 727981280 ps
CPU time 9.74 seconds
Started Jul 11 05:32:42 PM PDT 24
Finished Jul 11 05:32:54 PM PDT 24
Peak memory 213612 kb
Host smart-5aa2a7d6-1fcf-4ea8-85b7-7515defdef76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352494219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1352494219
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1204788462
Short name T158
Test name
Test status
Simulation time 6508817848 ps
CPU time 19.15 seconds
Started Jul 11 05:32:42 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 211292 kb
Host smart-83d7ac0d-5f62-4ad1-a752-27e073d0d759
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204788462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1204788462
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1013517580
Short name T12
Test name
Test status
Simulation time 561574121739 ps
CPU time 2178.97 seconds
Started Jul 11 05:32:41 PM PDT 24
Finished Jul 11 06:09:03 PM PDT 24
Peak memory 238548 kb
Host smart-212ccb03-ea8d-46ee-a65a-fb5f045fbb4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013517580 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1013517580
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3492044310
Short name T130
Test name
Test status
Simulation time 3924360419 ps
CPU time 9.82 seconds
Started Jul 11 05:32:42 PM PDT 24
Finished Jul 11 05:32:54 PM PDT 24
Peak memory 211320 kb
Host smart-e9fedd40-b0af-4369-b031-b4fa09e947a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492044310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3492044310
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.564970976
Short name T292
Test name
Test status
Simulation time 61656680809 ps
CPU time 176.81 seconds
Started Jul 11 05:32:39 PM PDT 24
Finished Jul 11 05:35:37 PM PDT 24
Peak memory 212584 kb
Host smart-e11f1e9a-9175-4e90-a746-f906f50da395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564970976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.564970976
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1853297445
Short name T231
Test name
Test status
Simulation time 3094457671 ps
CPU time 26.44 seconds
Started Jul 11 05:32:46 PM PDT 24
Finished Jul 11 05:33:16 PM PDT 24
Peak memory 212024 kb
Host smart-d898f8af-3b46-479a-810b-c90b353d9783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853297445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1853297445
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2632062096
Short name T181
Test name
Test status
Simulation time 2129459281 ps
CPU time 17.14 seconds
Started Jul 11 05:32:40 PM PDT 24
Finished Jul 11 05:32:59 PM PDT 24
Peak memory 211336 kb
Host smart-17b321de-3165-4ae2-8143-096377722a12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632062096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2632062096
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1160866387
Short name T275
Test name
Test status
Simulation time 2242623469 ps
CPU time 25.91 seconds
Started Jul 11 05:32:41 PM PDT 24
Finished Jul 11 05:33:09 PM PDT 24
Peak memory 213092 kb
Host smart-2ca7a721-cddb-40da-8cda-992b59f4f94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160866387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1160866387
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.491379162
Short name T168
Test name
Test status
Simulation time 31465516611 ps
CPU time 33.79 seconds
Started Jul 11 05:32:42 PM PDT 24
Finished Jul 11 05:33:18 PM PDT 24
Peak memory 215116 kb
Host smart-390e8803-bc74-4331-8190-98092b4e188d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491379162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.491379162
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.595942933
Short name T304
Test name
Test status
Simulation time 1254626036 ps
CPU time 6.18 seconds
Started Jul 11 05:32:46 PM PDT 24
Finished Jul 11 05:32:57 PM PDT 24
Peak memory 211332 kb
Host smart-582cb22a-7bf5-4f50-bc65-f3c6a743716e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595942933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.595942933
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1877798533
Short name T267
Test name
Test status
Simulation time 7844989895 ps
CPU time 104.78 seconds
Started Jul 11 05:32:44 PM PDT 24
Finished Jul 11 05:34:31 PM PDT 24
Peak memory 237820 kb
Host smart-6bb10f89-3cca-4457-92b4-adcbc73061c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877798533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1877798533
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1664866740
Short name T149
Test name
Test status
Simulation time 596142972 ps
CPU time 9.6 seconds
Started Jul 11 05:32:41 PM PDT 24
Finished Jul 11 05:32:52 PM PDT 24
Peak memory 212312 kb
Host smart-b0c6c08c-2627-4e01-a3c3-c290b6e0770d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664866740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1664866740
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2322038575
Short name T2
Test name
Test status
Simulation time 14125608032 ps
CPU time 16.18 seconds
Started Jul 11 05:32:42 PM PDT 24
Finished Jul 11 05:33:00 PM PDT 24
Peak memory 211372 kb
Host smart-869cd21d-436c-47c2-8a26-bcd2fd87570b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322038575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2322038575
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.227551735
Short name T249
Test name
Test status
Simulation time 3020174351 ps
CPU time 15.91 seconds
Started Jul 11 05:32:40 PM PDT 24
Finished Jul 11 05:32:57 PM PDT 24
Peak memory 213820 kb
Host smart-ea7eb03d-50fb-4471-89fa-de025a4d781d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227551735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.227551735
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.614225709
Short name T318
Test name
Test status
Simulation time 111454131768 ps
CPU time 60.71 seconds
Started Jul 11 05:32:44 PM PDT 24
Finished Jul 11 05:33:47 PM PDT 24
Peak memory 214672 kb
Host smart-7cfad0f9-5306-4edc-8020-a0d748a72230
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614225709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.614225709
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1549801558
Short name T245
Test name
Test status
Simulation time 1806821963 ps
CPU time 10.77 seconds
Started Jul 11 05:32:46 PM PDT 24
Finished Jul 11 05:33:01 PM PDT 24
Peak memory 211240 kb
Host smart-ff5f1721-162e-4af3-841c-ca8878a97c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549801558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1549801558
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2381482344
Short name T143
Test name
Test status
Simulation time 35612128527 ps
CPU time 199.29 seconds
Started Jul 11 05:32:55 PM PDT 24
Finished Jul 11 05:36:17 PM PDT 24
Peak memory 237528 kb
Host smart-0748c383-a66d-4c8d-ab06-190288988f0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381482344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2381482344
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2857366899
Short name T45
Test name
Test status
Simulation time 6224629854 ps
CPU time 18.45 seconds
Started Jul 11 05:32:46 PM PDT 24
Finished Jul 11 05:33:08 PM PDT 24
Peak memory 212888 kb
Host smart-2c1b59fc-042e-4cd2-ab38-3d67897882b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857366899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2857366899
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.146208434
Short name T120
Test name
Test status
Simulation time 2175214219 ps
CPU time 16.27 seconds
Started Jul 11 05:32:55 PM PDT 24
Finished Jul 11 05:33:14 PM PDT 24
Peak memory 211568 kb
Host smart-63e2ff48-f6c4-4365-9262-929452e12b32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146208434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.146208434
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2695167047
Short name T208
Test name
Test status
Simulation time 10011764609 ps
CPU time 24.02 seconds
Started Jul 11 05:32:47 PM PDT 24
Finished Jul 11 05:33:14 PM PDT 24
Peak memory 215284 kb
Host smart-0e2c7f24-a132-4a37-82d2-81c7a10074c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695167047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2695167047
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1985485772
Short name T217
Test name
Test status
Simulation time 2957111539 ps
CPU time 33.46 seconds
Started Jul 11 05:32:50 PM PDT 24
Finished Jul 11 05:33:27 PM PDT 24
Peak memory 212612 kb
Host smart-9dfff062-7de1-4caa-b9ab-b58318556524
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985485772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1985485772
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2447362063
Short name T336
Test name
Test status
Simulation time 414975209 ps
CPU time 4.18 seconds
Started Jul 11 05:32:55 PM PDT 24
Finished Jul 11 05:33:02 PM PDT 24
Peak memory 211324 kb
Host smart-8e9a0bd1-cb84-4db8-928a-ac230ec0df08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447362063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2447362063
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.740607459
Short name T235
Test name
Test status
Simulation time 4316086098 ps
CPU time 117.19 seconds
Started Jul 11 05:32:55 PM PDT 24
Finished Jul 11 05:34:55 PM PDT 24
Peak memory 238032 kb
Host smart-94782c4c-9d00-430a-ad08-496d09b046af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740607459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.740607459
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3511869871
Short name T170
Test name
Test status
Simulation time 4447048285 ps
CPU time 33.92 seconds
Started Jul 11 05:32:47 PM PDT 24
Finished Jul 11 05:33:24 PM PDT 24
Peak memory 212144 kb
Host smart-a38bec98-45d3-41ee-8018-05da5bcc029a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511869871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3511869871
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1751569430
Short name T335
Test name
Test status
Simulation time 95905129 ps
CPU time 5.38 seconds
Started Jul 11 05:32:52 PM PDT 24
Finished Jul 11 05:33:00 PM PDT 24
Peak memory 211360 kb
Host smart-3be9da72-74d3-4406-b6c1-02140ac5f9ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751569430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1751569430
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4181471301
Short name T8
Test name
Test status
Simulation time 7406983954 ps
CPU time 30.47 seconds
Started Jul 11 05:32:47 PM PDT 24
Finished Jul 11 05:33:21 PM PDT 24
Peak memory 214072 kb
Host smart-665d5460-11a3-4164-a08e-b2d0aa5dcdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181471301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4181471301
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3744120217
Short name T283
Test name
Test status
Simulation time 2213690109 ps
CPU time 19.95 seconds
Started Jul 11 05:32:46 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 216652 kb
Host smart-a6a8fd9d-d778-4fe7-85cc-a7f4c3706a76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744120217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3744120217
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1070048987
Short name T11
Test name
Test status
Simulation time 153281806166 ps
CPU time 5637.91 seconds
Started Jul 11 05:32:49 PM PDT 24
Finished Jul 11 07:06:50 PM PDT 24
Peak memory 235816 kb
Host smart-487ce15b-063a-4d1f-9685-5985b3df08d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070048987 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1070048987
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3630740584
Short name T185
Test name
Test status
Simulation time 1883988533 ps
CPU time 14.16 seconds
Started Jul 11 05:32:51 PM PDT 24
Finished Jul 11 05:33:08 PM PDT 24
Peak memory 211216 kb
Host smart-ee5b9b96-cb34-487b-8a24-8990c448afe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630740584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3630740584
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1115794385
Short name T133
Test name
Test status
Simulation time 771083154 ps
CPU time 69.26 seconds
Started Jul 11 05:32:48 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 236688 kb
Host smart-26d115b0-003c-49eb-aa68-706e1302e30e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115794385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1115794385
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.951021656
Short name T300
Test name
Test status
Simulation time 3944247879 ps
CPU time 21.32 seconds
Started Jul 11 05:32:55 PM PDT 24
Finished Jul 11 05:33:19 PM PDT 24
Peak memory 212332 kb
Host smart-1f2f641c-e4e2-4403-b00e-f3ebdf08efe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951021656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.951021656
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1175134836
Short name T277
Test name
Test status
Simulation time 2206237858 ps
CPU time 17.09 seconds
Started Jul 11 05:32:45 PM PDT 24
Finished Jul 11 05:33:05 PM PDT 24
Peak memory 211380 kb
Host smart-5ec20e1a-632e-4887-a4f6-2cf64ca8d7aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175134836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1175134836
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1923535696
Short name T360
Test name
Test status
Simulation time 5751651244 ps
CPU time 34.08 seconds
Started Jul 11 05:32:47 PM PDT 24
Finished Jul 11 05:33:25 PM PDT 24
Peak memory 213912 kb
Host smart-f52be0f2-eedb-4c21-82e3-ab2af250565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923535696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1923535696
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2405863000
Short name T328
Test name
Test status
Simulation time 2491878556 ps
CPU time 18.29 seconds
Started Jul 11 05:32:47 PM PDT 24
Finished Jul 11 05:33:09 PM PDT 24
Peak memory 214272 kb
Host smart-12b5a12b-340a-4cc5-a13f-5d34eab2b391
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405863000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2405863000
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2578743539
Short name T190
Test name
Test status
Simulation time 8337104688 ps
CPU time 16.01 seconds
Started Jul 11 05:32:53 PM PDT 24
Finished Jul 11 05:33:12 PM PDT 24
Peak memory 211396 kb
Host smart-cfea0c15-c111-4051-8029-bba742217016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578743539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2578743539
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2713631725
Short name T122
Test name
Test status
Simulation time 8562491096 ps
CPU time 175.25 seconds
Started Jul 11 05:32:54 PM PDT 24
Finished Jul 11 05:35:52 PM PDT 24
Peak memory 212732 kb
Host smart-93fec6e4-cfef-4c40-9341-3d1c9425033e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713631725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2713631725
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1066647372
Short name T178
Test name
Test status
Simulation time 3292727263 ps
CPU time 13.95 seconds
Started Jul 11 05:32:55 PM PDT 24
Finished Jul 11 05:33:12 PM PDT 24
Peak memory 212156 kb
Host smart-a34a4933-89a5-45b4-b981-b885b1713850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066647372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1066647372
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2926845316
Short name T150
Test name
Test status
Simulation time 2114015305 ps
CPU time 17.22 seconds
Started Jul 11 05:32:54 PM PDT 24
Finished Jul 11 05:33:14 PM PDT 24
Peak memory 211356 kb
Host smart-4b24b365-ec57-44f8-94a3-dacae5fd426d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926845316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2926845316
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1634130691
Short name T186
Test name
Test status
Simulation time 191610230 ps
CPU time 9.84 seconds
Started Jul 11 05:32:46 PM PDT 24
Finished Jul 11 05:33:00 PM PDT 24
Peak memory 213304 kb
Host smart-5f9659a8-169c-4fb7-b4b1-94a9e176bbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634130691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1634130691
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.115901805
Short name T173
Test name
Test status
Simulation time 17432720977 ps
CPU time 21.22 seconds
Started Jul 11 05:32:49 PM PDT 24
Finished Jul 11 05:33:14 PM PDT 24
Peak memory 211272 kb
Host smart-121c132d-06ea-4438-8872-ba12b0aae53d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115901805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.115901805
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1639737392
Short name T330
Test name
Test status
Simulation time 168119036 ps
CPU time 4.35 seconds
Started Jul 11 05:32:53 PM PDT 24
Finished Jul 11 05:33:00 PM PDT 24
Peak memory 211308 kb
Host smart-98200ce1-3433-4012-8534-c71afb5e47e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639737392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1639737392
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2792881108
Short name T252
Test name
Test status
Simulation time 114797324246 ps
CPU time 280.52 seconds
Started Jul 11 05:32:53 PM PDT 24
Finished Jul 11 05:37:36 PM PDT 24
Peak memory 237880 kb
Host smart-edbf10a3-700e-45a6-856c-166e80ddeba7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792881108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2792881108
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1780795950
Short name T166
Test name
Test status
Simulation time 639128772 ps
CPU time 9.63 seconds
Started Jul 11 05:32:54 PM PDT 24
Finished Jul 11 05:33:06 PM PDT 24
Peak memory 211900 kb
Host smart-158f2a02-c914-4e34-a9e4-43d229fcafb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780795950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1780795950
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1539896105
Short name T112
Test name
Test status
Simulation time 610225231 ps
CPU time 9.16 seconds
Started Jul 11 05:32:52 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 211392 kb
Host smart-d979fe22-bb4c-468e-a98a-816a941f0cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539896105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1539896105
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3226461715
Short name T68
Test name
Test status
Simulation time 2889161811 ps
CPU time 29.2 seconds
Started Jul 11 05:32:54 PM PDT 24
Finished Jul 11 05:33:26 PM PDT 24
Peak memory 211860 kb
Host smart-766c3693-ad13-4cb5-9544-68c3a6f136d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226461715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3226461715
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3717839709
Short name T361
Test name
Test status
Simulation time 1367018602 ps
CPU time 14.52 seconds
Started Jul 11 05:32:53 PM PDT 24
Finished Jul 11 05:33:11 PM PDT 24
Peak memory 211284 kb
Host smart-ec988b9b-7d66-4cd2-b2ea-03b793685562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717839709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3717839709
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3194164262
Short name T236
Test name
Test status
Simulation time 1893400508 ps
CPU time 7.54 seconds
Started Jul 11 05:32:57 PM PDT 24
Finished Jul 11 05:33:07 PM PDT 24
Peak memory 211260 kb
Host smart-b5171d63-1d98-4a7e-9b3e-3a15a4884a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194164262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3194164262
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3617695865
Short name T222
Test name
Test status
Simulation time 11265501710 ps
CPU time 17.6 seconds
Started Jul 11 05:32:56 PM PDT 24
Finished Jul 11 05:33:16 PM PDT 24
Peak memory 212244 kb
Host smart-f73fc206-3cce-471c-8601-445a3f16a60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617695865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3617695865
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3503599050
Short name T97
Test name
Test status
Simulation time 19190263873 ps
CPU time 16.52 seconds
Started Jul 11 05:32:56 PM PDT 24
Finished Jul 11 05:33:14 PM PDT 24
Peak memory 211348 kb
Host smart-dbe51bda-80f2-4af0-ae5a-e998a1830e67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3503599050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3503599050
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.251088920
Short name T250
Test name
Test status
Simulation time 418669848 ps
CPU time 10.32 seconds
Started Jul 11 05:32:53 PM PDT 24
Finished Jul 11 05:33:06 PM PDT 24
Peak memory 213640 kb
Host smart-e444d177-8bf4-4e3e-9269-d28e7b4b9efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251088920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.251088920
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1838925715
Short name T258
Test name
Test status
Simulation time 32176593362 ps
CPU time 60.68 seconds
Started Jul 11 05:32:54 PM PDT 24
Finished Jul 11 05:33:58 PM PDT 24
Peak memory 216784 kb
Host smart-a4bc9256-5cda-462d-854a-1df7fea21dcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838925715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1838925715
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3371408580
Short name T315
Test name
Test status
Simulation time 333811716 ps
CPU time 4.35 seconds
Started Jul 11 05:31:35 PM PDT 24
Finished Jul 11 05:31:42 PM PDT 24
Peak memory 210628 kb
Host smart-9a97ae6f-12f9-4e1a-b4ea-5bf909686773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371408580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3371408580
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4222508913
Short name T195
Test name
Test status
Simulation time 24375066873 ps
CPU time 151.39 seconds
Started Jul 11 05:31:31 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 234888 kb
Host smart-8f7cb287-a7e5-43f6-9b5d-341a86feaab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222508913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4222508913
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3410700244
Short name T354
Test name
Test status
Simulation time 16731131370 ps
CPU time 32.66 seconds
Started Jul 11 05:31:33 PM PDT 24
Finished Jul 11 05:32:08 PM PDT 24
Peak memory 212420 kb
Host smart-faf86b48-e731-41c4-b1ef-fa32327bbe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410700244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3410700244
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2044471908
Short name T40
Test name
Test status
Simulation time 1404432943 ps
CPU time 10.95 seconds
Started Jul 11 05:31:33 PM PDT 24
Finished Jul 11 05:31:47 PM PDT 24
Peak memory 211320 kb
Host smart-4c17f33f-2a84-4a01-ba91-50642dac5378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2044471908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2044471908
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2313304478
Short name T362
Test name
Test status
Simulation time 7127627860 ps
CPU time 28.94 seconds
Started Jul 11 05:31:35 PM PDT 24
Finished Jul 11 05:32:07 PM PDT 24
Peak memory 213764 kb
Host smart-245b6286-aeb6-4498-b2b4-d190397abcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313304478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2313304478
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2868829253
Short name T309
Test name
Test status
Simulation time 548274277 ps
CPU time 32.51 seconds
Started Jul 11 05:31:32 PM PDT 24
Finished Jul 11 05:32:07 PM PDT 24
Peak memory 216964 kb
Host smart-7f729c54-33fe-44d1-afe9-db16b6b7d4a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868829253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2868829253
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2816406807
Short name T234
Test name
Test status
Simulation time 139851696496 ps
CPU time 1275.97 seconds
Started Jul 11 05:31:33 PM PDT 24
Finished Jul 11 05:52:51 PM PDT 24
Peak memory 235820 kb
Host smart-5eab3a0f-e442-4f60-aad5-3a110fc04112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816406807 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2816406807
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3013055245
Short name T329
Test name
Test status
Simulation time 3126336303 ps
CPU time 8.94 seconds
Started Jul 11 05:31:33 PM PDT 24
Finished Jul 11 05:31:45 PM PDT 24
Peak memory 211332 kb
Host smart-b1a76e55-b371-4c50-98b6-4868da5cba40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013055245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3013055245
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3897107428
Short name T171
Test name
Test status
Simulation time 8433955896 ps
CPU time 165.33 seconds
Started Jul 11 05:31:28 PM PDT 24
Finished Jul 11 05:34:15 PM PDT 24
Peak memory 237832 kb
Host smart-e85a5ab3-dc7b-4ef2-9a96-440449b93a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897107428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3897107428
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3963082124
Short name T20
Test name
Test status
Simulation time 168323894 ps
CPU time 9.51 seconds
Started Jul 11 05:31:34 PM PDT 24
Finished Jul 11 05:31:46 PM PDT 24
Peak memory 211892 kb
Host smart-04d43813-e5aa-44fe-ad4f-21fa61170e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963082124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3963082124
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1484549583
Short name T293
Test name
Test status
Simulation time 1594178374 ps
CPU time 13.98 seconds
Started Jul 11 05:31:33 PM PDT 24
Finished Jul 11 05:31:49 PM PDT 24
Peak memory 211404 kb
Host smart-e127f332-4c0f-490b-a4c5-44bf687b65b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1484549583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1484549583
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2635371299
Short name T198
Test name
Test status
Simulation time 2575123555 ps
CPU time 26.5 seconds
Started Jul 11 05:31:30 PM PDT 24
Finished Jul 11 05:31:59 PM PDT 24
Peak memory 213032 kb
Host smart-546f894d-a8e8-4fd3-aaf3-fabbeb90c1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635371299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2635371299
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1966657150
Short name T281
Test name
Test status
Simulation time 6925226389 ps
CPU time 68.17 seconds
Started Jul 11 05:31:33 PM PDT 24
Finished Jul 11 05:32:43 PM PDT 24
Peak memory 216924 kb
Host smart-fcfe4303-a6e8-4edd-9114-3a3f4e345abe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966657150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1966657150
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2152781343
Short name T299
Test name
Test status
Simulation time 33912591357 ps
CPU time 3542.66 seconds
Started Jul 11 05:31:35 PM PDT 24
Finished Jul 11 06:30:40 PM PDT 24
Peak memory 235744 kb
Host smart-ad2b9ca1-6ad6-4af9-86d6-ff46a6f54e31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152781343 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2152781343
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2765121115
Short name T307
Test name
Test status
Simulation time 348232662 ps
CPU time 4.28 seconds
Started Jul 11 05:31:34 PM PDT 24
Finished Jul 11 05:31:41 PM PDT 24
Peak memory 211232 kb
Host smart-194a589d-ad7c-49f2-a245-41a575281e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765121115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2765121115
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3382266788
Short name T177
Test name
Test status
Simulation time 62985941353 ps
CPU time 161.45 seconds
Started Jul 11 05:31:47 PM PDT 24
Finished Jul 11 05:34:29 PM PDT 24
Peak memory 233752 kb
Host smart-b3dda6dd-0d08-40bc-89c6-5e7ee62a1cba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382266788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3382266788
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3680389727
Short name T29
Test name
Test status
Simulation time 8870353583 ps
CPU time 23.33 seconds
Started Jul 11 05:31:35 PM PDT 24
Finished Jul 11 05:32:00 PM PDT 24
Peak memory 212236 kb
Host smart-c65fb8ce-4053-40c2-b0fb-beee2d088266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680389727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3680389727
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4169692953
Short name T218
Test name
Test status
Simulation time 189914676 ps
CPU time 5.52 seconds
Started Jul 11 05:31:39 PM PDT 24
Finished Jul 11 05:31:45 PM PDT 24
Peak memory 211368 kb
Host smart-77d110f1-5185-46e2-8b29-8320cf581886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169692953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4169692953
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3456634884
Short name T358
Test name
Test status
Simulation time 7804296140 ps
CPU time 28.87 seconds
Started Jul 11 05:31:40 PM PDT 24
Finished Jul 11 05:32:10 PM PDT 24
Peak memory 213964 kb
Host smart-4ad79008-e413-413d-bbb5-18a5a305441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456634884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3456634884
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.807774407
Short name T225
Test name
Test status
Simulation time 7323084825 ps
CPU time 23.56 seconds
Started Jul 11 05:31:35 PM PDT 24
Finished Jul 11 05:32:01 PM PDT 24
Peak memory 214764 kb
Host smart-c0b55a62-d2ce-4a92-950a-1aca8e13efa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807774407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.807774407
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2951286858
Short name T46
Test name
Test status
Simulation time 44299647327 ps
CPU time 1666.47 seconds
Started Jul 11 05:31:35 PM PDT 24
Finished Jul 11 05:59:24 PM PDT 24
Peak memory 235820 kb
Host smart-fcd4c33a-c3f3-4f8e-a404-664f269da2b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951286858 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2951286858
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4226036136
Short name T269
Test name
Test status
Simulation time 4243636997 ps
CPU time 10.45 seconds
Started Jul 11 05:31:41 PM PDT 24
Finished Jul 11 05:31:53 PM PDT 24
Peak memory 211300 kb
Host smart-8a5068e5-2beb-419d-b517-c929764b0112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226036136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4226036136
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.747791249
Short name T251
Test name
Test status
Simulation time 14029276935 ps
CPU time 186.43 seconds
Started Jul 11 05:31:47 PM PDT 24
Finished Jul 11 05:34:54 PM PDT 24
Peak memory 225092 kb
Host smart-3c408032-91d7-4ff9-b093-e494aee1e5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747791249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.747791249
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.154516032
Short name T199
Test name
Test status
Simulation time 1900239717 ps
CPU time 21.42 seconds
Started Jul 11 05:31:35 PM PDT 24
Finished Jul 11 05:31:59 PM PDT 24
Peak memory 211816 kb
Host smart-e0c39b29-f4ef-4448-b3f1-656ab6cf4886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154516032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.154516032
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2119001626
Short name T255
Test name
Test status
Simulation time 100704229 ps
CPU time 5.82 seconds
Started Jul 11 05:31:36 PM PDT 24
Finished Jul 11 05:31:44 PM PDT 24
Peak memory 211320 kb
Host smart-9e4e6cd5-3906-4559-8df0-36fd2fc81832
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119001626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2119001626
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2218425120
Short name T260
Test name
Test status
Simulation time 2538626683 ps
CPU time 27.6 seconds
Started Jul 11 05:31:34 PM PDT 24
Finished Jul 11 05:32:04 PM PDT 24
Peak memory 213512 kb
Host smart-fe97e005-0b34-4699-bb53-9249db753dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218425120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2218425120
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1180871512
Short name T212
Test name
Test status
Simulation time 9675680440 ps
CPU time 80.15 seconds
Started Jul 11 05:31:35 PM PDT 24
Finished Jul 11 05:32:57 PM PDT 24
Peak memory 216076 kb
Host smart-15e667bc-8a2c-4c73-93d1-f89d368e8531
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180871512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1180871512
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3075192159
Short name T204
Test name
Test status
Simulation time 20377353121 ps
CPU time 5985.53 seconds
Started Jul 11 05:31:45 PM PDT 24
Finished Jul 11 07:11:33 PM PDT 24
Peak memory 235852 kb
Host smart-00fa08e0-e0ef-4dfa-b24e-78860de02e22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075192159 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3075192159
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1506492402
Short name T59
Test name
Test status
Simulation time 1488678170 ps
CPU time 6.97 seconds
Started Jul 11 05:31:40 PM PDT 24
Finished Jul 11 05:31:49 PM PDT 24
Peak memory 211288 kb
Host smart-0189ac04-0eb3-49d4-aafa-0de129402e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506492402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1506492402
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1421301314
Short name T15
Test name
Test status
Simulation time 2469136909 ps
CPU time 56.17 seconds
Started Jul 11 05:31:52 PM PDT 24
Finished Jul 11 05:32:50 PM PDT 24
Peak memory 232788 kb
Host smart-94a2dcfa-ebb1-4283-a988-23af3facf560
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421301314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1421301314
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2274311447
Short name T265
Test name
Test status
Simulation time 1010662822 ps
CPU time 13.33 seconds
Started Jul 11 05:31:41 PM PDT 24
Finished Jul 11 05:31:56 PM PDT 24
Peak memory 212088 kb
Host smart-474e8cc6-c8ff-44f7-8af2-b7d326209b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274311447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2274311447
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3766525339
Short name T322
Test name
Test status
Simulation time 5878936242 ps
CPU time 13.43 seconds
Started Jul 11 05:31:41 PM PDT 24
Finished Jul 11 05:31:56 PM PDT 24
Peak memory 211376 kb
Host smart-6643a1e6-4e63-4d67-8a3b-a0623b38d798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3766525339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3766525339
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3337095561
Short name T344
Test name
Test status
Simulation time 921506102 ps
CPU time 16.94 seconds
Started Jul 11 05:31:44 PM PDT 24
Finished Jul 11 05:32:02 PM PDT 24
Peak memory 211388 kb
Host smart-a66c41a0-b17b-454b-a450-0e62eded1ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337095561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3337095561
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.443660190
Short name T48
Test name
Test status
Simulation time 456905971811 ps
CPU time 4076.02 seconds
Started Jul 11 05:31:42 PM PDT 24
Finished Jul 11 06:39:40 PM PDT 24
Peak memory 246484 kb
Host smart-77b93686-ab7b-4517-a4fe-824a49e44832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443660190 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.443660190
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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