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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 96.89 91.85 97.67 100.00 98.28 97.45 98.37


Total test records in report: 462
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T302 /workspace/coverage/default/24.rom_ctrl_stress_all.3233898913 Jul 12 05:46:37 PM PDT 24 Jul 12 05:47:09 PM PDT 24 11955063591 ps
T303 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.593765771 Jul 12 05:46:25 PM PDT 24 Jul 12 05:49:00 PM PDT 24 19054780415 ps
T304 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2866828399 Jul 12 05:46:12 PM PDT 24 Jul 12 05:46:18 PM PDT 24 97845419 ps
T305 /workspace/coverage/default/11.rom_ctrl_alert_test.2686775752 Jul 12 05:46:16 PM PDT 24 Jul 12 05:46:34 PM PDT 24 2004332590 ps
T306 /workspace/coverage/default/5.rom_ctrl_stress_all.1000711984 Jul 12 05:46:08 PM PDT 24 Jul 12 05:46:22 PM PDT 24 855540544 ps
T307 /workspace/coverage/default/16.rom_ctrl_smoke.764011535 Jul 12 05:46:30 PM PDT 24 Jul 12 05:46:42 PM PDT 24 176838239 ps
T308 /workspace/coverage/default/26.rom_ctrl_smoke.652305284 Jul 12 05:46:33 PM PDT 24 Jul 12 05:46:56 PM PDT 24 2392461674 ps
T309 /workspace/coverage/default/27.rom_ctrl_alert_test.3849493333 Jul 12 05:46:43 PM PDT 24 Jul 12 05:46:58 PM PDT 24 11208140179 ps
T310 /workspace/coverage/default/33.rom_ctrl_alert_test.805761059 Jul 12 05:46:42 PM PDT 24 Jul 12 05:46:49 PM PDT 24 98181427 ps
T311 /workspace/coverage/default/48.rom_ctrl_smoke.3681788444 Jul 12 05:47:18 PM PDT 24 Jul 12 05:47:44 PM PDT 24 19828478891 ps
T312 /workspace/coverage/default/21.rom_ctrl_alert_test.360030933 Jul 12 05:46:26 PM PDT 24 Jul 12 05:46:31 PM PDT 24 830715094 ps
T313 /workspace/coverage/default/34.rom_ctrl_alert_test.1188887419 Jul 12 05:46:49 PM PDT 24 Jul 12 05:46:58 PM PDT 24 439028392 ps
T314 /workspace/coverage/default/6.rom_ctrl_alert_test.3633225487 Jul 12 05:46:15 PM PDT 24 Jul 12 05:46:30 PM PDT 24 6606106804 ps
T28 /workspace/coverage/default/0.rom_ctrl_sec_cm.950545471 Jul 12 05:46:09 PM PDT 24 Jul 12 05:47:13 PM PDT 24 1844831337 ps
T315 /workspace/coverage/default/31.rom_ctrl_smoke.3838228507 Jul 12 05:46:41 PM PDT 24 Jul 12 05:46:54 PM PDT 24 385677773 ps
T57 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2515464057 Jul 12 05:46:35 PM PDT 24 Jul 12 06:01:28 PM PDT 24 89424201366 ps
T316 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3474323198 Jul 12 05:47:05 PM PDT 24 Jul 12 05:55:01 PM PDT 24 49234115022 ps
T29 /workspace/coverage/default/4.rom_ctrl_sec_cm.2527349107 Jul 12 05:46:12 PM PDT 24 Jul 12 05:47:54 PM PDT 24 583556815 ps
T317 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1940623697 Jul 12 05:47:08 PM PDT 24 Jul 12 05:49:09 PM PDT 24 6069358852 ps
T318 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.101498110 Jul 12 05:46:48 PM PDT 24 Jul 12 05:52:13 PM PDT 24 84521457825 ps
T319 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1939152216 Jul 12 05:47:16 PM PDT 24 Jul 12 05:47:26 PM PDT 24 175433439 ps
T320 /workspace/coverage/default/25.rom_ctrl_smoke.2982916143 Jul 12 05:46:34 PM PDT 24 Jul 12 05:46:50 PM PDT 24 941899951 ps
T321 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4190333754 Jul 12 05:47:12 PM PDT 24 Jul 12 05:47:39 PM PDT 24 2750997823 ps
T322 /workspace/coverage/default/42.rom_ctrl_alert_test.1213989439 Jul 12 05:47:14 PM PDT 24 Jul 12 05:47:29 PM PDT 24 4624261177 ps
T323 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1520876026 Jul 12 05:47:20 PM PDT 24 Jul 12 05:47:31 PM PDT 24 334144224 ps
T324 /workspace/coverage/default/19.rom_ctrl_smoke.223287196 Jul 12 05:46:31 PM PDT 24 Jul 12 05:46:52 PM PDT 24 1572524269 ps
T325 /workspace/coverage/default/36.rom_ctrl_alert_test.2533652932 Jul 12 05:46:54 PM PDT 24 Jul 12 05:47:08 PM PDT 24 2689022114 ps
T326 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2412373662 Jul 12 05:46:59 PM PDT 24 Jul 12 05:47:15 PM PDT 24 943427503 ps
T327 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4191708921 Jul 12 05:47:03 PM PDT 24 Jul 12 05:49:49 PM PDT 24 12480012406 ps
T328 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1919916783 Jul 12 05:46:12 PM PDT 24 Jul 12 06:10:55 PM PDT 24 113926853000 ps
T329 /workspace/coverage/default/14.rom_ctrl_stress_all.2266102461 Jul 12 05:46:21 PM PDT 24 Jul 12 05:47:45 PM PDT 24 8613301481 ps
T330 /workspace/coverage/default/2.rom_ctrl_stress_all.3691042342 Jul 12 05:46:12 PM PDT 24 Jul 12 05:46:53 PM PDT 24 44128399378 ps
T331 /workspace/coverage/default/31.rom_ctrl_stress_all.3061390389 Jul 12 05:46:41 PM PDT 24 Jul 12 05:47:04 PM PDT 24 615157127 ps
T332 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.823188895 Jul 12 05:46:46 PM PDT 24 Jul 12 06:28:08 PM PDT 24 87679958219 ps
T333 /workspace/coverage/default/35.rom_ctrl_stress_all.780730062 Jul 12 05:46:52 PM PDT 24 Jul 12 05:47:16 PM PDT 24 382485707 ps
T334 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3216207528 Jul 12 05:46:40 PM PDT 24 Jul 12 05:49:04 PM PDT 24 2343779099 ps
T335 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2061947234 Jul 12 05:47:11 PM PDT 24 Jul 12 05:48:32 PM PDT 24 5025258979 ps
T336 /workspace/coverage/default/49.rom_ctrl_stress_all.2965721501 Jul 12 05:47:18 PM PDT 24 Jul 12 05:47:56 PM PDT 24 9048452348 ps
T337 /workspace/coverage/default/12.rom_ctrl_alert_test.3221188862 Jul 12 05:46:18 PM PDT 24 Jul 12 05:46:31 PM PDT 24 1150405427 ps
T338 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.967705610 Jul 12 05:47:19 PM PDT 24 Jul 12 05:47:46 PM PDT 24 10892878002 ps
T339 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3941980904 Jul 12 05:46:29 PM PDT 24 Jul 12 05:48:11 PM PDT 24 2835858554 ps
T340 /workspace/coverage/default/43.rom_ctrl_stress_all.3131729616 Jul 12 05:47:10 PM PDT 24 Jul 12 05:47:24 PM PDT 24 269882768 ps
T341 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4175032193 Jul 12 05:47:15 PM PDT 24 Jul 12 05:47:21 PM PDT 24 541468628 ps
T342 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.29782846 Jul 12 05:46:47 PM PDT 24 Jul 12 05:49:49 PM PDT 24 53401792409 ps
T343 /workspace/coverage/default/29.rom_ctrl_stress_all.4100960621 Jul 12 05:46:41 PM PDT 24 Jul 12 05:47:18 PM PDT 24 12481482322 ps
T344 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3703410548 Jul 12 05:46:53 PM PDT 24 Jul 12 05:47:25 PM PDT 24 4817894493 ps
T345 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1977488222 Jul 12 05:46:08 PM PDT 24 Jul 12 05:50:18 PM PDT 24 94110984671 ps
T346 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.532192876 Jul 12 05:47:10 PM PDT 24 Jul 12 05:51:44 PM PDT 24 29360833065 ps
T347 /workspace/coverage/default/3.rom_ctrl_smoke.1963197565 Jul 12 05:46:15 PM PDT 24 Jul 12 05:46:50 PM PDT 24 16470677282 ps
T348 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.574092294 Jul 12 05:46:41 PM PDT 24 Jul 12 05:46:49 PM PDT 24 355083973 ps
T349 /workspace/coverage/default/20.rom_ctrl_smoke.4003390672 Jul 12 05:46:26 PM PDT 24 Jul 12 05:46:40 PM PDT 24 2100221618 ps
T350 /workspace/coverage/default/6.rom_ctrl_stress_all.2211447321 Jul 12 05:46:18 PM PDT 24 Jul 12 05:46:30 PM PDT 24 140973034 ps
T351 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1609566983 Jul 12 05:46:22 PM PDT 24 Jul 12 05:46:46 PM PDT 24 9222736688 ps
T352 /workspace/coverage/default/46.rom_ctrl_stress_all.2289140286 Jul 12 05:47:12 PM PDT 24 Jul 12 05:47:24 PM PDT 24 642276591 ps
T353 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3260842203 Jul 12 05:46:09 PM PDT 24 Jul 12 05:46:21 PM PDT 24 4953635853 ps
T354 /workspace/coverage/default/44.rom_ctrl_smoke.2498263363 Jul 12 05:47:10 PM PDT 24 Jul 12 05:47:49 PM PDT 24 3504983647 ps
T355 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3450933624 Jul 12 05:46:28 PM PDT 24 Jul 12 05:46:40 PM PDT 24 341276124 ps
T356 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3931182291 Jul 12 05:46:15 PM PDT 24 Jul 12 05:46:30 PM PDT 24 6247102587 ps
T357 /workspace/coverage/default/38.rom_ctrl_stress_all.1576528611 Jul 12 05:46:53 PM PDT 24 Jul 12 05:47:34 PM PDT 24 14477862157 ps
T358 /workspace/coverage/default/24.rom_ctrl_smoke.3160873287 Jul 12 05:46:35 PM PDT 24 Jul 12 05:47:07 PM PDT 24 3094683232 ps
T359 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3241127511 Jul 12 05:46:28 PM PDT 24 Jul 12 05:47:03 PM PDT 24 4075244119 ps
T360 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2179639848 Jul 12 05:46:20 PM PDT 24 Jul 12 05:46:46 PM PDT 24 4833649458 ps
T361 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3891958816 Jul 12 05:46:42 PM PDT 24 Jul 12 05:50:57 PM PDT 24 97901603888 ps
T362 /workspace/coverage/default/32.rom_ctrl_stress_all.505809009 Jul 12 05:46:44 PM PDT 24 Jul 12 05:47:14 PM PDT 24 476046770 ps
T363 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.341835021 Jul 12 05:47:56 PM PDT 24 Jul 12 05:48:07 PM PDT 24 175719243 ps
T364 /workspace/coverage/default/3.rom_ctrl_stress_all.3717062392 Jul 12 05:46:07 PM PDT 24 Jul 12 05:46:24 PM PDT 24 7572346213 ps
T365 /workspace/coverage/default/21.rom_ctrl_smoke.86720540 Jul 12 05:46:27 PM PDT 24 Jul 12 05:46:50 PM PDT 24 1766917711 ps
T61 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3944018879 Jul 12 06:08:09 PM PDT 24 Jul 12 06:09:48 PM PDT 24 328623716 ps
T65 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2034955365 Jul 12 06:07:43 PM PDT 24 Jul 12 06:08:58 PM PDT 24 4359226008 ps
T62 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4111569823 Jul 12 06:07:49 PM PDT 24 Jul 12 06:09:30 PM PDT 24 2807250676 ps
T366 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2921247828 Jul 12 06:08:20 PM PDT 24 Jul 12 06:09:34 PM PDT 24 426669509 ps
T63 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3616922282 Jul 12 06:08:05 PM PDT 24 Jul 12 06:09:52 PM PDT 24 1659676160 ps
T68 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3029236124 Jul 12 06:08:23 PM PDT 24 Jul 12 06:10:35 PM PDT 24 8592916036 ps
T115 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1653037436 Jul 12 06:07:55 PM PDT 24 Jul 12 06:10:12 PM PDT 24 8274822576 ps
T105 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.419211378 Jul 12 06:07:49 PM PDT 24 Jul 12 06:08:51 PM PDT 24 379343600 ps
T106 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1521026592 Jul 12 06:08:28 PM PDT 24 Jul 12 06:10:36 PM PDT 24 27106533463 ps
T367 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3998711895 Jul 12 06:08:12 PM PDT 24 Jul 12 06:09:28 PM PDT 24 1123888062 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2262788426 Jul 12 06:07:50 PM PDT 24 Jul 12 06:08:57 PM PDT 24 571657770 ps
T107 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.635965961 Jul 12 06:08:21 PM PDT 24 Jul 12 06:09:38 PM PDT 24 1779019843 ps
T69 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4162579618 Jul 12 06:08:23 PM PDT 24 Jul 12 06:10:45 PM PDT 24 46473805241 ps
T369 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1025420003 Jul 12 06:08:02 PM PDT 24 Jul 12 06:09:16 PM PDT 24 2650943209 ps
T70 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2325515876 Jul 12 06:08:29 PM PDT 24 Jul 12 06:09:54 PM PDT 24 29640547928 ps
T108 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3189864086 Jul 12 06:08:30 PM PDT 24 Jul 12 06:09:57 PM PDT 24 18101937412 ps
T71 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1545701289 Jul 12 06:08:05 PM PDT 24 Jul 12 06:09:18 PM PDT 24 9732283481 ps
T72 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.155033441 Jul 12 06:08:32 PM PDT 24 Jul 12 06:09:55 PM PDT 24 1634601550 ps
T116 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.839914800 Jul 12 06:08:27 PM PDT 24 Jul 12 06:10:48 PM PDT 24 1035308212 ps
T109 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.734154844 Jul 12 06:08:32 PM PDT 24 Jul 12 06:10:00 PM PDT 24 735880716 ps
T370 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2008696369 Jul 12 06:08:23 PM PDT 24 Jul 12 06:09:49 PM PDT 24 3187747759 ps
T371 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.322424758 Jul 12 06:08:35 PM PDT 24 Jul 12 06:09:59 PM PDT 24 7613358778 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1091014507 Jul 12 06:07:57 PM PDT 24 Jul 12 06:09:15 PM PDT 24 2056297268 ps
T100 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1034534985 Jul 12 06:08:09 PM PDT 24 Jul 12 06:09:22 PM PDT 24 1277027892 ps
T117 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.200050622 Jul 12 06:08:21 PM PDT 24 Jul 12 06:10:38 PM PDT 24 463190895 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3464696296 Jul 12 06:07:49 PM PDT 24 Jul 12 06:08:55 PM PDT 24 1980581464 ps
T122 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3085566482 Jul 12 06:08:14 PM PDT 24 Jul 12 06:10:34 PM PDT 24 1087269628 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3955297805 Jul 12 06:07:49 PM PDT 24 Jul 12 06:08:52 PM PDT 24 92953513 ps
T73 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2652214756 Jul 12 06:08:15 PM PDT 24 Jul 12 06:09:51 PM PDT 24 577967901 ps
T375 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2263171207 Jul 12 06:08:29 PM PDT 24 Jul 12 06:09:56 PM PDT 24 3779489713 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3937347591 Jul 12 06:07:50 PM PDT 24 Jul 12 06:08:53 PM PDT 24 171208742 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.53592580 Jul 12 06:07:44 PM PDT 24 Jul 12 06:09:08 PM PDT 24 1188500719 ps
T378 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.791585764 Jul 12 06:07:52 PM PDT 24 Jul 12 06:08:56 PM PDT 24 184303846 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2313059028 Jul 12 06:07:44 PM PDT 24 Jul 12 06:08:51 PM PDT 24 899380061 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3335952456 Jul 12 06:08:01 PM PDT 24 Jul 12 06:09:14 PM PDT 24 4117500832 ps
T381 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1784190449 Jul 12 06:08:10 PM PDT 24 Jul 12 06:09:21 PM PDT 24 1437473302 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1029282129 Jul 12 06:08:09 PM PDT 24 Jul 12 06:09:59 PM PDT 24 12972373242 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.494669911 Jul 12 06:08:02 PM PDT 24 Jul 12 06:09:48 PM PDT 24 10300287776 ps
T384 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2925152802 Jul 12 06:08:10 PM PDT 24 Jul 12 06:09:28 PM PDT 24 1536411860 ps
T74 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2264393520 Jul 12 06:07:44 PM PDT 24 Jul 12 06:08:57 PM PDT 24 28616474326 ps
T385 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3029406084 Jul 12 06:08:22 PM PDT 24 Jul 12 06:09:34 PM PDT 24 332501476 ps
T386 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3590182718 Jul 12 06:07:58 PM PDT 24 Jul 12 06:09:16 PM PDT 24 4285572576 ps
T75 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3582697675 Jul 12 06:07:49 PM PDT 24 Jul 12 06:09:01 PM PDT 24 1763515009 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.600283337 Jul 12 06:08:05 PM PDT 24 Jul 12 06:09:16 PM PDT 24 3289340069 ps
T388 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.433410306 Jul 12 06:08:23 PM PDT 24 Jul 12 06:09:47 PM PDT 24 9666627921 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.247781646 Jul 12 06:07:55 PM PDT 24 Jul 12 06:09:06 PM PDT 24 4571586826 ps
T390 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4208297532 Jul 12 06:08:11 PM PDT 24 Jul 12 06:09:34 PM PDT 24 6041940611 ps
T123 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3043960178 Jul 12 06:08:23 PM PDT 24 Jul 12 06:10:17 PM PDT 24 1946682195 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.98158356 Jul 12 06:08:17 PM PDT 24 Jul 12 06:09:30 PM PDT 24 174218115 ps
T77 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3491247181 Jul 12 06:08:35 PM PDT 24 Jul 12 06:10:06 PM PDT 24 26675549069 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2093442825 Jul 12 06:08:07 PM PDT 24 Jul 12 06:09:25 PM PDT 24 7337830381 ps
T392 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1899005236 Jul 12 06:08:10 PM PDT 24 Jul 12 06:09:31 PM PDT 24 2735820109 ps
T101 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3907822552 Jul 12 06:08:36 PM PDT 24 Jul 12 06:09:56 PM PDT 24 431923983 ps
T102 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.851851555 Jul 12 06:08:10 PM PDT 24 Jul 12 06:09:20 PM PDT 24 519341107 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1530192233 Jul 12 06:08:23 PM PDT 24 Jul 12 06:09:48 PM PDT 24 8632172196 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3103979953 Jul 12 06:08:36 PM PDT 24 Jul 12 06:09:56 PM PDT 24 1591715268 ps
T395 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.480090744 Jul 12 06:08:35 PM PDT 24 Jul 12 06:10:04 PM PDT 24 1861335985 ps
T396 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1028751563 Jul 12 06:08:36 PM PDT 24 Jul 12 06:10:25 PM PDT 24 2556277820 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2705459930 Jul 12 06:07:44 PM PDT 24 Jul 12 06:09:53 PM PDT 24 16462738704 ps
T103 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4110830202 Jul 12 06:07:45 PM PDT 24 Jul 12 06:08:56 PM PDT 24 6661352976 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1260534357 Jul 12 06:08:17 PM PDT 24 Jul 12 06:09:35 PM PDT 24 4489897669 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.252447881 Jul 12 06:07:57 PM PDT 24 Jul 12 06:09:06 PM PDT 24 795442060 ps
T398 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2379518955 Jul 12 06:08:36 PM PDT 24 Jul 12 06:10:00 PM PDT 24 474236378 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1572114366 Jul 12 06:07:45 PM PDT 24 Jul 12 06:09:00 PM PDT 24 23069914569 ps
T128 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1616888444 Jul 12 06:08:09 PM PDT 24 Jul 12 06:09:55 PM PDT 24 15805739631 ps
T400 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.590319324 Jul 12 06:08:11 PM PDT 24 Jul 12 06:10:24 PM PDT 24 7058756046 ps
T85 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3275013704 Jul 12 06:08:23 PM PDT 24 Jul 12 06:09:55 PM PDT 24 6069170318 ps
T90 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.198146872 Jul 12 06:08:10 PM PDT 24 Jul 12 06:09:52 PM PDT 24 13775504814 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.521283079 Jul 12 06:07:46 PM PDT 24 Jul 12 06:08:58 PM PDT 24 3833166967 ps
T402 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.823536928 Jul 12 06:08:22 PM PDT 24 Jul 12 06:09:48 PM PDT 24 7116185071 ps
T104 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1454356611 Jul 12 06:08:32 PM PDT 24 Jul 12 06:09:56 PM PDT 24 9027934075 ps
T403 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3299344397 Jul 12 06:08:27 PM PDT 24 Jul 12 06:09:46 PM PDT 24 1146775311 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2371466636 Jul 12 06:07:53 PM PDT 24 Jul 12 06:09:53 PM PDT 24 7983068781 ps
T404 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3895385192 Jul 12 06:08:38 PM PDT 24 Jul 12 06:09:56 PM PDT 24 903750564 ps
T405 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3422494056 Jul 12 06:08:07 PM PDT 24 Jul 12 06:09:24 PM PDT 24 3359432786 ps
T91 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4273479986 Jul 12 06:08:36 PM PDT 24 Jul 12 06:10:57 PM PDT 24 34491782483 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2893290008 Jul 12 06:07:50 PM PDT 24 Jul 12 06:08:57 PM PDT 24 1970829089 ps
T407 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4285276791 Jul 12 06:08:29 PM PDT 24 Jul 12 06:10:23 PM PDT 24 7082745318 ps
T120 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1580477061 Jul 12 06:08:32 PM PDT 24 Jul 12 06:10:20 PM PDT 24 204048620 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3934036175 Jul 12 06:07:58 PM PDT 24 Jul 12 06:09:08 PM PDT 24 2072637694 ps
T124 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1386380372 Jul 12 06:07:45 PM PDT 24 Jul 12 06:10:00 PM PDT 24 4380677851 ps
T409 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3692973634 Jul 12 06:08:34 PM PDT 24 Jul 12 06:09:51 PM PDT 24 2939463648 ps
T410 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3208171268 Jul 12 06:08:22 PM PDT 24 Jul 12 06:09:38 PM PDT 24 2301700469 ps
T121 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1502412419 Jul 12 06:08:34 PM PDT 24 Jul 12 06:10:50 PM PDT 24 871056612 ps
T411 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3642873387 Jul 12 06:08:22 PM PDT 24 Jul 12 06:09:36 PM PDT 24 3151616697 ps
T412 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2388279430 Jul 12 06:08:04 PM PDT 24 Jul 12 06:09:25 PM PDT 24 8015461005 ps
T413 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1626665821 Jul 12 06:08:34 PM PDT 24 Jul 12 06:09:53 PM PDT 24 2213900102 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1653909597 Jul 12 06:08:03 PM PDT 24 Jul 12 06:09:10 PM PDT 24 333209257 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4120752528 Jul 12 06:08:02 PM PDT 24 Jul 12 06:10:06 PM PDT 24 14066997381 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2786559130 Jul 12 06:07:52 PM PDT 24 Jul 12 06:08:58 PM PDT 24 385007813 ps
T415 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4254410891 Jul 12 06:08:02 PM PDT 24 Jul 12 06:10:19 PM PDT 24 14324166453 ps
T118 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.883695947 Jul 12 06:08:20 PM PDT 24 Jul 12 06:10:40 PM PDT 24 4721751022 ps
T416 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2195390669 Jul 12 06:08:28 PM PDT 24 Jul 12 06:09:53 PM PDT 24 6878367560 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.556741711 Jul 12 06:07:56 PM PDT 24 Jul 12 06:09:06 PM PDT 24 14149757612 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.420734717 Jul 12 06:07:59 PM PDT 24 Jul 12 06:09:14 PM PDT 24 11413377416 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4204945084 Jul 12 06:08:03 PM PDT 24 Jul 12 06:09:13 PM PDT 24 534633476 ps
T420 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.449543370 Jul 12 06:08:42 PM PDT 24 Jul 12 06:10:05 PM PDT 24 1800100554 ps
T125 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1859025585 Jul 12 06:08:34 PM PDT 24 Jul 12 06:10:57 PM PDT 24 1720780948 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3317647623 Jul 12 06:07:50 PM PDT 24 Jul 12 06:09:06 PM PDT 24 1853112586 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1067133738 Jul 12 06:08:00 PM PDT 24 Jul 12 06:09:13 PM PDT 24 5541094594 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1802094631 Jul 12 06:08:37 PM PDT 24 Jul 12 06:10:35 PM PDT 24 39152668533 ps
T423 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3389999059 Jul 12 06:08:34 PM PDT 24 Jul 12 06:09:55 PM PDT 24 1500270351 ps
T424 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.838884609 Jul 12 06:07:57 PM PDT 24 Jul 12 06:10:12 PM PDT 24 8911408982 ps
T126 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2994434372 Jul 12 06:08:38 PM PDT 24 Jul 12 06:11:09 PM PDT 24 2418457517 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3677198554 Jul 12 06:08:02 PM PDT 24 Jul 12 06:09:11 PM PDT 24 90466724 ps
T426 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2391167770 Jul 12 06:08:22 PM PDT 24 Jul 12 06:09:37 PM PDT 24 1800381188 ps
T427 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.832713474 Jul 12 06:08:15 PM PDT 24 Jul 12 06:09:43 PM PDT 24 2021566449 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3139767338 Jul 12 06:08:36 PM PDT 24 Jul 12 06:09:58 PM PDT 24 1817015101 ps
T429 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.918984040 Jul 12 06:08:28 PM PDT 24 Jul 12 06:09:44 PM PDT 24 89258727 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2191634814 Jul 12 06:08:28 PM PDT 24 Jul 12 06:09:58 PM PDT 24 1540198162 ps
T431 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1039009214 Jul 12 06:07:58 PM PDT 24 Jul 12 06:09:04 PM PDT 24 88875363 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1973781110 Jul 12 06:07:56 PM PDT 24 Jul 12 06:09:03 PM PDT 24 469440021 ps
T433 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3646541908 Jul 12 06:08:24 PM PDT 24 Jul 12 06:09:45 PM PDT 24 6215398713 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2648423655 Jul 12 06:07:45 PM PDT 24 Jul 12 06:08:53 PM PDT 24 3979921142 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.707265568 Jul 12 06:08:32 PM PDT 24 Jul 12 06:09:48 PM PDT 24 1085929631 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1129401694 Jul 12 06:08:08 PM PDT 24 Jul 12 06:09:24 PM PDT 24 6333113462 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.308192963 Jul 12 06:07:56 PM PDT 24 Jul 12 06:09:00 PM PDT 24 88999466 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1365889072 Jul 12 06:07:51 PM PDT 24 Jul 12 06:08:54 PM PDT 24 88417319 ps
T439 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1286687636 Jul 12 06:08:14 PM PDT 24 Jul 12 06:09:40 PM PDT 24 3661330343 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.820507912 Jul 12 06:07:52 PM PDT 24 Jul 12 06:09:02 PM PDT 24 5228577830 ps
T441 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.882112103 Jul 12 06:08:05 PM PDT 24 Jul 12 06:09:11 PM PDT 24 516469448 ps
T442 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2820307661 Jul 12 06:08:10 PM PDT 24 Jul 12 06:09:19 PM PDT 24 88911593 ps
T443 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.600718816 Jul 12 06:08:45 PM PDT 24 Jul 12 06:10:15 PM PDT 24 1402743031 ps
T119 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1852041904 Jul 12 06:08:02 PM PDT 24 Jul 12 06:10:19 PM PDT 24 1265907472 ps
T444 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3839668893 Jul 12 06:08:14 PM PDT 24 Jul 12 06:09:31 PM PDT 24 2303315185 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.558792526 Jul 12 06:07:57 PM PDT 24 Jul 12 06:09:55 PM PDT 24 12645599545 ps
T127 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.924794540 Jul 12 06:07:47 PM PDT 24 Jul 12 06:10:04 PM PDT 24 8541181059 ps
T89 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1928156648 Jul 12 06:08:07 PM PDT 24 Jul 12 06:09:17 PM PDT 24 786060096 ps
T446 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3603014298 Jul 12 06:08:34 PM PDT 24 Jul 12 06:10:23 PM PDT 24 3899433940 ps
T447 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1040611775 Jul 12 06:08:22 PM PDT 24 Jul 12 06:09:47 PM PDT 24 2082326376 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.278840227 Jul 12 06:07:51 PM PDT 24 Jul 12 06:09:04 PM PDT 24 1822270593 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.356061096 Jul 12 06:07:57 PM PDT 24 Jul 12 06:09:09 PM PDT 24 3929266787 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3181266424 Jul 12 06:07:55 PM PDT 24 Jul 12 06:09:05 PM PDT 24 1243791576 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3688668006 Jul 12 06:07:59 PM PDT 24 Jul 12 06:09:06 PM PDT 24 453124074 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1973200014 Jul 12 06:08:00 PM PDT 24 Jul 12 06:09:18 PM PDT 24 2124295496 ps
T453 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2542159798 Jul 12 06:08:27 PM PDT 24 Jul 12 06:09:48 PM PDT 24 786255160 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2518402665 Jul 12 06:07:57 PM PDT 24 Jul 12 06:09:03 PM PDT 24 89757111 ps
T455 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1684130669 Jul 12 06:08:37 PM PDT 24 Jul 12 06:09:56 PM PDT 24 347532282 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1453467862 Jul 12 06:08:03 PM PDT 24 Jul 12 06:09:22 PM PDT 24 1625376694 ps
T457 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1274543056 Jul 12 06:08:27 PM PDT 24 Jul 12 06:09:58 PM PDT 24 6574951542 ps
T458 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2287813609 Jul 12 06:08:01 PM PDT 24 Jul 12 06:09:13 PM PDT 24 579518030 ps
T459 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2252559962 Jul 12 06:08:36 PM PDT 24 Jul 12 06:10:05 PM PDT 24 5727803490 ps
T460 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.343419559 Jul 12 06:08:38 PM PDT 24 Jul 12 06:09:55 PM PDT 24 209920134 ps
T461 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2854094317 Jul 12 06:08:05 PM PDT 24 Jul 12 06:09:13 PM PDT 24 90532777 ps
T462 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2086369734 Jul 12 06:07:50 PM PDT 24 Jul 12 06:09:03 PM PDT 24 6472405192 ps

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1036985236
Short name T5
Test name
Test status
Simulation time 36967502337 ps
CPU time 378.66 seconds
Started Jul 12 05:46:20 PM PDT 24
Finished Jul 12 05:52:40 PM PDT 24
Peak memory 234956 kb
Host smart-fecb0dfd-7412-462e-9539-31e44f14c21e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036985236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1036985236
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.938060767
Short name T16
Test name
Test status
Simulation time 17958137842 ps
CPU time 715.3 seconds
Started Jul 12 05:46:09 PM PDT 24
Finished Jul 12 05:58:06 PM PDT 24
Peak memory 227652 kb
Host smart-9c492494-47c1-4f9f-859e-09391c6ff340
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938060767 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.938060767
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2904602073
Short name T4
Test name
Test status
Simulation time 1098579054 ps
CPU time 15.98 seconds
Started Jul 12 05:46:33 PM PDT 24
Finished Jul 12 05:46:50 PM PDT 24
Peak memory 213440 kb
Host smart-93a3f621-0f82-45c5-a7b1-e8cd1c8f7eae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904602073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2904602073
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.283794472
Short name T19
Test name
Test status
Simulation time 8624626580 ps
CPU time 21.09 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:39 PM PDT 24
Peak memory 214620 kb
Host smart-32547b3b-45d7-4e3d-9c1d-077c901650a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283794472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.283794472
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2181771711
Short name T46
Test name
Test status
Simulation time 13410824803 ps
CPU time 109.4 seconds
Started Jul 12 05:46:56 PM PDT 24
Finished Jul 12 05:48:46 PM PDT 24
Peak memory 232768 kb
Host smart-8b9345d0-f1e3-4d59-beb2-fdae615af90e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181771711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2181771711
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.839914800
Short name T116
Test name
Test status
Simulation time 1035308212 ps
CPU time 68.57 seconds
Started Jul 12 06:08:27 PM PDT 24
Finished Jul 12 06:10:48 PM PDT 24
Peak memory 212324 kb
Host smart-1f4c0f9c-60e0-4645-a27a-ef0f79a15ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839914800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.839914800
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.724858574
Short name T50
Test name
Test status
Simulation time 1431883309 ps
CPU time 89.02 seconds
Started Jul 12 05:47:15 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 238928 kb
Host smart-2b69dd23-75e3-4b26-b760-23c3a7110110
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724858574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.724858574
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2419244138
Short name T23
Test name
Test status
Simulation time 12878320216 ps
CPU time 63.48 seconds
Started Jul 12 05:46:10 PM PDT 24
Finished Jul 12 05:47:14 PM PDT 24
Peak memory 236896 kb
Host smart-683a82b5-98be-46ae-90a7-a44521b22de3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419244138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2419244138
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3029236124
Short name T68
Test name
Test status
Simulation time 8592916036 ps
CPU time 64.5 seconds
Started Jul 12 06:08:23 PM PDT 24
Finished Jul 12 06:10:35 PM PDT 24
Peak memory 210736 kb
Host smart-ff306e20-c889-431d-a880-52213963439b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029236124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3029236124
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.200050622
Short name T117
Test name
Test status
Simulation time 463190895 ps
CPU time 68.66 seconds
Started Jul 12 06:08:21 PM PDT 24
Finished Jul 12 06:10:38 PM PDT 24
Peak memory 218840 kb
Host smart-7c7c25d5-90e5-4584-8c8a-a4136ac8b8a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200050622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.200050622
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1928141742
Short name T58
Test name
Test status
Simulation time 174994605 ps
CPU time 4.22 seconds
Started Jul 12 05:46:20 PM PDT 24
Finished Jul 12 05:46:25 PM PDT 24
Peak memory 211332 kb
Host smart-3e817680-d1fa-41af-b0dc-5c40d73884f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928141742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1928141742
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1920817628
Short name T137
Test name
Test status
Simulation time 170382974 ps
CPU time 9.55 seconds
Started Jul 12 05:46:17 PM PDT 24
Finished Jul 12 05:46:28 PM PDT 24
Peak memory 211944 kb
Host smart-83b1f6eb-d720-429c-9004-b1a75526fe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920817628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1920817628
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4047313349
Short name T47
Test name
Test status
Simulation time 2477843684 ps
CPU time 24.14 seconds
Started Jul 12 05:46:19 PM PDT 24
Finished Jul 12 05:46:44 PM PDT 24
Peak memory 211916 kb
Host smart-1ea4bde8-8ebb-4d5f-b3fc-74e5a67a266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047313349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4047313349
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1386380372
Short name T124
Test name
Test status
Simulation time 4380677851 ps
CPU time 78 seconds
Started Jul 12 06:07:45 PM PDT 24
Finished Jul 12 06:10:00 PM PDT 24
Peak memory 218892 kb
Host smart-b1c04736-11ee-4df0-9297-66a7cfa4551f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386380372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1386380372
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3275013704
Short name T85
Test name
Test status
Simulation time 6069170318 ps
CPU time 23.82 seconds
Started Jul 12 06:08:23 PM PDT 24
Finished Jul 12 06:09:55 PM PDT 24
Peak memory 217860 kb
Host smart-785fa2ba-3829-4cc3-b61d-6648722abef8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275013704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3275013704
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4044634262
Short name T111
Test name
Test status
Simulation time 2115395045 ps
CPU time 11.47 seconds
Started Jul 12 05:46:22 PM PDT 24
Finished Jul 12 05:46:34 PM PDT 24
Peak memory 211360 kb
Host smart-62139c7e-c914-4f0f-aacf-55c93ea53d06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044634262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4044634262
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1986582645
Short name T54
Test name
Test status
Simulation time 260838617336 ps
CPU time 4961.58 seconds
Started Jul 12 05:46:34 PM PDT 24
Finished Jul 12 07:09:17 PM PDT 24
Peak memory 252200 kb
Host smart-4d5a6c05-88b6-40e5-93e0-eeb3ea60b2f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986582645 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1986582645
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.924794540
Short name T127
Test name
Test status
Simulation time 8541181059 ps
CPU time 78.77 seconds
Started Jul 12 06:07:47 PM PDT 24
Finished Jul 12 06:10:04 PM PDT 24
Peak memory 218976 kb
Host smart-70c7a535-5baa-46cf-9852-cd390eb42a06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924794540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.924794540
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3747275598
Short name T92
Test name
Test status
Simulation time 379051786 ps
CPU time 5.33 seconds
Started Jul 12 05:47:18 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 211384 kb
Host smart-14051519-7382-4d4e-bde5-6e9138b2641e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747275598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3747275598
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2344384262
Short name T82
Test name
Test status
Simulation time 369500135 ps
CPU time 10.33 seconds
Started Jul 12 05:46:21 PM PDT 24
Finished Jul 12 05:46:32 PM PDT 24
Peak memory 213132 kb
Host smart-556b7560-bf5d-48df-a82f-cdedff2f6b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344384262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2344384262
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.419211378
Short name T105
Test name
Test status
Simulation time 379343600 ps
CPU time 4.34 seconds
Started Jul 12 06:07:49 PM PDT 24
Finished Jul 12 06:08:51 PM PDT 24
Peak memory 210716 kb
Host smart-a268af6e-b520-474f-aabd-21581a03176a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419211378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.419211378
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2313059028
Short name T379
Test name
Test status
Simulation time 899380061 ps
CPU time 9.76 seconds
Started Jul 12 06:07:44 PM PDT 24
Finished Jul 12 06:08:51 PM PDT 24
Peak memory 218164 kb
Host smart-0ffa2360-176b-466e-8608-263d8df62cf1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313059028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2313059028
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3955297805
Short name T374
Test name
Test status
Simulation time 92953513 ps
CPU time 5.82 seconds
Started Jul 12 06:07:49 PM PDT 24
Finished Jul 12 06:08:52 PM PDT 24
Peak memory 210708 kb
Host smart-fce43af2-0b83-402d-a301-f218463cdc2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955297805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3955297805
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2034955365
Short name T65
Test name
Test status
Simulation time 4359226008 ps
CPU time 17.17 seconds
Started Jul 12 06:07:43 PM PDT 24
Finished Jul 12 06:08:58 PM PDT 24
Peak memory 218980 kb
Host smart-04d78836-ae85-4bd6-bf79-8a595f6285b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034955365 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2034955365
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2264393520
Short name T74
Test name
Test status
Simulation time 28616474326 ps
CPU time 15.1 seconds
Started Jul 12 06:07:44 PM PDT 24
Finished Jul 12 06:08:57 PM PDT 24
Peak memory 210712 kb
Host smart-b596fde0-2bee-4278-a9ac-c85b19abfc35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264393520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2264393520
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.521283079
Short name T401
Test name
Test status
Simulation time 3833166967 ps
CPU time 15.58 seconds
Started Jul 12 06:07:46 PM PDT 24
Finished Jul 12 06:08:58 PM PDT 24
Peak memory 210616 kb
Host smart-1c3e7989-6eaa-42d2-8d97-dac0b9264476
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521283079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.521283079
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2648423655
Short name T434
Test name
Test status
Simulation time 3979921142 ps
CPU time 11.16 seconds
Started Jul 12 06:07:45 PM PDT 24
Finished Jul 12 06:08:53 PM PDT 24
Peak memory 210628 kb
Host smart-2377108e-e3a8-4279-b595-ffabed0b6a52
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648423655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2648423655
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2705459930
Short name T83
Test name
Test status
Simulation time 16462738704 ps
CPU time 71.85 seconds
Started Jul 12 06:07:44 PM PDT 24
Finished Jul 12 06:09:53 PM PDT 24
Peak memory 210848 kb
Host smart-5bb868b7-4892-4899-8fbe-1e636c819bcb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705459930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2705459930
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4110830202
Short name T103
Test name
Test status
Simulation time 6661352976 ps
CPU time 14.89 seconds
Started Jul 12 06:07:45 PM PDT 24
Finished Jul 12 06:08:56 PM PDT 24
Peak memory 211024 kb
Host smart-2e36c363-2e89-4d87-8ed9-895ebcbffec8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110830202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4110830202
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1572114366
Short name T399
Test name
Test status
Simulation time 23069914569 ps
CPU time 18.93 seconds
Started Jul 12 06:07:45 PM PDT 24
Finished Jul 12 06:09:00 PM PDT 24
Peak memory 218984 kb
Host smart-e675dd61-c8c5-4dd6-8097-81db966e0260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572114366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1572114366
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2786559130
Short name T88
Test name
Test status
Simulation time 385007813 ps
CPU time 6.97 seconds
Started Jul 12 06:07:52 PM PDT 24
Finished Jul 12 06:08:58 PM PDT 24
Peak memory 217644 kb
Host smart-06305f54-bf38-4bc1-b961-c16a38791272
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786559130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2786559130
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2893290008
Short name T406
Test name
Test status
Simulation time 1970829089 ps
CPU time 7.77 seconds
Started Jul 12 06:07:50 PM PDT 24
Finished Jul 12 06:08:57 PM PDT 24
Peak memory 217452 kb
Host smart-1d3b870a-b32c-4bb6-92b7-47fadbfa9fd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893290008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2893290008
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3464696296
Short name T373
Test name
Test status
Simulation time 1980581464 ps
CPU time 8.73 seconds
Started Jul 12 06:07:49 PM PDT 24
Finished Jul 12 06:08:55 PM PDT 24
Peak memory 218844 kb
Host smart-eb3b5a39-b9a9-442b-815e-f034b1eec8c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464696296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3464696296
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2086369734
Short name T462
Test name
Test status
Simulation time 6472405192 ps
CPU time 13.86 seconds
Started Jul 12 06:07:50 PM PDT 24
Finished Jul 12 06:09:03 PM PDT 24
Peak memory 219048 kb
Host smart-b0dc70c8-ca88-47d7-b988-3858adcf2fb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086369734 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2086369734
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3582697675
Short name T75
Test name
Test status
Simulation time 1763515009 ps
CPU time 14.22 seconds
Started Jul 12 06:07:49 PM PDT 24
Finished Jul 12 06:09:01 PM PDT 24
Peak memory 210680 kb
Host smart-6d94eabe-b571-4e6a-b82f-7f4077d0ae27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582697675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3582697675
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.791585764
Short name T378
Test name
Test status
Simulation time 184303846 ps
CPU time 5.39 seconds
Started Jul 12 06:07:52 PM PDT 24
Finished Jul 12 06:08:56 PM PDT 24
Peak memory 210544 kb
Host smart-a32d86b6-f756-40c0-bc21-654f378e700a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791585764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.791585764
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3937347591
Short name T376
Test name
Test status
Simulation time 171208742 ps
CPU time 4.2 seconds
Started Jul 12 06:07:50 PM PDT 24
Finished Jul 12 06:08:53 PM PDT 24
Peak memory 210492 kb
Host smart-9f27de56-9b87-4573-920e-e96307476f1c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937347591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3937347591
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.53592580
Short name T377
Test name
Test status
Simulation time 1188500719 ps
CPU time 26.94 seconds
Started Jul 12 06:07:44 PM PDT 24
Finished Jul 12 06:09:08 PM PDT 24
Peak memory 210724 kb
Host smart-303bda07-03fa-436f-a7e0-ed4da2266df5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53592580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pass
thru_mem_tl_intg_err.53592580
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.278840227
Short name T448
Test name
Test status
Simulation time 1822270593 ps
CPU time 14.39 seconds
Started Jul 12 06:07:51 PM PDT 24
Finished Jul 12 06:09:04 PM PDT 24
Peak memory 218548 kb
Host smart-3d2146ca-5983-47e9-b076-8efff9039128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278840227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.278840227
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3317647623
Short name T421
Test name
Test status
Simulation time 1853112586 ps
CPU time 16.38 seconds
Started Jul 12 06:07:50 PM PDT 24
Finished Jul 12 06:09:06 PM PDT 24
Peak memory 218956 kb
Host smart-0714efa1-1fc6-49a5-95f1-b6091387ed9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317647623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3317647623
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3642873387
Short name T411
Test name
Test status
Simulation time 3151616697 ps
CPU time 6.28 seconds
Started Jul 12 06:08:22 PM PDT 24
Finished Jul 12 06:09:36 PM PDT 24
Peak memory 218960 kb
Host smart-eebb942c-4f3e-4df8-bd2c-2ab6601bd22a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642873387 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3642873387
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2391167770
Short name T426
Test name
Test status
Simulation time 1800381188 ps
CPU time 7.05 seconds
Started Jul 12 06:08:22 PM PDT 24
Finished Jul 12 06:09:37 PM PDT 24
Peak memory 210700 kb
Host smart-2379b28a-9175-4a96-bcb0-0c92865c9d2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391167770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2391167770
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2652214756
Short name T73
Test name
Test status
Simulation time 577967901 ps
CPU time 28.2 seconds
Started Jul 12 06:08:15 PM PDT 24
Finished Jul 12 06:09:51 PM PDT 24
Peak memory 210712 kb
Host smart-9d4e0a68-5c75-46df-a8e9-4ec8b5402d84
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652214756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2652214756
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1040611775
Short name T447
Test name
Test status
Simulation time 2082326376 ps
CPU time 17.67 seconds
Started Jul 12 06:08:22 PM PDT 24
Finished Jul 12 06:09:47 PM PDT 24
Peak memory 210732 kb
Host smart-5f8e9952-9c3c-41b5-8ba8-73a046e6392f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040611775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1040611775
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1286687636
Short name T439
Test name
Test status
Simulation time 3661330343 ps
CPU time 17.48 seconds
Started Jul 12 06:08:14 PM PDT 24
Finished Jul 12 06:09:40 PM PDT 24
Peak memory 219028 kb
Host smart-2331da34-0317-499a-b586-7438e4c0ba1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286687636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1286687636
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3043960178
Short name T123
Test name
Test status
Simulation time 1946682195 ps
CPU time 46.32 seconds
Started Jul 12 06:08:23 PM PDT 24
Finished Jul 12 06:10:17 PM PDT 24
Peak memory 218872 kb
Host smart-160dd78d-011f-4431-ad8e-ad89a504a494
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043960178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3043960178
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.433410306
Short name T388
Test name
Test status
Simulation time 9666627921 ps
CPU time 16.08 seconds
Started Jul 12 06:08:23 PM PDT 24
Finished Jul 12 06:09:47 PM PDT 24
Peak memory 212828 kb
Host smart-80067817-f735-480c-8bb9-2d0946348ad2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433410306 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.433410306
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3029406084
Short name T385
Test name
Test status
Simulation time 332501476 ps
CPU time 4.18 seconds
Started Jul 12 06:08:22 PM PDT 24
Finished Jul 12 06:09:34 PM PDT 24
Peak memory 218056 kb
Host smart-f7eb4649-f0e8-40d1-97fa-93df22b32f7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029406084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3029406084
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3208171268
Short name T410
Test name
Test status
Simulation time 2301700469 ps
CPU time 8.32 seconds
Started Jul 12 06:08:22 PM PDT 24
Finished Jul 12 06:09:38 PM PDT 24
Peak memory 218300 kb
Host smart-af2b1d73-113d-44b3-9ae1-d49ef6d795b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208171268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3208171268
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.823536928
Short name T402
Test name
Test status
Simulation time 7116185071 ps
CPU time 17.88 seconds
Started Jul 12 06:08:22 PM PDT 24
Finished Jul 12 06:09:48 PM PDT 24
Peak memory 218984 kb
Host smart-188d2c43-89de-4944-bc0f-0b761f7f0d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823536928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.823536928
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2921247828
Short name T366
Test name
Test status
Simulation time 426669509 ps
CPU time 5.2 seconds
Started Jul 12 06:08:20 PM PDT 24
Finished Jul 12 06:09:34 PM PDT 24
Peak memory 218976 kb
Host smart-fcfd8f7f-b0ba-4d01-b1c2-c757557f21b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921247828 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2921247828
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.635965961
Short name T107
Test name
Test status
Simulation time 1779019843 ps
CPU time 9.12 seconds
Started Jul 12 06:08:21 PM PDT 24
Finished Jul 12 06:09:38 PM PDT 24
Peak memory 210688 kb
Host smart-23a874ec-f63a-4a7e-985d-5a2b35e5306c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635965961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.635965961
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4162579618
Short name T69
Test name
Test status
Simulation time 46473805241 ps
CPU time 73.92 seconds
Started Jul 12 06:08:23 PM PDT 24
Finished Jul 12 06:10:45 PM PDT 24
Peak memory 217840 kb
Host smart-f40e6dac-ce8e-430f-b518-5c051dfa0b44
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162579618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4162579618
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3646541908
Short name T433
Test name
Test status
Simulation time 6215398713 ps
CPU time 13.35 seconds
Started Jul 12 06:08:24 PM PDT 24
Finished Jul 12 06:09:45 PM PDT 24
Peak memory 218956 kb
Host smart-62cd77de-333b-47cf-b515-abd9acf51405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646541908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3646541908
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2008696369
Short name T370
Test name
Test status
Simulation time 3187747759 ps
CPU time 17.85 seconds
Started Jul 12 06:08:23 PM PDT 24
Finished Jul 12 06:09:49 PM PDT 24
Peak memory 219040 kb
Host smart-940cbc49-ccc7-4bf0-9e29-20d69a204311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008696369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2008696369
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.883695947
Short name T118
Test name
Test status
Simulation time 4721751022 ps
CPU time 71.88 seconds
Started Jul 12 06:08:20 PM PDT 24
Finished Jul 12 06:10:40 PM PDT 24
Peak memory 218936 kb
Host smart-10054a60-c838-4e9a-9ce2-e8760eea0765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883695947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.883695947
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2195390669
Short name T416
Test name
Test status
Simulation time 6878367560 ps
CPU time 14.03 seconds
Started Jul 12 06:08:28 PM PDT 24
Finished Jul 12 06:09:53 PM PDT 24
Peak memory 218988 kb
Host smart-741fd6f3-3894-44f8-8803-98828ff5e279
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195390669 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2195390669
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2325515876
Short name T70
Test name
Test status
Simulation time 29640547928 ps
CPU time 14.66 seconds
Started Jul 12 06:08:29 PM PDT 24
Finished Jul 12 06:09:54 PM PDT 24
Peak memory 210732 kb
Host smart-bf89b217-7eb7-4202-abb8-35972ce4b522
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325515876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2325515876
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1454356611
Short name T104
Test name
Test status
Simulation time 9027934075 ps
CPU time 14.08 seconds
Started Jul 12 06:08:32 PM PDT 24
Finished Jul 12 06:09:56 PM PDT 24
Peak memory 218780 kb
Host smart-53b9fbb3-0285-417c-a499-03c4626a3e3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454356611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1454356611
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1530192233
Short name T393
Test name
Test status
Simulation time 8632172196 ps
CPU time 16.49 seconds
Started Jul 12 06:08:23 PM PDT 24
Finished Jul 12 06:09:48 PM PDT 24
Peak memory 219024 kb
Host smart-c796bf01-7215-418f-8e26-285345b4d63a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530192233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1530192233
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4285276791
Short name T407
Test name
Test status
Simulation time 7082745318 ps
CPU time 43.45 seconds
Started Jul 12 06:08:29 PM PDT 24
Finished Jul 12 06:10:23 PM PDT 24
Peak memory 212416 kb
Host smart-dcb5cda8-fb31-4aa0-9070-3ee97329a954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285276791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4285276791
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.707265568
Short name T435
Test name
Test status
Simulation time 1085929631 ps
CPU time 6.06 seconds
Started Jul 12 06:08:32 PM PDT 24
Finished Jul 12 06:09:48 PM PDT 24
Peak memory 218964 kb
Host smart-712b9dc8-88f4-4c12-94ae-40e0e4f2e1f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707265568 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.707265568
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.155033441
Short name T72
Test name
Test status
Simulation time 1634601550 ps
CPU time 13.09 seconds
Started Jul 12 06:08:32 PM PDT 24
Finished Jul 12 06:09:55 PM PDT 24
Peak memory 210648 kb
Host smart-508a2297-3669-4a80-932d-2325a36a53bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155033441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.155033441
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.734154844
Short name T109
Test name
Test status
Simulation time 735880716 ps
CPU time 18.75 seconds
Started Jul 12 06:08:32 PM PDT 24
Finished Jul 12 06:10:00 PM PDT 24
Peak memory 210508 kb
Host smart-25c3e656-700d-4733-8866-69b913539132
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734154844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.734154844
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.918984040
Short name T429
Test name
Test status
Simulation time 89258727 ps
CPU time 4.35 seconds
Started Jul 12 06:08:28 PM PDT 24
Finished Jul 12 06:09:44 PM PDT 24
Peak memory 210740 kb
Host smart-7387d507-a895-499b-b2c0-13a5da8d0405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918984040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.918984040
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1274543056
Short name T457
Test name
Test status
Simulation time 6574951542 ps
CPU time 18.93 seconds
Started Jul 12 06:08:27 PM PDT 24
Finished Jul 12 06:09:58 PM PDT 24
Peak memory 218980 kb
Host smart-aaaa1d51-ef7d-413e-b769-65dd953c67f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274543056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1274543056
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3299344397
Short name T403
Test name
Test status
Simulation time 1146775311 ps
CPU time 6.77 seconds
Started Jul 12 06:08:27 PM PDT 24
Finished Jul 12 06:09:46 PM PDT 24
Peak memory 218948 kb
Host smart-1c45ae9c-1be7-4e35-b8c8-18170a3ac95f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299344397 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3299344397
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3189864086
Short name T108
Test name
Test status
Simulation time 18101937412 ps
CPU time 15.42 seconds
Started Jul 12 06:08:30 PM PDT 24
Finished Jul 12 06:09:57 PM PDT 24
Peak memory 210716 kb
Host smart-e7c2a2dd-98ee-4ab1-b3b8-b874aeefdf9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189864086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3189864086
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1521026592
Short name T106
Test name
Test status
Simulation time 27106533463 ps
CPU time 56.19 seconds
Started Jul 12 06:08:28 PM PDT 24
Finished Jul 12 06:10:36 PM PDT 24
Peak memory 210720 kb
Host smart-d318e2ae-5244-4c4f-a599-6dc44d9e1389
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521026592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1521026592
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2542159798
Short name T453
Test name
Test status
Simulation time 786255160 ps
CPU time 8.27 seconds
Started Jul 12 06:08:27 PM PDT 24
Finished Jul 12 06:09:48 PM PDT 24
Peak memory 210768 kb
Host smart-0e51c7b6-a62f-422c-9524-d07a5276059f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542159798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2542159798
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2263171207
Short name T375
Test name
Test status
Simulation time 3779489713 ps
CPU time 16.39 seconds
Started Jul 12 06:08:29 PM PDT 24
Finished Jul 12 06:09:56 PM PDT 24
Peak memory 219228 kb
Host smart-61a6325c-40fb-4c29-9da6-a03b526d4f33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263171207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2263171207
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1580477061
Short name T120
Test name
Test status
Simulation time 204048620 ps
CPU time 38.66 seconds
Started Jul 12 06:08:32 PM PDT 24
Finished Jul 12 06:10:20 PM PDT 24
Peak memory 212232 kb
Host smart-bb9dc827-ee97-4d83-a855-8c601c6697a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580477061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1580477061
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3895385192
Short name T404
Test name
Test status
Simulation time 903750564 ps
CPU time 6.59 seconds
Started Jul 12 06:08:38 PM PDT 24
Finished Jul 12 06:09:56 PM PDT 24
Peak memory 219008 kb
Host smart-553fac04-069d-4353-a1f5-11f39369ce97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895385192 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3895385192
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1626665821
Short name T413
Test name
Test status
Simulation time 2213900102 ps
CPU time 10.95 seconds
Started Jul 12 06:08:34 PM PDT 24
Finished Jul 12 06:09:53 PM PDT 24
Peak memory 210732 kb
Host smart-304bed16-9023-4e41-9fd9-4a30e3112982
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626665821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1626665821
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2191634814
Short name T430
Test name
Test status
Simulation time 1540198162 ps
CPU time 18.47 seconds
Started Jul 12 06:08:28 PM PDT 24
Finished Jul 12 06:09:58 PM PDT 24
Peak memory 210720 kb
Host smart-f60f4b75-7ee7-4e80-be57-37807e02f44f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191634814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2191634814
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3907822552
Short name T101
Test name
Test status
Simulation time 431923983 ps
CPU time 6.92 seconds
Started Jul 12 06:08:36 PM PDT 24
Finished Jul 12 06:09:56 PM PDT 24
Peak memory 210744 kb
Host smart-699fcd0e-f77a-4e07-91db-56393b6f8680
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907822552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3907822552
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2252559962
Short name T459
Test name
Test status
Simulation time 5727803490 ps
CPU time 15.72 seconds
Started Jul 12 06:08:36 PM PDT 24
Finished Jul 12 06:10:05 PM PDT 24
Peak memory 219004 kb
Host smart-64667f93-a8af-4eea-9bd5-b0655cb42b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252559962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2252559962
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1502412419
Short name T121
Test name
Test status
Simulation time 871056612 ps
CPU time 67.86 seconds
Started Jul 12 06:08:34 PM PDT 24
Finished Jul 12 06:10:50 PM PDT 24
Peak memory 218956 kb
Host smart-2cd7b7f3-57e0-4d89-b090-4f8a1f1023c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502412419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1502412419
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.343419559
Short name T460
Test name
Test status
Simulation time 209920134 ps
CPU time 5.23 seconds
Started Jul 12 06:08:38 PM PDT 24
Finished Jul 12 06:09:55 PM PDT 24
Peak memory 218896 kb
Host smart-f4e9c83a-bc3f-4646-a571-57360cf3cc36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343419559 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.343419559
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.322424758
Short name T371
Test name
Test status
Simulation time 7613358778 ps
CPU time 11.21 seconds
Started Jul 12 06:08:35 PM PDT 24
Finished Jul 12 06:09:59 PM PDT 24
Peak memory 218832 kb
Host smart-30f242a6-f36a-4ffa-ac40-c0c9706a7b89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322424758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.322424758
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4273479986
Short name T91
Test name
Test status
Simulation time 34491782483 ps
CPU time 68.15 seconds
Started Jul 12 06:08:36 PM PDT 24
Finished Jul 12 06:10:57 PM PDT 24
Peak memory 210800 kb
Host smart-d5cdaae7-8b61-4bfb-8097-450ada0832aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273479986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4273479986
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3389999059
Short name T423
Test name
Test status
Simulation time 1500270351 ps
CPU time 12.76 seconds
Started Jul 12 06:08:34 PM PDT 24
Finished Jul 12 06:09:55 PM PDT 24
Peak memory 210736 kb
Host smart-1a81263f-e57f-4b59-8fec-1a810147be58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389999059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3389999059
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.480090744
Short name T395
Test name
Test status
Simulation time 1861335985 ps
CPU time 16.41 seconds
Started Jul 12 06:08:35 PM PDT 24
Finished Jul 12 06:10:04 PM PDT 24
Peak memory 218940 kb
Host smart-c66aa653-4d09-415a-aa57-1a34f4439858
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480090744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.480090744
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1859025585
Short name T125
Test name
Test status
Simulation time 1720780948 ps
CPU time 74.62 seconds
Started Jul 12 06:08:34 PM PDT 24
Finished Jul 12 06:10:57 PM PDT 24
Peak memory 212156 kb
Host smart-166c2394-4183-4217-a73d-072d9c74152c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859025585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1859025585
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3103979953
Short name T394
Test name
Test status
Simulation time 1591715268 ps
CPU time 7.24 seconds
Started Jul 12 06:08:36 PM PDT 24
Finished Jul 12 06:09:56 PM PDT 24
Peak memory 218868 kb
Host smart-593422d0-74da-4688-af9c-bc89275e8cfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103979953 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3103979953
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3139767338
Short name T428
Test name
Test status
Simulation time 1817015101 ps
CPU time 9.44 seconds
Started Jul 12 06:08:36 PM PDT 24
Finished Jul 12 06:09:58 PM PDT 24
Peak memory 218400 kb
Host smart-33e11bfc-7761-440f-930a-b948af541e4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139767338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3139767338
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1028751563
Short name T396
Test name
Test status
Simulation time 2556277820 ps
CPU time 36.31 seconds
Started Jul 12 06:08:36 PM PDT 24
Finished Jul 12 06:10:25 PM PDT 24
Peak memory 210752 kb
Host smart-d43ef690-f792-4e62-9578-244a90b67f1a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028751563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1028751563
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3491247181
Short name T77
Test name
Test status
Simulation time 26675549069 ps
CPU time 18.95 seconds
Started Jul 12 06:08:35 PM PDT 24
Finished Jul 12 06:10:06 PM PDT 24
Peak memory 218980 kb
Host smart-bbd517a1-1095-47d8-a7b4-6d9e8fd4214f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491247181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3491247181
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1684130669
Short name T455
Test name
Test status
Simulation time 347532282 ps
CPU time 6.35 seconds
Started Jul 12 06:08:37 PM PDT 24
Finished Jul 12 06:09:56 PM PDT 24
Peak memory 218936 kb
Host smart-fc2b2e62-161e-4c40-87e9-3655cdd9cded
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684130669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1684130669
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3603014298
Short name T446
Test name
Test status
Simulation time 3899433940 ps
CPU time 41.42 seconds
Started Jul 12 06:08:34 PM PDT 24
Finished Jul 12 06:10:23 PM PDT 24
Peak memory 211996 kb
Host smart-967bc783-c8ed-4521-81b0-efcfccbbb77a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603014298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3603014298
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.600718816
Short name T443
Test name
Test status
Simulation time 1402743031 ps
CPU time 12.53 seconds
Started Jul 12 06:08:45 PM PDT 24
Finished Jul 12 06:10:15 PM PDT 24
Peak memory 218744 kb
Host smart-6701595e-c565-404b-9c0a-08a30f63613b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600718816 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.600718816
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3692973634
Short name T409
Test name
Test status
Simulation time 2939463648 ps
CPU time 8.88 seconds
Started Jul 12 06:08:34 PM PDT 24
Finished Jul 12 06:09:51 PM PDT 24
Peak memory 218740 kb
Host smart-5ab4da48-7724-4b3f-88be-4c4294007896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692973634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3692973634
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1802094631
Short name T113
Test name
Test status
Simulation time 39152668533 ps
CPU time 45.91 seconds
Started Jul 12 06:08:37 PM PDT 24
Finished Jul 12 06:10:35 PM PDT 24
Peak memory 210772 kb
Host smart-02ddc653-eb0c-404c-a02e-45f45116c60d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802094631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1802094631
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.449543370
Short name T420
Test name
Test status
Simulation time 1800100554 ps
CPU time 9.61 seconds
Started Jul 12 06:08:42 PM PDT 24
Finished Jul 12 06:10:05 PM PDT 24
Peak memory 218888 kb
Host smart-c519f507-7183-40a8-acf9-1b1a7b24f58e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449543370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.449543370
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2379518955
Short name T398
Test name
Test status
Simulation time 474236378 ps
CPU time 11.43 seconds
Started Jul 12 06:08:36 PM PDT 24
Finished Jul 12 06:10:00 PM PDT 24
Peak memory 218960 kb
Host smart-779ab1be-61ff-4e9a-8eba-c3fe83cee668
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379518955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2379518955
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2994434372
Short name T126
Test name
Test status
Simulation time 2418457517 ps
CPU time 79.46 seconds
Started Jul 12 06:08:38 PM PDT 24
Finished Jul 12 06:11:09 PM PDT 24
Peak memory 218956 kb
Host smart-9aac0173-75de-449c-a382-86aff8e26edb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994434372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2994434372
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.356061096
Short name T449
Test name
Test status
Simulation time 3929266787 ps
CPU time 9.95 seconds
Started Jul 12 06:07:57 PM PDT 24
Finished Jul 12 06:09:09 PM PDT 24
Peak memory 210684 kb
Host smart-6cc5180c-00ba-4984-bca8-49412bedea26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356061096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.356061096
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2518402665
Short name T454
Test name
Test status
Simulation time 89757111 ps
CPU time 4.53 seconds
Started Jul 12 06:07:57 PM PDT 24
Finished Jul 12 06:09:03 PM PDT 24
Peak memory 217340 kb
Host smart-85c57c49-f963-42d8-8ca6-1c32b03f47a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518402665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2518402665
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3677198554
Short name T425
Test name
Test status
Simulation time 90466724 ps
CPU time 5.63 seconds
Started Jul 12 06:08:02 PM PDT 24
Finished Jul 12 06:09:11 PM PDT 24
Peak memory 217800 kb
Host smart-e207fe95-dbf0-4019-9304-1cd8588b17c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677198554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3677198554
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1067133738
Short name T422
Test name
Test status
Simulation time 5541094594 ps
CPU time 12.47 seconds
Started Jul 12 06:08:00 PM PDT 24
Finished Jul 12 06:09:13 PM PDT 24
Peak memory 219072 kb
Host smart-2d528331-19b1-40d6-9303-3d3d49dccb4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067133738 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1067133738
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.556741711
Short name T417
Test name
Test status
Simulation time 14149757612 ps
CPU time 10.59 seconds
Started Jul 12 06:07:56 PM PDT 24
Finished Jul 12 06:09:06 PM PDT 24
Peak memory 218896 kb
Host smart-d9f2fc9e-15e1-45ec-b29e-78fe5f69ba0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556741711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.556741711
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1365889072
Short name T438
Test name
Test status
Simulation time 88417319 ps
CPU time 4.26 seconds
Started Jul 12 06:07:51 PM PDT 24
Finished Jul 12 06:08:54 PM PDT 24
Peak memory 210528 kb
Host smart-884d61e4-f70f-455f-86bf-850152b8a6cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365889072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1365889072
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2262788426
Short name T368
Test name
Test status
Simulation time 571657770 ps
CPU time 7.76 seconds
Started Jul 12 06:07:50 PM PDT 24
Finished Jul 12 06:08:57 PM PDT 24
Peak memory 210580 kb
Host smart-0bb336bc-3089-4582-9897-b23d1c097725
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262788426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2262788426
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2371466636
Short name T86
Test name
Test status
Simulation time 7983068781 ps
CPU time 62.33 seconds
Started Jul 12 06:07:53 PM PDT 24
Finished Jul 12 06:09:53 PM PDT 24
Peak memory 210740 kb
Host smart-f844edae-b692-462a-ba62-8b38f78538d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371466636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2371466636
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3688668006
Short name T451
Test name
Test status
Simulation time 453124074 ps
CPU time 5.85 seconds
Started Jul 12 06:07:59 PM PDT 24
Finished Jul 12 06:09:06 PM PDT 24
Peak memory 210760 kb
Host smart-8a2949e8-f1ba-422e-9dcb-0465708f623d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688668006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3688668006
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.820507912
Short name T440
Test name
Test status
Simulation time 5228577830 ps
CPU time 11.25 seconds
Started Jul 12 06:07:52 PM PDT 24
Finished Jul 12 06:09:02 PM PDT 24
Peak memory 218960 kb
Host smart-14884930-c07a-47a8-8104-df93dec0c757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820507912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.820507912
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4111569823
Short name T62
Test name
Test status
Simulation time 2807250676 ps
CPU time 43.37 seconds
Started Jul 12 06:07:49 PM PDT 24
Finished Jul 12 06:09:30 PM PDT 24
Peak memory 218968 kb
Host smart-f75c1095-a103-4a0b-848b-b398c2997d31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111569823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4111569823
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1039009214
Short name T431
Test name
Test status
Simulation time 88875363 ps
CPU time 4.22 seconds
Started Jul 12 06:07:58 PM PDT 24
Finished Jul 12 06:09:04 PM PDT 24
Peak memory 210548 kb
Host smart-b6c31802-a151-42e5-95aa-9f79f935bc86
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039009214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1039009214
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.247781646
Short name T389
Test name
Test status
Simulation time 4571586826 ps
CPU time 11.04 seconds
Started Jul 12 06:07:55 PM PDT 24
Finished Jul 12 06:09:06 PM PDT 24
Peak memory 210756 kb
Host smart-66e3a409-cef4-4f9f-a550-563e9e370c9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247781646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.247781646
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.252447881
Short name T84
Test name
Test status
Simulation time 795442060 ps
CPU time 7.21 seconds
Started Jul 12 06:07:57 PM PDT 24
Finished Jul 12 06:09:06 PM PDT 24
Peak memory 210516 kb
Host smart-060ac6dd-bb6b-469f-bbb0-ae5ba5e12df7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252447881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.252447881
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1973781110
Short name T432
Test name
Test status
Simulation time 469440021 ps
CPU time 7.75 seconds
Started Jul 12 06:07:56 PM PDT 24
Finished Jul 12 06:09:03 PM PDT 24
Peak memory 214876 kb
Host smart-deb7bc23-b874-406f-9d70-008540dc3961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973781110 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1973781110
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1091014507
Short name T372
Test name
Test status
Simulation time 2056297268 ps
CPU time 15.82 seconds
Started Jul 12 06:07:57 PM PDT 24
Finished Jul 12 06:09:15 PM PDT 24
Peak memory 210680 kb
Host smart-0b2cf546-a8a9-498f-8852-ab21204faf74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091014507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1091014507
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2093442825
Short name T391
Test name
Test status
Simulation time 7337830381 ps
CPU time 14.62 seconds
Started Jul 12 06:08:07 PM PDT 24
Finished Jul 12 06:09:25 PM PDT 24
Peak memory 210628 kb
Host smart-2e9a18c4-b46b-4e74-b4a9-fd3e58776a81
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093442825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2093442825
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.308192963
Short name T437
Test name
Test status
Simulation time 88999466 ps
CPU time 4.15 seconds
Started Jul 12 06:07:56 PM PDT 24
Finished Jul 12 06:09:00 PM PDT 24
Peak memory 210572 kb
Host smart-bb1ec0bc-5e6a-4b0e-9ef2-8e7ab6c75055
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308192963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
308192963
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.838884609
Short name T424
Test name
Test status
Simulation time 8911408982 ps
CPU time 72.8 seconds
Started Jul 12 06:07:57 PM PDT 24
Finished Jul 12 06:10:12 PM PDT 24
Peak memory 210772 kb
Host smart-a085f7be-3958-489b-a4d7-792eaf89bcc1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838884609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.838884609
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3934036175
Short name T408
Test name
Test status
Simulation time 2072637694 ps
CPU time 8.24 seconds
Started Jul 12 06:07:58 PM PDT 24
Finished Jul 12 06:09:08 PM PDT 24
Peak memory 218156 kb
Host smart-05112a3a-293f-4b4f-b288-6d2fa4816985
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934036175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3934036175
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1973200014
Short name T452
Test name
Test status
Simulation time 2124295496 ps
CPU time 17.98 seconds
Started Jul 12 06:08:00 PM PDT 24
Finished Jul 12 06:09:18 PM PDT 24
Peak memory 218952 kb
Host smart-dc8d22fa-8df8-4e6b-899e-b6f52eacce5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973200014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1973200014
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1653037436
Short name T115
Test name
Test status
Simulation time 8274822576 ps
CPU time 77.41 seconds
Started Jul 12 06:07:55 PM PDT 24
Finished Jul 12 06:10:12 PM PDT 24
Peak memory 218976 kb
Host smart-b00bf435-d3ea-4711-a6c4-da8bb498e56b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653037436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1653037436
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4204945084
Short name T419
Test name
Test status
Simulation time 534633476 ps
CPU time 7.8 seconds
Started Jul 12 06:08:03 PM PDT 24
Finished Jul 12 06:09:13 PM PDT 24
Peak memory 217160 kb
Host smart-9dbceaee-74bb-4eae-964f-7b82719417a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204945084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4204945084
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3335952456
Short name T380
Test name
Test status
Simulation time 4117500832 ps
CPU time 8.88 seconds
Started Jul 12 06:08:01 PM PDT 24
Finished Jul 12 06:09:14 PM PDT 24
Peak memory 210756 kb
Host smart-1d3152b1-0ee8-4e1d-97bc-0e3b3d3fa5a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335952456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3335952456
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1453467862
Short name T456
Test name
Test status
Simulation time 1625376694 ps
CPU time 16.53 seconds
Started Jul 12 06:08:03 PM PDT 24
Finished Jul 12 06:09:22 PM PDT 24
Peak memory 210708 kb
Host smart-c78ebda4-c253-41c6-b940-a8161dddea6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453467862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1453467862
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1129401694
Short name T436
Test name
Test status
Simulation time 6333113462 ps
CPU time 13.68 seconds
Started Jul 12 06:08:08 PM PDT 24
Finished Jul 12 06:09:24 PM PDT 24
Peak memory 219016 kb
Host smart-c137b633-1af7-4de5-8c34-d869e428837b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129401694 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1129401694
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2287813609
Short name T458
Test name
Test status
Simulation time 579518030 ps
CPU time 8.02 seconds
Started Jul 12 06:08:01 PM PDT 24
Finished Jul 12 06:09:13 PM PDT 24
Peak memory 210592 kb
Host smart-6ac45b5a-22cf-4bac-a885-5111af7da96b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287813609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2287813609
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3590182718
Short name T386
Test name
Test status
Simulation time 4285572576 ps
CPU time 16.7 seconds
Started Jul 12 06:07:58 PM PDT 24
Finished Jul 12 06:09:16 PM PDT 24
Peak memory 210604 kb
Host smart-b46ca1a5-47f0-4f2a-9cc9-2fa5fb232ff7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590182718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3590182718
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3181266424
Short name T450
Test name
Test status
Simulation time 1243791576 ps
CPU time 10.4 seconds
Started Jul 12 06:07:55 PM PDT 24
Finished Jul 12 06:09:05 PM PDT 24
Peak memory 210552 kb
Host smart-f64c1596-c69a-40bd-beb0-209deafd8936
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181266424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3181266424
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.558792526
Short name T445
Test name
Test status
Simulation time 12645599545 ps
CPU time 55.77 seconds
Started Jul 12 06:07:57 PM PDT 24
Finished Jul 12 06:09:55 PM PDT 24
Peak memory 210928 kb
Host smart-40057fc2-1e01-41a7-abf9-b89315c7fa84
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558792526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.558792526
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1653909597
Short name T414
Test name
Test status
Simulation time 333209257 ps
CPU time 4.25 seconds
Started Jul 12 06:08:03 PM PDT 24
Finished Jul 12 06:09:10 PM PDT 24
Peak memory 218176 kb
Host smart-8432e08d-1008-4f75-aab7-d65b3c05f80e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653909597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1653909597
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.420734717
Short name T418
Test name
Test status
Simulation time 11413377416 ps
CPU time 13.6 seconds
Started Jul 12 06:07:59 PM PDT 24
Finished Jul 12 06:09:14 PM PDT 24
Peak memory 219004 kb
Host smart-c6bb6937-7127-4e29-b2b7-ce9eda442582
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420734717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.420734717
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.494669911
Short name T383
Test name
Test status
Simulation time 10300287776 ps
CPU time 42.93 seconds
Started Jul 12 06:08:02 PM PDT 24
Finished Jul 12 06:09:48 PM PDT 24
Peak memory 218996 kb
Host smart-ad7efdd9-43c3-4499-9d48-cde8af26ed2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494669911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.494669911
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.882112103
Short name T441
Test name
Test status
Simulation time 516469448 ps
CPU time 4.64 seconds
Started Jul 12 06:08:05 PM PDT 24
Finished Jul 12 06:09:11 PM PDT 24
Peak memory 218928 kb
Host smart-1f49d3ba-056b-4ed7-9add-d894a9412bd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882112103 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.882112103
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.600283337
Short name T387
Test name
Test status
Simulation time 3289340069 ps
CPU time 9.39 seconds
Started Jul 12 06:08:05 PM PDT 24
Finished Jul 12 06:09:16 PM PDT 24
Peak memory 218628 kb
Host smart-0a1d0077-ba2e-483c-9252-c358e83570df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600283337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.600283337
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4120752528
Short name T87
Test name
Test status
Simulation time 14066997381 ps
CPU time 60.97 seconds
Started Jul 12 06:08:02 PM PDT 24
Finished Jul 12 06:10:06 PM PDT 24
Peak memory 210732 kb
Host smart-bd89bc40-e72a-4351-982b-8262c8c74342
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120752528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4120752528
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3422494056
Short name T405
Test name
Test status
Simulation time 3359432786 ps
CPU time 13.6 seconds
Started Jul 12 06:08:07 PM PDT 24
Finished Jul 12 06:09:24 PM PDT 24
Peak memory 218932 kb
Host smart-e6bade16-5ee6-4812-aa1d-b07735ca801a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422494056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3422494056
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1025420003
Short name T369
Test name
Test status
Simulation time 2650943209 ps
CPU time 10.08 seconds
Started Jul 12 06:08:02 PM PDT 24
Finished Jul 12 06:09:16 PM PDT 24
Peak memory 219012 kb
Host smart-44e74ff9-5328-4817-8097-fabf6e1d4846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025420003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1025420003
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1852041904
Short name T119
Test name
Test status
Simulation time 1265907472 ps
CPU time 73.72 seconds
Started Jul 12 06:08:02 PM PDT 24
Finished Jul 12 06:10:19 PM PDT 24
Peak memory 212108 kb
Host smart-8acfbf69-08e4-40f1-8a35-14f7d50b82af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852041904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1852041904
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3998711895
Short name T367
Test name
Test status
Simulation time 1123888062 ps
CPU time 11.12 seconds
Started Jul 12 06:08:12 PM PDT 24
Finished Jul 12 06:09:28 PM PDT 24
Peak memory 218920 kb
Host smart-6779c6b5-1a3f-4ab6-bec0-6253b1be0196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998711895 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3998711895
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1545701289
Short name T71
Test name
Test status
Simulation time 9732283481 ps
CPU time 10.87 seconds
Started Jul 12 06:08:05 PM PDT 24
Finished Jul 12 06:09:18 PM PDT 24
Peak memory 210688 kb
Host smart-dee188a3-9af1-4525-a88a-3bad061e8cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545701289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1545701289
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4254410891
Short name T415
Test name
Test status
Simulation time 14324166453 ps
CPU time 73.42 seconds
Started Jul 12 06:08:02 PM PDT 24
Finished Jul 12 06:10:19 PM PDT 24
Peak memory 217928 kb
Host smart-aa0cd6d6-4607-481f-bec1-2d585e46f3bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254410891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.4254410891
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2854094317
Short name T461
Test name
Test status
Simulation time 90532777 ps
CPU time 5.87 seconds
Started Jul 12 06:08:05 PM PDT 24
Finished Jul 12 06:09:13 PM PDT 24
Peak memory 210788 kb
Host smart-992f6bcb-6dff-4d07-b149-ebcf3363f21f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854094317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2854094317
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2388279430
Short name T412
Test name
Test status
Simulation time 8015461005 ps
CPU time 18.79 seconds
Started Jul 12 06:08:04 PM PDT 24
Finished Jul 12 06:09:25 PM PDT 24
Peak memory 219148 kb
Host smart-0e9ef520-11c3-4aab-a1b1-c20f9a862a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388279430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2388279430
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3616922282
Short name T63
Test name
Test status
Simulation time 1659676160 ps
CPU time 45.26 seconds
Started Jul 12 06:08:05 PM PDT 24
Finished Jul 12 06:09:52 PM PDT 24
Peak memory 219084 kb
Host smart-b12d37d5-f291-4c08-a63c-1962ff0f782d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616922282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3616922282
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1784190449
Short name T381
Test name
Test status
Simulation time 1437473302 ps
CPU time 6.64 seconds
Started Jul 12 06:08:10 PM PDT 24
Finished Jul 12 06:09:21 PM PDT 24
Peak memory 218904 kb
Host smart-b74823fb-9c65-47ef-a1ca-39a83aa99209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784190449 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1784190449
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1928156648
Short name T89
Test name
Test status
Simulation time 786060096 ps
CPU time 6.77 seconds
Started Jul 12 06:08:07 PM PDT 24
Finished Jul 12 06:09:17 PM PDT 24
Peak memory 217872 kb
Host smart-b2f1293d-0f82-4a59-a77c-de5d7e3d9d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928156648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1928156648
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1029282129
Short name T382
Test name
Test status
Simulation time 12972373242 ps
CPU time 48 seconds
Started Jul 12 06:08:09 PM PDT 24
Finished Jul 12 06:09:59 PM PDT 24
Peak memory 217836 kb
Host smart-307938d5-71cc-4f2c-9709-4b942bedbd16
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029282129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1029282129
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1034534985
Short name T100
Test name
Test status
Simulation time 1277027892 ps
CPU time 11.45 seconds
Started Jul 12 06:08:09 PM PDT 24
Finished Jul 12 06:09:22 PM PDT 24
Peak memory 218724 kb
Host smart-425c5ae1-a6d8-4120-9014-c340888054fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034534985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1034534985
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4208297532
Short name T390
Test name
Test status
Simulation time 6041940611 ps
CPU time 18.41 seconds
Started Jul 12 06:08:11 PM PDT 24
Finished Jul 12 06:09:34 PM PDT 24
Peak memory 219236 kb
Host smart-c048e3b5-4328-41d9-a671-7782b68f41e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208297532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4208297532
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3944018879
Short name T61
Test name
Test status
Simulation time 328623716 ps
CPU time 36.74 seconds
Started Jul 12 06:08:09 PM PDT 24
Finished Jul 12 06:09:48 PM PDT 24
Peak memory 211996 kb
Host smart-154395b4-386d-41c4-b31c-838111e3d20c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944018879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3944018879
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2925152802
Short name T384
Test name
Test status
Simulation time 1536411860 ps
CPU time 12.25 seconds
Started Jul 12 06:08:10 PM PDT 24
Finished Jul 12 06:09:28 PM PDT 24
Peak memory 218992 kb
Host smart-81f1b046-7bb0-4ffa-968a-e432db7f34a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925152802 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2925152802
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2820307661
Short name T442
Test name
Test status
Simulation time 88911593 ps
CPU time 4.23 seconds
Started Jul 12 06:08:10 PM PDT 24
Finished Jul 12 06:09:19 PM PDT 24
Peak memory 210704 kb
Host smart-492e9afd-4327-4fcb-aa7d-fdb02c67510e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820307661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2820307661
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.590319324
Short name T400
Test name
Test status
Simulation time 7058756046 ps
CPU time 68.29 seconds
Started Jul 12 06:08:11 PM PDT 24
Finished Jul 12 06:10:24 PM PDT 24
Peak memory 210740 kb
Host smart-c0377418-e19e-4e01-8a73-350058e16dc6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590319324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.590319324
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.851851555
Short name T102
Test name
Test status
Simulation time 519341107 ps
CPU time 4.28 seconds
Started Jul 12 06:08:10 PM PDT 24
Finished Jul 12 06:09:20 PM PDT 24
Peak memory 210732 kb
Host smart-06e1b0c9-69b3-4cf8-9707-a7b2cbd0eba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851851555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.851851555
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1899005236
Short name T392
Test name
Test status
Simulation time 2735820109 ps
CPU time 16.72 seconds
Started Jul 12 06:08:10 PM PDT 24
Finished Jul 12 06:09:31 PM PDT 24
Peak memory 219000 kb
Host smart-be9ecffb-4fba-4062-974b-f6c8d28805c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899005236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1899005236
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1616888444
Short name T128
Test name
Test status
Simulation time 15805739631 ps
CPU time 43.77 seconds
Started Jul 12 06:08:09 PM PDT 24
Finished Jul 12 06:09:55 PM PDT 24
Peak memory 212156 kb
Host smart-1be4807d-2af9-407a-9410-0b63307f026a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616888444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1616888444
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1260534357
Short name T397
Test name
Test status
Simulation time 4489897669 ps
CPU time 11.56 seconds
Started Jul 12 06:08:17 PM PDT 24
Finished Jul 12 06:09:35 PM PDT 24
Peak memory 219024 kb
Host smart-8c19d927-54b6-4f11-9945-2275a5347d17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260534357 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1260534357
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3839668893
Short name T444
Test name
Test status
Simulation time 2303315185 ps
CPU time 8.14 seconds
Started Jul 12 06:08:14 PM PDT 24
Finished Jul 12 06:09:31 PM PDT 24
Peak memory 210776 kb
Host smart-b263da84-e334-464c-b536-d89f03ca3c0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839668893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3839668893
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.198146872
Short name T90
Test name
Test status
Simulation time 13775504814 ps
CPU time 38.1 seconds
Started Jul 12 06:08:10 PM PDT 24
Finished Jul 12 06:09:52 PM PDT 24
Peak memory 210784 kb
Host smart-a9d3cdac-17e7-402b-b8d3-299b6259e0f4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198146872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.198146872
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.98158356
Short name T76
Test name
Test status
Simulation time 174218115 ps
CPU time 5.89 seconds
Started Jul 12 06:08:17 PM PDT 24
Finished Jul 12 06:09:30 PM PDT 24
Peak memory 210660 kb
Host smart-baef9b58-4e72-425e-a034-13ce3a07a4da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98158356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctr
l_same_csr_outstanding.98158356
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.832713474
Short name T427
Test name
Test status
Simulation time 2021566449 ps
CPU time 20.39 seconds
Started Jul 12 06:08:15 PM PDT 24
Finished Jul 12 06:09:43 PM PDT 24
Peak memory 218924 kb
Host smart-be990160-6285-4c9e-a7df-580cf4d50b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832713474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.832713474
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3085566482
Short name T122
Test name
Test status
Simulation time 1087269628 ps
CPU time 71.81 seconds
Started Jul 12 06:08:14 PM PDT 24
Finished Jul 12 06:10:34 PM PDT 24
Peak memory 218948 kb
Host smart-7ff7e8fa-b9d5-472d-8042-0699fb6e5dae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085566482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3085566482
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.43823303
Short name T213
Test name
Test status
Simulation time 89231431 ps
CPU time 4.4 seconds
Started Jul 12 05:46:11 PM PDT 24
Finished Jul 12 05:46:16 PM PDT 24
Peak memory 211252 kb
Host smart-42b6d62f-b2ee-4112-909c-c19b25f9a19f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43823303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.43823303
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.409390544
Short name T237
Test name
Test status
Simulation time 62086000887 ps
CPU time 191.92 seconds
Started Jul 12 05:46:13 PM PDT 24
Finished Jul 12 05:49:26 PM PDT 24
Peak memory 212824 kb
Host smart-1314884d-9f6e-4ec0-9558-187741ccdb0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409390544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.409390544
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.341835021
Short name T363
Test name
Test status
Simulation time 175719243 ps
CPU time 9.4 seconds
Started Jul 12 05:47:56 PM PDT 24
Finished Jul 12 05:48:07 PM PDT 24
Peak memory 212284 kb
Host smart-0c4215a8-e541-4e57-9602-b102a9a4b97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341835021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.341835021
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4078867059
Short name T254
Test name
Test status
Simulation time 1355035625 ps
CPU time 7.85 seconds
Started Jul 12 05:46:07 PM PDT 24
Finished Jul 12 05:46:16 PM PDT 24
Peak memory 211336 kb
Host smart-3b6cb4e7-12a5-4ad8-a21a-1493144dd29f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078867059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4078867059
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.950545471
Short name T28
Test name
Test status
Simulation time 1844831337 ps
CPU time 62.71 seconds
Started Jul 12 05:46:09 PM PDT 24
Finished Jul 12 05:47:13 PM PDT 24
Peak memory 237620 kb
Host smart-6f09ba38-d3bc-4e12-8496-17e3805a3fd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950545471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.950545471
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.873980740
Short name T131
Test name
Test status
Simulation time 5368549959 ps
CPU time 24.49 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:41 PM PDT 24
Peak memory 213848 kb
Host smart-7806f234-937f-41b4-a485-5c7f7ea7867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873980740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.873980740
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.556428464
Short name T162
Test name
Test status
Simulation time 21667505436 ps
CPU time 50.58 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:47:08 PM PDT 24
Peak memory 213900 kb
Host smart-45189e92-429d-47b2-886d-0f9006d9ea9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556428464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.556428464
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.553128910
Short name T212
Test name
Test status
Simulation time 85682969 ps
CPU time 4.36 seconds
Started Jul 12 05:46:08 PM PDT 24
Finished Jul 12 05:46:13 PM PDT 24
Peak memory 211308 kb
Host smart-88f71f47-3bdb-45b2-a01b-e4f36706264b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553128910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.553128910
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2600862887
Short name T298
Test name
Test status
Simulation time 33405700769 ps
CPU time 185.71 seconds
Started Jul 12 05:46:11 PM PDT 24
Finished Jul 12 05:49:17 PM PDT 24
Peak memory 236740 kb
Host smart-c0f54c8e-5dfb-4f86-8a0b-2a784eed7ab5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600862887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2600862887
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2622390062
Short name T185
Test name
Test status
Simulation time 551279262 ps
CPU time 10.34 seconds
Started Jul 12 05:46:08 PM PDT 24
Finished Jul 12 05:46:19 PM PDT 24
Peak memory 217008 kb
Host smart-1164719b-670e-432a-b6d3-f8046da022c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622390062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2622390062
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2866828399
Short name T304
Test name
Test status
Simulation time 97845419 ps
CPU time 5.69 seconds
Started Jul 12 05:46:12 PM PDT 24
Finished Jul 12 05:46:18 PM PDT 24
Peak memory 211368 kb
Host smart-88beebc0-89bf-49f6-b812-ab721e07a053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866828399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2866828399
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.352874150
Short name T24
Test name
Test status
Simulation time 25253184843 ps
CPU time 61.89 seconds
Started Jul 12 05:46:13 PM PDT 24
Finished Jul 12 05:47:16 PM PDT 24
Peak memory 235960 kb
Host smart-799894c9-c45e-478e-ac16-4ae74b982b2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352874150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.352874150
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1769335900
Short name T45
Test name
Test status
Simulation time 9953533293 ps
CPU time 46.63 seconds
Started Jul 12 05:46:11 PM PDT 24
Finished Jul 12 05:46:58 PM PDT 24
Peak memory 213732 kb
Host smart-66b573ef-8950-4e9c-85ee-2b903a61998f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769335900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1769335900
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.432331713
Short name T165
Test name
Test status
Simulation time 488672109 ps
CPU time 4.18 seconds
Started Jul 12 05:46:16 PM PDT 24
Finished Jul 12 05:46:22 PM PDT 24
Peak memory 211332 kb
Host smart-e8f7507c-7e44-4316-8c4c-58a317471480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432331713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.432331713
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.38869049
Short name T3
Test name
Test status
Simulation time 1010439769 ps
CPU time 65.41 seconds
Started Jul 12 05:46:17 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 228384 kb
Host smart-cb57025a-b17a-4af1-b4b7-ea1606390c30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38869049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_co
rrupt_sig_fatal_chk.38869049
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.534254602
Short name T264
Test name
Test status
Simulation time 2519493875 ps
CPU time 25 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:42 PM PDT 24
Peak memory 212012 kb
Host smart-0c042e68-b05b-4ab0-8aa1-0e081ee22099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534254602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.534254602
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3477659678
Short name T193
Test name
Test status
Simulation time 2247577451 ps
CPU time 17.13 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 05:46:32 PM PDT 24
Peak memory 211376 kb
Host smart-42f6cc9f-c6d6-4f09-91ba-4a19ab754909
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477659678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3477659678
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2066920148
Short name T155
Test name
Test status
Simulation time 3361195681 ps
CPU time 12.85 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 05:46:29 PM PDT 24
Peak memory 213984 kb
Host smart-22d74bc9-893d-4f67-815b-07f10a93aad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066920148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2066920148
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.943432871
Short name T173
Test name
Test status
Simulation time 1908606871 ps
CPU time 25.16 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:42 PM PDT 24
Peak memory 215600 kb
Host smart-56fd8865-011b-46d0-abd6-0d003fddfad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943432871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.943432871
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2686775752
Short name T305
Test name
Test status
Simulation time 2004332590 ps
CPU time 15.84 seconds
Started Jul 12 05:46:16 PM PDT 24
Finished Jul 12 05:46:34 PM PDT 24
Peak memory 211204 kb
Host smart-19ac986e-eff1-48d6-a9e9-708a8dd1aac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686775752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2686775752
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3927493280
Short name T42
Test name
Test status
Simulation time 605339475400 ps
CPU time 334.3 seconds
Started Jul 12 05:46:19 PM PDT 24
Finished Jul 12 05:51:55 PM PDT 24
Peak memory 234916 kb
Host smart-cef0955f-1afe-45a0-856a-d431019a7d88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927493280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3927493280
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2179639848
Short name T360
Test name
Test status
Simulation time 4833649458 ps
CPU time 24.87 seconds
Started Jul 12 05:46:20 PM PDT 24
Finished Jul 12 05:46:46 PM PDT 24
Peak memory 212152 kb
Host smart-fbb495f5-77e0-4f10-aeda-8d7a8ff445a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179639848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2179639848
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2037436734
Short name T141
Test name
Test status
Simulation time 4156718244 ps
CPU time 9.75 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 05:46:25 PM PDT 24
Peak memory 211404 kb
Host smart-85dc58d2-1cc2-44b5-a7ea-f18aab881319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037436734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2037436734
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3312420491
Short name T60
Test name
Test status
Simulation time 13797013372 ps
CPU time 29.59 seconds
Started Jul 12 05:46:16 PM PDT 24
Finished Jul 12 05:46:48 PM PDT 24
Peak memory 214520 kb
Host smart-212c86c5-8587-4c46-b963-e67db6c77337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312420491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3312420491
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1176127678
Short name T246
Test name
Test status
Simulation time 7637081345 ps
CPU time 21.23 seconds
Started Jul 12 05:46:16 PM PDT 24
Finished Jul 12 05:46:40 PM PDT 24
Peak memory 214520 kb
Host smart-a719367f-7f1a-41c9-b7db-3df4fcb85e3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176127678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1176127678
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3221188862
Short name T337
Test name
Test status
Simulation time 1150405427 ps
CPU time 10.96 seconds
Started Jul 12 05:46:18 PM PDT 24
Finished Jul 12 05:46:31 PM PDT 24
Peak memory 211284 kb
Host smart-4fc588ff-bac4-468c-8343-e427f30e7453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221188862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3221188862
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3616491786
Short name T38
Test name
Test status
Simulation time 37457787087 ps
CPU time 358.71 seconds
Started Jul 12 05:46:17 PM PDT 24
Finished Jul 12 05:52:17 PM PDT 24
Peak memory 237276 kb
Host smart-4b46c8e8-db11-4b7c-a3be-d2f42ed038c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616491786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3616491786
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3469413774
Short name T260
Test name
Test status
Simulation time 828259163 ps
CPU time 15.33 seconds
Started Jul 12 05:46:17 PM PDT 24
Finished Jul 12 05:46:34 PM PDT 24
Peak memory 211960 kb
Host smart-665821f0-5ed2-41b6-a286-753a9d4f0c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469413774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3469413774
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2153032165
Short name T230
Test name
Test status
Simulation time 2895056172 ps
CPU time 13.94 seconds
Started Jul 12 05:46:17 PM PDT 24
Finished Jul 12 05:46:33 PM PDT 24
Peak memory 211432 kb
Host smart-b35d8bef-754a-4147-a123-e18f7eca0441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2153032165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2153032165
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1935998659
Short name T285
Test name
Test status
Simulation time 3763578277 ps
CPU time 13.89 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 05:46:30 PM PDT 24
Peak memory 212416 kb
Host smart-f1d98fa0-4111-4c7f-a675-7eac056bf023
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935998659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1935998659
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.437595664
Short name T199
Test name
Test status
Simulation time 6194910317 ps
CPU time 80.38 seconds
Started Jul 12 05:46:21 PM PDT 24
Finished Jul 12 05:47:43 PM PDT 24
Peak memory 212596 kb
Host smart-c5d1b185-421d-4746-b823-f85f54890a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437595664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.437595664
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3187320767
Short name T256
Test name
Test status
Simulation time 168733640 ps
CPU time 9.57 seconds
Started Jul 12 05:46:20 PM PDT 24
Finished Jul 12 05:46:30 PM PDT 24
Peak memory 212060 kb
Host smart-31c4b74e-dd96-4c33-8dd6-0f9152e4e5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187320767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3187320767
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3148395118
Short name T176
Test name
Test status
Simulation time 3924738054 ps
CPU time 17 seconds
Started Jul 12 05:46:29 PM PDT 24
Finished Jul 12 05:46:48 PM PDT 24
Peak memory 211548 kb
Host smart-14053dee-c473-47f7-80ba-e68242994d29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148395118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3148395118
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2608772436
Short name T8
Test name
Test status
Simulation time 5993390042 ps
CPU time 25.89 seconds
Started Jul 12 05:46:30 PM PDT 24
Finished Jul 12 05:46:58 PM PDT 24
Peak memory 213828 kb
Host smart-a9ab946b-d0f7-4740-ae5e-ad079ab9cce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608772436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2608772436
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2334420664
Short name T227
Test name
Test status
Simulation time 5509137984 ps
CPU time 15.66 seconds
Started Jul 12 05:46:27 PM PDT 24
Finished Jul 12 05:46:43 PM PDT 24
Peak memory 211288 kb
Host smart-ee17c567-6631-495b-ba1d-75a4fb6444d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334420664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2334420664
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1114623251
Short name T271
Test name
Test status
Simulation time 746930623 ps
CPU time 6.81 seconds
Started Jul 12 05:46:19 PM PDT 24
Finished Jul 12 05:46:27 PM PDT 24
Peak memory 211340 kb
Host smart-df0b64b4-f609-4b6d-a4ed-9dd932489c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114623251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1114623251
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2915657967
Short name T166
Test name
Test status
Simulation time 13777390895 ps
CPU time 13.18 seconds
Started Jul 12 05:46:21 PM PDT 24
Finished Jul 12 05:46:35 PM PDT 24
Peak memory 211356 kb
Host smart-40189351-059e-4ae4-ad52-a691a81cbb63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2915657967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2915657967
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.99240347
Short name T259
Test name
Test status
Simulation time 1516439561 ps
CPU time 15.6 seconds
Started Jul 12 05:46:30 PM PDT 24
Finished Jul 12 05:46:48 PM PDT 24
Peak memory 211452 kb
Host smart-86c2e993-2dcc-4449-9930-2178ab7d4a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99240347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.99240347
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2266102461
Short name T329
Test name
Test status
Simulation time 8613301481 ps
CPU time 83.45 seconds
Started Jul 12 05:46:21 PM PDT 24
Finished Jul 12 05:47:45 PM PDT 24
Peak memory 219364 kb
Host smart-8978fc38-8bba-46f3-9cec-bad4f3afe791
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266102461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2266102461
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1660726385
Short name T9
Test name
Test status
Simulation time 3635943995 ps
CPU time 9.51 seconds
Started Jul 12 05:46:19 PM PDT 24
Finished Jul 12 05:46:30 PM PDT 24
Peak memory 211384 kb
Host smart-146f929e-3997-4d79-ba36-f40daa5d254f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660726385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1660726385
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2964946203
Short name T289
Test name
Test status
Simulation time 10600535876 ps
CPU time 135.91 seconds
Started Jul 12 05:46:24 PM PDT 24
Finished Jul 12 05:48:40 PM PDT 24
Peak memory 234896 kb
Host smart-9f160768-9bf5-409c-b9c4-261fd7e73cf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964946203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2964946203
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3241127511
Short name T359
Test name
Test status
Simulation time 4075244119 ps
CPU time 33.67 seconds
Started Jul 12 05:46:28 PM PDT 24
Finished Jul 12 05:47:03 PM PDT 24
Peak memory 211864 kb
Host smart-789bf599-53dd-48e0-8267-4e20bd1f2285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241127511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3241127511
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.546057963
Short name T197
Test name
Test status
Simulation time 3628771266 ps
CPU time 11.02 seconds
Started Jul 12 05:46:23 PM PDT 24
Finished Jul 12 05:46:34 PM PDT 24
Peak memory 211448 kb
Host smart-8e8a2ccb-c85c-41c5-a237-d0d1176b6e61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=546057963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.546057963
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1642079561
Short name T200
Test name
Test status
Simulation time 3684213121 ps
CPU time 33.82 seconds
Started Jul 12 05:46:18 PM PDT 24
Finished Jul 12 05:46:53 PM PDT 24
Peak memory 213412 kb
Host smart-9ef4c7b6-210a-466c-872a-016c4ea910de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642079561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1642079561
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2746593581
Short name T133
Test name
Test status
Simulation time 7881769058 ps
CPU time 18.12 seconds
Started Jul 12 05:46:20 PM PDT 24
Finished Jul 12 05:46:39 PM PDT 24
Peak memory 212276 kb
Host smart-6fee80af-2e26-4b56-9a84-8a2ccd63a56c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746593581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2746593581
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3041788055
Short name T275
Test name
Test status
Simulation time 6721879566 ps
CPU time 14.44 seconds
Started Jul 12 05:46:28 PM PDT 24
Finished Jul 12 05:46:44 PM PDT 24
Peak memory 211308 kb
Host smart-0da7096a-1127-412c-a9b8-c97dab77bd6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041788055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3041788055
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1681290504
Short name T160
Test name
Test status
Simulation time 5106619784 ps
CPU time 74.89 seconds
Started Jul 12 05:46:26 PM PDT 24
Finished Jul 12 05:47:41 PM PDT 24
Peak memory 212632 kb
Host smart-07898881-2005-415c-b8cc-557d9d9c17a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681290504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1681290504
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2111419115
Short name T142
Test name
Test status
Simulation time 173908047 ps
CPU time 9.41 seconds
Started Jul 12 05:46:21 PM PDT 24
Finished Jul 12 05:46:31 PM PDT 24
Peak memory 211880 kb
Host smart-f5f70ddf-8757-4e58-b172-db5b7e3f5acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111419115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2111419115
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.531802641
Short name T202
Test name
Test status
Simulation time 1243266792 ps
CPU time 9.26 seconds
Started Jul 12 05:46:30 PM PDT 24
Finished Jul 12 05:46:41 PM PDT 24
Peak memory 211472 kb
Host smart-18712aa8-a56a-40c3-80ba-af1bb9692306
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531802641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.531802641
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.764011535
Short name T307
Test name
Test status
Simulation time 176838239 ps
CPU time 10.22 seconds
Started Jul 12 05:46:30 PM PDT 24
Finished Jul 12 05:46:42 PM PDT 24
Peak memory 213332 kb
Host smart-5d4ec40d-df90-442e-89ae-1e1dfae94fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764011535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.764011535
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.228793147
Short name T7
Test name
Test status
Simulation time 14556346934 ps
CPU time 34.13 seconds
Started Jul 12 05:46:27 PM PDT 24
Finished Jul 12 05:47:02 PM PDT 24
Peak memory 214752 kb
Host smart-9f841c49-218e-42af-a34d-683ac8ee860d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228793147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.228793147
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3421835629
Short name T203
Test name
Test status
Simulation time 1933819486 ps
CPU time 16.05 seconds
Started Jul 12 05:46:23 PM PDT 24
Finished Jul 12 05:46:39 PM PDT 24
Peak memory 211324 kb
Host smart-522d37b0-b06e-4c57-85b0-d4fd96f2c547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421835629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3421835629
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1432761788
Short name T167
Test name
Test status
Simulation time 13733567389 ps
CPU time 93.35 seconds
Started Jul 12 05:46:24 PM PDT 24
Finished Jul 12 05:47:58 PM PDT 24
Peak memory 237856 kb
Host smart-0a72b9a4-c5cd-4288-b646-0f6af39d6e0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432761788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1432761788
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1609566983
Short name T351
Test name
Test status
Simulation time 9222736688 ps
CPU time 23.3 seconds
Started Jul 12 05:46:22 PM PDT 24
Finished Jul 12 05:46:46 PM PDT 24
Peak memory 212212 kb
Host smart-bdeeda23-a8ad-4a8b-bc28-f9afccccd133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609566983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1609566983
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4000437116
Short name T194
Test name
Test status
Simulation time 7058340274 ps
CPU time 15.33 seconds
Started Jul 12 05:46:27 PM PDT 24
Finished Jul 12 05:46:44 PM PDT 24
Peak memory 211332 kb
Host smart-295719b9-d28b-4d99-967c-2505041c7a4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4000437116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4000437116
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.975857051
Short name T191
Test name
Test status
Simulation time 719959448 ps
CPU time 10.16 seconds
Started Jul 12 05:46:28 PM PDT 24
Finished Jul 12 05:46:39 PM PDT 24
Peak memory 213632 kb
Host smart-17390f34-31ac-49b5-950a-953810223b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975857051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.975857051
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2992123248
Short name T112
Test name
Test status
Simulation time 53847718484 ps
CPU time 67.71 seconds
Started Jul 12 05:46:22 PM PDT 24
Finished Jul 12 05:47:30 PM PDT 24
Peak memory 217344 kb
Host smart-acbe6cf1-27ac-423c-9cbf-a2d14259eac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992123248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2992123248
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3905020407
Short name T263
Test name
Test status
Simulation time 10579787589 ps
CPU time 14.55 seconds
Started Jul 12 05:46:26 PM PDT 24
Finished Jul 12 05:46:41 PM PDT 24
Peak memory 211360 kb
Host smart-e6840c04-9996-4508-b039-caf3e7e5695f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905020407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3905020407
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4125454868
Short name T252
Test name
Test status
Simulation time 111207054879 ps
CPU time 303.94 seconds
Started Jul 12 05:46:26 PM PDT 24
Finished Jul 12 05:51:30 PM PDT 24
Peak memory 224860 kb
Host smart-80abdbc9-31f3-4a19-8029-ab9a45db9646
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125454868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4125454868
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.589780819
Short name T244
Test name
Test status
Simulation time 173658774 ps
CPU time 9.19 seconds
Started Jul 12 05:46:27 PM PDT 24
Finished Jul 12 05:46:36 PM PDT 24
Peak memory 211884 kb
Host smart-7cd78785-2fc8-4155-9fba-a8bc22ecd1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589780819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.589780819
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1310582823
Short name T242
Test name
Test status
Simulation time 7654647571 ps
CPU time 26.91 seconds
Started Jul 12 05:46:27 PM PDT 24
Finished Jul 12 05:46:55 PM PDT 24
Peak memory 214464 kb
Host smart-2425d570-b320-4268-b73c-4c825c0c3773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310582823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1310582823
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1412231547
Short name T97
Test name
Test status
Simulation time 1340219498 ps
CPU time 32.46 seconds
Started Jul 12 05:46:21 PM PDT 24
Finished Jul 12 05:46:55 PM PDT 24
Peak memory 215712 kb
Host smart-64053a3b-c7a8-4c04-a939-4b71e9433340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412231547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1412231547
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1742639768
Short name T174
Test name
Test status
Simulation time 86281110 ps
CPU time 4.28 seconds
Started Jul 12 05:46:26 PM PDT 24
Finished Jul 12 05:46:30 PM PDT 24
Peak memory 211272 kb
Host smart-7d401bcf-8cc6-41fd-b326-73770a491802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742639768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1742639768
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3091696103
Short name T278
Test name
Test status
Simulation time 137763491459 ps
CPU time 310.24 seconds
Started Jul 12 05:46:31 PM PDT 24
Finished Jul 12 05:51:43 PM PDT 24
Peak memory 228656 kb
Host smart-b52180ba-6b99-42ec-a89a-353cdb672898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091696103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3091696103
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.998421821
Short name T161
Test name
Test status
Simulation time 9137645394 ps
CPU time 23.9 seconds
Started Jul 12 05:46:29 PM PDT 24
Finished Jul 12 05:46:54 PM PDT 24
Peak memory 212272 kb
Host smart-3d895592-b084-4209-9045-98ab35b2e3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998421821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.998421821
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.98023113
Short name T159
Test name
Test status
Simulation time 3582232936 ps
CPU time 14.68 seconds
Started Jul 12 05:46:31 PM PDT 24
Finished Jul 12 05:46:47 PM PDT 24
Peak memory 211444 kb
Host smart-3f188114-5747-4ffb-bf55-e01b328ab901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98023113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.98023113
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.223287196
Short name T324
Test name
Test status
Simulation time 1572524269 ps
CPU time 19.76 seconds
Started Jul 12 05:46:31 PM PDT 24
Finished Jul 12 05:46:52 PM PDT 24
Peak memory 213336 kb
Host smart-b097aae1-96fd-4cda-a9a4-0caa4591f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223287196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.223287196
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2304006059
Short name T233
Test name
Test status
Simulation time 739598205 ps
CPU time 21.22 seconds
Started Jul 12 05:46:28 PM PDT 24
Finished Jul 12 05:46:51 PM PDT 24
Peak memory 214976 kb
Host smart-d1c225c0-fd93-4f3c-a550-6c35da1d4931
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304006059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2304006059
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1492050101
Short name T296
Test name
Test status
Simulation time 3166637514 ps
CPU time 13.57 seconds
Started Jul 12 05:46:16 PM PDT 24
Finished Jul 12 05:46:31 PM PDT 24
Peak memory 211400 kb
Host smart-b3d38cab-0a8d-41c1-8602-b483574223e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492050101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1492050101
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2777617760
Short name T297
Test name
Test status
Simulation time 124107494315 ps
CPU time 398.49 seconds
Started Jul 12 05:46:07 PM PDT 24
Finished Jul 12 05:52:47 PM PDT 24
Peak memory 236852 kb
Host smart-7d3c5ecb-d86c-45d8-82cf-897bb41efb69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777617760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2777617760
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.293183052
Short name T228
Test name
Test status
Simulation time 1169803993 ps
CPU time 17.03 seconds
Started Jul 12 05:46:08 PM PDT 24
Finished Jul 12 05:46:26 PM PDT 24
Peak memory 212152 kb
Host smart-64ce7122-4b1d-4522-b8b2-078a7beba29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293183052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.293183052
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2442763466
Short name T239
Test name
Test status
Simulation time 534959433 ps
CPU time 5.4 seconds
Started Jul 12 05:46:12 PM PDT 24
Finished Jul 12 05:46:19 PM PDT 24
Peak memory 211580 kb
Host smart-b1e2c767-13f5-4dca-8353-d2880e3ade8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442763466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2442763466
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2649972279
Short name T135
Test name
Test status
Simulation time 14576072059 ps
CPU time 23.36 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:41 PM PDT 24
Peak memory 214156 kb
Host smart-3c7134d4-1483-4711-89c1-c81eb21e13a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649972279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2649972279
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3691042342
Short name T330
Test name
Test status
Simulation time 44128399378 ps
CPU time 39.67 seconds
Started Jul 12 05:46:12 PM PDT 24
Finished Jul 12 05:46:53 PM PDT 24
Peak memory 216904 kb
Host smart-14b6eeab-9c93-4ec9-ada9-4e871d4aeda1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691042342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3691042342
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1919916783
Short name T328
Test name
Test status
Simulation time 113926853000 ps
CPU time 1480.97 seconds
Started Jul 12 05:46:12 PM PDT 24
Finished Jul 12 06:10:55 PM PDT 24
Peak memory 235832 kb
Host smart-6f03127a-5a76-42c0-87c8-4ae37860a972
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919916783 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1919916783
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1159311503
Short name T35
Test name
Test status
Simulation time 4825871196 ps
CPU time 7.44 seconds
Started Jul 12 05:46:28 PM PDT 24
Finished Jul 12 05:46:38 PM PDT 24
Peak memory 211400 kb
Host smart-208ee95a-20ec-440b-b189-50f5b57341f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159311503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1159311503
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.732590185
Short name T170
Test name
Test status
Simulation time 54940468864 ps
CPU time 279.66 seconds
Started Jul 12 05:46:31 PM PDT 24
Finished Jul 12 05:51:12 PM PDT 24
Peak memory 213652 kb
Host smart-f1dec84f-dc61-464c-9169-b73c1b37442c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732590185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.732590185
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3450933624
Short name T355
Test name
Test status
Simulation time 341276124 ps
CPU time 9.54 seconds
Started Jul 12 05:46:28 PM PDT 24
Finished Jul 12 05:46:40 PM PDT 24
Peak memory 212024 kb
Host smart-a48dd83e-a425-4eb3-aee6-83242a79b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450933624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3450933624
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3795768798
Short name T114
Test name
Test status
Simulation time 1040512512 ps
CPU time 11.55 seconds
Started Jul 12 05:46:28 PM PDT 24
Finished Jul 12 05:46:42 PM PDT 24
Peak memory 211248 kb
Host smart-a9dba412-45d6-4cd5-a073-8bed9b481006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795768798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3795768798
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4003390672
Short name T349
Test name
Test status
Simulation time 2100221618 ps
CPU time 13.21 seconds
Started Jul 12 05:46:26 PM PDT 24
Finished Jul 12 05:46:40 PM PDT 24
Peak memory 213816 kb
Host smart-86b3c120-169a-40b4-89be-8794ed35d0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003390672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4003390672
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.155338690
Short name T15
Test name
Test status
Simulation time 191806765963 ps
CPU time 2010.62 seconds
Started Jul 12 05:46:29 PM PDT 24
Finished Jul 12 06:20:01 PM PDT 24
Peak memory 248724 kb
Host smart-f66701a9-daad-4674-a880-9128c66ed381
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155338690 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.155338690
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.360030933
Short name T312
Test name
Test status
Simulation time 830715094 ps
CPU time 4.33 seconds
Started Jul 12 05:46:26 PM PDT 24
Finished Jul 12 05:46:31 PM PDT 24
Peak memory 211320 kb
Host smart-c827ffaa-a214-4eef-99b2-79bf3a651f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360030933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.360030933
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3941980904
Short name T339
Test name
Test status
Simulation time 2835858554 ps
CPU time 100.17 seconds
Started Jul 12 05:46:29 PM PDT 24
Finished Jul 12 05:48:11 PM PDT 24
Peak memory 233780 kb
Host smart-98b6bc3c-7cdf-47b0-8fbd-4d97860951b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941980904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3941980904
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3249507764
Short name T295
Test name
Test status
Simulation time 4003978658 ps
CPU time 29.7 seconds
Started Jul 12 05:46:29 PM PDT 24
Finished Jul 12 05:47:00 PM PDT 24
Peak memory 211964 kb
Host smart-9cbf4a71-723b-4190-befa-8596f4c7e3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249507764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3249507764
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1128465608
Short name T255
Test name
Test status
Simulation time 2605007135 ps
CPU time 12.58 seconds
Started Jul 12 05:46:29 PM PDT 24
Finished Jul 12 05:46:43 PM PDT 24
Peak memory 211400 kb
Host smart-c61d039a-e329-45c8-b59d-97698d7b6f2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1128465608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1128465608
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.86720540
Short name T365
Test name
Test status
Simulation time 1766917711 ps
CPU time 21.93 seconds
Started Jul 12 05:46:27 PM PDT 24
Finished Jul 12 05:46:50 PM PDT 24
Peak memory 213172 kb
Host smart-8900702a-79a2-4b45-97a3-dc66bacaa08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86720540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.86720540
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1121404265
Short name T110
Test name
Test status
Simulation time 9083485261 ps
CPU time 17.81 seconds
Started Jul 12 05:46:28 PM PDT 24
Finished Jul 12 05:46:48 PM PDT 24
Peak memory 211424 kb
Host smart-39d5ae31-97b4-4cb6-8e53-9772f60e77cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121404265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1121404265
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3451460870
Short name T93
Test name
Test status
Simulation time 3911316986 ps
CPU time 15.31 seconds
Started Jul 12 05:46:28 PM PDT 24
Finished Jul 12 05:46:45 PM PDT 24
Peak memory 211384 kb
Host smart-89c89b79-49f9-4f44-9972-79fd4e4cfdc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451460870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3451460870
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1708352521
Short name T39
Test name
Test status
Simulation time 13934897834 ps
CPU time 236.91 seconds
Started Jul 12 05:46:26 PM PDT 24
Finished Jul 12 05:50:23 PM PDT 24
Peak memory 234376 kb
Host smart-1596c5e0-c585-4297-ad80-70371bf344d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708352521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1708352521
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2894666077
Short name T210
Test name
Test status
Simulation time 4126368368 ps
CPU time 35.9 seconds
Started Jul 12 05:46:29 PM PDT 24
Finished Jul 12 05:47:07 PM PDT 24
Peak memory 211900 kb
Host smart-0f1a6885-513a-4e8d-81de-9a9d77524bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894666077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2894666077
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.881372923
Short name T274
Test name
Test status
Simulation time 1085160225 ps
CPU time 11.27 seconds
Started Jul 12 05:46:24 PM PDT 24
Finished Jul 12 05:46:36 PM PDT 24
Peak memory 211356 kb
Host smart-ffeff92d-9afe-4484-bcc2-8f01c8ec035e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881372923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.881372923
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.4030788709
Short name T6
Test name
Test status
Simulation time 11439765006 ps
CPU time 28.45 seconds
Started Jul 12 05:46:25 PM PDT 24
Finished Jul 12 05:46:53 PM PDT 24
Peak memory 212948 kb
Host smart-41f5c7d8-bcf5-4dd3-babe-642a48ad53e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030788709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.4030788709
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1673306030
Short name T2
Test name
Test status
Simulation time 9027506982 ps
CPU time 28.92 seconds
Started Jul 12 05:46:31 PM PDT 24
Finished Jul 12 05:47:02 PM PDT 24
Peak memory 214600 kb
Host smart-409a4465-9942-45ed-81a1-51f70f071315
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673306030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1673306030
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1200369854
Short name T169
Test name
Test status
Simulation time 909854572 ps
CPU time 7.58 seconds
Started Jul 12 05:46:33 PM PDT 24
Finished Jul 12 05:46:42 PM PDT 24
Peak memory 211320 kb
Host smart-7297c1f6-5bcd-4ac0-9ed1-f49fa8b395fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200369854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1200369854
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3578170571
Short name T146
Test name
Test status
Simulation time 2890498440 ps
CPU time 118.49 seconds
Started Jul 12 05:46:26 PM PDT 24
Finished Jul 12 05:48:25 PM PDT 24
Peak memory 237568 kb
Host smart-6ead9d3b-5446-45d8-8877-4a7451e83f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578170571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3578170571
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1973382349
Short name T163
Test name
Test status
Simulation time 3889253385 ps
CPU time 30.7 seconds
Started Jul 12 05:46:27 PM PDT 24
Finished Jul 12 05:46:58 PM PDT 24
Peak memory 212028 kb
Host smart-4aba9010-1b12-40bf-95f7-d54d67e379ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973382349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1973382349
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3862320049
Short name T171
Test name
Test status
Simulation time 3930363334 ps
CPU time 10.93 seconds
Started Jul 12 05:46:29 PM PDT 24
Finished Jul 12 05:46:42 PM PDT 24
Peak memory 211364 kb
Host smart-390201df-f60f-4ea5-856c-dcec55782b2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3862320049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3862320049
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3131039552
Short name T31
Test name
Test status
Simulation time 16970167213 ps
CPU time 27.29 seconds
Started Jul 12 05:46:29 PM PDT 24
Finished Jul 12 05:46:59 PM PDT 24
Peak memory 214108 kb
Host smart-0e90b85b-1299-4fbf-af83-7cce6a00e378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131039552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3131039552
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2292744558
Short name T13
Test name
Test status
Simulation time 1109421214 ps
CPU time 13.35 seconds
Started Jul 12 05:46:26 PM PDT 24
Finished Jul 12 05:46:40 PM PDT 24
Peak memory 213948 kb
Host smart-822f01c9-a0e8-482b-ada8-f6fd90840c09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292744558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2292744558
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4134468142
Short name T1
Test name
Test status
Simulation time 19630821411 ps
CPU time 16.86 seconds
Started Jul 12 05:46:35 PM PDT 24
Finished Jul 12 05:46:53 PM PDT 24
Peak memory 211384 kb
Host smart-0f1d552a-ca00-4941-9749-03d105c89bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134468142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4134468142
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3855184010
Short name T156
Test name
Test status
Simulation time 69081851740 ps
CPU time 165.22 seconds
Started Jul 12 05:46:33 PM PDT 24
Finished Jul 12 05:49:20 PM PDT 24
Peak memory 237292 kb
Host smart-05107ed8-1911-4330-a93e-8d85a76048ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855184010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3855184010
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3354670463
Short name T216
Test name
Test status
Simulation time 693465086 ps
CPU time 9.5 seconds
Started Jul 12 05:46:34 PM PDT 24
Finished Jul 12 05:46:45 PM PDT 24
Peak memory 212024 kb
Host smart-200af8b5-634a-4745-b02a-46a465553709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354670463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3354670463
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.757316000
Short name T129
Test name
Test status
Simulation time 1857915200 ps
CPU time 7.29 seconds
Started Jul 12 05:46:32 PM PDT 24
Finished Jul 12 05:46:41 PM PDT 24
Peak memory 211300 kb
Host smart-7d239e11-4421-49b4-9424-9acffa48c155
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757316000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.757316000
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3160873287
Short name T358
Test name
Test status
Simulation time 3094683232 ps
CPU time 30.6 seconds
Started Jul 12 05:46:35 PM PDT 24
Finished Jul 12 05:47:07 PM PDT 24
Peak memory 212240 kb
Host smart-368da565-4573-4a55-86be-f077b67c87f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160873287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3160873287
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3233898913
Short name T302
Test name
Test status
Simulation time 11955063591 ps
CPU time 29.92 seconds
Started Jul 12 05:46:37 PM PDT 24
Finished Jul 12 05:47:09 PM PDT 24
Peak memory 216884 kb
Host smart-b5ccdbf8-2c3d-4094-bd92-d5666f24f03d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233898913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3233898913
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2182100725
Short name T293
Test name
Test status
Simulation time 1767216674 ps
CPU time 14.45 seconds
Started Jul 12 05:46:33 PM PDT 24
Finished Jul 12 05:46:49 PM PDT 24
Peak memory 211324 kb
Host smart-608087fb-ff81-4aac-a096-21d1502e19f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182100725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2182100725
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2789592104
Short name T294
Test name
Test status
Simulation time 40330608855 ps
CPU time 280.19 seconds
Started Jul 12 05:46:38 PM PDT 24
Finished Jul 12 05:51:19 PM PDT 24
Peak memory 238420 kb
Host smart-98bf1179-c2bc-4547-9551-28da2b93e976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789592104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2789592104
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.145178316
Short name T221
Test name
Test status
Simulation time 28181130968 ps
CPU time 21.49 seconds
Started Jul 12 05:46:32 PM PDT 24
Finished Jul 12 05:46:55 PM PDT 24
Peak memory 212384 kb
Host smart-d650a758-09c8-4c13-8b50-68fc5a6ab38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145178316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.145178316
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3241236586
Short name T251
Test name
Test status
Simulation time 2693102386 ps
CPU time 12.76 seconds
Started Jul 12 05:46:33 PM PDT 24
Finished Jul 12 05:46:47 PM PDT 24
Peak memory 211448 kb
Host smart-3ac69dd2-71d0-486f-81fe-cda62a3e2bd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241236586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3241236586
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2982916143
Short name T320
Test name
Test status
Simulation time 941899951 ps
CPU time 15.5 seconds
Started Jul 12 05:46:34 PM PDT 24
Finished Jul 12 05:46:50 PM PDT 24
Peak memory 212072 kb
Host smart-32035b80-63b9-447a-9ea7-363a59e6db41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982916143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2982916143
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1001299442
Short name T11
Test name
Test status
Simulation time 2125210685 ps
CPU time 25.7 seconds
Started Jul 12 05:46:38 PM PDT 24
Finished Jul 12 05:47:05 PM PDT 24
Peak memory 215496 kb
Host smart-651c00b8-1c2f-447b-9449-11bd668345a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001299442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1001299442
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.232334965
Short name T188
Test name
Test status
Simulation time 2181225559 ps
CPU time 15.8 seconds
Started Jul 12 05:46:37 PM PDT 24
Finished Jul 12 05:46:54 PM PDT 24
Peak memory 211388 kb
Host smart-1bbbb7f3-cf3b-4db4-83a0-e74a2420658f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232334965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.232334965
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.693696230
Short name T266
Test name
Test status
Simulation time 6638906729 ps
CPU time 101.59 seconds
Started Jul 12 05:46:36 PM PDT 24
Finished Jul 12 05:48:19 PM PDT 24
Peak memory 232768 kb
Host smart-5427da6b-ee4a-4329-a77b-e28283f3b671
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693696230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.693696230
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1052869421
Short name T132
Test name
Test status
Simulation time 792837006 ps
CPU time 9.6 seconds
Started Jul 12 05:46:36 PM PDT 24
Finished Jul 12 05:46:47 PM PDT 24
Peak memory 212136 kb
Host smart-f65e7132-6465-4e33-a627-0fd182a7b2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052869421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1052869421
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1075693534
Short name T245
Test name
Test status
Simulation time 671394618 ps
CPU time 9.69 seconds
Started Jul 12 05:46:36 PM PDT 24
Finished Jul 12 05:46:47 PM PDT 24
Peak memory 211356 kb
Host smart-18d42977-83f8-4d9c-a5f5-9aa771921bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075693534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1075693534
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.652305284
Short name T308
Test name
Test status
Simulation time 2392461674 ps
CPU time 21.28 seconds
Started Jul 12 05:46:33 PM PDT 24
Finished Jul 12 05:46:56 PM PDT 24
Peak memory 212212 kb
Host smart-e4104972-8861-4732-bd84-00b81d1c7c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652305284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.652305284
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1212387401
Short name T225
Test name
Test status
Simulation time 45067454228 ps
CPU time 58.25 seconds
Started Jul 12 05:46:39 PM PDT 24
Finished Jul 12 05:47:39 PM PDT 24
Peak memory 217760 kb
Host smart-872135e9-00d3-4a91-a79c-24fd846711d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212387401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1212387401
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2515464057
Short name T57
Test name
Test status
Simulation time 89424201366 ps
CPU time 892.56 seconds
Started Jul 12 05:46:35 PM PDT 24
Finished Jul 12 06:01:28 PM PDT 24
Peak memory 235784 kb
Host smart-31083483-a548-4e62-bd46-8fc8a83c6378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515464057 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2515464057
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3849493333
Short name T309
Test name
Test status
Simulation time 11208140179 ps
CPU time 11.64 seconds
Started Jul 12 05:46:43 PM PDT 24
Finished Jul 12 05:46:58 PM PDT 24
Peak memory 211296 kb
Host smart-3e1f9671-c9fd-4796-8311-5aac33316c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849493333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3849493333
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.625128475
Short name T49
Test name
Test status
Simulation time 14867712830 ps
CPU time 233.78 seconds
Started Jul 12 05:46:35 PM PDT 24
Finished Jul 12 05:50:31 PM PDT 24
Peak memory 225076 kb
Host smart-6e5d6bdf-7152-4545-8a24-eebbf21f1bad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625128475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.625128475
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3106465624
Short name T204
Test name
Test status
Simulation time 501641307 ps
CPU time 12.92 seconds
Started Jul 12 05:46:33 PM PDT 24
Finished Jul 12 05:46:47 PM PDT 24
Peak memory 211856 kb
Host smart-c55a564d-f80a-4468-b144-df34667b3eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106465624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3106465624
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.680189308
Short name T205
Test name
Test status
Simulation time 2342628848 ps
CPU time 9.98 seconds
Started Jul 12 05:46:39 PM PDT 24
Finished Jul 12 05:46:50 PM PDT 24
Peak memory 211352 kb
Host smart-4f83c85e-e1af-4bac-9d02-77d578e325c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=680189308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.680189308
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.702828802
Short name T79
Test name
Test status
Simulation time 442525760 ps
CPU time 12.8 seconds
Started Jul 12 05:46:38 PM PDT 24
Finished Jul 12 05:46:53 PM PDT 24
Peak memory 213336 kb
Host smart-64ded5db-8c00-478e-9d3f-bdc508613679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702828802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.702828802
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1608235627
Short name T235
Test name
Test status
Simulation time 11861555931 ps
CPU time 59.04 seconds
Started Jul 12 05:46:35 PM PDT 24
Finished Jul 12 05:47:36 PM PDT 24
Peak memory 213720 kb
Host smart-d6a81545-58bb-4b6f-9592-7ef92123fd1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608235627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1608235627
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4236002618
Short name T226
Test name
Test status
Simulation time 86664086 ps
CPU time 4.25 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:46:49 PM PDT 24
Peak memory 211292 kb
Host smart-7671a818-53b8-4bf4-b204-95f0f28ca8d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236002618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4236002618
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1081053620
Short name T32
Test name
Test status
Simulation time 49505291789 ps
CPU time 128.5 seconds
Started Jul 12 05:46:44 PM PDT 24
Finished Jul 12 05:48:56 PM PDT 24
Peak memory 236296 kb
Host smart-e665375c-b47b-44ef-b336-c4a4f382b2ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081053620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1081053620
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3780533867
Short name T215
Test name
Test status
Simulation time 15960221639 ps
CPU time 29.61 seconds
Started Jul 12 05:46:40 PM PDT 24
Finished Jul 12 05:47:12 PM PDT 24
Peak memory 212432 kb
Host smart-8796359e-8a77-49ee-90cf-bba6a5f22d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780533867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3780533867
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.445594363
Short name T150
Test name
Test status
Simulation time 1839437687 ps
CPU time 15.01 seconds
Started Jul 12 05:46:44 PM PDT 24
Finished Jul 12 05:47:03 PM PDT 24
Peak memory 211280 kb
Host smart-7e96d38f-2515-4075-b14f-579117a5bef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=445594363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.445594363
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1210290695
Short name T95
Test name
Test status
Simulation time 378355229 ps
CPU time 9.94 seconds
Started Jul 12 05:46:46 PM PDT 24
Finished Jul 12 05:46:59 PM PDT 24
Peak memory 214028 kb
Host smart-9599362a-1430-4364-b8c0-aa8f6e53b6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210290695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1210290695
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3103171556
Short name T78
Test name
Test status
Simulation time 2270581376 ps
CPU time 25.72 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:47:11 PM PDT 24
Peak memory 215152 kb
Host smart-6d78c572-2750-4fca-b0e1-f4da7affb5b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103171556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3103171556
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3149511269
Short name T217
Test name
Test status
Simulation time 1876634400 ps
CPU time 10.08 seconds
Started Jul 12 05:46:44 PM PDT 24
Finished Jul 12 05:46:57 PM PDT 24
Peak memory 211352 kb
Host smart-2e83954c-3a84-4e31-ae61-1e2741ba7033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149511269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3149511269
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2094812528
Short name T40
Test name
Test status
Simulation time 42612182301 ps
CPU time 237.42 seconds
Started Jul 12 05:46:40 PM PDT 24
Finished Jul 12 05:50:39 PM PDT 24
Peak memory 212932 kb
Host smart-66b5e405-1683-4ed9-a39b-51be042a40e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094812528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2094812528
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2019579719
Short name T183
Test name
Test status
Simulation time 723877824 ps
CPU time 9.49 seconds
Started Jul 12 05:46:44 PM PDT 24
Finished Jul 12 05:46:56 PM PDT 24
Peak memory 212160 kb
Host smart-494a9844-d34a-4180-bd22-11fe6acc252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019579719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2019579719
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.641632412
Short name T282
Test name
Test status
Simulation time 1569708915 ps
CPU time 14.43 seconds
Started Jul 12 05:46:41 PM PDT 24
Finished Jul 12 05:46:57 PM PDT 24
Peak memory 211304 kb
Host smart-b788b43d-dab0-4b32-b357-88a15c483575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641632412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.641632412
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2144206624
Short name T80
Test name
Test status
Simulation time 6498292803 ps
CPU time 32.85 seconds
Started Jul 12 05:46:44 PM PDT 24
Finished Jul 12 05:47:20 PM PDT 24
Peak memory 213720 kb
Host smart-6585a279-4736-4ba2-811c-90e546e30f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144206624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2144206624
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4100960621
Short name T343
Test name
Test status
Simulation time 12481482322 ps
CPU time 34.9 seconds
Started Jul 12 05:46:41 PM PDT 24
Finished Jul 12 05:47:18 PM PDT 24
Peak memory 217536 kb
Host smart-6050f98b-c52c-44c3-9331-c57051da8e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100960621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4100960621
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.567299868
Short name T157
Test name
Test status
Simulation time 1198651860 ps
CPU time 6.39 seconds
Started Jul 12 05:46:12 PM PDT 24
Finished Jul 12 05:46:20 PM PDT 24
Peak memory 211148 kb
Host smart-34fb601b-5cd0-4c0d-8c01-0d17160a1a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567299868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.567299868
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3270672757
Short name T218
Test name
Test status
Simulation time 1063669850 ps
CPU time 76.53 seconds
Started Jul 12 05:46:08 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 228556 kb
Host smart-2ee0d03f-9aff-4924-8071-46836cdafb3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270672757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3270672757
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.623411466
Short name T186
Test name
Test status
Simulation time 15121314173 ps
CPU time 30.82 seconds
Started Jul 12 05:46:08 PM PDT 24
Finished Jul 12 05:46:40 PM PDT 24
Peak memory 212416 kb
Host smart-cdf709d3-e7b6-4fa4-822d-84cfd069174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623411466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.623411466
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3260842203
Short name T353
Test name
Test status
Simulation time 4953635853 ps
CPU time 11.1 seconds
Started Jul 12 05:46:09 PM PDT 24
Finished Jul 12 05:46:21 PM PDT 24
Peak memory 211444 kb
Host smart-c9a7b115-c805-4e48-8eb2-105e2283af47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260842203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3260842203
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3633574241
Short name T22
Test name
Test status
Simulation time 676401405 ps
CPU time 53.77 seconds
Started Jul 12 05:46:09 PM PDT 24
Finished Jul 12 05:47:03 PM PDT 24
Peak memory 235792 kb
Host smart-72df6cb5-1670-43d6-8aea-245f4e0e4172
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633574241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3633574241
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1963197565
Short name T347
Test name
Test status
Simulation time 16470677282 ps
CPU time 31.88 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:50 PM PDT 24
Peak memory 214444 kb
Host smart-a5b48f14-b667-44d9-b25a-a9f4ff5d9058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963197565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1963197565
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3717062392
Short name T364
Test name
Test status
Simulation time 7572346213 ps
CPU time 16.26 seconds
Started Jul 12 05:46:07 PM PDT 24
Finished Jul 12 05:46:24 PM PDT 24
Peak memory 211320 kb
Host smart-d91ee05a-b9d7-444e-9d95-0697bb45c93b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717062392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3717062392
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3149345928
Short name T180
Test name
Test status
Simulation time 1692530932 ps
CPU time 13.8 seconds
Started Jul 12 05:46:39 PM PDT 24
Finished Jul 12 05:46:55 PM PDT 24
Peak memory 211336 kb
Host smart-a16af913-f8e0-44a8-9fad-8a2a11c3539f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149345928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3149345928
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3216207528
Short name T334
Test name
Test status
Simulation time 2343779099 ps
CPU time 141.48 seconds
Started Jul 12 05:46:40 PM PDT 24
Finished Jul 12 05:49:04 PM PDT 24
Peak memory 211800 kb
Host smart-40044a3d-b22a-490c-a62d-420ee7ed1502
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216207528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3216207528
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3105821564
Short name T138
Test name
Test status
Simulation time 239114316 ps
CPU time 9.53 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:46:55 PM PDT 24
Peak memory 211880 kb
Host smart-62f7a8f8-07cc-4f11-8fba-289431fcbda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105821564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3105821564
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3889454334
Short name T147
Test name
Test status
Simulation time 98222816 ps
CPU time 5.44 seconds
Started Jul 12 05:46:40 PM PDT 24
Finished Jul 12 05:46:47 PM PDT 24
Peak memory 211328 kb
Host smart-d9177e61-d4fc-4d3e-b9bc-d5b705bec0c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3889454334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3889454334
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2031660141
Short name T253
Test name
Test status
Simulation time 3452203238 ps
CPU time 17.23 seconds
Started Jul 12 05:46:45 PM PDT 24
Finished Jul 12 05:47:05 PM PDT 24
Peak memory 213600 kb
Host smart-c40705a6-de37-4228-acfd-15f4ede01dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031660141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2031660141
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3893626020
Short name T30
Test name
Test status
Simulation time 314748823 ps
CPU time 16.02 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:47:00 PM PDT 24
Peak memory 215184 kb
Host smart-b4a6140f-122e-4876-983c-8148af683b15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893626020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3893626020
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3076339593
Short name T300
Test name
Test status
Simulation time 6924625774 ps
CPU time 13.67 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:46:58 PM PDT 24
Peak memory 211376 kb
Host smart-f90042ac-0d3e-4967-831e-2913833d77c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076339593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3076339593
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1910902387
Short name T140
Test name
Test status
Simulation time 23608160487 ps
CPU time 145.03 seconds
Started Jul 12 05:46:41 PM PDT 24
Finished Jul 12 05:49:09 PM PDT 24
Peak memory 237884 kb
Host smart-c562cc57-8b40-4d81-acc9-d480d4582935
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910902387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1910902387
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4206598910
Short name T222
Test name
Test status
Simulation time 1360450675 ps
CPU time 18.24 seconds
Started Jul 12 05:46:44 PM PDT 24
Finished Jul 12 05:47:06 PM PDT 24
Peak memory 212048 kb
Host smart-3354c482-983c-419e-ae9b-61ffa183808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206598910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4206598910
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.112399687
Short name T290
Test name
Test status
Simulation time 413401729 ps
CPU time 5.17 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:46:50 PM PDT 24
Peak memory 211360 kb
Host smart-2a40847e-a212-4e45-a4f0-61130f5e0fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112399687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.112399687
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3838228507
Short name T315
Test name
Test status
Simulation time 385677773 ps
CPU time 10.27 seconds
Started Jul 12 05:46:41 PM PDT 24
Finished Jul 12 05:46:54 PM PDT 24
Peak memory 213848 kb
Host smart-7346eb0d-6587-430b-868b-d91f7ac02662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838228507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3838228507
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3061390389
Short name T331
Test name
Test status
Simulation time 615157127 ps
CPU time 20.81 seconds
Started Jul 12 05:46:41 PM PDT 24
Finished Jul 12 05:47:04 PM PDT 24
Peak memory 214304 kb
Host smart-cd20f14b-aa9d-44f7-b2b2-8f913805bd6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061390389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3061390389
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.823188895
Short name T332
Test name
Test status
Simulation time 87679958219 ps
CPU time 2478.66 seconds
Started Jul 12 05:46:46 PM PDT 24
Finished Jul 12 06:28:08 PM PDT 24
Peak memory 241836 kb
Host smart-43e6b4fc-5591-44c7-be14-4e636db35ef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823188895 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.823188895
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2796533315
Short name T33
Test name
Test status
Simulation time 261809367 ps
CPU time 4.27 seconds
Started Jul 12 05:46:41 PM PDT 24
Finished Jul 12 05:46:48 PM PDT 24
Peak memory 211304 kb
Host smart-e6458f31-f309-4702-bdd4-583652c928a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796533315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2796533315
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2084591697
Short name T148
Test name
Test status
Simulation time 27693552724 ps
CPU time 273.43 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:51:18 PM PDT 24
Peak memory 235000 kb
Host smart-2a21dd7f-a0cc-4cd0-847e-f9e9ba82aacd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084591697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2084591697
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.589076405
Short name T281
Test name
Test status
Simulation time 348328213 ps
CPU time 9.42 seconds
Started Jul 12 05:46:41 PM PDT 24
Finished Jul 12 05:46:53 PM PDT 24
Peak memory 211848 kb
Host smart-76428ffe-edd4-485d-abe2-656ea0fc8ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589076405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.589076405
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4249280449
Short name T10
Test name
Test status
Simulation time 4480158346 ps
CPU time 11.64 seconds
Started Jul 12 05:46:44 PM PDT 24
Finished Jul 12 05:46:59 PM PDT 24
Peak memory 211388 kb
Host smart-f7599701-8620-4f4e-beb7-298f2854d6d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249280449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4249280449
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3727028020
Short name T136
Test name
Test status
Simulation time 3353682458 ps
CPU time 29.62 seconds
Started Jul 12 05:46:41 PM PDT 24
Finished Jul 12 05:47:13 PM PDT 24
Peak memory 213396 kb
Host smart-746544db-ce0e-42b8-aacc-7fd80ce160e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727028020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3727028020
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.505809009
Short name T362
Test name
Test status
Simulation time 476046770 ps
CPU time 27.54 seconds
Started Jul 12 05:46:44 PM PDT 24
Finished Jul 12 05:47:14 PM PDT 24
Peak memory 215428 kb
Host smart-98b3b19f-4b26-4fc0-a25a-6822918aecf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505809009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.505809009
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.805761059
Short name T310
Test name
Test status
Simulation time 98181427 ps
CPU time 4.2 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:46:49 PM PDT 24
Peak memory 211332 kb
Host smart-c0284bfc-3ce5-48a4-aa30-e789a6d0620f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805761059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.805761059
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3891958816
Short name T361
Test name
Test status
Simulation time 97901603888 ps
CPU time 252.52 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:50:57 PM PDT 24
Peak memory 225236 kb
Host smart-fc00e494-ecdd-47a2-8331-a7ca853e85b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891958816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3891958816
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.463575612
Short name T20
Test name
Test status
Simulation time 2373528749 ps
CPU time 9.62 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:46:55 PM PDT 24
Peak memory 212252 kb
Host smart-34172f56-cdff-4fe5-95f3-63642bdc0c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463575612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.463575612
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.574092294
Short name T348
Test name
Test status
Simulation time 355083973 ps
CPU time 5.44 seconds
Started Jul 12 05:46:41 PM PDT 24
Finished Jul 12 05:46:49 PM PDT 24
Peak memory 211368 kb
Host smart-6301e741-b14a-43b4-b963-f95ea7476f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=574092294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.574092294
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2688153354
Short name T98
Test name
Test status
Simulation time 9946446246 ps
CPU time 31.9 seconds
Started Jul 12 05:46:41 PM PDT 24
Finished Jul 12 05:47:14 PM PDT 24
Peak memory 214364 kb
Host smart-101d2a75-f0eb-4dca-8196-384fed4ab0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688153354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2688153354
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.262738175
Short name T149
Test name
Test status
Simulation time 3561023060 ps
CPU time 17.1 seconds
Started Jul 12 05:46:42 PM PDT 24
Finished Jul 12 05:47:01 PM PDT 24
Peak memory 215516 kb
Host smart-5a8a9bdb-26d2-434c-b77a-e6f8e819b5fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262738175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.262738175
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1188887419
Short name T313
Test name
Test status
Simulation time 439028392 ps
CPU time 7.05 seconds
Started Jul 12 05:46:49 PM PDT 24
Finished Jul 12 05:46:58 PM PDT 24
Peak memory 211340 kb
Host smart-99e4be59-ed8a-40f1-82d3-6c41feb44b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188887419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1188887419
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2898030481
Short name T96
Test name
Test status
Simulation time 44025960820 ps
CPU time 452.92 seconds
Started Jul 12 05:46:49 PM PDT 24
Finished Jul 12 05:54:24 PM PDT 24
Peak memory 212712 kb
Host smart-0042d3aa-696a-41d5-accd-1fdd3346e0a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898030481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2898030481
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1063495865
Short name T261
Test name
Test status
Simulation time 478745680 ps
CPU time 9.63 seconds
Started Jul 12 05:46:47 PM PDT 24
Finished Jul 12 05:46:59 PM PDT 24
Peak memory 211456 kb
Host smart-de73c741-ee5f-4250-abcd-72c7d1062aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063495865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1063495865
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.854631211
Short name T247
Test name
Test status
Simulation time 1575859215 ps
CPU time 15.01 seconds
Started Jul 12 05:46:46 PM PDT 24
Finished Jul 12 05:47:04 PM PDT 24
Peak memory 211256 kb
Host smart-e26834d3-e006-4e3e-96ce-a05d0b9b002c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854631211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.854631211
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4044190481
Short name T37
Test name
Test status
Simulation time 8887429787 ps
CPU time 23.94 seconds
Started Jul 12 05:46:47 PM PDT 24
Finished Jul 12 05:47:13 PM PDT 24
Peak memory 214184 kb
Host smart-bd296c5a-09f8-4823-963b-a790d53c82f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044190481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4044190481
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3277190256
Short name T240
Test name
Test status
Simulation time 9364627698 ps
CPU time 44.83 seconds
Started Jul 12 05:46:48 PM PDT 24
Finished Jul 12 05:47:35 PM PDT 24
Peak memory 216560 kb
Host smart-16c0c89d-16b0-4830-939a-44a1b560f583
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277190256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3277190256
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2019115696
Short name T184
Test name
Test status
Simulation time 4881409395 ps
CPU time 15.73 seconds
Started Jul 12 05:46:52 PM PDT 24
Finished Jul 12 05:47:09 PM PDT 24
Peak memory 211176 kb
Host smart-7159d3db-bcee-4b17-b154-c647b63385b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019115696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2019115696
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.101498110
Short name T318
Test name
Test status
Simulation time 84521457825 ps
CPU time 322.83 seconds
Started Jul 12 05:46:48 PM PDT 24
Finished Jul 12 05:52:13 PM PDT 24
Peak memory 234776 kb
Host smart-64aeb865-546d-4950-8d26-4f3f20528481
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101498110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.101498110
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1727188006
Short name T238
Test name
Test status
Simulation time 12487288716 ps
CPU time 27.14 seconds
Started Jul 12 05:46:52 PM PDT 24
Finished Jul 12 05:47:20 PM PDT 24
Peak memory 212244 kb
Host smart-6e85998e-0427-43f4-b8d6-ef08eaa5526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727188006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1727188006
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2319971561
Short name T257
Test name
Test status
Simulation time 1715461806 ps
CPU time 9.06 seconds
Started Jul 12 05:46:47 PM PDT 24
Finished Jul 12 05:46:59 PM PDT 24
Peak memory 211332 kb
Host smart-f6e31c39-6341-4a67-97d4-c59bc4538297
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319971561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2319971561
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.33868193
Short name T269
Test name
Test status
Simulation time 22114829651 ps
CPU time 18.07 seconds
Started Jul 12 05:46:48 PM PDT 24
Finished Jul 12 05:47:08 PM PDT 24
Peak memory 213844 kb
Host smart-666acf75-39c9-4fda-b6c4-8f441a9e7a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33868193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.33868193
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.780730062
Short name T333
Test name
Test status
Simulation time 382485707 ps
CPU time 23.49 seconds
Started Jul 12 05:46:52 PM PDT 24
Finished Jul 12 05:47:16 PM PDT 24
Peak memory 215304 kb
Host smart-00116191-0a9f-4292-99e4-cdb5e1da0ec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780730062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.780730062
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2533652932
Short name T325
Test name
Test status
Simulation time 2689022114 ps
CPU time 12.42 seconds
Started Jul 12 05:46:54 PM PDT 24
Finished Jul 12 05:47:08 PM PDT 24
Peak memory 211240 kb
Host smart-3a4566a6-970a-40c9-96bc-0dec3dcc307f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533652932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2533652932
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.29782846
Short name T342
Test name
Test status
Simulation time 53401792409 ps
CPU time 179.09 seconds
Started Jul 12 05:46:47 PM PDT 24
Finished Jul 12 05:49:49 PM PDT 24
Peak memory 225252 kb
Host smart-f0915875-e455-4277-9583-4494043f5fce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29782846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_co
rrupt_sig_fatal_chk.29782846
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.806765936
Short name T44
Test name
Test status
Simulation time 177179904 ps
CPU time 9.45 seconds
Started Jul 12 05:46:50 PM PDT 24
Finished Jul 12 05:47:01 PM PDT 24
Peak memory 211920 kb
Host smart-9e241395-394f-4f89-9349-b90da45852ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806765936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.806765936
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2516044385
Short name T276
Test name
Test status
Simulation time 524783568 ps
CPU time 8.35 seconds
Started Jul 12 05:46:51 PM PDT 24
Finished Jul 12 05:47:01 PM PDT 24
Peak memory 211372 kb
Host smart-9e97fd34-0afa-4e16-af1b-c9b70c214d57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516044385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2516044385
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1392352698
Short name T179
Test name
Test status
Simulation time 1397655124 ps
CPU time 14.31 seconds
Started Jul 12 05:46:49 PM PDT 24
Finished Jul 12 05:47:06 PM PDT 24
Peak memory 213412 kb
Host smart-e0654649-1fac-47ee-95fe-f34a291987d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392352698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1392352698
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2876762544
Short name T299
Test name
Test status
Simulation time 3925653322 ps
CPU time 18.45 seconds
Started Jul 12 05:46:50 PM PDT 24
Finished Jul 12 05:47:10 PM PDT 24
Peak memory 214240 kb
Host smart-9a49b016-5391-4b0d-934b-883fa6aa4758
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876762544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2876762544
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1569111151
Short name T262
Test name
Test status
Simulation time 175457311 ps
CPU time 4.15 seconds
Started Jul 12 05:46:53 PM PDT 24
Finished Jul 12 05:46:59 PM PDT 24
Peak memory 211228 kb
Host smart-e7ddbaca-6828-4c59-965e-5faf86445f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569111151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1569111151
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1479990352
Short name T198
Test name
Test status
Simulation time 71798597134 ps
CPU time 348.65 seconds
Started Jul 12 05:46:48 PM PDT 24
Finished Jul 12 05:52:39 PM PDT 24
Peak memory 237764 kb
Host smart-edd5a861-4ba7-4b39-82c0-a5992d38ee0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479990352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1479990352
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3703410548
Short name T344
Test name
Test status
Simulation time 4817894493 ps
CPU time 30.22 seconds
Started Jul 12 05:46:53 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 212312 kb
Host smart-0e1ee21f-3f2e-4919-a56c-5d08aabc5491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703410548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3703410548
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1613100104
Short name T187
Test name
Test status
Simulation time 5521980620 ps
CPU time 12.93 seconds
Started Jul 12 05:46:50 PM PDT 24
Finished Jul 12 05:47:04 PM PDT 24
Peak memory 211420 kb
Host smart-529a4f49-3f82-4df2-98e0-4cec963925d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613100104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1613100104
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.4275291442
Short name T134
Test name
Test status
Simulation time 2587244205 ps
CPU time 16.18 seconds
Started Jul 12 05:46:52 PM PDT 24
Finished Jul 12 05:47:10 PM PDT 24
Peak memory 213712 kb
Host smart-9b835924-7863-4ba7-82dd-31f975049dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275291442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.4275291442
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.458939363
Short name T232
Test name
Test status
Simulation time 8848659498 ps
CPU time 25.24 seconds
Started Jul 12 05:46:53 PM PDT 24
Finished Jul 12 05:47:20 PM PDT 24
Peak memory 217124 kb
Host smart-cc5e3e3d-e20b-4712-838a-f325792c15c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458939363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.458939363
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.337388295
Short name T250
Test name
Test status
Simulation time 88134414 ps
CPU time 4.39 seconds
Started Jul 12 05:46:56 PM PDT 24
Finished Jul 12 05:47:02 PM PDT 24
Peak memory 211320 kb
Host smart-fca3780e-64ee-48cb-a810-facb6f8baa6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337388295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.337388295
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2447358232
Short name T153
Test name
Test status
Simulation time 12835939053 ps
CPU time 186.37 seconds
Started Jul 12 05:46:54 PM PDT 24
Finished Jul 12 05:50:02 PM PDT 24
Peak memory 237768 kb
Host smart-063cabf1-38e3-4467-96a8-2b1f7ff9a138
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447358232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2447358232
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2989743925
Short name T241
Test name
Test status
Simulation time 2296753111 ps
CPU time 23.76 seconds
Started Jul 12 05:46:54 PM PDT 24
Finished Jul 12 05:47:19 PM PDT 24
Peak memory 211888 kb
Host smart-442ab501-ae99-48a1-96f8-b111e7c6ef7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989743925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2989743925
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3593146005
Short name T223
Test name
Test status
Simulation time 1842664862 ps
CPU time 15.05 seconds
Started Jul 12 05:46:56 PM PDT 24
Finished Jul 12 05:47:12 PM PDT 24
Peak memory 211348 kb
Host smart-98575417-83c5-4196-8b97-daa5048ef4b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593146005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3593146005
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2833926036
Short name T145
Test name
Test status
Simulation time 778712441 ps
CPU time 9.84 seconds
Started Jul 12 05:46:59 PM PDT 24
Finished Jul 12 05:47:10 PM PDT 24
Peak memory 213244 kb
Host smart-06b8b458-dc1f-4872-9ca8-b68d1fa9d205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833926036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2833926036
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1576528611
Short name T357
Test name
Test status
Simulation time 14477862157 ps
CPU time 38.36 seconds
Started Jul 12 05:46:53 PM PDT 24
Finished Jul 12 05:47:34 PM PDT 24
Peak memory 214336 kb
Host smart-3ddf16f4-bf3c-43ec-abca-8098da31ea49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576528611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1576528611
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3203346323
Short name T17
Test name
Test status
Simulation time 151785484315 ps
CPU time 2806.23 seconds
Started Jul 12 05:46:54 PM PDT 24
Finished Jul 12 06:33:42 PM PDT 24
Peak memory 240388 kb
Host smart-f33f4a71-4483-4b50-b9d5-4dca641828a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203346323 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3203346323
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2671878099
Short name T99
Test name
Test status
Simulation time 171435002 ps
CPU time 4.11 seconds
Started Jul 12 05:46:54 PM PDT 24
Finished Jul 12 05:46:59 PM PDT 24
Peak memory 211300 kb
Host smart-9cca52c6-abaf-4dc4-86e9-09e9f297c935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671878099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2671878099
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2412373662
Short name T326
Test name
Test status
Simulation time 943427503 ps
CPU time 14.97 seconds
Started Jul 12 05:46:59 PM PDT 24
Finished Jul 12 05:47:15 PM PDT 24
Peak memory 211764 kb
Host smart-2457a22f-5dea-4b8d-84a9-5c39cad1f0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412373662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2412373662
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3079279046
Short name T34
Test name
Test status
Simulation time 1330173395 ps
CPU time 13.67 seconds
Started Jul 12 05:46:56 PM PDT 24
Finished Jul 12 05:47:11 PM PDT 24
Peak memory 211364 kb
Host smart-32557bbc-87e7-4b3c-82aa-a740584c4a54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079279046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3079279046
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3110192958
Short name T190
Test name
Test status
Simulation time 8354488533 ps
CPU time 33.17 seconds
Started Jul 12 05:46:54 PM PDT 24
Finished Jul 12 05:47:29 PM PDT 24
Peak memory 214584 kb
Host smart-013de966-1ade-40c6-abbe-77834acc4083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110192958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3110192958
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2760028275
Short name T18
Test name
Test status
Simulation time 3390679119 ps
CPU time 38.61 seconds
Started Jul 12 05:46:56 PM PDT 24
Finished Jul 12 05:47:36 PM PDT 24
Peak memory 215984 kb
Host smart-f29506d6-e9e1-4b54-becc-2d3a5fdb9b3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760028275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2760028275
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2020687209
Short name T51
Test name
Test status
Simulation time 190411860090 ps
CPU time 2076.04 seconds
Started Jul 12 05:46:56 PM PDT 24
Finished Jul 12 06:21:33 PM PDT 24
Peak memory 238828 kb
Host smart-83468fa6-13f4-4a6b-bb74-64da6548b52b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020687209 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2020687209
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.140736912
Short name T243
Test name
Test status
Simulation time 1374663139 ps
CPU time 8.56 seconds
Started Jul 12 05:46:12 PM PDT 24
Finished Jul 12 05:46:22 PM PDT 24
Peak memory 211300 kb
Host smart-0ebbeb41-c5e6-4585-86f3-68eead72ee6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140736912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.140736912
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1977488222
Short name T345
Test name
Test status
Simulation time 94110984671 ps
CPU time 249.29 seconds
Started Jul 12 05:46:08 PM PDT 24
Finished Jul 12 05:50:18 PM PDT 24
Peak memory 212816 kb
Host smart-3efcc16a-2f00-4f31-8166-a58f97d9b29f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977488222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1977488222
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2205766236
Short name T26
Test name
Test status
Simulation time 1840711552 ps
CPU time 9.5 seconds
Started Jul 12 05:46:08 PM PDT 24
Finished Jul 12 05:46:18 PM PDT 24
Peak memory 211956 kb
Host smart-43dc8fe2-a757-402e-94a8-616d9dac242d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205766236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2205766236
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3931182291
Short name T356
Test name
Test status
Simulation time 6247102587 ps
CPU time 11.87 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:30 PM PDT 24
Peak memory 211444 kb
Host smart-0a73247e-f0ee-4aac-b493-033c9f581a88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931182291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3931182291
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2527349107
Short name T29
Test name
Test status
Simulation time 583556815 ps
CPU time 100.07 seconds
Started Jul 12 05:46:12 PM PDT 24
Finished Jul 12 05:47:54 PM PDT 24
Peak memory 235936 kb
Host smart-eaa1d8e5-23aa-4fa8-bef0-72111c9a7209
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527349107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2527349107
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1392831561
Short name T229
Test name
Test status
Simulation time 6829565274 ps
CPU time 31.84 seconds
Started Jul 12 05:46:09 PM PDT 24
Finished Jul 12 05:46:42 PM PDT 24
Peak memory 214244 kb
Host smart-5349d3f5-7c74-4830-966c-5fb77f0bb8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392831561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1392831561
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.606122275
Short name T265
Test name
Test status
Simulation time 469997071 ps
CPU time 6.29 seconds
Started Jul 12 05:46:12 PM PDT 24
Finished Jul 12 05:46:19 PM PDT 24
Peak memory 211376 kb
Host smart-246ee22e-0ce9-4549-af5b-07515f5404b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606122275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.606122275
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.288767900
Short name T66
Test name
Test status
Simulation time 460011359 ps
CPU time 7.25 seconds
Started Jul 12 05:47:03 PM PDT 24
Finished Jul 12 05:47:13 PM PDT 24
Peak memory 211320 kb
Host smart-72bc7f73-7691-4579-97f7-d104fcc1e893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288767900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.288767900
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4191708921
Short name T327
Test name
Test status
Simulation time 12480012406 ps
CPU time 163.48 seconds
Started Jul 12 05:47:03 PM PDT 24
Finished Jul 12 05:49:49 PM PDT 24
Peak memory 237352 kb
Host smart-7538354a-c79d-4f26-82d0-d791d1b6fb2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191708921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4191708921
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3962075868
Short name T301
Test name
Test status
Simulation time 8037098891 ps
CPU time 33.44 seconds
Started Jul 12 05:47:03 PM PDT 24
Finished Jul 12 05:47:39 PM PDT 24
Peak memory 212252 kb
Host smart-1d94aae4-a0c5-4871-b045-56cc1acd3920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962075868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3962075868
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2698307184
Short name T286
Test name
Test status
Simulation time 376082971 ps
CPU time 5.72 seconds
Started Jul 12 05:47:04 PM PDT 24
Finished Jul 12 05:47:12 PM PDT 24
Peak memory 211308 kb
Host smart-53d7a552-93ef-4d81-bc6d-0362aa0a126a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2698307184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2698307184
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2057281173
Short name T12
Test name
Test status
Simulation time 5654832672 ps
CPU time 26.52 seconds
Started Jul 12 05:46:53 PM PDT 24
Finished Jul 12 05:47:21 PM PDT 24
Peak memory 213864 kb
Host smart-adaf0849-74f3-4a03-8135-718cec21797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057281173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2057281173
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4107550471
Short name T201
Test name
Test status
Simulation time 1350689990 ps
CPU time 15.92 seconds
Started Jul 12 05:46:58 PM PDT 24
Finished Jul 12 05:47:15 PM PDT 24
Peak memory 211336 kb
Host smart-b7698f99-e682-4e1b-afff-b3dc46bd53e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107550471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4107550471
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1300737508
Short name T143
Test name
Test status
Simulation time 302537701 ps
CPU time 6.25 seconds
Started Jul 12 05:47:02 PM PDT 24
Finished Jul 12 05:47:10 PM PDT 24
Peak memory 211332 kb
Host smart-5a7df12d-6351-4edf-81f2-a6a313dbedc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300737508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1300737508
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.407428510
Short name T249
Test name
Test status
Simulation time 1347581595 ps
CPU time 80.27 seconds
Started Jul 12 05:47:05 PM PDT 24
Finished Jul 12 05:48:28 PM PDT 24
Peak memory 224648 kb
Host smart-3c47f534-d05f-4101-9bd0-2e6b662e62e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407428510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.407428510
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2673297104
Short name T139
Test name
Test status
Simulation time 22821100965 ps
CPU time 35.83 seconds
Started Jul 12 05:47:03 PM PDT 24
Finished Jul 12 05:47:41 PM PDT 24
Peak memory 212244 kb
Host smart-0969639f-b41f-4817-959c-3f42666d39f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673297104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2673297104
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.584628058
Short name T258
Test name
Test status
Simulation time 395406216 ps
CPU time 5.67 seconds
Started Jul 12 05:47:07 PM PDT 24
Finished Jul 12 05:47:14 PM PDT 24
Peak memory 211224 kb
Host smart-b210e285-de8a-49d3-b0fb-44ea58593229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584628058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.584628058
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3172568497
Short name T273
Test name
Test status
Simulation time 4647997754 ps
CPU time 19.72 seconds
Started Jul 12 05:47:03 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 213900 kb
Host smart-c1f0a354-13ae-43d2-be96-083293b89cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172568497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3172568497
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2925932265
Short name T272
Test name
Test status
Simulation time 31622878422 ps
CPU time 82.84 seconds
Started Jul 12 05:47:02 PM PDT 24
Finished Jul 12 05:48:27 PM PDT 24
Peak memory 218056 kb
Host smart-1ce2a129-9697-4539-bf76-2101bdc990c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925932265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2925932265
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1213989439
Short name T322
Test name
Test status
Simulation time 4624261177 ps
CPU time 13.64 seconds
Started Jul 12 05:47:14 PM PDT 24
Finished Jul 12 05:47:29 PM PDT 24
Peak memory 211360 kb
Host smart-574e2d78-2c8e-4a19-94d0-3b1b9a0ea490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213989439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1213989439
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3474323198
Short name T316
Test name
Test status
Simulation time 49234115022 ps
CPU time 473.9 seconds
Started Jul 12 05:47:05 PM PDT 24
Finished Jul 12 05:55:01 PM PDT 24
Peak memory 212604 kb
Host smart-61c12500-42c9-4e49-8eb8-d728e6f43ec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474323198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3474323198
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1520663674
Short name T268
Test name
Test status
Simulation time 2076039777 ps
CPU time 13.84 seconds
Started Jul 12 05:47:03 PM PDT 24
Finished Jul 12 05:47:20 PM PDT 24
Peak memory 211812 kb
Host smart-e4fa7480-aec7-4859-9df9-3b603541749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520663674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1520663674
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.273061868
Short name T130
Test name
Test status
Simulation time 5806621640 ps
CPU time 13.11 seconds
Started Jul 12 05:47:03 PM PDT 24
Finished Jul 12 05:47:19 PM PDT 24
Peak memory 211424 kb
Host smart-af25bbb8-4673-4cd8-b842-12fdc17347ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273061868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.273061868
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4205716334
Short name T270
Test name
Test status
Simulation time 751416007 ps
CPU time 10.11 seconds
Started Jul 12 05:47:02 PM PDT 24
Finished Jul 12 05:47:14 PM PDT 24
Peak memory 214072 kb
Host smart-bcfb0907-a35c-4a5d-a0c3-a7c823ba2124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205716334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4205716334
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1854591072
Short name T231
Test name
Test status
Simulation time 1598083968 ps
CPU time 17.95 seconds
Started Jul 12 05:47:02 PM PDT 24
Finished Jul 12 05:47:23 PM PDT 24
Peak memory 212200 kb
Host smart-6cae7b5f-abc1-49a9-a518-dc8603f0c339
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854591072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1854591072
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3325417972
Short name T55
Test name
Test status
Simulation time 37663604864 ps
CPU time 1614.53 seconds
Started Jul 12 05:47:12 PM PDT 24
Finished Jul 12 06:14:09 PM PDT 24
Peak memory 236028 kb
Host smart-b3d4f8f9-439c-4db3-bd0b-e262f7ad838c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325417972 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3325417972
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2081583655
Short name T236
Test name
Test status
Simulation time 1502846388 ps
CPU time 13.21 seconds
Started Jul 12 05:47:10 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 211320 kb
Host smart-b54b0867-018e-4157-be54-fd2a18f61584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081583655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2081583655
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1940623697
Short name T317
Test name
Test status
Simulation time 6069358852 ps
CPU time 119.12 seconds
Started Jul 12 05:47:08 PM PDT 24
Finished Jul 12 05:49:09 PM PDT 24
Peak memory 237856 kb
Host smart-1e3f1c0e-866e-4a24-a0c8-90db4fb9d41a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940623697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1940623697
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2441116306
Short name T182
Test name
Test status
Simulation time 8171432554 ps
CPU time 31.45 seconds
Started Jul 12 05:47:10 PM PDT 24
Finished Jul 12 05:47:44 PM PDT 24
Peak memory 213064 kb
Host smart-6bd6deee-619d-47ab-99f4-15b255a4a0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441116306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2441116306
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2202829254
Short name T192
Test name
Test status
Simulation time 100050524 ps
CPU time 5.35 seconds
Started Jul 12 05:47:08 PM PDT 24
Finished Jul 12 05:47:16 PM PDT 24
Peak memory 211372 kb
Host smart-006fb4cc-a973-4eb9-94f9-7458517ab029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202829254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2202829254
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.982615118
Short name T189
Test name
Test status
Simulation time 6665752073 ps
CPU time 32.48 seconds
Started Jul 12 05:47:12 PM PDT 24
Finished Jul 12 05:47:47 PM PDT 24
Peak memory 214372 kb
Host smart-502eb6e7-4d1b-4a28-acc4-eadef6db0907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982615118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.982615118
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3131729616
Short name T340
Test name
Test status
Simulation time 269882768 ps
CPU time 11.74 seconds
Started Jul 12 05:47:10 PM PDT 24
Finished Jul 12 05:47:24 PM PDT 24
Peak memory 213876 kb
Host smart-76b74a80-800f-40be-b50e-175aab417d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131729616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3131729616
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3893042623
Short name T287
Test name
Test status
Simulation time 1688039200 ps
CPU time 8.7 seconds
Started Jul 12 05:47:09 PM PDT 24
Finished Jul 12 05:47:20 PM PDT 24
Peak memory 211260 kb
Host smart-74a754f5-398a-452d-9122-4d0aeed8df71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893042623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3893042623
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2682461709
Short name T41
Test name
Test status
Simulation time 34949451949 ps
CPU time 178.4 seconds
Started Jul 12 05:47:07 PM PDT 24
Finished Jul 12 05:50:07 PM PDT 24
Peak memory 232848 kb
Host smart-a8e3c283-7f59-41ed-bee3-17c3ae79b760
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682461709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2682461709
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4190333754
Short name T321
Test name
Test status
Simulation time 2750997823 ps
CPU time 25.16 seconds
Started Jul 12 05:47:12 PM PDT 24
Finished Jul 12 05:47:39 PM PDT 24
Peak memory 212320 kb
Host smart-cfde1fb5-492b-4fb0-9d03-781081c14413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190333754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.4190333754
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.586852306
Short name T292
Test name
Test status
Simulation time 396241833 ps
CPU time 5.18 seconds
Started Jul 12 05:47:13 PM PDT 24
Finished Jul 12 05:47:20 PM PDT 24
Peak memory 211344 kb
Host smart-b56e7565-2c9d-44d6-9aa2-1ee3f1633d2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586852306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.586852306
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2498263363
Short name T354
Test name
Test status
Simulation time 3504983647 ps
CPU time 37.39 seconds
Started Jul 12 05:47:10 PM PDT 24
Finished Jul 12 05:47:49 PM PDT 24
Peak memory 213440 kb
Host smart-c3755b78-1ffe-423a-9b31-45d706472126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498263363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2498263363
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1744639882
Short name T280
Test name
Test status
Simulation time 9054500531 ps
CPU time 31.67 seconds
Started Jul 12 05:47:11 PM PDT 24
Finished Jul 12 05:47:45 PM PDT 24
Peak memory 216760 kb
Host smart-50ae6604-b7df-4662-b5d0-44d0a0cebb75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744639882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1744639882
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1866284724
Short name T196
Test name
Test status
Simulation time 3675509600 ps
CPU time 7.22 seconds
Started Jul 12 05:47:14 PM PDT 24
Finished Jul 12 05:47:22 PM PDT 24
Peak memory 211380 kb
Host smart-1ca24b29-5d78-461f-ac7a-f6208066273b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866284724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1866284724
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2061947234
Short name T335
Test name
Test status
Simulation time 5025258979 ps
CPU time 79.15 seconds
Started Jul 12 05:47:11 PM PDT 24
Finished Jul 12 05:48:32 PM PDT 24
Peak memory 240012 kb
Host smart-a53cdfdd-cba9-4730-8706-489b66c0b452
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061947234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2061947234
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2435939832
Short name T158
Test name
Test status
Simulation time 1188618830 ps
CPU time 9.62 seconds
Started Jul 12 05:47:10 PM PDT 24
Finished Jul 12 05:47:21 PM PDT 24
Peak memory 211788 kb
Host smart-d27e1911-53e2-4ab6-8760-7dd99cc30ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435939832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2435939832
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3999795783
Short name T267
Test name
Test status
Simulation time 1200499167 ps
CPU time 8.66 seconds
Started Jul 12 05:47:13 PM PDT 24
Finished Jul 12 05:47:23 PM PDT 24
Peak memory 211376 kb
Host smart-d2efb6c5-3366-4c0e-be04-25d8dacf9cf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999795783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3999795783
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1843824637
Short name T81
Test name
Test status
Simulation time 1667657560 ps
CPU time 22.19 seconds
Started Jul 12 05:47:08 PM PDT 24
Finished Jul 12 05:47:33 PM PDT 24
Peak memory 213360 kb
Host smart-3f1ffe5b-a0e2-4a63-b17c-4098091e7ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843824637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1843824637
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2319185083
Short name T43
Test name
Test status
Simulation time 5680079520 ps
CPU time 15.22 seconds
Started Jul 12 05:47:11 PM PDT 24
Finished Jul 12 05:47:28 PM PDT 24
Peak memory 212168 kb
Host smart-88e4f2f1-e161-463f-81fb-e5fd0a6222c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319185083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2319185083
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3019878338
Short name T211
Test name
Test status
Simulation time 209155775 ps
CPU time 5.8 seconds
Started Jul 12 05:47:08 PM PDT 24
Finished Jul 12 05:47:16 PM PDT 24
Peak memory 211268 kb
Host smart-b654ccfc-9ce7-4669-b2eb-3620eda951da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019878338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3019878338
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.532192876
Short name T346
Test name
Test status
Simulation time 29360833065 ps
CPU time 271.85 seconds
Started Jul 12 05:47:10 PM PDT 24
Finished Jul 12 05:51:44 PM PDT 24
Peak memory 212568 kb
Host smart-fbab45d9-5d54-4d87-b713-c8c616d9fc72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532192876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.532192876
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2291088794
Short name T151
Test name
Test status
Simulation time 3533059441 ps
CPU time 31.22 seconds
Started Jul 12 05:47:12 PM PDT 24
Finished Jul 12 05:47:45 PM PDT 24
Peak memory 211992 kb
Host smart-a6e201f9-be9c-4529-9dfc-bbeac2f438e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291088794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2291088794
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2750532443
Short name T277
Test name
Test status
Simulation time 1364917351 ps
CPU time 13.39 seconds
Started Jul 12 05:47:09 PM PDT 24
Finished Jul 12 05:47:25 PM PDT 24
Peak memory 211332 kb
Host smart-16964c8c-7cea-4050-8845-ef8be79e3c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750532443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2750532443
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.873575724
Short name T64
Test name
Test status
Simulation time 13128304044 ps
CPU time 26.65 seconds
Started Jul 12 05:47:10 PM PDT 24
Finished Jul 12 05:47:39 PM PDT 24
Peak memory 214444 kb
Host smart-c9b7a957-23ae-430f-86ec-a9d3c6328d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873575724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.873575724
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2289140286
Short name T352
Test name
Test status
Simulation time 642276591 ps
CPU time 9.9 seconds
Started Jul 12 05:47:12 PM PDT 24
Finished Jul 12 05:47:24 PM PDT 24
Peak memory 214232 kb
Host smart-fe945214-9e20-4561-81f0-269998d722ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289140286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2289140286
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1552703920
Short name T224
Test name
Test status
Simulation time 604295654 ps
CPU time 7.92 seconds
Started Jul 12 05:47:15 PM PDT 24
Finished Jul 12 05:47:24 PM PDT 24
Peak memory 211292 kb
Host smart-1c18b5cc-af42-426b-846b-56b4411edf00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552703920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1552703920
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1520876026
Short name T323
Test name
Test status
Simulation time 334144224 ps
CPU time 9.66 seconds
Started Jul 12 05:47:20 PM PDT 24
Finished Jul 12 05:47:31 PM PDT 24
Peak memory 211924 kb
Host smart-65feb04c-0648-4ba4-be07-9f4eafd38b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520876026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1520876026
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4125770292
Short name T59
Test name
Test status
Simulation time 699915976 ps
CPU time 6.87 seconds
Started Jul 12 05:47:08 PM PDT 24
Finished Jul 12 05:47:17 PM PDT 24
Peak memory 211316 kb
Host smart-9d0ed89b-e60e-4764-a2d8-3965d667240c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125770292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4125770292
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2269314599
Short name T175
Test name
Test status
Simulation time 1943530658 ps
CPU time 27.04 seconds
Started Jul 12 05:47:11 PM PDT 24
Finished Jul 12 05:47:40 PM PDT 24
Peak memory 213076 kb
Host smart-ac25e34c-d016-487e-87cc-97215ab99f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269314599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2269314599
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1460583894
Short name T94
Test name
Test status
Simulation time 16612153447 ps
CPU time 97.87 seconds
Started Jul 12 05:47:11 PM PDT 24
Finished Jul 12 05:48:50 PM PDT 24
Peak memory 216156 kb
Host smart-0970e020-7a04-4734-a75e-ba2846048a3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460583894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1460583894
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2879359470
Short name T144
Test name
Test status
Simulation time 346219645 ps
CPU time 5.37 seconds
Started Jul 12 05:47:15 PM PDT 24
Finished Jul 12 05:47:22 PM PDT 24
Peak memory 211316 kb
Host smart-219fc58d-13c3-4935-9af0-239bbd8fb205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879359470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2879359470
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2533216086
Short name T284
Test name
Test status
Simulation time 31147888097 ps
CPU time 125.41 seconds
Started Jul 12 05:47:13 PM PDT 24
Finished Jul 12 05:49:20 PM PDT 24
Peak memory 237568 kb
Host smart-dfac5875-be9f-4b68-8eab-57c3764d1be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533216086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2533216086
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.967705610
Short name T338
Test name
Test status
Simulation time 10892878002 ps
CPU time 25.59 seconds
Started Jul 12 05:47:19 PM PDT 24
Finished Jul 12 05:47:46 PM PDT 24
Peak memory 212164 kb
Host smart-12fbe0f2-dcc0-425e-b5d1-48c20aab759b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967705610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.967705610
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3681788444
Short name T311
Test name
Test status
Simulation time 19828478891 ps
CPU time 25.26 seconds
Started Jul 12 05:47:18 PM PDT 24
Finished Jul 12 05:47:44 PM PDT 24
Peak memory 214896 kb
Host smart-17d9ae9c-6aa1-4e93-923f-f8f23ef0d203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681788444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3681788444
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3965529241
Short name T181
Test name
Test status
Simulation time 17302629228 ps
CPU time 43.55 seconds
Started Jul 12 05:47:16 PM PDT 24
Finished Jul 12 05:48:01 PM PDT 24
Peak memory 219408 kb
Host smart-4fe7e5ea-791a-4666-950b-07b2bced32a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965529241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3965529241
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3367513976
Short name T56
Test name
Test status
Simulation time 87104130040 ps
CPU time 824.63 seconds
Started Jul 12 05:47:16 PM PDT 24
Finished Jul 12 06:01:01 PM PDT 24
Peak memory 235804 kb
Host smart-9a801981-e06d-46b3-b440-1a6dab7b8b5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367513976 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3367513976
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2023812506
Short name T67
Test name
Test status
Simulation time 18893586980 ps
CPU time 14.51 seconds
Started Jul 12 05:47:14 PM PDT 24
Finished Jul 12 05:47:30 PM PDT 24
Peak memory 211372 kb
Host smart-262e0064-6bde-4dd8-bd7e-e2818f0c26cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023812506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2023812506
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.981816136
Short name T178
Test name
Test status
Simulation time 28138264137 ps
CPU time 147.93 seconds
Started Jul 12 05:47:19 PM PDT 24
Finished Jul 12 05:49:48 PM PDT 24
Peak memory 237848 kb
Host smart-cc60d843-534d-42f4-a145-74f255442355
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981816136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.981816136
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1939152216
Short name T319
Test name
Test status
Simulation time 175433439 ps
CPU time 9.38 seconds
Started Jul 12 05:47:16 PM PDT 24
Finished Jul 12 05:47:26 PM PDT 24
Peak memory 212008 kb
Host smart-cfaecb56-50bb-4674-9b70-5a8ca14cfb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939152216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1939152216
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4175032193
Short name T341
Test name
Test status
Simulation time 541468628 ps
CPU time 5.43 seconds
Started Jul 12 05:47:15 PM PDT 24
Finished Jul 12 05:47:21 PM PDT 24
Peak memory 211308 kb
Host smart-69631837-e2cb-44fd-bc1c-222a3660e568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4175032193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4175032193
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1514902879
Short name T234
Test name
Test status
Simulation time 33494118766 ps
CPU time 31.45 seconds
Started Jul 12 05:47:15 PM PDT 24
Finished Jul 12 05:47:48 PM PDT 24
Peak memory 214104 kb
Host smart-cf4be34a-2832-47b7-b04c-6a21c310d9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514902879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1514902879
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2965721501
Short name T336
Test name
Test status
Simulation time 9048452348 ps
CPU time 37.38 seconds
Started Jul 12 05:47:18 PM PDT 24
Finished Jul 12 05:47:56 PM PDT 24
Peak memory 215796 kb
Host smart-f8eb8bb2-6794-4c09-8692-bfd97bf10f61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965721501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2965721501
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3102991185
Short name T207
Test name
Test status
Simulation time 1839286137 ps
CPU time 14.31 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:31 PM PDT 24
Peak memory 211332 kb
Host smart-eba2bae7-2235-4358-804a-9987460d5c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102991185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3102991185
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.326385674
Short name T36
Test name
Test status
Simulation time 48761559235 ps
CPU time 258.14 seconds
Started Jul 12 05:46:09 PM PDT 24
Finished Jul 12 05:50:28 PM PDT 24
Peak memory 234924 kb
Host smart-783558b4-0190-4ec9-a98e-5bd7b282d9a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326385674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.326385674
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1763670038
Short name T27
Test name
Test status
Simulation time 2418781620 ps
CPU time 13.93 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 05:46:31 PM PDT 24
Peak memory 212132 kb
Host smart-34697ddb-be95-454b-8591-3c2de064ca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763670038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1763670038
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2637763313
Short name T195
Test name
Test status
Simulation time 95161927 ps
CPU time 5.31 seconds
Started Jul 12 05:46:13 PM PDT 24
Finished Jul 12 05:46:19 PM PDT 24
Peak memory 211364 kb
Host smart-df79b84c-88ab-4a3d-a2af-ce37e73bae8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637763313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2637763313
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3872307260
Short name T220
Test name
Test status
Simulation time 3052908669 ps
CPU time 25.56 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:43 PM PDT 24
Peak memory 213112 kb
Host smart-70e092da-8878-4157-a1dd-8989bb6f373a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872307260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3872307260
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1000711984
Short name T306
Test name
Test status
Simulation time 855540544 ps
CPU time 12.57 seconds
Started Jul 12 05:46:08 PM PDT 24
Finished Jul 12 05:46:22 PM PDT 24
Peak memory 212292 kb
Host smart-80ee76e2-800e-40a5-aa84-226456da31b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000711984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1000711984
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2194573922
Short name T52
Test name
Test status
Simulation time 285164948640 ps
CPU time 1136.17 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 06:05:12 PM PDT 24
Peak memory 232448 kb
Host smart-8f3e8f69-c607-43b6-9b68-728077342472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194573922 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2194573922
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3633225487
Short name T314
Test name
Test status
Simulation time 6606106804 ps
CPU time 12.5 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:30 PM PDT 24
Peak memory 211320 kb
Host smart-d4487d5c-4fad-4cbe-885a-f0daecbe7e78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633225487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3633225487
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2940258902
Short name T152
Test name
Test status
Simulation time 28321709991 ps
CPU time 110.15 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:48:08 PM PDT 24
Peak memory 232768 kb
Host smart-1c83ec2b-feed-4a40-ae49-6e5bd024989f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940258902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2940258902
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2657390874
Short name T279
Test name
Test status
Simulation time 17030298878 ps
CPU time 35.24 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 05:46:51 PM PDT 24
Peak memory 219192 kb
Host smart-09fdcfb1-e39c-4f17-85e5-2c454f2f5c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657390874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2657390874
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4041561280
Short name T172
Test name
Test status
Simulation time 7155620975 ps
CPU time 13.74 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 05:46:29 PM PDT 24
Peak memory 211424 kb
Host smart-fc23dd37-8769-4fe3-bfee-ff1f17648177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4041561280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4041561280
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4256096609
Short name T291
Test name
Test status
Simulation time 1042519096 ps
CPU time 16.61 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 05:46:33 PM PDT 24
Peak memory 213224 kb
Host smart-26993d79-c219-4f1b-be71-1573919f80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256096609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4256096609
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2211447321
Short name T350
Test name
Test status
Simulation time 140973034 ps
CPU time 10.1 seconds
Started Jul 12 05:46:18 PM PDT 24
Finished Jul 12 05:46:30 PM PDT 24
Peak memory 211308 kb
Host smart-cce54c53-829c-498d-a5c9-fb5c926d2ab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211447321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2211447321
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1094452114
Short name T177
Test name
Test status
Simulation time 4053637033 ps
CPU time 15.96 seconds
Started Jul 12 05:46:20 PM PDT 24
Finished Jul 12 05:46:37 PM PDT 24
Peak memory 211320 kb
Host smart-fc67f85c-6dad-460c-9f41-5829d8a35235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094452114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1094452114
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2626590786
Short name T208
Test name
Test status
Simulation time 13078107930 ps
CPU time 114.57 seconds
Started Jul 12 05:46:16 PM PDT 24
Finished Jul 12 05:48:13 PM PDT 24
Peak memory 237720 kb
Host smart-bd5d467a-4f1e-48d8-83b0-0dd44da1a0d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626590786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2626590786
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3970488788
Short name T48
Test name
Test status
Simulation time 3509888995 ps
CPU time 29.29 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 05:46:44 PM PDT 24
Peak memory 211824 kb
Host smart-eeaed1bb-4638-4707-b474-4731bbe6b703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970488788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3970488788
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4026740744
Short name T14
Test name
Test status
Simulation time 18932056065 ps
CPU time 15.02 seconds
Started Jul 12 05:46:21 PM PDT 24
Finished Jul 12 05:46:37 PM PDT 24
Peak memory 211364 kb
Host smart-208ba9ec-d9d8-4901-bbe8-6dfca6f3a02f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026740744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4026740744
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2346043825
Short name T154
Test name
Test status
Simulation time 14413135800 ps
CPU time 30.36 seconds
Started Jul 12 05:46:19 PM PDT 24
Finished Jul 12 05:46:51 PM PDT 24
Peak memory 214236 kb
Host smart-4a452a6e-9044-495c-a62d-2ce9b8368890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346043825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2346043825
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.352682574
Short name T168
Test name
Test status
Simulation time 42909122689 ps
CPU time 93.57 seconds
Started Jul 12 05:46:13 PM PDT 24
Finished Jul 12 05:47:48 PM PDT 24
Peak memory 216640 kb
Host smart-22fe49e3-6c9c-40f3-8cd5-dec0179a28d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352682574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.352682574
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.604405755
Short name T206
Test name
Test status
Simulation time 1788038953 ps
CPU time 13.91 seconds
Started Jul 12 05:46:13 PM PDT 24
Finished Jul 12 05:46:29 PM PDT 24
Peak memory 211336 kb
Host smart-28b3a723-4d3d-4845-a506-595af9a2be0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604405755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.604405755
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.593765771
Short name T303
Test name
Test status
Simulation time 19054780415 ps
CPU time 155.12 seconds
Started Jul 12 05:46:25 PM PDT 24
Finished Jul 12 05:49:00 PM PDT 24
Peak memory 233808 kb
Host smart-fc506294-ab61-4a00-bf26-0f2edd079a01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593765771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.593765771
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3412412601
Short name T214
Test name
Test status
Simulation time 307225926 ps
CPU time 7.89 seconds
Started Jul 12 05:46:14 PM PDT 24
Finished Jul 12 05:46:24 PM PDT 24
Peak memory 211360 kb
Host smart-491f88cd-2922-44a5-98b7-b54c00149e9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412412601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3412412601
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2241370070
Short name T283
Test name
Test status
Simulation time 783436673 ps
CPU time 10.02 seconds
Started Jul 12 05:46:17 PM PDT 24
Finished Jul 12 05:46:29 PM PDT 24
Peak memory 213512 kb
Host smart-7d6e222e-5da9-4ab2-b481-0115d73fb163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241370070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2241370070
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1584774625
Short name T209
Test name
Test status
Simulation time 19019948583 ps
CPU time 51.09 seconds
Started Jul 12 05:46:27 PM PDT 24
Finished Jul 12 05:47:19 PM PDT 24
Peak memory 216360 kb
Host smart-78415e98-e855-44b5-aad8-7792bf32d7c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584774625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1584774625
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1927617242
Short name T53
Test name
Test status
Simulation time 26605981956 ps
CPU time 1128.44 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 06:05:06 PM PDT 24
Peak memory 235720 kb
Host smart-47f09926-00f3-4979-badd-d7105d8a7569
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927617242 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1927617242
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3100281168
Short name T25
Test name
Test status
Simulation time 2045806045 ps
CPU time 15.35 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:32 PM PDT 24
Peak memory 211320 kb
Host smart-c7c61b19-8d9f-4e49-b0c8-02478feee2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100281168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3100281168
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3340072648
Short name T21
Test name
Test status
Simulation time 12385491820 ps
CPU time 156.4 seconds
Started Jul 12 05:46:16 PM PDT 24
Finished Jul 12 05:48:54 PM PDT 24
Peak memory 236888 kb
Host smart-cffcbd14-aa8c-4338-aaff-5b6bc14211c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340072648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3340072648
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1209670641
Short name T219
Test name
Test status
Simulation time 3501359590 ps
CPU time 29.97 seconds
Started Jul 12 05:46:19 PM PDT 24
Finished Jul 12 05:46:50 PM PDT 24
Peak memory 212096 kb
Host smart-501f8316-7597-4457-94c8-d475dab6545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209670641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1209670641
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3520372567
Short name T288
Test name
Test status
Simulation time 2079633662 ps
CPU time 16.62 seconds
Started Jul 12 05:46:15 PM PDT 24
Finished Jul 12 05:46:33 PM PDT 24
Peak memory 211364 kb
Host smart-c2a4f8ca-56ee-4914-bde6-95dd50f2f421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520372567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3520372567
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1469709203
Short name T164
Test name
Test status
Simulation time 13804834221 ps
CPU time 19.58 seconds
Started Jul 12 05:46:13 PM PDT 24
Finished Jul 12 05:46:34 PM PDT 24
Peak memory 214448 kb
Host smart-6ef2f491-9ef1-4add-88b2-cb28e80b8944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469709203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1469709203
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.299598873
Short name T248
Test name
Test status
Simulation time 209283937 ps
CPU time 7.25 seconds
Started Jul 12 05:46:16 PM PDT 24
Finished Jul 12 05:46:25 PM PDT 24
Peak memory 211316 kb
Host smart-f7812291-0eea-4e1c-ace7-769a787c442a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299598873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.299598873
Directory /workspace/9.rom_ctrl_stress_all/latest
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