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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.67 100.00 98.28 97.45 98.37


Total test records in report: 464
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T305 /workspace/coverage/default/48.rom_ctrl_stress_all.3225447003 Jul 13 06:55:29 PM PDT 24 Jul 13 06:55:43 PM PDT 24 302548797 ps
T306 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2721982412 Jul 13 06:55:14 PM PDT 24 Jul 13 06:55:47 PM PDT 24 16030175864 ps
T307 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.64940084 Jul 13 06:54:39 PM PDT 24 Jul 13 06:54:51 PM PDT 24 265156919 ps
T308 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3652021429 Jul 13 06:54:13 PM PDT 24 Jul 13 06:54:23 PM PDT 24 622917547 ps
T309 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1298970934 Jul 13 06:54:56 PM PDT 24 Jul 13 06:55:02 PM PDT 24 382325249 ps
T310 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1239045216 Jul 13 06:55:21 PM PDT 24 Jul 13 06:55:31 PM PDT 24 175361671 ps
T311 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.457715494 Jul 13 06:54:59 PM PDT 24 Jul 13 06:55:32 PM PDT 24 7660460598 ps
T312 /workspace/coverage/default/39.rom_ctrl_stress_all.1102766016 Jul 13 06:55:13 PM PDT 24 Jul 13 06:55:30 PM PDT 24 1763797101 ps
T313 /workspace/coverage/default/16.rom_ctrl_smoke.1568732260 Jul 13 06:54:31 PM PDT 24 Jul 13 06:55:13 PM PDT 24 4537919471 ps
T314 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1240966945 Jul 13 06:54:39 PM PDT 24 Jul 13 06:57:43 PM PDT 24 10813013659 ps
T315 /workspace/coverage/default/38.rom_ctrl_alert_test.779273936 Jul 13 06:55:15 PM PDT 24 Jul 13 06:55:30 PM PDT 24 1711112494 ps
T316 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3746466964 Jul 13 06:55:20 PM PDT 24 Jul 13 06:55:53 PM PDT 24 4167292632 ps
T317 /workspace/coverage/default/31.rom_ctrl_smoke.3092677874 Jul 13 06:54:47 PM PDT 24 Jul 13 06:55:28 PM PDT 24 3933648799 ps
T318 /workspace/coverage/default/48.rom_ctrl_smoke.444215890 Jul 13 06:55:30 PM PDT 24 Jul 13 06:56:04 PM PDT 24 8043163485 ps
T319 /workspace/coverage/default/16.rom_ctrl_alert_test.3192489873 Jul 13 06:54:29 PM PDT 24 Jul 13 06:54:35 PM PDT 24 85564158 ps
T320 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2183810594 Jul 13 06:54:38 PM PDT 24 Jul 13 06:55:06 PM PDT 24 2943115776 ps
T48 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3269639900 Jul 13 06:55:29 PM PDT 24 Jul 13 08:54:14 PM PDT 24 190437742583 ps
T321 /workspace/coverage/default/47.rom_ctrl_alert_test.2881245602 Jul 13 06:55:29 PM PDT 24 Jul 13 06:55:38 PM PDT 24 2560972259 ps
T322 /workspace/coverage/default/41.rom_ctrl_stress_all.66871928 Jul 13 06:55:14 PM PDT 24 Jul 13 06:55:36 PM PDT 24 388981482 ps
T323 /workspace/coverage/default/36.rom_ctrl_stress_all.3744468128 Jul 13 06:55:06 PM PDT 24 Jul 13 06:56:00 PM PDT 24 6047273084 ps
T324 /workspace/coverage/default/27.rom_ctrl_smoke.186426094 Jul 13 06:54:39 PM PDT 24 Jul 13 06:55:15 PM PDT 24 6614602061 ps
T325 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3505279359 Jul 13 06:54:30 PM PDT 24 Jul 13 06:56:19 PM PDT 24 1701851049 ps
T326 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.520212829 Jul 13 06:55:27 PM PDT 24 Jul 13 06:57:59 PM PDT 24 74451363981 ps
T327 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2767158612 Jul 13 06:54:13 PM PDT 24 Jul 13 06:54:22 PM PDT 24 425268944 ps
T328 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2612892013 Jul 13 06:54:47 PM PDT 24 Jul 13 06:56:34 PM PDT 24 1723192913 ps
T329 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2766239329 Jul 13 06:55:05 PM PDT 24 Jul 13 06:55:34 PM PDT 24 14240389356 ps
T330 /workspace/coverage/default/43.rom_ctrl_alert_test.1016413471 Jul 13 06:55:25 PM PDT 24 Jul 13 06:55:37 PM PDT 24 2248688025 ps
T331 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1658902870 Jul 13 06:55:12 PM PDT 24 Jul 13 07:39:59 PM PDT 24 39885343254 ps
T84 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2916454991 Jul 13 06:55:05 PM PDT 24 Jul 13 06:55:17 PM PDT 24 4156614362 ps
T85 /workspace/coverage/default/38.rom_ctrl_smoke.2933845989 Jul 13 06:55:05 PM PDT 24 Jul 13 06:55:30 PM PDT 24 8236061160 ps
T86 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2671960516 Jul 13 06:55:29 PM PDT 24 Jul 13 06:58:49 PM PDT 24 71695926076 ps
T87 /workspace/coverage/default/21.rom_ctrl_alert_test.3665599249 Jul 13 06:54:39 PM PDT 24 Jul 13 06:54:49 PM PDT 24 770848356 ps
T88 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1483045989 Jul 13 06:54:54 PM PDT 24 Jul 13 06:55:01 PM PDT 24 427585789 ps
T89 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2934585002 Jul 13 06:54:13 PM PDT 24 Jul 13 06:56:28 PM PDT 24 11915704984 ps
T90 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2354635373 Jul 13 06:55:14 PM PDT 24 Jul 13 06:55:47 PM PDT 24 13120191634 ps
T91 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2300294234 Jul 13 06:54:19 PM PDT 24 Jul 13 06:56:38 PM PDT 24 23852610792 ps
T92 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.413810745 Jul 13 06:54:11 PM PDT 24 Jul 13 09:37:36 PM PDT 24 138062472966 ps
T93 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1902126723 Jul 13 06:55:20 PM PDT 24 Jul 13 07:32:43 PM PDT 24 26343469126 ps
T332 /workspace/coverage/default/32.rom_ctrl_alert_test.2410318341 Jul 13 06:54:56 PM PDT 24 Jul 13 06:55:09 PM PDT 24 1525142303 ps
T333 /workspace/coverage/default/31.rom_ctrl_stress_all.1627030887 Jul 13 06:54:47 PM PDT 24 Jul 13 06:55:38 PM PDT 24 12684357577 ps
T334 /workspace/coverage/default/29.rom_ctrl_stress_all.2247888699 Jul 13 06:54:48 PM PDT 24 Jul 13 06:55:27 PM PDT 24 3155152717 ps
T335 /workspace/coverage/default/19.rom_ctrl_smoke.1354117229 Jul 13 06:54:30 PM PDT 24 Jul 13 06:55:07 PM PDT 24 4042648550 ps
T336 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.858795128 Jul 13 06:55:20 PM PDT 24 Jul 13 08:37:01 PM PDT 24 22847922570 ps
T337 /workspace/coverage/default/42.rom_ctrl_stress_all.859084259 Jul 13 06:55:12 PM PDT 24 Jul 13 06:55:35 PM PDT 24 1738214177 ps
T338 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1385646538 Jul 13 06:55:12 PM PDT 24 Jul 13 06:55:29 PM PDT 24 2097384884 ps
T339 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.909346236 Jul 13 06:54:55 PM PDT 24 Jul 13 06:55:10 PM PDT 24 1314730056 ps
T340 /workspace/coverage/default/25.rom_ctrl_smoke.1855945596 Jul 13 06:54:45 PM PDT 24 Jul 13 06:54:55 PM PDT 24 831398552 ps
T341 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3498511143 Jul 13 06:54:27 PM PDT 24 Jul 13 06:54:44 PM PDT 24 7090914516 ps
T342 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3468515018 Jul 13 06:55:05 PM PDT 24 Jul 13 06:55:21 PM PDT 24 1714814518 ps
T343 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.809829478 Jul 13 06:54:37 PM PDT 24 Jul 13 06:54:52 PM PDT 24 6723674409 ps
T344 /workspace/coverage/default/10.rom_ctrl_alert_test.705195627 Jul 13 06:54:19 PM PDT 24 Jul 13 06:54:23 PM PDT 24 395853510 ps
T345 /workspace/coverage/default/49.rom_ctrl_alert_test.802125015 Jul 13 06:55:33 PM PDT 24 Jul 13 06:55:45 PM PDT 24 2305454223 ps
T346 /workspace/coverage/default/44.rom_ctrl_stress_all.2477117183 Jul 13 06:55:22 PM PDT 24 Jul 13 06:55:59 PM PDT 24 3524455711 ps
T347 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1257927193 Jul 13 06:54:05 PM PDT 24 Jul 13 06:54:18 PM PDT 24 3963384900 ps
T348 /workspace/coverage/default/39.rom_ctrl_alert_test.12060964 Jul 13 06:55:12 PM PDT 24 Jul 13 06:55:18 PM PDT 24 1140876371 ps
T349 /workspace/coverage/default/8.rom_ctrl_stress_all.2297240268 Jul 13 06:54:11 PM PDT 24 Jul 13 06:54:48 PM PDT 24 4193086422 ps
T350 /workspace/coverage/default/20.rom_ctrl_stress_all.2741721531 Jul 13 06:54:29 PM PDT 24 Jul 13 06:54:47 PM PDT 24 4399755278 ps
T351 /workspace/coverage/default/21.rom_ctrl_smoke.1729665888 Jul 13 06:54:37 PM PDT 24 Jul 13 06:54:58 PM PDT 24 1740289421 ps
T352 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2665835465 Jul 13 06:55:13 PM PDT 24 Jul 13 06:55:19 PM PDT 24 98598359 ps
T353 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2653444046 Jul 13 06:55:31 PM PDT 24 Jul 13 06:56:03 PM PDT 24 7695835262 ps
T354 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1934207525 Jul 13 06:54:01 PM PDT 24 Jul 13 06:55:09 PM PDT 24 1919358043 ps
T355 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3216286334 Jul 13 06:54:29 PM PDT 24 Jul 13 06:54:41 PM PDT 24 4340837450 ps
T356 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1035854389 Jul 13 06:55:12 PM PDT 24 Jul 13 06:55:29 PM PDT 24 1068321876 ps
T357 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2140112966 Jul 13 06:54:55 PM PDT 24 Jul 13 07:00:45 PM PDT 24 41137175636 ps
T358 /workspace/coverage/default/19.rom_ctrl_alert_test.2758184006 Jul 13 06:54:29 PM PDT 24 Jul 13 06:54:40 PM PDT 24 3634614306 ps
T359 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1451468089 Jul 13 06:54:20 PM PDT 24 Jul 13 06:54:36 PM PDT 24 747185575 ps
T360 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1242301476 Jul 13 06:54:20 PM PDT 24 Jul 13 06:54:30 PM PDT 24 1686621792 ps
T361 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1034756709 Jul 13 06:55:22 PM PDT 24 Jul 13 06:59:11 PM PDT 24 51855418511 ps
T362 /workspace/coverage/default/8.rom_ctrl_alert_test.3281915142 Jul 13 06:54:16 PM PDT 24 Jul 13 06:54:22 PM PDT 24 499483659 ps
T58 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.831201602 Jul 13 06:30:40 PM PDT 24 Jul 13 06:30:49 PM PDT 24 1069924592 ps
T59 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2888007417 Jul 13 06:30:47 PM PDT 24 Jul 13 06:31:58 PM PDT 24 7565619352 ps
T55 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2693525619 Jul 13 06:30:58 PM PDT 24 Jul 13 06:31:44 PM PDT 24 10372819149 ps
T363 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3868985851 Jul 13 06:30:56 PM PDT 24 Jul 13 06:31:10 PM PDT 24 2465057268 ps
T364 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3437381876 Jul 13 06:30:54 PM PDT 24 Jul 13 06:31:10 PM PDT 24 5340467382 ps
T62 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3390552055 Jul 13 06:30:40 PM PDT 24 Jul 13 06:31:29 PM PDT 24 7847880769 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2196924804 Jul 13 06:30:39 PM PDT 24 Jul 13 06:30:56 PM PDT 24 23141217994 ps
T100 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2223806503 Jul 13 06:30:47 PM PDT 24 Jul 13 06:31:08 PM PDT 24 7164019780 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1431849624 Jul 13 06:30:40 PM PDT 24 Jul 13 06:30:54 PM PDT 24 13066291948 ps
T56 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3618451880 Jul 13 06:30:45 PM PDT 24 Jul 13 06:31:30 PM PDT 24 5235189459 ps
T63 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1765342170 Jul 13 06:30:47 PM PDT 24 Jul 13 06:31:03 PM PDT 24 2917430383 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3964255354 Jul 13 06:30:39 PM PDT 24 Jul 13 06:30:50 PM PDT 24 3599496624 ps
T65 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2995539978 Jul 13 06:30:38 PM PDT 24 Jul 13 06:30:50 PM PDT 24 4751272458 ps
T66 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3686900900 Jul 13 06:30:40 PM PDT 24 Jul 13 06:31:01 PM PDT 24 4394588135 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2646259266 Jul 13 06:30:31 PM PDT 24 Jul 13 06:31:59 PM PDT 24 38565811281 ps
T68 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.462669226 Jul 13 06:30:48 PM PDT 24 Jul 13 06:31:17 PM PDT 24 1076456820 ps
T365 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.965226290 Jul 13 06:30:52 PM PDT 24 Jul 13 06:30:57 PM PDT 24 124791048 ps
T366 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2623225741 Jul 13 06:30:39 PM PDT 24 Jul 13 06:30:55 PM PDT 24 1676834828 ps
T69 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.806400572 Jul 13 06:30:47 PM PDT 24 Jul 13 06:31:01 PM PDT 24 7685129978 ps
T367 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3322880830 Jul 13 06:31:02 PM PDT 24 Jul 13 06:31:18 PM PDT 24 2150065228 ps
T368 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2383961588 Jul 13 06:30:42 PM PDT 24 Jul 13 06:30:59 PM PDT 24 1999579961 ps
T369 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.849846655 Jul 13 06:30:41 PM PDT 24 Jul 13 06:30:54 PM PDT 24 4825935828 ps
T57 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1614123283 Jul 13 06:30:41 PM PDT 24 Jul 13 06:32:00 PM PDT 24 1818402956 ps
T370 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.933332160 Jul 13 06:30:45 PM PDT 24 Jul 13 06:30:59 PM PDT 24 860088720 ps
T70 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1860021919 Jul 13 06:30:54 PM PDT 24 Jul 13 06:31:08 PM PDT 24 3079111660 ps
T371 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2011811548 Jul 13 06:30:42 PM PDT 24 Jul 13 06:31:00 PM PDT 24 1474920433 ps
T105 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1946497273 Jul 13 06:30:58 PM PDT 24 Jul 13 06:31:45 PM PDT 24 8008744396 ps
T372 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1945454686 Jul 13 06:30:40 PM PDT 24 Jul 13 06:31:09 PM PDT 24 1351016639 ps
T106 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4049754667 Jul 13 06:30:48 PM PDT 24 Jul 13 06:32:03 PM PDT 24 3474329580 ps
T75 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1921138532 Jul 13 06:30:39 PM PDT 24 Jul 13 06:31:55 PM PDT 24 20401504803 ps
T373 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1445986051 Jul 13 06:30:48 PM PDT 24 Jul 13 06:31:05 PM PDT 24 2009778979 ps
T109 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.841722386 Jul 13 06:30:47 PM PDT 24 Jul 13 06:31:27 PM PDT 24 496429805 ps
T76 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3404560039 Jul 13 06:30:53 PM PDT 24 Jul 13 06:31:21 PM PDT 24 3577500281 ps
T115 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2055545536 Jul 13 06:30:52 PM PDT 24 Jul 13 06:32:07 PM PDT 24 959969479 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2825090390 Jul 13 06:30:48 PM PDT 24 Jul 13 06:31:00 PM PDT 24 2617259579 ps
T375 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1871609618 Jul 13 06:30:56 PM PDT 24 Jul 13 06:31:06 PM PDT 24 496834843 ps
T113 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2145821272 Jul 13 06:30:49 PM PDT 24 Jul 13 06:32:05 PM PDT 24 8928824374 ps
T376 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3596141235 Jul 13 06:30:29 PM PDT 24 Jul 13 06:30:35 PM PDT 24 85529672 ps
T377 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3653845553 Jul 13 06:30:48 PM PDT 24 Jul 13 06:31:08 PM PDT 24 1699315409 ps
T378 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2241977833 Jul 13 06:30:38 PM PDT 24 Jul 13 06:30:56 PM PDT 24 2494394650 ps
T379 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.786003144 Jul 13 06:30:47 PM PDT 24 Jul 13 06:30:53 PM PDT 24 143519402 ps
T95 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4178259266 Jul 13 06:30:40 PM PDT 24 Jul 13 06:30:54 PM PDT 24 2410906214 ps
T380 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.446735680 Jul 13 06:30:48 PM PDT 24 Jul 13 06:31:36 PM PDT 24 28751486637 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1196987413 Jul 13 06:30:45 PM PDT 24 Jul 13 06:31:04 PM PDT 24 2014591420 ps
T96 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.596932636 Jul 13 06:31:02 PM PDT 24 Jul 13 06:31:19 PM PDT 24 8497926391 ps
T382 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1433696027 Jul 13 06:30:51 PM PDT 24 Jul 13 06:31:02 PM PDT 24 2285523165 ps
T108 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.127381625 Jul 13 06:30:56 PM PDT 24 Jul 13 06:32:10 PM PDT 24 3554542306 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4265743344 Jul 13 06:30:43 PM PDT 24 Jul 13 06:30:59 PM PDT 24 9013910374 ps
T80 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2430065124 Jul 13 06:30:55 PM PDT 24 Jul 13 06:31:53 PM PDT 24 8448706280 ps
T97 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1366712275 Jul 13 06:30:56 PM PDT 24 Jul 13 06:31:11 PM PDT 24 1378696624 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2315961303 Jul 13 06:30:49 PM PDT 24 Jul 13 06:31:03 PM PDT 24 6324698006 ps
T385 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3370724769 Jul 13 06:30:52 PM PDT 24 Jul 13 06:31:03 PM PDT 24 583574129 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1088990781 Jul 13 06:30:39 PM PDT 24 Jul 13 06:30:45 PM PDT 24 347446594 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2911534110 Jul 13 06:30:41 PM PDT 24 Jul 13 06:30:57 PM PDT 24 985801197 ps
T388 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.191976492 Jul 13 06:30:55 PM PDT 24 Jul 13 06:31:02 PM PDT 24 209761291 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2484953641 Jul 13 06:30:39 PM PDT 24 Jul 13 06:30:51 PM PDT 24 2182930734 ps
T390 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.148946864 Jul 13 06:30:55 PM PDT 24 Jul 13 06:31:03 PM PDT 24 686416191 ps
T107 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3760278199 Jul 13 06:30:46 PM PDT 24 Jul 13 06:31:30 PM PDT 24 2108538442 ps
T98 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2153767959 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:41 PM PDT 24 555454447 ps
T391 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4035581693 Jul 13 06:30:46 PM PDT 24 Jul 13 06:31:01 PM PDT 24 8601383748 ps
T392 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.321458666 Jul 13 06:30:56 PM PDT 24 Jul 13 06:31:14 PM PDT 24 8502350970 ps
T393 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1827704127 Jul 13 06:30:49 PM PDT 24 Jul 13 06:31:08 PM PDT 24 3730534165 ps
T394 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3380988364 Jul 13 06:30:46 PM PDT 24 Jul 13 06:31:02 PM PDT 24 3097352513 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2239062569 Jul 13 06:30:31 PM PDT 24 Jul 13 06:30:49 PM PDT 24 1626462012 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3869740262 Jul 13 06:30:46 PM PDT 24 Jul 13 06:30:59 PM PDT 24 7156014839 ps
T397 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1275034946 Jul 13 06:30:56 PM PDT 24 Jul 13 06:31:13 PM PDT 24 1775920630 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2386323616 Jul 13 06:30:46 PM PDT 24 Jul 13 06:30:56 PM PDT 24 2807707216 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.475408819 Jul 13 06:30:45 PM PDT 24 Jul 13 06:30:56 PM PDT 24 2097558963 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.190392590 Jul 13 06:30:56 PM PDT 24 Jul 13 06:31:44 PM PDT 24 3651492283 ps
T112 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3048579880 Jul 13 06:30:39 PM PDT 24 Jul 13 06:31:19 PM PDT 24 205733839 ps
T401 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3630092849 Jul 13 06:30:58 PM PDT 24 Jul 13 06:31:38 PM PDT 24 3448113392 ps
T402 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1689748520 Jul 13 06:30:46 PM PDT 24 Jul 13 06:31:04 PM PDT 24 1370264729 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3260072155 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:37 PM PDT 24 321213286 ps
T103 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3081358593 Jul 13 06:30:52 PM PDT 24 Jul 13 06:31:41 PM PDT 24 10000872066 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3818660283 Jul 13 06:30:46 PM PDT 24 Jul 13 06:31:01 PM PDT 24 4991938604 ps
T81 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3440389915 Jul 13 06:30:54 PM PDT 24 Jul 13 06:31:08 PM PDT 24 1538404986 ps
T405 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.664876585 Jul 13 06:30:36 PM PDT 24 Jul 13 06:30:53 PM PDT 24 2255797259 ps
T110 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1425518548 Jul 13 06:30:52 PM PDT 24 Jul 13 06:31:38 PM PDT 24 7641681524 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.274729066 Jul 13 06:30:42 PM PDT 24 Jul 13 06:30:52 PM PDT 24 1866234729 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.754504458 Jul 13 06:30:45 PM PDT 24 Jul 13 06:30:56 PM PDT 24 964079326 ps
T408 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2925482471 Jul 13 06:30:52 PM PDT 24 Jul 13 06:31:12 PM PDT 24 2074129622 ps
T409 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4107365653 Jul 13 06:30:52 PM PDT 24 Jul 13 06:30:57 PM PDT 24 333029979 ps
T410 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.875705661 Jul 13 06:30:43 PM PDT 24 Jul 13 06:30:48 PM PDT 24 168260783 ps
T104 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2860811511 Jul 13 06:30:41 PM PDT 24 Jul 13 06:31:46 PM PDT 24 8220907135 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3105025411 Jul 13 06:30:46 PM PDT 24 Jul 13 06:31:02 PM PDT 24 3685953971 ps
T412 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3485952525 Jul 13 06:30:39 PM PDT 24 Jul 13 06:30:50 PM PDT 24 1651216778 ps
T77 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.313723802 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:44 PM PDT 24 2985300376 ps
T413 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3458695924 Jul 13 06:30:47 PM PDT 24 Jul 13 06:31:10 PM PDT 24 2455422693 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2886546924 Jul 13 06:30:47 PM PDT 24 Jul 13 06:31:04 PM PDT 24 3928034829 ps
T415 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2942192687 Jul 13 06:30:51 PM PDT 24 Jul 13 06:31:03 PM PDT 24 1173592993 ps
T416 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3494751190 Jul 13 06:30:55 PM PDT 24 Jul 13 06:31:08 PM PDT 24 5712923381 ps
T417 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.444968745 Jul 13 06:30:52 PM PDT 24 Jul 13 06:31:09 PM PDT 24 1271439249 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.209188796 Jul 13 06:30:39 PM PDT 24 Jul 13 06:30:52 PM PDT 24 1281852636 ps
T419 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.860946652 Jul 13 06:30:46 PM PDT 24 Jul 13 06:31:03 PM PDT 24 4189453733 ps
T420 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1239616396 Jul 13 06:30:47 PM PDT 24 Jul 13 06:31:02 PM PDT 24 1596119093 ps
T421 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.842928739 Jul 13 06:30:55 PM PDT 24 Jul 13 06:31:08 PM PDT 24 2067064003 ps
T422 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3786230211 Jul 13 06:30:48 PM PDT 24 Jul 13 06:32:02 PM PDT 24 5178037665 ps
T423 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3978972538 Jul 13 06:30:52 PM PDT 24 Jul 13 06:31:03 PM PDT 24 3435390274 ps
T424 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4100755228 Jul 13 06:30:54 PM PDT 24 Jul 13 06:31:48 PM PDT 24 11488366684 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1579042122 Jul 13 06:30:41 PM PDT 24 Jul 13 06:30:57 PM PDT 24 12089282386 ps
T426 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1935857131 Jul 13 06:30:28 PM PDT 24 Jul 13 06:31:45 PM PDT 24 2805935355 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2166394932 Jul 13 06:30:40 PM PDT 24 Jul 13 06:30:53 PM PDT 24 1190130548 ps
T428 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2448549842 Jul 13 06:31:01 PM PDT 24 Jul 13 06:31:19 PM PDT 24 2018829485 ps
T114 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3515644987 Jul 13 06:30:39 PM PDT 24 Jul 13 06:31:23 PM PDT 24 4037315111 ps
T82 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1595457233 Jul 13 06:30:40 PM PDT 24 Jul 13 06:32:01 PM PDT 24 41424952319 ps
T429 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.199487147 Jul 13 06:30:41 PM PDT 24 Jul 13 06:30:58 PM PDT 24 4095108578 ps
T430 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1596428283 Jul 13 06:30:41 PM PDT 24 Jul 13 06:30:53 PM PDT 24 4825332825 ps
T83 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3323219140 Jul 13 06:30:46 PM PDT 24 Jul 13 06:30:59 PM PDT 24 5750445329 ps
T431 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3619038018 Jul 13 06:30:46 PM PDT 24 Jul 13 06:31:29 PM PDT 24 2161536604 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3001660186 Jul 13 06:30:46 PM PDT 24 Jul 13 06:30:53 PM PDT 24 163637906 ps
T111 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3897029871 Jul 13 06:30:52 PM PDT 24 Jul 13 06:32:02 PM PDT 24 948726754 ps
T433 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1139896196 Jul 13 06:31:16 PM PDT 24 Jul 13 06:31:21 PM PDT 24 87951682 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1482782828 Jul 13 06:30:29 PM PDT 24 Jul 13 06:30:47 PM PDT 24 2236605396 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.727900042 Jul 13 06:30:48 PM PDT 24 Jul 13 06:31:34 PM PDT 24 1522554881 ps
T78 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1387177187 Jul 13 06:31:01 PM PDT 24 Jul 13 06:31:06 PM PDT 24 174675930 ps
T436 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2478734249 Jul 13 06:30:56 PM PDT 24 Jul 13 06:31:02 PM PDT 24 232327853 ps
T437 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3725507171 Jul 13 06:30:29 PM PDT 24 Jul 13 06:30:39 PM PDT 24 848553399 ps
T438 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1645242797 Jul 13 06:30:56 PM PDT 24 Jul 13 06:31:25 PM PDT 24 566750223 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1638400165 Jul 13 06:30:31 PM PDT 24 Jul 13 06:31:06 PM PDT 24 9433695226 ps
T440 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.702337844 Jul 13 06:30:58 PM PDT 24 Jul 13 06:31:52 PM PDT 24 60797818580 ps
T441 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2182418045 Jul 13 06:31:01 PM PDT 24 Jul 13 06:31:22 PM PDT 24 10700976784 ps
T442 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1625315074 Jul 13 06:30:59 PM PDT 24 Jul 13 06:31:16 PM PDT 24 1830014256 ps
T443 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.805721591 Jul 13 06:30:51 PM PDT 24 Jul 13 06:31:07 PM PDT 24 1967486389 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2863661391 Jul 13 06:30:41 PM PDT 24 Jul 13 06:30:47 PM PDT 24 88220561 ps
T445 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2496696663 Jul 13 06:30:51 PM PDT 24 Jul 13 06:31:08 PM PDT 24 3333306131 ps
T446 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2931463425 Jul 13 06:30:55 PM PDT 24 Jul 13 06:31:08 PM PDT 24 2225009124 ps
T447 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3774729639 Jul 13 06:30:52 PM PDT 24 Jul 13 06:30:59 PM PDT 24 431275814 ps
T448 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2606317466 Jul 13 06:30:40 PM PDT 24 Jul 13 06:30:45 PM PDT 24 108511522 ps
T449 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.124711815 Jul 13 06:30:42 PM PDT 24 Jul 13 06:31:11 PM PDT 24 8991062720 ps
T79 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2176390471 Jul 13 06:30:42 PM PDT 24 Jul 13 06:30:58 PM PDT 24 7159048586 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1980504187 Jul 13 06:30:39 PM PDT 24 Jul 13 06:30:51 PM PDT 24 2329178700 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.713939172 Jul 13 06:30:37 PM PDT 24 Jul 13 06:30:42 PM PDT 24 98950576 ps
T452 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4266742659 Jul 13 06:30:46 PM PDT 24 Jul 13 06:30:57 PM PDT 24 1209138244 ps
T453 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3035868611 Jul 13 06:30:41 PM PDT 24 Jul 13 06:30:51 PM PDT 24 785519797 ps
T454 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1826820258 Jul 13 06:30:54 PM PDT 24 Jul 13 06:31:05 PM PDT 24 8234622170 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.598596921 Jul 13 06:30:47 PM PDT 24 Jul 13 06:31:46 PM PDT 24 6398270123 ps
T456 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.494705665 Jul 13 06:30:46 PM PDT 24 Jul 13 06:31:02 PM PDT 24 6333869182 ps
T457 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1866854160 Jul 13 06:30:37 PM PDT 24 Jul 13 06:31:25 PM PDT 24 1905654348 ps
T458 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3975195898 Jul 13 06:30:42 PM PDT 24 Jul 13 06:30:48 PM PDT 24 321188752 ps
T459 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2681148077 Jul 13 06:30:48 PM PDT 24 Jul 13 06:30:56 PM PDT 24 349981563 ps
T460 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1616171332 Jul 13 06:30:51 PM PDT 24 Jul 13 06:31:02 PM PDT 24 3323856350 ps
T461 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4058401653 Jul 13 06:30:32 PM PDT 24 Jul 13 06:30:44 PM PDT 24 956261458 ps
T462 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3919279751 Jul 13 06:30:49 PM PDT 24 Jul 13 06:31:01 PM PDT 24 4305334320 ps
T463 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.729220678 Jul 13 06:30:30 PM PDT 24 Jul 13 06:30:37 PM PDT 24 86581395 ps
T464 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.265023997 Jul 13 06:30:55 PM PDT 24 Jul 13 06:31:09 PM PDT 24 1024425110 ps

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3693446924
Short name T1
Test name
Test status
Simulation time 9363137971 ps
CPU time 140.1 seconds
Started Jul 13 06:55:20 PM PDT 24
Finished Jul 13 06:57:41 PM PDT 24
Peak memory 233056 kb
Host smart-27cdd7f9-8080-4619-86bb-52ae8a256934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693446924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3693446924
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2811061673
Short name T13
Test name
Test status
Simulation time 174411030616 ps
CPU time 559.39 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 07:03:42 PM PDT 24
Peak memory 229500 kb
Host smart-51a52974-72a1-4d03-ab22-e5b04e58feb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811061673 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2811061673
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1845964678
Short name T18
Test name
Test status
Simulation time 65880517495 ps
CPU time 286.61 seconds
Started Jul 13 06:54:20 PM PDT 24
Finished Jul 13 06:59:07 PM PDT 24
Peak memory 225236 kb
Host smart-745ae848-f973-4d9e-820c-11dc70ff8397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845964678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1845964678
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2690504078
Short name T12
Test name
Test status
Simulation time 90742219918 ps
CPU time 5568.37 seconds
Started Jul 13 06:54:28 PM PDT 24
Finished Jul 13 08:27:17 PM PDT 24
Peak memory 235840 kb
Host smart-964d3dd8-354a-4d35-943e-604fa7409823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690504078 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2690504078
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2693525619
Short name T55
Test name
Test status
Simulation time 10372819149 ps
CPU time 43.92 seconds
Started Jul 13 06:30:58 PM PDT 24
Finished Jul 13 06:31:44 PM PDT 24
Peak memory 210840 kb
Host smart-74494f66-0e84-4c68-a4c5-56641e14d159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693525619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2693525619
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.367414444
Short name T240
Test name
Test status
Simulation time 2466536854 ps
CPU time 143.51 seconds
Started Jul 13 06:54:24 PM PDT 24
Finished Jul 13 06:56:49 PM PDT 24
Peak memory 237864 kb
Host smart-c761c7e4-5ba4-4c13-b70f-60344d1ec32b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367414444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.367414444
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3933269806
Short name T23
Test name
Test status
Simulation time 1702402243 ps
CPU time 100.83 seconds
Started Jul 13 06:54:05 PM PDT 24
Finished Jul 13 06:55:47 PM PDT 24
Peak memory 237684 kb
Host smart-ac6d3eec-c57a-4cab-bd01-b7564f4fa759
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933269806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3933269806
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3764339162
Short name T4
Test name
Test status
Simulation time 1504201811 ps
CPU time 8.99 seconds
Started Jul 13 06:54:47 PM PDT 24
Finished Jul 13 06:54:56 PM PDT 24
Peak memory 211344 kb
Host smart-651240fc-c189-4ecc-88ff-38c817f3a70c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764339162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3764339162
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2995539978
Short name T65
Test name
Test status
Simulation time 4751272458 ps
CPU time 11.69 seconds
Started Jul 13 06:30:38 PM PDT 24
Finished Jul 13 06:30:50 PM PDT 24
Peak memory 210724 kb
Host smart-a64097cc-55ae-414d-a7de-fa52958ebf97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995539978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2995539978
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1946497273
Short name T105
Test name
Test status
Simulation time 8008744396 ps
CPU time 46.41 seconds
Started Jul 13 06:30:58 PM PDT 24
Finished Jul 13 06:31:45 PM PDT 24
Peak memory 218976 kb
Host smart-d7fd7038-ce55-4536-acfd-f14d7e0ac541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946497273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1946497273
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.818324420
Short name T11
Test name
Test status
Simulation time 3873874778 ps
CPU time 39.57 seconds
Started Jul 13 06:54:48 PM PDT 24
Finished Jul 13 06:55:29 PM PDT 24
Peak memory 213236 kb
Host smart-c33d1a97-a97f-481d-ae8f-02938ff3df90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818324420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.818324420
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.803551764
Short name T39
Test name
Test status
Simulation time 1841072721 ps
CPU time 13.18 seconds
Started Jul 13 06:54:32 PM PDT 24
Finished Jul 13 06:54:46 PM PDT 24
Peak memory 212016 kb
Host smart-50df6ce0-f23a-46b4-9123-5449e287cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803551764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.803551764
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3801567369
Short name T54
Test name
Test status
Simulation time 179526473 ps
CPU time 9.34 seconds
Started Jul 13 06:54:33 PM PDT 24
Finished Jul 13 06:54:43 PM PDT 24
Peak memory 212296 kb
Host smart-16f8b27f-5675-49e1-abc9-0c6484bd5e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801567369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3801567369
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.127381625
Short name T108
Test name
Test status
Simulation time 3554542306 ps
CPU time 72.6 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:32:10 PM PDT 24
Peak memory 218992 kb
Host smart-c927b126-950d-4d7d-85a9-8a1517079f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127381625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.127381625
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2646259266
Short name T67
Test name
Test status
Simulation time 38565811281 ps
CPU time 85.65 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:31:59 PM PDT 24
Peak memory 210688 kb
Host smart-bd0db3f0-f331-4512-8960-7efe581e9c4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646259266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2646259266
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.841722386
Short name T109
Test name
Test status
Simulation time 496429805 ps
CPU time 38.1 seconds
Started Jul 13 06:30:47 PM PDT 24
Finished Jul 13 06:31:27 PM PDT 24
Peak memory 218912 kb
Host smart-c74e4a4e-8853-4ad4-a8d8-146ddc4dbd03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841722386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.841722386
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3048579880
Short name T112
Test name
Test status
Simulation time 205733839 ps
CPU time 38.87 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:31:19 PM PDT 24
Peak memory 212332 kb
Host smart-e8791e40-9cb3-490c-b635-889476c4c5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048579880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3048579880
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2153767959
Short name T98
Test name
Test status
Simulation time 555454447 ps
CPU time 8.1 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:41 PM PDT 24
Peak memory 210604 kb
Host smart-4fc142a0-e441-40c3-a123-b054ad642ac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153767959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2153767959
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2916454991
Short name T84
Test name
Test status
Simulation time 4156614362 ps
CPU time 11.12 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 06:55:17 PM PDT 24
Peak memory 211460 kb
Host smart-efbb34e5-cb10-4a76-9517-f45fcac032ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916454991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2916454991
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4114731274
Short name T15
Test name
Test status
Simulation time 32783822492 ps
CPU time 1272.18 seconds
Started Jul 13 06:54:44 PM PDT 24
Finished Jul 13 07:15:57 PM PDT 24
Peak memory 235848 kb
Host smart-4bb86afd-7585-40fe-9621-7567c0e166c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114731274 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.4114731274
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3596141235
Short name T376
Test name
Test status
Simulation time 85529672 ps
CPU time 4.7 seconds
Started Jul 13 06:30:29 PM PDT 24
Finished Jul 13 06:30:35 PM PDT 24
Peak memory 217540 kb
Host smart-78ad3438-8875-44e3-bf79-3da2d26f7e51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596141235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3596141235
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.729220678
Short name T463
Test name
Test status
Simulation time 86581395 ps
CPU time 4.84 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:37 PM PDT 24
Peak memory 210748 kb
Host smart-e3c12773-df90-4604-b8bb-27be6769da27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729220678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.729220678
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.313723802
Short name T77
Test name
Test status
Simulation time 2985300376 ps
CPU time 12.11 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:44 PM PDT 24
Peak memory 210740 kb
Host smart-a0fe254c-94ad-4447-a7f6-f8ad27ac5446
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313723802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.313723802
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4058401653
Short name T461
Test name
Test status
Simulation time 956261458 ps
CPU time 10.71 seconds
Started Jul 13 06:30:32 PM PDT 24
Finished Jul 13 06:30:44 PM PDT 24
Peak memory 219028 kb
Host smart-ee494301-358f-4ca1-a202-2b7d6df991b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058401653 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4058401653
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3725507171
Short name T437
Test name
Test status
Simulation time 848553399 ps
CPU time 9.05 seconds
Started Jul 13 06:30:29 PM PDT 24
Finished Jul 13 06:30:39 PM PDT 24
Peak memory 210712 kb
Host smart-5001c595-a0d9-4029-a010-8b41e038c39c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725507171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3725507171
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1482782828
Short name T434
Test name
Test status
Simulation time 2236605396 ps
CPU time 17.01 seconds
Started Jul 13 06:30:29 PM PDT 24
Finished Jul 13 06:30:47 PM PDT 24
Peak memory 210672 kb
Host smart-42767ae2-6021-4806-b775-a89bb2d7edd1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482782828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1482782828
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3260072155
Short name T403
Test name
Test status
Simulation time 321213286 ps
CPU time 4.3 seconds
Started Jul 13 06:30:30 PM PDT 24
Finished Jul 13 06:30:37 PM PDT 24
Peak memory 210576 kb
Host smart-a1b1a932-b6af-444e-ad6e-db09a6fc20f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260072155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3260072155
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2239062569
Short name T395
Test name
Test status
Simulation time 1626462012 ps
CPU time 16.01 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:30:49 PM PDT 24
Peak memory 218980 kb
Host smart-a2d02398-c316-4719-ab03-77754ca81eec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239062569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2239062569
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1935857131
Short name T426
Test name
Test status
Simulation time 2805935355 ps
CPU time 76.37 seconds
Started Jul 13 06:30:28 PM PDT 24
Finished Jul 13 06:31:45 PM PDT 24
Peak memory 211408 kb
Host smart-22f12d93-e281-47b0-8ea2-281ac03a6779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935857131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1935857131
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1088990781
Short name T386
Test name
Test status
Simulation time 347446594 ps
CPU time 4.83 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:30:45 PM PDT 24
Peak memory 210648 kb
Host smart-8c80a44f-52c2-4fc0-b1c9-d2f0fc8ccf40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088990781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1088990781
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3818660283
Short name T404
Test name
Test status
Simulation time 4991938604 ps
CPU time 13.06 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:31:01 PM PDT 24
Peak memory 210696 kb
Host smart-c6f21b95-4c79-4969-8cf9-34c7bc1d5c1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818660283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3818660283
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3485952525
Short name T412
Test name
Test status
Simulation time 1651216778 ps
CPU time 9.64 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:30:50 PM PDT 24
Peak memory 219000 kb
Host smart-7128e309-8a53-47af-9c2c-38e6bdbdd2af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485952525 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3485952525
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2863661391
Short name T444
Test name
Test status
Simulation time 88220561 ps
CPU time 4.43 seconds
Started Jul 13 06:30:41 PM PDT 24
Finished Jul 13 06:30:47 PM PDT 24
Peak memory 217548 kb
Host smart-892b8882-469e-4a64-b8a8-144758977728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863661391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2863661391
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2241977833
Short name T378
Test name
Test status
Simulation time 2494394650 ps
CPU time 17.18 seconds
Started Jul 13 06:30:38 PM PDT 24
Finished Jul 13 06:30:56 PM PDT 24
Peak memory 210636 kb
Host smart-51773ba0-f1db-46de-8480-023ec5873fb3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241977833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2241977833
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2623225741
Short name T366
Test name
Test status
Simulation time 1676834828 ps
CPU time 14.75 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:30:55 PM PDT 24
Peak memory 210540 kb
Host smart-cecd08f3-0e28-477c-8438-62fb0a52c35f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623225741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2623225741
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1638400165
Short name T439
Test name
Test status
Simulation time 9433695226 ps
CPU time 33.67 seconds
Started Jul 13 06:30:31 PM PDT 24
Finished Jul 13 06:31:06 PM PDT 24
Peak memory 210776 kb
Host smart-01bd95f0-ae51-4e61-89c7-e863bd727882
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638400165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1638400165
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1765342170
Short name T63
Test name
Test status
Simulation time 2917430383 ps
CPU time 14.63 seconds
Started Jul 13 06:30:47 PM PDT 24
Finished Jul 13 06:31:03 PM PDT 24
Peak memory 210836 kb
Host smart-8e8d0bbc-8b70-415f-8743-9bf22aec452b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765342170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1765342170
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.933332160
Short name T370
Test name
Test status
Simulation time 860088720 ps
CPU time 13.3 seconds
Started Jul 13 06:30:45 PM PDT 24
Finished Jul 13 06:30:59 PM PDT 24
Peak memory 218952 kb
Host smart-0a82a586-9d52-434d-9a25-c4f78fd756f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933332160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.933332160
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.727900042
Short name T435
Test name
Test status
Simulation time 1522554881 ps
CPU time 45.12 seconds
Started Jul 13 06:30:48 PM PDT 24
Finished Jul 13 06:31:34 PM PDT 24
Peak memory 212096 kb
Host smart-61a57943-4275-4392-9919-fe6c4ff60c12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727900042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.727900042
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2886546924
Short name T414
Test name
Test status
Simulation time 3928034829 ps
CPU time 15.6 seconds
Started Jul 13 06:30:47 PM PDT 24
Finished Jul 13 06:31:04 PM PDT 24
Peak memory 219008 kb
Host smart-716585ce-bf25-4408-bc55-ae09af6a5784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886546924 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2886546924
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.806400572
Short name T69
Test name
Test status
Simulation time 7685129978 ps
CPU time 12.15 seconds
Started Jul 13 06:30:47 PM PDT 24
Finished Jul 13 06:31:01 PM PDT 24
Peak memory 218940 kb
Host smart-4f5ff5cf-4b09-4361-9443-df601acd63ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806400572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.806400572
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1645242797
Short name T438
Test name
Test status
Simulation time 566750223 ps
CPU time 27.9 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:25 PM PDT 24
Peak memory 210480 kb
Host smart-74fbc038-145c-4809-a8d6-edcdb766d000
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645242797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1645242797
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1275034946
Short name T397
Test name
Test status
Simulation time 1775920630 ps
CPU time 15.9 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:13 PM PDT 24
Peak memory 210572 kb
Host smart-d697ac13-4734-4408-9d39-847be5a88b08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275034946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1275034946
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3653845553
Short name T377
Test name
Test status
Simulation time 1699315409 ps
CPU time 18.6 seconds
Started Jul 13 06:30:48 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 218968 kb
Host smart-19dc065a-850c-471c-b307-ad83dc96c057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653845553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3653845553
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.786003144
Short name T379
Test name
Test status
Simulation time 143519402 ps
CPU time 5.12 seconds
Started Jul 13 06:30:47 PM PDT 24
Finished Jul 13 06:30:53 PM PDT 24
Peak memory 218936 kb
Host smart-21ce2405-496f-449e-ab9f-a2bf38d2b789
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786003144 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.786003144
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4107365653
Short name T409
Test name
Test status
Simulation time 333029979 ps
CPU time 4.44 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:30:57 PM PDT 24
Peak memory 217320 kb
Host smart-07139457-d4d9-4807-b4c8-3bf95febf22a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107365653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4107365653
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2223806503
Short name T100
Test name
Test status
Simulation time 7164019780 ps
CPU time 19.5 seconds
Started Jul 13 06:30:47 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 210772 kb
Host smart-55e2488e-3b11-4e1b-a5c9-4e58cf963165
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223806503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2223806503
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1239616396
Short name T420
Test name
Test status
Simulation time 1596119093 ps
CPU time 13.62 seconds
Started Jul 13 06:30:47 PM PDT 24
Finished Jul 13 06:31:02 PM PDT 24
Peak memory 210712 kb
Host smart-764b23bc-3718-41f8-ab19-8984e714cfc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239616396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1239616396
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3458695924
Short name T413
Test name
Test status
Simulation time 2455422693 ps
CPU time 21.07 seconds
Started Jul 13 06:30:47 PM PDT 24
Finished Jul 13 06:31:10 PM PDT 24
Peak memory 219032 kb
Host smart-988f4aa9-84b5-4dd1-a509-fb9f82901dfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458695924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3458695924
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3619038018
Short name T431
Test name
Test status
Simulation time 2161536604 ps
CPU time 42.07 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:31:29 PM PDT 24
Peak memory 211932 kb
Host smart-f766b981-93bd-4c28-8dd1-17efe6dbec9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619038018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3619038018
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3380988364
Short name T394
Test name
Test status
Simulation time 3097352513 ps
CPU time 14.35 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:31:02 PM PDT 24
Peak memory 219096 kb
Host smart-e6915741-1255-4d3e-9391-05ef797621aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380988364 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3380988364
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1139896196
Short name T433
Test name
Test status
Simulation time 87951682 ps
CPU time 4.28 seconds
Started Jul 13 06:31:16 PM PDT 24
Finished Jul 13 06:31:21 PM PDT 24
Peak memory 217920 kb
Host smart-4c447b9c-2a88-4f2a-b016-54c86112ffac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139896196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1139896196
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.446735680
Short name T380
Test name
Test status
Simulation time 28751486637 ps
CPU time 46.54 seconds
Started Jul 13 06:30:48 PM PDT 24
Finished Jul 13 06:31:36 PM PDT 24
Peak memory 210768 kb
Host smart-004f4e46-3f95-42d8-8fab-5dc5b254db86
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446735680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.446735680
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1827704127
Short name T393
Test name
Test status
Simulation time 3730534165 ps
CPU time 17.56 seconds
Started Jul 13 06:30:49 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 210884 kb
Host smart-d11440f5-9bb5-4961-baa3-f3d0244cdf69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827704127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1827704127
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1826820258
Short name T454
Test name
Test status
Simulation time 8234622170 ps
CPU time 10.59 seconds
Started Jul 13 06:30:54 PM PDT 24
Finished Jul 13 06:31:05 PM PDT 24
Peak memory 219016 kb
Host smart-3db730ab-b100-4650-ada8-26f8f260615a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826820258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1826820258
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2145821272
Short name T113
Test name
Test status
Simulation time 8928824374 ps
CPU time 75.16 seconds
Started Jul 13 06:30:49 PM PDT 24
Finished Jul 13 06:32:05 PM PDT 24
Peak memory 211588 kb
Host smart-96bc1ce7-de6c-420b-a675-fb3870bc940a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145821272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2145821272
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2942192687
Short name T415
Test name
Test status
Simulation time 1173592993 ps
CPU time 11.58 seconds
Started Jul 13 06:30:51 PM PDT 24
Finished Jul 13 06:31:03 PM PDT 24
Peak memory 218844 kb
Host smart-c92788b5-b0dc-4559-9d41-4b496b63f7da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942192687 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2942192687
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.805721591
Short name T443
Test name
Test status
Simulation time 1967486389 ps
CPU time 15.59 seconds
Started Jul 13 06:30:51 PM PDT 24
Finished Jul 13 06:31:07 PM PDT 24
Peak memory 218728 kb
Host smart-ebadc0cf-e1ac-44bc-8020-c8689edf4e45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805721591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.805721591
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3081358593
Short name T103
Test name
Test status
Simulation time 10000872066 ps
CPU time 48.15 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:31:41 PM PDT 24
Peak memory 210776 kb
Host smart-20e79a9c-79b7-43f9-b98d-59963b94bd4e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081358593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3081358593
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3978972538
Short name T423
Test name
Test status
Simulation time 3435390274 ps
CPU time 9.72 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:31:03 PM PDT 24
Peak memory 210852 kb
Host smart-b0d068ce-2b36-47c6-9971-8e6c4861ef30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978972538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3978972538
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2925482471
Short name T408
Test name
Test status
Simulation time 2074129622 ps
CPU time 19.69 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:31:12 PM PDT 24
Peak memory 218952 kb
Host smart-6d236fae-4940-47eb-950d-836a213b98a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925482471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2925482471
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3897029871
Short name T111
Test name
Test status
Simulation time 948726754 ps
CPU time 70.22 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:32:02 PM PDT 24
Peak memory 212396 kb
Host smart-9d956f5e-8f2d-4b14-a066-ea6331715565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897029871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3897029871
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1445986051
Short name T373
Test name
Test status
Simulation time 2009778979 ps
CPU time 16.12 seconds
Started Jul 13 06:30:48 PM PDT 24
Finished Jul 13 06:31:05 PM PDT 24
Peak memory 219160 kb
Host smart-2e20c532-1389-4b0b-896d-575ae25b93d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445986051 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1445986051
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3323219140
Short name T83
Test name
Test status
Simulation time 5750445329 ps
CPU time 13.24 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:30:59 PM PDT 24
Peak memory 210672 kb
Host smart-faf675d0-3493-4229-84d5-2d64f0e0ff35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323219140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3323219140
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4100755228
Short name T424
Test name
Test status
Simulation time 11488366684 ps
CPU time 53.47 seconds
Started Jul 13 06:30:54 PM PDT 24
Finished Jul 13 06:31:48 PM PDT 24
Peak memory 210712 kb
Host smart-f1bed8b7-91d8-420b-9f40-3ae5b5dbd9bc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100755228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4100755228
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.494705665
Short name T456
Test name
Test status
Simulation time 6333869182 ps
CPU time 15.65 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:31:02 PM PDT 24
Peak memory 211128 kb
Host smart-ada7d22c-cec3-4709-badb-64bd14370c4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494705665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.494705665
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.444968745
Short name T417
Test name
Test status
Simulation time 1271439249 ps
CPU time 15.86 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:31:09 PM PDT 24
Peak memory 218856 kb
Host smart-441de556-31a5-4ccf-b16f-d5c897e7f8fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444968745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.444968745
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2055545536
Short name T115
Test name
Test status
Simulation time 959969479 ps
CPU time 74.49 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:32:07 PM PDT 24
Peak memory 211984 kb
Host smart-4fa7e826-6b5f-4bdd-82f9-1865dc7265b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055545536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2055545536
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2315961303
Short name T384
Test name
Test status
Simulation time 6324698006 ps
CPU time 13.46 seconds
Started Jul 13 06:30:49 PM PDT 24
Finished Jul 13 06:31:03 PM PDT 24
Peak memory 219024 kb
Host smart-6ec893fb-0cd6-4702-99d6-df85f852fb75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315961303 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2315961303
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3440389915
Short name T81
Test name
Test status
Simulation time 1538404986 ps
CPU time 13.43 seconds
Started Jul 13 06:30:54 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 210708 kb
Host smart-3316cf76-d0fe-48bb-8a80-5c6678a527cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440389915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3440389915
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.462669226
Short name T68
Test name
Test status
Simulation time 1076456820 ps
CPU time 27.82 seconds
Started Jul 13 06:30:48 PM PDT 24
Finished Jul 13 06:31:17 PM PDT 24
Peak memory 210748 kb
Host smart-b4bccee6-926b-46e8-ae6f-835026df51aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462669226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.462669226
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1860021919
Short name T70
Test name
Test status
Simulation time 3079111660 ps
CPU time 13.36 seconds
Started Jul 13 06:30:54 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 218960 kb
Host smart-e2670929-3895-4b34-a663-a5c3641939ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860021919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1860021919
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.860946652
Short name T419
Test name
Test status
Simulation time 4189453733 ps
CPU time 16.69 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:31:03 PM PDT 24
Peak memory 218984 kb
Host smart-07de91d6-fdfd-45f1-830c-fe568c9e55d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860946652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.860946652
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4049754667
Short name T106
Test name
Test status
Simulation time 3474329580 ps
CPU time 73.34 seconds
Started Jul 13 06:30:48 PM PDT 24
Finished Jul 13 06:32:03 PM PDT 24
Peak memory 218888 kb
Host smart-faffd16e-6dc2-45bc-bb76-b67f22200cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049754667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4049754667
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2448549842
Short name T428
Test name
Test status
Simulation time 2018829485 ps
CPU time 16.84 seconds
Started Jul 13 06:31:01 PM PDT 24
Finished Jul 13 06:31:19 PM PDT 24
Peak memory 218896 kb
Host smart-3427b037-0a7c-43c3-8d2e-fccf82c9879c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448549842 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2448549842
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3494751190
Short name T416
Test name
Test status
Simulation time 5712923381 ps
CPU time 11.86 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 210800 kb
Host smart-0484d518-4337-425a-b285-302bb7413434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494751190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3494751190
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3404560039
Short name T76
Test name
Test status
Simulation time 3577500281 ps
CPU time 27.47 seconds
Started Jul 13 06:30:53 PM PDT 24
Finished Jul 13 06:31:21 PM PDT 24
Peak memory 210804 kb
Host smart-f3f61488-ea99-40e1-b733-580d529dedd2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404560039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3404560039
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.596932636
Short name T96
Test name
Test status
Simulation time 8497926391 ps
CPU time 16.6 seconds
Started Jul 13 06:31:02 PM PDT 24
Finished Jul 13 06:31:19 PM PDT 24
Peak memory 211088 kb
Host smart-7debc1cb-6f82-4c14-9f31-58df6d2b8920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596932636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.596932636
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3322880830
Short name T367
Test name
Test status
Simulation time 2150065228 ps
CPU time 14.9 seconds
Started Jul 13 06:31:02 PM PDT 24
Finished Jul 13 06:31:18 PM PDT 24
Peak memory 219016 kb
Host smart-22abd756-be32-454f-b7ed-ebbb70afee96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322880830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3322880830
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.190392590
Short name T400
Test name
Test status
Simulation time 3651492283 ps
CPU time 46.9 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:44 PM PDT 24
Peak memory 219000 kb
Host smart-6b027555-0d8a-4870-bb8d-dc3f84ff8ba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190392590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.190392590
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1625315074
Short name T442
Test name
Test status
Simulation time 1830014256 ps
CPU time 16.13 seconds
Started Jul 13 06:30:59 PM PDT 24
Finished Jul 13 06:31:16 PM PDT 24
Peak memory 218880 kb
Host smart-0b7b53e2-cd77-4b6d-89c3-da2035a56229
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625315074 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1625315074
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.148946864
Short name T390
Test name
Test status
Simulation time 686416191 ps
CPU time 6.69 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:03 PM PDT 24
Peak memory 210656 kb
Host smart-8934f44f-9774-4963-8d2e-0ef37f300241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148946864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.148946864
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2430065124
Short name T80
Test name
Test status
Simulation time 8448706280 ps
CPU time 55.53 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:53 PM PDT 24
Peak memory 210824 kb
Host smart-4d53c14d-5ddc-403f-88de-d522155b79f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430065124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2430065124
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.321458666
Short name T392
Test name
Test status
Simulation time 8502350970 ps
CPU time 16.72 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:14 PM PDT 24
Peak memory 218992 kb
Host smart-1839bd4c-4410-4914-aeda-b085580fae15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321458666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.321458666
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2182418045
Short name T441
Test name
Test status
Simulation time 10700976784 ps
CPU time 20.11 seconds
Started Jul 13 06:31:01 PM PDT 24
Finished Jul 13 06:31:22 PM PDT 24
Peak memory 218916 kb
Host smart-9d907776-b15b-4867-9dbe-0ac04c7503fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182418045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2182418045
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3868985851
Short name T363
Test name
Test status
Simulation time 2465057268 ps
CPU time 12.34 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:10 PM PDT 24
Peak memory 219064 kb
Host smart-aba7fa8c-5328-4c37-b574-96ae89666ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868985851 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3868985851
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2478734249
Short name T436
Test name
Test status
Simulation time 232327853 ps
CPU time 4.32 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:02 PM PDT 24
Peak memory 210620 kb
Host smart-b5883811-0e4a-4112-a9fb-073f6bf18c1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478734249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2478734249
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3630092849
Short name T401
Test name
Test status
Simulation time 3448113392 ps
CPU time 38.65 seconds
Started Jul 13 06:30:58 PM PDT 24
Finished Jul 13 06:31:38 PM PDT 24
Peak memory 210668 kb
Host smart-904abbf5-8b06-493e-98be-52421260ae74
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630092849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3630092849
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.265023997
Short name T464
Test name
Test status
Simulation time 1024425110 ps
CPU time 11.93 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:09 PM PDT 24
Peak memory 218912 kb
Host smart-09195ab1-fafb-4007-b601-bf05d80698eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265023997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.265023997
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2931463425
Short name T446
Test name
Test status
Simulation time 2225009124 ps
CPU time 12.49 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 218964 kb
Host smart-292b601a-d1e0-444a-bb93-0d21241a0b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931463425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2931463425
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3437381876
Short name T364
Test name
Test status
Simulation time 5340467382 ps
CPU time 15.11 seconds
Started Jul 13 06:30:54 PM PDT 24
Finished Jul 13 06:31:10 PM PDT 24
Peak memory 218968 kb
Host smart-f2b73195-0c0d-4a9a-bc51-4d121b5c5c7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437381876 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3437381876
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1387177187
Short name T78
Test name
Test status
Simulation time 174675930 ps
CPU time 4.38 seconds
Started Jul 13 06:31:01 PM PDT 24
Finished Jul 13 06:31:06 PM PDT 24
Peak memory 210620 kb
Host smart-d87048a6-e400-4d65-b39d-0971cf2b50e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387177187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1387177187
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.702337844
Short name T440
Test name
Test status
Simulation time 60797818580 ps
CPU time 52.41 seconds
Started Jul 13 06:30:58 PM PDT 24
Finished Jul 13 06:31:52 PM PDT 24
Peak memory 210676 kb
Host smart-1e23f808-7711-4b8a-8f01-9e0025768472
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702337844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.702337844
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.842928739
Short name T421
Test name
Test status
Simulation time 2067064003 ps
CPU time 11.32 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 218908 kb
Host smart-9c902067-7073-4783-8218-7a10edeb3bab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842928739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.842928739
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.191976492
Short name T388
Test name
Test status
Simulation time 209761291 ps
CPU time 6.95 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:02 PM PDT 24
Peak memory 218988 kb
Host smart-bb680467-e572-4e8b-b47a-760fd78730ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191976492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.191976492
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2196924804
Short name T99
Test name
Test status
Simulation time 23141217994 ps
CPU time 16.27 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:30:56 PM PDT 24
Peak memory 218916 kb
Host smart-a0e82794-030c-47a8-9f1e-9756548669aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196924804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2196924804
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2166394932
Short name T427
Test name
Test status
Simulation time 1190130548 ps
CPU time 11.9 seconds
Started Jul 13 06:30:40 PM PDT 24
Finished Jul 13 06:30:53 PM PDT 24
Peak memory 210724 kb
Host smart-4574e64c-986f-4512-b7b1-88dd8232e27a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166394932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2166394932
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1196987413
Short name T381
Test name
Test status
Simulation time 2014591420 ps
CPU time 18.87 seconds
Started Jul 13 06:30:45 PM PDT 24
Finished Jul 13 06:31:04 PM PDT 24
Peak memory 210724 kb
Host smart-1fe368a0-a951-4cde-a4ac-e78f999081bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196987413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1196987413
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3919279751
Short name T462
Test name
Test status
Simulation time 4305334320 ps
CPU time 11.25 seconds
Started Jul 13 06:30:49 PM PDT 24
Finished Jul 13 06:31:01 PM PDT 24
Peak memory 218900 kb
Host smart-23ee408d-bc8f-4c71-942e-1750fbdd11fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919279751 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3919279751
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2176390471
Short name T79
Test name
Test status
Simulation time 7159048586 ps
CPU time 15.23 seconds
Started Jul 13 06:30:42 PM PDT 24
Finished Jul 13 06:30:58 PM PDT 24
Peak memory 210772 kb
Host smart-7c65aab2-9dcf-4b02-acbb-e6952e077eca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176390471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2176390471
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3975195898
Short name T458
Test name
Test status
Simulation time 321188752 ps
CPU time 4.38 seconds
Started Jul 13 06:30:42 PM PDT 24
Finished Jul 13 06:30:48 PM PDT 24
Peak memory 210868 kb
Host smart-54fdad76-8ef4-483e-b217-5dd32691b049
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975195898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3975195898
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1579042122
Short name T425
Test name
Test status
Simulation time 12089282386 ps
CPU time 15.82 seconds
Started Jul 13 06:30:41 PM PDT 24
Finished Jul 13 06:30:57 PM PDT 24
Peak memory 210848 kb
Host smart-70108885-e525-4265-8513-b892c7eda38b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579042122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1579042122
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1921138532
Short name T75
Test name
Test status
Simulation time 20401504803 ps
CPU time 75.8 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:31:55 PM PDT 24
Peak memory 210772 kb
Host smart-b29f279c-ec1b-411b-9b53-303f106fb17e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921138532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1921138532
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3105025411
Short name T411
Test name
Test status
Simulation time 3685953971 ps
CPU time 15.2 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:31:02 PM PDT 24
Peak memory 210832 kb
Host smart-e02e3356-d002-4f73-a295-f5ab2eda5b23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105025411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3105025411
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2911534110
Short name T387
Test name
Test status
Simulation time 985801197 ps
CPU time 14.98 seconds
Started Jul 13 06:30:41 PM PDT 24
Finished Jul 13 06:30:57 PM PDT 24
Peak memory 218964 kb
Host smart-6efcc822-bb31-4953-8f6d-255dbe74a0ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911534110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2911534110
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3515644987
Short name T114
Test name
Test status
Simulation time 4037315111 ps
CPU time 43.35 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:31:23 PM PDT 24
Peak memory 211172 kb
Host smart-c6e67fc7-fe9e-45c9-b020-fde601f113e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515644987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3515644987
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3964255354
Short name T64
Test name
Test status
Simulation time 3599496624 ps
CPU time 10.07 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:30:50 PM PDT 24
Peak memory 218600 kb
Host smart-aac03cd6-a518-4b0e-8558-4675ae2f13b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964255354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3964255354
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.209188796
Short name T418
Test name
Test status
Simulation time 1281852636 ps
CPU time 12.6 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:30:52 PM PDT 24
Peak memory 210724 kb
Host smart-dccfb4ae-1f19-412e-9820-2bfede6bb326
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209188796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.209188796
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3686900900
Short name T66
Test name
Test status
Simulation time 4394588135 ps
CPU time 20.25 seconds
Started Jul 13 06:30:40 PM PDT 24
Finished Jul 13 06:31:01 PM PDT 24
Peak memory 210804 kb
Host smart-ac613138-60c8-4d62-8912-fb6903bfdef7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686900900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3686900900
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3001660186
Short name T432
Test name
Test status
Simulation time 163637906 ps
CPU time 5.35 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:30:53 PM PDT 24
Peak memory 218968 kb
Host smart-5b613fbe-a91a-4240-b949-cc772f6b67c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001660186 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3001660186
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2386323616
Short name T398
Test name
Test status
Simulation time 2807707216 ps
CPU time 8.97 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:30:56 PM PDT 24
Peak memory 210616 kb
Host smart-5121986a-a54a-48fb-801b-29b8c16c1cf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386323616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2386323616
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.754504458
Short name T407
Test name
Test status
Simulation time 964079326 ps
CPU time 10.27 seconds
Started Jul 13 06:30:45 PM PDT 24
Finished Jul 13 06:30:56 PM PDT 24
Peak memory 210460 kb
Host smart-20bad6f4-dbfb-4e24-9369-1bd66a74b950
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754504458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.754504458
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.475408819
Short name T399
Test name
Test status
Simulation time 2097558963 ps
CPU time 10.53 seconds
Started Jul 13 06:30:45 PM PDT 24
Finished Jul 13 06:30:56 PM PDT 24
Peak memory 210448 kb
Host smart-fd622a39-960c-4f44-98d6-9a3dfe908a32
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475408819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
475408819
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.598596921
Short name T455
Test name
Test status
Simulation time 6398270123 ps
CPU time 58.22 seconds
Started Jul 13 06:30:47 PM PDT 24
Finished Jul 13 06:31:46 PM PDT 24
Peak memory 210724 kb
Host smart-cf8112af-5636-4f97-b724-9b95363ff6a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598596921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.598596921
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1980504187
Short name T450
Test name
Test status
Simulation time 2329178700 ps
CPU time 11.73 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:30:51 PM PDT 24
Peak memory 218972 kb
Host smart-72a3ae1b-5a06-497e-bc9e-04e63a551c7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980504187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1980504187
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2484953641
Short name T389
Test name
Test status
Simulation time 2182930734 ps
CPU time 11.64 seconds
Started Jul 13 06:30:39 PM PDT 24
Finished Jul 13 06:30:51 PM PDT 24
Peak memory 219032 kb
Host smart-73142205-d67e-4d3a-a392-b13a8e2c2fb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484953641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2484953641
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2681148077
Short name T459
Test name
Test status
Simulation time 349981563 ps
CPU time 6.67 seconds
Started Jul 13 06:30:48 PM PDT 24
Finished Jul 13 06:30:56 PM PDT 24
Peak memory 210524 kb
Host smart-aa64a353-ac56-42dd-a5ab-815eef95c32e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681148077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2681148077
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.831201602
Short name T58
Test name
Test status
Simulation time 1069924592 ps
CPU time 8.48 seconds
Started Jul 13 06:30:40 PM PDT 24
Finished Jul 13 06:30:49 PM PDT 24
Peak memory 210708 kb
Host smart-3e03877d-e795-44d4-a5d8-c2aef0f64688
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831201602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.831201602
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2825090390
Short name T374
Test name
Test status
Simulation time 2617259579 ps
CPU time 10.23 seconds
Started Jul 13 06:30:48 PM PDT 24
Finished Jul 13 06:31:00 PM PDT 24
Peak memory 210632 kb
Host smart-775bda78-d4a9-48c5-befe-93fee2e7ba9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825090390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2825090390
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.274729066
Short name T406
Test name
Test status
Simulation time 1866234729 ps
CPU time 9.97 seconds
Started Jul 13 06:30:42 PM PDT 24
Finished Jul 13 06:30:52 PM PDT 24
Peak memory 218952 kb
Host smart-b5529852-f6bd-4c95-8767-49464d29252b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274729066 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.274729066
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3869740262
Short name T396
Test name
Test status
Simulation time 7156014839 ps
CPU time 12.45 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:30:59 PM PDT 24
Peak memory 218848 kb
Host smart-fdfd35a0-9a6b-4360-a9d5-68680fad2e7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869740262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3869740262
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2383961588
Short name T368
Test name
Test status
Simulation time 1999579961 ps
CPU time 15.98 seconds
Started Jul 13 06:30:42 PM PDT 24
Finished Jul 13 06:30:59 PM PDT 24
Peak memory 210596 kb
Host smart-44581760-080d-46d1-9f44-50cd403e1757
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383961588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2383961588
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.664876585
Short name T405
Test name
Test status
Simulation time 2255797259 ps
CPU time 17.05 seconds
Started Jul 13 06:30:36 PM PDT 24
Finished Jul 13 06:30:53 PM PDT 24
Peak memory 210528 kb
Host smart-f0414e50-292b-49c0-beca-f6089bc97f93
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664876585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
664876585
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3390552055
Short name T62
Test name
Test status
Simulation time 7847880769 ps
CPU time 48.1 seconds
Started Jul 13 06:30:40 PM PDT 24
Finished Jul 13 06:31:29 PM PDT 24
Peak memory 210856 kb
Host smart-8580d4a2-ae7e-4a01-b23a-e239ff98b47f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390552055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3390552055
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.713939172
Short name T451
Test name
Test status
Simulation time 98950576 ps
CPU time 4.51 seconds
Started Jul 13 06:30:37 PM PDT 24
Finished Jul 13 06:30:42 PM PDT 24
Peak memory 210680 kb
Host smart-113602e9-1301-48b7-92e6-c6e444b9b32f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713939172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.713939172
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4265743344
Short name T383
Test name
Test status
Simulation time 9013910374 ps
CPU time 15.69 seconds
Started Jul 13 06:30:43 PM PDT 24
Finished Jul 13 06:30:59 PM PDT 24
Peak memory 219324 kb
Host smart-f52a8517-b550-4aac-8bee-4433197a6425
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265743344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4265743344
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1866854160
Short name T457
Test name
Test status
Simulation time 1905654348 ps
CPU time 46.92 seconds
Started Jul 13 06:30:37 PM PDT 24
Finished Jul 13 06:31:25 PM PDT 24
Peak memory 218920 kb
Host smart-e411bb0a-8860-493e-9384-bc674946bd54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866854160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1866854160
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2606317466
Short name T448
Test name
Test status
Simulation time 108511522 ps
CPU time 4.43 seconds
Started Jul 13 06:30:40 PM PDT 24
Finished Jul 13 06:30:45 PM PDT 24
Peak memory 212408 kb
Host smart-e0ea322e-83f3-4fc5-bb51-165e7add9b5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606317466 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2606317466
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1596428283
Short name T430
Test name
Test status
Simulation time 4825332825 ps
CPU time 11.48 seconds
Started Jul 13 06:30:41 PM PDT 24
Finished Jul 13 06:30:53 PM PDT 24
Peak memory 218848 kb
Host smart-6f8897a3-8f36-453b-b446-c88632a86e46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596428283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1596428283
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1945454686
Short name T372
Test name
Test status
Simulation time 1351016639 ps
CPU time 28.52 seconds
Started Jul 13 06:30:40 PM PDT 24
Finished Jul 13 06:31:09 PM PDT 24
Peak memory 210652 kb
Host smart-8e6d979a-9cbf-4e3b-a4df-3532c1766fcc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945454686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1945454686
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1431849624
Short name T94
Test name
Test status
Simulation time 13066291948 ps
CPU time 13.78 seconds
Started Jul 13 06:30:40 PM PDT 24
Finished Jul 13 06:30:54 PM PDT 24
Peak memory 211228 kb
Host smart-6f5baf19-9159-40a8-a78f-e651a5058b9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431849624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1431849624
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4035581693
Short name T391
Test name
Test status
Simulation time 8601383748 ps
CPU time 13.64 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:31:01 PM PDT 24
Peak memory 218928 kb
Host smart-504970d1-fc96-4a22-b377-bb0d2e6485d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035581693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4035581693
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3760278199
Short name T107
Test name
Test status
Simulation time 2108538442 ps
CPU time 43.32 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:31:30 PM PDT 24
Peak memory 212188 kb
Host smart-50db8a54-e8d7-4de3-a7c2-6c8e281f0d06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760278199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3760278199
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3035868611
Short name T453
Test name
Test status
Simulation time 785519797 ps
CPU time 9.16 seconds
Started Jul 13 06:30:41 PM PDT 24
Finished Jul 13 06:30:51 PM PDT 24
Peak memory 218992 kb
Host smart-47f566cb-d809-4c1b-8a70-5369e41af357
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035868611 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3035868611
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.875705661
Short name T410
Test name
Test status
Simulation time 168260783 ps
CPU time 4.32 seconds
Started Jul 13 06:30:43 PM PDT 24
Finished Jul 13 06:30:48 PM PDT 24
Peak memory 217616 kb
Host smart-253a25dd-76ee-44c1-98e9-101ab55e9ce3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875705661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.875705661
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.124711815
Short name T449
Test name
Test status
Simulation time 8991062720 ps
CPU time 28.49 seconds
Started Jul 13 06:30:42 PM PDT 24
Finished Jul 13 06:31:11 PM PDT 24
Peak memory 210776 kb
Host smart-660fb529-f7cc-44ab-9af9-9f8344a7776d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124711815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.124711815
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.199487147
Short name T429
Test name
Test status
Simulation time 4095108578 ps
CPU time 16.97 seconds
Started Jul 13 06:30:41 PM PDT 24
Finished Jul 13 06:30:58 PM PDT 24
Peak memory 218972 kb
Host smart-c76d32ee-7ed4-4fb7-8511-cc3755b803c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199487147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.199487147
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2011811548
Short name T371
Test name
Test status
Simulation time 1474920433 ps
CPU time 16.79 seconds
Started Jul 13 06:30:42 PM PDT 24
Finished Jul 13 06:31:00 PM PDT 24
Peak memory 219248 kb
Host smart-769390f1-734b-48ef-a0cb-7ba40c37589e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011811548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2011811548
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1614123283
Short name T57
Test name
Test status
Simulation time 1818402956 ps
CPU time 78.09 seconds
Started Jul 13 06:30:41 PM PDT 24
Finished Jul 13 06:32:00 PM PDT 24
Peak memory 212340 kb
Host smart-af244287-ffb7-4f24-87c0-1a0e0f980086
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614123283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1614123283
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.849846655
Short name T369
Test name
Test status
Simulation time 4825935828 ps
CPU time 12.38 seconds
Started Jul 13 06:30:41 PM PDT 24
Finished Jul 13 06:30:54 PM PDT 24
Peak memory 219032 kb
Host smart-fed291e7-51a7-4433-8f2d-474aed91880e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849846655 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.849846655
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4266742659
Short name T452
Test name
Test status
Simulation time 1209138244 ps
CPU time 9.16 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:30:57 PM PDT 24
Peak memory 217620 kb
Host smart-9d6f33bd-0380-4146-9a8d-ba3e65b80e9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266742659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4266742659
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1595457233
Short name T82
Test name
Test status
Simulation time 41424952319 ps
CPU time 79.78 seconds
Started Jul 13 06:30:40 PM PDT 24
Finished Jul 13 06:32:01 PM PDT 24
Peak memory 210776 kb
Host smart-16e470f4-c57d-4ac7-86a3-cd33a679fa1e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595457233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1595457233
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4178259266
Short name T95
Test name
Test status
Simulation time 2410906214 ps
CPU time 12.99 seconds
Started Jul 13 06:30:40 PM PDT 24
Finished Jul 13 06:30:54 PM PDT 24
Peak memory 218980 kb
Host smart-1a1f9264-40f9-447f-a09c-b3440c4e5857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178259266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.4178259266
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1689748520
Short name T402
Test name
Test status
Simulation time 1370264729 ps
CPU time 16.32 seconds
Started Jul 13 06:30:46 PM PDT 24
Finished Jul 13 06:31:04 PM PDT 24
Peak memory 218864 kb
Host smart-7c8caf61-e184-4a20-8a71-f2ebdb221e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689748520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1689748520
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3786230211
Short name T422
Test name
Test status
Simulation time 5178037665 ps
CPU time 72.92 seconds
Started Jul 13 06:30:48 PM PDT 24
Finished Jul 13 06:32:02 PM PDT 24
Peak memory 218924 kb
Host smart-3b5d79b6-44d9-4112-a2ad-2cefdec21a9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786230211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3786230211
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1433696027
Short name T382
Test name
Test status
Simulation time 2285523165 ps
CPU time 10.63 seconds
Started Jul 13 06:30:51 PM PDT 24
Finished Jul 13 06:31:02 PM PDT 24
Peak memory 219092 kb
Host smart-11d8d2bc-42e6-4ec9-a6d0-7c244e2689e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433696027 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1433696027
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.965226290
Short name T365
Test name
Test status
Simulation time 124791048 ps
CPU time 4.44 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:30:57 PM PDT 24
Peak memory 217656 kb
Host smart-401bcea3-a1e4-4786-b4da-997b14b03e5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965226290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.965226290
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2860811511
Short name T104
Test name
Test status
Simulation time 8220907135 ps
CPU time 63.82 seconds
Started Jul 13 06:30:41 PM PDT 24
Finished Jul 13 06:31:46 PM PDT 24
Peak memory 210740 kb
Host smart-d24e4621-6220-4eda-a1dd-83979c9fc091
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860811511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2860811511
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1366712275
Short name T97
Test name
Test status
Simulation time 1378696624 ps
CPU time 13.91 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:11 PM PDT 24
Peak memory 218900 kb
Host smart-60b86a1a-7cd2-4e39-8ad5-5dcc885327e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366712275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1366712275
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3370724769
Short name T385
Test name
Test status
Simulation time 583574129 ps
CPU time 10.66 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:31:03 PM PDT 24
Peak memory 218608 kb
Host smart-444a9723-d82f-4d67-b3bf-36ee1d2babd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370724769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3370724769
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1425518548
Short name T110
Test name
Test status
Simulation time 7641681524 ps
CPU time 45.78 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:31:38 PM PDT 24
Peak memory 218952 kb
Host smart-7fc4d963-6d2d-4296-8c2d-961f3043f3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425518548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1425518548
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1616171332
Short name T460
Test name
Test status
Simulation time 3323856350 ps
CPU time 10.1 seconds
Started Jul 13 06:30:51 PM PDT 24
Finished Jul 13 06:31:02 PM PDT 24
Peak memory 218996 kb
Host smart-df3d0b19-ee51-4ea5-ba98-334960a79300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616171332 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1616171332
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1871609618
Short name T375
Test name
Test status
Simulation time 496834843 ps
CPU time 7.94 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:06 PM PDT 24
Peak memory 210612 kb
Host smart-c09c445f-f74b-4e46-8305-015f4b79a8ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871609618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1871609618
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2888007417
Short name T59
Test name
Test status
Simulation time 7565619352 ps
CPU time 69.89 seconds
Started Jul 13 06:30:47 PM PDT 24
Finished Jul 13 06:31:58 PM PDT 24
Peak memory 210752 kb
Host smart-401f4233-0ca9-4d67-aa95-bac4932a7bcf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888007417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2888007417
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3774729639
Short name T447
Test name
Test status
Simulation time 431275814 ps
CPU time 6.97 seconds
Started Jul 13 06:30:52 PM PDT 24
Finished Jul 13 06:30:59 PM PDT 24
Peak memory 218316 kb
Host smart-58591e1f-8913-47e4-abec-b3ea29a41331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774729639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3774729639
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2496696663
Short name T445
Test name
Test status
Simulation time 3333306131 ps
CPU time 17.04 seconds
Started Jul 13 06:30:51 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 219024 kb
Host smart-7c1713d5-0b83-472b-b2c1-4e1583071b57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496696663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2496696663
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3618451880
Short name T56
Test name
Test status
Simulation time 5235189459 ps
CPU time 43.98 seconds
Started Jul 13 06:30:45 PM PDT 24
Finished Jul 13 06:31:30 PM PDT 24
Peak memory 218976 kb
Host smart-e2a234e7-8a76-42e2-8fe8-50c15d17cf90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618451880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3618451880
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4045578718
Short name T137
Test name
Test status
Simulation time 1349921903 ps
CPU time 12.98 seconds
Started Jul 13 06:54:04 PM PDT 24
Finished Jul 13 06:54:18 PM PDT 24
Peak memory 211264 kb
Host smart-be2edeb7-c596-46ed-9e4a-64616d66839a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045578718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4045578718
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1934207525
Short name T354
Test name
Test status
Simulation time 1919358043 ps
CPU time 67.75 seconds
Started Jul 13 06:54:01 PM PDT 24
Finished Jul 13 06:55:09 PM PDT 24
Peak memory 236540 kb
Host smart-cec1e00d-8428-45ce-8b96-0ea4ea1a7ff0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934207525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1934207525
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1491434578
Short name T199
Test name
Test status
Simulation time 3944161598 ps
CPU time 22.55 seconds
Started Jul 13 06:54:03 PM PDT 24
Finished Jul 13 06:54:26 PM PDT 24
Peak memory 212020 kb
Host smart-3dce17d6-3780-4ee9-9529-77fcc8a2240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491434578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1491434578
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1257927193
Short name T347
Test name
Test status
Simulation time 3963384900 ps
CPU time 11.65 seconds
Started Jul 13 06:54:05 PM PDT 24
Finished Jul 13 06:54:18 PM PDT 24
Peak memory 211432 kb
Host smart-e0185f6c-18ba-43c9-96ec-e1a662f039e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257927193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1257927193
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.515476467
Short name T22
Test name
Test status
Simulation time 2227841516 ps
CPU time 57.19 seconds
Started Jul 13 06:54:04 PM PDT 24
Finished Jul 13 06:55:02 PM PDT 24
Peak memory 236856 kb
Host smart-ba7ac230-ab8a-4662-9e59-0f127cfda7be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515476467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.515476467
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3377863510
Short name T6
Test name
Test status
Simulation time 5247926454 ps
CPU time 18.37 seconds
Started Jul 13 06:54:01 PM PDT 24
Finished Jul 13 06:54:19 PM PDT 24
Peak memory 214256 kb
Host smart-2571b305-89be-4a76-836a-e2a474e736d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377863510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3377863510
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1304989955
Short name T248
Test name
Test status
Simulation time 10102891374 ps
CPU time 59.83 seconds
Started Jul 13 06:54:04 PM PDT 24
Finished Jul 13 06:55:04 PM PDT 24
Peak memory 219404 kb
Host smart-ba4553d8-1027-47f9-b28d-c2a569cf0bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304989955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1304989955
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2711865817
Short name T27
Test name
Test status
Simulation time 1244585301 ps
CPU time 11.45 seconds
Started Jul 13 06:54:03 PM PDT 24
Finished Jul 13 06:54:15 PM PDT 24
Peak memory 211324 kb
Host smart-95eaeb17-a1c6-4a76-9783-50447629d8a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711865817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2711865817
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.680312502
Short name T281
Test name
Test status
Simulation time 223767892036 ps
CPU time 296.09 seconds
Started Jul 13 06:54:04 PM PDT 24
Finished Jul 13 06:59:01 PM PDT 24
Peak memory 225140 kb
Host smart-fd9a7512-e455-46de-ac05-49f684403d74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680312502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.680312502
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2666386887
Short name T179
Test name
Test status
Simulation time 8241496963 ps
CPU time 13.22 seconds
Started Jul 13 06:54:06 PM PDT 24
Finished Jul 13 06:54:20 PM PDT 24
Peak memory 212632 kb
Host smart-5b139714-be8a-41fb-b04c-21d38b29530a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666386887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2666386887
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.336056007
Short name T124
Test name
Test status
Simulation time 1480604695 ps
CPU time 13.88 seconds
Started Jul 13 06:54:06 PM PDT 24
Finished Jul 13 06:54:21 PM PDT 24
Peak memory 211440 kb
Host smart-13bbd1c8-21a7-415b-a00d-64a116398646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=336056007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.336056007
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3190146119
Short name T21
Test name
Test status
Simulation time 6041431331 ps
CPU time 104.64 seconds
Started Jul 13 06:54:05 PM PDT 24
Finished Jul 13 06:55:50 PM PDT 24
Peak memory 236344 kb
Host smart-d006e496-c6b5-4aeb-b4f1-de1e8443b5b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190146119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3190146119
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3095388549
Short name T206
Test name
Test status
Simulation time 1048924628 ps
CPU time 13.65 seconds
Started Jul 13 06:54:03 PM PDT 24
Finished Jul 13 06:54:17 PM PDT 24
Peak memory 213624 kb
Host smart-48b74730-15f9-4df3-8280-d5c1fa2fd527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095388549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3095388549
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.288662511
Short name T170
Test name
Test status
Simulation time 1959399937 ps
CPU time 27.75 seconds
Started Jul 13 06:54:03 PM PDT 24
Finished Jul 13 06:54:31 PM PDT 24
Peak memory 213968 kb
Host smart-b2c634c5-918e-4522-b905-9ce5e746984f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288662511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.288662511
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.705195627
Short name T344
Test name
Test status
Simulation time 395853510 ps
CPU time 4.23 seconds
Started Jul 13 06:54:19 PM PDT 24
Finished Jul 13 06:54:23 PM PDT 24
Peak memory 211296 kb
Host smart-08695457-5c5c-49fb-8ce5-ee310bac06df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705195627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.705195627
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1451468089
Short name T359
Test name
Test status
Simulation time 747185575 ps
CPU time 14.65 seconds
Started Jul 13 06:54:20 PM PDT 24
Finished Jul 13 06:54:36 PM PDT 24
Peak memory 212044 kb
Host smart-4c1944f1-22dc-48e1-99ea-76a66eb83fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451468089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1451468089
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1242301476
Short name T360
Test name
Test status
Simulation time 1686621792 ps
CPU time 9.61 seconds
Started Jul 13 06:54:20 PM PDT 24
Finished Jul 13 06:54:30 PM PDT 24
Peak memory 211376 kb
Host smart-077627a9-4280-4d6e-91b6-c9096230538a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242301476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1242301476
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3912071147
Short name T241
Test name
Test status
Simulation time 180716752 ps
CPU time 10.38 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 06:54:33 PM PDT 24
Peak memory 212916 kb
Host smart-b7eb4668-3317-4851-ac4a-e21bf3ae7d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912071147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3912071147
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1954374749
Short name T280
Test name
Test status
Simulation time 193836851 ps
CPU time 11.41 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 06:54:34 PM PDT 24
Peak memory 211260 kb
Host smart-e43fcf71-6a80-4cc1-9aa2-3e39a6e55f06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954374749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1954374749
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1695186160
Short name T274
Test name
Test status
Simulation time 3937384401 ps
CPU time 11.59 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 06:54:35 PM PDT 24
Peak memory 211388 kb
Host smart-1fd14d07-09e1-4de3-978f-bc7c2591b672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695186160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1695186160
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2300294234
Short name T91
Test name
Test status
Simulation time 23852610792 ps
CPU time 138.17 seconds
Started Jul 13 06:54:19 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 212652 kb
Host smart-5633da81-c94e-4254-821a-3e03f7b49d9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300294234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2300294234
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2165693575
Short name T256
Test name
Test status
Simulation time 14955743030 ps
CPU time 29.54 seconds
Started Jul 13 06:54:21 PM PDT 24
Finished Jul 13 06:54:51 PM PDT 24
Peak memory 212204 kb
Host smart-6d6baba5-a564-4c47-b4be-f3ae7484891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165693575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2165693575
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2235875860
Short name T246
Test name
Test status
Simulation time 995502676 ps
CPU time 10.67 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 06:54:33 PM PDT 24
Peak memory 211376 kb
Host smart-f1810484-7cc4-4828-8ccb-7022043567c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235875860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2235875860
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1243160690
Short name T262
Test name
Test status
Simulation time 14045344420 ps
CPU time 34.14 seconds
Started Jul 13 06:54:23 PM PDT 24
Finished Jul 13 06:54:58 PM PDT 24
Peak memory 214076 kb
Host smart-4f7bff01-26a1-4def-be3e-0f60626a9d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243160690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1243160690
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4014763007
Short name T225
Test name
Test status
Simulation time 4743451903 ps
CPU time 43.82 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 06:55:07 PM PDT 24
Peak memory 213728 kb
Host smart-6abde7a6-6013-4144-a944-54e1a6fb3a50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014763007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4014763007
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1586293638
Short name T46
Test name
Test status
Simulation time 141267992435 ps
CPU time 2526.5 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 07:36:30 PM PDT 24
Peak memory 238440 kb
Host smart-e6c76252-4234-4b8e-91b9-526ee37f7301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586293638 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1586293638
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3953017207
Short name T175
Test name
Test status
Simulation time 6893260841 ps
CPU time 13.91 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 06:54:36 PM PDT 24
Peak memory 211348 kb
Host smart-ad7025f6-c9f9-4dd4-91c8-8103e9583973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953017207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3953017207
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3587160536
Short name T235
Test name
Test status
Simulation time 12606628182 ps
CPU time 167.01 seconds
Started Jul 13 06:54:20 PM PDT 24
Finished Jul 13 06:57:07 PM PDT 24
Peak memory 233768 kb
Host smart-69ff7891-3461-402c-be4c-e6f0a4ebb092
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587160536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3587160536
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3799180072
Short name T253
Test name
Test status
Simulation time 5183860102 ps
CPU time 20.71 seconds
Started Jul 13 06:54:21 PM PDT 24
Finished Jul 13 06:54:42 PM PDT 24
Peak memory 212204 kb
Host smart-28b78768-d89a-44e2-8a39-65e8b79e0da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799180072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3799180072
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.795442379
Short name T141
Test name
Test status
Simulation time 775905555 ps
CPU time 7.31 seconds
Started Jul 13 06:54:23 PM PDT 24
Finished Jul 13 06:54:31 PM PDT 24
Peak memory 211416 kb
Host smart-6f21e04f-887e-4c58-85ad-60accc0ce55d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795442379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.795442379
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3668929313
Short name T72
Test name
Test status
Simulation time 747923055 ps
CPU time 10.14 seconds
Started Jul 13 06:54:19 PM PDT 24
Finished Jul 13 06:54:30 PM PDT 24
Peak memory 213736 kb
Host smart-d1aba40c-2929-415c-bb4e-27312f0a8080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668929313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3668929313
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4210969924
Short name T159
Test name
Test status
Simulation time 3544367732 ps
CPU time 31.18 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 06:54:54 PM PDT 24
Peak memory 214796 kb
Host smart-6e51939d-0785-4ca9-a879-7b2f244939e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210969924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4210969924
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.107414627
Short name T174
Test name
Test status
Simulation time 2711126763 ps
CPU time 12.45 seconds
Started Jul 13 06:54:24 PM PDT 24
Finished Jul 13 06:54:38 PM PDT 24
Peak memory 211412 kb
Host smart-dc58c2a8-2aa7-4b80-938e-2474e0f5fccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107414627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.107414627
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2371213031
Short name T149
Test name
Test status
Simulation time 4132084514 ps
CPU time 33.91 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 06:54:57 PM PDT 24
Peak memory 212028 kb
Host smart-f0106bd3-48f3-4597-a787-657edd662914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371213031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2371213031
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2943356939
Short name T32
Test name
Test status
Simulation time 822434537 ps
CPU time 10.04 seconds
Started Jul 13 06:54:23 PM PDT 24
Finished Jul 13 06:54:34 PM PDT 24
Peak memory 211360 kb
Host smart-f23bcf90-710c-4579-80cb-e55cc7a399aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943356939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2943356939
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2305797041
Short name T166
Test name
Test status
Simulation time 15342859249 ps
CPU time 34.97 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 06:54:57 PM PDT 24
Peak memory 214284 kb
Host smart-3ec31551-4db2-4ba9-9747-18864dc6231b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305797041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2305797041
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4100584455
Short name T120
Test name
Test status
Simulation time 3932905173 ps
CPU time 38.58 seconds
Started Jul 13 06:54:19 PM PDT 24
Finished Jul 13 06:54:59 PM PDT 24
Peak memory 216388 kb
Host smart-e7d42ad2-3e0e-4f43-943e-53d28b60b9da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100584455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4100584455
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3446422715
Short name T204
Test name
Test status
Simulation time 1941655069 ps
CPU time 15.73 seconds
Started Jul 13 06:54:30 PM PDT 24
Finished Jul 13 06:54:46 PM PDT 24
Peak memory 211328 kb
Host smart-3da67bc0-c191-44d6-bbb9-c9fb226869a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446422715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3446422715
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.130787458
Short name T258
Test name
Test status
Simulation time 300861777029 ps
CPU time 224.66 seconds
Started Jul 13 06:54:20 PM PDT 24
Finished Jul 13 06:58:05 PM PDT 24
Peak memory 236956 kb
Host smart-ec58aa72-ba88-4245-b312-0febdfcab671
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130787458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.130787458
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1872033245
Short name T259
Test name
Test status
Simulation time 4393343380 ps
CPU time 34.75 seconds
Started Jul 13 06:54:23 PM PDT 24
Finished Jul 13 06:54:58 PM PDT 24
Peak memory 212312 kb
Host smart-75045cb7-7a24-4760-9554-81a6d274f04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872033245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1872033245
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2203545340
Short name T184
Test name
Test status
Simulation time 12955871544 ps
CPU time 15.88 seconds
Started Jul 13 06:54:21 PM PDT 24
Finished Jul 13 06:54:38 PM PDT 24
Peak memory 211496 kb
Host smart-bf132177-6659-454f-9da6-0a6d03d0eb0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203545340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2203545340
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2035791111
Short name T297
Test name
Test status
Simulation time 3841026420 ps
CPU time 18.27 seconds
Started Jul 13 06:54:21 PM PDT 24
Finished Jul 13 06:54:40 PM PDT 24
Peak memory 213880 kb
Host smart-7d81e08b-feb5-41de-8269-78120792e529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035791111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2035791111
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1616034716
Short name T161
Test name
Test status
Simulation time 1410653922 ps
CPU time 24.57 seconds
Started Jul 13 06:54:22 PM PDT 24
Finished Jul 13 06:54:47 PM PDT 24
Peak memory 215960 kb
Host smart-148ce795-a9ba-4e57-91eb-dc0997376670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616034716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1616034716
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2663321889
Short name T140
Test name
Test status
Simulation time 85734336 ps
CPU time 4.21 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:54:34 PM PDT 24
Peak memory 211356 kb
Host smart-ee1c5baf-0e84-47f4-aea8-459621f7064a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663321889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2663321889
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4105317404
Short name T146
Test name
Test status
Simulation time 139192915977 ps
CPU time 166.71 seconds
Started Jul 13 06:54:30 PM PDT 24
Finished Jul 13 06:57:18 PM PDT 24
Peak memory 236844 kb
Host smart-9ec2cd8f-1de0-4888-a1f0-00730a8d0635
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105317404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4105317404
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3216286334
Short name T355
Test name
Test status
Simulation time 4340837450 ps
CPU time 11.7 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:54:41 PM PDT 24
Peak memory 211484 kb
Host smart-409f9082-f3da-453a-9fa4-09e69d906c42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216286334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3216286334
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2373028800
Short name T49
Test name
Test status
Simulation time 7872694692 ps
CPU time 23.99 seconds
Started Jul 13 06:54:32 PM PDT 24
Finished Jul 13 06:54:56 PM PDT 24
Peak memory 213104 kb
Host smart-f5c62193-a40b-4629-b622-bb03e3742c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373028800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2373028800
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3198637121
Short name T212
Test name
Test status
Simulation time 16914746483 ps
CPU time 44.96 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:55:14 PM PDT 24
Peak memory 215600 kb
Host smart-37c56da0-cb8e-42c7-a511-1c538b517d11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198637121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3198637121
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3192489873
Short name T319
Test name
Test status
Simulation time 85564158 ps
CPU time 4.27 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:54:35 PM PDT 24
Peak memory 211328 kb
Host smart-c108e7c6-413b-4803-ac89-dce0189167f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192489873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3192489873
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3505279359
Short name T325
Test name
Test status
Simulation time 1701851049 ps
CPU time 107.95 seconds
Started Jul 13 06:54:30 PM PDT 24
Finished Jul 13 06:56:19 PM PDT 24
Peak memory 237652 kb
Host smart-a39812ea-4469-41ef-b911-98bf86b9499d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505279359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3505279359
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.106375840
Short name T215
Test name
Test status
Simulation time 1069016587 ps
CPU time 7.1 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:54:36 PM PDT 24
Peak memory 211388 kb
Host smart-21e4b5a2-20f1-4735-a81e-f826340cc3c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106375840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.106375840
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1568732260
Short name T313
Test name
Test status
Simulation time 4537919471 ps
CPU time 41.28 seconds
Started Jul 13 06:54:31 PM PDT 24
Finished Jul 13 06:55:13 PM PDT 24
Peak memory 213776 kb
Host smart-9af96a45-6ac0-4d1e-a315-b2d55eb7b899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568732260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1568732260
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3653435679
Short name T224
Test name
Test status
Simulation time 1444136984 ps
CPU time 18 seconds
Started Jul 13 06:54:27 PM PDT 24
Finished Jul 13 06:54:46 PM PDT 24
Peak memory 211276 kb
Host smart-6eac41c3-494c-4ba1-8eb3-66ee37ca5875
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653435679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3653435679
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3513123431
Short name T182
Test name
Test status
Simulation time 984558577 ps
CPU time 10.18 seconds
Started Jul 13 06:54:28 PM PDT 24
Finished Jul 13 06:54:38 PM PDT 24
Peak memory 211340 kb
Host smart-c0442fdd-c1f4-4924-b9ac-232147a17d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513123431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3513123431
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4248199438
Short name T177
Test name
Test status
Simulation time 15700292573 ps
CPU time 169.01 seconds
Started Jul 13 06:54:30 PM PDT 24
Finished Jul 13 06:57:20 PM PDT 24
Peak memory 212568 kb
Host smart-6471b06f-46eb-4605-b2cb-ec334ec1e393
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248199438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4248199438
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1626680494
Short name T134
Test name
Test status
Simulation time 1811102068 ps
CPU time 21.19 seconds
Started Jul 13 06:54:31 PM PDT 24
Finished Jul 13 06:54:53 PM PDT 24
Peak memory 211368 kb
Host smart-ea2a26aa-881d-44c8-a736-0af0500667b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626680494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1626680494
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3498511143
Short name T341
Test name
Test status
Simulation time 7090914516 ps
CPU time 16.64 seconds
Started Jul 13 06:54:27 PM PDT 24
Finished Jul 13 06:54:44 PM PDT 24
Peak memory 211460 kb
Host smart-9453824c-0fc1-4058-aee4-5d663083d504
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498511143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3498511143
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2078623135
Short name T74
Test name
Test status
Simulation time 1105432004 ps
CPU time 11.72 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:54:41 PM PDT 24
Peak memory 213760 kb
Host smart-b0dd805a-7b88-41a7-9887-e385c51f290f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078623135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2078623135
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3404517095
Short name T117
Test name
Test status
Simulation time 3869316268 ps
CPU time 52.51 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:55:22 PM PDT 24
Peak memory 216980 kb
Host smart-b5c2c927-a904-4485-ac51-2c51d8db20c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404517095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3404517095
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1090231526
Short name T221
Test name
Test status
Simulation time 5944473092 ps
CPU time 12.9 seconds
Started Jul 13 06:54:28 PM PDT 24
Finished Jul 13 06:54:41 PM PDT 24
Peak memory 211408 kb
Host smart-c7c8c25b-34c9-48e1-a65c-cf1a07eee9dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090231526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1090231526
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4254555944
Short name T102
Test name
Test status
Simulation time 12002086788 ps
CPU time 158.14 seconds
Started Jul 13 06:54:32 PM PDT 24
Finished Jul 13 06:57:11 PM PDT 24
Peak memory 236812 kb
Host smart-e0e8dc35-826f-41bd-93fd-0bdd382fe5fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254555944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4254555944
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3894297657
Short name T211
Test name
Test status
Simulation time 12563286029 ps
CPU time 29.62 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:54:59 PM PDT 24
Peak memory 212188 kb
Host smart-dcabda86-01ad-4247-856f-0048b68ecc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894297657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3894297657
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1583310673
Short name T197
Test name
Test status
Simulation time 3459264293 ps
CPU time 15.38 seconds
Started Jul 13 06:54:32 PM PDT 24
Finished Jul 13 06:54:48 PM PDT 24
Peak memory 211436 kb
Host smart-33f09d15-d6c3-4ae9-ab10-9c444a7f8159
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583310673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1583310673
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.137445749
Short name T205
Test name
Test status
Simulation time 6819044472 ps
CPU time 27.89 seconds
Started Jul 13 06:54:30 PM PDT 24
Finished Jul 13 06:54:59 PM PDT 24
Peak memory 214408 kb
Host smart-5ff6b316-715f-4dc7-89f0-dbcbc53f95c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137445749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.137445749
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3255456323
Short name T279
Test name
Test status
Simulation time 2468592121 ps
CPU time 26.25 seconds
Started Jul 13 06:54:28 PM PDT 24
Finished Jul 13 06:54:55 PM PDT 24
Peak memory 214200 kb
Host smart-c72d45f4-77f1-40e0-b916-e6596aeba0e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255456323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3255456323
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2758184006
Short name T358
Test name
Test status
Simulation time 3634614306 ps
CPU time 9.75 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:54:40 PM PDT 24
Peak memory 211416 kb
Host smart-eb4b636f-897f-46f3-bdc2-2bb7d59bca53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758184006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2758184006
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3753473611
Short name T20
Test name
Test status
Simulation time 23193922854 ps
CPU time 229.35 seconds
Started Jul 13 06:54:30 PM PDT 24
Finished Jul 13 06:58:21 PM PDT 24
Peak memory 236816 kb
Host smart-2d462702-8daf-4350-851c-6ab8edef6e53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753473611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3753473611
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3847722169
Short name T189
Test name
Test status
Simulation time 4071422076 ps
CPU time 33.72 seconds
Started Jul 13 06:54:31 PM PDT 24
Finished Jul 13 06:55:05 PM PDT 24
Peak memory 212008 kb
Host smart-b3e2e22c-cb59-4ff3-a165-4d1c82086a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847722169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3847722169
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1345580909
Short name T290
Test name
Test status
Simulation time 626052684 ps
CPU time 9.35 seconds
Started Jul 13 06:54:32 PM PDT 24
Finished Jul 13 06:54:42 PM PDT 24
Peak memory 211376 kb
Host smart-a2698fa6-6594-423d-993c-63152dc60974
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345580909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1345580909
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1354117229
Short name T335
Test name
Test status
Simulation time 4042648550 ps
CPU time 35.85 seconds
Started Jul 13 06:54:30 PM PDT 24
Finished Jul 13 06:55:07 PM PDT 24
Peak memory 213332 kb
Host smart-147dcb1b-0b6c-43c3-b13e-ede78ea26c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354117229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1354117229
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.740305427
Short name T17
Test name
Test status
Simulation time 402462870 ps
CPU time 5.75 seconds
Started Jul 13 06:54:31 PM PDT 24
Finished Jul 13 06:54:38 PM PDT 24
Peak memory 211352 kb
Host smart-696771df-dc11-40ca-aabd-da23ed412e46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740305427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.740305427
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4115638932
Short name T128
Test name
Test status
Simulation time 171537520 ps
CPU time 4.37 seconds
Started Jul 13 06:54:03 PM PDT 24
Finished Jul 13 06:54:07 PM PDT 24
Peak memory 211340 kb
Host smart-909c2f25-e728-4477-a026-2353b8365363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115638932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4115638932
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.716125371
Short name T283
Test name
Test status
Simulation time 1033079022 ps
CPU time 70.82 seconds
Started Jul 13 06:54:05 PM PDT 24
Finished Jul 13 06:55:17 PM PDT 24
Peak memory 237860 kb
Host smart-d565d520-37f9-4ae2-820c-a06377e48292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716125371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.716125371
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1060946135
Short name T8
Test name
Test status
Simulation time 695058591 ps
CPU time 9.43 seconds
Started Jul 13 06:54:05 PM PDT 24
Finished Jul 13 06:54:16 PM PDT 24
Peak memory 212404 kb
Host smart-4f64b1af-5609-41cb-80a5-7bdeabc93a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060946135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1060946135
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1770781165
Short name T188
Test name
Test status
Simulation time 3719149713 ps
CPU time 15.58 seconds
Started Jul 13 06:54:03 PM PDT 24
Finished Jul 13 06:54:19 PM PDT 24
Peak memory 211460 kb
Host smart-2dd2de53-4c5f-4cd1-8e1d-01301c7f2d5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770781165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1770781165
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.4226778277
Short name T118
Test name
Test status
Simulation time 4959834651 ps
CPU time 19.34 seconds
Started Jul 13 06:54:05 PM PDT 24
Finished Jul 13 06:54:26 PM PDT 24
Peak memory 214048 kb
Host smart-11acb0a8-e71d-490e-85a8-48adb799937d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226778277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4226778277
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4165242262
Short name T19
Test name
Test status
Simulation time 2553807654 ps
CPU time 9.67 seconds
Started Jul 13 06:54:05 PM PDT 24
Finished Jul 13 06:54:15 PM PDT 24
Peak memory 211456 kb
Host smart-2306d511-1ef8-41f6-a6d0-0966803d12a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165242262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4165242262
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3692205287
Short name T14
Test name
Test status
Simulation time 71652271783 ps
CPU time 9561.36 seconds
Started Jul 13 06:54:05 PM PDT 24
Finished Jul 13 09:33:28 PM PDT 24
Peak memory 230292 kb
Host smart-c245cbc9-dd2f-4cc2-bd48-7a80297e8e55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692205287 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3692205287
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1305041650
Short name T148
Test name
Test status
Simulation time 503687973 ps
CPU time 7.41 seconds
Started Jul 13 06:54:32 PM PDT 24
Finished Jul 13 06:54:40 PM PDT 24
Peak memory 211348 kb
Host smart-f4eb557e-89dd-493e-abd5-e4f9916f1720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305041650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1305041650
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.617677776
Short name T239
Test name
Test status
Simulation time 3787825821 ps
CPU time 138.84 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:56:49 PM PDT 24
Peak memory 238972 kb
Host smart-47206ddd-7681-43a1-b5c7-072088665e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617677776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.617677776
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3665824977
Short name T37
Test name
Test status
Simulation time 8708677056 ps
CPU time 33.57 seconds
Started Jul 13 06:58:02 PM PDT 24
Finished Jul 13 06:58:36 PM PDT 24
Peak memory 212488 kb
Host smart-47dadfc5-7892-4d40-a802-f1f82602a684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665824977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3665824977
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1948651124
Short name T142
Test name
Test status
Simulation time 445361374 ps
CPU time 6.82 seconds
Started Jul 13 06:54:30 PM PDT 24
Finished Jul 13 06:54:37 PM PDT 24
Peak memory 211376 kb
Host smart-4a9e59e6-42e4-4fe9-9823-4a9615e6b697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948651124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1948651124
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3478457552
Short name T51
Test name
Test status
Simulation time 9871190455 ps
CPU time 28.35 seconds
Started Jul 13 06:54:30 PM PDT 24
Finished Jul 13 06:54:59 PM PDT 24
Peak memory 213916 kb
Host smart-d6384afb-9a1e-41cc-84d3-c15249233f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478457552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3478457552
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2741721531
Short name T350
Test name
Test status
Simulation time 4399755278 ps
CPU time 17.52 seconds
Started Jul 13 06:54:29 PM PDT 24
Finished Jul 13 06:54:47 PM PDT 24
Peak memory 211440 kb
Host smart-21e9f45d-7e1a-45d6-bcf2-07e46689420c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741721531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2741721531
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3665599249
Short name T87
Test name
Test status
Simulation time 770848356 ps
CPU time 8.63 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:54:49 PM PDT 24
Peak memory 211328 kb
Host smart-3274ca4f-9a25-4a79-b5bd-6950f88944c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665599249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3665599249
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2330144159
Short name T36
Test name
Test status
Simulation time 9489378744 ps
CPU time 168.21 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:57:28 PM PDT 24
Peak memory 236880 kb
Host smart-c09d3eea-adf0-4486-bb43-62adbc964fc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330144159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2330144159
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.64940084
Short name T307
Test name
Test status
Simulation time 265156919 ps
CPU time 11.07 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:54:51 PM PDT 24
Peak memory 212264 kb
Host smart-317a6106-4209-49c1-8a5b-7084731ad48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64940084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.64940084
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3407301849
Short name T131
Test name
Test status
Simulation time 5991644467 ps
CPU time 13.17 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:54:54 PM PDT 24
Peak memory 211436 kb
Host smart-1efea05a-79fd-489f-a2c2-94e9c0c68d55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407301849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3407301849
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1729665888
Short name T351
Test name
Test status
Simulation time 1740289421 ps
CPU time 19.56 seconds
Started Jul 13 06:54:37 PM PDT 24
Finished Jul 13 06:54:58 PM PDT 24
Peak memory 213440 kb
Host smart-60ab33c7-67f5-4928-8d29-8bbcfdd373bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729665888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1729665888
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2974456104
Short name T165
Test name
Test status
Simulation time 605373111 ps
CPU time 17.5 seconds
Started Jul 13 06:54:38 PM PDT 24
Finished Jul 13 06:54:56 PM PDT 24
Peak memory 215044 kb
Host smart-ceb6295d-36ad-4f9b-a26c-50e91d0517af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974456104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2974456104
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2176385394
Short name T198
Test name
Test status
Simulation time 2168019197 ps
CPU time 10.65 seconds
Started Jul 13 06:54:38 PM PDT 24
Finished Jul 13 06:54:49 PM PDT 24
Peak memory 211404 kb
Host smart-124b551a-5002-47c9-81ae-7bee0f451cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176385394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2176385394
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.252129805
Short name T129
Test name
Test status
Simulation time 39125883744 ps
CPU time 280.09 seconds
Started Jul 13 06:54:38 PM PDT 24
Finished Jul 13 06:59:19 PM PDT 24
Peak memory 228600 kb
Host smart-48e743d1-32fb-49cb-a5d5-b1931d488de2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252129805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.252129805
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3862468769
Short name T10
Test name
Test status
Simulation time 173713143 ps
CPU time 9.4 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:54:49 PM PDT 24
Peak memory 211916 kb
Host smart-3b059cb4-44e0-4683-9637-9d9ebc5ec323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862468769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3862468769
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.843131610
Short name T260
Test name
Test status
Simulation time 1890654235 ps
CPU time 11.33 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:54:52 PM PDT 24
Peak memory 211412 kb
Host smart-2f82fe4e-a536-4291-9f01-cae29956146a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=843131610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.843131610
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2982624584
Short name T38
Test name
Test status
Simulation time 17163410911 ps
CPU time 33.93 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:55:14 PM PDT 24
Peak memory 213912 kb
Host smart-f7b46114-1cfd-49bc-bc00-ef7af3f86e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982624584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2982624584
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3709326897
Short name T143
Test name
Test status
Simulation time 139071607 ps
CPU time 6.92 seconds
Started Jul 13 06:54:38 PM PDT 24
Finished Jul 13 06:54:46 PM PDT 24
Peak memory 211260 kb
Host smart-5f320d8b-d3e0-4be5-8382-d5d516b6153f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709326897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3709326897
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3016352775
Short name T45
Test name
Test status
Simulation time 190771339632 ps
CPU time 756.8 seconds
Started Jul 13 06:54:38 PM PDT 24
Finished Jul 13 07:07:16 PM PDT 24
Peak memory 235828 kb
Host smart-0427d1a5-5936-4ef8-8975-a967e7facd3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016352775 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3016352775
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3063592215
Short name T213
Test name
Test status
Simulation time 5059908787 ps
CPU time 11.96 seconds
Started Jul 13 06:54:45 PM PDT 24
Finished Jul 13 06:54:58 PM PDT 24
Peak memory 211244 kb
Host smart-d56e8da4-d55e-44d5-835a-6436ce300fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063592215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3063592215
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3649116583
Short name T200
Test name
Test status
Simulation time 32357240014 ps
CPU time 270.69 seconds
Started Jul 13 06:54:37 PM PDT 24
Finished Jul 13 06:59:08 PM PDT 24
Peak memory 237764 kb
Host smart-33e985f2-0652-4a26-8200-2ab927e62cd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649116583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3649116583
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3797291693
Short name T151
Test name
Test status
Simulation time 665798030 ps
CPU time 9.69 seconds
Started Jul 13 06:54:40 PM PDT 24
Finished Jul 13 06:54:51 PM PDT 24
Peak memory 211944 kb
Host smart-5f34051a-ef90-402a-8b56-4b1cd825a701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797291693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3797291693
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2869504960
Short name T276
Test name
Test status
Simulation time 363676727 ps
CPU time 5.28 seconds
Started Jul 13 06:54:37 PM PDT 24
Finished Jul 13 06:54:43 PM PDT 24
Peak memory 211392 kb
Host smart-36d0b753-4996-4b05-aeef-0596d40be060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869504960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2869504960
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3452198535
Short name T227
Test name
Test status
Simulation time 2809917124 ps
CPU time 22.69 seconds
Started Jul 13 06:54:42 PM PDT 24
Finished Jul 13 06:55:05 PM PDT 24
Peak memory 213572 kb
Host smart-34464c12-5d38-403d-b8e7-d8600cd762ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452198535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3452198535
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1131601029
Short name T52
Test name
Test status
Simulation time 20433858780 ps
CPU time 67.91 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:55:49 PM PDT 24
Peak memory 217744 kb
Host smart-a333a6b7-23b5-4c38-99e4-9937d18814e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131601029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1131601029
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2957219091
Short name T47
Test name
Test status
Simulation time 26360810672 ps
CPU time 1056 seconds
Started Jul 13 06:54:38 PM PDT 24
Finished Jul 13 07:12:15 PM PDT 24
Peak memory 235848 kb
Host smart-7b61dfe6-7812-4174-b43c-1e1d067c165c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957219091 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2957219091
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1798171553
Short name T156
Test name
Test status
Simulation time 1080168068 ps
CPU time 10.46 seconds
Started Jul 13 06:54:43 PM PDT 24
Finished Jul 13 06:54:53 PM PDT 24
Peak memory 211344 kb
Host smart-2de75f26-e31a-4649-8e7d-2606b78ffd98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798171553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1798171553
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1240966945
Short name T314
Test name
Test status
Simulation time 10813013659 ps
CPU time 182.6 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:57:43 PM PDT 24
Peak memory 237900 kb
Host smart-34c34b2b-82c8-41ec-9fc2-91cf35409548
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240966945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1240966945
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2537722182
Short name T50
Test name
Test status
Simulation time 1381348421 ps
CPU time 10.16 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:54:50 PM PDT 24
Peak memory 211868 kb
Host smart-a4f4b857-8dc3-43f3-873b-f52b68d84970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537722182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2537722182
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.427993946
Short name T183
Test name
Test status
Simulation time 2115990479 ps
CPU time 16.83 seconds
Started Jul 13 06:54:44 PM PDT 24
Finished Jul 13 06:55:02 PM PDT 24
Peak memory 211400 kb
Host smart-c3a0007d-6553-4eec-9932-e4c1e2f74248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=427993946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.427993946
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3227903421
Short name T304
Test name
Test status
Simulation time 187985697 ps
CPU time 10.56 seconds
Started Jul 13 06:54:41 PM PDT 24
Finished Jul 13 06:54:52 PM PDT 24
Peak memory 213528 kb
Host smart-1d3a999f-8a3d-4dd4-8372-f36319e8e205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227903421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3227903421
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1951324533
Short name T236
Test name
Test status
Simulation time 1926800522 ps
CPU time 20.4 seconds
Started Jul 13 06:54:45 PM PDT 24
Finished Jul 13 06:55:06 PM PDT 24
Peak memory 211236 kb
Host smart-8754e6ea-696b-4bb0-baab-73c237692d9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951324533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1951324533
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3107087020
Short name T222
Test name
Test status
Simulation time 1307861381 ps
CPU time 11.47 seconds
Started Jul 13 06:54:41 PM PDT 24
Finished Jul 13 06:54:53 PM PDT 24
Peak memory 211364 kb
Host smart-48abf000-5352-427e-b6ed-3c11761b554c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107087020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3107087020
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2191236576
Short name T275
Test name
Test status
Simulation time 30359143763 ps
CPU time 175.01 seconds
Started Jul 13 06:54:40 PM PDT 24
Finished Jul 13 06:57:36 PM PDT 24
Peak memory 228668 kb
Host smart-2e3b5776-edda-4bcc-be15-64701690999a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191236576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2191236576
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2183810594
Short name T320
Test name
Test status
Simulation time 2943115776 ps
CPU time 26.64 seconds
Started Jul 13 06:54:38 PM PDT 24
Finished Jul 13 06:55:06 PM PDT 24
Peak memory 212040 kb
Host smart-ae2b0ad4-91f0-4127-a455-2042eda5412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183810594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2183810594
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.809829478
Short name T343
Test name
Test status
Simulation time 6723674409 ps
CPU time 14.21 seconds
Started Jul 13 06:54:37 PM PDT 24
Finished Jul 13 06:54:52 PM PDT 24
Peak memory 211416 kb
Host smart-f7ef0d88-80c1-48a5-b52c-7a8ce175f370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809829478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.809829478
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1855945596
Short name T340
Test name
Test status
Simulation time 831398552 ps
CPU time 10.25 seconds
Started Jul 13 06:54:45 PM PDT 24
Finished Jul 13 06:54:55 PM PDT 24
Peak memory 213692 kb
Host smart-66a4c622-cc96-4a57-aaba-eaf273ab48f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855945596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1855945596
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2399083049
Short name T261
Test name
Test status
Simulation time 10655556221 ps
CPU time 26.83 seconds
Started Jul 13 06:54:38 PM PDT 24
Finished Jul 13 06:55:06 PM PDT 24
Peak memory 215192 kb
Host smart-72e6f72e-da5f-4873-84d8-ee77de9eafeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399083049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2399083049
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2781118426
Short name T172
Test name
Test status
Simulation time 1620903219 ps
CPU time 12.84 seconds
Started Jul 13 06:54:45 PM PDT 24
Finished Jul 13 06:54:59 PM PDT 24
Peak memory 211364 kb
Host smart-6941aab9-8acf-4055-88d1-9b2fda909245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781118426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2781118426
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1928946914
Short name T264
Test name
Test status
Simulation time 24935949995 ps
CPU time 164.5 seconds
Started Jul 13 06:54:41 PM PDT 24
Finished Jul 13 06:57:26 PM PDT 24
Peak memory 213616 kb
Host smart-09da694e-076a-476c-a76e-b1e821b7707f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928946914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1928946914
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1437558444
Short name T147
Test name
Test status
Simulation time 1840616387 ps
CPU time 19.17 seconds
Started Jul 13 06:54:37 PM PDT 24
Finished Jul 13 06:54:57 PM PDT 24
Peak memory 211928 kb
Host smart-9a57dcd7-183c-4472-97b0-e507f3c77160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437558444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1437558444
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3792431227
Short name T126
Test name
Test status
Simulation time 612608691 ps
CPU time 7.74 seconds
Started Jul 13 06:54:41 PM PDT 24
Finished Jul 13 06:54:49 PM PDT 24
Peak memory 211596 kb
Host smart-13f7073b-bb7e-42af-bbbc-bc0c2884941c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792431227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3792431227
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.932886075
Short name T9
Test name
Test status
Simulation time 2068336511 ps
CPU time 21.97 seconds
Started Jul 13 06:54:38 PM PDT 24
Finished Jul 13 06:55:01 PM PDT 24
Peak memory 212080 kb
Host smart-748df2e4-99ec-47f7-ae8c-ecbdcff3e1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932886075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.932886075
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1400656902
Short name T31
Test name
Test status
Simulation time 9073849311 ps
CPU time 46.07 seconds
Started Jul 13 06:54:38 PM PDT 24
Finished Jul 13 06:55:25 PM PDT 24
Peak memory 215560 kb
Host smart-87e1d1b7-b4da-4db8-8731-afddf38e6cb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400656902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1400656902
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2371321523
Short name T5
Test name
Test status
Simulation time 100003323 ps
CPU time 4.19 seconds
Started Jul 13 06:54:44 PM PDT 24
Finished Jul 13 06:54:49 PM PDT 24
Peak memory 211348 kb
Host smart-9c0db547-220a-42b6-8f6f-d7e17bd7d6f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371321523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2371321523
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3212072019
Short name T252
Test name
Test status
Simulation time 51131906762 ps
CPU time 295.25 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:59:35 PM PDT 24
Peak memory 213636 kb
Host smart-f79a15ff-94b2-4e35-9f83-233af8ce9970
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212072019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3212072019
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.67399782
Short name T272
Test name
Test status
Simulation time 4106681962 ps
CPU time 34.83 seconds
Started Jul 13 06:54:43 PM PDT 24
Finished Jul 13 06:55:18 PM PDT 24
Peak memory 211916 kb
Host smart-c82c8323-79ef-4b27-9271-b63e60d98e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67399782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.67399782
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4060949975
Short name T273
Test name
Test status
Simulation time 6293106506 ps
CPU time 14.25 seconds
Started Jul 13 06:54:40 PM PDT 24
Finished Jul 13 06:54:55 PM PDT 24
Peak memory 211432 kb
Host smart-b4ab4fb0-fef9-46d1-a5c2-d979b25ea1bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4060949975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4060949975
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.186426094
Short name T324
Test name
Test status
Simulation time 6614602061 ps
CPU time 35.03 seconds
Started Jul 13 06:54:39 PM PDT 24
Finished Jul 13 06:55:15 PM PDT 24
Peak memory 214584 kb
Host smart-a41c64e5-2cd8-4941-bebe-1f9119fff8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186426094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.186426094
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1480530454
Short name T162
Test name
Test status
Simulation time 25588383743 ps
CPU time 65.85 seconds
Started Jul 13 06:54:40 PM PDT 24
Finished Jul 13 06:55:47 PM PDT 24
Peak memory 219420 kb
Host smart-10c68c5f-1831-4dcc-b39f-c651a43d2e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480530454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1480530454
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3547762766
Short name T171
Test name
Test status
Simulation time 2951927242 ps
CPU time 6.05 seconds
Started Jul 13 06:54:48 PM PDT 24
Finished Jul 13 06:54:55 PM PDT 24
Peak memory 211424 kb
Host smart-4e4c3324-be3a-4619-acb8-f512cf14afb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547762766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3547762766
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3608889083
Short name T223
Test name
Test status
Simulation time 9671312181 ps
CPU time 108.63 seconds
Started Jul 13 06:54:49 PM PDT 24
Finished Jul 13 06:56:39 PM PDT 24
Peak memory 228588 kb
Host smart-e83ad4aa-2aec-4a3a-a91b-4761f00c03e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608889083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3608889083
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2079631712
Short name T40
Test name
Test status
Simulation time 4427646354 ps
CPU time 17.17 seconds
Started Jul 13 06:54:47 PM PDT 24
Finished Jul 13 06:55:06 PM PDT 24
Peak memory 212228 kb
Host smart-de8e8526-9072-4570-b18a-3870f8468022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079631712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2079631712
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1396629521
Short name T3
Test name
Test status
Simulation time 721513821 ps
CPU time 9.66 seconds
Started Jul 13 06:54:45 PM PDT 24
Finished Jul 13 06:54:55 PM PDT 24
Peak memory 211380 kb
Host smart-34d2674c-712b-4531-9f93-16c4471d9774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396629521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1396629521
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1143378284
Short name T193
Test name
Test status
Simulation time 14145019655 ps
CPU time 31.2 seconds
Started Jul 13 06:54:40 PM PDT 24
Finished Jul 13 06:55:12 PM PDT 24
Peak memory 214372 kb
Host smart-1bc6b6d1-b0a0-4e30-9499-bf0fdd629d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143378284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1143378284
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3320830525
Short name T185
Test name
Test status
Simulation time 228318229 ps
CPU time 8.88 seconds
Started Jul 13 06:54:37 PM PDT 24
Finished Jul 13 06:54:46 PM PDT 24
Peak memory 211488 kb
Host smart-0fb65f28-81f0-4c62-a013-b3ff7b74ba9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320830525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3320830525
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2157459126
Short name T26
Test name
Test status
Simulation time 1220279956 ps
CPU time 11.74 seconds
Started Jul 13 06:54:49 PM PDT 24
Finished Jul 13 06:55:02 PM PDT 24
Peak memory 211340 kb
Host smart-f1a95b9b-70bb-4182-9ca2-18081b48cac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157459126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2157459126
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2612892013
Short name T328
Test name
Test status
Simulation time 1723192913 ps
CPU time 106 seconds
Started Jul 13 06:54:47 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 237432 kb
Host smart-102dae01-e4f6-4c63-8cf2-ab39d4a0c5df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612892013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2612892013
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.896196650
Short name T296
Test name
Test status
Simulation time 7436511239 ps
CPU time 20.68 seconds
Started Jul 13 06:54:45 PM PDT 24
Finished Jul 13 06:55:07 PM PDT 24
Peak memory 212528 kb
Host smart-a864edae-54c9-4be5-b973-8b5ef2e8ce0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896196650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.896196650
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3584458426
Short name T219
Test name
Test status
Simulation time 1891782277 ps
CPU time 15.63 seconds
Started Jul 13 06:54:50 PM PDT 24
Finished Jul 13 06:55:06 PM PDT 24
Peak memory 211596 kb
Host smart-4ddf9c66-84f5-4341-9c89-b2cec35ceae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584458426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3584458426
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2247888699
Short name T334
Test name
Test status
Simulation time 3155152717 ps
CPU time 37.73 seconds
Started Jul 13 06:54:48 PM PDT 24
Finished Jul 13 06:55:27 PM PDT 24
Peak memory 213160 kb
Host smart-1aa97f71-60bd-4e4a-97d9-f220fdf5f8c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247888699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2247888699
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3901775787
Short name T25
Test name
Test status
Simulation time 85506414 ps
CPU time 4.28 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:54:18 PM PDT 24
Peak memory 211344 kb
Host smart-3ee92744-c675-49d6-a2cd-39cbdd7f2313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901775787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3901775787
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4221040881
Short name T163
Test name
Test status
Simulation time 59752782747 ps
CPU time 202.44 seconds
Started Jul 13 06:54:15 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 212260 kb
Host smart-386a8338-81aa-4318-a01a-33eba536efda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221040881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4221040881
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3203625253
Short name T271
Test name
Test status
Simulation time 8795712599 ps
CPU time 22.97 seconds
Started Jul 13 06:54:14 PM PDT 24
Finished Jul 13 06:54:38 PM PDT 24
Peak memory 212352 kb
Host smart-31771d63-f6ef-4ef2-9a7d-628fc4a25e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203625253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3203625253
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3224146850
Short name T300
Test name
Test status
Simulation time 1731162401 ps
CPU time 15.36 seconds
Started Jul 13 06:54:14 PM PDT 24
Finished Jul 13 06:54:30 PM PDT 24
Peak memory 211368 kb
Host smart-2fe765ff-e0cb-44e6-ae38-49983ae4ee71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224146850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3224146850
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2260335928
Short name T29
Test name
Test status
Simulation time 306924778 ps
CPU time 52.77 seconds
Started Jul 13 06:54:12 PM PDT 24
Finished Jul 13 06:55:05 PM PDT 24
Peak memory 236828 kb
Host smart-153648b2-86c1-40e8-b319-16c164a76058
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260335928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2260335928
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1284612926
Short name T169
Test name
Test status
Simulation time 1358247167 ps
CPU time 20.73 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:54:34 PM PDT 24
Peak memory 213828 kb
Host smart-c5bd1b81-27d3-45c3-9d66-39f4e035f246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284612926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1284612926
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1021355695
Short name T216
Test name
Test status
Simulation time 10503573588 ps
CPU time 40.14 seconds
Started Jul 13 06:54:11 PM PDT 24
Finished Jul 13 06:54:52 PM PDT 24
Peak memory 215644 kb
Host smart-53dcba70-197f-47cf-aeea-06fc3727379d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021355695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1021355695
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1542193771
Short name T157
Test name
Test status
Simulation time 58920601729 ps
CPU time 233.8 seconds
Started Jul 13 06:54:48 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 237856 kb
Host smart-ff4cc46b-5bb6-4f42-9555-daf4deedf1d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542193771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1542193771
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1684656741
Short name T133
Test name
Test status
Simulation time 22524110230 ps
CPU time 33.92 seconds
Started Jul 13 06:54:49 PM PDT 24
Finished Jul 13 06:55:24 PM PDT 24
Peak memory 212484 kb
Host smart-edc46006-768c-48ad-b327-06160eee248f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684656741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1684656741
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1113203953
Short name T187
Test name
Test status
Simulation time 1358137558 ps
CPU time 13.01 seconds
Started Jul 13 06:54:47 PM PDT 24
Finished Jul 13 06:55:01 PM PDT 24
Peak memory 211376 kb
Host smart-af4ba83c-fc94-47fd-a59d-3cd10b20e907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113203953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1113203953
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.829676599
Short name T245
Test name
Test status
Simulation time 52929831449 ps
CPU time 36 seconds
Started Jul 13 06:54:47 PM PDT 24
Finished Jul 13 06:55:23 PM PDT 24
Peak memory 214156 kb
Host smart-02c1b126-005e-44bc-b837-424ccc10457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829676599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.829676599
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4056055248
Short name T292
Test name
Test status
Simulation time 30135618000 ps
CPU time 28.41 seconds
Started Jul 13 06:54:50 PM PDT 24
Finished Jul 13 06:55:19 PM PDT 24
Peak memory 214424 kb
Host smart-0df79306-40c5-42eb-b009-83a5fc289962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056055248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4056055248
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3070692345
Short name T203
Test name
Test status
Simulation time 88845284 ps
CPU time 4.36 seconds
Started Jul 13 06:54:49 PM PDT 24
Finished Jul 13 06:54:54 PM PDT 24
Peak memory 211340 kb
Host smart-b9004c32-fb46-4f6c-a8a1-15f53c83ce67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070692345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3070692345
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4070215708
Short name T207
Test name
Test status
Simulation time 55786380333 ps
CPU time 350.93 seconds
Started Jul 13 06:54:47 PM PDT 24
Finished Jul 13 07:00:38 PM PDT 24
Peak memory 228592 kb
Host smart-35010350-ee0e-4568-880a-59c6e1da5f20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070215708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4070215708
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3889039434
Short name T132
Test name
Test status
Simulation time 252375756 ps
CPU time 11.46 seconds
Started Jul 13 06:54:46 PM PDT 24
Finished Jul 13 06:54:58 PM PDT 24
Peak memory 212564 kb
Host smart-057ac885-f1e3-495d-b1d8-cf6f7757d3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889039434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3889039434
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1002234750
Short name T286
Test name
Test status
Simulation time 6246313062 ps
CPU time 14.59 seconds
Started Jul 13 06:54:49 PM PDT 24
Finished Jul 13 06:55:05 PM PDT 24
Peak memory 211420 kb
Host smart-d341fdaf-a988-49b2-abee-2a1ae9fa23dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002234750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1002234750
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3092677874
Short name T317
Test name
Test status
Simulation time 3933648799 ps
CPU time 40.13 seconds
Started Jul 13 06:54:47 PM PDT 24
Finished Jul 13 06:55:28 PM PDT 24
Peak memory 213612 kb
Host smart-feb3dfde-17d7-481a-8d61-87ecc938a750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092677874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3092677874
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1627030887
Short name T333
Test name
Test status
Simulation time 12684357577 ps
CPU time 50.74 seconds
Started Jul 13 06:54:47 PM PDT 24
Finished Jul 13 06:55:38 PM PDT 24
Peak memory 219384 kb
Host smart-c96a884e-637e-4f62-bec2-ed7293268659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627030887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1627030887
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2410318341
Short name T332
Test name
Test status
Simulation time 1525142303 ps
CPU time 13.01 seconds
Started Jul 13 06:54:56 PM PDT 24
Finished Jul 13 06:55:09 PM PDT 24
Peak memory 211376 kb
Host smart-a2775cff-170c-48b4-b363-6fd3be51255e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410318341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2410318341
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2140112966
Short name T357
Test name
Test status
Simulation time 41137175636 ps
CPU time 348.66 seconds
Started Jul 13 06:54:55 PM PDT 24
Finished Jul 13 07:00:45 PM PDT 24
Peak memory 235052 kb
Host smart-1a68bd50-b3c7-46d1-85b1-646141f82b1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140112966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2140112966
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.457715494
Short name T311
Test name
Test status
Simulation time 7660460598 ps
CPU time 33.33 seconds
Started Jul 13 06:54:59 PM PDT 24
Finished Jul 13 06:55:32 PM PDT 24
Peak memory 212216 kb
Host smart-0bd5ca1c-1cc8-4f24-b346-348f27056336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457715494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.457715494
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1298970934
Short name T309
Test name
Test status
Simulation time 382325249 ps
CPU time 5.53 seconds
Started Jul 13 06:54:56 PM PDT 24
Finished Jul 13 06:55:02 PM PDT 24
Peak memory 211376 kb
Host smart-a20ccf3e-e738-4a7d-be17-2d5c7bfaaf66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1298970934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1298970934
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1248554508
Short name T257
Test name
Test status
Simulation time 9850455775 ps
CPU time 24.93 seconds
Started Jul 13 06:54:48 PM PDT 24
Finished Jul 13 06:55:15 PM PDT 24
Peak memory 214252 kb
Host smart-1a359172-6e9a-4a30-a90b-96ecf11b9d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248554508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1248554508
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3481496095
Short name T138
Test name
Test status
Simulation time 1342683521 ps
CPU time 43.51 seconds
Started Jul 13 06:54:47 PM PDT 24
Finished Jul 13 06:55:32 PM PDT 24
Peak memory 215116 kb
Host smart-74b754d5-5391-433f-af87-3acdd0041dea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481496095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3481496095
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1911023556
Short name T243
Test name
Test status
Simulation time 1229915911 ps
CPU time 11.51 seconds
Started Jul 13 06:54:57 PM PDT 24
Finished Jul 13 06:55:09 PM PDT 24
Peak memory 211328 kb
Host smart-0c1a6518-efff-4ead-b174-e2f56e8d106b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911023556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1911023556
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3318317390
Short name T293
Test name
Test status
Simulation time 382785026978 ps
CPU time 249.06 seconds
Started Jul 13 06:54:57 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 233896 kb
Host smart-77ed0a82-2902-4e77-b85d-9afa314d7eb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318317390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3318317390
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3894743038
Short name T33
Test name
Test status
Simulation time 176821156 ps
CPU time 9.45 seconds
Started Jul 13 06:54:57 PM PDT 24
Finished Jul 13 06:55:07 PM PDT 24
Peak memory 211892 kb
Host smart-2932dca5-855a-43ed-823d-98712c45a9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894743038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3894743038
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1483045989
Short name T88
Test name
Test status
Simulation time 427585789 ps
CPU time 5.84 seconds
Started Jul 13 06:54:54 PM PDT 24
Finished Jul 13 06:55:01 PM PDT 24
Peak memory 211376 kb
Host smart-ef76b657-1305-470c-a849-06f6cd0ddf7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483045989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1483045989
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3428978125
Short name T202
Test name
Test status
Simulation time 959794946 ps
CPU time 15.97 seconds
Started Jul 13 06:54:54 PM PDT 24
Finished Jul 13 06:55:10 PM PDT 24
Peak memory 211952 kb
Host smart-c9c1a60c-3323-486a-ac0b-75f3da08126f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428978125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3428978125
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2164413874
Short name T244
Test name
Test status
Simulation time 1780153422 ps
CPU time 16.09 seconds
Started Jul 13 06:54:53 PM PDT 24
Finished Jul 13 06:55:10 PM PDT 24
Peak memory 211244 kb
Host smart-aedcdbe6-0a4b-41a6-83a6-977fece6e0c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164413874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2164413874
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1067361069
Short name T61
Test name
Test status
Simulation time 4105574234 ps
CPU time 13.9 seconds
Started Jul 13 06:54:58 PM PDT 24
Finished Jul 13 06:55:12 PM PDT 24
Peak memory 211388 kb
Host smart-a4e74de6-7322-450b-ac86-ba35071b2771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067361069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1067361069
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1137241871
Short name T24
Test name
Test status
Simulation time 2075747309 ps
CPU time 124.17 seconds
Started Jul 13 06:54:57 PM PDT 24
Finished Jul 13 06:57:02 PM PDT 24
Peak memory 212696 kb
Host smart-8d4a0939-33d1-4213-a400-e9eba45b9612
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137241871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1137241871
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.909346236
Short name T339
Test name
Test status
Simulation time 1314730056 ps
CPU time 14.25 seconds
Started Jul 13 06:54:55 PM PDT 24
Finished Jul 13 06:55:10 PM PDT 24
Peak memory 212040 kb
Host smart-2935be8b-22d9-4cdd-89d7-e6d2ccd9bf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909346236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.909346236
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3267922813
Short name T233
Test name
Test status
Simulation time 694783306 ps
CPU time 7.36 seconds
Started Jul 13 06:54:54 PM PDT 24
Finished Jul 13 06:55:03 PM PDT 24
Peak memory 211388 kb
Host smart-ce8670f7-b2ff-4be7-a3e1-33791d7ec9a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267922813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3267922813
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3124538132
Short name T73
Test name
Test status
Simulation time 4283062619 ps
CPU time 37.44 seconds
Started Jul 13 06:54:54 PM PDT 24
Finished Jul 13 06:55:32 PM PDT 24
Peak memory 213472 kb
Host smart-cd5fd405-37e2-4b88-9316-19da9cea77f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124538132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3124538132
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3901005925
Short name T2
Test name
Test status
Simulation time 1058919029 ps
CPU time 18.42 seconds
Started Jul 13 06:54:55 PM PDT 24
Finished Jul 13 06:55:14 PM PDT 24
Peak memory 213488 kb
Host smart-e0d94f4d-063b-4b55-9c62-409e1ac8dcac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901005925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3901005925
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2149840826
Short name T155
Test name
Test status
Simulation time 2046111474 ps
CPU time 15.61 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 06:55:22 PM PDT 24
Peak memory 211352 kb
Host smart-93c0b48c-edae-4aee-8d12-b01859697e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149840826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2149840826
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2201440926
Short name T160
Test name
Test status
Simulation time 26359320937 ps
CPU time 276.19 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 06:59:43 PM PDT 24
Peak memory 233884 kb
Host smart-fd9cc237-0fef-4e46-b258-b20fbc8fd49b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201440926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2201440926
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2766239329
Short name T329
Test name
Test status
Simulation time 14240389356 ps
CPU time 28.62 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 06:55:34 PM PDT 24
Peak memory 212248 kb
Host smart-5a441871-755d-4d25-86d8-a025052ece5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766239329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2766239329
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2364603461
Short name T220
Test name
Test status
Simulation time 5426346914 ps
CPU time 8.92 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 06:55:15 PM PDT 24
Peak memory 211436 kb
Host smart-40b0a9e2-5456-44a5-b0c2-4fd6713bd713
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364603461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2364603461
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2196772892
Short name T218
Test name
Test status
Simulation time 3827893497 ps
CPU time 21.94 seconds
Started Jul 13 06:54:54 PM PDT 24
Finished Jul 13 06:55:16 PM PDT 24
Peak memory 213952 kb
Host smart-cd5d24fc-0fb1-42ef-b73e-d4ffe594dd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196772892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2196772892
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3761025775
Short name T7
Test name
Test status
Simulation time 336568710 ps
CPU time 7.52 seconds
Started Jul 13 06:55:06 PM PDT 24
Finished Jul 13 06:55:15 PM PDT 24
Peak memory 211592 kb
Host smart-dbddfdf6-680f-40a7-9c5a-93ac61088f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761025775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3761025775
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1275362168
Short name T43
Test name
Test status
Simulation time 28099536580 ps
CPU time 4592.58 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 08:11:40 PM PDT 24
Peak memory 229480 kb
Host smart-70693d9a-f09c-416f-82c6-c9a2b683f2ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275362168 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1275362168
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3447979619
Short name T195
Test name
Test status
Simulation time 1523477591 ps
CPU time 13.35 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 06:55:19 PM PDT 24
Peak memory 211364 kb
Host smart-bd9374ff-6f0e-496c-8cef-f4225a484e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447979619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3447979619
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4103059334
Short name T42
Test name
Test status
Simulation time 9692762454 ps
CPU time 97.09 seconds
Started Jul 13 06:55:04 PM PDT 24
Finished Jul 13 06:56:41 PM PDT 24
Peak memory 237876 kb
Host smart-a0a49d21-9462-4df0-9b37-499c100e8fb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103059334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4103059334
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3960451085
Short name T139
Test name
Test status
Simulation time 692381801 ps
CPU time 9.64 seconds
Started Jul 13 06:55:03 PM PDT 24
Finished Jul 13 06:55:13 PM PDT 24
Peak memory 211848 kb
Host smart-700b1dc2-b395-4c0e-8337-5e12e40bfcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960451085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3960451085
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3468515018
Short name T342
Test name
Test status
Simulation time 1714814518 ps
CPU time 14.95 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 06:55:21 PM PDT 24
Peak memory 211388 kb
Host smart-e0e7f5b7-a3d4-48a0-af23-db709eb87aed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3468515018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3468515018
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2688129041
Short name T214
Test name
Test status
Simulation time 9600760949 ps
CPU time 23.74 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 06:55:30 PM PDT 24
Peak memory 213964 kb
Host smart-f9b47fc3-c21d-4dc5-aaf3-2bf75ede7b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688129041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2688129041
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3744468128
Short name T323
Test name
Test status
Simulation time 6047273084 ps
CPU time 52.88 seconds
Started Jul 13 06:55:06 PM PDT 24
Finished Jul 13 06:56:00 PM PDT 24
Peak memory 213584 kb
Host smart-fe0cb710-1dec-4f04-a098-2e3a0adfb94f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744468128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3744468128
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2498168314
Short name T136
Test name
Test status
Simulation time 2123547821 ps
CPU time 10.84 seconds
Started Jul 13 06:55:03 PM PDT 24
Finished Jul 13 06:55:14 PM PDT 24
Peak memory 211312 kb
Host smart-a9fa6758-fbe4-45fe-be91-d1f609de1396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498168314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2498168314
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2320177376
Short name T285
Test name
Test status
Simulation time 165887681900 ps
CPU time 256.54 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 06:59:23 PM PDT 24
Peak memory 213792 kb
Host smart-d1f438c8-2ba6-4afd-9bb6-5daa8262d6a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320177376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2320177376
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3648521793
Short name T158
Test name
Test status
Simulation time 533294984 ps
CPU time 12.54 seconds
Started Jul 13 06:55:06 PM PDT 24
Finished Jul 13 06:55:20 PM PDT 24
Peak memory 212188 kb
Host smart-48b5c775-1717-40bf-8691-70141e26bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648521793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3648521793
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1571029660
Short name T123
Test name
Test status
Simulation time 1188865995 ps
CPU time 14.52 seconds
Started Jul 13 06:55:06 PM PDT 24
Finished Jul 13 06:55:22 PM PDT 24
Peak memory 213224 kb
Host smart-feb223c4-2be2-4f08-a95d-3665658c2e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571029660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1571029660
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3120593328
Short name T153
Test name
Test status
Simulation time 12349846386 ps
CPU time 50.91 seconds
Started Jul 13 06:55:06 PM PDT 24
Finished Jul 13 06:55:58 PM PDT 24
Peak memory 213884 kb
Host smart-b2c67ab5-288a-49c7-ba11-7412a55796da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120593328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3120593328
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.779273936
Short name T315
Test name
Test status
Simulation time 1711112494 ps
CPU time 14.51 seconds
Started Jul 13 06:55:15 PM PDT 24
Finished Jul 13 06:55:30 PM PDT 24
Peak memory 211328 kb
Host smart-57d419c0-5c2c-4031-8dbe-d5b051e0b90f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779273936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.779273936
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.246395432
Short name T267
Test name
Test status
Simulation time 35310409584 ps
CPU time 184.01 seconds
Started Jul 13 06:55:13 PM PDT 24
Finished Jul 13 06:58:17 PM PDT 24
Peak memory 237816 kb
Host smart-532a4645-ad9f-48dd-918b-94d0771353aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246395432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.246395432
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2354635373
Short name T90
Test name
Test status
Simulation time 13120191634 ps
CPU time 31.98 seconds
Started Jul 13 06:55:14 PM PDT 24
Finished Jul 13 06:55:47 PM PDT 24
Peak memory 212300 kb
Host smart-bbf0093b-67a0-45a5-b408-8928da0c8d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354635373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2354635373
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2650314981
Short name T150
Test name
Test status
Simulation time 179678686 ps
CPU time 5.95 seconds
Started Jul 13 06:55:06 PM PDT 24
Finished Jul 13 06:55:13 PM PDT 24
Peak memory 211436 kb
Host smart-618b05d8-1772-445c-95c7-9f2fef294d75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2650314981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2650314981
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2933845989
Short name T85
Test name
Test status
Simulation time 8236061160 ps
CPU time 24.07 seconds
Started Jul 13 06:55:05 PM PDT 24
Finished Jul 13 06:55:30 PM PDT 24
Peak memory 214024 kb
Host smart-38610721-454e-44dd-be53-7ee0b7d4e3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933845989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2933845989
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.770643783
Short name T294
Test name
Test status
Simulation time 11581247500 ps
CPU time 71.28 seconds
Started Jul 13 06:55:06 PM PDT 24
Finished Jul 13 06:56:19 PM PDT 24
Peak memory 219412 kb
Host smart-b7c91341-56d3-4a75-a4dc-828c5c783d34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770643783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.770643783
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.12060964
Short name T348
Test name
Test status
Simulation time 1140876371 ps
CPU time 5.59 seconds
Started Jul 13 06:55:12 PM PDT 24
Finished Jul 13 06:55:18 PM PDT 24
Peak memory 211352 kb
Host smart-6fe03a20-eebf-4d7f-9568-ad79fbd7b89b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12060964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.12060964
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1772845505
Short name T230
Test name
Test status
Simulation time 329297835864 ps
CPU time 230.52 seconds
Started Jul 13 06:55:12 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 228588 kb
Host smart-42954b30-1246-4032-908d-621876c7de05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772845505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1772845505
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3719828839
Short name T255
Test name
Test status
Simulation time 3067260086 ps
CPU time 25.92 seconds
Started Jul 13 06:55:14 PM PDT 24
Finished Jul 13 06:55:41 PM PDT 24
Peak memory 212164 kb
Host smart-aba27f78-7d52-411c-834d-ebc4b0e611b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719828839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3719828839
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.93407797
Short name T181
Test name
Test status
Simulation time 1699094375 ps
CPU time 14.93 seconds
Started Jul 13 06:55:14 PM PDT 24
Finished Jul 13 06:55:30 PM PDT 24
Peak memory 211400 kb
Host smart-01449fe6-d68d-4d86-b44d-71e7bc44eb7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93407797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.93407797
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2924332746
Short name T116
Test name
Test status
Simulation time 2002179129 ps
CPU time 25.96 seconds
Started Jul 13 06:55:13 PM PDT 24
Finished Jul 13 06:55:40 PM PDT 24
Peak memory 213320 kb
Host smart-36bf8b1a-5c0b-43fa-ad3a-e24e03e8b976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924332746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2924332746
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1102766016
Short name T312
Test name
Test status
Simulation time 1763797101 ps
CPU time 16.8 seconds
Started Jul 13 06:55:13 PM PDT 24
Finished Jul 13 06:55:30 PM PDT 24
Peak memory 216620 kb
Host smart-f3564f74-0fd4-4a0c-8f0b-ac41f555a9ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102766016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1102766016
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1848759055
Short name T289
Test name
Test status
Simulation time 291533338 ps
CPU time 6.42 seconds
Started Jul 13 06:54:14 PM PDT 24
Finished Jul 13 06:54:21 PM PDT 24
Peak memory 211272 kb
Host smart-b7d47309-6acf-445b-bcdc-4a68a74785a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848759055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1848759055
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1146865461
Short name T34
Test name
Test status
Simulation time 11295725843 ps
CPU time 211.06 seconds
Started Jul 13 06:54:09 PM PDT 24
Finished Jul 13 06:57:41 PM PDT 24
Peak memory 236988 kb
Host smart-ef4ab1ba-fc0a-4c8c-ad5b-8171e57f5a53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146865461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1146865461
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2646676529
Short name T125
Test name
Test status
Simulation time 6245087253 ps
CPU time 18.89 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:54:33 PM PDT 24
Peak memory 212580 kb
Host smart-f36c5710-ad75-42df-98d6-ac96206a90d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646676529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2646676529
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3652021429
Short name T308
Test name
Test status
Simulation time 622917547 ps
CPU time 8.83 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:54:23 PM PDT 24
Peak memory 211396 kb
Host smart-bb5e4463-1797-405c-8f88-66eacca11f49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652021429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3652021429
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3465116503
Short name T30
Test name
Test status
Simulation time 9782118517 ps
CPU time 106.18 seconds
Started Jul 13 06:54:12 PM PDT 24
Finished Jul 13 06:55:59 PM PDT 24
Peak memory 236912 kb
Host smart-3843e864-2075-4908-9061-0266beb09b91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465116503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3465116503
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3654670269
Short name T176
Test name
Test status
Simulation time 3000369636 ps
CPU time 32.55 seconds
Started Jul 13 06:54:16 PM PDT 24
Finished Jul 13 06:54:49 PM PDT 24
Peak memory 213436 kb
Host smart-34424314-ea94-4144-9d70-8ed3bdc76095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654670269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3654670269
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1415625964
Short name T231
Test name
Test status
Simulation time 295661465 ps
CPU time 17.68 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:54:31 PM PDT 24
Peak memory 214712 kb
Host smart-c0526114-ce21-4964-a7a0-f2ab50f577d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415625964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1415625964
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3241483189
Short name T299
Test name
Test status
Simulation time 3684113242 ps
CPU time 11.6 seconds
Started Jul 13 06:55:15 PM PDT 24
Finished Jul 13 06:55:27 PM PDT 24
Peak memory 211652 kb
Host smart-1069362d-7027-4dd2-b15b-ba6124a6ce3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241483189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3241483189
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2661894436
Short name T35
Test name
Test status
Simulation time 63332377304 ps
CPU time 200.08 seconds
Started Jul 13 06:55:14 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 228644 kb
Host smart-6f0299e3-896c-487c-a69d-7a01dae9315e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661894436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2661894436
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1035854389
Short name T356
Test name
Test status
Simulation time 1068321876 ps
CPU time 16.56 seconds
Started Jul 13 06:55:12 PM PDT 24
Finished Jul 13 06:55:29 PM PDT 24
Peak memory 212108 kb
Host smart-f1ba52ac-d240-4df3-a6b6-bf84aeee376f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035854389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1035854389
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1385646538
Short name T338
Test name
Test status
Simulation time 2097384884 ps
CPU time 16.12 seconds
Started Jul 13 06:55:12 PM PDT 24
Finished Jul 13 06:55:29 PM PDT 24
Peak memory 211400 kb
Host smart-1d710460-69a8-4760-8c8e-dc2d3b6fa91a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385646538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1385646538
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1924186980
Short name T164
Test name
Test status
Simulation time 368059181 ps
CPU time 10.38 seconds
Started Jul 13 06:55:12 PM PDT 24
Finished Jul 13 06:55:23 PM PDT 24
Peak memory 213616 kb
Host smart-c4b2d378-82f7-4d60-9d22-212f89dbd13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924186980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1924186980
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.932694177
Short name T190
Test name
Test status
Simulation time 7050784333 ps
CPU time 28.49 seconds
Started Jul 13 06:55:15 PM PDT 24
Finished Jul 13 06:55:44 PM PDT 24
Peak memory 215324 kb
Host smart-279aa7f7-a436-4bf0-9b6f-ac35f3bcbed5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932694177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.932694177
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1664983639
Short name T288
Test name
Test status
Simulation time 535433443 ps
CPU time 7.99 seconds
Started Jul 13 06:55:13 PM PDT 24
Finished Jul 13 06:55:22 PM PDT 24
Peak memory 211348 kb
Host smart-e3e7ce2b-f889-4da9-9e43-4d0520065b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664983639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1664983639
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.98735463
Short name T251
Test name
Test status
Simulation time 84714157964 ps
CPU time 404.02 seconds
Started Jul 13 06:55:12 PM PDT 24
Finished Jul 13 07:01:57 PM PDT 24
Peak memory 212636 kb
Host smart-c4cd825a-48ab-4d40-b1ea-5650691bf88a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98735463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_co
rrupt_sig_fatal_chk.98735463
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2721982412
Short name T306
Test name
Test status
Simulation time 16030175864 ps
CPU time 32.02 seconds
Started Jul 13 06:55:14 PM PDT 24
Finished Jul 13 06:55:47 PM PDT 24
Peak memory 212276 kb
Host smart-45ad2900-948e-40ef-8422-b39fb009f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721982412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2721982412
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2665835465
Short name T352
Test name
Test status
Simulation time 98598359 ps
CPU time 5.79 seconds
Started Jul 13 06:55:13 PM PDT 24
Finished Jul 13 06:55:19 PM PDT 24
Peak memory 211372 kb
Host smart-d38c917f-de4a-4119-b42d-17c9229f728e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665835465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2665835465
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.849502197
Short name T302
Test name
Test status
Simulation time 5616221838 ps
CPU time 18.79 seconds
Started Jul 13 06:55:15 PM PDT 24
Finished Jul 13 06:55:35 PM PDT 24
Peak memory 213812 kb
Host smart-fde1ec77-e786-48a7-b173-2909e4c5ef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849502197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.849502197
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.66871928
Short name T322
Test name
Test status
Simulation time 388981482 ps
CPU time 21.41 seconds
Started Jul 13 06:55:14 PM PDT 24
Finished Jul 13 06:55:36 PM PDT 24
Peak memory 216296 kb
Host smart-58036f36-a6f2-4dcb-a6d5-28a93f9fab1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66871928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.rom_ctrl_stress_all.66871928
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1658902870
Short name T331
Test name
Test status
Simulation time 39885343254 ps
CPU time 2686.15 seconds
Started Jul 13 06:55:12 PM PDT 24
Finished Jul 13 07:39:59 PM PDT 24
Peak memory 235844 kb
Host smart-2837ed5d-65cd-47b1-b78a-384064ffac08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658902870 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1658902870
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.824887412
Short name T303
Test name
Test status
Simulation time 100009572 ps
CPU time 4.35 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:55:27 PM PDT 24
Peak memory 211384 kb
Host smart-ca30839e-45e1-4ec2-bd7d-ea1aa939cf74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824887412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.824887412
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2209554699
Short name T41
Test name
Test status
Simulation time 129481532887 ps
CPU time 364.97 seconds
Started Jul 13 06:55:14 PM PDT 24
Finished Jul 13 07:01:20 PM PDT 24
Peak memory 225280 kb
Host smart-70646306-2aa5-4439-87dd-40e38494434c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209554699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2209554699
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.317981599
Short name T167
Test name
Test status
Simulation time 11268619489 ps
CPU time 26.13 seconds
Started Jul 13 06:55:14 PM PDT 24
Finished Jul 13 06:55:41 PM PDT 24
Peak memory 212236 kb
Host smart-98f389af-abf9-4ad0-a30a-f83700132b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317981599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.317981599
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1237148028
Short name T228
Test name
Test status
Simulation time 1516348198 ps
CPU time 8.13 seconds
Started Jul 13 06:55:14 PM PDT 24
Finished Jul 13 06:55:23 PM PDT 24
Peak memory 211360 kb
Host smart-7a5046ba-cb32-49d7-a370-63b6ed29f766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1237148028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1237148028
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2950232468
Short name T16
Test name
Test status
Simulation time 20444802409 ps
CPU time 32.64 seconds
Started Jul 13 06:55:15 PM PDT 24
Finished Jul 13 06:55:48 PM PDT 24
Peak memory 214332 kb
Host smart-168edc9c-8239-458e-aee9-701ba7dddf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950232468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2950232468
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.859084259
Short name T337
Test name
Test status
Simulation time 1738214177 ps
CPU time 22.07 seconds
Started Jul 13 06:55:12 PM PDT 24
Finished Jul 13 06:55:35 PM PDT 24
Peak memory 213336 kb
Host smart-a80feb8f-8807-47b6-a8e0-d75215873ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859084259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.859084259
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1016413471
Short name T330
Test name
Test status
Simulation time 2248688025 ps
CPU time 11.41 seconds
Started Jul 13 06:55:25 PM PDT 24
Finished Jul 13 06:55:37 PM PDT 24
Peak memory 211404 kb
Host smart-da54fec3-0dc8-4f82-847a-a87c83d77d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016413471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1016413471
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1959529401
Short name T191
Test name
Test status
Simulation time 173773325 ps
CPU time 9.56 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:55:33 PM PDT 24
Peak memory 212056 kb
Host smart-4f4f6f39-2c0d-42fc-8843-239b3cf11096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959529401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1959529401
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3107443215
Short name T242
Test name
Test status
Simulation time 1141313789 ps
CPU time 11.29 seconds
Started Jul 13 06:55:20 PM PDT 24
Finished Jul 13 06:55:31 PM PDT 24
Peak memory 211424 kb
Host smart-b48b3aa7-af22-4402-ace2-83074bce508b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107443215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3107443215
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1934526619
Short name T135
Test name
Test status
Simulation time 3599682459 ps
CPU time 30.31 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:55:53 PM PDT 24
Peak memory 213128 kb
Host smart-1d78e0e3-8df6-41a4-a99a-390e746aeae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934526619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1934526619
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.843873690
Short name T237
Test name
Test status
Simulation time 478124028 ps
CPU time 8.02 seconds
Started Jul 13 06:55:24 PM PDT 24
Finished Jul 13 06:55:32 PM PDT 24
Peak memory 211404 kb
Host smart-38c446d2-6f56-4187-9bf5-4b02bc77aca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843873690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.843873690
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1902126723
Short name T93
Test name
Test status
Simulation time 26343469126 ps
CPU time 2242.09 seconds
Started Jul 13 06:55:20 PM PDT 24
Finished Jul 13 07:32:43 PM PDT 24
Peak memory 235580 kb
Host smart-173dcb35-d24e-4cfd-a897-8d24cb691614
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902126723 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1902126723
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.887607251
Short name T60
Test name
Test status
Simulation time 2454718546 ps
CPU time 12.05 seconds
Started Jul 13 06:55:16 PM PDT 24
Finished Jul 13 06:55:28 PM PDT 24
Peak memory 211372 kb
Host smart-06048b95-c0f2-4ee3-877e-b4e7a9f06416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887607251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.887607251
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.520212829
Short name T326
Test name
Test status
Simulation time 74451363981 ps
CPU time 151.74 seconds
Started Jul 13 06:55:27 PM PDT 24
Finished Jul 13 06:57:59 PM PDT 24
Peak memory 233328 kb
Host smart-a822fd07-0fe1-4f05-8d5e-ca43e7e7cfd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520212829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.520212829
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4041993898
Short name T250
Test name
Test status
Simulation time 4630080760 ps
CPU time 27.7 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:55:51 PM PDT 24
Peak memory 212244 kb
Host smart-23da8428-d8ac-4707-b6e8-1ab7f290e65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041993898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.4041993898
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1787595908
Short name T291
Test name
Test status
Simulation time 3769054579 ps
CPU time 7.73 seconds
Started Jul 13 06:55:26 PM PDT 24
Finished Jul 13 06:55:34 PM PDT 24
Peak memory 211376 kb
Host smart-edbb923a-a4eb-4da8-9efb-24a7482cda29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787595908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1787595908
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3757769524
Short name T127
Test name
Test status
Simulation time 9970283147 ps
CPU time 23.9 seconds
Started Jul 13 06:55:27 PM PDT 24
Finished Jul 13 06:55:52 PM PDT 24
Peak memory 214212 kb
Host smart-6feb0e1a-07eb-40c2-b19c-7346c64a1a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757769524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3757769524
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2477117183
Short name T346
Test name
Test status
Simulation time 3524455711 ps
CPU time 35.78 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:55:59 PM PDT 24
Peak memory 216456 kb
Host smart-29452fb0-6c87-4656-91f8-93736dd000cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477117183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2477117183
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3704761553
Short name T265
Test name
Test status
Simulation time 8932467778 ps
CPU time 14.05 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:55:37 PM PDT 24
Peak memory 211380 kb
Host smart-ea0817bf-6830-446e-991b-5c728afd3d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704761553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3704761553
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1034756709
Short name T361
Test name
Test status
Simulation time 51855418511 ps
CPU time 227.9 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:59:11 PM PDT 24
Peak memory 238628 kb
Host smart-f578ac70-00d0-405c-b9d5-127ed57bbbe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034756709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1034756709
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3746466964
Short name T316
Test name
Test status
Simulation time 4167292632 ps
CPU time 33.31 seconds
Started Jul 13 06:55:20 PM PDT 24
Finished Jul 13 06:55:53 PM PDT 24
Peak memory 212008 kb
Host smart-a5546ba5-1704-41f2-bc6c-f9e35c327408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746466964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3746466964
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4069421078
Short name T168
Test name
Test status
Simulation time 2470174885 ps
CPU time 8.79 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:55:31 PM PDT 24
Peak memory 211396 kb
Host smart-7550d5da-7859-4caf-a4c3-751fc689103b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069421078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4069421078
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1290543878
Short name T192
Test name
Test status
Simulation time 3253771959 ps
CPU time 20.63 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:55:43 PM PDT 24
Peak memory 212192 kb
Host smart-9d964201-774a-4490-86c2-d2b2190a4468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290543878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1290543878
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3871810696
Short name T268
Test name
Test status
Simulation time 1793828293 ps
CPU time 15.13 seconds
Started Jul 13 06:55:21 PM PDT 24
Finished Jul 13 06:55:37 PM PDT 24
Peak memory 211404 kb
Host smart-95f45bf3-9daa-4031-a463-fa1c17854946
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871810696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3871810696
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.858795128
Short name T336
Test name
Test status
Simulation time 22847922570 ps
CPU time 6099.85 seconds
Started Jul 13 06:55:20 PM PDT 24
Finished Jul 13 08:37:01 PM PDT 24
Peak memory 228452 kb
Host smart-a7a96efc-8ebf-4a8d-bf9a-648ac49a75ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858795128 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.858795128
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.433985925
Short name T210
Test name
Test status
Simulation time 692312814 ps
CPU time 5.16 seconds
Started Jul 13 06:55:24 PM PDT 24
Finished Jul 13 06:55:29 PM PDT 24
Peak memory 211336 kb
Host smart-6cf35970-b254-4373-be5b-2b826e91d4b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433985925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.433985925
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4184787048
Short name T232
Test name
Test status
Simulation time 36293489251 ps
CPU time 179.69 seconds
Started Jul 13 06:55:20 PM PDT 24
Finished Jul 13 06:58:20 PM PDT 24
Peak memory 234880 kb
Host smart-6163f2e3-5293-413c-8a7c-566104dc4662
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184787048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4184787048
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1239045216
Short name T310
Test name
Test status
Simulation time 175361671 ps
CPU time 9.61 seconds
Started Jul 13 06:55:21 PM PDT 24
Finished Jul 13 06:55:31 PM PDT 24
Peak memory 212056 kb
Host smart-3735ab9b-e2ed-4ac7-b74c-477fe8d3ef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239045216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1239045216
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3080196968
Short name T178
Test name
Test status
Simulation time 1318891142 ps
CPU time 12.9 seconds
Started Jul 13 06:55:21 PM PDT 24
Finished Jul 13 06:55:35 PM PDT 24
Peak memory 211400 kb
Host smart-4cb357c2-e8cd-4474-9895-eedc4705fe70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080196968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3080196968
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1109090848
Short name T209
Test name
Test status
Simulation time 5352321994 ps
CPU time 35 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:55:58 PM PDT 24
Peak memory 214076 kb
Host smart-1f032b0a-a88b-4df8-b414-38eb8e6dcca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109090848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1109090848
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.92309362
Short name T301
Test name
Test status
Simulation time 2916682073 ps
CPU time 21.97 seconds
Started Jul 13 06:55:22 PM PDT 24
Finished Jul 13 06:55:45 PM PDT 24
Peak memory 212576 kb
Host smart-252bd7dc-dc67-48f4-bb58-7ce46fe0039d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92309362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.rom_ctrl_stress_all.92309362
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.478107815
Short name T44
Test name
Test status
Simulation time 294943400385 ps
CPU time 2905.43 seconds
Started Jul 13 06:55:28 PM PDT 24
Finished Jul 13 07:43:54 PM PDT 24
Peak memory 244296 kb
Host smart-322a858d-bf9c-4182-8466-db8f5ae9f4d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478107815 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.478107815
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2881245602
Short name T321
Test name
Test status
Simulation time 2560972259 ps
CPU time 8.14 seconds
Started Jul 13 06:55:29 PM PDT 24
Finished Jul 13 06:55:38 PM PDT 24
Peak memory 211388 kb
Host smart-d0c140e7-3914-4050-862c-1fa9539b64c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881245602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2881245602
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1556713193
Short name T201
Test name
Test status
Simulation time 14726785229 ps
CPU time 210.68 seconds
Started Jul 13 06:55:33 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 236712 kb
Host smart-3d1a4f3b-c4a7-4155-9d7e-b756d40091f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556713193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1556713193
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2653444046
Short name T353
Test name
Test status
Simulation time 7695835262 ps
CPU time 30.81 seconds
Started Jul 13 06:55:31 PM PDT 24
Finished Jul 13 06:56:03 PM PDT 24
Peak memory 212612 kb
Host smart-f6904a65-7677-45ba-ae3f-4fe3896eac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653444046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2653444046
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3746923789
Short name T208
Test name
Test status
Simulation time 1975521951 ps
CPU time 11.01 seconds
Started Jul 13 06:55:28 PM PDT 24
Finished Jul 13 06:55:40 PM PDT 24
Peak memory 211380 kb
Host smart-cced4250-77fa-4d12-a9ba-f1f485ae7c95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746923789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3746923789
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1825084740
Short name T249
Test name
Test status
Simulation time 8882209826 ps
CPU time 26.23 seconds
Started Jul 13 06:55:28 PM PDT 24
Finished Jul 13 06:55:55 PM PDT 24
Peak memory 214348 kb
Host smart-687754bc-ce14-4e51-95de-d269e1d9686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825084740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1825084740
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1125257055
Short name T53
Test name
Test status
Simulation time 1376841710 ps
CPU time 21.48 seconds
Started Jul 13 06:55:30 PM PDT 24
Finished Jul 13 06:55:52 PM PDT 24
Peak memory 212592 kb
Host smart-5843cee8-d2fd-4534-a72b-4792e015ce23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125257055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1125257055
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4025079406
Short name T254
Test name
Test status
Simulation time 4900842608 ps
CPU time 11.18 seconds
Started Jul 13 06:55:29 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 211372 kb
Host smart-5f9a0fce-6522-4c91-8cea-483e7f0be5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025079406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4025079406
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2671960516
Short name T86
Test name
Test status
Simulation time 71695926076 ps
CPU time 198.33 seconds
Started Jul 13 06:55:29 PM PDT 24
Finished Jul 13 06:58:49 PM PDT 24
Peak memory 238076 kb
Host smart-df064534-5166-4e7e-90d7-cad3848fab75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671960516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2671960516
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1842694113
Short name T122
Test name
Test status
Simulation time 873961863 ps
CPU time 9.84 seconds
Started Jul 13 06:55:30 PM PDT 24
Finished Jul 13 06:55:41 PM PDT 24
Peak memory 211932 kb
Host smart-b319e997-5c4c-4b4f-83fd-52ec6ae798e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842694113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1842694113
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.154873923
Short name T266
Test name
Test status
Simulation time 1390799489 ps
CPU time 13.27 seconds
Started Jul 13 06:55:31 PM PDT 24
Finished Jul 13 06:55:46 PM PDT 24
Peak memory 211400 kb
Host smart-b25965bb-b936-4600-a9c0-f7f36e1efb45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154873923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.154873923
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.444215890
Short name T318
Test name
Test status
Simulation time 8043163485 ps
CPU time 32.85 seconds
Started Jul 13 06:55:30 PM PDT 24
Finished Jul 13 06:56:04 PM PDT 24
Peak memory 213976 kb
Host smart-8bb6ec8a-bcda-4df4-b228-23954dcb4ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444215890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.444215890
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3225447003
Short name T305
Test name
Test status
Simulation time 302548797 ps
CPU time 13.11 seconds
Started Jul 13 06:55:29 PM PDT 24
Finished Jul 13 06:55:43 PM PDT 24
Peak memory 214700 kb
Host smart-e227dbe6-c23f-4535-ab8a-7f3262773af8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225447003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3225447003
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.802125015
Short name T345
Test name
Test status
Simulation time 2305454223 ps
CPU time 11.72 seconds
Started Jul 13 06:55:33 PM PDT 24
Finished Jul 13 06:55:45 PM PDT 24
Peak memory 211596 kb
Host smart-2250fdcf-78b4-4203-852c-f80bbc4691b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802125015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.802125015
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.332116248
Short name T234
Test name
Test status
Simulation time 31515042617 ps
CPU time 147.46 seconds
Started Jul 13 06:55:30 PM PDT 24
Finished Jul 13 06:58:00 PM PDT 24
Peak memory 237864 kb
Host smart-e583b996-ddbd-48c2-819d-6af15853f7f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332116248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.332116248
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1019805737
Short name T186
Test name
Test status
Simulation time 2693578935 ps
CPU time 17.92 seconds
Started Jul 13 06:55:31 PM PDT 24
Finished Jul 13 06:55:51 PM PDT 24
Peak memory 212008 kb
Host smart-6dffe3e0-be16-4084-9836-9f594e2bb3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019805737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1019805737
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1482733603
Short name T173
Test name
Test status
Simulation time 10383913248 ps
CPU time 12.27 seconds
Started Jul 13 06:55:29 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 211428 kb
Host smart-fd4533b8-30cc-440c-af9c-7478334028e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482733603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1482733603
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.34768370
Short name T71
Test name
Test status
Simulation time 726582997 ps
CPU time 10.41 seconds
Started Jul 13 06:55:31 PM PDT 24
Finished Jul 13 06:55:43 PM PDT 24
Peak memory 213528 kb
Host smart-b16e2894-dd27-4136-b17d-a63b6a016d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34768370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.34768370
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.479357249
Short name T145
Test name
Test status
Simulation time 25527613382 ps
CPU time 30.44 seconds
Started Jul 13 06:55:32 PM PDT 24
Finished Jul 13 06:56:04 PM PDT 24
Peak memory 215028 kb
Host smart-22967fbb-c308-4911-b8af-6bc58334fb0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479357249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.479357249
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3269639900
Short name T48
Test name
Test status
Simulation time 190437742583 ps
CPU time 7123.55 seconds
Started Jul 13 06:55:29 PM PDT 24
Finished Jul 13 08:54:14 PM PDT 24
Peak memory 236508 kb
Host smart-7fda8f90-59d1-4685-a862-e57727089a19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269639900 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3269639900
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.466626228
Short name T229
Test name
Test status
Simulation time 89022878 ps
CPU time 4.27 seconds
Started Jul 13 06:54:15 PM PDT 24
Finished Jul 13 06:54:20 PM PDT 24
Peak memory 211548 kb
Host smart-b6ccd9fc-d5f3-4240-b0d1-82e28f4ff8d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466626228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.466626228
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2934585002
Short name T89
Test name
Test status
Simulation time 11915704984 ps
CPU time 134.14 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:56:28 PM PDT 24
Peak memory 236760 kb
Host smart-0a0e6ae5-5014-4ddb-9b6a-dbf141470245
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934585002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2934585002
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2764949234
Short name T196
Test name
Test status
Simulation time 5431067664 ps
CPU time 24.52 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:54:39 PM PDT 24
Peak memory 212276 kb
Host smart-586e6319-5c87-41ac-94de-2f9465d53d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764949234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2764949234
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1374012292
Short name T278
Test name
Test status
Simulation time 100985837 ps
CPU time 5.69 seconds
Started Jul 13 06:54:10 PM PDT 24
Finished Jul 13 06:54:16 PM PDT 24
Peak memory 211412 kb
Host smart-64ba66fc-100b-424e-b761-39b5a3655804
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374012292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1374012292
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2447948576
Short name T180
Test name
Test status
Simulation time 4499723807 ps
CPU time 20.98 seconds
Started Jul 13 06:54:14 PM PDT 24
Finished Jul 13 06:54:36 PM PDT 24
Peak memory 213544 kb
Host smart-7c6af71f-b449-4401-b81b-1ed808429ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447948576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2447948576
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.422500627
Short name T154
Test name
Test status
Simulation time 457451507 ps
CPU time 21.31 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:54:35 PM PDT 24
Peak memory 215180 kb
Host smart-10f945cd-d445-43b8-9545-bcbfb473e15f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422500627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.422500627
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.413810745
Short name T92
Test name
Test status
Simulation time 138062472966 ps
CPU time 9803.44 seconds
Started Jul 13 06:54:11 PM PDT 24
Finished Jul 13 09:37:36 PM PDT 24
Peak memory 235828 kb
Host smart-df154f4e-13ac-479d-8751-9da70e2e3dac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413810745 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.413810745
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1330913695
Short name T144
Test name
Test status
Simulation time 86237720 ps
CPU time 4.4 seconds
Started Jul 13 06:54:14 PM PDT 24
Finished Jul 13 06:54:19 PM PDT 24
Peak memory 211328 kb
Host smart-6cd372a4-bcc3-4537-8318-c8b06d6c38b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330913695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1330913695
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3251756069
Short name T247
Test name
Test status
Simulation time 14046415468 ps
CPU time 189 seconds
Started Jul 13 06:54:17 PM PDT 24
Finished Jul 13 06:57:27 PM PDT 24
Peak memory 237840 kb
Host smart-6781b4dc-be79-4250-8b06-9610254ca32a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251756069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3251756069
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2809090399
Short name T194
Test name
Test status
Simulation time 4413266464 ps
CPU time 31.49 seconds
Started Jul 13 06:54:16 PM PDT 24
Finished Jul 13 06:54:48 PM PDT 24
Peak memory 211484 kb
Host smart-3928e872-e1a7-4093-aa24-6910d23fcba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809090399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2809090399
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.887998970
Short name T282
Test name
Test status
Simulation time 607869621 ps
CPU time 7.66 seconds
Started Jul 13 06:54:14 PM PDT 24
Finished Jul 13 06:54:22 PM PDT 24
Peak memory 211440 kb
Host smart-636e7ef3-34d9-41da-ad42-11c396a6775e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887998970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.887998970
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3079725938
Short name T298
Test name
Test status
Simulation time 33723616026 ps
CPU time 31.75 seconds
Started Jul 13 06:54:17 PM PDT 24
Finished Jul 13 06:54:49 PM PDT 24
Peak memory 214408 kb
Host smart-9cdb3962-956c-42c1-a3e9-dedf4be3489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079725938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3079725938
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3761200151
Short name T263
Test name
Test status
Simulation time 7672308413 ps
CPU time 16.79 seconds
Started Jul 13 06:54:16 PM PDT 24
Finished Jul 13 06:54:34 PM PDT 24
Peak memory 212656 kb
Host smart-eb697f93-41bf-4f8a-8dd9-adef3d392965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761200151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3761200151
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.794630547
Short name T152
Test name
Test status
Simulation time 548719963 ps
CPU time 7.63 seconds
Started Jul 13 06:54:17 PM PDT 24
Finished Jul 13 06:54:25 PM PDT 24
Peak memory 211340 kb
Host smart-093f29a3-e6b9-411d-868b-e22c5bc6f59a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794630547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.794630547
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.888719644
Short name T217
Test name
Test status
Simulation time 34610125341 ps
CPU time 311.66 seconds
Started Jul 13 06:54:16 PM PDT 24
Finished Jul 13 06:59:29 PM PDT 24
Peak memory 228596 kb
Host smart-5d53b4cc-ba43-4c80-b368-9b47723f32ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888719644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.888719644
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3098932189
Short name T270
Test name
Test status
Simulation time 15130648982 ps
CPU time 30.6 seconds
Started Jul 13 06:54:11 PM PDT 24
Finished Jul 13 06:54:42 PM PDT 24
Peak memory 212260 kb
Host smart-779f9d48-de6c-43c3-808b-3f1fb3d632ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098932189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3098932189
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2767158612
Short name T327
Test name
Test status
Simulation time 425268944 ps
CPU time 8.35 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:54:22 PM PDT 24
Peak memory 211388 kb
Host smart-97df0b73-b0b4-4148-ab5f-5310fd669bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767158612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2767158612
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2770995287
Short name T119
Test name
Test status
Simulation time 3323237766 ps
CPU time 29.08 seconds
Started Jul 13 06:54:12 PM PDT 24
Finished Jul 13 06:54:42 PM PDT 24
Peak memory 211876 kb
Host smart-be2b9994-c706-4fb8-b5b4-e3e0bc0bfb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770995287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2770995287
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3910356993
Short name T121
Test name
Test status
Simulation time 8021150991 ps
CPU time 71.54 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:55:25 PM PDT 24
Peak memory 216900 kb
Host smart-76bf7db8-c0eb-4adf-a714-0501f235df7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910356993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3910356993
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3281915142
Short name T362
Test name
Test status
Simulation time 499483659 ps
CPU time 5.16 seconds
Started Jul 13 06:54:16 PM PDT 24
Finished Jul 13 06:54:22 PM PDT 24
Peak memory 211336 kb
Host smart-1e9cd763-0a63-4ed3-89b7-3e2cccfeffb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281915142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3281915142
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4173684381
Short name T284
Test name
Test status
Simulation time 17270246715 ps
CPU time 212.01 seconds
Started Jul 13 06:54:16 PM PDT 24
Finished Jul 13 06:57:49 PM PDT 24
Peak memory 225152 kb
Host smart-b62f2af5-190f-4ddc-9629-ab7975ceefac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173684381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4173684381
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2276315896
Short name T28
Test name
Test status
Simulation time 3210635116 ps
CPU time 18.59 seconds
Started Jul 13 06:54:12 PM PDT 24
Finished Jul 13 06:54:32 PM PDT 24
Peak memory 213088 kb
Host smart-9eefa712-0bff-4fc2-9a55-06b0a576a87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276315896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2276315896
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2254965941
Short name T287
Test name
Test status
Simulation time 7851269508 ps
CPU time 16.59 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:54:30 PM PDT 24
Peak memory 211484 kb
Host smart-48343695-67c3-44c4-bc0b-4b86ab1d6ece
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254965941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2254965941
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.515875931
Short name T238
Test name
Test status
Simulation time 4296418711 ps
CPU time 34.95 seconds
Started Jul 13 06:54:16 PM PDT 24
Finished Jul 13 06:54:51 PM PDT 24
Peak memory 213852 kb
Host smart-1f6315a4-86a7-430b-8ee1-92e7ce0177e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515875931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.515875931
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2297240268
Short name T349
Test name
Test status
Simulation time 4193086422 ps
CPU time 36.61 seconds
Started Jul 13 06:54:11 PM PDT 24
Finished Jul 13 06:54:48 PM PDT 24
Peak memory 213012 kb
Host smart-d7f38498-4892-4cbf-b068-86bc60435aa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297240268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2297240268
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2276672159
Short name T130
Test name
Test status
Simulation time 1114008508 ps
CPU time 7.85 seconds
Started Jul 13 06:54:20 PM PDT 24
Finished Jul 13 06:54:29 PM PDT 24
Peak memory 211340 kb
Host smart-3b7cdd40-d814-4147-8c5f-e17e0734e601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276672159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2276672159
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.679454564
Short name T295
Test name
Test status
Simulation time 114888954055 ps
CPU time 310.55 seconds
Started Jul 13 06:54:10 PM PDT 24
Finished Jul 13 06:59:21 PM PDT 24
Peak memory 211668 kb
Host smart-013df008-3c36-447a-9404-9c39043d00f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679454564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.679454564
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.144114810
Short name T269
Test name
Test status
Simulation time 183063163 ps
CPU time 9.6 seconds
Started Jul 13 06:54:12 PM PDT 24
Finished Jul 13 06:54:23 PM PDT 24
Peak memory 211968 kb
Host smart-a7dbafa2-e8ac-47f8-b061-aed0d6eb8d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144114810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.144114810
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4108726247
Short name T101
Test name
Test status
Simulation time 1202866740 ps
CPU time 12.09 seconds
Started Jul 13 06:54:13 PM PDT 24
Finished Jul 13 06:54:26 PM PDT 24
Peak memory 211348 kb
Host smart-4cbffc23-1d9d-443e-bb91-ae8b0de55211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4108726247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4108726247
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4174631987
Short name T226
Test name
Test status
Simulation time 19461829521 ps
CPU time 33.45 seconds
Started Jul 13 06:54:14 PM PDT 24
Finished Jul 13 06:54:48 PM PDT 24
Peak memory 213948 kb
Host smart-110a8251-cd2c-4f2b-8fb7-02308525918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174631987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4174631987
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4130843560
Short name T277
Test name
Test status
Simulation time 19364332400 ps
CPU time 41.69 seconds
Started Jul 13 06:54:12 PM PDT 24
Finished Jul 13 06:54:54 PM PDT 24
Peak memory 214300 kb
Host smart-5fa7b302-601d-4ecf-9546-0e1f2047d9cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130843560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4130843560
Directory /workspace/9.rom_ctrl_stress_all/latest
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