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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.34 96.89 91.99 97.67 100.00 98.28 97.45 99.07


Total test records in report: 468
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T299 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.889774646 Jul 14 06:51:20 PM PDT 24 Jul 14 06:51:33 PM PDT 24 4683423216 ps
T300 /workspace/coverage/default/19.rom_ctrl_stress_all.2755290959 Jul 14 06:50:55 PM PDT 24 Jul 14 06:51:10 PM PDT 24 422060855 ps
T301 /workspace/coverage/default/43.rom_ctrl_smoke.2085186491 Jul 14 06:51:31 PM PDT 24 Jul 14 06:52:05 PM PDT 24 4123785569 ps
T302 /workspace/coverage/default/42.rom_ctrl_stress_all.1948619785 Jul 14 06:51:32 PM PDT 24 Jul 14 06:53:11 PM PDT 24 9486908109 ps
T303 /workspace/coverage/default/10.rom_ctrl_smoke.1081441286 Jul 14 06:50:43 PM PDT 24 Jul 14 06:51:04 PM PDT 24 1122431974 ps
T304 /workspace/coverage/default/25.rom_ctrl_smoke.3351016295 Jul 14 06:51:00 PM PDT 24 Jul 14 06:51:36 PM PDT 24 19520979240 ps
T305 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3459622111 Jul 14 06:51:23 PM PDT 24 Jul 14 06:51:42 PM PDT 24 6072653401 ps
T306 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.974979181 Jul 14 06:50:56 PM PDT 24 Jul 14 06:51:13 PM PDT 24 7174941858 ps
T307 /workspace/coverage/default/18.rom_ctrl_stress_all.3575286882 Jul 14 06:50:51 PM PDT 24 Jul 14 06:51:15 PM PDT 24 1266347289 ps
T308 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1541608237 Jul 14 06:51:34 PM PDT 24 Jul 14 06:51:51 PM PDT 24 1751374225 ps
T309 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.695037283 Jul 14 06:51:07 PM PDT 24 Jul 14 06:51:23 PM PDT 24 1850607854 ps
T310 /workspace/coverage/default/5.rom_ctrl_stress_all.326790547 Jul 14 06:50:32 PM PDT 24 Jul 14 06:50:56 PM PDT 24 739555736 ps
T311 /workspace/coverage/default/10.rom_ctrl_alert_test.2902961675 Jul 14 06:50:42 PM PDT 24 Jul 14 06:50:51 PM PDT 24 1668021087 ps
T312 /workspace/coverage/default/34.rom_ctrl_alert_test.4261040328 Jul 14 06:51:22 PM PDT 24 Jul 14 06:51:28 PM PDT 24 830577703 ps
T313 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1237923679 Jul 14 06:50:42 PM PDT 24 Jul 14 06:58:39 PM PDT 24 49641270402 ps
T314 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3032090254 Jul 14 06:51:34 PM PDT 24 Jul 14 06:51:47 PM PDT 24 1141101341 ps
T315 /workspace/coverage/default/44.rom_ctrl_alert_test.108668994 Jul 14 06:51:38 PM PDT 24 Jul 14 06:51:50 PM PDT 24 1062592842 ps
T26 /workspace/coverage/default/0.rom_ctrl_sec_cm.592236476 Jul 14 06:50:23 PM PDT 24 Jul 14 06:51:16 PM PDT 24 139161800 ps
T316 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3643838669 Jul 14 06:51:11 PM PDT 24 Jul 14 06:51:17 PM PDT 24 333744413 ps
T317 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1561275822 Jul 14 06:51:32 PM PDT 24 Jul 14 06:51:51 PM PDT 24 1242040466 ps
T318 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.654752104 Jul 14 06:50:54 PM PDT 24 Jul 14 06:51:14 PM PDT 24 1413565557 ps
T319 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3789434330 Jul 14 06:51:31 PM PDT 24 Jul 14 06:51:43 PM PDT 24 692927337 ps
T320 /workspace/coverage/default/26.rom_ctrl_alert_test.2472267181 Jul 14 06:51:10 PM PDT 24 Jul 14 06:51:25 PM PDT 24 1871219323 ps
T321 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3373749495 Jul 14 06:51:38 PM PDT 24 Jul 14 06:52:04 PM PDT 24 10320571275 ps
T322 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2773399859 Jul 14 06:50:44 PM PDT 24 Jul 14 06:51:05 PM PDT 24 1934279345 ps
T323 /workspace/coverage/default/10.rom_ctrl_stress_all.2125409003 Jul 14 06:50:41 PM PDT 24 Jul 14 06:51:15 PM PDT 24 4519884139 ps
T324 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3807973832 Jul 14 06:51:19 PM PDT 24 Jul 14 06:54:03 PM PDT 24 8843313217 ps
T325 /workspace/coverage/default/7.rom_ctrl_alert_test.594707023 Jul 14 06:50:37 PM PDT 24 Jul 14 06:50:44 PM PDT 24 1538781583 ps
T326 /workspace/coverage/default/34.rom_ctrl_stress_all.453520705 Jul 14 06:51:14 PM PDT 24 Jul 14 06:51:47 PM PDT 24 6214949489 ps
T327 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1215796456 Jul 14 06:50:48 PM PDT 24 Jul 14 06:56:54 PM PDT 24 151498719054 ps
T328 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2822317203 Jul 14 06:50:43 PM PDT 24 Jul 14 06:50:53 PM PDT 24 864096899 ps
T329 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2549595278 Jul 14 06:50:36 PM PDT 24 Jul 14 06:50:50 PM PDT 24 4825154668 ps
T330 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1052512160 Jul 14 06:51:29 PM PDT 24 Jul 14 06:51:54 PM PDT 24 11182605076 ps
T331 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2917398124 Jul 14 06:51:42 PM PDT 24 Jul 14 06:52:08 PM PDT 24 11618428667 ps
T332 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2665988013 Jul 14 06:50:42 PM PDT 24 Jul 14 08:12:14 PM PDT 24 28687891280 ps
T333 /workspace/coverage/default/47.rom_ctrl_stress_all.3789142031 Jul 14 06:51:36 PM PDT 24 Jul 14 06:52:27 PM PDT 24 5808100427 ps
T334 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2393811532 Jul 14 06:51:37 PM PDT 24 Jul 14 06:52:10 PM PDT 24 8011017424 ps
T335 /workspace/coverage/default/3.rom_ctrl_smoke.3737622232 Jul 14 06:50:29 PM PDT 24 Jul 14 06:50:50 PM PDT 24 3940756955 ps
T336 /workspace/coverage/default/16.rom_ctrl_stress_all.1779107483 Jul 14 06:50:52 PM PDT 24 Jul 14 06:51:18 PM PDT 24 13498631509 ps
T337 /workspace/coverage/default/26.rom_ctrl_smoke.708732252 Jul 14 06:51:03 PM PDT 24 Jul 14 06:51:14 PM PDT 24 387086480 ps
T338 /workspace/coverage/default/30.rom_ctrl_stress_all.1349746292 Jul 14 06:51:15 PM PDT 24 Jul 14 06:51:56 PM PDT 24 4392576034 ps
T339 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3890573412 Jul 14 06:51:37 PM PDT 24 Jul 14 06:52:02 PM PDT 24 2404839406 ps
T340 /workspace/coverage/default/47.rom_ctrl_alert_test.1984276074 Jul 14 06:51:37 PM PDT 24 Jul 14 06:51:51 PM PDT 24 1528858522 ps
T341 /workspace/coverage/default/29.rom_ctrl_smoke.3877484693 Jul 14 06:51:07 PM PDT 24 Jul 14 06:51:21 PM PDT 24 427898940 ps
T342 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1662892961 Jul 14 06:51:14 PM PDT 24 Jul 14 06:52:44 PM PDT 24 1866206531 ps
T343 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.242190277 Jul 14 06:51:14 PM PDT 24 Jul 14 06:51:21 PM PDT 24 492352426 ps
T118 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1413440760 Jul 14 06:50:47 PM PDT 24 Jul 14 07:19:08 PM PDT 24 82208663823 ps
T344 /workspace/coverage/default/40.rom_ctrl_stress_all.4183340671 Jul 14 06:51:31 PM PDT 24 Jul 14 06:51:51 PM PDT 24 1684086393 ps
T345 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1240068989 Jul 14 06:51:20 PM PDT 24 Jul 14 07:26:50 PM PDT 24 151487267790 ps
T346 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.584539564 Jul 14 06:51:11 PM PDT 24 Jul 14 06:51:27 PM PDT 24 7522068618 ps
T347 /workspace/coverage/default/16.rom_ctrl_alert_test.1587344415 Jul 14 06:50:49 PM PDT 24 Jul 14 06:51:02 PM PDT 24 2257031640 ps
T348 /workspace/coverage/default/11.rom_ctrl_stress_all.2207797030 Jul 14 06:50:42 PM PDT 24 Jul 14 06:52:06 PM PDT 24 17920161936 ps
T349 /workspace/coverage/default/21.rom_ctrl_alert_test.2537254457 Jul 14 06:50:58 PM PDT 24 Jul 14 06:51:03 PM PDT 24 333709524 ps
T350 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.609264195 Jul 14 06:50:46 PM PDT 24 Jul 14 06:53:15 PM PDT 24 17588101293 ps
T351 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4027897554 Jul 14 06:50:49 PM PDT 24 Jul 14 06:51:06 PM PDT 24 1972113425 ps
T352 /workspace/coverage/default/49.rom_ctrl_alert_test.2473355968 Jul 14 06:51:53 PM PDT 24 Jul 14 06:52:04 PM PDT 24 804494487 ps
T353 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3922319336 Jul 14 06:51:14 PM PDT 24 Jul 14 06:52:28 PM PDT 24 1021171218 ps
T354 /workspace/coverage/default/14.rom_ctrl_smoke.1322551675 Jul 14 06:50:47 PM PDT 24 Jul 14 06:51:26 PM PDT 24 4458501626 ps
T355 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.133291380 Jul 14 06:51:34 PM PDT 24 Jul 14 06:51:46 PM PDT 24 1456250693 ps
T356 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2303552234 Jul 14 06:50:41 PM PDT 24 Jul 14 06:50:56 PM PDT 24 1543593338 ps
T357 /workspace/coverage/default/8.rom_ctrl_alert_test.3849105663 Jul 14 06:50:42 PM PDT 24 Jul 14 06:50:48 PM PDT 24 209310779 ps
T358 /workspace/coverage/default/26.rom_ctrl_stress_all.3331435283 Jul 14 06:51:02 PM PDT 24 Jul 14 06:51:47 PM PDT 24 7286596080 ps
T359 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3082593995 Jul 14 06:51:00 PM PDT 24 Jul 14 06:51:14 PM PDT 24 2594207348 ps
T360 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.582156067 Jul 14 06:50:24 PM PDT 24 Jul 14 06:50:36 PM PDT 24 2091953188 ps
T361 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4277106459 Jul 14 06:50:36 PM PDT 24 Jul 14 06:50:47 PM PDT 24 1916720831 ps
T362 /workspace/coverage/default/19.rom_ctrl_alert_test.1851573066 Jul 14 06:50:54 PM PDT 24 Jul 14 06:50:59 PM PDT 24 246770549 ps
T363 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.567527550 Jul 14 06:51:37 PM PDT 24 Jul 14 06:58:33 PM PDT 24 473106291291 ps
T364 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2531592035 Jul 14 06:50:30 PM PDT 24 Jul 14 06:50:37 PM PDT 24 443776537 ps
T365 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2671320853 Jul 14 06:51:06 PM PDT 24 Jul 14 06:51:22 PM PDT 24 4118153080 ps
T366 /workspace/coverage/default/46.rom_ctrl_alert_test.3578975805 Jul 14 06:51:35 PM PDT 24 Jul 14 06:51:45 PM PDT 24 13014385933 ps
T367 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3093327392 Jul 14 06:50:55 PM PDT 24 Jul 14 06:54:45 PM PDT 24 85554747875 ps
T368 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.127733352 Jul 14 06:51:08 PM PDT 24 Jul 14 06:51:21 PM PDT 24 1326769198 ps
T369 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4201493412 Jul 14 06:50:43 PM PDT 24 Jul 14 06:51:12 PM PDT 24 3927612396 ps
T370 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.177082035 Jul 14 06:52:03 PM PDT 24 Jul 14 06:52:24 PM PDT 24 7819886866 ps
T60 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2133908750 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:09 PM PDT 24 437344995 ps
T61 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3087508726 Jul 14 06:51:56 PM PDT 24 Jul 14 06:52:13 PM PDT 24 12501413917 ps
T62 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3418189971 Jul 14 06:51:50 PM PDT 24 Jul 14 06:52:01 PM PDT 24 2228115581 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.681862555 Jul 14 06:51:44 PM PDT 24 Jul 14 06:51:57 PM PDT 24 1004523228 ps
T67 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4159055188 Jul 14 06:51:49 PM PDT 24 Jul 14 06:52:04 PM PDT 24 2629301751 ps
T111 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4069368563 Jul 14 06:52:03 PM PDT 24 Jul 14 06:52:11 PM PDT 24 132708787 ps
T372 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3203808911 Jul 14 06:51:56 PM PDT 24 Jul 14 06:52:14 PM PDT 24 4193977271 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.303365324 Jul 14 06:51:45 PM PDT 24 Jul 14 06:52:01 PM PDT 24 1763400256 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2692492356 Jul 14 06:51:44 PM PDT 24 Jul 14 06:51:58 PM PDT 24 1677350608 ps
T68 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.817519691 Jul 14 06:52:07 PM PDT 24 Jul 14 06:53:25 PM PDT 24 27868716016 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3488068761 Jul 14 06:51:42 PM PDT 24 Jul 14 06:51:55 PM PDT 24 1114252423 ps
T374 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3762673850 Jul 14 06:51:54 PM PDT 24 Jul 14 06:52:06 PM PDT 24 763642624 ps
T57 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.532490604 Jul 14 06:52:01 PM PDT 24 Jul 14 06:53:18 PM PDT 24 1742861574 ps
T58 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3094572537 Jul 14 06:52:03 PM PDT 24 Jul 14 06:52:51 PM PDT 24 6813564425 ps
T113 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4147190286 Jul 14 06:51:43 PM PDT 24 Jul 14 06:53:16 PM PDT 24 40746467614 ps
T70 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3728925711 Jul 14 06:51:48 PM PDT 24 Jul 14 06:51:56 PM PDT 24 2038934705 ps
T71 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1175385081 Jul 14 06:52:06 PM PDT 24 Jul 14 06:52:18 PM PDT 24 3009267779 ps
T72 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2222387310 Jul 14 06:52:03 PM PDT 24 Jul 14 06:53:33 PM PDT 24 10952153965 ps
T59 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3290670369 Jul 14 06:51:47 PM PDT 24 Jul 14 06:52:28 PM PDT 24 2906781108 ps
T73 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2363940740 Jul 14 06:52:08 PM PDT 24 Jul 14 06:52:37 PM PDT 24 5590217010 ps
T74 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1272813204 Jul 14 06:52:04 PM PDT 24 Jul 14 06:52:16 PM PDT 24 5677684434 ps
T75 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4221053104 Jul 14 06:52:05 PM PDT 24 Jul 14 06:52:15 PM PDT 24 797853769 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.417230934 Jul 14 06:51:42 PM PDT 24 Jul 14 06:52:01 PM PDT 24 9109363155 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2216884076 Jul 14 06:51:43 PM PDT 24 Jul 14 06:52:01 PM PDT 24 10374876187 ps
T377 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2632927368 Jul 14 06:52:19 PM PDT 24 Jul 14 06:52:36 PM PDT 24 1303216988 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2612551616 Jul 14 06:52:05 PM PDT 24 Jul 14 06:52:16 PM PDT 24 217143471 ps
T76 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.936065537 Jul 14 06:51:53 PM PDT 24 Jul 14 06:52:01 PM PDT 24 835175616 ps
T121 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1024578755 Jul 14 06:51:54 PM PDT 24 Jul 14 06:53:05 PM PDT 24 1135661418 ps
T85 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.438624772 Jul 14 06:52:00 PM PDT 24 Jul 14 06:53:00 PM PDT 24 22745301899 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.628837035 Jul 14 06:52:03 PM PDT 24 Jul 14 06:53:28 PM PDT 24 24634355890 ps
T379 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2433749092 Jul 14 06:52:02 PM PDT 24 Jul 14 06:52:19 PM PDT 24 6250712244 ps
T380 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3332989893 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:08 PM PDT 24 89016602 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3975848152 Jul 14 06:51:43 PM PDT 24 Jul 14 06:52:02 PM PDT 24 3755113580 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.466076833 Jul 14 06:51:47 PM PDT 24 Jul 14 06:51:52 PM PDT 24 379047723 ps
T125 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2611699657 Jul 14 06:51:54 PM PDT 24 Jul 14 06:52:34 PM PDT 24 218013872 ps
T382 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1318251309 Jul 14 06:52:02 PM PDT 24 Jul 14 06:52:15 PM PDT 24 8843486163 ps
T383 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1292923005 Jul 14 06:51:49 PM PDT 24 Jul 14 06:52:04 PM PDT 24 6703888000 ps
T384 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1846788324 Jul 14 06:52:05 PM PDT 24 Jul 14 06:52:18 PM PDT 24 1430134673 ps
T385 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2250372220 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:17 PM PDT 24 883254817 ps
T386 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.176958437 Jul 14 06:51:55 PM PDT 24 Jul 14 06:52:03 PM PDT 24 111427592 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4042762742 Jul 14 06:51:46 PM PDT 24 Jul 14 06:51:52 PM PDT 24 253284084 ps
T388 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1135245807 Jul 14 06:52:10 PM PDT 24 Jul 14 06:52:26 PM PDT 24 4777001911 ps
T90 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4085946366 Jul 14 06:52:19 PM PDT 24 Jul 14 06:52:48 PM PDT 24 2077651890 ps
T389 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1480687412 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:15 PM PDT 24 1100212285 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.28737274 Jul 14 06:51:51 PM PDT 24 Jul 14 06:52:10 PM PDT 24 3493012925 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3904641018 Jul 14 06:51:50 PM PDT 24 Jul 14 06:51:59 PM PDT 24 3880450195 ps
T123 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2338100487 Jul 14 06:52:18 PM PDT 24 Jul 14 06:53:38 PM PDT 24 7943381443 ps
T109 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2526426904 Jul 14 06:52:02 PM PDT 24 Jul 14 06:52:12 PM PDT 24 1770021239 ps
T392 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2741502479 Jul 14 06:51:56 PM PDT 24 Jul 14 06:52:08 PM PDT 24 2844988667 ps
T87 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1248578352 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:10 PM PDT 24 2227972020 ps
T393 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2623343082 Jul 14 06:52:03 PM PDT 24 Jul 14 06:53:10 PM PDT 24 8588997803 ps
T127 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3360953475 Jul 14 06:51:55 PM PDT 24 Jul 14 06:53:08 PM PDT 24 747452147 ps
T110 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3283534351 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:20 PM PDT 24 11385944203 ps
T394 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3230445263 Jul 14 06:51:51 PM PDT 24 Jul 14 06:52:05 PM PDT 24 4118099813 ps
T395 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1122686673 Jul 14 06:51:52 PM PDT 24 Jul 14 06:52:03 PM PDT 24 553076674 ps
T396 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1009831736 Jul 14 06:51:55 PM PDT 24 Jul 14 06:52:08 PM PDT 24 1737065658 ps
T397 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2283017768 Jul 14 06:51:55 PM PDT 24 Jul 14 06:52:04 PM PDT 24 328090159 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1209485538 Jul 14 06:51:53 PM PDT 24 Jul 14 06:52:05 PM PDT 24 975579011 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1391779007 Jul 14 06:51:46 PM PDT 24 Jul 14 06:51:56 PM PDT 24 1240961557 ps
T399 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1443973641 Jul 14 06:51:51 PM PDT 24 Jul 14 06:51:56 PM PDT 24 165305517 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1389726907 Jul 14 06:51:50 PM PDT 24 Jul 14 06:52:04 PM PDT 24 4120794323 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2472557833 Jul 14 06:51:43 PM PDT 24 Jul 14 06:51:58 PM PDT 24 5570944194 ps
T402 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2228170686 Jul 14 06:51:55 PM PDT 24 Jul 14 06:52:11 PM PDT 24 1626535348 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.56955378 Jul 14 06:51:53 PM PDT 24 Jul 14 06:52:12 PM PDT 24 7937026765 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3630142945 Jul 14 06:51:45 PM PDT 24 Jul 14 06:52:51 PM PDT 24 32943790334 ps
T405 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1409703314 Jul 14 06:52:08 PM PDT 24 Jul 14 06:52:20 PM PDT 24 1999315429 ps
T406 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.718047581 Jul 14 06:52:07 PM PDT 24 Jul 14 06:52:25 PM PDT 24 5918297768 ps
T407 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2749442559 Jul 14 06:51:56 PM PDT 24 Jul 14 06:52:10 PM PDT 24 1251400202 ps
T129 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1119962544 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:44 PM PDT 24 1060641457 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3605111280 Jul 14 06:52:11 PM PDT 24 Jul 14 06:52:22 PM PDT 24 2936029938 ps
T128 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1364984603 Jul 14 06:52:00 PM PDT 24 Jul 14 06:52:38 PM PDT 24 663803316 ps
T409 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.457744610 Jul 14 06:52:05 PM PDT 24 Jul 14 06:52:19 PM PDT 24 1645790554 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1807829886 Jul 14 06:51:44 PM PDT 24 Jul 14 06:51:55 PM PDT 24 1370429470 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.795620797 Jul 14 06:51:44 PM PDT 24 Jul 14 06:51:57 PM PDT 24 5451399843 ps
T412 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4123371796 Jul 14 06:52:03 PM PDT 24 Jul 14 06:52:22 PM PDT 24 2254394716 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1305519879 Jul 14 06:51:43 PM PDT 24 Jul 14 06:52:04 PM PDT 24 1906362196 ps
T414 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.847940818 Jul 14 06:52:02 PM PDT 24 Jul 14 06:52:18 PM PDT 24 4626374250 ps
T415 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.701284980 Jul 14 06:52:18 PM PDT 24 Jul 14 06:53:07 PM PDT 24 7611199306 ps
T416 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.691733507 Jul 14 06:52:02 PM PDT 24 Jul 14 06:52:42 PM PDT 24 177009270 ps
T417 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1421665647 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:21 PM PDT 24 3852178880 ps
T126 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1276400041 Jul 14 06:51:47 PM PDT 24 Jul 14 06:52:27 PM PDT 24 240100692 ps
T418 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4158144454 Jul 14 06:52:08 PM PDT 24 Jul 14 06:52:14 PM PDT 24 379883921 ps
T419 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1764974930 Jul 14 06:52:06 PM PDT 24 Jul 14 06:52:18 PM PDT 24 4303137066 ps
T420 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.866969432 Jul 14 06:51:43 PM PDT 24 Jul 14 06:51:56 PM PDT 24 4812599746 ps
T421 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2047007113 Jul 14 06:52:02 PM PDT 24 Jul 14 06:52:12 PM PDT 24 439272349 ps
T422 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2812400423 Jul 14 06:51:51 PM PDT 24 Jul 14 06:52:07 PM PDT 24 1837291874 ps
T423 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2724007976 Jul 14 06:52:07 PM PDT 24 Jul 14 06:52:23 PM PDT 24 7821066611 ps
T424 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3495263764 Jul 14 06:52:19 PM PDT 24 Jul 14 06:52:30 PM PDT 24 773079859 ps
T425 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3129786843 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:49 PM PDT 24 5799086249 ps
T426 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.666512109 Jul 14 06:51:53 PM PDT 24 Jul 14 06:52:00 PM PDT 24 1371037870 ps
T427 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2802854437 Jul 14 06:52:03 PM PDT 24 Jul 14 06:52:22 PM PDT 24 3689625260 ps
T428 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2958951662 Jul 14 06:52:06 PM PDT 24 Jul 14 06:52:17 PM PDT 24 1023256919 ps
T429 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2767299882 Jul 14 06:51:54 PM PDT 24 Jul 14 06:52:01 PM PDT 24 168359743 ps
T89 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4020200262 Jul 14 06:51:52 PM PDT 24 Jul 14 06:52:55 PM PDT 24 15144648224 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3777311512 Jul 14 06:51:46 PM PDT 24 Jul 14 06:52:03 PM PDT 24 1784664965 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3474152671 Jul 14 06:51:45 PM PDT 24 Jul 14 06:52:00 PM PDT 24 7224817842 ps
T432 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3127719651 Jul 14 06:51:44 PM PDT 24 Jul 14 06:51:51 PM PDT 24 827516589 ps
T433 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4279756809 Jul 14 06:52:07 PM PDT 24 Jul 14 06:52:14 PM PDT 24 116114413 ps
T434 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3681062019 Jul 14 06:51:45 PM PDT 24 Jul 14 06:51:57 PM PDT 24 1015045764 ps
T435 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3374652932 Jul 14 06:52:07 PM PDT 24 Jul 14 06:52:19 PM PDT 24 10381607886 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2748548900 Jul 14 06:51:49 PM PDT 24 Jul 14 06:51:54 PM PDT 24 379757524 ps
T437 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3676456373 Jul 14 06:51:45 PM PDT 24 Jul 14 06:51:57 PM PDT 24 2165850759 ps
T438 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1843948604 Jul 14 06:52:06 PM PDT 24 Jul 14 06:52:18 PM PDT 24 1261775700 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1155738147 Jul 14 06:51:49 PM PDT 24 Jul 14 06:51:59 PM PDT 24 2795640325 ps
T91 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2897537755 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:31 PM PDT 24 618859584 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3174985525 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:08 PM PDT 24 87343788 ps
T441 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2879163238 Jul 14 06:52:05 PM PDT 24 Jul 14 06:52:51 PM PDT 24 1781712337 ps
T442 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2205622969 Jul 14 06:52:03 PM PDT 24 Jul 14 06:52:52 PM PDT 24 12278710207 ps
T124 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3466388930 Jul 14 06:51:49 PM PDT 24 Jul 14 06:53:03 PM PDT 24 4746738156 ps
T92 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2303021996 Jul 14 06:51:45 PM PDT 24 Jul 14 06:53:06 PM PDT 24 46836642478 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.710752816 Jul 14 06:51:54 PM PDT 24 Jul 14 06:52:40 PM PDT 24 1574489628 ps
T122 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1113443201 Jul 14 06:52:02 PM PDT 24 Jul 14 06:52:45 PM PDT 24 1599788788 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2676151493 Jul 14 06:51:46 PM PDT 24 Jul 14 06:51:58 PM PDT 24 4455836592 ps
T444 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.429943055 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:12 PM PDT 24 3038074009 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.756055657 Jul 14 06:51:49 PM PDT 24 Jul 14 06:53:10 PM PDT 24 34483507696 ps
T445 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3058210936 Jul 14 06:52:02 PM PDT 24 Jul 14 06:52:11 PM PDT 24 175489175 ps
T446 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3655544737 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:40 PM PDT 24 182286519 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1723857905 Jul 14 06:51:46 PM PDT 24 Jul 14 06:52:00 PM PDT 24 1527422216 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1620456407 Jul 14 06:51:52 PM PDT 24 Jul 14 06:53:25 PM PDT 24 67604626272 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2557385932 Jul 14 06:51:45 PM PDT 24 Jul 14 06:51:55 PM PDT 24 8192247024 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.230374530 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:10 PM PDT 24 213448744 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2432276257 Jul 14 06:51:44 PM PDT 24 Jul 14 06:52:00 PM PDT 24 8801486079 ps
T451 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2222055617 Jul 14 06:51:56 PM PDT 24 Jul 14 06:53:06 PM PDT 24 16388972873 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1499972916 Jul 14 06:51:43 PM PDT 24 Jul 14 06:51:57 PM PDT 24 1345402619 ps
T453 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3648067966 Jul 14 06:51:54 PM PDT 24 Jul 14 06:52:23 PM PDT 24 4076458255 ps
T454 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4090564378 Jul 14 06:51:55 PM PDT 24 Jul 14 06:52:06 PM PDT 24 100528393 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4108699801 Jul 14 06:51:45 PM PDT 24 Jul 14 06:51:53 PM PDT 24 751971375 ps
T97 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2877736562 Jul 14 06:51:54 PM PDT 24 Jul 14 06:52:08 PM PDT 24 1880883899 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.394909112 Jul 14 06:51:49 PM PDT 24 Jul 14 06:51:55 PM PDT 24 1028337047 ps
T95 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3477592778 Jul 14 06:52:03 PM PDT 24 Jul 14 06:52:10 PM PDT 24 85489224 ps
T457 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.964980842 Jul 14 06:52:07 PM PDT 24 Jul 14 06:52:13 PM PDT 24 1651186193 ps
T119 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3839994003 Jul 14 06:51:58 PM PDT 24 Jul 14 06:52:39 PM PDT 24 1480433605 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2562549564 Jul 14 06:51:43 PM PDT 24 Jul 14 06:52:33 PM PDT 24 2624192563 ps
T459 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1732019076 Jul 14 06:51:45 PM PDT 24 Jul 14 06:51:54 PM PDT 24 2553554247 ps
T460 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3845305531 Jul 14 06:51:46 PM PDT 24 Jul 14 06:51:59 PM PDT 24 1245030671 ps
T461 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1621811968 Jul 14 06:52:05 PM PDT 24 Jul 14 06:53:09 PM PDT 24 7440047389 ps
T120 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.59988350 Jul 14 06:52:10 PM PDT 24 Jul 14 06:53:30 PM PDT 24 4547801617 ps
T462 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3262354220 Jul 14 06:51:44 PM PDT 24 Jul 14 06:51:51 PM PDT 24 87212553 ps
T463 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.864363247 Jul 14 06:51:42 PM PDT 24 Jul 14 06:51:54 PM PDT 24 7322061851 ps
T464 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2634246898 Jul 14 06:52:01 PM PDT 24 Jul 14 06:52:18 PM PDT 24 18983445914 ps
T465 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2807826828 Jul 14 06:52:09 PM PDT 24 Jul 14 06:52:16 PM PDT 24 93036206 ps
T466 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4159299733 Jul 14 06:51:56 PM PDT 24 Jul 14 06:52:07 PM PDT 24 1549051777 ps
T467 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1414875875 Jul 14 06:51:45 PM PDT 24 Jul 14 06:52:26 PM PDT 24 1774324834 ps
T468 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.243970496 Jul 14 06:51:45 PM PDT 24 Jul 14 06:51:55 PM PDT 24 696081984 ps

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3627764298
Short name T7
Test name
Test status
Simulation time 10928269040 ps
CPU time 209.68 seconds
Started Jul 14 06:50:26 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 225248 kb
Host smart-ce02b6ed-0e1e-45b9-bc6b-b328fba51f53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627764298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3627764298
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.630253602
Short name T12
Test name
Test status
Simulation time 88244291275 ps
CPU time 1304.32 seconds
Started Jul 14 06:51:31 PM PDT 24
Finished Jul 14 07:13:16 PM PDT 24
Peak memory 235840 kb
Host smart-466a8954-6a55-46c6-9358-8a2455867c7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630253602 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.630253602
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.532490604
Short name T57
Test name
Test status
Simulation time 1742861574 ps
CPU time 74.61 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:53:18 PM PDT 24
Peak memory 218884 kb
Host smart-7e735fcd-7e6e-4418-9d2f-7600485c636f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532490604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.532490604
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3728571184
Short name T36
Test name
Test status
Simulation time 93020806913 ps
CPU time 229.82 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:55:28 PM PDT 24
Peak memory 232868 kb
Host smart-ee988017-511f-4c55-8673-fe7a33388e0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728571184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3728571184
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.155440332
Short name T50
Test name
Test status
Simulation time 754952437709 ps
CPU time 2351.52 seconds
Started Jul 14 06:51:19 PM PDT 24
Finished Jul 14 07:30:32 PM PDT 24
Peak memory 238492 kb
Host smart-eb61daba-9390-4ae9-8f8b-dbaa7b400df9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155440332 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.155440332
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3842411447
Short name T23
Test name
Test status
Simulation time 205533497 ps
CPU time 99.78 seconds
Started Jul 14 06:50:26 PM PDT 24
Finished Jul 14 06:52:07 PM PDT 24
Peak memory 236348 kb
Host smart-2e240502-f6f5-4c0f-a12c-d125d87652bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842411447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3842411447
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2222387310
Short name T72
Test name
Test status
Simulation time 10952153965 ps
CPU time 87.91 seconds
Started Jul 14 06:52:03 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 210872 kb
Host smart-615b4714-ac1f-4784-85c5-709731f1b9ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222387310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2222387310
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1354285089
Short name T10
Test name
Test status
Simulation time 168268958 ps
CPU time 4.35 seconds
Started Jul 14 06:50:43 PM PDT 24
Finished Jul 14 06:50:49 PM PDT 24
Peak memory 211340 kb
Host smart-136f5609-23b0-436f-aed8-b5034551172b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354285089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1354285089
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2338100487
Short name T123
Test name
Test status
Simulation time 7943381443 ps
CPU time 77.94 seconds
Started Jul 14 06:52:18 PM PDT 24
Finished Jul 14 06:53:38 PM PDT 24
Peak memory 219020 kb
Host smart-9672c0f8-8ee9-4d30-b7ed-15a4d31db5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338100487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2338100487
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2616109279
Short name T49
Test name
Test status
Simulation time 324995799763 ps
CPU time 3119.23 seconds
Started Jul 14 06:51:21 PM PDT 24
Finished Jul 14 07:43:22 PM PDT 24
Peak memory 242824 kb
Host smart-79707538-ac2e-4786-bfe6-f8f41f1194b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616109279 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2616109279
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2303021996
Short name T92
Test name
Test status
Simulation time 46836642478 ps
CPU time 79.9 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:53:06 PM PDT 24
Peak memory 210828 kb
Host smart-fd21db05-0e3d-4993-9ee8-01ed9331f6e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303021996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2303021996
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1867196800
Short name T11
Test name
Test status
Simulation time 462459272 ps
CPU time 5.57 seconds
Started Jul 14 06:51:09 PM PDT 24
Finished Jul 14 06:51:16 PM PDT 24
Peak memory 211356 kb
Host smart-a528c869-a6b7-4eab-a1b3-c68d7921a8ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867196800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1867196800
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2778194549
Short name T148
Test name
Test status
Simulation time 1922448743 ps
CPU time 19.91 seconds
Started Jul 14 06:50:26 PM PDT 24
Finished Jul 14 06:50:47 PM PDT 24
Peak memory 211920 kb
Host smart-f0b02c82-c863-463d-a339-156056cad5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778194549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2778194549
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1609761769
Short name T280
Test name
Test status
Simulation time 334504258 ps
CPU time 9.79 seconds
Started Jul 14 06:50:51 PM PDT 24
Finished Jul 14 06:51:02 PM PDT 24
Peak memory 211908 kb
Host smart-08c992a4-59be-498e-a8ba-bc967b1ebfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609761769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1609761769
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1113443201
Short name T122
Test name
Test status
Simulation time 1599788788 ps
CPU time 40.81 seconds
Started Jul 14 06:52:02 PM PDT 24
Finished Jul 14 06:52:45 PM PDT 24
Peak memory 212160 kb
Host smart-384f72d9-f070-447a-80bb-cf3f6fac82a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113443201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1113443201
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.59988350
Short name T120
Test name
Test status
Simulation time 4547801617 ps
CPU time 79.47 seconds
Started Jul 14 06:52:10 PM PDT 24
Finished Jul 14 06:53:30 PM PDT 24
Peak memory 219060 kb
Host smart-560b2e07-5b2b-44c3-8b81-bb6c63885880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59988350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_int
g_err.59988350
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1024578755
Short name T121
Test name
Test status
Simulation time 1135661418 ps
CPU time 69.19 seconds
Started Jul 14 06:51:54 PM PDT 24
Finished Jul 14 06:53:05 PM PDT 24
Peak memory 218936 kb
Host smart-96f58ac1-847f-440f-99db-c7bc0cba470d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024578755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1024578755
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3466388930
Short name T124
Test name
Test status
Simulation time 4746738156 ps
CPU time 73.27 seconds
Started Jul 14 06:51:49 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 219068 kb
Host smart-b82025b0-eb7a-4fce-9677-f71a6e1e16df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466388930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3466388930
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3383269614
Short name T42
Test name
Test status
Simulation time 53522779576 ps
CPU time 295.01 seconds
Started Jul 14 06:50:25 PM PDT 24
Finished Jul 14 06:55:21 PM PDT 24
Peak memory 212664 kb
Host smart-c60494f5-1ed9-434c-aa8c-b1f748b639c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383269614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3383269614
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.394598369
Short name T63
Test name
Test status
Simulation time 17549125463 ps
CPU time 39.43 seconds
Started Jul 14 06:50:44 PM PDT 24
Finished Jul 14 06:51:25 PM PDT 24
Peak memory 213884 kb
Host smart-76ad2a53-1274-467f-8fca-904f6cb94b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394598369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.394598369
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3230505238
Short name T98
Test name
Test status
Simulation time 7353825906 ps
CPU time 16.21 seconds
Started Jul 14 06:51:30 PM PDT 24
Finished Jul 14 06:51:47 PM PDT 24
Peak memory 211448 kb
Host smart-1c4ded9e-f282-46b9-aa6c-2502566292dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3230505238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3230505238
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2692492356
Short name T112
Test name
Test status
Simulation time 1677350608 ps
CPU time 13.68 seconds
Started Jul 14 06:51:44 PM PDT 24
Finished Jul 14 06:51:58 PM PDT 24
Peak memory 210728 kb
Host smart-6d52f138-a6ff-4d0e-980c-fd51c5c76cd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692492356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2692492356
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1222007190
Short name T17
Test name
Test status
Simulation time 41495361806 ps
CPU time 1423.44 seconds
Started Jul 14 06:51:01 PM PDT 24
Finished Jul 14 07:14:45 PM PDT 24
Peak memory 235840 kb
Host smart-c0a796ff-87f8-41df-b140-5aa57e3dc602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222007190 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1222007190
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2472557833
Short name T401
Test name
Test status
Simulation time 5570944194 ps
CPU time 13.03 seconds
Started Jul 14 06:51:43 PM PDT 24
Finished Jul 14 06:51:58 PM PDT 24
Peak memory 218740 kb
Host smart-0754c95e-f36f-4191-8009-7a784764e377
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472557833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2472557833
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2432276257
Short name T450
Test name
Test status
Simulation time 8801486079 ps
CPU time 15.75 seconds
Started Jul 14 06:51:44 PM PDT 24
Finished Jul 14 06:52:00 PM PDT 24
Peak memory 218976 kb
Host smart-b5259bb5-c6f3-4194-8f94-aeca2d13b007
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432276257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2432276257
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3975848152
Short name T86
Test name
Test status
Simulation time 3755113580 ps
CPU time 17.64 seconds
Started Jul 14 06:51:43 PM PDT 24
Finished Jul 14 06:52:02 PM PDT 24
Peak memory 218584 kb
Host smart-27b0d3ad-e698-4487-8d01-5031e476dade
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975848152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3975848152
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3845305531
Short name T460
Test name
Test status
Simulation time 1245030671 ps
CPU time 11.72 seconds
Started Jul 14 06:51:46 PM PDT 24
Finished Jul 14 06:51:59 PM PDT 24
Peak memory 219116 kb
Host smart-e4661ca4-9825-44b1-ac08-d5cbedcb7ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845305531 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3845305531
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3127719651
Short name T432
Test name
Test status
Simulation time 827516589 ps
CPU time 5.57 seconds
Started Jul 14 06:51:44 PM PDT 24
Finished Jul 14 06:51:51 PM PDT 24
Peak memory 210592 kb
Host smart-4ac70754-02a5-46de-b553-5bf9389cadc6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127719651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3127719651
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3676456373
Short name T437
Test name
Test status
Simulation time 2165850759 ps
CPU time 10.73 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:51:57 PM PDT 24
Peak memory 210252 kb
Host smart-d8677aab-1ad8-4733-90e0-9a931af2b533
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676456373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3676456373
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3630142945
Short name T404
Test name
Test status
Simulation time 32943790334 ps
CPU time 65.11 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:52:51 PM PDT 24
Peak memory 210872 kb
Host smart-9ba7f614-7352-4198-8875-3ab300a7d026
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630142945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3630142945
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.866969432
Short name T420
Test name
Test status
Simulation time 4812599746 ps
CPU time 11.18 seconds
Started Jul 14 06:51:43 PM PDT 24
Finished Jul 14 06:51:56 PM PDT 24
Peak memory 211168 kb
Host smart-93910f52-9bc3-4325-b617-d049c2964774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866969432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.866969432
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.56955378
Short name T403
Test name
Test status
Simulation time 7937026765 ps
CPU time 17.69 seconds
Started Jul 14 06:51:53 PM PDT 24
Finished Jul 14 06:52:12 PM PDT 24
Peak memory 219032 kb
Host smart-d1d8b84a-9321-41e4-8da4-e8e51b1b4cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56955378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.56955378
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2562549564
Short name T458
Test name
Test status
Simulation time 2624192563 ps
CPU time 49.74 seconds
Started Jul 14 06:51:43 PM PDT 24
Finished Jul 14 06:52:33 PM PDT 24
Peak memory 211792 kb
Host smart-0c66ee0c-10f2-494b-98ae-07cf5fea047c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562549564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2562549564
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1209485538
Short name T88
Test name
Test status
Simulation time 975579011 ps
CPU time 9.84 seconds
Started Jul 14 06:51:53 PM PDT 24
Finished Jul 14 06:52:05 PM PDT 24
Peak memory 218624 kb
Host smart-b2f7b30b-996d-4720-82bc-8d375393e337
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209485538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1209485538
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2216884076
Short name T376
Test name
Test status
Simulation time 10374876187 ps
CPU time 16.74 seconds
Started Jul 14 06:51:43 PM PDT 24
Finished Jul 14 06:52:01 PM PDT 24
Peak memory 218988 kb
Host smart-0e121e45-2980-44c1-bf7d-e481cdabe6d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216884076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2216884076
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3262354220
Short name T462
Test name
Test status
Simulation time 87212553 ps
CPU time 5.66 seconds
Started Jul 14 06:51:44 PM PDT 24
Finished Jul 14 06:51:51 PM PDT 24
Peak memory 210700 kb
Host smart-0b21379a-be46-42ca-a3f5-e4f71b10c88d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262354220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3262354220
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3474152671
Short name T431
Test name
Test status
Simulation time 7224817842 ps
CPU time 14.12 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:52:00 PM PDT 24
Peak memory 219036 kb
Host smart-986ebc9f-41d7-4c48-83ae-40d5e604c525
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474152671 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3474152671
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2557385932
Short name T448
Test name
Test status
Simulation time 8192247024 ps
CPU time 8.6 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:51:55 PM PDT 24
Peak memory 218932 kb
Host smart-65c4f5a8-b695-46cf-a993-6485f44ecc5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557385932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2557385932
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4042762742
Short name T387
Test name
Test status
Simulation time 253284084 ps
CPU time 4.21 seconds
Started Jul 14 06:51:46 PM PDT 24
Finished Jul 14 06:51:52 PM PDT 24
Peak memory 210604 kb
Host smart-075bc7d0-0698-45fe-8b04-cc29d62e5348
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042762742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4042762742
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.303365324
Short name T373
Test name
Test status
Simulation time 1763400256 ps
CPU time 14.71 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:52:01 PM PDT 24
Peak memory 210108 kb
Host smart-45054e28-029c-4fc6-9879-99bf63a46fe5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303365324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
303365324
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3488068761
Short name T69
Test name
Test status
Simulation time 1114252423 ps
CPU time 12.5 seconds
Started Jul 14 06:51:42 PM PDT 24
Finished Jul 14 06:51:55 PM PDT 24
Peak memory 210908 kb
Host smart-cb4286ae-2dc0-4ef1-a2f5-2039e12dc582
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488068761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3488068761
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.417230934
Short name T375
Test name
Test status
Simulation time 9109363155 ps
CPU time 17.97 seconds
Started Jul 14 06:51:42 PM PDT 24
Finished Jul 14 06:52:01 PM PDT 24
Peak memory 219068 kb
Host smart-93e483cd-5569-43dc-9d03-0d84e2c92c80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417230934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.417230934
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.710752816
Short name T443
Test name
Test status
Simulation time 1574489628 ps
CPU time 43.33 seconds
Started Jul 14 06:51:54 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 212188 kb
Host smart-d82d97be-9207-411c-a793-39c9e3aa1128
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710752816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.710752816
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3203808911
Short name T372
Test name
Test status
Simulation time 4193977271 ps
CPU time 16.01 seconds
Started Jul 14 06:51:56 PM PDT 24
Finished Jul 14 06:52:14 PM PDT 24
Peak memory 219036 kb
Host smart-45415a24-562d-4bcb-a79d-f4a3de7e817c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203808911 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3203808911
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4159299733
Short name T466
Test name
Test status
Simulation time 1549051777 ps
CPU time 9.09 seconds
Started Jul 14 06:51:56 PM PDT 24
Finished Jul 14 06:52:07 PM PDT 24
Peak memory 210704 kb
Host smart-6175d6c5-9533-4600-8187-50a0d5e11873
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159299733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4159299733
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3648067966
Short name T453
Test name
Test status
Simulation time 4076458255 ps
CPU time 26.35 seconds
Started Jul 14 06:51:54 PM PDT 24
Finished Jul 14 06:52:23 PM PDT 24
Peak memory 210796 kb
Host smart-bf6d54ce-d744-416c-bab9-a616c90493b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648067966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3648067966
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2526426904
Short name T109
Test name
Test status
Simulation time 1770021239 ps
CPU time 7.83 seconds
Started Jul 14 06:52:02 PM PDT 24
Finished Jul 14 06:52:12 PM PDT 24
Peak memory 218240 kb
Host smart-a2ce4b65-090c-4587-a681-6c5a7f5d7f8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526426904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2526426904
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2433749092
Short name T379
Test name
Test status
Simulation time 6250712244 ps
CPU time 14.69 seconds
Started Jul 14 06:52:02 PM PDT 24
Finished Jul 14 06:52:19 PM PDT 24
Peak memory 219060 kb
Host smart-e52e4e88-de71-40c4-bb59-728b3d6001b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433749092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2433749092
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.691733507
Short name T416
Test name
Test status
Simulation time 177009270 ps
CPU time 37.23 seconds
Started Jul 14 06:52:02 PM PDT 24
Finished Jul 14 06:52:42 PM PDT 24
Peak memory 212304 kb
Host smart-daee7d78-a153-4ea1-b7d8-b6b2a45ab93c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691733507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.691733507
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2133908750
Short name T60
Test name
Test status
Simulation time 437344995 ps
CPU time 5.61 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:09 PM PDT 24
Peak memory 219068 kb
Host smart-94f0e88b-93a6-4121-b99a-6350940e23a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133908750 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2133908750
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2877736562
Short name T97
Test name
Test status
Simulation time 1880883899 ps
CPU time 10.59 seconds
Started Jul 14 06:51:54 PM PDT 24
Finished Jul 14 06:52:08 PM PDT 24
Peak memory 218912 kb
Host smart-a6fbe345-c779-4898-875b-c80bf0a53ff1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877736562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2877736562
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.628837035
Short name T108
Test name
Test status
Simulation time 24634355890 ps
CPU time 82.63 seconds
Started Jul 14 06:52:03 PM PDT 24
Finished Jul 14 06:53:28 PM PDT 24
Peak memory 210860 kb
Host smart-fd0996e1-a3eb-4155-8508-c5b76f6b7d6b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628837035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.628837035
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2283017768
Short name T397
Test name
Test status
Simulation time 328090159 ps
CPU time 6.27 seconds
Started Jul 14 06:51:55 PM PDT 24
Finished Jul 14 06:52:04 PM PDT 24
Peak memory 218984 kb
Host smart-55ddbf26-ac45-41dc-b428-84fa4c12efb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283017768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2283017768
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1421665647
Short name T417
Test name
Test status
Simulation time 3852178880 ps
CPU time 17.45 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:21 PM PDT 24
Peak memory 219040 kb
Host smart-509e1f3d-924f-4bf8-bf50-ca44b36e74df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421665647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1421665647
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2611699657
Short name T125
Test name
Test status
Simulation time 218013872 ps
CPU time 37.08 seconds
Started Jul 14 06:51:54 PM PDT 24
Finished Jul 14 06:52:34 PM PDT 24
Peak memory 211184 kb
Host smart-5df5471e-ffba-48f0-8fab-5ceaf2373f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611699657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2611699657
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4158144454
Short name T418
Test name
Test status
Simulation time 379883921 ps
CPU time 4.81 seconds
Started Jul 14 06:52:08 PM PDT 24
Finished Jul 14 06:52:14 PM PDT 24
Peak memory 218952 kb
Host smart-6f7447f4-45be-49e7-aa1d-db2b56e58c09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158144454 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4158144454
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3477592778
Short name T95
Test name
Test status
Simulation time 85489224 ps
CPU time 4.29 seconds
Started Jul 14 06:52:03 PM PDT 24
Finished Jul 14 06:52:10 PM PDT 24
Peak memory 210680 kb
Host smart-814c9da5-02e9-4530-8561-cdeffbaedd6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477592778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3477592778
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2205622969
Short name T442
Test name
Test status
Simulation time 12278710207 ps
CPU time 47.07 seconds
Started Jul 14 06:52:03 PM PDT 24
Finished Jul 14 06:52:52 PM PDT 24
Peak memory 210848 kb
Host smart-057871fb-41b2-4309-a0e6-a69a6077ec31
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205622969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2205622969
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.847940818
Short name T414
Test name
Test status
Simulation time 4626374250 ps
CPU time 13.38 seconds
Started Jul 14 06:52:02 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 219032 kb
Host smart-9110fc0c-16b5-4e02-9b74-d0dcd7dab03c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847940818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.847940818
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.177082035
Short name T370
Test name
Test status
Simulation time 7819886866 ps
CPU time 18.63 seconds
Started Jul 14 06:52:03 PM PDT 24
Finished Jul 14 06:52:24 PM PDT 24
Peak memory 219084 kb
Host smart-ebc35030-97ed-4ee1-8f83-eed32e23ebd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177082035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.177082035
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3655544737
Short name T446
Test name
Test status
Simulation time 182286519 ps
CPU time 36.78 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 211012 kb
Host smart-7126cb8b-1f86-4922-a897-61cb1b4c1272
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655544737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3655544737
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1846788324
Short name T384
Test name
Test status
Simulation time 1430134673 ps
CPU time 11.99 seconds
Started Jul 14 06:52:05 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 219024 kb
Host smart-dac69a24-d1c5-4342-b5d3-5ee13f37f983
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846788324 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1846788324
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4221053104
Short name T75
Test name
Test status
Simulation time 797853769 ps
CPU time 8.83 seconds
Started Jul 14 06:52:05 PM PDT 24
Finished Jul 14 06:52:15 PM PDT 24
Peak memory 210708 kb
Host smart-5c5367dd-64d3-4985-807b-afb5c18f571e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221053104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4221053104
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2897537755
Short name T91
Test name
Test status
Simulation time 618859584 ps
CPU time 28.78 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:31 PM PDT 24
Peak memory 210720 kb
Host smart-e60ecb8a-3f04-44ba-b489-2447e7e445b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897537755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2897537755
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1272813204
Short name T74
Test name
Test status
Simulation time 5677684434 ps
CPU time 10.57 seconds
Started Jul 14 06:52:04 PM PDT 24
Finished Jul 14 06:52:16 PM PDT 24
Peak memory 211088 kb
Host smart-d6604637-9088-4f23-8a09-9eba4418e748
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272813204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1272813204
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1318251309
Short name T382
Test name
Test status
Simulation time 8843486163 ps
CPU time 10.52 seconds
Started Jul 14 06:52:02 PM PDT 24
Finished Jul 14 06:52:15 PM PDT 24
Peak memory 219056 kb
Host smart-e53421cf-e79b-4988-bf97-dc771045309f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318251309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1318251309
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2047007113
Short name T421
Test name
Test status
Simulation time 439272349 ps
CPU time 7.5 seconds
Started Jul 14 06:52:02 PM PDT 24
Finished Jul 14 06:52:12 PM PDT 24
Peak memory 219012 kb
Host smart-499e628b-5d0f-4a1e-b280-67e403421a0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047007113 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2047007113
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2958951662
Short name T428
Test name
Test status
Simulation time 1023256919 ps
CPU time 10.44 seconds
Started Jul 14 06:52:06 PM PDT 24
Finished Jul 14 06:52:17 PM PDT 24
Peak memory 210696 kb
Host smart-b1f32184-7307-487a-b717-ceaaaebd06b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958951662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2958951662
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1621811968
Short name T461
Test name
Test status
Simulation time 7440047389 ps
CPU time 63.23 seconds
Started Jul 14 06:52:05 PM PDT 24
Finished Jul 14 06:53:09 PM PDT 24
Peak memory 210760 kb
Host smart-54ebe768-1762-4f1f-853c-dd31d6172ae7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621811968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1621811968
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3283534351
Short name T110
Test name
Test status
Simulation time 11385944203 ps
CPU time 16.58 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:20 PM PDT 24
Peak memory 210904 kb
Host smart-c8595f98-121c-4c45-94b7-ecf584d582a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283534351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3283534351
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2634246898
Short name T464
Test name
Test status
Simulation time 18983445914 ps
CPU time 15.61 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 218984 kb
Host smart-c055bee6-9c33-42e2-924d-8e1631259605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634246898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2634246898
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1364984603
Short name T128
Test name
Test status
Simulation time 663803316 ps
CPU time 36.99 seconds
Started Jul 14 06:52:00 PM PDT 24
Finished Jul 14 06:52:38 PM PDT 24
Peak memory 212228 kb
Host smart-4e21a1cc-ce62-4e71-a7ea-c8e86833afb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364984603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1364984603
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4123371796
Short name T412
Test name
Test status
Simulation time 2254394716 ps
CPU time 16.49 seconds
Started Jul 14 06:52:03 PM PDT 24
Finished Jul 14 06:52:22 PM PDT 24
Peak memory 219072 kb
Host smart-d586631a-892b-433b-b44f-264a4197ac42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123371796 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4123371796
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.457744610
Short name T409
Test name
Test status
Simulation time 1645790554 ps
CPU time 13.46 seconds
Started Jul 14 06:52:05 PM PDT 24
Finished Jul 14 06:52:19 PM PDT 24
Peak memory 210772 kb
Host smart-c0ee54a8-da3f-4dff-806f-e582b3433c1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457744610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.457744610
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.429943055
Short name T444
Test name
Test status
Simulation time 3038074009 ps
CPU time 10.16 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:12 PM PDT 24
Peak memory 210896 kb
Host smart-086c7abb-ac11-4fad-a6aa-ce35912bde7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429943055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.429943055
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2612551616
Short name T378
Test name
Test status
Simulation time 217143471 ps
CPU time 10.04 seconds
Started Jul 14 06:52:05 PM PDT 24
Finished Jul 14 06:52:16 PM PDT 24
Peak memory 219000 kb
Host smart-893daf82-2208-482d-9bc0-ce40a5c64c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612551616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2612551616
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3495263764
Short name T424
Test name
Test status
Simulation time 773079859 ps
CPU time 9.63 seconds
Started Jul 14 06:52:19 PM PDT 24
Finished Jul 14 06:52:30 PM PDT 24
Peak memory 215176 kb
Host smart-b2a35ef2-c2ff-424a-80c1-b105347d2379
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495263764 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3495263764
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4069368563
Short name T111
Test name
Test status
Simulation time 132708787 ps
CPU time 5.16 seconds
Started Jul 14 06:52:03 PM PDT 24
Finished Jul 14 06:52:11 PM PDT 24
Peak memory 217692 kb
Host smart-a12f0294-4c8f-45ca-8e49-1f80410119f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069368563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4069368563
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2623343082
Short name T393
Test name
Test status
Simulation time 8588997803 ps
CPU time 65.06 seconds
Started Jul 14 06:52:03 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 210836 kb
Host smart-bd9a5222-5f2b-4ae1-b413-4bc9cbab5958
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623343082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2623343082
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2807826828
Short name T465
Test name
Test status
Simulation time 93036206 ps
CPU time 5.97 seconds
Started Jul 14 06:52:09 PM PDT 24
Finished Jul 14 06:52:16 PM PDT 24
Peak memory 218972 kb
Host smart-132188b8-7d02-45b2-9632-063640e55f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807826828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2807826828
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3058210936
Short name T445
Test name
Test status
Simulation time 175489175 ps
CPU time 6.52 seconds
Started Jul 14 06:52:02 PM PDT 24
Finished Jul 14 06:52:11 PM PDT 24
Peak memory 219016 kb
Host smart-afa815cb-8ad3-4787-b690-f3f9765d0730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058210936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3058210936
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2879163238
Short name T441
Test name
Test status
Simulation time 1781712337 ps
CPU time 45.23 seconds
Started Jul 14 06:52:05 PM PDT 24
Finished Jul 14 06:52:51 PM PDT 24
Peak memory 218956 kb
Host smart-90a11164-f7d5-4e62-b277-b9b35a1d3514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879163238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2879163238
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3605111280
Short name T408
Test name
Test status
Simulation time 2936029938 ps
CPU time 10.64 seconds
Started Jul 14 06:52:11 PM PDT 24
Finished Jul 14 06:52:22 PM PDT 24
Peak memory 219116 kb
Host smart-2773cf12-34e0-437b-9799-3f33858a2913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605111280 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3605111280
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1175385081
Short name T71
Test name
Test status
Simulation time 3009267779 ps
CPU time 11.51 seconds
Started Jul 14 06:52:06 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 210848 kb
Host smart-c2ba47c0-919a-4a3a-a609-5c10fbf8c72e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175385081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1175385081
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4085946366
Short name T90
Test name
Test status
Simulation time 2077651890 ps
CPU time 27.32 seconds
Started Jul 14 06:52:19 PM PDT 24
Finished Jul 14 06:52:48 PM PDT 24
Peak memory 210724 kb
Host smart-7139d51f-6e9b-4aae-828f-2837c614ea7d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085946366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4085946366
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.718047581
Short name T406
Test name
Test status
Simulation time 5918297768 ps
CPU time 17.19 seconds
Started Jul 14 06:52:07 PM PDT 24
Finished Jul 14 06:52:25 PM PDT 24
Peak memory 210984 kb
Host smart-6bb1ffd6-d21e-4b8e-b65e-0a167a8e7353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718047581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.718047581
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1409703314
Short name T405
Test name
Test status
Simulation time 1999315429 ps
CPU time 10.7 seconds
Started Jul 14 06:52:08 PM PDT 24
Finished Jul 14 06:52:20 PM PDT 24
Peak memory 219028 kb
Host smart-a422fc1c-5fc5-4cc6-8a4f-8cccded88358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409703314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1409703314
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3374652932
Short name T435
Test name
Test status
Simulation time 10381607886 ps
CPU time 11.16 seconds
Started Jul 14 06:52:07 PM PDT 24
Finished Jul 14 06:52:19 PM PDT 24
Peak memory 219060 kb
Host smart-89d2ffd7-f027-4034-8834-0a6749136b8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374652932 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3374652932
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.964980842
Short name T457
Test name
Test status
Simulation time 1651186193 ps
CPU time 4.32 seconds
Started Jul 14 06:52:07 PM PDT 24
Finished Jul 14 06:52:13 PM PDT 24
Peak memory 210708 kb
Host smart-06e51d17-da91-4995-a9f5-384328115fd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964980842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.964980842
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.817519691
Short name T68
Test name
Test status
Simulation time 27868716016 ps
CPU time 77.31 seconds
Started Jul 14 06:52:07 PM PDT 24
Finished Jul 14 06:53:25 PM PDT 24
Peak memory 210876 kb
Host smart-1a4134a1-5c35-4167-b136-45af16d242d4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817519691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.817519691
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2724007976
Short name T423
Test name
Test status
Simulation time 7821066611 ps
CPU time 15.04 seconds
Started Jul 14 06:52:07 PM PDT 24
Finished Jul 14 06:52:23 PM PDT 24
Peak memory 219016 kb
Host smart-3c083576-83b5-4837-b2c5-f5c289859740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724007976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2724007976
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2632927368
Short name T377
Test name
Test status
Simulation time 1303216988 ps
CPU time 15.82 seconds
Started Jul 14 06:52:19 PM PDT 24
Finished Jul 14 06:52:36 PM PDT 24
Peak memory 218920 kb
Host smart-2fa4dee0-fdcd-4d2b-b34a-af76bf0ee05f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632927368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2632927368
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.701284980
Short name T415
Test name
Test status
Simulation time 7611199306 ps
CPU time 46.81 seconds
Started Jul 14 06:52:18 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 211408 kb
Host smart-3046fe84-1ee6-4dbe-a625-722ce02a03d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701284980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.701284980
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4279756809
Short name T433
Test name
Test status
Simulation time 116114413 ps
CPU time 5.55 seconds
Started Jul 14 06:52:07 PM PDT 24
Finished Jul 14 06:52:14 PM PDT 24
Peak memory 215720 kb
Host smart-944d0b60-2d92-44ac-bb9a-3c07bfcd2ef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279756809 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.4279756809
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1843948604
Short name T438
Test name
Test status
Simulation time 1261775700 ps
CPU time 11.71 seconds
Started Jul 14 06:52:06 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 217856 kb
Host smart-9db902d1-424c-467a-9de4-3e1596970c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843948604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1843948604
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2363940740
Short name T73
Test name
Test status
Simulation time 5590217010 ps
CPU time 28.62 seconds
Started Jul 14 06:52:08 PM PDT 24
Finished Jul 14 06:52:37 PM PDT 24
Peak memory 210764 kb
Host smart-c5c92124-450b-4dad-ab14-a7f1a1eabe25
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363940740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2363940740
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1764974930
Short name T419
Test name
Test status
Simulation time 4303137066 ps
CPU time 10.94 seconds
Started Jul 14 06:52:06 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 210904 kb
Host smart-e87cee9f-d5c8-44db-9d2f-62c1e22b3b01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764974930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1764974930
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1135245807
Short name T388
Test name
Test status
Simulation time 4777001911 ps
CPU time 14.9 seconds
Started Jul 14 06:52:10 PM PDT 24
Finished Jul 14 06:52:26 PM PDT 24
Peak memory 219068 kb
Host smart-7a3b3b15-9a35-408b-b797-8ad9045e5382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135245807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1135245807
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2676151493
Short name T93
Test name
Test status
Simulation time 4455836592 ps
CPU time 11.41 seconds
Started Jul 14 06:51:46 PM PDT 24
Finished Jul 14 06:51:58 PM PDT 24
Peak memory 210772 kb
Host smart-e510699c-8331-4d85-b3a8-d91e4816b516
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676151493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2676151493
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.466076833
Short name T381
Test name
Test status
Simulation time 379047723 ps
CPU time 4.34 seconds
Started Jul 14 06:51:47 PM PDT 24
Finished Jul 14 06:51:52 PM PDT 24
Peak memory 217388 kb
Host smart-39c35502-0c7f-4ad6-a8fa-14f4dafcabb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466076833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.466076833
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3777311512
Short name T430
Test name
Test status
Simulation time 1784664965 ps
CPU time 15.92 seconds
Started Jul 14 06:51:46 PM PDT 24
Finished Jul 14 06:52:03 PM PDT 24
Peak memory 210588 kb
Host smart-7cc24253-c9d6-498c-9642-515be98bf6ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777311512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3777311512
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.795620797
Short name T411
Test name
Test status
Simulation time 5451399843 ps
CPU time 12.17 seconds
Started Jul 14 06:51:44 PM PDT 24
Finished Jul 14 06:51:57 PM PDT 24
Peak memory 219060 kb
Host smart-bf3b968b-57c1-418a-914e-f282fca0ecd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795620797 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.795620797
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.936065537
Short name T76
Test name
Test status
Simulation time 835175616 ps
CPU time 6.78 seconds
Started Jul 14 06:51:53 PM PDT 24
Finished Jul 14 06:52:01 PM PDT 24
Peak memory 210732 kb
Host smart-ae69b5e4-6db4-48ca-b0a2-92e71645ca23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936065537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.936065537
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1723857905
Short name T447
Test name
Test status
Simulation time 1527422216 ps
CPU time 13.05 seconds
Started Jul 14 06:51:46 PM PDT 24
Finished Jul 14 06:52:00 PM PDT 24
Peak memory 210588 kb
Host smart-8cdbb960-3399-490a-a9c5-81005a0e55b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723857905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1723857905
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1732019076
Short name T459
Test name
Test status
Simulation time 2553554247 ps
CPU time 7.93 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:51:54 PM PDT 24
Peak memory 210676 kb
Host smart-de4d6ac3-c5c5-41a1-8249-a8c2bd9d6cfe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732019076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1732019076
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4147190286
Short name T113
Test name
Test status
Simulation time 40746467614 ps
CPU time 91.47 seconds
Started Jul 14 06:51:43 PM PDT 24
Finished Jul 14 06:53:16 PM PDT 24
Peak memory 210836 kb
Host smart-e6e5448a-7711-4cd0-ae9b-efd5e8ed232d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147190286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4147190286
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.666512109
Short name T426
Test name
Test status
Simulation time 1371037870 ps
CPU time 6.43 seconds
Started Jul 14 06:51:53 PM PDT 24
Finished Jul 14 06:52:00 PM PDT 24
Peak memory 210728 kb
Host smart-f0ab9a27-7746-4fb8-a3e9-5fec173ff2b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666512109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.666512109
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1807829886
Short name T410
Test name
Test status
Simulation time 1370429470 ps
CPU time 9.78 seconds
Started Jul 14 06:51:44 PM PDT 24
Finished Jul 14 06:51:55 PM PDT 24
Peak memory 219008 kb
Host smart-91e009a8-7f65-422a-88fd-ef6e04d6ee68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807829886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1807829886
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1391779007
Short name T398
Test name
Test status
Simulation time 1240961557 ps
CPU time 8.64 seconds
Started Jul 14 06:51:46 PM PDT 24
Finished Jul 14 06:51:56 PM PDT 24
Peak memory 210772 kb
Host smart-c689c77b-bae1-4edc-bc73-52962f3ebd88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391779007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1391779007
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1499972916
Short name T452
Test name
Test status
Simulation time 1345402619 ps
CPU time 12.6 seconds
Started Jul 14 06:51:43 PM PDT 24
Finished Jul 14 06:51:57 PM PDT 24
Peak memory 217400 kb
Host smart-bbfa7212-491c-4e80-b279-9ef98a0da0c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499972916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1499972916
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.681862555
Short name T371
Test name
Test status
Simulation time 1004523228 ps
CPU time 11.99 seconds
Started Jul 14 06:51:44 PM PDT 24
Finished Jul 14 06:51:57 PM PDT 24
Peak memory 210704 kb
Host smart-90b490e9-9ab2-4420-bc9a-e151a1f40160
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681862555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.681862555
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.230374530
Short name T449
Test name
Test status
Simulation time 213448744 ps
CPU time 5.92 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:10 PM PDT 24
Peak memory 218816 kb
Host smart-ed64b51e-c520-4192-8eca-49b1c68619ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230374530 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.230374530
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.864363247
Short name T463
Test name
Test status
Simulation time 7322061851 ps
CPU time 11.14 seconds
Started Jul 14 06:51:42 PM PDT 24
Finished Jul 14 06:51:54 PM PDT 24
Peak memory 210844 kb
Host smart-16d9fa1b-b78e-46da-94a3-876445f768bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864363247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.864363247
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3681062019
Short name T434
Test name
Test status
Simulation time 1015045764 ps
CPU time 9.96 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:51:57 PM PDT 24
Peak memory 210608 kb
Host smart-2a3a32be-730d-44bb-8241-e82d0eb557f4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681062019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3681062019
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4108699801
Short name T455
Test name
Test status
Simulation time 751971375 ps
CPU time 6.56 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:51:53 PM PDT 24
Peak memory 210516 kb
Host smart-9bd8a767-0f10-4f91-815c-3b37be9631fb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108699801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4108699801
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1414875875
Short name T467
Test name
Test status
Simulation time 1774324834 ps
CPU time 38.77 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:52:26 PM PDT 24
Peak memory 210772 kb
Host smart-996ecab6-d457-48c2-bc7f-32e635311b3a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414875875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1414875875
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.243970496
Short name T468
Test name
Test status
Simulation time 696081984 ps
CPU time 8.65 seconds
Started Jul 14 06:51:45 PM PDT 24
Finished Jul 14 06:51:55 PM PDT 24
Peak memory 218464 kb
Host smart-a524d118-a4ce-40e8-9b69-17f081a787a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243970496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.243970496
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1305519879
Short name T413
Test name
Test status
Simulation time 1906362196 ps
CPU time 18.92 seconds
Started Jul 14 06:51:43 PM PDT 24
Finished Jul 14 06:52:04 PM PDT 24
Peak memory 219004 kb
Host smart-a3dfbacb-2d2e-4f3e-83b7-41342cac7b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305519879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1305519879
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3290670369
Short name T59
Test name
Test status
Simulation time 2906781108 ps
CPU time 40.14 seconds
Started Jul 14 06:51:47 PM PDT 24
Finished Jul 14 06:52:28 PM PDT 24
Peak memory 211908 kb
Host smart-025d5152-565b-4d7f-96fe-98dc2882ba9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290670369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3290670369
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3728925711
Short name T70
Test name
Test status
Simulation time 2038934705 ps
CPU time 7.31 seconds
Started Jul 14 06:51:48 PM PDT 24
Finished Jul 14 06:51:56 PM PDT 24
Peak memory 210768 kb
Host smart-133bcb81-0bed-4529-96f0-f6a8921bce27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728925711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3728925711
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3174985525
Short name T440
Test name
Test status
Simulation time 87343788 ps
CPU time 4.37 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:08 PM PDT 24
Peak memory 210592 kb
Host smart-cfa33ae8-0d69-486b-ab8d-915c3ec227e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174985525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3174985525
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4159055188
Short name T67
Test name
Test status
Simulation time 2629301751 ps
CPU time 14.78 seconds
Started Jul 14 06:51:49 PM PDT 24
Finished Jul 14 06:52:04 PM PDT 24
Peak memory 210848 kb
Host smart-bd6b6c30-a6d8-479b-a68b-9214dac7ef6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159055188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4159055188
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2748548900
Short name T436
Test name
Test status
Simulation time 379757524 ps
CPU time 4.58 seconds
Started Jul 14 06:51:49 PM PDT 24
Finished Jul 14 06:51:54 PM PDT 24
Peak memory 219060 kb
Host smart-57aca529-6c51-416d-95d6-25ee303dd8dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748548900 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2748548900
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1389726907
Short name T400
Test name
Test status
Simulation time 4120794323 ps
CPU time 13.28 seconds
Started Jul 14 06:51:50 PM PDT 24
Finished Jul 14 06:52:04 PM PDT 24
Peak memory 218820 kb
Host smart-d9664400-3fe4-41ed-b238-f242cd0d1d80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389726907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1389726907
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.394909112
Short name T456
Test name
Test status
Simulation time 1028337047 ps
CPU time 5.95 seconds
Started Jul 14 06:51:49 PM PDT 24
Finished Jul 14 06:51:55 PM PDT 24
Peak memory 210640 kb
Host smart-8247ae02-ece4-4b2f-8906-bb2e7abce232
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394909112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.394909112
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3904641018
Short name T391
Test name
Test status
Simulation time 3880450195 ps
CPU time 9.11 seconds
Started Jul 14 06:51:50 PM PDT 24
Finished Jul 14 06:51:59 PM PDT 24
Peak memory 210688 kb
Host smart-3d2b8d52-4edc-45a6-9b1a-0f9b85078c82
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904641018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3904641018
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1620456407
Short name T96
Test name
Test status
Simulation time 67604626272 ps
CPU time 91.45 seconds
Started Jul 14 06:51:52 PM PDT 24
Finished Jul 14 06:53:25 PM PDT 24
Peak memory 210876 kb
Host smart-9f930496-5aa6-456a-82cf-29861f87dd3f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620456407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1620456407
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1155738147
Short name T439
Test name
Test status
Simulation time 2795640325 ps
CPU time 9.1 seconds
Started Jul 14 06:51:49 PM PDT 24
Finished Jul 14 06:51:59 PM PDT 24
Peak memory 218364 kb
Host smart-021d5cb3-079d-431c-9a20-c4398b7286a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155738147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1155738147
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.28737274
Short name T390
Test name
Test status
Simulation time 3493012925 ps
CPU time 18.85 seconds
Started Jul 14 06:51:51 PM PDT 24
Finished Jul 14 06:52:10 PM PDT 24
Peak memory 219096 kb
Host smart-a26b117a-da90-41a3-9950-bcdfe3c98ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28737274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.28737274
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3762673850
Short name T374
Test name
Test status
Simulation time 763642624 ps
CPU time 9.49 seconds
Started Jul 14 06:51:54 PM PDT 24
Finished Jul 14 06:52:06 PM PDT 24
Peak memory 218916 kb
Host smart-868ca47a-6242-453e-bfc1-349911640534
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762673850 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3762673850
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2812400423
Short name T422
Test name
Test status
Simulation time 1837291874 ps
CPU time 15.06 seconds
Started Jul 14 06:51:51 PM PDT 24
Finished Jul 14 06:52:07 PM PDT 24
Peak memory 210708 kb
Host smart-3c21c703-d9fd-4371-9ce0-066e3b5bf219
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812400423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2812400423
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.756055657
Short name T94
Test name
Test status
Simulation time 34483507696 ps
CPU time 79.9 seconds
Started Jul 14 06:51:49 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 210732 kb
Host smart-ecfeecd7-2b3b-4b22-b713-d57b645021fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756055657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.756055657
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3418189971
Short name T62
Test name
Test status
Simulation time 2228115581 ps
CPU time 10.66 seconds
Started Jul 14 06:51:50 PM PDT 24
Finished Jul 14 06:52:01 PM PDT 24
Peak memory 219016 kb
Host smart-8e7bba2d-ec64-4f5a-8dcf-333769bfa679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418189971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3418189971
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3230445263
Short name T394
Test name
Test status
Simulation time 4118099813 ps
CPU time 12.91 seconds
Started Jul 14 06:51:51 PM PDT 24
Finished Jul 14 06:52:05 PM PDT 24
Peak memory 219088 kb
Host smart-c482d373-f79b-4848-a222-bac2a370a7a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230445263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3230445263
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1119962544
Short name T129
Test name
Test status
Simulation time 1060641457 ps
CPU time 40.89 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 218956 kb
Host smart-3b92a84e-01bb-4363-b9ce-a5d6ea9bec77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119962544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1119962544
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1292923005
Short name T383
Test name
Test status
Simulation time 6703888000 ps
CPU time 13.87 seconds
Started Jul 14 06:51:49 PM PDT 24
Finished Jul 14 06:52:04 PM PDT 24
Peak memory 219068 kb
Host smart-ef64e236-1f05-46ad-a843-6dd11ec78041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292923005 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1292923005
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1248578352
Short name T87
Test name
Test status
Simulation time 2227972020 ps
CPU time 7.61 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:10 PM PDT 24
Peak memory 217832 kb
Host smart-d4f9f394-566b-479f-b6df-7c92b1ebcbc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248578352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1248578352
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3129786843
Short name T425
Test name
Test status
Simulation time 5799086249 ps
CPU time 45.05 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:49 PM PDT 24
Peak memory 210820 kb
Host smart-169d3dbb-b451-4a4a-85b6-774f120febd8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129786843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3129786843
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1443973641
Short name T399
Test name
Test status
Simulation time 165305517 ps
CPU time 4.33 seconds
Started Jul 14 06:51:51 PM PDT 24
Finished Jul 14 06:51:56 PM PDT 24
Peak memory 218272 kb
Host smart-b5f4b8f5-cb81-45fe-8a65-b903bef04a81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443973641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1443973641
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2250372220
Short name T385
Test name
Test status
Simulation time 883254817 ps
CPU time 13.31 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:17 PM PDT 24
Peak memory 219000 kb
Host smart-73ad1284-0f5c-4ee5-92db-9abe401161dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250372220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2250372220
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1276400041
Short name T126
Test name
Test status
Simulation time 240100692 ps
CPU time 38.94 seconds
Started Jul 14 06:51:47 PM PDT 24
Finished Jul 14 06:52:27 PM PDT 24
Peak memory 218896 kb
Host smart-dd4d88e3-ee6a-40ac-b7de-1e7d0f89af9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276400041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1276400041
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.176958437
Short name T386
Test name
Test status
Simulation time 111427592 ps
CPU time 5.48 seconds
Started Jul 14 06:51:55 PM PDT 24
Finished Jul 14 06:52:03 PM PDT 24
Peak memory 219100 kb
Host smart-95fe0383-1792-40c0-a118-53306f1dea7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176958437 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.176958437
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2741502479
Short name T392
Test name
Test status
Simulation time 2844988667 ps
CPU time 9.99 seconds
Started Jul 14 06:51:56 PM PDT 24
Finished Jul 14 06:52:08 PM PDT 24
Peak memory 210860 kb
Host smart-b896c89e-9225-4038-811c-03b174b1ae9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741502479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2741502479
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4020200262
Short name T89
Test name
Test status
Simulation time 15144648224 ps
CPU time 61.55 seconds
Started Jul 14 06:51:52 PM PDT 24
Finished Jul 14 06:52:55 PM PDT 24
Peak memory 210828 kb
Host smart-7d80491e-0755-4cd6-8773-4ef39f1cd85c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020200262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.4020200262
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2228170686
Short name T402
Test name
Test status
Simulation time 1626535348 ps
CPU time 13.82 seconds
Started Jul 14 06:51:55 PM PDT 24
Finished Jul 14 06:52:11 PM PDT 24
Peak memory 210808 kb
Host smart-83ee3259-c878-4683-b069-539eb6951890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228170686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2228170686
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1122686673
Short name T395
Test name
Test status
Simulation time 553076674 ps
CPU time 9.7 seconds
Started Jul 14 06:51:52 PM PDT 24
Finished Jul 14 06:52:03 PM PDT 24
Peak memory 219044 kb
Host smart-fab44063-bd1a-4bdb-9e40-7e1b52d593fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122686673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1122686673
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3094572537
Short name T58
Test name
Test status
Simulation time 6813564425 ps
CPU time 46.12 seconds
Started Jul 14 06:52:03 PM PDT 24
Finished Jul 14 06:52:51 PM PDT 24
Peak memory 219016 kb
Host smart-719e4a3b-026b-4f62-b731-ef52ad2bd7f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094572537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3094572537
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1480687412
Short name T389
Test name
Test status
Simulation time 1100212285 ps
CPU time 10.92 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:15 PM PDT 24
Peak memory 219024 kb
Host smart-63616164-d623-44bf-8736-383092b612a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480687412 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1480687412
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3332989893
Short name T380
Test name
Test status
Simulation time 89016602 ps
CPU time 4.39 seconds
Started Jul 14 06:52:01 PM PDT 24
Finished Jul 14 06:52:08 PM PDT 24
Peak memory 210728 kb
Host smart-e1e2cf8d-c6d9-479f-91d3-fb269c5c5c01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332989893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3332989893
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2222055617
Short name T451
Test name
Test status
Simulation time 16388972873 ps
CPU time 67.56 seconds
Started Jul 14 06:51:56 PM PDT 24
Finished Jul 14 06:53:06 PM PDT 24
Peak memory 210788 kb
Host smart-a4d2e0e2-4eaf-4eaa-8374-0eb52d52efda
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222055617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2222055617
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2767299882
Short name T429
Test name
Test status
Simulation time 168359743 ps
CPU time 4.35 seconds
Started Jul 14 06:51:54 PM PDT 24
Finished Jul 14 06:52:01 PM PDT 24
Peak memory 210788 kb
Host smart-d0f3a84c-1f2c-48e8-9056-157573d2e55f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767299882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2767299882
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4090564378
Short name T454
Test name
Test status
Simulation time 100528393 ps
CPU time 7.83 seconds
Started Jul 14 06:51:55 PM PDT 24
Finished Jul 14 06:52:06 PM PDT 24
Peak memory 215492 kb
Host smart-02422db3-cad3-48a2-ab42-74dbaae0a043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090564378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.4090564378
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3839994003
Short name T119
Test name
Test status
Simulation time 1480433605 ps
CPU time 40.35 seconds
Started Jul 14 06:51:58 PM PDT 24
Finished Jul 14 06:52:39 PM PDT 24
Peak memory 218856 kb
Host smart-1ea63ac9-2f7b-4d2a-b143-8129d7747a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839994003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3839994003
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3087508726
Short name T61
Test name
Test status
Simulation time 12501413917 ps
CPU time 14.35 seconds
Started Jul 14 06:51:56 PM PDT 24
Finished Jul 14 06:52:13 PM PDT 24
Peak memory 219084 kb
Host smart-57420373-8e3c-46a2-8ef1-19e86f49740d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087508726 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3087508726
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1009831736
Short name T396
Test name
Test status
Simulation time 1737065658 ps
CPU time 10.75 seconds
Started Jul 14 06:51:55 PM PDT 24
Finished Jul 14 06:52:08 PM PDT 24
Peak memory 218936 kb
Host smart-d3c3d1d2-73b2-49bf-b372-ae38333e34b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009831736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1009831736
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.438624772
Short name T85
Test name
Test status
Simulation time 22745301899 ps
CPU time 59.01 seconds
Started Jul 14 06:52:00 PM PDT 24
Finished Jul 14 06:53:00 PM PDT 24
Peak memory 211720 kb
Host smart-0861eaf3-f954-44e5-932d-0eac9b4660ae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438624772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.438624772
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2749442559
Short name T407
Test name
Test status
Simulation time 1251400202 ps
CPU time 12.12 seconds
Started Jul 14 06:51:56 PM PDT 24
Finished Jul 14 06:52:10 PM PDT 24
Peak memory 210828 kb
Host smart-88b1782f-233d-4204-9a60-1c0e1cc87443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749442559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2749442559
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2802854437
Short name T427
Test name
Test status
Simulation time 3689625260 ps
CPU time 16.84 seconds
Started Jul 14 06:52:03 PM PDT 24
Finished Jul 14 06:52:22 PM PDT 24
Peak memory 219016 kb
Host smart-0ce1c1ef-f848-4b67-aca5-29f5f00bc8c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802854437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2802854437
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3360953475
Short name T127
Test name
Test status
Simulation time 747452147 ps
CPU time 70.72 seconds
Started Jul 14 06:51:55 PM PDT 24
Finished Jul 14 06:53:08 PM PDT 24
Peak memory 218984 kb
Host smart-8b5c8a34-e10f-41e1-ba6b-7ffce5d22f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360953475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3360953475
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.255962309
Short name T206
Test name
Test status
Simulation time 8867318752 ps
CPU time 17.17 seconds
Started Jul 14 06:50:22 PM PDT 24
Finished Jul 14 06:50:40 PM PDT 24
Peak memory 211376 kb
Host smart-14381ece-a486-4e60-8743-b1860f9c220a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255962309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.255962309
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3238284289
Short name T115
Test name
Test status
Simulation time 879908581 ps
CPU time 6.27 seconds
Started Jul 14 06:50:24 PM PDT 24
Finished Jul 14 06:50:31 PM PDT 24
Peak memory 211380 kb
Host smart-0ebcc3de-77a9-4133-921e-b315f463e9b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238284289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3238284289
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.592236476
Short name T26
Test name
Test status
Simulation time 139161800 ps
CPU time 52.09 seconds
Started Jul 14 06:50:23 PM PDT 24
Finished Jul 14 06:51:16 PM PDT 24
Peak memory 237700 kb
Host smart-b1ae8b1c-adae-47db-90d1-18831a47fed5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592236476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.592236476
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3607626600
Short name T213
Test name
Test status
Simulation time 4279651033 ps
CPU time 33.36 seconds
Started Jul 14 06:50:22 PM PDT 24
Finished Jul 14 06:50:55 PM PDT 24
Peak memory 213708 kb
Host smart-723be526-e483-4a67-9afa-2971bf2dae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607626600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3607626600
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2050705081
Short name T230
Test name
Test status
Simulation time 7595166721 ps
CPU time 19.63 seconds
Started Jul 14 06:50:27 PM PDT 24
Finished Jul 14 06:50:47 PM PDT 24
Peak memory 211404 kb
Host smart-71e173a1-63b4-4860-82d3-8c27ee992586
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050705081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2050705081
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2430007116
Short name T242
Test name
Test status
Simulation time 898324399 ps
CPU time 9.53 seconds
Started Jul 14 06:50:26 PM PDT 24
Finished Jul 14 06:50:36 PM PDT 24
Peak memory 211316 kb
Host smart-4eab2ca3-8723-440f-a892-1edbd4c174ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430007116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2430007116
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3697821094
Short name T160
Test name
Test status
Simulation time 8225645010 ps
CPU time 23.4 seconds
Started Jul 14 06:50:25 PM PDT 24
Finished Jul 14 06:50:49 PM PDT 24
Peak memory 212616 kb
Host smart-9221263b-b8f8-4a74-af76-a578ba655f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697821094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3697821094
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.582156067
Short name T360
Test name
Test status
Simulation time 2091953188 ps
CPU time 11.17 seconds
Started Jul 14 06:50:24 PM PDT 24
Finished Jul 14 06:50:36 PM PDT 24
Peak memory 211452 kb
Host smart-9e81e20a-b238-4218-b20a-34a5973b5fff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582156067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.582156067
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1174784478
Short name T258
Test name
Test status
Simulation time 15855632341 ps
CPU time 25.16 seconds
Started Jul 14 06:50:26 PM PDT 24
Finished Jul 14 06:50:52 PM PDT 24
Peak memory 214220 kb
Host smart-f03f5c52-931b-46bd-959c-742442f4d865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174784478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1174784478
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2069105787
Short name T28
Test name
Test status
Simulation time 216821276 ps
CPU time 13.07 seconds
Started Jul 14 06:50:24 PM PDT 24
Finished Jul 14 06:50:38 PM PDT 24
Peak memory 214264 kb
Host smart-6555f542-f228-41f3-b4a6-0c9b14eb4def
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069105787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2069105787
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2902961675
Short name T311
Test name
Test status
Simulation time 1668021087 ps
CPU time 7.4 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:50:51 PM PDT 24
Peak memory 211284 kb
Host smart-efc53f85-9e1d-43cf-9d87-deea81333cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902961675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2902961675
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.729707404
Short name T263
Test name
Test status
Simulation time 62938510141 ps
CPU time 279.72 seconds
Started Jul 14 06:50:47 PM PDT 24
Finished Jul 14 06:55:28 PM PDT 24
Peak memory 233056 kb
Host smart-c4bdb934-4418-4665-98e0-bf7eec36703a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729707404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.729707404
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2773399859
Short name T322
Test name
Test status
Simulation time 1934279345 ps
CPU time 20.09 seconds
Started Jul 14 06:50:44 PM PDT 24
Finished Jul 14 06:51:05 PM PDT 24
Peak memory 211916 kb
Host smart-efe73617-5dae-4a0d-8d04-8bbf5a6b4f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773399859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2773399859
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1248606103
Short name T228
Test name
Test status
Simulation time 1077056501 ps
CPU time 11.49 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:50:56 PM PDT 24
Peak memory 211368 kb
Host smart-6e97c7a5-9f83-4fa3-9ab7-8347e76aa10e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248606103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1248606103
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1081441286
Short name T303
Test name
Test status
Simulation time 1122431974 ps
CPU time 19.25 seconds
Started Jul 14 06:50:43 PM PDT 24
Finished Jul 14 06:51:04 PM PDT 24
Peak memory 213456 kb
Host smart-bce24a93-d738-4a74-8ed7-97b16000999f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081441286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1081441286
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2125409003
Short name T323
Test name
Test status
Simulation time 4519884139 ps
CPU time 32.45 seconds
Started Jul 14 06:50:41 PM PDT 24
Finished Jul 14 06:51:15 PM PDT 24
Peak memory 216752 kb
Host smart-b1be0fc2-fb14-4cbb-847f-f4a4e875a6b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125409003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2125409003
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2665988013
Short name T332
Test name
Test status
Simulation time 28687891280 ps
CPU time 4889.56 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 08:12:14 PM PDT 24
Peak memory 235840 kb
Host smart-7f39114c-f6be-44d4-82aa-128596ba1cbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665988013 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2665988013
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2839066079
Short name T106
Test name
Test status
Simulation time 141374502173 ps
CPU time 375.62 seconds
Started Jul 14 06:50:41 PM PDT 24
Finished Jul 14 06:56:57 PM PDT 24
Peak memory 228280 kb
Host smart-f421b38c-c5d0-424d-8b0a-8d3974ebbeca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839066079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2839066079
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2457919516
Short name T190
Test name
Test status
Simulation time 4317984087 ps
CPU time 35.81 seconds
Started Jul 14 06:50:44 PM PDT 24
Finished Jul 14 06:51:21 PM PDT 24
Peak memory 212152 kb
Host smart-e20b1e4a-b334-43f5-b2ba-483c59d1b9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457919516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2457919516
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2440157858
Short name T295
Test name
Test status
Simulation time 389829012 ps
CPU time 5.8 seconds
Started Jul 14 06:50:43 PM PDT 24
Finished Jul 14 06:50:50 PM PDT 24
Peak memory 211384 kb
Host smart-0208912c-7981-4ea2-93d9-60fae245e820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440157858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2440157858
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2980768962
Short name T146
Test name
Test status
Simulation time 15467565454 ps
CPU time 31.16 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:51:15 PM PDT 24
Peak memory 214192 kb
Host smart-963291e8-c5d9-4454-8214-3e7d62329a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980768962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2980768962
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2207797030
Short name T348
Test name
Test status
Simulation time 17920161936 ps
CPU time 82.34 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:52:06 PM PDT 24
Peak memory 217864 kb
Host smart-3e0a8668-1395-48d5-8cba-774976a0da72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207797030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2207797030
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3165240901
Short name T4
Test name
Test status
Simulation time 1335986167 ps
CPU time 6.62 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:50:51 PM PDT 24
Peak memory 211400 kb
Host smart-c845445c-34e6-44b0-8092-9b6d5b0d71fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165240901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3165240901
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.784021421
Short name T220
Test name
Test status
Simulation time 22938578979 ps
CPU time 261.41 seconds
Started Jul 14 06:50:41 PM PDT 24
Finished Jul 14 06:55:03 PM PDT 24
Peak memory 225852 kb
Host smart-5a0c9fd3-4902-4537-a911-45382de61086
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784021421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.784021421
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4201493412
Short name T369
Test name
Test status
Simulation time 3927612396 ps
CPU time 27.92 seconds
Started Jul 14 06:50:43 PM PDT 24
Finished Jul 14 06:51:12 PM PDT 24
Peak memory 212008 kb
Host smart-cc27a3d3-d4ac-4925-b5dc-7727adbf967b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201493412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4201493412
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2303552234
Short name T356
Test name
Test status
Simulation time 1543593338 ps
CPU time 13.94 seconds
Started Jul 14 06:50:41 PM PDT 24
Finished Jul 14 06:50:56 PM PDT 24
Peak memory 211368 kb
Host smart-69b25c55-ac7f-4769-9dd1-98a7020d0341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2303552234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2303552234
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2761718727
Short name T185
Test name
Test status
Simulation time 1270620574 ps
CPU time 21.59 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:51:05 PM PDT 24
Peak memory 214948 kb
Host smart-816cd334-e96c-43a1-a891-f23e2c149403
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761718727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2761718727
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4024857532
Short name T193
Test name
Test status
Simulation time 87412967 ps
CPU time 4.41 seconds
Started Jul 14 06:50:50 PM PDT 24
Finished Jul 14 06:50:55 PM PDT 24
Peak memory 211336 kb
Host smart-aabdf3e1-144d-42a0-ba6f-0f34b34f30f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024857532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4024857532
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2991996798
Short name T236
Test name
Test status
Simulation time 67881722443 ps
CPU time 186.43 seconds
Started Jul 14 06:50:44 PM PDT 24
Finished Jul 14 06:53:51 PM PDT 24
Peak memory 236764 kb
Host smart-ad56cb89-f020-4981-b6c1-9b05260bc6be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991996798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2991996798
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3716762391
Short name T174
Test name
Test status
Simulation time 40858481265 ps
CPU time 31.06 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:51:14 PM PDT 24
Peak memory 212192 kb
Host smart-0d5b80b2-c41a-4490-ac49-bcfd4897b105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716762391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3716762391
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3795646834
Short name T232
Test name
Test status
Simulation time 1809430803 ps
CPU time 7.06 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:50:51 PM PDT 24
Peak memory 211352 kb
Host smart-7575b467-5b13-4c1f-bca3-010bc24ae870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795646834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3795646834
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.856207371
Short name T21
Test name
Test status
Simulation time 193963143 ps
CPU time 10 seconds
Started Jul 14 06:50:44 PM PDT 24
Finished Jul 14 06:50:55 PM PDT 24
Peak memory 213456 kb
Host smart-431b46bf-c838-422f-8d63-61650c37472c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856207371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.856207371
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3174564431
Short name T141
Test name
Test status
Simulation time 757158725 ps
CPU time 11.58 seconds
Started Jul 14 06:50:43 PM PDT 24
Finished Jul 14 06:50:56 PM PDT 24
Peak memory 213660 kb
Host smart-03fd45f5-9587-4758-83a9-fb315ec0688b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174564431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3174564431
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1768630919
Short name T138
Test name
Test status
Simulation time 1213008701 ps
CPU time 11.77 seconds
Started Jul 14 06:50:50 PM PDT 24
Finished Jul 14 06:51:02 PM PDT 24
Peak memory 211340 kb
Host smart-15843247-f976-49f9-98db-e369a4eed2d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768630919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1768630919
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1583570777
Short name T286
Test name
Test status
Simulation time 2466951489 ps
CPU time 86.67 seconds
Started Jul 14 06:50:51 PM PDT 24
Finished Jul 14 06:52:19 PM PDT 24
Peak memory 237840 kb
Host smart-a81ccad9-6e8a-4a91-bd26-93a419891c66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583570777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1583570777
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.706464544
Short name T180
Test name
Test status
Simulation time 7844571918 ps
CPU time 21.93 seconds
Started Jul 14 06:50:48 PM PDT 24
Finished Jul 14 06:51:11 PM PDT 24
Peak memory 212516 kb
Host smart-df94d773-895e-4fcf-a9ff-618ec491f5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706464544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.706464544
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3693193137
Short name T239
Test name
Test status
Simulation time 302921630 ps
CPU time 7.61 seconds
Started Jul 14 06:50:48 PM PDT 24
Finished Jul 14 06:50:57 PM PDT 24
Peak memory 211352 kb
Host smart-0528b1a6-0603-4d56-b924-0208f2f0aff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693193137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3693193137
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1322551675
Short name T354
Test name
Test status
Simulation time 4458501626 ps
CPU time 39.12 seconds
Started Jul 14 06:50:47 PM PDT 24
Finished Jul 14 06:51:26 PM PDT 24
Peak memory 214180 kb
Host smart-a6534169-0f90-4ae5-bda2-8c853f7526da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322551675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1322551675
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1936038348
Short name T231
Test name
Test status
Simulation time 11229384286 ps
CPU time 61.76 seconds
Started Jul 14 06:50:49 PM PDT 24
Finished Jul 14 06:51:51 PM PDT 24
Peak memory 216816 kb
Host smart-857645e2-6525-470d-bf90-caeaf6b97787
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936038348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1936038348
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1833428805
Short name T298
Test name
Test status
Simulation time 2167000946 ps
CPU time 11.05 seconds
Started Jul 14 06:50:50 PM PDT 24
Finished Jul 14 06:51:02 PM PDT 24
Peak memory 211408 kb
Host smart-a46b3a2d-f980-47d8-961d-b6e701a145f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833428805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1833428805
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1215796456
Short name T327
Test name
Test status
Simulation time 151498719054 ps
CPU time 364.36 seconds
Started Jul 14 06:50:48 PM PDT 24
Finished Jul 14 06:56:54 PM PDT 24
Peak memory 237824 kb
Host smart-5c48b85f-0f34-4e4e-90f7-1c3dc032437f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215796456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1215796456
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4208929254
Short name T144
Test name
Test status
Simulation time 4193329453 ps
CPU time 8.48 seconds
Started Jul 14 06:50:53 PM PDT 24
Finished Jul 14 06:51:02 PM PDT 24
Peak memory 211444 kb
Host smart-e2b2a27f-bcdb-4618-b39a-c67dcf8ae5cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208929254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4208929254
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2039358841
Short name T202
Test name
Test status
Simulation time 5145197876 ps
CPU time 19.31 seconds
Started Jul 14 06:50:50 PM PDT 24
Finished Jul 14 06:51:10 PM PDT 24
Peak memory 213624 kb
Host smart-9d7d88c8-4a90-4877-9ec6-0dd2af39d8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039358841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2039358841
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1053763116
Short name T82
Test name
Test status
Simulation time 24266357373 ps
CPU time 58.66 seconds
Started Jul 14 06:50:48 PM PDT 24
Finished Jul 14 06:51:48 PM PDT 24
Peak memory 215704 kb
Host smart-76a052f7-2533-4d56-ab7b-b483de60f5d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053763116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1053763116
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1587344415
Short name T347
Test name
Test status
Simulation time 2257031640 ps
CPU time 11.49 seconds
Started Jul 14 06:50:49 PM PDT 24
Finished Jul 14 06:51:02 PM PDT 24
Peak memory 211396 kb
Host smart-1907645e-5d21-40b2-a754-464aa3654946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587344415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1587344415
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.609264195
Short name T350
Test name
Test status
Simulation time 17588101293 ps
CPU time 149.35 seconds
Started Jul 14 06:50:46 PM PDT 24
Finished Jul 14 06:53:15 PM PDT 24
Peak memory 234568 kb
Host smart-684b7608-8ff7-474f-b2a4-261090f4ae87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609264195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.609264195
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4072556010
Short name T142
Test name
Test status
Simulation time 5245266072 ps
CPU time 29.2 seconds
Started Jul 14 06:50:47 PM PDT 24
Finished Jul 14 06:51:17 PM PDT 24
Peak memory 212232 kb
Host smart-0754417b-7576-4fa3-88b2-3604a4edb33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072556010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4072556010
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.623832914
Short name T156
Test name
Test status
Simulation time 8982584139 ps
CPU time 17.5 seconds
Started Jul 14 06:50:49 PM PDT 24
Finished Jul 14 06:51:07 PM PDT 24
Peak memory 211380 kb
Host smart-9d3fec00-2b7f-4c5b-80a8-ba8f494436a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623832914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.623832914
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2083320293
Short name T204
Test name
Test status
Simulation time 3888185349 ps
CPU time 29.91 seconds
Started Jul 14 06:50:51 PM PDT 24
Finished Jul 14 06:51:22 PM PDT 24
Peak memory 213436 kb
Host smart-5af96755-6d54-49d1-8b72-30d8d32aa471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083320293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2083320293
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1779107483
Short name T336
Test name
Test status
Simulation time 13498631509 ps
CPU time 26.02 seconds
Started Jul 14 06:50:52 PM PDT 24
Finished Jul 14 06:51:18 PM PDT 24
Peak memory 214928 kb
Host smart-6d861c98-6652-4622-a853-9821b7d65626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779107483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1779107483
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1424107261
Short name T294
Test name
Test status
Simulation time 89029281 ps
CPU time 4.35 seconds
Started Jul 14 06:50:50 PM PDT 24
Finished Jul 14 06:50:55 PM PDT 24
Peak memory 211348 kb
Host smart-9cf9edf2-f4eb-4716-a72f-0a552ec5f130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424107261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1424107261
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2128166089
Short name T208
Test name
Test status
Simulation time 18643855436 ps
CPU time 155.4 seconds
Started Jul 14 06:50:50 PM PDT 24
Finished Jul 14 06:53:26 PM PDT 24
Peak memory 239880 kb
Host smart-0a74f87b-b61f-493c-b388-78dbb67bc87c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128166089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2128166089
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2343623856
Short name T225
Test name
Test status
Simulation time 5584766091 ps
CPU time 26.27 seconds
Started Jul 14 06:50:48 PM PDT 24
Finished Jul 14 06:51:16 PM PDT 24
Peak memory 212168 kb
Host smart-0e9d00a6-2906-465a-8a70-3f5519ba41be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343623856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2343623856
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4027897554
Short name T351
Test name
Test status
Simulation time 1972113425 ps
CPU time 15.56 seconds
Started Jul 14 06:50:49 PM PDT 24
Finished Jul 14 06:51:06 PM PDT 24
Peak memory 211316 kb
Host smart-b16cd6a6-00c9-471b-886a-6c6fb708fb1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027897554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4027897554
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.305197794
Short name T56
Test name
Test status
Simulation time 182011404 ps
CPU time 10.49 seconds
Started Jul 14 06:50:50 PM PDT 24
Finished Jul 14 06:51:01 PM PDT 24
Peak memory 213564 kb
Host smart-c5ce5f95-90ad-4c46-87c5-51aa09356a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305197794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.305197794
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3161985282
Short name T241
Test name
Test status
Simulation time 18708749109 ps
CPU time 41.23 seconds
Started Jul 14 06:50:50 PM PDT 24
Finished Jul 14 06:51:32 PM PDT 24
Peak memory 217024 kb
Host smart-d3d37026-77b5-4c57-9da2-cd72f1672961
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161985282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3161985282
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3954665473
Short name T53
Test name
Test status
Simulation time 55723626865 ps
CPU time 2133.64 seconds
Started Jul 14 06:50:48 PM PDT 24
Finished Jul 14 07:26:23 PM PDT 24
Peak memory 236104 kb
Host smart-81fa3681-0767-4369-948d-8cbb97d90596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954665473 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3954665473
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3978803170
Short name T288
Test name
Test status
Simulation time 812362234 ps
CPU time 9.16 seconds
Started Jul 14 06:50:56 PM PDT 24
Finished Jul 14 06:51:06 PM PDT 24
Peak memory 211252 kb
Host smart-ef55b712-016b-4d2e-86c7-cc5cdaafe86c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978803170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3978803170
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2038188920
Short name T13
Test name
Test status
Simulation time 34966793736 ps
CPU time 317.26 seconds
Started Jul 14 06:50:57 PM PDT 24
Finished Jul 14 06:56:15 PM PDT 24
Peak memory 236836 kb
Host smart-252c30e5-6f9c-4ab9-8a13-9e58de51da21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038188920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2038188920
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.654752104
Short name T318
Test name
Test status
Simulation time 1413565557 ps
CPU time 18.44 seconds
Started Jul 14 06:50:54 PM PDT 24
Finished Jul 14 06:51:14 PM PDT 24
Peak memory 215696 kb
Host smart-c8ce8160-5e40-4905-a690-8b6e50ad3d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654752104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.654752104
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1023955079
Short name T168
Test name
Test status
Simulation time 3730456497 ps
CPU time 10.4 seconds
Started Jul 14 06:50:50 PM PDT 24
Finished Jul 14 06:51:01 PM PDT 24
Peak memory 211392 kb
Host smart-b64d2378-174a-4543-93aa-faa6c484622c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023955079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1023955079
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2754094078
Short name T245
Test name
Test status
Simulation time 2990580741 ps
CPU time 29.38 seconds
Started Jul 14 06:50:48 PM PDT 24
Finished Jul 14 06:51:18 PM PDT 24
Peak memory 213064 kb
Host smart-5b457753-74ca-4886-8512-8b2e1a6f1abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754094078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2754094078
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3575286882
Short name T307
Test name
Test status
Simulation time 1266347289 ps
CPU time 22.87 seconds
Started Jul 14 06:50:51 PM PDT 24
Finished Jul 14 06:51:15 PM PDT 24
Peak memory 213648 kb
Host smart-0366d09b-903b-413b-8838-0bf07d3471ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575286882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3575286882
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1851573066
Short name T362
Test name
Test status
Simulation time 246770549 ps
CPU time 4.39 seconds
Started Jul 14 06:50:54 PM PDT 24
Finished Jul 14 06:50:59 PM PDT 24
Peak memory 211328 kb
Host smart-662061a0-d62c-4645-adde-9bfa1ae5007f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851573066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1851573066
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3093327392
Short name T367
Test name
Test status
Simulation time 85554747875 ps
CPU time 228.65 seconds
Started Jul 14 06:50:55 PM PDT 24
Finished Jul 14 06:54:45 PM PDT 24
Peak memory 228200 kb
Host smart-f156f3f3-0330-4256-abe7-653d1408e574
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093327392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3093327392
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4112542441
Short name T292
Test name
Test status
Simulation time 348056396 ps
CPU time 9.61 seconds
Started Jul 14 06:50:56 PM PDT 24
Finished Jul 14 06:51:07 PM PDT 24
Peak memory 211936 kb
Host smart-524f963e-7005-449e-af27-5206c1fedc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112542441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4112542441
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.974979181
Short name T306
Test name
Test status
Simulation time 7174941858 ps
CPU time 15.77 seconds
Started Jul 14 06:50:56 PM PDT 24
Finished Jul 14 06:51:13 PM PDT 24
Peak memory 211436 kb
Host smart-2dba64f0-3ae3-4308-b36b-754fe880a112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974979181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.974979181
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3901437861
Short name T261
Test name
Test status
Simulation time 756763624 ps
CPU time 10.53 seconds
Started Jul 14 06:50:55 PM PDT 24
Finished Jul 14 06:51:07 PM PDT 24
Peak memory 213808 kb
Host smart-b09291cc-90de-4902-9f94-0035e303691a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901437861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3901437861
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2755290959
Short name T300
Test name
Test status
Simulation time 422060855 ps
CPU time 14.11 seconds
Started Jul 14 06:50:55 PM PDT 24
Finished Jul 14 06:51:10 PM PDT 24
Peak memory 214420 kb
Host smart-9bbdc58d-f2b6-43f9-9b2a-8b084abca217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755290959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2755290959
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1168314925
Short name T145
Test name
Test status
Simulation time 89769112 ps
CPU time 4.29 seconds
Started Jul 14 06:50:33 PM PDT 24
Finished Jul 14 06:50:38 PM PDT 24
Peak memory 211304 kb
Host smart-a28bfede-57f7-434b-8e24-b4f7d9bb066d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168314925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1168314925
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1885007438
Short name T38
Test name
Test status
Simulation time 25213349599 ps
CPU time 132.17 seconds
Started Jul 14 06:50:30 PM PDT 24
Finished Jul 14 06:52:42 PM PDT 24
Peak memory 237824 kb
Host smart-72b6daa1-459c-4624-89f9-5869787cb938
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885007438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1885007438
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2405551798
Short name T184
Test name
Test status
Simulation time 1514852694 ps
CPU time 14.76 seconds
Started Jul 14 06:50:25 PM PDT 24
Finished Jul 14 06:50:40 PM PDT 24
Peak memory 212108 kb
Host smart-3db0d8ba-b0a5-4857-9c61-6fea390fdcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405551798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2405551798
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2422083162
Short name T149
Test name
Test status
Simulation time 1926946896 ps
CPU time 16.47 seconds
Started Jul 14 06:50:23 PM PDT 24
Finished Jul 14 06:50:40 PM PDT 24
Peak memory 211392 kb
Host smart-03e9fe54-37ec-447f-8324-4f3fa2700175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422083162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2422083162
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3041111482
Short name T25
Test name
Test status
Simulation time 1141996050 ps
CPU time 100.9 seconds
Started Jul 14 06:50:32 PM PDT 24
Finished Jul 14 06:52:14 PM PDT 24
Peak memory 236868 kb
Host smart-dbcb5baf-255d-4de7-bfc1-735d76d600d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041111482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3041111482
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3328529186
Short name T199
Test name
Test status
Simulation time 8942906850 ps
CPU time 30.58 seconds
Started Jul 14 06:50:24 PM PDT 24
Finished Jul 14 06:50:56 PM PDT 24
Peak memory 213416 kb
Host smart-85c16a94-5394-4534-8b3e-04c0b9e5b883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328529186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3328529186
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.787959190
Short name T77
Test name
Test status
Simulation time 1641515154 ps
CPU time 20.59 seconds
Started Jul 14 06:50:25 PM PDT 24
Finished Jul 14 06:50:46 PM PDT 24
Peak memory 213120 kb
Host smart-d6dc434f-c741-4ec9-a35a-18e457e82501
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787959190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.787959190
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3067043712
Short name T218
Test name
Test status
Simulation time 1274012107 ps
CPU time 11.43 seconds
Started Jul 14 06:50:56 PM PDT 24
Finished Jul 14 06:51:09 PM PDT 24
Peak memory 211360 kb
Host smart-d9d87d8d-ebe5-4f79-9109-0f01348e4b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067043712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3067043712
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1983624786
Short name T159
Test name
Test status
Simulation time 5914950969 ps
CPU time 140.29 seconds
Started Jul 14 06:50:55 PM PDT 24
Finished Jul 14 06:53:17 PM PDT 24
Peak memory 233740 kb
Host smart-f47d8887-02b0-4a36-b08a-9288fd25bf80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983624786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1983624786
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1100350068
Short name T9
Test name
Test status
Simulation time 755187823 ps
CPU time 9.37 seconds
Started Jul 14 06:50:52 PM PDT 24
Finished Jul 14 06:51:02 PM PDT 24
Peak memory 211816 kb
Host smart-c584610b-0015-44aa-843f-5f602205ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100350068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1100350068
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2890197539
Short name T179
Test name
Test status
Simulation time 2904381442 ps
CPU time 9.43 seconds
Started Jul 14 06:50:51 PM PDT 24
Finished Jul 14 06:51:01 PM PDT 24
Peak memory 211452 kb
Host smart-63c98202-f02d-4f83-a93a-bc8e3fdbcecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890197539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2890197539
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.562930697
Short name T285
Test name
Test status
Simulation time 4052314455 ps
CPU time 32.07 seconds
Started Jul 14 06:50:53 PM PDT 24
Finished Jul 14 06:51:26 PM PDT 24
Peak memory 213424 kb
Host smart-dd879e69-d949-4ad4-ac46-3f6f70ab7b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562930697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.562930697
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.698134734
Short name T270
Test name
Test status
Simulation time 4565264963 ps
CPU time 25.09 seconds
Started Jul 14 06:50:55 PM PDT 24
Finished Jul 14 06:51:21 PM PDT 24
Peak memory 216948 kb
Host smart-c6c6b1d1-6010-44a7-8beb-72f2ae3b98da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698134734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.698134734
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3538201816
Short name T116
Test name
Test status
Simulation time 9577803446 ps
CPU time 206.96 seconds
Started Jul 14 06:50:59 PM PDT 24
Finished Jul 14 06:54:26 PM PDT 24
Peak memory 231012 kb
Host smart-b9444739-3e06-4f94-9d0d-2205f655855d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538201816 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3538201816
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2537254457
Short name T349
Test name
Test status
Simulation time 333709524 ps
CPU time 4.28 seconds
Started Jul 14 06:50:58 PM PDT 24
Finished Jul 14 06:51:03 PM PDT 24
Peak memory 211308 kb
Host smart-7f4d8802-7aa8-4ee6-ac79-84f3ec6943f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537254457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2537254457
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.693918849
Short name T238
Test name
Test status
Simulation time 4348689373 ps
CPU time 132.63 seconds
Started Jul 14 06:50:55 PM PDT 24
Finished Jul 14 06:53:09 PM PDT 24
Peak memory 234884 kb
Host smart-3855d8b5-aa4b-438c-9a00-a914ff9630e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693918849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.693918849
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2409721958
Short name T191
Test name
Test status
Simulation time 1718221784 ps
CPU time 19.88 seconds
Started Jul 14 06:50:55 PM PDT 24
Finished Jul 14 06:51:17 PM PDT 24
Peak memory 211940 kb
Host smart-b419367d-fdfb-4fbd-89bb-511c8cc55df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409721958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2409721958
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.147697894
Short name T277
Test name
Test status
Simulation time 11803006183 ps
CPU time 14.59 seconds
Started Jul 14 06:50:53 PM PDT 24
Finished Jul 14 06:51:08 PM PDT 24
Peak memory 211456 kb
Host smart-e50b0683-4eb4-4925-a090-2ad055c5537e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147697894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.147697894
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3768435612
Short name T100
Test name
Test status
Simulation time 7981983200 ps
CPU time 22.16 seconds
Started Jul 14 06:50:55 PM PDT 24
Finished Jul 14 06:51:18 PM PDT 24
Peak memory 213548 kb
Host smart-060a15ff-4028-470a-96c7-a6eda5c331ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768435612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3768435612
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1051436548
Short name T79
Test name
Test status
Simulation time 2214438573 ps
CPU time 43.23 seconds
Started Jul 14 06:50:56 PM PDT 24
Finished Jul 14 06:51:41 PM PDT 24
Peak memory 215916 kb
Host smart-5c9c9d54-5997-4c50-b581-f3aae2a2d541
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051436548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1051436548
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4088822236
Short name T8
Test name
Test status
Simulation time 855912393 ps
CPU time 5.95 seconds
Started Jul 14 06:50:57 PM PDT 24
Finished Jul 14 06:51:04 PM PDT 24
Peak memory 211360 kb
Host smart-7e19cc04-2b7c-4dbd-8f21-944c8e03ffb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088822236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4088822236
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1504108524
Short name T222
Test name
Test status
Simulation time 87812693421 ps
CPU time 185.85 seconds
Started Jul 14 06:50:54 PM PDT 24
Finished Jul 14 06:54:02 PM PDT 24
Peak memory 212584 kb
Host smart-aa6c3783-7638-408f-948a-b53370773153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504108524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1504108524
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3813041585
Short name T173
Test name
Test status
Simulation time 8438781035 ps
CPU time 25.39 seconds
Started Jul 14 06:50:52 PM PDT 24
Finished Jul 14 06:51:18 PM PDT 24
Peak memory 212556 kb
Host smart-e5cfa155-d36e-4eeb-aed9-3da710b23764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813041585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3813041585
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.523672242
Short name T210
Test name
Test status
Simulation time 4141081755 ps
CPU time 14.8 seconds
Started Jul 14 06:50:58 PM PDT 24
Finished Jul 14 06:51:13 PM PDT 24
Peak memory 211460 kb
Host smart-eb5b349a-9a48-42c9-838e-79ddc4f2be17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=523672242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.523672242
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.66752905
Short name T192
Test name
Test status
Simulation time 17779464651 ps
CPU time 33.79 seconds
Started Jul 14 06:50:56 PM PDT 24
Finished Jul 14 06:51:31 PM PDT 24
Peak memory 213776 kb
Host smart-6e555e6f-8d51-4297-a938-ef9996cf09cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66752905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.66752905
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3054491220
Short name T194
Test name
Test status
Simulation time 4452724225 ps
CPU time 37.64 seconds
Started Jul 14 06:50:54 PM PDT 24
Finished Jul 14 06:51:32 PM PDT 24
Peak memory 213760 kb
Host smart-3d22b388-506f-44c9-937c-721717464dad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054491220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3054491220
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.261823703
Short name T216
Test name
Test status
Simulation time 1450110657 ps
CPU time 13.31 seconds
Started Jul 14 06:50:59 PM PDT 24
Finished Jul 14 06:51:13 PM PDT 24
Peak memory 211388 kb
Host smart-9f70e99d-5fb3-4a42-8b81-3ed2baec2577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261823703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.261823703
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2333520573
Short name T135
Test name
Test status
Simulation time 113493320876 ps
CPU time 273.83 seconds
Started Jul 14 06:51:03 PM PDT 24
Finished Jul 14 06:55:37 PM PDT 24
Peak memory 228296 kb
Host smart-f1d0b583-9357-487d-ba0f-95e885817323
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333520573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2333520573
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.823118783
Short name T5
Test name
Test status
Simulation time 5667332358 ps
CPU time 26.36 seconds
Started Jul 14 06:51:01 PM PDT 24
Finished Jul 14 06:51:28 PM PDT 24
Peak memory 212188 kb
Host smart-79ded48e-aa6d-4268-a321-545355c50cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823118783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.823118783
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.161913556
Short name T114
Test name
Test status
Simulation time 1554725770 ps
CPU time 14.79 seconds
Started Jul 14 06:50:59 PM PDT 24
Finished Jul 14 06:51:15 PM PDT 24
Peak memory 211400 kb
Host smart-fddad31c-d8dc-4756-8ac8-947276a9ef31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161913556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.161913556
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.311152318
Short name T176
Test name
Test status
Simulation time 2910983488 ps
CPU time 33.25 seconds
Started Jul 14 06:50:55 PM PDT 24
Finished Jul 14 06:51:30 PM PDT 24
Peak memory 214092 kb
Host smart-15b373dc-9ee2-474b-9ea3-72fad3e80c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311152318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.311152318
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.477877239
Short name T18
Test name
Test status
Simulation time 764683527 ps
CPU time 12.93 seconds
Started Jul 14 06:50:59 PM PDT 24
Finished Jul 14 06:51:13 PM PDT 24
Peak memory 215432 kb
Host smart-03bb5698-c40f-48c1-b061-e93dff75ccb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477877239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.477877239
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2533261712
Short name T47
Test name
Test status
Simulation time 1038115921 ps
CPU time 10.19 seconds
Started Jul 14 06:51:02 PM PDT 24
Finished Jul 14 06:51:13 PM PDT 24
Peak memory 211324 kb
Host smart-a02cca1b-38da-4e54-8dad-ffadcfb031ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533261712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2533261712
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1233766563
Short name T175
Test name
Test status
Simulation time 62474176700 ps
CPU time 164.6 seconds
Started Jul 14 06:51:00 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 233888 kb
Host smart-b2ef935f-9bb5-4f48-9f7f-656105ea073f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233766563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1233766563
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3082593995
Short name T359
Test name
Test status
Simulation time 2594207348 ps
CPU time 12.68 seconds
Started Jul 14 06:51:00 PM PDT 24
Finished Jul 14 06:51:14 PM PDT 24
Peak memory 212008 kb
Host smart-27e05dbc-3678-4add-812f-0a07e487fcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082593995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3082593995
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1426999786
Short name T165
Test name
Test status
Simulation time 181185205 ps
CPU time 5.54 seconds
Started Jul 14 06:51:00 PM PDT 24
Finished Jul 14 06:51:06 PM PDT 24
Peak memory 211352 kb
Host smart-f61720d5-c72b-43c0-80a6-aae470603dd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426999786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1426999786
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1362433294
Short name T189
Test name
Test status
Simulation time 366616805 ps
CPU time 10.15 seconds
Started Jul 14 06:51:10 PM PDT 24
Finished Jul 14 06:51:21 PM PDT 24
Peak memory 213300 kb
Host smart-2260e36a-d673-4310-b4c4-d827d7afe076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362433294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1362433294
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.632914723
Short name T84
Test name
Test status
Simulation time 25544777541 ps
CPU time 52.58 seconds
Started Jul 14 06:51:00 PM PDT 24
Finished Jul 14 06:51:53 PM PDT 24
Peak memory 219400 kb
Host smart-ea9e9f9d-6e26-4d76-9388-99d061f8181b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632914723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.632914723
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4122966514
Short name T276
Test name
Test status
Simulation time 1439809480 ps
CPU time 12.61 seconds
Started Jul 14 06:51:00 PM PDT 24
Finished Jul 14 06:51:13 PM PDT 24
Peak memory 211316 kb
Host smart-6e960c3d-11ae-417c-b547-418d84f23727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122966514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4122966514
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2829223096
Short name T297
Test name
Test status
Simulation time 56223486556 ps
CPU time 151.89 seconds
Started Jul 14 06:51:06 PM PDT 24
Finished Jul 14 06:53:38 PM PDT 24
Peak memory 228480 kb
Host smart-8d566a81-e931-4eaa-a16e-f53e212b8844
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829223096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2829223096
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.987965433
Short name T260
Test name
Test status
Simulation time 181114612 ps
CPU time 9.55 seconds
Started Jul 14 06:51:02 PM PDT 24
Finished Jul 14 06:51:12 PM PDT 24
Peak memory 212160 kb
Host smart-6af47545-3e0a-4da4-8bad-93714d1c9813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987965433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.987965433
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3265320799
Short name T65
Test name
Test status
Simulation time 100187579 ps
CPU time 5.98 seconds
Started Jul 14 06:51:01 PM PDT 24
Finished Jul 14 06:51:08 PM PDT 24
Peak memory 211368 kb
Host smart-26cfb247-f8de-4373-ae3c-4ad9255555a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265320799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3265320799
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3351016295
Short name T304
Test name
Test status
Simulation time 19520979240 ps
CPU time 34.9 seconds
Started Jul 14 06:51:00 PM PDT 24
Finished Jul 14 06:51:36 PM PDT 24
Peak memory 214320 kb
Host smart-b797a959-f01d-4825-8a65-a9be8e356726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351016295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3351016295
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1366172086
Short name T177
Test name
Test status
Simulation time 2876786474 ps
CPU time 35.4 seconds
Started Jul 14 06:50:59 PM PDT 24
Finished Jul 14 06:51:35 PM PDT 24
Peak memory 214812 kb
Host smart-36f7ab5e-5246-4e77-b561-41b085cf3e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366172086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1366172086
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2472267181
Short name T320
Test name
Test status
Simulation time 1871219323 ps
CPU time 14.18 seconds
Started Jul 14 06:51:10 PM PDT 24
Finished Jul 14 06:51:25 PM PDT 24
Peak memory 211352 kb
Host smart-b59379ec-0254-45de-9a64-85116ac132b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472267181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2472267181
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4190835414
Short name T39
Test name
Test status
Simulation time 93347603736 ps
CPU time 217.13 seconds
Started Jul 14 06:51:02 PM PDT 24
Finished Jul 14 06:54:40 PM PDT 24
Peak memory 234912 kb
Host smart-82673647-fb04-4585-9385-33be008570b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190835414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4190835414
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3621024129
Short name T45
Test name
Test status
Simulation time 321664943 ps
CPU time 9.57 seconds
Started Jul 14 06:51:08 PM PDT 24
Finished Jul 14 06:51:18 PM PDT 24
Peak memory 211968 kb
Host smart-4abbe4ca-397c-4899-8812-d32ad8e4ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621024129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3621024129
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.695037283
Short name T309
Test name
Test status
Simulation time 1850607854 ps
CPU time 15.16 seconds
Started Jul 14 06:51:07 PM PDT 24
Finished Jul 14 06:51:23 PM PDT 24
Peak memory 211404 kb
Host smart-2a987e22-3900-46a0-b69f-96edc2595524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695037283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.695037283
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.708732252
Short name T337
Test name
Test status
Simulation time 387086480 ps
CPU time 9.88 seconds
Started Jul 14 06:51:03 PM PDT 24
Finished Jul 14 06:51:14 PM PDT 24
Peak memory 212176 kb
Host smart-4b1b0be2-973b-4b8c-8381-69d98bcf412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708732252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.708732252
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3331435283
Short name T358
Test name
Test status
Simulation time 7286596080 ps
CPU time 45.05 seconds
Started Jul 14 06:51:02 PM PDT 24
Finished Jul 14 06:51:47 PM PDT 24
Peak memory 217644 kb
Host smart-e1085d65-e375-42f0-8493-06a9989f2647
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331435283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3331435283
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.198784097
Short name T103
Test name
Test status
Simulation time 313709065242 ps
CPU time 2859.99 seconds
Started Jul 14 06:51:07 PM PDT 24
Finished Jul 14 07:38:48 PM PDT 24
Peak memory 244028 kb
Host smart-fd8d1f53-131c-45e0-8bca-0bd5a0d9ba5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198784097 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.198784097
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.776305172
Short name T131
Test name
Test status
Simulation time 6121699049 ps
CPU time 8.9 seconds
Started Jul 14 06:51:08 PM PDT 24
Finished Jul 14 06:51:18 PM PDT 24
Peak memory 211376 kb
Host smart-ccf4d0ff-f7f3-449b-afdd-91d2a79b3c53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776305172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.776305172
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.105755329
Short name T136
Test name
Test status
Simulation time 64435221272 ps
CPU time 161.27 seconds
Started Jul 14 06:51:11 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 237608 kb
Host smart-5fd8199f-c6f0-4740-af82-8463e24c3ca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105755329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.105755329
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2671320853
Short name T365
Test name
Test status
Simulation time 4118153080 ps
CPU time 15.37 seconds
Started Jul 14 06:51:06 PM PDT 24
Finished Jul 14 06:51:22 PM PDT 24
Peak memory 211912 kb
Host smart-ce1cde47-781d-408c-9391-74439993c93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671320853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2671320853
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3643838669
Short name T316
Test name
Test status
Simulation time 333744413 ps
CPU time 5.33 seconds
Started Jul 14 06:51:11 PM PDT 24
Finished Jul 14 06:51:17 PM PDT 24
Peak memory 211392 kb
Host smart-e52ae50a-3ebd-44cf-b09b-95c2751c267d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643838669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3643838669
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2550251811
Short name T6
Test name
Test status
Simulation time 1317752400 ps
CPU time 17.41 seconds
Started Jul 14 06:51:09 PM PDT 24
Finished Jul 14 06:51:27 PM PDT 24
Peak memory 213172 kb
Host smart-6ca510c9-37f8-42f0-94bd-b68d2a291a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550251811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2550251811
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.881021591
Short name T247
Test name
Test status
Simulation time 23575877303 ps
CPU time 29.86 seconds
Started Jul 14 06:51:09 PM PDT 24
Finished Jul 14 06:51:40 PM PDT 24
Peak memory 215508 kb
Host smart-d5f459e8-44f1-491d-8fc4-764254ef298e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881021591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.881021591
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2344101671
Short name T254
Test name
Test status
Simulation time 2080254159 ps
CPU time 12.59 seconds
Started Jul 14 06:51:08 PM PDT 24
Finished Jul 14 06:51:22 PM PDT 24
Peak memory 211360 kb
Host smart-c1c9b3f3-91f4-425e-8318-7fc46f7e3ee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344101671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2344101671
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3635447862
Short name T268
Test name
Test status
Simulation time 37231412365 ps
CPU time 181.7 seconds
Started Jul 14 06:51:09 PM PDT 24
Finished Jul 14 06:54:12 PM PDT 24
Peak memory 238896 kb
Host smart-8e054d44-f782-481f-a960-c8b50aea977e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635447862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3635447862
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.127733352
Short name T368
Test name
Test status
Simulation time 1326769198 ps
CPU time 11.94 seconds
Started Jul 14 06:51:08 PM PDT 24
Finished Jul 14 06:51:21 PM PDT 24
Peak memory 212792 kb
Host smart-7aa5fe7d-a4d3-478e-9454-0216949cf7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127733352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.127733352
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.584539564
Short name T346
Test name
Test status
Simulation time 7522068618 ps
CPU time 16.04 seconds
Started Jul 14 06:51:11 PM PDT 24
Finished Jul 14 06:51:27 PM PDT 24
Peak memory 211464 kb
Host smart-46e9958c-9909-4978-968a-5c360948adaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584539564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.584539564
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2414592226
Short name T209
Test name
Test status
Simulation time 4058813699 ps
CPU time 33.2 seconds
Started Jul 14 06:51:07 PM PDT 24
Finished Jul 14 06:51:41 PM PDT 24
Peak memory 213452 kb
Host smart-0737c305-922a-48c2-a0a9-b3d74e035732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414592226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2414592226
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1400063958
Short name T274
Test name
Test status
Simulation time 2352610362 ps
CPU time 40.02 seconds
Started Jul 14 06:51:07 PM PDT 24
Finished Jul 14 06:51:48 PM PDT 24
Peak memory 216032 kb
Host smart-7fd41b10-15b5-42ff-8aa1-3ecefc7250fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400063958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1400063958
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3941674864
Short name T117
Test name
Test status
Simulation time 28224343254 ps
CPU time 762.54 seconds
Started Jul 14 06:51:10 PM PDT 24
Finished Jul 14 07:03:53 PM PDT 24
Peak memory 233520 kb
Host smart-21120a20-ed65-46e3-a51b-32cc0ad1a6f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941674864 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3941674864
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.321793274
Short name T55
Test name
Test status
Simulation time 85761089 ps
CPU time 4.36 seconds
Started Jul 14 06:51:09 PM PDT 24
Finished Jul 14 06:51:15 PM PDT 24
Peak memory 211276 kb
Host smart-b455ae49-aa64-47cb-a89b-f9de7440b1a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321793274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.321793274
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2541445951
Short name T27
Test name
Test status
Simulation time 11157911437 ps
CPU time 112.73 seconds
Started Jul 14 06:51:10 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 235284 kb
Host smart-6f0ee60c-42ab-42df-b313-2514d6962036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541445951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2541445951
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1761000621
Short name T200
Test name
Test status
Simulation time 9803157051 ps
CPU time 24.14 seconds
Started Jul 14 06:51:10 PM PDT 24
Finished Jul 14 06:51:35 PM PDT 24
Peak memory 212608 kb
Host smart-8359535d-c398-49d3-8fe3-dd502aeca074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761000621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1761000621
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3877484693
Short name T341
Test name
Test status
Simulation time 427898940 ps
CPU time 12.75 seconds
Started Jul 14 06:51:07 PM PDT 24
Finished Jul 14 06:51:21 PM PDT 24
Peak memory 213708 kb
Host smart-dcb1c6e8-43c1-46c0-acb6-2faa879b09e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877484693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3877484693
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.86066522
Short name T252
Test name
Test status
Simulation time 11205795652 ps
CPU time 93.36 seconds
Started Jul 14 06:51:08 PM PDT 24
Finished Jul 14 06:52:42 PM PDT 24
Peak memory 219388 kb
Host smart-2929c5f1-6b06-4f2b-953b-fdcad08b19f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86066522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.rom_ctrl_stress_all.86066522
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2487850264
Short name T140
Test name
Test status
Simulation time 7955539897 ps
CPU time 13.97 seconds
Started Jul 14 06:50:32 PM PDT 24
Finished Jul 14 06:50:47 PM PDT 24
Peak memory 211376 kb
Host smart-3648c770-9fea-4c37-b49f-f99e68648836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487850264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2487850264
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2178296600
Short name T229
Test name
Test status
Simulation time 457660737743 ps
CPU time 356.92 seconds
Started Jul 14 06:50:32 PM PDT 24
Finished Jul 14 06:56:30 PM PDT 24
Peak memory 228320 kb
Host smart-f6e3eefa-8629-410f-82c0-fef036ef3ff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178296600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2178296600
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1294252928
Short name T29
Test name
Test status
Simulation time 175545589 ps
CPU time 9.46 seconds
Started Jul 14 06:50:32 PM PDT 24
Finished Jul 14 06:50:43 PM PDT 24
Peak memory 212280 kb
Host smart-02b6c4bc-d99c-4fc9-987a-d59ccd0df20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294252928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1294252928
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2531592035
Short name T364
Test name
Test status
Simulation time 443776537 ps
CPU time 6.71 seconds
Started Jul 14 06:50:30 PM PDT 24
Finished Jul 14 06:50:37 PM PDT 24
Peak memory 211356 kb
Host smart-dbf5032c-2c22-4d68-94c1-d201b6e31e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531592035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2531592035
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3848527048
Short name T22
Test name
Test status
Simulation time 163070205 ps
CPU time 52.04 seconds
Started Jul 14 06:50:30 PM PDT 24
Finished Jul 14 06:51:23 PM PDT 24
Peak memory 237776 kb
Host smart-e737dbb4-e1cf-450e-ab1b-6e5765cbf34b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848527048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3848527048
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3737622232
Short name T335
Test name
Test status
Simulation time 3940756955 ps
CPU time 20.43 seconds
Started Jul 14 06:50:29 PM PDT 24
Finished Jul 14 06:50:50 PM PDT 24
Peak memory 213848 kb
Host smart-037c0793-8f3c-469c-99f1-0d54fad92139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737622232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3737622232
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2589719040
Short name T255
Test name
Test status
Simulation time 3182261746 ps
CPU time 23.26 seconds
Started Jul 14 06:50:30 PM PDT 24
Finished Jul 14 06:50:55 PM PDT 24
Peak memory 213684 kb
Host smart-a5826408-e60d-42bb-85a5-f475a84337f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589719040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2589719040
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.287896370
Short name T51
Test name
Test status
Simulation time 88352925565 ps
CPU time 876.67 seconds
Started Jul 14 06:50:30 PM PDT 24
Finished Jul 14 07:05:07 PM PDT 24
Peak memory 229092 kb
Host smart-7af24686-d10d-4b14-954f-625de72ff178
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287896370 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.287896370
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3512589036
Short name T157
Test name
Test status
Simulation time 4020880328 ps
CPU time 15.68 seconds
Started Jul 14 06:51:13 PM PDT 24
Finished Jul 14 06:51:29 PM PDT 24
Peak memory 211264 kb
Host smart-762b8de1-74c9-4f19-9191-0cfc8deaef84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512589036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3512589036
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2158842997
Short name T130
Test name
Test status
Simulation time 4577987608 ps
CPU time 140.45 seconds
Started Jul 14 06:51:15 PM PDT 24
Finished Jul 14 06:53:37 PM PDT 24
Peak memory 237836 kb
Host smart-63d81086-dd89-4751-bdcf-fd2b26ae825a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158842997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2158842997
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1491521557
Short name T167
Test name
Test status
Simulation time 680526909 ps
CPU time 14.13 seconds
Started Jul 14 06:51:14 PM PDT 24
Finished Jul 14 06:51:29 PM PDT 24
Peak memory 211960 kb
Host smart-f24d513f-4847-4e0b-95b8-28e033ba1e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491521557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1491521557
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2621260444
Short name T1
Test name
Test status
Simulation time 2068513509 ps
CPU time 17.27 seconds
Started Jul 14 06:51:14 PM PDT 24
Finished Jul 14 06:51:33 PM PDT 24
Peak memory 211416 kb
Host smart-2f3f7caa-cd9a-4986-ab1b-620c80b169ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621260444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2621260444
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3820580235
Short name T48
Test name
Test status
Simulation time 5621688736 ps
CPU time 19.03 seconds
Started Jul 14 06:51:14 PM PDT 24
Finished Jul 14 06:51:34 PM PDT 24
Peak memory 213580 kb
Host smart-5bd0f765-2c09-478f-aeb8-9756b2c892cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820580235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3820580235
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1349746292
Short name T338
Test name
Test status
Simulation time 4392576034 ps
CPU time 40.05 seconds
Started Jul 14 06:51:15 PM PDT 24
Finished Jul 14 06:51:56 PM PDT 24
Peak memory 215608 kb
Host smart-9104ab7c-ea86-41ec-a4b7-ffde068edcf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349746292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1349746292
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1148512698
Short name T64
Test name
Test status
Simulation time 876661129 ps
CPU time 9.82 seconds
Started Jul 14 06:51:16 PM PDT 24
Finished Jul 14 06:51:27 PM PDT 24
Peak memory 211348 kb
Host smart-9661b314-1a32-456b-96d0-cb41cf93c804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148512698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1148512698
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2027142065
Short name T166
Test name
Test status
Simulation time 12018314562 ps
CPU time 21.29 seconds
Started Jul 14 06:51:19 PM PDT 24
Finished Jul 14 06:51:40 PM PDT 24
Peak memory 212280 kb
Host smart-413ad156-2157-4a16-bcd9-4aec91af8017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027142065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2027142065
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4090538111
Short name T271
Test name
Test status
Simulation time 99428359 ps
CPU time 6.04 seconds
Started Jul 14 06:51:17 PM PDT 24
Finished Jul 14 06:51:24 PM PDT 24
Peak memory 211456 kb
Host smart-febc8a59-6c9a-4aa3-b84b-9229340e7548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090538111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4090538111
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1187009193
Short name T249
Test name
Test status
Simulation time 5829251173 ps
CPU time 28.98 seconds
Started Jul 14 06:51:19 PM PDT 24
Finished Jul 14 06:51:49 PM PDT 24
Peak memory 214140 kb
Host smart-de42cff2-9258-42b1-94a1-f482e309ebec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187009193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1187009193
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1716263748
Short name T31
Test name
Test status
Simulation time 3775956615 ps
CPU time 45.17 seconds
Started Jul 14 06:51:18 PM PDT 24
Finished Jul 14 06:52:04 PM PDT 24
Peak memory 215080 kb
Host smart-ac682265-ca71-4adf-b820-6559b1b93c84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716263748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1716263748
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1146429594
Short name T35
Test name
Test status
Simulation time 859328679 ps
CPU time 9.95 seconds
Started Jul 14 06:51:17 PM PDT 24
Finished Jul 14 06:51:27 PM PDT 24
Peak memory 211348 kb
Host smart-8af4e193-7225-47e6-8cd4-b57729e10e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146429594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1146429594
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3922319336
Short name T353
Test name
Test status
Simulation time 1021171218 ps
CPU time 72.61 seconds
Started Jul 14 06:51:14 PM PDT 24
Finished Jul 14 06:52:28 PM PDT 24
Peak memory 237312 kb
Host smart-7cb5e3d9-c3fc-4c32-95de-2ddd26da44b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922319336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3922319336
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2559288663
Short name T235
Test name
Test status
Simulation time 6868802919 ps
CPU time 29.91 seconds
Started Jul 14 06:51:13 PM PDT 24
Finished Jul 14 06:51:44 PM PDT 24
Peak memory 212280 kb
Host smart-005344d3-881b-4174-b459-40a806b8e747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559288663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2559288663
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.654469390
Short name T240
Test name
Test status
Simulation time 7983904978 ps
CPU time 13.46 seconds
Started Jul 14 06:51:11 PM PDT 24
Finished Jul 14 06:51:26 PM PDT 24
Peak memory 211412 kb
Host smart-4f95de16-2407-45ed-ac05-33d2afb9832d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654469390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.654469390
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.193652074
Short name T105
Test name
Test status
Simulation time 11121505914 ps
CPU time 17.29 seconds
Started Jul 14 06:51:18 PM PDT 24
Finished Jul 14 06:51:36 PM PDT 24
Peak memory 214388 kb
Host smart-12ec509a-2267-4af7-bfba-d867f9e0db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193652074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.193652074
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1078418584
Short name T80
Test name
Test status
Simulation time 14973330835 ps
CPU time 36.76 seconds
Started Jul 14 06:51:17 PM PDT 24
Finished Jul 14 06:51:54 PM PDT 24
Peak memory 219388 kb
Host smart-85004355-7915-4ae0-ab2f-3b60e63c44e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078418584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1078418584
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2249818644
Short name T226
Test name
Test status
Simulation time 8572433893 ps
CPU time 15.45 seconds
Started Jul 14 06:51:13 PM PDT 24
Finished Jul 14 06:51:30 PM PDT 24
Peak memory 211356 kb
Host smart-30a2318a-83f0-435a-85d4-38b70b0e7952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249818644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2249818644
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1662892961
Short name T342
Test name
Test status
Simulation time 1866206531 ps
CPU time 88.72 seconds
Started Jul 14 06:51:14 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 228616 kb
Host smart-23ab5580-522d-44fb-b883-5ab535f24fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662892961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1662892961
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2302931065
Short name T293
Test name
Test status
Simulation time 11950586202 ps
CPU time 28.01 seconds
Started Jul 14 06:51:13 PM PDT 24
Finished Jul 14 06:51:42 PM PDT 24
Peak memory 212432 kb
Host smart-45e21233-594e-40d1-8b93-2f9520f24925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302931065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2302931065
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.242190277
Short name T343
Test name
Test status
Simulation time 492352426 ps
CPU time 5.67 seconds
Started Jul 14 06:51:14 PM PDT 24
Finished Jul 14 06:51:21 PM PDT 24
Peak memory 211392 kb
Host smart-be547f4b-a9d5-440f-a97a-d3185c1d2894
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=242190277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.242190277
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3134931179
Short name T181
Test name
Test status
Simulation time 198249243 ps
CPU time 10.24 seconds
Started Jul 14 06:51:16 PM PDT 24
Finished Jul 14 06:51:27 PM PDT 24
Peak memory 213576 kb
Host smart-f6a82254-8173-4b7e-907a-da2148c8df3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134931179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3134931179
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3604959589
Short name T178
Test name
Test status
Simulation time 964666895 ps
CPU time 16.5 seconds
Started Jul 14 06:51:14 PM PDT 24
Finished Jul 14 06:51:32 PM PDT 24
Peak memory 214952 kb
Host smart-cbb7a7ea-862c-48ee-ae40-71444bd2be2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604959589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3604959589
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.646538339
Short name T275
Test name
Test status
Simulation time 13665828954 ps
CPU time 501.62 seconds
Started Jul 14 06:51:14 PM PDT 24
Finished Jul 14 06:59:37 PM PDT 24
Peak memory 228372 kb
Host smart-f56b77c1-9991-4bd5-98de-8132bb61c7fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646538339 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.646538339
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4261040328
Short name T312
Test name
Test status
Simulation time 830577703 ps
CPU time 4.23 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:51:28 PM PDT 24
Peak memory 211352 kb
Host smart-09a277c2-8f30-428d-9cf4-ad294ce23a4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261040328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4261040328
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3807973832
Short name T324
Test name
Test status
Simulation time 8843313217 ps
CPU time 163.61 seconds
Started Jul 14 06:51:19 PM PDT 24
Finished Jul 14 06:54:03 PM PDT 24
Peak memory 212676 kb
Host smart-469f3882-4e16-4c4b-8209-6bfdd49ca571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807973832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3807973832
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1976974909
Short name T2
Test name
Test status
Simulation time 2663249370 ps
CPU time 24.41 seconds
Started Jul 14 06:51:20 PM PDT 24
Finished Jul 14 06:51:46 PM PDT 24
Peak memory 212116 kb
Host smart-eba850dd-b44f-4d71-bbe2-e2ae5baf1c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976974909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1976974909
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.889774646
Short name T299
Test name
Test status
Simulation time 4683423216 ps
CPU time 12.32 seconds
Started Jul 14 06:51:20 PM PDT 24
Finished Jul 14 06:51:33 PM PDT 24
Peak memory 211448 kb
Host smart-b7898b99-516c-4508-9664-e8fef1feb733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889774646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.889774646
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2248789296
Short name T150
Test name
Test status
Simulation time 25681655432 ps
CPU time 22.71 seconds
Started Jul 14 06:51:14 PM PDT 24
Finished Jul 14 06:51:38 PM PDT 24
Peak memory 213928 kb
Host smart-4fdc977c-a7aa-4277-9d27-cc6c938be8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248789296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2248789296
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.453520705
Short name T326
Test name
Test status
Simulation time 6214949489 ps
CPU time 32.79 seconds
Started Jul 14 06:51:14 PM PDT 24
Finished Jul 14 06:51:47 PM PDT 24
Peak memory 214376 kb
Host smart-f2ff9e23-e0d2-453a-bed6-a2fad6881f36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453520705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.453520705
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1240068989
Short name T345
Test name
Test status
Simulation time 151487267790 ps
CPU time 2128.41 seconds
Started Jul 14 06:51:20 PM PDT 24
Finished Jul 14 07:26:50 PM PDT 24
Peak memory 235672 kb
Host smart-f1d3591b-037a-4799-afd5-b698b81c3d53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240068989 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1240068989
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3992532329
Short name T227
Test name
Test status
Simulation time 2315067047 ps
CPU time 11.52 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:51:35 PM PDT 24
Peak memory 211420 kb
Host smart-7d85858f-be5e-4f87-81a6-81c2dfd13191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992532329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3992532329
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1958966615
Short name T153
Test name
Test status
Simulation time 21282275017 ps
CPU time 206.32 seconds
Started Jul 14 06:51:21 PM PDT 24
Finished Jul 14 06:54:49 PM PDT 24
Peak memory 233888 kb
Host smart-3aee30f8-f1a5-46ff-b6be-9a3dd342ed9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958966615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1958966615
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3927222625
Short name T152
Test name
Test status
Simulation time 7593831965 ps
CPU time 28.97 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:51:53 PM PDT 24
Peak memory 212292 kb
Host smart-c27b39f5-0d17-4134-aee2-57013e4e626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927222625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3927222625
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2045420324
Short name T182
Test name
Test status
Simulation time 180988400 ps
CPU time 7.31 seconds
Started Jul 14 06:51:19 PM PDT 24
Finished Jul 14 06:51:27 PM PDT 24
Peak memory 211348 kb
Host smart-ed710eab-c1ad-4e19-a28a-8d7be7b37096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045420324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2045420324
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3568542744
Short name T262
Test name
Test status
Simulation time 10518110307 ps
CPU time 24.75 seconds
Started Jul 14 06:51:20 PM PDT 24
Finished Jul 14 06:51:47 PM PDT 24
Peak memory 214112 kb
Host smart-201a76f3-164b-4b18-b540-e4c10e60ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568542744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3568542744
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1483907415
Short name T284
Test name
Test status
Simulation time 7414558807 ps
CPU time 35.56 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:51:59 PM PDT 24
Peak memory 219352 kb
Host smart-24a4a79f-bf98-4789-9260-35a1a23e3fd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483907415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1483907415
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4208985251
Short name T43
Test name
Test status
Simulation time 167760987 ps
CPU time 4.32 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:51:29 PM PDT 24
Peak memory 211352 kb
Host smart-d59852fb-9822-4aff-bbbd-e3f2bc3cecd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208985251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4208985251
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2327135199
Short name T217
Test name
Test status
Simulation time 56891359130 ps
CPU time 126.39 seconds
Started Jul 14 06:51:24 PM PDT 24
Finished Jul 14 06:53:32 PM PDT 24
Peak memory 228604 kb
Host smart-1c7ed7e9-3e33-4276-92ad-cf61e4819c83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327135199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2327135199
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2635854283
Short name T46
Test name
Test status
Simulation time 694859407 ps
CPU time 9.48 seconds
Started Jul 14 06:51:23 PM PDT 24
Finished Jul 14 06:51:34 PM PDT 24
Peak memory 211844 kb
Host smart-1532b104-62fc-4621-b72f-9a7d651ffd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635854283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2635854283
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2732027027
Short name T195
Test name
Test status
Simulation time 2224227214 ps
CPU time 17.99 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:51:42 PM PDT 24
Peak memory 211492 kb
Host smart-c75ad932-a9d5-4f46-9a34-3bcbd38dea63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2732027027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2732027027
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1359476876
Short name T233
Test name
Test status
Simulation time 6541205703 ps
CPU time 28.05 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:51:52 PM PDT 24
Peak memory 213980 kb
Host smart-aa3c3b91-e9d8-4a5e-944f-2f380480d504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359476876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1359476876
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1553085758
Short name T186
Test name
Test status
Simulation time 2224102358 ps
CPU time 37.83 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:52:02 PM PDT 24
Peak memory 214224 kb
Host smart-3b9388f9-bcc0-4ca1-b2b9-f3be93e2daff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553085758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1553085758
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2141248497
Short name T14
Test name
Test status
Simulation time 29779312109 ps
CPU time 1640.46 seconds
Started Jul 14 06:51:23 PM PDT 24
Finished Jul 14 07:18:45 PM PDT 24
Peak memory 235860 kb
Host smart-b33396ee-30d1-4912-a752-b2ec667afe65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141248497 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2141248497
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1227911102
Short name T155
Test name
Test status
Simulation time 4044965482 ps
CPU time 14.91 seconds
Started Jul 14 06:51:20 PM PDT 24
Finished Jul 14 06:51:36 PM PDT 24
Peak memory 211404 kb
Host smart-98ba9d08-2eac-407a-bfde-f60ee6d49d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227911102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1227911102
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2080095696
Short name T264
Test name
Test status
Simulation time 46740319599 ps
CPU time 312.53 seconds
Started Jul 14 06:51:21 PM PDT 24
Finished Jul 14 06:56:35 PM PDT 24
Peak memory 225320 kb
Host smart-348e297f-a0b8-4952-9246-134e6bde877f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080095696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2080095696
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3459622111
Short name T305
Test name
Test status
Simulation time 6072653401 ps
CPU time 17.31 seconds
Started Jul 14 06:51:23 PM PDT 24
Finished Jul 14 06:51:42 PM PDT 24
Peak memory 212808 kb
Host smart-910afb6c-5ff3-4186-9f29-90c9cedf01ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459622111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3459622111
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4248693967
Short name T198
Test name
Test status
Simulation time 1842733732 ps
CPU time 15.59 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:51:39 PM PDT 24
Peak memory 211396 kb
Host smart-34d930a0-0feb-48a0-b911-c6c1d1d42afd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4248693967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4248693967
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.921893163
Short name T214
Test name
Test status
Simulation time 2832291391 ps
CPU time 26.81 seconds
Started Jul 14 06:51:20 PM PDT 24
Finished Jul 14 06:51:49 PM PDT 24
Peak memory 213296 kb
Host smart-6db5669c-1ed0-44f9-a091-1b009e77116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921893163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.921893163
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3250279905
Short name T257
Test name
Test status
Simulation time 296010800 ps
CPU time 15.77 seconds
Started Jul 14 06:51:20 PM PDT 24
Finished Jul 14 06:51:37 PM PDT 24
Peak memory 215688 kb
Host smart-9dda875d-e776-4bff-a415-dc830b80663d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250279905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3250279905
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3529430335
Short name T253
Test name
Test status
Simulation time 565300960 ps
CPU time 7.52 seconds
Started Jul 14 06:51:31 PM PDT 24
Finished Jul 14 06:51:41 PM PDT 24
Peak memory 211292 kb
Host smart-3143f723-13c2-4150-9b27-c6817a5c688f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529430335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3529430335
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3394009893
Short name T250
Test name
Test status
Simulation time 3906538343 ps
CPU time 58.72 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:52:22 PM PDT 24
Peak memory 212628 kb
Host smart-36f6b5b5-aaf5-46ba-a8c6-0f1a144db0f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394009893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3394009893
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3713738419
Short name T139
Test name
Test status
Simulation time 7485638419 ps
CPU time 30.4 seconds
Started Jul 14 06:51:23 PM PDT 24
Finished Jul 14 06:51:55 PM PDT 24
Peak memory 212776 kb
Host smart-aade72f3-9789-47a6-9a04-e1886954c368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713738419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3713738419
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3979747801
Short name T102
Test name
Test status
Simulation time 1688828425 ps
CPU time 14.32 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:51:39 PM PDT 24
Peak memory 211332 kb
Host smart-4dbbb906-f9c8-4bb1-b6ec-24c5d1bfa780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979747801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3979747801
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2778764779
Short name T215
Test name
Test status
Simulation time 4180693039 ps
CPU time 17.75 seconds
Started Jul 14 06:51:21 PM PDT 24
Finished Jul 14 06:51:41 PM PDT 24
Peak memory 213572 kb
Host smart-1f3b6913-3086-4d0d-a5cd-102e8153cf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778764779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2778764779
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2677352356
Short name T291
Test name
Test status
Simulation time 704644551 ps
CPU time 21.7 seconds
Started Jul 14 06:51:22 PM PDT 24
Finished Jul 14 06:51:45 PM PDT 24
Peak memory 214976 kb
Host smart-8c766237-aebb-4a4a-8eb1-91aee96c21f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677352356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2677352356
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.532682113
Short name T169
Test name
Test status
Simulation time 130506264 ps
CPU time 4.28 seconds
Started Jul 14 06:51:30 PM PDT 24
Finished Jul 14 06:51:36 PM PDT 24
Peak memory 211268 kb
Host smart-aa056609-eda3-447a-9144-8454eb0bd952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532682113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.532682113
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.740663169
Short name T201
Test name
Test status
Simulation time 135939050010 ps
CPU time 245 seconds
Started Jul 14 06:51:29 PM PDT 24
Finished Jul 14 06:55:35 PM PDT 24
Peak memory 236960 kb
Host smart-81d3c09f-d809-40ba-a97a-563ff45a7915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740663169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.740663169
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.133291380
Short name T355
Test name
Test status
Simulation time 1456250693 ps
CPU time 11.28 seconds
Started Jul 14 06:51:34 PM PDT 24
Finished Jul 14 06:51:46 PM PDT 24
Peak memory 211832 kb
Host smart-1a2ad107-d9be-4ff0-8681-ee7ba7e83fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133291380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.133291380
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.257197505
Short name T132
Test name
Test status
Simulation time 1827797921 ps
CPU time 8.16 seconds
Started Jul 14 06:51:33 PM PDT 24
Finished Jul 14 06:51:43 PM PDT 24
Peak memory 211392 kb
Host smart-b0017a30-6a3a-411e-9559-15f689b10a11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257197505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.257197505
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2616401423
Short name T137
Test name
Test status
Simulation time 9917752943 ps
CPU time 24.66 seconds
Started Jul 14 06:51:30 PM PDT 24
Finished Jul 14 06:51:56 PM PDT 24
Peak memory 213432 kb
Host smart-6c672868-94c6-4ba0-93bc-c04f67fe6142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616401423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2616401423
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2817218767
Short name T81
Test name
Test status
Simulation time 2500868278 ps
CPU time 32.46 seconds
Started Jul 14 06:51:31 PM PDT 24
Finished Jul 14 06:52:06 PM PDT 24
Peak memory 215072 kb
Host smart-3eeba1da-22bf-4c6e-8ca1-9ff53ae87287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817218767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2817218767
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3366270378
Short name T207
Test name
Test status
Simulation time 17239727406 ps
CPU time 15.12 seconds
Started Jul 14 06:50:33 PM PDT 24
Finished Jul 14 06:50:49 PM PDT 24
Peak memory 211408 kb
Host smart-da28c3be-7cb2-4e8f-bb2c-4a392c3c9345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366270378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3366270378
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.318205131
Short name T279
Test name
Test status
Simulation time 41867772973 ps
CPU time 403.17 seconds
Started Jul 14 06:50:27 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 238732 kb
Host smart-966226bf-3c6e-4535-ab75-bdd0816a3800
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318205131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.318205131
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1668195659
Short name T158
Test name
Test status
Simulation time 806343687 ps
CPU time 15.17 seconds
Started Jul 14 06:50:30 PM PDT 24
Finished Jul 14 06:50:47 PM PDT 24
Peak memory 211928 kb
Host smart-2e15e1ea-c136-42c5-ad0f-b68c304d040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668195659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1668195659
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2375933120
Short name T99
Test name
Test status
Simulation time 607119378 ps
CPU time 5.61 seconds
Started Jul 14 06:50:33 PM PDT 24
Finished Jul 14 06:50:39 PM PDT 24
Peak memory 211360 kb
Host smart-7e6f06e7-3e68-43f6-891d-e70c214ac49b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375933120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2375933120
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1064286406
Short name T24
Test name
Test status
Simulation time 16808864640 ps
CPU time 62.9 seconds
Started Jul 14 06:50:29 PM PDT 24
Finished Jul 14 06:51:33 PM PDT 24
Peak memory 236964 kb
Host smart-5a37b3aa-f33f-4fa7-b56b-91491a88ce6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064286406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1064286406
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2245662807
Short name T134
Test name
Test status
Simulation time 1955607122 ps
CPU time 21.35 seconds
Started Jul 14 06:50:32 PM PDT 24
Finished Jul 14 06:50:54 PM PDT 24
Peak memory 213052 kb
Host smart-4931ef41-396b-48a6-be50-1eef7f0738b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245662807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2245662807
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4205708303
Short name T164
Test name
Test status
Simulation time 877217098 ps
CPU time 13.24 seconds
Started Jul 14 06:50:29 PM PDT 24
Finished Jul 14 06:50:43 PM PDT 24
Peak memory 212888 kb
Host smart-31a8f180-d418-414c-bd59-e0869ae3a390
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205708303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4205708303
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2114737773
Short name T278
Test name
Test status
Simulation time 85645459 ps
CPU time 4.4 seconds
Started Jul 14 06:51:31 PM PDT 24
Finished Jul 14 06:51:37 PM PDT 24
Peak memory 211360 kb
Host smart-72fc52e4-fb65-4308-b769-4630835a03e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114737773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2114737773
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.59915434
Short name T212
Test name
Test status
Simulation time 37017550924 ps
CPU time 358.54 seconds
Started Jul 14 06:51:31 PM PDT 24
Finished Jul 14 06:57:32 PM PDT 24
Peak memory 237856 kb
Host smart-628c5cf8-09cb-4f72-9e23-bff955d0e36d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59915434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_co
rrupt_sig_fatal_chk.59915434
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1561275822
Short name T317
Test name
Test status
Simulation time 1242040466 ps
CPU time 17.85 seconds
Started Jul 14 06:51:32 PM PDT 24
Finished Jul 14 06:51:51 PM PDT 24
Peak memory 212000 kb
Host smart-d61dc2db-36c0-41c5-92de-595e51dd3711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561275822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1561275822
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.29364298
Short name T188
Test name
Test status
Simulation time 1790060324 ps
CPU time 19.36 seconds
Started Jul 14 06:51:35 PM PDT 24
Finished Jul 14 06:51:56 PM PDT 24
Peak memory 213420 kb
Host smart-f9471f43-ab43-49da-87ba-9a53b1793f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29364298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.29364298
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4183340671
Short name T344
Test name
Test status
Simulation time 1684086393 ps
CPU time 18.7 seconds
Started Jul 14 06:51:31 PM PDT 24
Finished Jul 14 06:51:51 PM PDT 24
Peak memory 214016 kb
Host smart-2ac260bc-4912-4be1-82e5-c9d350a66601
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183340671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4183340671
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3245584507
Short name T161
Test name
Test status
Simulation time 641584592 ps
CPU time 6.52 seconds
Started Jul 14 06:51:33 PM PDT 24
Finished Jul 14 06:51:41 PM PDT 24
Peak memory 211324 kb
Host smart-6e34f0b2-4f65-4ddc-8dff-eaeafaf088a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245584507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3245584507
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2897203919
Short name T273
Test name
Test status
Simulation time 4410175185 ps
CPU time 126.15 seconds
Started Jul 14 06:51:32 PM PDT 24
Finished Jul 14 06:53:40 PM PDT 24
Peak memory 228656 kb
Host smart-9a064010-a08a-4288-88d7-ea061a05c537
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897203919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2897203919
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1052512160
Short name T330
Test name
Test status
Simulation time 11182605076 ps
CPU time 24.71 seconds
Started Jul 14 06:51:29 PM PDT 24
Finished Jul 14 06:51:54 PM PDT 24
Peak memory 213816 kb
Host smart-326861fe-e819-4581-b1bb-6eb03e844bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052512160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1052512160
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2975297329
Short name T243
Test name
Test status
Simulation time 3970841688 ps
CPU time 16.08 seconds
Started Jul 14 06:51:30 PM PDT 24
Finished Jul 14 06:51:47 PM PDT 24
Peak memory 211444 kb
Host smart-dc59d757-aa8b-4372-ba00-3aa9f7164965
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975297329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2975297329
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1944589499
Short name T269
Test name
Test status
Simulation time 5129510551 ps
CPU time 31.37 seconds
Started Jul 14 06:51:30 PM PDT 24
Finished Jul 14 06:52:02 PM PDT 24
Peak memory 213612 kb
Host smart-3e66f862-8982-47ef-a17c-219123bc8abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944589499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1944589499
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1583050206
Short name T78
Test name
Test status
Simulation time 25061341327 ps
CPU time 69.1 seconds
Started Jul 14 06:51:32 PM PDT 24
Finished Jul 14 06:52:43 PM PDT 24
Peak memory 217464 kb
Host smart-843a2ce8-dea8-4bb1-b90d-39ce6d5338d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583050206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1583050206
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.331008071
Short name T283
Test name
Test status
Simulation time 1686247835 ps
CPU time 10.7 seconds
Started Jul 14 06:51:32 PM PDT 24
Finished Jul 14 06:51:44 PM PDT 24
Peak memory 211284 kb
Host smart-9b5f2923-495f-4cd7-a303-0bbd68ab195a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331008071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.331008071
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.749530646
Short name T163
Test name
Test status
Simulation time 27576332294 ps
CPU time 318.26 seconds
Started Jul 14 06:51:30 PM PDT 24
Finished Jul 14 06:56:49 PM PDT 24
Peak memory 212628 kb
Host smart-4a5abec3-7a70-464f-984c-22026fd6f788
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749530646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.749530646
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3608890704
Short name T197
Test name
Test status
Simulation time 5151838720 ps
CPU time 17.52 seconds
Started Jul 14 06:51:28 PM PDT 24
Finished Jul 14 06:51:46 PM PDT 24
Peak memory 212368 kb
Host smart-0bb88a79-cb9e-4b3f-bb73-2af412e68054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608890704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3608890704
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1541608237
Short name T308
Test name
Test status
Simulation time 1751374225 ps
CPU time 15.41 seconds
Started Jul 14 06:51:34 PM PDT 24
Finished Jul 14 06:51:51 PM PDT 24
Peak memory 211368 kb
Host smart-490a5f1b-57fb-45b8-88d6-5415f0d9ca5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541608237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1541608237
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2971279716
Short name T147
Test name
Test status
Simulation time 12158992272 ps
CPU time 25.01 seconds
Started Jul 14 06:51:30 PM PDT 24
Finished Jul 14 06:51:56 PM PDT 24
Peak memory 213980 kb
Host smart-da959d22-ab00-4ed3-a926-609c3230d37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971279716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2971279716
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1948619785
Short name T302
Test name
Test status
Simulation time 9486908109 ps
CPU time 96.95 seconds
Started Jul 14 06:51:32 PM PDT 24
Finished Jul 14 06:53:11 PM PDT 24
Peak memory 217568 kb
Host smart-8fa7557a-70a7-425d-abe8-fd08b87f0fd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948619785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1948619785
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.65871390
Short name T101
Test name
Test status
Simulation time 105533677391 ps
CPU time 1669.34 seconds
Started Jul 14 06:51:32 PM PDT 24
Finished Jul 14 07:19:23 PM PDT 24
Peak memory 234880 kb
Host smart-d86f540b-fcb4-474d-97d8-a84a92ab471e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65871390 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.65871390
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3764465239
Short name T66
Test name
Test status
Simulation time 1799657168 ps
CPU time 14.26 seconds
Started Jul 14 06:51:30 PM PDT 24
Finished Jul 14 06:51:46 PM PDT 24
Peak memory 211324 kb
Host smart-fd2dbf47-31cd-4bc5-a5ef-99e8c2e2b6c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764465239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3764465239
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.946176984
Short name T266
Test name
Test status
Simulation time 122332249523 ps
CPU time 309.83 seconds
Started Jul 14 06:51:30 PM PDT 24
Finished Jul 14 06:56:42 PM PDT 24
Peak memory 228488 kb
Host smart-d2132078-d553-4a8c-bcbc-62c7f9e543ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946176984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.946176984
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4045690087
Short name T281
Test name
Test status
Simulation time 4149636172 ps
CPU time 11.03 seconds
Started Jul 14 06:51:32 PM PDT 24
Finished Jul 14 06:51:45 PM PDT 24
Peak memory 211920 kb
Host smart-3c0d951a-735d-4980-bf53-9e0132784a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045690087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4045690087
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3032090254
Short name T314
Test name
Test status
Simulation time 1141101341 ps
CPU time 12.07 seconds
Started Jul 14 06:51:34 PM PDT 24
Finished Jul 14 06:51:47 PM PDT 24
Peak memory 211388 kb
Host smart-4430c8c2-bec2-4016-9930-a7416dcc61a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032090254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3032090254
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2085186491
Short name T301
Test name
Test status
Simulation time 4123785569 ps
CPU time 32.4 seconds
Started Jul 14 06:51:31 PM PDT 24
Finished Jul 14 06:52:05 PM PDT 24
Peak memory 213288 kb
Host smart-b8d4115e-77fd-49e3-9722-d694ada32ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085186491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2085186491
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.522254921
Short name T290
Test name
Test status
Simulation time 16731865114 ps
CPU time 23.79 seconds
Started Jul 14 06:51:32 PM PDT 24
Finished Jul 14 06:51:58 PM PDT 24
Peak memory 214492 kb
Host smart-c3dc528f-b830-44f6-840e-b029b49a2b09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522254921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.522254921
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.108668994
Short name T315
Test name
Test status
Simulation time 1062592842 ps
CPU time 11.02 seconds
Started Jul 14 06:51:38 PM PDT 24
Finished Jul 14 06:51:50 PM PDT 24
Peak memory 211324 kb
Host smart-f0c43573-86c8-40f3-93ff-78243652105a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108668994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.108668994
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.625816876
Short name T41
Test name
Test status
Simulation time 12196191625 ps
CPU time 155.04 seconds
Started Jul 14 06:51:30 PM PDT 24
Finished Jul 14 06:54:06 PM PDT 24
Peak memory 236856 kb
Host smart-9f4f7c03-4d26-422b-aaa7-c78f8689fbd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625816876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.625816876
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3789434330
Short name T319
Test name
Test status
Simulation time 692927337 ps
CPU time 9.6 seconds
Started Jul 14 06:51:31 PM PDT 24
Finished Jul 14 06:51:43 PM PDT 24
Peak memory 211920 kb
Host smart-edf0a9ef-62fc-49ad-8715-78f57f11a267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789434330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3789434330
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3476861493
Short name T246
Test name
Test status
Simulation time 6683527178 ps
CPU time 15.65 seconds
Started Jul 14 06:51:31 PM PDT 24
Finished Jul 14 06:51:48 PM PDT 24
Peak memory 211432 kb
Host smart-5879f1b6-006d-4a33-b5c1-1cf41dfc853d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476861493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3476861493
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3727710594
Short name T32
Test name
Test status
Simulation time 6277273544 ps
CPU time 19.72 seconds
Started Jul 14 06:51:31 PM PDT 24
Finished Jul 14 06:51:53 PM PDT 24
Peak memory 214704 kb
Host smart-ce3ab82a-2f08-44ff-9507-e8e5704b05d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727710594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3727710594
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1617350436
Short name T143
Test name
Test status
Simulation time 2984867055 ps
CPU time 20.3 seconds
Started Jul 14 06:51:35 PM PDT 24
Finished Jul 14 06:51:57 PM PDT 24
Peak memory 213716 kb
Host smart-7361e52c-027d-454e-a529-20fd0e4f898f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617350436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1617350436
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.714476640
Short name T282
Test name
Test status
Simulation time 87331963 ps
CPU time 4.32 seconds
Started Jul 14 06:51:41 PM PDT 24
Finished Jul 14 06:51:46 PM PDT 24
Peak memory 211332 kb
Host smart-3e85791f-efe2-471f-8557-b4e699576520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714476640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.714476640
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1887465965
Short name T172
Test name
Test status
Simulation time 10888739111 ps
CPU time 152.45 seconds
Started Jul 14 06:51:36 PM PDT 24
Finished Jul 14 06:54:10 PM PDT 24
Peak memory 237840 kb
Host smart-88c75064-2dec-4000-9ece-22e337dedc54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887465965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1887465965
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3890573412
Short name T339
Test name
Test status
Simulation time 2404839406 ps
CPU time 23.54 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:52:02 PM PDT 24
Peak memory 212124 kb
Host smart-435cf086-a455-4a78-8040-1ead3b29e1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890573412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3890573412
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.793725665
Short name T237
Test name
Test status
Simulation time 4695201000 ps
CPU time 11.5 seconds
Started Jul 14 06:51:41 PM PDT 24
Finished Jul 14 06:51:53 PM PDT 24
Peak memory 211436 kb
Host smart-2a8bd435-6e53-46af-9b87-4fb852f623fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793725665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.793725665
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.266600193
Short name T54
Test name
Test status
Simulation time 701614106 ps
CPU time 9.9 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:51:48 PM PDT 24
Peak memory 213276 kb
Host smart-90410783-4b9c-4144-bc6d-77fa8b68ff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266600193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.266600193
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2641262659
Short name T151
Test name
Test status
Simulation time 8198402864 ps
CPU time 68.9 seconds
Started Jul 14 06:51:35 PM PDT 24
Finished Jul 14 06:52:45 PM PDT 24
Peak memory 215620 kb
Host smart-415742db-fd24-43aa-8bf6-557e28cf643b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641262659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2641262659
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3578975805
Short name T366
Test name
Test status
Simulation time 13014385933 ps
CPU time 9.02 seconds
Started Jul 14 06:51:35 PM PDT 24
Finished Jul 14 06:51:45 PM PDT 24
Peak memory 211380 kb
Host smart-3c6a3ac9-8417-469f-9037-c0f0942f5683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578975805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3578975805
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2393811532
Short name T334
Test name
Test status
Simulation time 8011017424 ps
CPU time 32.39 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:52:10 PM PDT 24
Peak memory 212524 kb
Host smart-1dc59a43-f31b-4c09-8c6d-d714d0f60ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393811532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2393811532
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.235825447
Short name T19
Test name
Test status
Simulation time 300097214 ps
CPU time 7.24 seconds
Started Jul 14 06:51:41 PM PDT 24
Finished Jul 14 06:51:49 PM PDT 24
Peak memory 211372 kb
Host smart-4cb94eaf-1652-46cd-b135-653ae538de2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235825447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.235825447
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2991539618
Short name T187
Test name
Test status
Simulation time 10906674329 ps
CPU time 26.25 seconds
Started Jul 14 06:51:42 PM PDT 24
Finished Jul 14 06:52:09 PM PDT 24
Peak memory 214136 kb
Host smart-c668dc92-e430-4dfc-94ba-f2ca0e139e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991539618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2991539618
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3724830417
Short name T219
Test name
Test status
Simulation time 59620154424 ps
CPU time 55.15 seconds
Started Jul 14 06:51:38 PM PDT 24
Finished Jul 14 06:52:35 PM PDT 24
Peak memory 217340 kb
Host smart-32a71eab-e6eb-467c-8a40-55c44ef50496
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724830417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3724830417
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1984276074
Short name T340
Test name
Test status
Simulation time 1528858522 ps
CPU time 12.53 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:51:51 PM PDT 24
Peak memory 211312 kb
Host smart-9d4fabd5-a3f0-4451-888b-9687e0023b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984276074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1984276074
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.567527550
Short name T363
Test name
Test status
Simulation time 473106291291 ps
CPU time 414.11 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:58:33 PM PDT 24
Peak memory 236836 kb
Host smart-2dacd917-659f-4269-acfc-95a42a1711bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567527550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.567527550
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2576333350
Short name T44
Test name
Test status
Simulation time 1984534590 ps
CPU time 21.53 seconds
Started Jul 14 06:51:42 PM PDT 24
Finished Jul 14 06:52:05 PM PDT 24
Peak memory 212208 kb
Host smart-4e648b83-dc29-49e8-8ded-3c0a99c00664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576333350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2576333350
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2386981213
Short name T203
Test name
Test status
Simulation time 2398673557 ps
CPU time 12.52 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:51:51 PM PDT 24
Peak memory 211368 kb
Host smart-ac0253d8-fadf-4c33-88e8-a42344f96ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386981213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2386981213
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2750303293
Short name T205
Test name
Test status
Simulation time 13945590820 ps
CPU time 23.17 seconds
Started Jul 14 06:51:39 PM PDT 24
Finished Jul 14 06:52:03 PM PDT 24
Peak memory 213916 kb
Host smart-eced6fac-e61e-4371-a1d8-5d4352d6fc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750303293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2750303293
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3789142031
Short name T333
Test name
Test status
Simulation time 5808100427 ps
CPU time 49.54 seconds
Started Jul 14 06:51:36 PM PDT 24
Finished Jul 14 06:52:27 PM PDT 24
Peak memory 216564 kb
Host smart-f7ab24f2-8a41-43a4-8c0e-346e2bd2a5c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789142031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3789142031
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4184777333
Short name T15
Test name
Test status
Simulation time 30815682938 ps
CPU time 586.77 seconds
Started Jul 14 06:51:38 PM PDT 24
Finished Jul 14 07:01:27 PM PDT 24
Peak memory 227960 kb
Host smart-984f6982-b68f-40b7-a1f6-9153de31a868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184777333 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.4184777333
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3249465945
Short name T259
Test name
Test status
Simulation time 1243993123 ps
CPU time 11.52 seconds
Started Jul 14 06:51:38 PM PDT 24
Finished Jul 14 06:51:51 PM PDT 24
Peak memory 211288 kb
Host smart-ee4cc0ba-3e06-4afb-9d69-bd4570d9bb58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249465945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3249465945
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1337689384
Short name T34
Test name
Test status
Simulation time 71732449477 ps
CPU time 340.81 seconds
Started Jul 14 06:51:36 PM PDT 24
Finished Jul 14 06:57:19 PM PDT 24
Peak memory 228616 kb
Host smart-be3e76e6-3d17-4265-a797-3dd357b0c6bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337689384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1337689384
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3373749495
Short name T321
Test name
Test status
Simulation time 10320571275 ps
CPU time 24.3 seconds
Started Jul 14 06:51:38 PM PDT 24
Finished Jul 14 06:52:04 PM PDT 24
Peak memory 211408 kb
Host smart-9aee011a-3452-444c-bf4e-6483d3424287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373749495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3373749495
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1442942069
Short name T272
Test name
Test status
Simulation time 196239218 ps
CPU time 6.31 seconds
Started Jul 14 06:51:38 PM PDT 24
Finished Jul 14 06:51:46 PM PDT 24
Peak memory 211392 kb
Host smart-ee564cce-43c8-4d2f-b654-50a6a996e0dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442942069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1442942069
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3402330077
Short name T211
Test name
Test status
Simulation time 181788104 ps
CPU time 10.07 seconds
Started Jul 14 06:51:38 PM PDT 24
Finished Jul 14 06:51:50 PM PDT 24
Peak memory 213008 kb
Host smart-55806eb3-8d05-4620-9325-ab343353461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402330077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3402330077
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2955101508
Short name T33
Test name
Test status
Simulation time 4614340760 ps
CPU time 48.18 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:52:27 PM PDT 24
Peak memory 216812 kb
Host smart-80103291-0464-4fa0-9957-873d442df5aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955101508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2955101508
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4073789479
Short name T52
Test name
Test status
Simulation time 21021469875 ps
CPU time 795.57 seconds
Started Jul 14 06:51:41 PM PDT 24
Finished Jul 14 07:04:58 PM PDT 24
Peak memory 227676 kb
Host smart-f27ba6a9-eb64-4bd9-9a4b-66753223df90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073789479 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.4073789479
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2473355968
Short name T352
Test name
Test status
Simulation time 804494487 ps
CPU time 8.96 seconds
Started Jul 14 06:51:53 PM PDT 24
Finished Jul 14 06:52:04 PM PDT 24
Peak memory 211284 kb
Host smart-725d3999-ed25-4ae9-b109-24d36fa711eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473355968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2473355968
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2140989792
Short name T20
Test name
Test status
Simulation time 25862289004 ps
CPU time 235.83 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:55:35 PM PDT 24
Peak memory 233912 kb
Host smart-efc10398-5f2b-4da6-8a80-c65d121e6c35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140989792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2140989792
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2917398124
Short name T331
Test name
Test status
Simulation time 11618428667 ps
CPU time 25.5 seconds
Started Jul 14 06:51:42 PM PDT 24
Finished Jul 14 06:52:08 PM PDT 24
Peak memory 212332 kb
Host smart-a9213229-c632-480b-9163-b82ba5a1d235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917398124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2917398124
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.131987783
Short name T154
Test name
Test status
Simulation time 3401298070 ps
CPU time 16.78 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:51:55 PM PDT 24
Peak memory 211392 kb
Host smart-afd4614b-5671-4cbd-ae39-7fafad24adca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131987783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.131987783
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3104774931
Short name T196
Test name
Test status
Simulation time 8325436401 ps
CPU time 37.83 seconds
Started Jul 14 06:51:37 PM PDT 24
Finished Jul 14 06:52:17 PM PDT 24
Peak memory 214932 kb
Host smart-c94201cb-5031-4f5b-a367-3dd8eb20f9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104774931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3104774931
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1849194389
Short name T83
Test name
Test status
Simulation time 12921544272 ps
CPU time 134.93 seconds
Started Jul 14 06:51:41 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 217096 kb
Host smart-a0d5a49e-6b79-4536-a6bf-508abf98c320
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849194389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1849194389
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2649757746
Short name T251
Test name
Test status
Simulation time 1768703254 ps
CPU time 14.55 seconds
Started Jul 14 06:50:32 PM PDT 24
Finished Jul 14 06:50:47 PM PDT 24
Peak memory 211296 kb
Host smart-e3000d3b-4c4a-425e-a6b9-1ac95ebf4fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649757746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2649757746
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1357208014
Short name T221
Test name
Test status
Simulation time 6162116953 ps
CPU time 98.12 seconds
Started Jul 14 06:50:28 PM PDT 24
Finished Jul 14 06:52:07 PM PDT 24
Peak memory 237888 kb
Host smart-6a4e5ebe-08ec-4424-b62b-fbe9d5dc7b7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357208014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1357208014
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1659579199
Short name T289
Test name
Test status
Simulation time 1725058827 ps
CPU time 12.4 seconds
Started Jul 14 06:50:32 PM PDT 24
Finished Jul 14 06:50:46 PM PDT 24
Peak memory 212192 kb
Host smart-3ad34263-7bf5-41ef-aae6-2218d9ed5b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659579199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1659579199
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1315826534
Short name T170
Test name
Test status
Simulation time 1533314809 ps
CPU time 14.11 seconds
Started Jul 14 06:50:27 PM PDT 24
Finished Jul 14 06:50:42 PM PDT 24
Peak memory 211344 kb
Host smart-1705d93b-706a-4e73-bd23-606d118f05e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315826534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1315826534
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2431381195
Short name T16
Test name
Test status
Simulation time 6830331460 ps
CPU time 29.48 seconds
Started Jul 14 06:50:31 PM PDT 24
Finished Jul 14 06:51:01 PM PDT 24
Peak memory 214228 kb
Host smart-f746d35b-782a-4f8f-8eaa-7bbb19122dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431381195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2431381195
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.326790547
Short name T310
Test name
Test status
Simulation time 739555736 ps
CPU time 23.4 seconds
Started Jul 14 06:50:32 PM PDT 24
Finished Jul 14 06:50:56 PM PDT 24
Peak memory 215348 kb
Host smart-cdf31ab1-a471-4d99-9a9e-71e2c57d5292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326790547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.326790547
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2324278552
Short name T30
Test name
Test status
Simulation time 10791226164 ps
CPU time 4503.33 seconds
Started Jul 14 06:50:33 PM PDT 24
Finished Jul 14 08:05:38 PM PDT 24
Peak memory 230580 kb
Host smart-b2e5a5f7-8eef-4dc7-90ae-53215d172012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324278552 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2324278552
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2103848807
Short name T3
Test name
Test status
Simulation time 669338316 ps
CPU time 6.77 seconds
Started Jul 14 06:50:37 PM PDT 24
Finished Jul 14 06:50:45 PM PDT 24
Peak memory 211316 kb
Host smart-d9aecfbd-bc22-40a4-83b1-b65f8d507bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103848807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2103848807
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1936954125
Short name T40
Test name
Test status
Simulation time 113139933353 ps
CPU time 252.76 seconds
Started Jul 14 06:50:40 PM PDT 24
Finished Jul 14 06:54:53 PM PDT 24
Peak memory 212616 kb
Host smart-f79d2a31-6ec8-4aca-823e-56ad118268be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936954125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1936954125
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1041610650
Short name T162
Test name
Test status
Simulation time 8919093686 ps
CPU time 21.81 seconds
Started Jul 14 06:50:36 PM PDT 24
Finished Jul 14 06:50:59 PM PDT 24
Peak memory 212860 kb
Host smart-0fef0c6d-72e3-4424-b5a6-b149b4079dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041610650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1041610650
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4277106459
Short name T361
Test name
Test status
Simulation time 1916720831 ps
CPU time 10.76 seconds
Started Jul 14 06:50:36 PM PDT 24
Finished Jul 14 06:50:47 PM PDT 24
Peak memory 211384 kb
Host smart-a02810c7-2023-4855-b644-fc763b95873c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277106459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4277106459
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2185697148
Short name T223
Test name
Test status
Simulation time 2304484371 ps
CPU time 26.96 seconds
Started Jul 14 06:50:30 PM PDT 24
Finished Jul 14 06:50:57 PM PDT 24
Peak memory 213304 kb
Host smart-7bca92a7-0870-4f0e-a16d-782417be24de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185697148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2185697148
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4016171580
Short name T244
Test name
Test status
Simulation time 1961808444 ps
CPU time 10.66 seconds
Started Jul 14 06:50:38 PM PDT 24
Finished Jul 14 06:50:50 PM PDT 24
Peak memory 211396 kb
Host smart-46305603-0ce7-4624-8e72-70bdbc10ed38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016171580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4016171580
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.594707023
Short name T325
Test name
Test status
Simulation time 1538781583 ps
CPU time 7.03 seconds
Started Jul 14 06:50:37 PM PDT 24
Finished Jul 14 06:50:44 PM PDT 24
Peak memory 211348 kb
Host smart-0608c621-406a-48b2-a7dd-137df00ddaa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594707023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.594707023
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.926698987
Short name T265
Test name
Test status
Simulation time 6679344733 ps
CPU time 182.48 seconds
Started Jul 14 06:50:39 PM PDT 24
Finished Jul 14 06:53:42 PM PDT 24
Peak memory 233776 kb
Host smart-86c3ff11-1e0f-4adc-9d39-0ac569a18a04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926698987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.926698987
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2644119310
Short name T234
Test name
Test status
Simulation time 1511190760 ps
CPU time 19.05 seconds
Started Jul 14 06:50:36 PM PDT 24
Finished Jul 14 06:50:56 PM PDT 24
Peak memory 211948 kb
Host smart-225fd6f8-2bd0-4ef5-96b5-15967c1835a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644119310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2644119310
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2549595278
Short name T329
Test name
Test status
Simulation time 4825154668 ps
CPU time 12.58 seconds
Started Jul 14 06:50:36 PM PDT 24
Finished Jul 14 06:50:50 PM PDT 24
Peak memory 211440 kb
Host smart-7ae4b25f-db42-46f8-8258-0d38ac25f49b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549595278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2549595278
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2346741739
Short name T224
Test name
Test status
Simulation time 40974513617 ps
CPU time 25.79 seconds
Started Jul 14 06:50:38 PM PDT 24
Finished Jul 14 06:51:05 PM PDT 24
Peak memory 214624 kb
Host smart-1c9c5118-6339-498f-bc76-a5b798cd5061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346741739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2346741739
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3167183958
Short name T248
Test name
Test status
Simulation time 12366787050 ps
CPU time 26.15 seconds
Started Jul 14 06:50:39 PM PDT 24
Finished Jul 14 06:51:06 PM PDT 24
Peak memory 214100 kb
Host smart-642d1902-de08-407f-9415-f0a57eac2157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167183958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3167183958
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3849105663
Short name T357
Test name
Test status
Simulation time 209310779 ps
CPU time 4.33 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:50:48 PM PDT 24
Peak memory 211300 kb
Host smart-b26cb126-d2c7-48e7-8602-33b126d8b995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849105663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3849105663
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.730814848
Short name T37
Test name
Test status
Simulation time 111773051519 ps
CPU time 170.1 seconds
Started Jul 14 06:50:36 PM PDT 24
Finished Jul 14 06:53:26 PM PDT 24
Peak memory 237536 kb
Host smart-5c91ea3c-936c-41a0-a90e-15b9ac110e61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730814848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.730814848
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3085478727
Short name T133
Test name
Test status
Simulation time 7898381485 ps
CPU time 25.14 seconds
Started Jul 14 06:50:37 PM PDT 24
Finished Jul 14 06:51:04 PM PDT 24
Peak memory 212212 kb
Host smart-592aeb58-b3f9-4289-bea7-e0351a0ca4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085478727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3085478727
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1479287502
Short name T107
Test name
Test status
Simulation time 604951675 ps
CPU time 5.44 seconds
Started Jul 14 06:50:35 PM PDT 24
Finished Jul 14 06:50:41 PM PDT 24
Peak memory 211348 kb
Host smart-ed94ced0-6622-4aab-b52c-fa66494195a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479287502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1479287502
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3502628553
Short name T267
Test name
Test status
Simulation time 3757340796 ps
CPU time 42.54 seconds
Started Jul 14 06:50:37 PM PDT 24
Finished Jul 14 06:51:21 PM PDT 24
Peak memory 213692 kb
Host smart-25d333f1-2375-4a68-aac4-ca9635549482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502628553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3502628553
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3103272371
Short name T104
Test name
Test status
Simulation time 37084767145 ps
CPU time 90.16 seconds
Started Jul 14 06:50:39 PM PDT 24
Finished Jul 14 06:52:09 PM PDT 24
Peak memory 219352 kb
Host smart-caef0797-fe60-4a4a-bf34-3fb1eec190ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103272371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3103272371
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1413440760
Short name T118
Test name
Test status
Simulation time 82208663823 ps
CPU time 1699.67 seconds
Started Jul 14 06:50:47 PM PDT 24
Finished Jul 14 07:19:08 PM PDT 24
Peak memory 244008 kb
Host smart-5040ffd7-c5b3-4f35-a8ad-4fe67741ef7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413440760 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1413440760
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4084851972
Short name T296
Test name
Test status
Simulation time 4380444527 ps
CPU time 11.86 seconds
Started Jul 14 06:50:41 PM PDT 24
Finished Jul 14 06:50:55 PM PDT 24
Peak memory 211408 kb
Host smart-4cb71092-8852-4630-ba6f-adad4a3c5955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084851972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4084851972
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.627835274
Short name T171
Test name
Test status
Simulation time 188789089448 ps
CPU time 283.51 seconds
Started Jul 14 06:50:44 PM PDT 24
Finished Jul 14 06:55:29 PM PDT 24
Peak memory 213208 kb
Host smart-966e8f54-62a0-4ff4-b378-65c2a26c6cc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627835274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.627835274
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.146693135
Short name T183
Test name
Test status
Simulation time 1547947575 ps
CPU time 14.84 seconds
Started Jul 14 06:50:45 PM PDT 24
Finished Jul 14 06:51:00 PM PDT 24
Peak memory 212124 kb
Host smart-4489e168-fb79-4fa8-a062-0bcb89b64651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146693135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.146693135
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2822317203
Short name T328
Test name
Test status
Simulation time 864096899 ps
CPU time 8.16 seconds
Started Jul 14 06:50:43 PM PDT 24
Finished Jul 14 06:50:53 PM PDT 24
Peak memory 211380 kb
Host smart-ecb5f474-25c4-43b2-af40-3c277901607f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822317203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2822317203
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1332516653
Short name T287
Test name
Test status
Simulation time 4980334253 ps
CPU time 19.54 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:51:03 PM PDT 24
Peak memory 212100 kb
Host smart-25970118-e236-4c13-ba8f-8d7cea7accb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332516653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1332516653
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1485981238
Short name T256
Test name
Test status
Simulation time 679674290 ps
CPU time 10.59 seconds
Started Jul 14 06:50:47 PM PDT 24
Finished Jul 14 06:50:58 PM PDT 24
Peak memory 211212 kb
Host smart-9c0b4495-93cd-4081-b05d-e70aba9527e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485981238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1485981238
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1237923679
Short name T313
Test name
Test status
Simulation time 49641270402 ps
CPU time 475.36 seconds
Started Jul 14 06:50:42 PM PDT 24
Finished Jul 14 06:58:39 PM PDT 24
Peak memory 226404 kb
Host smart-b65ca7cd-eaa4-4fc9-8387-ff3dd25061f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237923679 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1237923679
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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