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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.32 96.89 91.85 97.67 100.00 98.28 97.45 99.07


Total test records in report: 464
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T23 /workspace/coverage/default/3.rom_ctrl_sec_cm.819288870 Jul 15 05:49:14 PM PDT 24 Jul 15 05:51:00 PM PDT 24 1214917425 ps
T300 /workspace/coverage/default/45.rom_ctrl_alert_test.187340249 Jul 15 05:50:40 PM PDT 24 Jul 15 05:50:45 PM PDT 24 333899679 ps
T301 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.125775162 Jul 15 05:50:16 PM PDT 24 Jul 15 05:50:39 PM PDT 24 8227970322 ps
T302 /workspace/coverage/default/11.rom_ctrl_smoke.2160754838 Jul 15 05:49:31 PM PDT 24 Jul 15 05:49:47 PM PDT 24 842733951 ps
T303 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4046544340 Jul 15 05:50:18 PM PDT 24 Jul 15 06:27:29 PM PDT 24 53827104919 ps
T304 /workspace/coverage/default/34.rom_ctrl_alert_test.1630484740 Jul 15 05:50:12 PM PDT 24 Jul 15 05:50:20 PM PDT 24 579078133 ps
T305 /workspace/coverage/default/11.rom_ctrl_stress_all.2280669097 Jul 15 05:49:26 PM PDT 24 Jul 15 05:49:46 PM PDT 24 1804178594 ps
T306 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3047035055 Jul 15 05:49:27 PM PDT 24 Jul 15 05:49:45 PM PDT 24 39332380056 ps
T307 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2495979465 Jul 15 05:50:02 PM PDT 24 Jul 15 05:50:12 PM PDT 24 1263247523 ps
T99 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4037143895 Jul 15 05:49:17 PM PDT 24 Jul 15 05:49:31 PM PDT 24 1292595597 ps
T308 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1098303352 Jul 15 05:50:09 PM PDT 24 Jul 15 05:52:40 PM PDT 24 7874292730 ps
T309 /workspace/coverage/default/33.rom_ctrl_alert_test.1023161433 Jul 15 05:50:14 PM PDT 24 Jul 15 05:50:23 PM PDT 24 2239405952 ps
T310 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2015933303 Jul 15 05:50:15 PM PDT 24 Jul 15 05:55:41 PM PDT 24 33476436045 ps
T311 /workspace/coverage/default/20.rom_ctrl_smoke.3164565990 Jul 15 05:49:49 PM PDT 24 Jul 15 05:50:22 PM PDT 24 5094023004 ps
T312 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3179518792 Jul 15 05:50:12 PM PDT 24 Jul 15 05:54:50 PM PDT 24 192906413177 ps
T313 /workspace/coverage/default/16.rom_ctrl_smoke.4132335928 Jul 15 05:49:43 PM PDT 24 Jul 15 05:50:14 PM PDT 24 7387722429 ps
T314 /workspace/coverage/default/32.rom_ctrl_smoke.3633262813 Jul 15 05:50:11 PM PDT 24 Jul 15 05:50:30 PM PDT 24 1211307385 ps
T315 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3638509041 Jul 15 05:50:20 PM PDT 24 Jul 15 05:57:15 PM PDT 24 43015831637 ps
T316 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3353492269 Jul 15 05:49:34 PM PDT 24 Jul 15 05:51:50 PM PDT 24 11417402128 ps
T317 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1911358479 Jul 15 05:50:30 PM PDT 24 Jul 15 05:52:17 PM PDT 24 8523521821 ps
T318 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2975200999 Jul 15 05:49:18 PM PDT 24 Jul 15 05:49:36 PM PDT 24 2131974090 ps
T319 /workspace/coverage/default/3.rom_ctrl_stress_all.3152328585 Jul 15 05:49:12 PM PDT 24 Jul 15 05:50:14 PM PDT 24 6858510669 ps
T320 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2648766079 Jul 15 05:49:16 PM PDT 24 Jul 15 05:49:40 PM PDT 24 11639476432 ps
T321 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3632378875 Jul 15 05:50:06 PM PDT 24 Jul 15 05:50:22 PM PDT 24 4814378560 ps
T322 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4144625963 Jul 15 05:50:32 PM PDT 24 Jul 15 05:50:52 PM PDT 24 24662727876 ps
T323 /workspace/coverage/default/33.rom_ctrl_smoke.2971436031 Jul 15 05:50:14 PM PDT 24 Jul 15 05:50:45 PM PDT 24 3495678812 ps
T24 /workspace/coverage/default/2.rom_ctrl_sec_cm.3051132591 Jul 15 05:49:10 PM PDT 24 Jul 15 05:50:13 PM PDT 24 2202929520 ps
T324 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1851116135 Jul 15 05:50:32 PM PDT 24 Jul 15 05:50:48 PM PDT 24 6317536541 ps
T325 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1694816995 Jul 15 05:50:20 PM PDT 24 Jul 15 05:57:40 PM PDT 24 43449419136 ps
T326 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2968684937 Jul 15 05:50:03 PM PDT 24 Jul 15 05:50:31 PM PDT 24 12736116943 ps
T327 /workspace/coverage/default/48.rom_ctrl_stress_all.2888657283 Jul 15 05:50:42 PM PDT 24 Jul 15 05:51:53 PM PDT 24 17597473608 ps
T328 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1911870873 Jul 15 05:49:42 PM PDT 24 Jul 15 05:50:11 PM PDT 24 6046171165 ps
T329 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3419923158 Jul 15 05:50:35 PM PDT 24 Jul 15 05:50:40 PM PDT 24 1132057458 ps
T330 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.763316701 Jul 15 05:50:13 PM PDT 24 Jul 15 05:50:23 PM PDT 24 928685843 ps
T331 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2809689721 Jul 15 05:50:12 PM PDT 24 Jul 15 05:50:46 PM PDT 24 4143489883 ps
T332 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.300621420 Jul 15 05:50:18 PM PDT 24 Jul 15 05:50:41 PM PDT 24 7863752233 ps
T114 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1725603686 Jul 15 05:50:14 PM PDT 24 Jul 15 06:10:15 PM PDT 24 30117280440 ps
T333 /workspace/coverage/default/37.rom_ctrl_stress_all.1479399433 Jul 15 05:50:19 PM PDT 24 Jul 15 05:50:55 PM PDT 24 8659602397 ps
T334 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2703814013 Jul 15 05:50:04 PM PDT 24 Jul 15 06:11:51 PM PDT 24 85735274256 ps
T335 /workspace/coverage/default/32.rom_ctrl_alert_test.2813883739 Jul 15 05:50:12 PM PDT 24 Jul 15 05:50:29 PM PDT 24 1836441612 ps
T336 /workspace/coverage/default/7.rom_ctrl_smoke.4051803561 Jul 15 05:49:21 PM PDT 24 Jul 15 05:49:52 PM PDT 24 3458533380 ps
T337 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1915167373 Jul 15 05:50:32 PM PDT 24 Jul 15 05:54:38 PM PDT 24 291934510652 ps
T338 /workspace/coverage/default/32.rom_ctrl_stress_all.2129859123 Jul 15 05:50:14 PM PDT 24 Jul 15 05:51:16 PM PDT 24 6683200655 ps
T339 /workspace/coverage/default/34.rom_ctrl_smoke.3878069628 Jul 15 05:50:11 PM PDT 24 Jul 15 05:50:28 PM PDT 24 960312878 ps
T340 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2139431755 Jul 15 05:49:56 PM PDT 24 Jul 15 05:50:15 PM PDT 24 2795105673 ps
T341 /workspace/coverage/default/16.rom_ctrl_alert_test.3354792207 Jul 15 05:49:42 PM PDT 24 Jul 15 05:49:47 PM PDT 24 348217038 ps
T342 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3267910141 Jul 15 05:50:33 PM PDT 24 Jul 15 05:50:45 PM PDT 24 273826307 ps
T343 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3584465648 Jul 15 05:50:05 PM PDT 24 Jul 15 05:50:16 PM PDT 24 792928343 ps
T344 /workspace/coverage/default/3.rom_ctrl_alert_test.2779512335 Jul 15 05:49:09 PM PDT 24 Jul 15 05:49:14 PM PDT 24 175500780 ps
T345 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.331152425 Jul 15 05:49:31 PM PDT 24 Jul 15 05:49:52 PM PDT 24 3209451453 ps
T346 /workspace/coverage/default/26.rom_ctrl_smoke.1172479288 Jul 15 05:50:04 PM PDT 24 Jul 15 05:50:38 PM PDT 24 10332459003 ps
T347 /workspace/coverage/default/17.rom_ctrl_alert_test.3800058216 Jul 15 05:49:41 PM PDT 24 Jul 15 05:49:50 PM PDT 24 1626640808 ps
T348 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.998603220 Jul 15 05:49:54 PM PDT 24 Jul 15 05:52:05 PM PDT 24 15561639205 ps
T349 /workspace/coverage/default/31.rom_ctrl_stress_all.786681126 Jul 15 05:50:13 PM PDT 24 Jul 15 05:50:42 PM PDT 24 9918972766 ps
T350 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2590466928 Jul 15 05:49:17 PM PDT 24 Jul 15 05:49:52 PM PDT 24 21235392752 ps
T351 /workspace/coverage/default/12.rom_ctrl_smoke.3770839791 Jul 15 05:49:35 PM PDT 24 Jul 15 05:49:56 PM PDT 24 1817540439 ps
T352 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1220831408 Jul 15 05:50:05 PM PDT 24 Jul 15 05:52:11 PM PDT 24 13331377128 ps
T353 /workspace/coverage/default/29.rom_ctrl_stress_all.1164226903 Jul 15 05:50:04 PM PDT 24 Jul 15 05:50:33 PM PDT 24 2507685785 ps
T354 /workspace/coverage/default/2.rom_ctrl_alert_test.3843214961 Jul 15 05:49:13 PM PDT 24 Jul 15 05:49:26 PM PDT 24 5033621507 ps
T355 /workspace/coverage/default/8.rom_ctrl_stress_all.2804138898 Jul 15 05:49:27 PM PDT 24 Jul 15 05:50:12 PM PDT 24 5590489280 ps
T356 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1466954662 Jul 15 05:49:33 PM PDT 24 Jul 15 05:49:51 PM PDT 24 2015111551 ps
T357 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2254259461 Jul 15 05:49:55 PM PDT 24 Jul 15 05:50:07 PM PDT 24 970818266 ps
T358 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3473962874 Jul 15 05:50:30 PM PDT 24 Jul 15 05:50:43 PM PDT 24 4715145834 ps
T359 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4098269383 Jul 15 05:50:34 PM PDT 24 Jul 15 05:50:42 PM PDT 24 397032697 ps
T360 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.133421037 Jul 15 05:49:18 PM PDT 24 Jul 15 05:49:28 PM PDT 24 640680522 ps
T361 /workspace/coverage/default/19.rom_ctrl_smoke.1817098390 Jul 15 05:49:56 PM PDT 24 Jul 15 05:50:32 PM PDT 24 3543152983 ps
T362 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.271105088 Jul 15 05:49:46 PM PDT 24 Jul 15 05:50:03 PM PDT 24 1898298298 ps
T363 /workspace/coverage/default/19.rom_ctrl_stress_all.2167346125 Jul 15 05:49:56 PM PDT 24 Jul 15 05:50:26 PM PDT 24 2830524900 ps
T364 /workspace/coverage/default/9.rom_ctrl_smoke.2057649018 Jul 15 05:49:27 PM PDT 24 Jul 15 05:49:38 PM PDT 24 765260364 ps
T52 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2318347322 Jul 15 06:59:58 PM PDT 24 Jul 15 07:00:17 PM PDT 24 1209458814 ps
T49 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2393808043 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:57 PM PDT 24 3508713436 ps
T53 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2454955544 Jul 15 06:59:35 PM PDT 24 Jul 15 06:59:46 PM PDT 24 2153601885 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4276972690 Jul 15 06:59:43 PM PDT 24 Jul 15 06:59:49 PM PDT 24 334936738 ps
T90 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1530036591 Jul 15 06:59:57 PM PDT 24 Jul 15 07:00:02 PM PDT 24 171583374 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2378178386 Jul 15 06:59:40 PM PDT 24 Jul 15 06:59:50 PM PDT 24 557559849 ps
T61 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2006450031 Jul 15 07:00:03 PM PDT 24 Jul 15 07:00:13 PM PDT 24 1698022483 ps
T50 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.529614420 Jul 15 06:59:34 PM PDT 24 Jul 15 07:00:45 PM PDT 24 3023293640 ps
T367 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1410949615 Jul 15 06:59:45 PM PDT 24 Jul 15 07:00:00 PM PDT 24 7620030316 ps
T100 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3679500496 Jul 15 06:59:29 PM PDT 24 Jul 15 07:00:29 PM PDT 24 29508696014 ps
T62 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2087314814 Jul 15 07:00:03 PM PDT 24 Jul 15 07:00:10 PM PDT 24 2249473943 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3194054249 Jul 15 06:59:45 PM PDT 24 Jul 15 06:59:56 PM PDT 24 4858468153 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1781377541 Jul 15 06:59:48 PM PDT 24 Jul 15 07:00:00 PM PDT 24 4401386263 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2625685349 Jul 15 06:59:40 PM PDT 24 Jul 15 06:59:57 PM PDT 24 7951513294 ps
T51 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1433423683 Jul 15 07:00:01 PM PDT 24 Jul 15 07:00:50 PM PDT 24 2078985157 ps
T369 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3944048214 Jul 15 06:59:54 PM PDT 24 Jul 15 07:00:00 PM PDT 24 330433980 ps
T63 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.254355291 Jul 15 06:59:41 PM PDT 24 Jul 15 07:00:11 PM PDT 24 1969079557 ps
T370 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1312312701 Jul 15 06:59:56 PM PDT 24 Jul 15 07:00:14 PM PDT 24 4015011898 ps
T93 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.343907400 Jul 15 06:59:51 PM PDT 24 Jul 15 07:00:07 PM PDT 24 7544509359 ps
T104 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.718673790 Jul 15 06:59:45 PM PDT 24 Jul 15 07:00:34 PM PDT 24 38601486397 ps
T113 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3461682721 Jul 15 06:59:41 PM PDT 24 Jul 15 07:00:22 PM PDT 24 3545619104 ps
T64 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3429389672 Jul 15 06:59:43 PM PDT 24 Jul 15 06:59:56 PM PDT 24 5915064789 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3915035862 Jul 15 06:59:44 PM PDT 24 Jul 15 07:00:00 PM PDT 24 2476865274 ps
T372 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2447240647 Jul 15 06:59:48 PM PDT 24 Jul 15 06:59:53 PM PDT 24 203780775 ps
T103 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3590038155 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:34 PM PDT 24 2030819837 ps
T373 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.697406226 Jul 15 06:59:51 PM PDT 24 Jul 15 07:00:01 PM PDT 24 2762312985 ps
T374 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.47741355 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:05 PM PDT 24 1523524637 ps
T65 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.528376059 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:54 PM PDT 24 88362413336 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2942112677 Jul 15 06:59:34 PM PDT 24 Jul 15 06:59:50 PM PDT 24 1361947811 ps
T105 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1706578860 Jul 15 06:59:51 PM PDT 24 Jul 15 07:01:02 PM PDT 24 1074118892 ps
T376 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2456246113 Jul 15 06:59:56 PM PDT 24 Jul 15 07:00:13 PM PDT 24 1389347693 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1731026241 Jul 15 06:59:41 PM PDT 24 Jul 15 06:59:56 PM PDT 24 1744258319 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3285607885 Jul 15 06:59:39 PM PDT 24 Jul 15 07:00:24 PM PDT 24 31243154192 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1755837951 Jul 15 07:00:01 PM PDT 24 Jul 15 07:00:16 PM PDT 24 1786035088 ps
T95 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2412887599 Jul 15 07:00:04 PM PDT 24 Jul 15 07:00:12 PM PDT 24 1077888463 ps
T96 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2173801803 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:46 PM PDT 24 8939379470 ps
T379 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3358011841 Jul 15 06:59:58 PM PDT 24 Jul 15 07:00:09 PM PDT 24 5660065479 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.177610817 Jul 15 06:59:58 PM PDT 24 Jul 15 07:00:06 PM PDT 24 489122810 ps
T381 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4232996179 Jul 15 06:59:48 PM PDT 24 Jul 15 06:59:56 PM PDT 24 689858441 ps
T106 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.314695245 Jul 15 07:00:04 PM PDT 24 Jul 15 07:00:41 PM PDT 24 332627828 ps
T382 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.705097385 Jul 15 06:59:47 PM PDT 24 Jul 15 07:00:03 PM PDT 24 3724479013 ps
T383 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2536544299 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:32 PM PDT 24 4459765332 ps
T97 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2652427848 Jul 15 07:00:12 PM PDT 24 Jul 15 07:00:25 PM PDT 24 29669809749 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2017972525 Jul 15 06:59:37 PM PDT 24 Jul 15 06:59:49 PM PDT 24 1913630895 ps
T385 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1519805566 Jul 15 06:59:54 PM PDT 24 Jul 15 07:00:14 PM PDT 24 18581200572 ps
T386 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1541312383 Jul 15 06:59:42 PM PDT 24 Jul 15 06:59:47 PM PDT 24 116368972 ps
T107 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3412439909 Jul 15 06:59:55 PM PDT 24 Jul 15 07:01:12 PM PDT 24 2259096305 ps
T102 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.189913844 Jul 15 06:59:50 PM PDT 24 Jul 15 07:00:37 PM PDT 24 3291171196 ps
T66 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2208526884 Jul 15 06:59:54 PM PDT 24 Jul 15 07:01:18 PM PDT 24 22916232909 ps
T67 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3043667945 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:00 PM PDT 24 1230929580 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2106313865 Jul 15 06:59:41 PM PDT 24 Jul 15 06:59:52 PM PDT 24 962856988 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.430784207 Jul 15 06:59:39 PM PDT 24 Jul 15 06:59:47 PM PDT 24 1087561794 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1322352307 Jul 15 06:59:42 PM PDT 24 Jul 15 06:59:58 PM PDT 24 3590867499 ps
T388 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3116107310 Jul 15 06:59:48 PM PDT 24 Jul 15 07:00:33 PM PDT 24 2648239205 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.880771790 Jul 15 06:59:48 PM PDT 24 Jul 15 06:59:58 PM PDT 24 198843207 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3448994314 Jul 15 07:00:02 PM PDT 24 Jul 15 07:00:15 PM PDT 24 5472513519 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2399872530 Jul 15 06:59:39 PM PDT 24 Jul 15 06:59:45 PM PDT 24 415159853 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1399376942 Jul 15 06:59:42 PM PDT 24 Jul 15 06:59:47 PM PDT 24 346961539 ps
T76 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.516503349 Jul 15 06:59:53 PM PDT 24 Jul 15 07:00:44 PM PDT 24 30348124785 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4044721732 Jul 15 06:59:39 PM PDT 24 Jul 15 06:59:53 PM PDT 24 6377600812 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3084583876 Jul 15 06:59:40 PM PDT 24 Jul 15 06:59:45 PM PDT 24 169515684 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1314286346 Jul 15 06:59:38 PM PDT 24 Jul 15 06:59:45 PM PDT 24 130729429 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.873992803 Jul 15 06:59:43 PM PDT 24 Jul 15 06:59:56 PM PDT 24 12439141359 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.229622337 Jul 15 06:59:56 PM PDT 24 Jul 15 07:00:04 PM PDT 24 873148129 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4191388172 Jul 15 06:59:43 PM PDT 24 Jul 15 06:59:48 PM PDT 24 384241856 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.93270055 Jul 15 06:59:54 PM PDT 24 Jul 15 07:00:10 PM PDT 24 3475623929 ps
T400 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.767362053 Jul 15 06:59:55 PM PDT 24 Jul 15 07:00:10 PM PDT 24 1662186601 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2340082734 Jul 15 06:59:39 PM PDT 24 Jul 15 06:59:52 PM PDT 24 1407761375 ps
T402 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1878879030 Jul 15 06:59:51 PM PDT 24 Jul 15 07:00:32 PM PDT 24 822491282 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.286088883 Jul 15 06:59:47 PM PDT 24 Jul 15 06:59:52 PM PDT 24 174944309 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4191035043 Jul 15 06:59:47 PM PDT 24 Jul 15 07:00:03 PM PDT 24 2006739137 ps
T405 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.789897477 Jul 15 07:00:02 PM PDT 24 Jul 15 07:00:15 PM PDT 24 2325918335 ps
T77 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2609546195 Jul 15 07:00:05 PM PDT 24 Jul 15 07:00:47 PM PDT 24 4600820918 ps
T406 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3778522278 Jul 15 06:59:47 PM PDT 24 Jul 15 06:59:55 PM PDT 24 364749072 ps
T407 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2387570054 Jul 15 07:00:02 PM PDT 24 Jul 15 07:00:16 PM PDT 24 6098393164 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.622246505 Jul 15 06:59:38 PM PDT 24 Jul 15 06:59:42 PM PDT 24 90971115 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3485490920 Jul 15 06:59:40 PM PDT 24 Jul 15 06:59:51 PM PDT 24 1237094493 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2902706687 Jul 15 06:59:39 PM PDT 24 Jul 15 06:59:51 PM PDT 24 2879752840 ps
T411 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.52708034 Jul 15 06:59:51 PM PDT 24 Jul 15 06:59:56 PM PDT 24 433127708 ps
T412 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2498782967 Jul 15 07:00:12 PM PDT 24 Jul 15 07:00:26 PM PDT 24 865839176 ps
T413 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3183129397 Jul 15 07:00:04 PM PDT 24 Jul 15 07:00:15 PM PDT 24 2080494378 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3174510737 Jul 15 06:59:39 PM PDT 24 Jul 15 06:59:53 PM PDT 24 6737920192 ps
T415 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4165661991 Jul 15 06:59:59 PM PDT 24 Jul 15 07:00:07 PM PDT 24 1662745985 ps
T416 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2210843965 Jul 15 06:59:58 PM PDT 24 Jul 15 07:00:12 PM PDT 24 1246619925 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1318303035 Jul 15 06:59:41 PM PDT 24 Jul 15 07:00:01 PM PDT 24 8183580767 ps
T418 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3343748411 Jul 15 06:59:57 PM PDT 24 Jul 15 07:00:16 PM PDT 24 376666191 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2827265297 Jul 15 06:59:35 PM PDT 24 Jul 15 06:59:50 PM PDT 24 1683193954 ps
T420 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2114311872 Jul 15 07:00:12 PM PDT 24 Jul 15 07:00:26 PM PDT 24 9372686651 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.553896421 Jul 15 06:59:38 PM PDT 24 Jul 15 06:59:53 PM PDT 24 1598159856 ps
T422 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3432468348 Jul 15 07:00:02 PM PDT 24 Jul 15 07:00:17 PM PDT 24 2036144972 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3543045276 Jul 15 06:59:42 PM PDT 24 Jul 15 06:59:55 PM PDT 24 11674273837 ps
T78 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1583139737 Jul 15 07:00:05 PM PDT 24 Jul 15 07:01:18 PM PDT 24 7833243674 ps
T424 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2106912844 Jul 15 07:00:11 PM PDT 24 Jul 15 07:00:20 PM PDT 24 1687921569 ps
T425 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3026541057 Jul 15 06:59:57 PM PDT 24 Jul 15 07:00:52 PM PDT 24 5903325988 ps
T108 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.69395532 Jul 15 07:00:05 PM PDT 24 Jul 15 07:01:22 PM PDT 24 1653033947 ps
T112 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3322362693 Jul 15 06:59:57 PM PDT 24 Jul 15 07:00:41 PM PDT 24 3531515650 ps
T426 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4141292289 Jul 15 07:00:03 PM PDT 24 Jul 15 07:00:10 PM PDT 24 165239165 ps
T79 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.830089225 Jul 15 06:59:43 PM PDT 24 Jul 15 07:00:49 PM PDT 24 29228627338 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1239571490 Jul 15 06:59:32 PM PDT 24 Jul 15 06:59:49 PM PDT 24 5628299363 ps
T83 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3658258291 Jul 15 06:59:41 PM PDT 24 Jul 15 07:00:19 PM PDT 24 6547301659 ps
T110 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2991776351 Jul 15 06:59:41 PM PDT 24 Jul 15 07:00:59 PM PDT 24 2138940250 ps
T428 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1452492751 Jul 15 06:59:57 PM PDT 24 Jul 15 07:00:06 PM PDT 24 1380600292 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.759756675 Jul 15 06:59:43 PM PDT 24 Jul 15 06:59:53 PM PDT 24 1806550315 ps
T429 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1727671456 Jul 15 06:59:48 PM PDT 24 Jul 15 06:59:56 PM PDT 24 468647024 ps
T111 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.894301811 Jul 15 06:59:29 PM PDT 24 Jul 15 07:00:42 PM PDT 24 493444016 ps
T430 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1492402544 Jul 15 06:59:51 PM PDT 24 Jul 15 07:00:06 PM PDT 24 8545393565 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.999769609 Jul 15 06:59:35 PM PDT 24 Jul 15 06:59:46 PM PDT 24 9534979918 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4097266288 Jul 15 06:59:44 PM PDT 24 Jul 15 07:00:59 PM PDT 24 1083606147 ps
T84 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2017471125 Jul 15 07:00:11 PM PDT 24 Jul 15 07:00:55 PM PDT 24 19470044257 ps
T433 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4210737653 Jul 15 06:59:57 PM PDT 24 Jul 15 07:00:02 PM PDT 24 829598877 ps
T434 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1213017025 Jul 15 06:59:42 PM PDT 24 Jul 15 06:59:49 PM PDT 24 385505416 ps
T109 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3719745725 Jul 15 07:00:00 PM PDT 24 Jul 15 07:01:18 PM PDT 24 3698807916 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1390744833 Jul 15 06:59:35 PM PDT 24 Jul 15 06:59:39 PM PDT 24 168077341 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2838427633 Jul 15 06:59:43 PM PDT 24 Jul 15 06:59:48 PM PDT 24 1879164120 ps
T436 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1315954898 Jul 15 06:59:46 PM PDT 24 Jul 15 06:59:55 PM PDT 24 877464378 ps
T437 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3128604960 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:02 PM PDT 24 3655468519 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1587321939 Jul 15 06:59:42 PM PDT 24 Jul 15 06:59:46 PM PDT 24 362117427 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.781910854 Jul 15 06:59:38 PM PDT 24 Jul 15 06:59:49 PM PDT 24 1683638997 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2694604484 Jul 15 06:59:36 PM PDT 24 Jul 15 06:59:40 PM PDT 24 168144717 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1407179382 Jul 15 06:59:42 PM PDT 24 Jul 15 06:59:47 PM PDT 24 85759682 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3795379108 Jul 15 06:59:34 PM PDT 24 Jul 15 06:59:42 PM PDT 24 310720541 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1155608911 Jul 15 06:59:46 PM PDT 24 Jul 15 06:59:57 PM PDT 24 7773502211 ps
T444 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3679603044 Jul 15 06:59:57 PM PDT 24 Jul 15 07:00:11 PM PDT 24 3043802771 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4121310100 Jul 15 06:59:52 PM PDT 24 Jul 15 06:59:59 PM PDT 24 909301139 ps
T446 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2548748850 Jul 15 06:59:45 PM PDT 24 Jul 15 07:00:56 PM PDT 24 643158059 ps
T447 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3911692325 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:33 PM PDT 24 5254463326 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4237913186 Jul 15 06:59:41 PM PDT 24 Jul 15 06:59:53 PM PDT 24 2227076500 ps
T448 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1305553279 Jul 15 06:59:48 PM PDT 24 Jul 15 07:00:04 PM PDT 24 1908625003 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3227055529 Jul 15 06:59:54 PM PDT 24 Jul 15 07:00:06 PM PDT 24 1122398958 ps
T450 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1544183005 Jul 15 07:00:02 PM PDT 24 Jul 15 07:00:14 PM PDT 24 1316224284 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2106371749 Jul 15 06:59:43 PM PDT 24 Jul 15 07:00:00 PM PDT 24 4380623695 ps
T452 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3009728215 Jul 15 06:59:57 PM PDT 24 Jul 15 07:01:08 PM PDT 24 1485995086 ps
T453 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2680856380 Jul 15 07:00:04 PM PDT 24 Jul 15 07:00:23 PM PDT 24 521152771 ps
T454 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.501115668 Jul 15 07:00:11 PM PDT 24 Jul 15 07:00:24 PM PDT 24 1103762889 ps
T455 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.319460391 Jul 15 06:59:51 PM PDT 24 Jul 15 07:00:03 PM PDT 24 1010764614 ps
T456 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1312416455 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:00 PM PDT 24 2097256609 ps
T82 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2973827284 Jul 15 07:00:05 PM PDT 24 Jul 15 07:00:10 PM PDT 24 520165772 ps
T457 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3357405182 Jul 15 06:59:46 PM PDT 24 Jul 15 07:00:55 PM PDT 24 858283830 ps
T458 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.274237179 Jul 15 06:59:50 PM PDT 24 Jul 15 07:00:03 PM PDT 24 1807297895 ps
T459 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1502058120 Jul 15 06:59:55 PM PDT 24 Jul 15 07:01:14 PM PDT 24 4043540873 ps
T460 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1272601030 Jul 15 06:59:45 PM PDT 24 Jul 15 06:59:57 PM PDT 24 1139089711 ps
T461 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4215721626 Jul 15 07:00:01 PM PDT 24 Jul 15 07:00:11 PM PDT 24 11271989808 ps
T462 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.854726713 Jul 15 06:59:51 PM PDT 24 Jul 15 07:00:10 PM PDT 24 22176711046 ps
T463 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4162748223 Jul 15 06:59:54 PM PDT 24 Jul 15 07:00:08 PM PDT 24 20506648281 ps
T464 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2520650117 Jul 15 07:00:01 PM PDT 24 Jul 15 07:00:07 PM PDT 24 169249516 ps

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2809931053
Short name T5
Test name
Test status
Simulation time 94132016007 ps
CPU time 499.22 seconds
Started Jul 15 05:49:13 PM PDT 24
Finished Jul 15 05:57:33 PM PDT 24
Peak memory 230352 kb
Host smart-f77357b0-d691-4987-ae22-eb70582f0d46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809931053 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2809931053
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.759919390
Short name T33
Test name
Test status
Simulation time 34833303865 ps
CPU time 375.92 seconds
Started Jul 15 05:49:43 PM PDT 24
Finished Jul 15 05:56:00 PM PDT 24
Peak memory 228496 kb
Host smart-504d6a5e-5a5e-411b-8b4b-0bd7c6dde2b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759919390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.759919390
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1804305631
Short name T11
Test name
Test status
Simulation time 22313524723 ps
CPU time 1492.74 seconds
Started Jul 15 05:49:21 PM PDT 24
Finished Jul 15 06:14:14 PM PDT 24
Peak memory 233508 kb
Host smart-2b9c098a-59e6-433c-aa9e-651e3803af51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804305631 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1804305631
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.396556694
Short name T38
Test name
Test status
Simulation time 73665220523 ps
CPU time 284.84 seconds
Started Jul 15 05:49:42 PM PDT 24
Finished Jul 15 05:54:29 PM PDT 24
Peak memory 237840 kb
Host smart-1f685ba2-b65b-4b48-8715-8fafcbf23422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396556694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.396556694
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2393808043
Short name T49
Test name
Test status
Simulation time 3508713436 ps
CPU time 70.52 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:57 PM PDT 24
Peak memory 212376 kb
Host smart-99a421c6-068f-4a0a-97b0-bfbe487b9568
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393808043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2393808043
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.748407743
Short name T3
Test name
Test status
Simulation time 143425815 ps
CPU time 6.8 seconds
Started Jul 15 05:49:37 PM PDT 24
Finished Jul 15 05:49:45 PM PDT 24
Peak memory 211284 kb
Host smart-6d20a8f2-3b92-459e-89c8-1927a94746b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748407743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.748407743
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1699486926
Short name T16
Test name
Test status
Simulation time 996984964 ps
CPU time 104.07 seconds
Started Jul 15 05:49:12 PM PDT 24
Finished Jul 15 05:50:58 PM PDT 24
Peak memory 237940 kb
Host smart-257e6e2d-0064-4d53-bf88-8a3d9e987d85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699486926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1699486926
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2208526884
Short name T66
Test name
Test status
Simulation time 22916232909 ps
CPU time 83.53 seconds
Started Jul 15 06:59:54 PM PDT 24
Finished Jul 15 07:01:18 PM PDT 24
Peak memory 211804 kb
Host smart-e0ae959e-8cd2-4f4f-8ef9-5cc2d6dd1d6c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208526884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2208526884
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.69395532
Short name T108
Test name
Test status
Simulation time 1653033947 ps
CPU time 76.37 seconds
Started Jul 15 07:00:05 PM PDT 24
Finished Jul 15 07:01:22 PM PDT 24
Peak memory 218936 kb
Host smart-d72f0921-9354-4e19-8508-7f40fcbb4f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69395532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_int
g_err.69395532
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.894301811
Short name T111
Test name
Test status
Simulation time 493444016 ps
CPU time 72.85 seconds
Started Jul 15 06:59:29 PM PDT 24
Finished Jul 15 07:00:42 PM PDT 24
Peak memory 212420 kb
Host smart-f378833b-53da-4334-92eb-3ead8cb73a85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894301811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.894301811
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.158185205
Short name T128
Test name
Test status
Simulation time 1514243492 ps
CPU time 7.3 seconds
Started Jul 15 05:49:11 PM PDT 24
Finished Jul 15 05:49:19 PM PDT 24
Peak memory 211284 kb
Host smart-f8faa98e-2cf6-4dcb-aaa5-f655d8c53817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158185205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.158185205
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.254355291
Short name T63
Test name
Test status
Simulation time 1969079557 ps
CPU time 29.32 seconds
Started Jul 15 06:59:41 PM PDT 24
Finished Jul 15 07:00:11 PM PDT 24
Peak memory 210696 kb
Host smart-8add7591-e452-4252-86c1-e98301a6863c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254355291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.254355291
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3515663625
Short name T125
Test name
Test status
Simulation time 2376963477 ps
CPU time 17.14 seconds
Started Jul 15 05:49:16 PM PDT 24
Finished Jul 15 05:49:34 PM PDT 24
Peak memory 211812 kb
Host smart-8df49126-551f-4beb-ab24-337b15557112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515663625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3515663625
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2069762319
Short name T146
Test name
Test status
Simulation time 693361755 ps
CPU time 9.6 seconds
Started Jul 15 05:49:10 PM PDT 24
Finished Jul 15 05:49:21 PM PDT 24
Peak memory 211852 kb
Host smart-fa4044d4-6ed9-4a28-a502-3d71da4d23ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069762319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2069762319
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4134724027
Short name T34
Test name
Test status
Simulation time 15953820006 ps
CPU time 249.91 seconds
Started Jul 15 05:49:36 PM PDT 24
Finished Jul 15 05:53:47 PM PDT 24
Peak memory 225660 kb
Host smart-0b39230b-f1f3-4f7a-a0ab-3e24df7c25c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134724027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4134724027
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2412998302
Short name T45
Test name
Test status
Simulation time 33588630456 ps
CPU time 2946.82 seconds
Started Jul 15 05:49:49 PM PDT 24
Finished Jul 15 06:38:56 PM PDT 24
Peak memory 235744 kb
Host smart-967897b9-1763-4b60-b154-3a88ec5f9415
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412998302 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2412998302
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.476667071
Short name T86
Test name
Test status
Simulation time 3915337529 ps
CPU time 16.83 seconds
Started Jul 15 05:50:29 PM PDT 24
Finished Jul 15 05:50:46 PM PDT 24
Peak memory 211384 kb
Host smart-c3af4632-bae6-400a-b9ca-7cd5f63c8399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476667071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.476667071
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.529614420
Short name T50
Test name
Test status
Simulation time 3023293640 ps
CPU time 70.04 seconds
Started Jul 15 06:59:34 PM PDT 24
Finished Jul 15 07:00:45 PM PDT 24
Peak memory 218944 kb
Host smart-e28d14b0-e0c9-4390-9058-453550b636ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529614420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.529614420
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2314845248
Short name T73
Test name
Test status
Simulation time 7949297022 ps
CPU time 72.85 seconds
Started Jul 15 05:49:04 PM PDT 24
Finished Jul 15 05:50:17 PM PDT 24
Peak memory 215844 kb
Host smart-961c8796-5b69-4e0e-8ba7-11e9ab187db7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314845248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2314845248
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2340082734
Short name T401
Test name
Test status
Simulation time 1407761375 ps
CPU time 12.25 seconds
Started Jul 15 06:59:39 PM PDT 24
Finished Jul 15 06:59:52 PM PDT 24
Peak memory 218260 kb
Host smart-b5075424-c4de-4980-b398-31f66eb9802f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340082734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2340082734
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2902706687
Short name T410
Test name
Test status
Simulation time 2879752840 ps
CPU time 11.59 seconds
Started Jul 15 06:59:39 PM PDT 24
Finished Jul 15 06:59:51 PM PDT 24
Peak memory 210808 kb
Host smart-125a5111-f029-4b9b-b232-1f8235f47fe7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902706687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2902706687
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2454955544
Short name T53
Test name
Test status
Simulation time 2153601885 ps
CPU time 10.57 seconds
Started Jul 15 06:59:35 PM PDT 24
Finished Jul 15 06:59:46 PM PDT 24
Peak memory 218568 kb
Host smart-6b403238-9118-4567-bcdc-a44d12ae1a90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454955544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2454955544
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2399872530
Short name T391
Test name
Test status
Simulation time 415159853 ps
CPU time 5.05 seconds
Started Jul 15 06:59:39 PM PDT 24
Finished Jul 15 06:59:45 PM PDT 24
Peak memory 218960 kb
Host smart-a6abcf1d-5d5d-46ed-a4cf-c61b2a3c3f16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399872530 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2399872530
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2827265297
Short name T419
Test name
Test status
Simulation time 1683193954 ps
CPU time 14.65 seconds
Started Jul 15 06:59:35 PM PDT 24
Finished Jul 15 06:59:50 PM PDT 24
Peak memory 210708 kb
Host smart-06d4392b-11b4-4578-abe7-c25c8aea47a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827265297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2827265297
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2694604484
Short name T440
Test name
Test status
Simulation time 168144717 ps
CPU time 4.14 seconds
Started Jul 15 06:59:36 PM PDT 24
Finished Jul 15 06:59:40 PM PDT 24
Peak memory 210556 kb
Host smart-6ff6fc3b-0e24-4336-8dbc-49605a00264a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694604484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2694604484
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.622246505
Short name T408
Test name
Test status
Simulation time 90971115 ps
CPU time 4.06 seconds
Started Jul 15 06:59:38 PM PDT 24
Finished Jul 15 06:59:42 PM PDT 24
Peak memory 210576 kb
Host smart-a1b26f23-1731-4da0-9881-d7d79ed1d3ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622246505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
622246505
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3679500496
Short name T100
Test name
Test status
Simulation time 29508696014 ps
CPU time 59.08 seconds
Started Jul 15 06:59:29 PM PDT 24
Finished Jul 15 07:00:29 PM PDT 24
Peak memory 210812 kb
Host smart-6d458f08-7bc3-4a96-a1b4-a44f45b6f9ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679500496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3679500496
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3795379108
Short name T442
Test name
Test status
Simulation time 310720541 ps
CPU time 7.88 seconds
Started Jul 15 06:59:34 PM PDT 24
Finished Jul 15 06:59:42 PM PDT 24
Peak memory 210800 kb
Host smart-3ca6baca-ce8b-4df5-8243-2554dafa7d87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795379108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3795379108
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1239571490
Short name T427
Test name
Test status
Simulation time 5628299363 ps
CPU time 16.53 seconds
Started Jul 15 06:59:32 PM PDT 24
Finished Jul 15 06:59:49 PM PDT 24
Peak memory 218980 kb
Host smart-e3aa4eb3-f6f5-4630-8616-232c1b0f6c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239571490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1239571490
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2106371749
Short name T451
Test name
Test status
Simulation time 4380623695 ps
CPU time 16.53 seconds
Started Jul 15 06:59:43 PM PDT 24
Finished Jul 15 07:00:00 PM PDT 24
Peak memory 218872 kb
Host smart-c0e1c54f-155f-4227-a94b-751020916cc8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106371749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2106371749
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1213017025
Short name T434
Test name
Test status
Simulation time 385505416 ps
CPU time 7.04 seconds
Started Jul 15 06:59:42 PM PDT 24
Finished Jul 15 06:59:49 PM PDT 24
Peak memory 210636 kb
Host smart-3400a48f-a7bf-4aa4-932b-c1241da297e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213017025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1213017025
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2017972525
Short name T384
Test name
Test status
Simulation time 1913630895 ps
CPU time 11.32 seconds
Started Jul 15 06:59:37 PM PDT 24
Finished Jul 15 06:59:49 PM PDT 24
Peak memory 216428 kb
Host smart-3c709b1b-ed03-4498-85c2-c539dd78d1ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017972525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2017972525
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4191388172
Short name T398
Test name
Test status
Simulation time 384241856 ps
CPU time 4.69 seconds
Started Jul 15 06:59:43 PM PDT 24
Finished Jul 15 06:59:48 PM PDT 24
Peak memory 218964 kb
Host smart-32022b86-7ee4-4916-a44a-02d1693802f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191388172 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4191388172
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1390744833
Short name T81
Test name
Test status
Simulation time 168077341 ps
CPU time 4.28 seconds
Started Jul 15 06:59:35 PM PDT 24
Finished Jul 15 06:59:39 PM PDT 24
Peak memory 217580 kb
Host smart-da42c72d-c617-4198-8ac5-3e0bfb1c9f0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390744833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1390744833
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3084583876
Short name T394
Test name
Test status
Simulation time 169515684 ps
CPU time 5.16 seconds
Started Jul 15 06:59:40 PM PDT 24
Finished Jul 15 06:59:45 PM PDT 24
Peak memory 210560 kb
Host smart-3ec85f9d-b7d4-4c77-8d0f-d24274372c04
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084583876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3084583876
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.999769609
Short name T431
Test name
Test status
Simulation time 9534979918 ps
CPU time 10.21 seconds
Started Jul 15 06:59:35 PM PDT 24
Finished Jul 15 06:59:46 PM PDT 24
Peak memory 210504 kb
Host smart-79c398a5-555f-4e26-ada7-3db5a3b392d7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999769609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
999769609
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3285607885
Short name T94
Test name
Test status
Simulation time 31243154192 ps
CPU time 44.4 seconds
Started Jul 15 06:59:39 PM PDT 24
Finished Jul 15 07:00:24 PM PDT 24
Peak memory 210796 kb
Host smart-13b2f932-24f5-47bf-8dd1-37c0105f9a58
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285607885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3285607885
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1155608911
Short name T443
Test name
Test status
Simulation time 7773502211 ps
CPU time 10.42 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 06:59:57 PM PDT 24
Peak memory 218976 kb
Host smart-2bac98a1-c337-4386-86db-b6025d1f4966
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155608911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1155608911
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2942112677
Short name T375
Test name
Test status
Simulation time 1361947811 ps
CPU time 15.16 seconds
Started Jul 15 06:59:34 PM PDT 24
Finished Jul 15 06:59:50 PM PDT 24
Peak memory 218976 kb
Host smart-47b46205-aa9b-4ef5-8a6a-877bbe8fe91c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942112677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2942112677
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.319460391
Short name T455
Test name
Test status
Simulation time 1010764614 ps
CPU time 11.36 seconds
Started Jul 15 06:59:51 PM PDT 24
Finished Jul 15 07:00:03 PM PDT 24
Peak memory 218876 kb
Host smart-667260c1-3d12-4750-a475-28f85b79a031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319460391 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.319460391
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1492402544
Short name T430
Test name
Test status
Simulation time 8545393565 ps
CPU time 14.68 seconds
Started Jul 15 06:59:51 PM PDT 24
Finished Jul 15 07:00:06 PM PDT 24
Peak memory 210724 kb
Host smart-136b15be-6e0c-485d-bda0-9edc097ccf5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492402544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1492402544
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4162748223
Short name T463
Test name
Test status
Simulation time 20506648281 ps
CPU time 13.32 seconds
Started Jul 15 06:59:54 PM PDT 24
Finished Jul 15 07:00:08 PM PDT 24
Peak memory 211192 kb
Host smart-90bc2360-c370-46b7-923b-c8080f6aea1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162748223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4162748223
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1519805566
Short name T385
Test name
Test status
Simulation time 18581200572 ps
CPU time 19.32 seconds
Started Jul 15 06:59:54 PM PDT 24
Finished Jul 15 07:00:14 PM PDT 24
Peak memory 219024 kb
Host smart-4e834ea4-8771-4e73-9958-d389ca188ea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519805566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1519805566
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1706578860
Short name T105
Test name
Test status
Simulation time 1074118892 ps
CPU time 71.28 seconds
Started Jul 15 06:59:51 PM PDT 24
Finished Jul 15 07:01:02 PM PDT 24
Peak memory 218944 kb
Host smart-ac5118ec-967d-4ce1-a78b-a9fa6e4a6674
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706578860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1706578860
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.52708034
Short name T411
Test name
Test status
Simulation time 433127708 ps
CPU time 4.29 seconds
Started Jul 15 06:59:51 PM PDT 24
Finished Jul 15 06:59:56 PM PDT 24
Peak memory 212264 kb
Host smart-4c07460a-10d1-4a77-9b67-e8faa312a4dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52708034 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.52708034
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.697406226
Short name T373
Test name
Test status
Simulation time 2762312985 ps
CPU time 8.64 seconds
Started Jul 15 06:59:51 PM PDT 24
Finished Jul 15 07:00:01 PM PDT 24
Peak memory 210736 kb
Host smart-2f24c031-27c2-4fe6-9e6f-3ca2ae15af86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697406226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.697406226
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.516503349
Short name T76
Test name
Test status
Simulation time 30348124785 ps
CPU time 50.44 seconds
Started Jul 15 06:59:53 PM PDT 24
Finished Jul 15 07:00:44 PM PDT 24
Peak memory 210784 kb
Host smart-e2cb22f3-cd71-4893-9f4e-c81310fcda20
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516503349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.516503349
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.343907400
Short name T93
Test name
Test status
Simulation time 7544509359 ps
CPU time 15.53 seconds
Started Jul 15 06:59:51 PM PDT 24
Finished Jul 15 07:00:07 PM PDT 24
Peak memory 210804 kb
Host smart-de39b9fa-f50d-4851-9e87-86225978bed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343907400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.343907400
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.274237179
Short name T458
Test name
Test status
Simulation time 1807297895 ps
CPU time 12.88 seconds
Started Jul 15 06:59:50 PM PDT 24
Finished Jul 15 07:00:03 PM PDT 24
Peak memory 215436 kb
Host smart-92dbd11b-3636-4e67-a2c3-bbba7c663185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274237179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.274237179
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1878879030
Short name T402
Test name
Test status
Simulation time 822491282 ps
CPU time 40.32 seconds
Started Jul 15 06:59:51 PM PDT 24
Finished Jul 15 07:00:32 PM PDT 24
Peak memory 218912 kb
Host smart-b6d529bc-e6fa-4665-8c8c-a8a82be334a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878879030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1878879030
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1452492751
Short name T428
Test name
Test status
Simulation time 1380600292 ps
CPU time 7.81 seconds
Started Jul 15 06:59:57 PM PDT 24
Finished Jul 15 07:00:06 PM PDT 24
Peak memory 219052 kb
Host smart-058b4e72-0219-42d1-9853-2ad38cc11b09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452492751 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1452492751
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3358011841
Short name T379
Test name
Test status
Simulation time 5660065479 ps
CPU time 11.3 seconds
Started Jul 15 06:59:58 PM PDT 24
Finished Jul 15 07:00:09 PM PDT 24
Peak memory 210680 kb
Host smart-06107c38-966d-41c8-8b7e-fe851ed97cdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358011841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3358011841
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.189913844
Short name T102
Test name
Test status
Simulation time 3291171196 ps
CPU time 46.54 seconds
Started Jul 15 06:59:50 PM PDT 24
Finished Jul 15 07:00:37 PM PDT 24
Peak memory 210788 kb
Host smart-e6eaa55e-0d78-4207-8d2e-67b2cbbcab9c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189913844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.189913844
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1530036591
Short name T90
Test name
Test status
Simulation time 171583374 ps
CPU time 4.35 seconds
Started Jul 15 06:59:57 PM PDT 24
Finished Jul 15 07:00:02 PM PDT 24
Peak memory 210756 kb
Host smart-8fda0495-9b3c-409c-9016-ac301013983e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530036591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1530036591
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.854726713
Short name T462
Test name
Test status
Simulation time 22176711046 ps
CPU time 18.96 seconds
Started Jul 15 06:59:51 PM PDT 24
Finished Jul 15 07:00:10 PM PDT 24
Peak memory 219016 kb
Host smart-18fbf333-42ca-4320-a871-ae95d3981a54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854726713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.854726713
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3412439909
Short name T107
Test name
Test status
Simulation time 2259096305 ps
CPU time 77.4 seconds
Started Jul 15 06:59:55 PM PDT 24
Finished Jul 15 07:01:12 PM PDT 24
Peak memory 219012 kb
Host smart-e35ced5f-5cb8-4e88-a347-118d632ede13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412439909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3412439909
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3679603044
Short name T444
Test name
Test status
Simulation time 3043802771 ps
CPU time 13.54 seconds
Started Jul 15 06:59:57 PM PDT 24
Finished Jul 15 07:00:11 PM PDT 24
Peak memory 218996 kb
Host smart-47c903be-5f9b-4b19-8bf6-a5ce5084006a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679603044 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3679603044
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.229622337
Short name T397
Test name
Test status
Simulation time 873148129 ps
CPU time 7.17 seconds
Started Jul 15 06:59:56 PM PDT 24
Finished Jul 15 07:00:04 PM PDT 24
Peak memory 210668 kb
Host smart-62d09629-04f0-4a9a-a8a1-081de2b1046e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229622337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.229622337
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2318347322
Short name T52
Test name
Test status
Simulation time 1209458814 ps
CPU time 18.67 seconds
Started Jul 15 06:59:58 PM PDT 24
Finished Jul 15 07:00:17 PM PDT 24
Peak memory 210728 kb
Host smart-01fbac5f-9593-420b-8728-1d8a2976465c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318347322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2318347322
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.767362053
Short name T400
Test name
Test status
Simulation time 1662186601 ps
CPU time 14.38 seconds
Started Jul 15 06:59:55 PM PDT 24
Finished Jul 15 07:00:10 PM PDT 24
Peak memory 218216 kb
Host smart-6b58fd22-b98c-4036-844a-11ca131a60f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767362053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.767362053
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1312312701
Short name T370
Test name
Test status
Simulation time 4015011898 ps
CPU time 17.45 seconds
Started Jul 15 06:59:56 PM PDT 24
Finished Jul 15 07:00:14 PM PDT 24
Peak memory 219044 kb
Host smart-19f511f4-d313-4abb-b46c-abfee85c558d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312312701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1312312701
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3009728215
Short name T452
Test name
Test status
Simulation time 1485995086 ps
CPU time 70.28 seconds
Started Jul 15 06:59:57 PM PDT 24
Finished Jul 15 07:01:08 PM PDT 24
Peak memory 212392 kb
Host smart-1a6a862c-4573-41fa-8323-7ea595655076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009728215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3009728215
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4165661991
Short name T415
Test name
Test status
Simulation time 1662745985 ps
CPU time 7.13 seconds
Started Jul 15 06:59:59 PM PDT 24
Finished Jul 15 07:00:07 PM PDT 24
Peak memory 218908 kb
Host smart-fec54518-d87f-4e58-9c2e-be977c20a520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165661991 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4165661991
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4210737653
Short name T433
Test name
Test status
Simulation time 829598877 ps
CPU time 4.27 seconds
Started Jul 15 06:59:57 PM PDT 24
Finished Jul 15 07:00:02 PM PDT 24
Peak memory 217984 kb
Host smart-705d02a7-ad39-439b-812d-f989c9679332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210737653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4210737653
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3343748411
Short name T418
Test name
Test status
Simulation time 376666191 ps
CPU time 18.37 seconds
Started Jul 15 06:59:57 PM PDT 24
Finished Jul 15 07:00:16 PM PDT 24
Peak memory 210768 kb
Host smart-55e091a0-3c97-49a7-8cca-18fb0bfaf67b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343748411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3343748411
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2210843965
Short name T416
Test name
Test status
Simulation time 1246619925 ps
CPU time 13.12 seconds
Started Jul 15 06:59:58 PM PDT 24
Finished Jul 15 07:00:12 PM PDT 24
Peak memory 218896 kb
Host smart-e32c418f-5a7e-4732-8301-30411cedaa0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210843965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2210843965
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.177610817
Short name T380
Test name
Test status
Simulation time 489122810 ps
CPU time 6.95 seconds
Started Jul 15 06:59:58 PM PDT 24
Finished Jul 15 07:00:06 PM PDT 24
Peak memory 218988 kb
Host smart-6cf99216-36ec-4cad-96a0-48987d253810
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177610817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.177610817
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1502058120
Short name T459
Test name
Test status
Simulation time 4043540873 ps
CPU time 78.88 seconds
Started Jul 15 06:59:55 PM PDT 24
Finished Jul 15 07:01:14 PM PDT 24
Peak memory 212272 kb
Host smart-866481b3-9035-4ca8-aa5b-0ab2c4bfc84c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502058120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1502058120
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1755837951
Short name T378
Test name
Test status
Simulation time 1786035088 ps
CPU time 14.97 seconds
Started Jul 15 07:00:01 PM PDT 24
Finished Jul 15 07:00:16 PM PDT 24
Peak memory 213144 kb
Host smart-c6fa5a04-2490-45ed-9a63-700fa92ff6ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755837951 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1755837951
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3432468348
Short name T422
Test name
Test status
Simulation time 2036144972 ps
CPU time 14.39 seconds
Started Jul 15 07:00:02 PM PDT 24
Finished Jul 15 07:00:17 PM PDT 24
Peak memory 217424 kb
Host smart-2ff5ac52-3048-4de8-aec3-c2cf8d533cf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432468348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3432468348
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3026541057
Short name T425
Test name
Test status
Simulation time 5903325988 ps
CPU time 54.8 seconds
Started Jul 15 06:59:57 PM PDT 24
Finished Jul 15 07:00:52 PM PDT 24
Peak memory 210780 kb
Host smart-d2e9589c-dd7e-44bf-b890-e6759ca8a395
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026541057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3026541057
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2412887599
Short name T95
Test name
Test status
Simulation time 1077888463 ps
CPU time 7.61 seconds
Started Jul 15 07:00:04 PM PDT 24
Finished Jul 15 07:00:12 PM PDT 24
Peak memory 210820 kb
Host smart-f65b368b-ce5f-4383-8bc2-369be8e963f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412887599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2412887599
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2456246113
Short name T376
Test name
Test status
Simulation time 1389347693 ps
CPU time 16.8 seconds
Started Jul 15 06:59:56 PM PDT 24
Finished Jul 15 07:00:13 PM PDT 24
Peak memory 218956 kb
Host smart-f1968fdd-9992-4229-bd60-6cbc91f3ddae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456246113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2456246113
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3322362693
Short name T112
Test name
Test status
Simulation time 3531515650 ps
CPU time 43.85 seconds
Started Jul 15 06:59:57 PM PDT 24
Finished Jul 15 07:00:41 PM PDT 24
Peak memory 211892 kb
Host smart-b40bb214-af65-4407-8575-f39dfe6c9987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322362693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3322362693
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2106912844
Short name T424
Test name
Test status
Simulation time 1687921569 ps
CPU time 8.58 seconds
Started Jul 15 07:00:11 PM PDT 24
Finished Jul 15 07:00:20 PM PDT 24
Peak memory 218976 kb
Host smart-be015775-97ef-46de-be65-12650a8faf37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106912844 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2106912844
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2087314814
Short name T62
Test name
Test status
Simulation time 2249473943 ps
CPU time 5.99 seconds
Started Jul 15 07:00:03 PM PDT 24
Finished Jul 15 07:00:10 PM PDT 24
Peak memory 210784 kb
Host smart-c15f2b1a-86b1-4349-ac24-5bfcc9353f3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087314814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2087314814
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2680856380
Short name T453
Test name
Test status
Simulation time 521152771 ps
CPU time 18.6 seconds
Started Jul 15 07:00:04 PM PDT 24
Finished Jul 15 07:00:23 PM PDT 24
Peak memory 210724 kb
Host smart-7090a073-33c8-47a8-ae01-ebc9cec51ca4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680856380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2680856380
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2652427848
Short name T97
Test name
Test status
Simulation time 29669809749 ps
CPU time 12.57 seconds
Started Jul 15 07:00:12 PM PDT 24
Finished Jul 15 07:00:25 PM PDT 24
Peak memory 218964 kb
Host smart-e0f17d0f-c04d-4002-a05f-80284cab8b39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652427848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2652427848
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2498782967
Short name T412
Test name
Test status
Simulation time 865839176 ps
CPU time 13.34 seconds
Started Jul 15 07:00:12 PM PDT 24
Finished Jul 15 07:00:26 PM PDT 24
Peak memory 218896 kb
Host smart-d34ed0b5-3b0f-4398-a49e-9d4fb723f87c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498782967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2498782967
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.314695245
Short name T106
Test name
Test status
Simulation time 332627828 ps
CPU time 36.23 seconds
Started Jul 15 07:00:04 PM PDT 24
Finished Jul 15 07:00:41 PM PDT 24
Peak memory 218912 kb
Host smart-ca4732df-be3d-477d-b05e-8fc4794b3b81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314695245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.314695245
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3183129397
Short name T413
Test name
Test status
Simulation time 2080494378 ps
CPU time 10.53 seconds
Started Jul 15 07:00:04 PM PDT 24
Finished Jul 15 07:00:15 PM PDT 24
Peak memory 215044 kb
Host smart-7f701511-6075-42da-b05f-4ec959f9cdbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183129397 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3183129397
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2006450031
Short name T61
Test name
Test status
Simulation time 1698022483 ps
CPU time 9.14 seconds
Started Jul 15 07:00:03 PM PDT 24
Finished Jul 15 07:00:13 PM PDT 24
Peak memory 218696 kb
Host smart-88f40058-a9fc-4a49-8ec2-6b0c1a0411d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006450031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2006450031
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2609546195
Short name T77
Test name
Test status
Simulation time 4600820918 ps
CPU time 42.21 seconds
Started Jul 15 07:00:05 PM PDT 24
Finished Jul 15 07:00:47 PM PDT 24
Peak memory 210768 kb
Host smart-057df2b4-ffa5-455d-92ab-cc25f8c91a2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609546195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2609546195
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1544183005
Short name T450
Test name
Test status
Simulation time 1316224284 ps
CPU time 11.84 seconds
Started Jul 15 07:00:02 PM PDT 24
Finished Jul 15 07:00:14 PM PDT 24
Peak memory 210780 kb
Host smart-e5bd67b5-2d31-4b19-9b55-8f79d3a7e63d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544183005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1544183005
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4141292289
Short name T426
Test name
Test status
Simulation time 165239165 ps
CPU time 6.41 seconds
Started Jul 15 07:00:03 PM PDT 24
Finished Jul 15 07:00:10 PM PDT 24
Peak memory 218904 kb
Host smart-397189bc-b1f3-45ff-878e-c9c9cf34a3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141292289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4141292289
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1433423683
Short name T51
Test name
Test status
Simulation time 2078985157 ps
CPU time 47.93 seconds
Started Jul 15 07:00:01 PM PDT 24
Finished Jul 15 07:00:50 PM PDT 24
Peak memory 212020 kb
Host smart-0ad480e2-4dd5-43eb-b281-828e06aa0a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433423683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1433423683
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2387570054
Short name T407
Test name
Test status
Simulation time 6098393164 ps
CPU time 13.72 seconds
Started Jul 15 07:00:02 PM PDT 24
Finished Jul 15 07:00:16 PM PDT 24
Peak memory 219064 kb
Host smart-5485cbce-8044-4a69-8d4c-f05ea7cdc22b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387570054 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2387570054
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2973827284
Short name T82
Test name
Test status
Simulation time 520165772 ps
CPU time 4.24 seconds
Started Jul 15 07:00:05 PM PDT 24
Finished Jul 15 07:00:10 PM PDT 24
Peak memory 218092 kb
Host smart-576a8266-015b-42fa-9ac7-3240ea908179
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973827284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2973827284
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2017471125
Short name T84
Test name
Test status
Simulation time 19470044257 ps
CPU time 43.41 seconds
Started Jul 15 07:00:11 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 210780 kb
Host smart-bf844345-4a2e-46e9-846b-6638d80e7efe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017471125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2017471125
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2520650117
Short name T464
Test name
Test status
Simulation time 169249516 ps
CPU time 5.47 seconds
Started Jul 15 07:00:01 PM PDT 24
Finished Jul 15 07:00:07 PM PDT 24
Peak memory 210760 kb
Host smart-1e5f4860-f993-4ec7-8d7f-67fb8b594f35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520650117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2520650117
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.501115668
Short name T454
Test name
Test status
Simulation time 1103762889 ps
CPU time 11.94 seconds
Started Jul 15 07:00:11 PM PDT 24
Finished Jul 15 07:00:24 PM PDT 24
Peak memory 218948 kb
Host smart-fd192db3-b95f-410a-b6f4-6ab5b1306313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501115668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.501115668
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.789897477
Short name T405
Test name
Test status
Simulation time 2325918335 ps
CPU time 13.04 seconds
Started Jul 15 07:00:02 PM PDT 24
Finished Jul 15 07:00:15 PM PDT 24
Peak memory 218992 kb
Host smart-9451f8b7-d967-48a5-af37-11e2951e9f55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789897477 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.789897477
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4215721626
Short name T461
Test name
Test status
Simulation time 11271989808 ps
CPU time 9.94 seconds
Started Jul 15 07:00:01 PM PDT 24
Finished Jul 15 07:00:11 PM PDT 24
Peak memory 218904 kb
Host smart-c862e802-f694-4116-a7dd-06d6bdc963bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215721626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4215721626
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1583139737
Short name T78
Test name
Test status
Simulation time 7833243674 ps
CPU time 73.41 seconds
Started Jul 15 07:00:05 PM PDT 24
Finished Jul 15 07:01:18 PM PDT 24
Peak memory 211780 kb
Host smart-e32c50fb-d3da-4664-b3a6-b5b099f1e3a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583139737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1583139737
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2114311872
Short name T420
Test name
Test status
Simulation time 9372686651 ps
CPU time 13.92 seconds
Started Jul 15 07:00:12 PM PDT 24
Finished Jul 15 07:00:26 PM PDT 24
Peak memory 218932 kb
Host smart-75e91340-0d9f-49ed-b693-e1d7f2f43c01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114311872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2114311872
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3448994314
Short name T390
Test name
Test status
Simulation time 5472513519 ps
CPU time 11.8 seconds
Started Jul 15 07:00:02 PM PDT 24
Finished Jul 15 07:00:15 PM PDT 24
Peak memory 219060 kb
Host smart-23fa32fd-0aad-48cc-9007-63ee49e72031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448994314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3448994314
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3719745725
Short name T109
Test name
Test status
Simulation time 3698807916 ps
CPU time 76.88 seconds
Started Jul 15 07:00:00 PM PDT 24
Finished Jul 15 07:01:18 PM PDT 24
Peak memory 211228 kb
Host smart-a78e9d09-978b-4696-9bbe-fedb4d0f2848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719745725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3719745725
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.759756675
Short name T80
Test name
Test status
Simulation time 1806550315 ps
CPU time 9.84 seconds
Started Jul 15 06:59:43 PM PDT 24
Finished Jul 15 06:59:53 PM PDT 24
Peak memory 210612 kb
Host smart-7aec91b7-54ae-4794-9309-477411515487
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759756675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.759756675
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3194054249
Short name T368
Test name
Test status
Simulation time 4858468153 ps
CPU time 11.18 seconds
Started Jul 15 06:59:45 PM PDT 24
Finished Jul 15 06:59:56 PM PDT 24
Peak memory 218556 kb
Host smart-f059ff0d-4ede-4a37-95b5-c9d873d97ef7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194054249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3194054249
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.553896421
Short name T421
Test name
Test status
Simulation time 1598159856 ps
CPU time 14.97 seconds
Started Jul 15 06:59:38 PM PDT 24
Finished Jul 15 06:59:53 PM PDT 24
Peak memory 210740 kb
Host smart-054890cc-ee00-4c74-88d2-d534ca052a1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553896421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.553896421
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2838427633
Short name T435
Test name
Test status
Simulation time 1879164120 ps
CPU time 4.8 seconds
Started Jul 15 06:59:43 PM PDT 24
Finished Jul 15 06:59:48 PM PDT 24
Peak memory 219000 kb
Host smart-971d3437-80cc-4f33-ac49-31f807189cf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838427633 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2838427633
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4237913186
Short name T85
Test name
Test status
Simulation time 2227076500 ps
CPU time 10.81 seconds
Started Jul 15 06:59:41 PM PDT 24
Finished Jul 15 06:59:53 PM PDT 24
Peak memory 210744 kb
Host smart-3032c189-6d3b-4387-b4ce-8de146e9260e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237913186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.4237913186
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1399376942
Short name T392
Test name
Test status
Simulation time 346961539 ps
CPU time 4.18 seconds
Started Jul 15 06:59:42 PM PDT 24
Finished Jul 15 06:59:47 PM PDT 24
Peak memory 210576 kb
Host smart-1fedc497-6016-4cbd-bff4-1c6aadcde8f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399376942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1399376942
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1587321939
Short name T438
Test name
Test status
Simulation time 362117427 ps
CPU time 4.09 seconds
Started Jul 15 06:59:42 PM PDT 24
Finished Jul 15 06:59:46 PM PDT 24
Peak memory 210540 kb
Host smart-9e1e4e35-e0b8-4c04-ac44-4f38bd8b0a50
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587321939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1587321939
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2625685349
Short name T92
Test name
Test status
Simulation time 7951513294 ps
CPU time 16.88 seconds
Started Jul 15 06:59:40 PM PDT 24
Finished Jul 15 06:59:57 PM PDT 24
Peak memory 210776 kb
Host smart-d4f02ef3-5b07-448a-92bc-b6a5a74fcffa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625685349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2625685349
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1318303035
Short name T417
Test name
Test status
Simulation time 8183580767 ps
CPU time 19.45 seconds
Started Jul 15 06:59:41 PM PDT 24
Finished Jul 15 07:00:01 PM PDT 24
Peak memory 218988 kb
Host smart-b0e5eafd-951f-43c7-9e53-2ad5918b9fff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318303035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1318303035
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3461682721
Short name T113
Test name
Test status
Simulation time 3545619104 ps
CPU time 40.89 seconds
Started Jul 15 06:59:41 PM PDT 24
Finished Jul 15 07:00:22 PM PDT 24
Peak memory 212188 kb
Host smart-703cac26-ac92-4f4b-87a3-b47dbe9ed2c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461682721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3461682721
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2106313865
Short name T68
Test name
Test status
Simulation time 962856988 ps
CPU time 10.41 seconds
Started Jul 15 06:59:41 PM PDT 24
Finished Jul 15 06:59:52 PM PDT 24
Peak memory 218228 kb
Host smart-7a4f154a-93be-4f74-a2af-ded1ac34abad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106313865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2106313865
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1731026241
Short name T377
Test name
Test status
Simulation time 1744258319 ps
CPU time 14.48 seconds
Started Jul 15 06:59:41 PM PDT 24
Finished Jul 15 06:59:56 PM PDT 24
Peak memory 210688 kb
Host smart-9e68bbdc-3ce4-41be-aece-20da418dae70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731026241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1731026241
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.873992803
Short name T396
Test name
Test status
Simulation time 12439141359 ps
CPU time 12.29 seconds
Started Jul 15 06:59:43 PM PDT 24
Finished Jul 15 06:59:56 PM PDT 24
Peak memory 210708 kb
Host smart-63e5acde-bf1d-487f-b961-97c32efd4a18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873992803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.873992803
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3174510737
Short name T414
Test name
Test status
Simulation time 6737920192 ps
CPU time 13.75 seconds
Started Jul 15 06:59:39 PM PDT 24
Finished Jul 15 06:59:53 PM PDT 24
Peak memory 219052 kb
Host smart-5b2d8768-e64c-4a59-9886-23d9a15c6167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174510737 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3174510737
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.430784207
Short name T69
Test name
Test status
Simulation time 1087561794 ps
CPU time 7.82 seconds
Started Jul 15 06:59:39 PM PDT 24
Finished Jul 15 06:59:47 PM PDT 24
Peak memory 210628 kb
Host smart-de43f0a3-5d8c-4ed9-88a6-12993cd3fd64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430784207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.430784207
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3543045276
Short name T423
Test name
Test status
Simulation time 11674273837 ps
CPU time 12.55 seconds
Started Jul 15 06:59:42 PM PDT 24
Finished Jul 15 06:59:55 PM PDT 24
Peak memory 210644 kb
Host smart-c44f4787-e899-4a55-b841-1a505e7c1da2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543045276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3543045276
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1322352307
Short name T387
Test name
Test status
Simulation time 3590867499 ps
CPU time 14.73 seconds
Started Jul 15 06:59:42 PM PDT 24
Finished Jul 15 06:59:58 PM PDT 24
Peak memory 210652 kb
Host smart-b915d88f-f469-4546-a383-c635e9c13cda
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322352307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1322352307
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.830089225
Short name T79
Test name
Test status
Simulation time 29228627338 ps
CPU time 65.36 seconds
Started Jul 15 06:59:43 PM PDT 24
Finished Jul 15 07:00:49 PM PDT 24
Peak memory 210684 kb
Host smart-ca15f2dd-7eea-4580-b268-39b9558ffb32
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830089225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.830089225
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4044721732
Short name T393
Test name
Test status
Simulation time 6377600812 ps
CPU time 13.84 seconds
Started Jul 15 06:59:39 PM PDT 24
Finished Jul 15 06:59:53 PM PDT 24
Peak memory 218928 kb
Host smart-c8a68a6e-430c-4c0e-8ae6-9a722d8ce45b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044721732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4044721732
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3915035862
Short name T371
Test name
Test status
Simulation time 2476865274 ps
CPU time 15.7 seconds
Started Jul 15 06:59:44 PM PDT 24
Finished Jul 15 07:00:00 PM PDT 24
Peak memory 218904 kb
Host smart-fb15881d-f62d-4616-8c28-9fde1647d874
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915035862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3915035862
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4097266288
Short name T432
Test name
Test status
Simulation time 1083606147 ps
CPU time 74.04 seconds
Started Jul 15 06:59:44 PM PDT 24
Finished Jul 15 07:00:59 PM PDT 24
Peak memory 211032 kb
Host smart-069ef109-bd61-4ea2-b332-0a766e0cead7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097266288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4097266288
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3429389672
Short name T64
Test name
Test status
Simulation time 5915064789 ps
CPU time 12.56 seconds
Started Jul 15 06:59:43 PM PDT 24
Finished Jul 15 06:59:56 PM PDT 24
Peak memory 210732 kb
Host smart-0375bb02-cab8-4f95-b07c-544f54eb7611
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429389672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3429389672
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1541312383
Short name T386
Test name
Test status
Simulation time 116368972 ps
CPU time 4.54 seconds
Started Jul 15 06:59:42 PM PDT 24
Finished Jul 15 06:59:47 PM PDT 24
Peak memory 210696 kb
Host smart-40732dc5-852f-460b-98e1-41378a1512bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541312383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1541312383
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1314286346
Short name T395
Test name
Test status
Simulation time 130729429 ps
CPU time 6.48 seconds
Started Jul 15 06:59:38 PM PDT 24
Finished Jul 15 06:59:45 PM PDT 24
Peak memory 218864 kb
Host smart-9c1ed19e-796c-4c9b-9d24-42a1e6d75d81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314286346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1314286346
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3227055529
Short name T449
Test name
Test status
Simulation time 1122398958 ps
CPU time 11.13 seconds
Started Jul 15 06:59:54 PM PDT 24
Finished Jul 15 07:00:06 PM PDT 24
Peak memory 218976 kb
Host smart-90f9838f-6fdf-4e58-bdf9-af854bcded40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227055529 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3227055529
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.781910854
Short name T439
Test name
Test status
Simulation time 1683638997 ps
CPU time 10.47 seconds
Started Jul 15 06:59:38 PM PDT 24
Finished Jul 15 06:59:49 PM PDT 24
Peak memory 217660 kb
Host smart-9b3e9d46-2b16-4b53-bf24-3c6c5216cb18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781910854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.781910854
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3485490920
Short name T409
Test name
Test status
Simulation time 1237094493 ps
CPU time 10.62 seconds
Started Jul 15 06:59:40 PM PDT 24
Finished Jul 15 06:59:51 PM PDT 24
Peak memory 210532 kb
Host smart-cfe63b3e-2787-49d3-971d-170fa621eec0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485490920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3485490920
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4276972690
Short name T365
Test name
Test status
Simulation time 334936738 ps
CPU time 5.48 seconds
Started Jul 15 06:59:43 PM PDT 24
Finished Jul 15 06:59:49 PM PDT 24
Peak memory 210536 kb
Host smart-42fb9616-e1d0-44e8-a4c7-f362e7615e0e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276972690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4276972690
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3658258291
Short name T83
Test name
Test status
Simulation time 6547301659 ps
CPU time 37.79 seconds
Started Jul 15 06:59:41 PM PDT 24
Finished Jul 15 07:00:19 PM PDT 24
Peak memory 210760 kb
Host smart-fecff084-9b34-4364-8c3b-e89ab5fd0d1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658258291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3658258291
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1407179382
Short name T441
Test name
Test status
Simulation time 85759682 ps
CPU time 4.42 seconds
Started Jul 15 06:59:42 PM PDT 24
Finished Jul 15 06:59:47 PM PDT 24
Peak memory 210812 kb
Host smart-9eeed094-28c4-4195-8c69-4ebeb2038db5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407179382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1407179382
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2378178386
Short name T366
Test name
Test status
Simulation time 557559849 ps
CPU time 9.33 seconds
Started Jul 15 06:59:40 PM PDT 24
Finished Jul 15 06:59:50 PM PDT 24
Peak memory 218956 kb
Host smart-85a998fd-1eed-4273-8e88-0cfbb852d9ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378178386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2378178386
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2991776351
Short name T110
Test name
Test status
Simulation time 2138940250 ps
CPU time 78.38 seconds
Started Jul 15 06:59:41 PM PDT 24
Finished Jul 15 07:00:59 PM PDT 24
Peak memory 218952 kb
Host smart-cf737dc9-dc96-48ad-b2fb-3a78719723f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991776351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2991776351
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1410949615
Short name T367
Test name
Test status
Simulation time 7620030316 ps
CPU time 14.67 seconds
Started Jul 15 06:59:45 PM PDT 24
Finished Jul 15 07:00:00 PM PDT 24
Peak memory 219032 kb
Host smart-4a798c3a-6766-4663-82c6-85da58b7d2ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410949615 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1410949615
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3128604960
Short name T437
Test name
Test status
Simulation time 3655468519 ps
CPU time 14.47 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:02 PM PDT 24
Peak memory 218900 kb
Host smart-d286e9aa-4baa-405a-abe9-96beab3e359e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128604960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3128604960
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3116107310
Short name T388
Test name
Test status
Simulation time 2648239205 ps
CPU time 45.21 seconds
Started Jul 15 06:59:48 PM PDT 24
Finished Jul 15 07:00:33 PM PDT 24
Peak memory 210788 kb
Host smart-ed6b714e-3cd3-484f-bcef-8e04b0c1e3f3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116107310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3116107310
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3043667945
Short name T67
Test name
Test status
Simulation time 1230929580 ps
CPU time 13.12 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:00 PM PDT 24
Peak memory 210780 kb
Host smart-c7f27ff0-c24b-42cc-85a8-6ba9d2215778
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043667945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3043667945
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1312416455
Short name T456
Test name
Test status
Simulation time 2097256609 ps
CPU time 13.04 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:00 PM PDT 24
Peak memory 218840 kb
Host smart-c15b7d71-d9a3-42a6-b7b4-f86d52a2ddec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312416455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1312416455
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.718673790
Short name T104
Test name
Test status
Simulation time 38601486397 ps
CPU time 48.11 seconds
Started Jul 15 06:59:45 PM PDT 24
Finished Jul 15 07:00:34 PM PDT 24
Peak memory 219056 kb
Host smart-709125d6-392f-44e0-8fd9-4ad9d1f531f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718673790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.718673790
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.705097385
Short name T382
Test name
Test status
Simulation time 3724479013 ps
CPU time 15.38 seconds
Started Jul 15 06:59:47 PM PDT 24
Finished Jul 15 07:00:03 PM PDT 24
Peak memory 219004 kb
Host smart-14693c3a-92e2-424f-a226-d125bde78f6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705097385 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.705097385
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3944048214
Short name T369
Test name
Test status
Simulation time 330433980 ps
CPU time 5.2 seconds
Started Jul 15 06:59:54 PM PDT 24
Finished Jul 15 07:00:00 PM PDT 24
Peak memory 210648 kb
Host smart-4c6f9266-dd09-414d-bf30-94be754685b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944048214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3944048214
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2173801803
Short name T96
Test name
Test status
Simulation time 8939379470 ps
CPU time 59.39 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:46 PM PDT 24
Peak memory 210672 kb
Host smart-8b3d4b38-6e86-4e54-8921-08e66425bc39
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173801803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2173801803
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1305553279
Short name T448
Test name
Test status
Simulation time 1908625003 ps
CPU time 14.77 seconds
Started Jul 15 06:59:48 PM PDT 24
Finished Jul 15 07:00:04 PM PDT 24
Peak memory 210788 kb
Host smart-0ef1a8c3-b16c-476f-9f0c-1f9fab6af453
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305553279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1305553279
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.880771790
Short name T389
Test name
Test status
Simulation time 198843207 ps
CPU time 9.59 seconds
Started Jul 15 06:59:48 PM PDT 24
Finished Jul 15 06:59:58 PM PDT 24
Peak memory 218960 kb
Host smart-b0cb1a90-2e6a-4864-8093-d33924051574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880771790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.880771790
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4232996179
Short name T381
Test name
Test status
Simulation time 689858441 ps
CPU time 7.56 seconds
Started Jul 15 06:59:48 PM PDT 24
Finished Jul 15 06:59:56 PM PDT 24
Peak memory 218976 kb
Host smart-2cecec5f-d4b7-46b9-9b28-47b0a9ad7ca3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232996179 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4232996179
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4191035043
Short name T404
Test name
Test status
Simulation time 2006739137 ps
CPU time 15.27 seconds
Started Jul 15 06:59:47 PM PDT 24
Finished Jul 15 07:00:03 PM PDT 24
Peak memory 218752 kb
Host smart-bc0e0e51-9177-425e-85fa-1118725fe040
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191035043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4191035043
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2536544299
Short name T383
Test name
Test status
Simulation time 4459765332 ps
CPU time 45.46 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:32 PM PDT 24
Peak memory 210812 kb
Host smart-c7191857-6eda-4509-8732-0af82ea10d50
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536544299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2536544299
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4121310100
Short name T445
Test name
Test status
Simulation time 909301139 ps
CPU time 7.08 seconds
Started Jul 15 06:59:52 PM PDT 24
Finished Jul 15 06:59:59 PM PDT 24
Peak memory 210776 kb
Host smart-6518fc96-04ed-4dcd-8d0a-8ce5bffd6303
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121310100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.4121310100
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3778522278
Short name T406
Test name
Test status
Simulation time 364749072 ps
CPU time 7.44 seconds
Started Jul 15 06:59:47 PM PDT 24
Finished Jul 15 06:59:55 PM PDT 24
Peak memory 218952 kb
Host smart-b981d525-cdb8-4b87-9a41-935f56d34ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778522278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3778522278
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3357405182
Short name T457
Test name
Test status
Simulation time 858283830 ps
CPU time 67.71 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:55 PM PDT 24
Peak memory 218896 kb
Host smart-042ce257-e557-4d8e-938b-8144c6755c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357405182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3357405182
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2447240647
Short name T372
Test name
Test status
Simulation time 203780775 ps
CPU time 4.97 seconds
Started Jul 15 06:59:48 PM PDT 24
Finished Jul 15 06:59:53 PM PDT 24
Peak memory 214552 kb
Host smart-5e8520a3-6720-401b-9b39-7e2375f0b304
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447240647 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2447240647
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1727671456
Short name T429
Test name
Test status
Simulation time 468647024 ps
CPU time 7.24 seconds
Started Jul 15 06:59:48 PM PDT 24
Finished Jul 15 06:59:56 PM PDT 24
Peak memory 217304 kb
Host smart-99d4f111-1466-40ba-9470-92116624c9de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727671456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1727671456
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.528376059
Short name T65
Test name
Test status
Simulation time 88362413336 ps
CPU time 67.27 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:54 PM PDT 24
Peak memory 210792 kb
Host smart-f033199b-dd99-4cfa-84b2-7330e25d9327
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528376059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.528376059
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.286088883
Short name T403
Test name
Test status
Simulation time 174944309 ps
CPU time 4.39 seconds
Started Jul 15 06:59:47 PM PDT 24
Finished Jul 15 06:59:52 PM PDT 24
Peak memory 218228 kb
Host smart-fdd5cf68-20d7-4e52-a52d-eaf83882df97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286088883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.286088883
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1315954898
Short name T436
Test name
Test status
Simulation time 877464378 ps
CPU time 8.28 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 06:59:55 PM PDT 24
Peak memory 218940 kb
Host smart-40c77271-f061-4b49-8594-dc994fa2c794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315954898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1315954898
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2548748850
Short name T446
Test name
Test status
Simulation time 643158059 ps
CPU time 69.99 seconds
Started Jul 15 06:59:45 PM PDT 24
Finished Jul 15 07:00:56 PM PDT 24
Peak memory 218912 kb
Host smart-7a6ba8c8-c8bd-4b29-99df-0ae13e76d0d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548748850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2548748850
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.93270055
Short name T399
Test name
Test status
Simulation time 3475623929 ps
CPU time 15.79 seconds
Started Jul 15 06:59:54 PM PDT 24
Finished Jul 15 07:00:10 PM PDT 24
Peak memory 219040 kb
Host smart-a4a9daa0-1da3-46f7-9a58-4f171b95ffb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93270055 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.93270055
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1272601030
Short name T460
Test name
Test status
Simulation time 1139089711 ps
CPU time 11.06 seconds
Started Jul 15 06:59:45 PM PDT 24
Finished Jul 15 06:59:57 PM PDT 24
Peak memory 210628 kb
Host smart-0538f861-486a-4084-bd0e-8ede763cd277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272601030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1272601030
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3911692325
Short name T447
Test name
Test status
Simulation time 5254463326 ps
CPU time 46.45 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:33 PM PDT 24
Peak memory 210832 kb
Host smart-8122e4db-4c93-444b-bac1-0124e4bebdd0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911692325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3911692325
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1781377541
Short name T91
Test name
Test status
Simulation time 4401386263 ps
CPU time 11.35 seconds
Started Jul 15 06:59:48 PM PDT 24
Finished Jul 15 07:00:00 PM PDT 24
Peak memory 218988 kb
Host smart-4b90aca0-8698-4149-81a7-830053f13064
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781377541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1781377541
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.47741355
Short name T374
Test name
Test status
Simulation time 1523524637 ps
CPU time 17.52 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:05 PM PDT 24
Peak memory 218948 kb
Host smart-0199312c-785c-4e36-b8ee-6fbc3f4488fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47741355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.47741355
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3590038155
Short name T103
Test name
Test status
Simulation time 2030819837 ps
CPU time 46.9 seconds
Started Jul 15 06:59:46 PM PDT 24
Finished Jul 15 07:00:34 PM PDT 24
Peak memory 211724 kb
Host smart-4bce04fd-5451-403a-9a0c-55e98777be26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590038155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3590038155
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4090372391
Short name T240
Test name
Test status
Simulation time 334343288 ps
CPU time 4.28 seconds
Started Jul 15 05:49:12 PM PDT 24
Finished Jul 15 05:49:17 PM PDT 24
Peak memory 211264 kb
Host smart-a24de373-af98-44ae-a09b-ed06b8149899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090372391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4090372391
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2667222300
Short name T149
Test name
Test status
Simulation time 8784981366 ps
CPU time 137.18 seconds
Started Jul 15 05:49:05 PM PDT 24
Finished Jul 15 05:51:23 PM PDT 24
Peak memory 236760 kb
Host smart-3640fd4f-987b-4dcd-b1df-5c7bf4bb0cbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667222300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2667222300
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.245758653
Short name T244
Test name
Test status
Simulation time 7461856938 ps
CPU time 30.71 seconds
Started Jul 15 05:49:03 PM PDT 24
Finished Jul 15 05:49:35 PM PDT 24
Peak memory 212592 kb
Host smart-9c66dbb6-fba7-46df-b2bc-4ac0d6cbceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245758653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.245758653
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.265669741
Short name T261
Test name
Test status
Simulation time 2037378186 ps
CPU time 11.99 seconds
Started Jul 15 05:49:03 PM PDT 24
Finished Jul 15 05:49:16 PM PDT 24
Peak memory 211360 kb
Host smart-54245c16-2922-4165-98ff-cf9fe7d08f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=265669741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.265669741
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.641715582
Short name T277
Test name
Test status
Simulation time 1379198489 ps
CPU time 18.24 seconds
Started Jul 15 05:49:07 PM PDT 24
Finished Jul 15 05:49:26 PM PDT 24
Peak memory 213708 kb
Host smart-1d56f29c-48e9-4489-9567-93d619e37f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641715582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.641715582
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3181438506
Short name T152
Test name
Test status
Simulation time 89714155373 ps
CPU time 240 seconds
Started Jul 15 05:49:10 PM PDT 24
Finished Jul 15 05:53:10 PM PDT 24
Peak memory 224940 kb
Host smart-d1a496ea-997e-4149-a19b-2900de5d91b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181438506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3181438506
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4035936726
Short name T184
Test name
Test status
Simulation time 3219495807 ps
CPU time 17.84 seconds
Started Jul 15 05:49:11 PM PDT 24
Finished Jul 15 05:49:30 PM PDT 24
Peak memory 211396 kb
Host smart-b0a16b9b-04af-4ba5-97aa-1cd9d20742c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035936726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4035936726
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4146832989
Short name T17
Test name
Test status
Simulation time 506359551 ps
CPU time 56.19 seconds
Started Jul 15 05:49:11 PM PDT 24
Finished Jul 15 05:50:08 PM PDT 24
Peak memory 236844 kb
Host smart-4122bd42-01d1-4678-b746-e8540b0c795d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146832989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4146832989
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1634087844
Short name T236
Test name
Test status
Simulation time 3514752624 ps
CPU time 33.14 seconds
Started Jul 15 05:49:11 PM PDT 24
Finished Jul 15 05:49:45 PM PDT 24
Peak memory 213960 kb
Host smart-1b0206f6-24d1-410e-8d67-e9c862eff041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634087844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1634087844
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2472967336
Short name T235
Test name
Test status
Simulation time 4328617955 ps
CPU time 31.75 seconds
Started Jul 15 05:49:10 PM PDT 24
Finished Jul 15 05:49:43 PM PDT 24
Peak memory 217556 kb
Host smart-1bc41c12-9421-423c-bed5-2a208bd76638
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472967336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2472967336
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1911609998
Short name T196
Test name
Test status
Simulation time 89156039 ps
CPU time 4.34 seconds
Started Jul 15 05:49:27 PM PDT 24
Finished Jul 15 05:49:32 PM PDT 24
Peak memory 211320 kb
Host smart-bb302588-4857-402c-8e04-9d08d34658f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911609998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1911609998
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.545877418
Short name T269
Test name
Test status
Simulation time 59269365931 ps
CPU time 211.5 seconds
Started Jul 15 05:49:28 PM PDT 24
Finished Jul 15 05:53:00 PM PDT 24
Peak memory 238044 kb
Host smart-10740ac7-618c-4d5d-9a50-33c63d17ad9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545877418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.545877418
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2949721972
Short name T155
Test name
Test status
Simulation time 8173299331 ps
CPU time 21.86 seconds
Started Jul 15 05:49:26 PM PDT 24
Finished Jul 15 05:49:48 PM PDT 24
Peak memory 212504 kb
Host smart-278dfc6f-73e8-4e2e-b02d-c2a9d798237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949721972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2949721972
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3047035055
Short name T306
Test name
Test status
Simulation time 39332380056 ps
CPU time 17.21 seconds
Started Jul 15 05:49:27 PM PDT 24
Finished Jul 15 05:49:45 PM PDT 24
Peak memory 211440 kb
Host smart-4101070b-5a99-496d-83e0-3a7f85a7b2dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047035055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3047035055
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2277888066
Short name T142
Test name
Test status
Simulation time 2682729456 ps
CPU time 17.76 seconds
Started Jul 15 05:49:33 PM PDT 24
Finished Jul 15 05:49:51 PM PDT 24
Peak memory 213780 kb
Host smart-7aac0840-b9ef-46ae-8f3d-6c86b91eb136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277888066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2277888066
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4025596695
Short name T230
Test name
Test status
Simulation time 16691776030 ps
CPU time 73.4 seconds
Started Jul 15 05:49:27 PM PDT 24
Finished Jul 15 05:50:41 PM PDT 24
Peak memory 216400 kb
Host smart-7b2573da-4fa5-4fca-a2b8-d175a6dd103e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025596695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4025596695
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2309575668
Short name T58
Test name
Test status
Simulation time 1186409368 ps
CPU time 4.32 seconds
Started Jul 15 05:49:28 PM PDT 24
Finished Jul 15 05:49:33 PM PDT 24
Peak memory 211276 kb
Host smart-be974669-45a6-4d17-a8bf-29acc5cc2ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309575668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2309575668
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3874911439
Short name T253
Test name
Test status
Simulation time 10360372948 ps
CPU time 157.91 seconds
Started Jul 15 05:49:32 PM PDT 24
Finished Jul 15 05:52:11 PM PDT 24
Peak memory 213512 kb
Host smart-c4e21951-9877-4edc-b301-60148a17a4df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874911439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3874911439
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2484328253
Short name T251
Test name
Test status
Simulation time 347761882 ps
CPU time 9.41 seconds
Started Jul 15 05:49:28 PM PDT 24
Finished Jul 15 05:49:38 PM PDT 24
Peak memory 212056 kb
Host smart-5091599a-1b4a-4517-a62e-5dc802b80a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484328253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2484328253
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2447733387
Short name T294
Test name
Test status
Simulation time 7118519271 ps
CPU time 15.62 seconds
Started Jul 15 05:49:28 PM PDT 24
Finished Jul 15 05:49:45 PM PDT 24
Peak memory 211416 kb
Host smart-5ef94d9e-8761-4605-b523-df8b6a691926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2447733387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2447733387
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2160754838
Short name T302
Test name
Test status
Simulation time 842733951 ps
CPU time 15.38 seconds
Started Jul 15 05:49:31 PM PDT 24
Finished Jul 15 05:49:47 PM PDT 24
Peak memory 213444 kb
Host smart-677b95f1-ed62-43c1-ae53-d31738ef6831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160754838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2160754838
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2280669097
Short name T305
Test name
Test status
Simulation time 1804178594 ps
CPU time 19.07 seconds
Started Jul 15 05:49:26 PM PDT 24
Finished Jul 15 05:49:46 PM PDT 24
Peak memory 211892 kb
Host smart-9ace6514-363e-49c1-9442-b60f0a76ed4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280669097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2280669097
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3731726274
Short name T19
Test name
Test status
Simulation time 89892712 ps
CPU time 4.34 seconds
Started Jul 15 05:49:42 PM PDT 24
Finished Jul 15 05:49:47 PM PDT 24
Peak memory 211468 kb
Host smart-5ebe6b80-7dd3-401b-8486-3b932bfaa5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731726274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3731726274
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2917205780
Short name T120
Test name
Test status
Simulation time 33767842454 ps
CPU time 377.88 seconds
Started Jul 15 05:49:33 PM PDT 24
Finished Jul 15 05:55:52 PM PDT 24
Peak memory 237812 kb
Host smart-0c179841-bb0c-46b9-b922-fd181173fb05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917205780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2917205780
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2110959752
Short name T28
Test name
Test status
Simulation time 1613096029 ps
CPU time 19.63 seconds
Started Jul 15 05:49:35 PM PDT 24
Finished Jul 15 05:49:56 PM PDT 24
Peak memory 211844 kb
Host smart-9dc9fc18-39d7-41b2-bed4-d8d117fa5da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110959752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2110959752
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1466954662
Short name T356
Test name
Test status
Simulation time 2015111551 ps
CPU time 17.03 seconds
Started Jul 15 05:49:33 PM PDT 24
Finished Jul 15 05:49:51 PM PDT 24
Peak memory 211312 kb
Host smart-da4bda45-2e14-4e24-be10-adad0695ccc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466954662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1466954662
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3770839791
Short name T351
Test name
Test status
Simulation time 1817540439 ps
CPU time 20.96 seconds
Started Jul 15 05:49:35 PM PDT 24
Finished Jul 15 05:49:56 PM PDT 24
Peak memory 213276 kb
Host smart-a8248af9-ac8b-47db-8c88-b848a1738bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770839791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3770839791
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1348184327
Short name T189
Test name
Test status
Simulation time 102238301598 ps
CPU time 90.19 seconds
Started Jul 15 05:49:34 PM PDT 24
Finished Jul 15 05:51:05 PM PDT 24
Peak memory 219356 kb
Host smart-7d504065-2706-45d1-8b6f-a2885964fd3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348184327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1348184327
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.176903853
Short name T57
Test name
Test status
Simulation time 1809542041 ps
CPU time 14.37 seconds
Started Jul 15 05:49:36 PM PDT 24
Finished Jul 15 05:49:50 PM PDT 24
Peak memory 211256 kb
Host smart-13c2d618-dff9-4580-a875-5479fa01a095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176903853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.176903853
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3353492269
Short name T316
Test name
Test status
Simulation time 11417402128 ps
CPU time 135.53 seconds
Started Jul 15 05:49:34 PM PDT 24
Finished Jul 15 05:51:50 PM PDT 24
Peak memory 224688 kb
Host smart-1c2bd87f-fd5e-4cb5-b994-e2c6f56b536c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353492269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3353492269
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.346393089
Short name T264
Test name
Test status
Simulation time 2678993239 ps
CPU time 25.07 seconds
Started Jul 15 05:49:41 PM PDT 24
Finished Jul 15 05:50:08 PM PDT 24
Peak memory 211884 kb
Host smart-bd209ff9-c88e-4a41-ab0f-171cac93a5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346393089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.346393089
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3898090408
Short name T208
Test name
Test status
Simulation time 98720080 ps
CPU time 5.56 seconds
Started Jul 15 05:49:39 PM PDT 24
Finished Jul 15 05:49:45 PM PDT 24
Peak memory 211272 kb
Host smart-36697031-261e-4bf3-ada1-0462a4e5fe6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898090408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3898090408
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3211118108
Short name T275
Test name
Test status
Simulation time 895901351 ps
CPU time 16.83 seconds
Started Jul 15 05:49:39 PM PDT 24
Finished Jul 15 05:49:57 PM PDT 24
Peak memory 213376 kb
Host smart-f6bba7c3-574b-4901-983c-5f01ff5e3566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211118108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3211118108
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2131232925
Short name T171
Test name
Test status
Simulation time 996212846 ps
CPU time 26.51 seconds
Started Jul 15 05:49:35 PM PDT 24
Finished Jul 15 05:50:02 PM PDT 24
Peak memory 215532 kb
Host smart-7e328d06-a8b5-4164-bc8a-a5468d13d6fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131232925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2131232925
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1561970562
Short name T150
Test name
Test status
Simulation time 585471264 ps
CPU time 8.26 seconds
Started Jul 15 05:49:35 PM PDT 24
Finished Jul 15 05:49:44 PM PDT 24
Peak memory 211288 kb
Host smart-0fa44b48-0ed0-4f4d-8362-777794508094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561970562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1561970562
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2421825732
Short name T156
Test name
Test status
Simulation time 1658287108 ps
CPU time 15.16 seconds
Started Jul 15 05:49:41 PM PDT 24
Finished Jul 15 05:49:58 PM PDT 24
Peak memory 212540 kb
Host smart-6da92bf6-24e6-42e4-ac45-dd53f7c05914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421825732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2421825732
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4028423154
Short name T256
Test name
Test status
Simulation time 361246315 ps
CPU time 5.46 seconds
Started Jul 15 05:49:35 PM PDT 24
Finished Jul 15 05:49:41 PM PDT 24
Peak memory 211316 kb
Host smart-1b918280-35c8-46fe-a73d-92d3e106d675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028423154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4028423154
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2754722283
Short name T258
Test name
Test status
Simulation time 16553483113 ps
CPU time 15.4 seconds
Started Jul 15 05:49:37 PM PDT 24
Finished Jul 15 05:49:53 PM PDT 24
Peak memory 214232 kb
Host smart-222d93dd-0926-407f-8627-520845f22925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754722283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2754722283
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4213460759
Short name T27
Test name
Test status
Simulation time 11908810646 ps
CPU time 12.64 seconds
Started Jul 15 05:49:42 PM PDT 24
Finished Jul 15 05:49:56 PM PDT 24
Peak memory 211320 kb
Host smart-9863e78c-8153-4c77-8409-9fa6daa9e08b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213460759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4213460759
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1429279819
Short name T119
Test name
Test status
Simulation time 109074038258 ps
CPU time 300.08 seconds
Started Jul 15 05:49:42 PM PDT 24
Finished Jul 15 05:54:44 PM PDT 24
Peak memory 212528 kb
Host smart-e5166c4e-d438-4301-b418-b6e28858b6a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429279819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1429279819
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.267813983
Short name T153
Test name
Test status
Simulation time 37631931088 ps
CPU time 28.43 seconds
Started Jul 15 05:49:42 PM PDT 24
Finished Jul 15 05:50:11 PM PDT 24
Peak memory 212184 kb
Host smart-8ce127f8-e528-4e07-9d39-1ee7a9b3f4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267813983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.267813983
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3685212623
Short name T266
Test name
Test status
Simulation time 1823829286 ps
CPU time 14.86 seconds
Started Jul 15 05:49:44 PM PDT 24
Finished Jul 15 05:50:00 PM PDT 24
Peak memory 210884 kb
Host smart-aa38c106-6960-4a5d-8fe9-e2f23f5f144e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685212623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3685212623
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3819592437
Short name T1
Test name
Test status
Simulation time 22590065011 ps
CPU time 23.17 seconds
Started Jul 15 05:49:39 PM PDT 24
Finished Jul 15 05:50:03 PM PDT 24
Peak memory 214332 kb
Host smart-d2ffcbc4-4c53-48db-86b4-7e883a71a90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819592437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3819592437
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1427057369
Short name T281
Test name
Test status
Simulation time 4298931744 ps
CPU time 33.49 seconds
Started Jul 15 05:49:34 PM PDT 24
Finished Jul 15 05:50:08 PM PDT 24
Peak memory 215832 kb
Host smart-5722fb74-78b2-4c8c-a9fc-b9e075cc6d47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427057369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1427057369
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3354792207
Short name T341
Test name
Test status
Simulation time 348217038 ps
CPU time 4.25 seconds
Started Jul 15 05:49:42 PM PDT 24
Finished Jul 15 05:49:47 PM PDT 24
Peak memory 211348 kb
Host smart-1d0b6dd3-44b5-4ca4-aa6d-d34f24c91863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354792207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3354792207
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1911870873
Short name T328
Test name
Test status
Simulation time 6046171165 ps
CPU time 28.31 seconds
Started Jul 15 05:49:42 PM PDT 24
Finished Jul 15 05:50:11 PM PDT 24
Peak memory 212204 kb
Host smart-1ae1a99c-aab3-4c0d-bc1d-f0ec695a3509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911870873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1911870873
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2290829650
Short name T182
Test name
Test status
Simulation time 896091927 ps
CPU time 10.49 seconds
Started Jul 15 05:49:40 PM PDT 24
Finished Jul 15 05:49:51 PM PDT 24
Peak memory 211272 kb
Host smart-ca1a755a-9423-4e56-bf14-9dc231eb7d5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290829650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2290829650
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4132335928
Short name T313
Test name
Test status
Simulation time 7387722429 ps
CPU time 30.07 seconds
Started Jul 15 05:49:43 PM PDT 24
Finished Jul 15 05:50:14 PM PDT 24
Peak memory 214404 kb
Host smart-aeb6019b-c6b5-4bf4-959a-70ea696dddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132335928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4132335928
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3165011045
Short name T145
Test name
Test status
Simulation time 3490227300 ps
CPU time 43.52 seconds
Started Jul 15 05:49:44 PM PDT 24
Finished Jul 15 05:50:29 PM PDT 24
Peak memory 214196 kb
Host smart-d2073d9f-9564-4079-b157-dd0aff3a59c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165011045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3165011045
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3800058216
Short name T347
Test name
Test status
Simulation time 1626640808 ps
CPU time 8.31 seconds
Started Jul 15 05:49:41 PM PDT 24
Finished Jul 15 05:49:50 PM PDT 24
Peak memory 211272 kb
Host smart-9eb9bd64-6523-4e64-9984-018fff74cf48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800058216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3800058216
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3865661786
Short name T18
Test name
Test status
Simulation time 58066426701 ps
CPU time 270.82 seconds
Started Jul 15 05:49:40 PM PDT 24
Finished Jul 15 05:54:11 PM PDT 24
Peak memory 224668 kb
Host smart-e8ba0023-d755-4c02-ab51-8f33090f4d2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865661786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3865661786
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1854594169
Short name T147
Test name
Test status
Simulation time 2841658376 ps
CPU time 18.47 seconds
Started Jul 15 05:49:44 PM PDT 24
Finished Jul 15 05:50:04 PM PDT 24
Peak memory 212100 kb
Host smart-b0758d79-bd74-495a-8af0-71d8c3137b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854594169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1854594169
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.271105088
Short name T362
Test name
Test status
Simulation time 1898298298 ps
CPU time 16.63 seconds
Started Jul 15 05:49:46 PM PDT 24
Finished Jul 15 05:50:03 PM PDT 24
Peak memory 211316 kb
Host smart-fb65b1e4-a752-49fa-b430-a89e663f4f8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271105088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.271105088
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1537609265
Short name T205
Test name
Test status
Simulation time 5968287428 ps
CPU time 27.31 seconds
Started Jul 15 05:49:43 PM PDT 24
Finished Jul 15 05:50:11 PM PDT 24
Peak memory 213444 kb
Host smart-8cf0251c-2f46-44f8-854f-897b90588c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537609265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1537609265
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.708245781
Short name T254
Test name
Test status
Simulation time 7581628008 ps
CPU time 25.24 seconds
Started Jul 15 05:49:43 PM PDT 24
Finished Jul 15 05:50:09 PM PDT 24
Peak memory 215040 kb
Host smart-5bf4f4f3-dc13-41d3-93f2-d1920eaf9dfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708245781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.708245781
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2364244209
Short name T299
Test name
Test status
Simulation time 5943587498 ps
CPU time 12.39 seconds
Started Jul 15 05:49:57 PM PDT 24
Finished Jul 15 05:50:10 PM PDT 24
Peak memory 211376 kb
Host smart-fd5d5673-74f7-4028-9006-15ad5f9c78d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364244209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2364244209
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3753590236
Short name T274
Test name
Test status
Simulation time 578605250 ps
CPU time 13.59 seconds
Started Jul 15 05:49:44 PM PDT 24
Finished Jul 15 05:49:59 PM PDT 24
Peak memory 211848 kb
Host smart-7dc15219-cbc3-429f-bbcf-59195d44d197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753590236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3753590236
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.895451321
Short name T285
Test name
Test status
Simulation time 13484027274 ps
CPU time 12.82 seconds
Started Jul 15 05:49:42 PM PDT 24
Finished Jul 15 05:49:56 PM PDT 24
Peak memory 211448 kb
Host smart-ec347680-66e5-44f9-bc75-59a06213ce24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895451321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.895451321
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1220205178
Short name T74
Test name
Test status
Simulation time 185378459 ps
CPU time 10.45 seconds
Started Jul 15 05:49:41 PM PDT 24
Finished Jul 15 05:49:52 PM PDT 24
Peak memory 213440 kb
Host smart-deabebc7-a5af-405c-83fb-04a9e9cc4f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220205178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1220205178
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1581572775
Short name T160
Test name
Test status
Simulation time 3324442018 ps
CPU time 51.86 seconds
Started Jul 15 05:49:43 PM PDT 24
Finished Jul 15 05:50:36 PM PDT 24
Peak memory 214716 kb
Host smart-f4a68c75-f345-490f-b5b0-40bc10641439
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581572775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1581572775
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1813864580
Short name T252
Test name
Test status
Simulation time 255767846 ps
CPU time 5.23 seconds
Started Jul 15 05:49:50 PM PDT 24
Finished Jul 15 05:49:56 PM PDT 24
Peak memory 211340 kb
Host smart-0b83404a-0913-4012-9f41-e646ff3a3c23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813864580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1813864580
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.96683119
Short name T121
Test name
Test status
Simulation time 8986857905 ps
CPU time 145.04 seconds
Started Jul 15 05:49:48 PM PDT 24
Finished Jul 15 05:52:13 PM PDT 24
Peak memory 237756 kb
Host smart-cfcc747e-9d73-4227-b4d4-aae8b1bfccd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96683119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_co
rrupt_sig_fatal_chk.96683119
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2139431755
Short name T340
Test name
Test status
Simulation time 2795105673 ps
CPU time 18.56 seconds
Started Jul 15 05:49:56 PM PDT 24
Finished Jul 15 05:50:15 PM PDT 24
Peak memory 211916 kb
Host smart-73ea78a1-0709-469a-aebe-f5cc112d6e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139431755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2139431755
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3976769738
Short name T161
Test name
Test status
Simulation time 996904107 ps
CPU time 11.06 seconds
Started Jul 15 05:49:56 PM PDT 24
Finished Jul 15 05:50:08 PM PDT 24
Peak memory 211348 kb
Host smart-ade943cf-261a-4496-ba0d-a5b2a0b462b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976769738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3976769738
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1817098390
Short name T361
Test name
Test status
Simulation time 3543152983 ps
CPU time 34.36 seconds
Started Jul 15 05:49:56 PM PDT 24
Finished Jul 15 05:50:32 PM PDT 24
Peak memory 213312 kb
Host smart-134b87a1-93a0-41d4-be7a-df89738a2060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817098390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1817098390
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2167346125
Short name T363
Test name
Test status
Simulation time 2830524900 ps
CPU time 28.99 seconds
Started Jul 15 05:49:56 PM PDT 24
Finished Jul 15 05:50:26 PM PDT 24
Peak memory 214432 kb
Host smart-1592c34a-2079-474a-ad0f-410373d17632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167346125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2167346125
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3843214961
Short name T354
Test name
Test status
Simulation time 5033621507 ps
CPU time 11.6 seconds
Started Jul 15 05:49:13 PM PDT 24
Finished Jul 15 05:49:26 PM PDT 24
Peak memory 211420 kb
Host smart-0e9cb449-60b6-451b-94a5-38663ffa2566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843214961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3843214961
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.405356728
Short name T222
Test name
Test status
Simulation time 53187355092 ps
CPU time 294.6 seconds
Started Jul 15 05:49:11 PM PDT 24
Finished Jul 15 05:54:07 PM PDT 24
Peak memory 213636 kb
Host smart-fa71e3ef-f9e0-4395-a809-b15a88167dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405356728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.405356728
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.63695862
Short name T154
Test name
Test status
Simulation time 3064846927 ps
CPU time 10.75 seconds
Started Jul 15 05:49:10 PM PDT 24
Finished Jul 15 05:49:21 PM PDT 24
Peak memory 211448 kb
Host smart-c83cbbc6-b71f-4974-9e6a-6ad7fc4d408c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=63695862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.63695862
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3051132591
Short name T24
Test name
Test status
Simulation time 2202929520 ps
CPU time 62.47 seconds
Started Jul 15 05:49:10 PM PDT 24
Finished Jul 15 05:50:13 PM PDT 24
Peak memory 237804 kb
Host smart-c4cfafa3-1743-45ac-9817-bed1c05c4309
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051132591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3051132591
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.4250811513
Short name T197
Test name
Test status
Simulation time 774037644 ps
CPU time 14.53 seconds
Started Jul 15 05:49:13 PM PDT 24
Finished Jul 15 05:49:29 PM PDT 24
Peak memory 213604 kb
Host smart-a784422a-d0a9-4e10-ab68-09e347ce1691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250811513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4250811513
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1334443155
Short name T216
Test name
Test status
Simulation time 2020028517 ps
CPU time 19.83 seconds
Started Jul 15 05:49:11 PM PDT 24
Finished Jul 15 05:49:32 PM PDT 24
Peak memory 212004 kb
Host smart-49c428de-769a-418f-bad5-559f881061f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334443155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1334443155
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3256114584
Short name T271
Test name
Test status
Simulation time 6128166284 ps
CPU time 64.62 seconds
Started Jul 15 05:49:11 PM PDT 24
Finished Jul 15 05:50:16 PM PDT 24
Peak memory 222308 kb
Host smart-b050b1c6-d0f6-4ec8-81de-cba3da936301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256114584 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3256114584
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3888602782
Short name T148
Test name
Test status
Simulation time 90818038 ps
CPU time 4.19 seconds
Started Jul 15 05:49:47 PM PDT 24
Finished Jul 15 05:49:52 PM PDT 24
Peak memory 211284 kb
Host smart-7ca779d1-394d-4f20-a4a3-cef1ddfb2d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888602782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3888602782
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.309196083
Short name T195
Test name
Test status
Simulation time 26888896790 ps
CPU time 168.2 seconds
Started Jul 15 05:49:48 PM PDT 24
Finished Jul 15 05:52:37 PM PDT 24
Peak memory 233888 kb
Host smart-3603c622-8818-4782-8ddd-6d7981291313
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309196083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.309196083
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4251563454
Short name T255
Test name
Test status
Simulation time 174766895 ps
CPU time 9.42 seconds
Started Jul 15 05:49:55 PM PDT 24
Finished Jul 15 05:50:06 PM PDT 24
Peak memory 212180 kb
Host smart-75abe516-7b34-4ddf-b7d3-ca91309e81c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251563454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4251563454
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1693666790
Short name T123
Test name
Test status
Simulation time 6123615781 ps
CPU time 12.06 seconds
Started Jul 15 05:49:48 PM PDT 24
Finished Jul 15 05:50:01 PM PDT 24
Peak memory 211352 kb
Host smart-79b1ff7f-47a3-4cf6-ad9b-b038fe43af53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693666790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1693666790
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3164565990
Short name T311
Test name
Test status
Simulation time 5094023004 ps
CPU time 32.81 seconds
Started Jul 15 05:49:49 PM PDT 24
Finished Jul 15 05:50:22 PM PDT 24
Peak memory 213584 kb
Host smart-3d77e5a8-3bd3-4642-936f-2b8f4eb8fbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164565990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3164565990
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2472628558
Short name T14
Test name
Test status
Simulation time 391227160 ps
CPU time 22.04 seconds
Started Jul 15 05:49:57 PM PDT 24
Finished Jul 15 05:50:19 PM PDT 24
Peak memory 215288 kb
Host smart-34879acf-9755-4992-bbef-c7376486cccc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472628558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2472628558
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2821447456
Short name T231
Test name
Test status
Simulation time 1866805872 ps
CPU time 16.05 seconds
Started Jul 15 05:49:56 PM PDT 24
Finished Jul 15 05:50:13 PM PDT 24
Peak memory 211336 kb
Host smart-e7177223-b9e2-4d9b-a07f-c9d86e1938c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821447456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2821447456
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2750087999
Short name T158
Test name
Test status
Simulation time 5554946186 ps
CPU time 105.14 seconds
Started Jul 15 05:49:54 PM PDT 24
Finished Jul 15 05:51:40 PM PDT 24
Peak memory 237808 kb
Host smart-bc4ac9fc-9c96-43ea-a191-44a458230bce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750087999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2750087999
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.846182429
Short name T174
Test name
Test status
Simulation time 3571347367 ps
CPU time 19.49 seconds
Started Jul 15 05:49:55 PM PDT 24
Finished Jul 15 05:50:16 PM PDT 24
Peak memory 212112 kb
Host smart-bad928ca-5d17-4a28-92c0-cd087d239273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846182429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.846182429
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2900504002
Short name T115
Test name
Test status
Simulation time 2227070887 ps
CPU time 11.68 seconds
Started Jul 15 05:49:55 PM PDT 24
Finished Jul 15 05:50:07 PM PDT 24
Peak memory 211376 kb
Host smart-ff91425a-1476-475a-b9d4-dd6d6d99a76b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900504002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2900504002
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3196389234
Short name T227
Test name
Test status
Simulation time 13710375234 ps
CPU time 20.48 seconds
Started Jul 15 05:49:49 PM PDT 24
Finished Jul 15 05:50:10 PM PDT 24
Peak memory 214064 kb
Host smart-415494dd-5019-4147-8589-1530544e8a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196389234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3196389234
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1462564958
Short name T29
Test name
Test status
Simulation time 1646167081 ps
CPU time 23.41 seconds
Started Jul 15 05:49:48 PM PDT 24
Finished Jul 15 05:50:12 PM PDT 24
Peak memory 213336 kb
Host smart-2d37b9e7-daff-495b-9346-cc62cf2dba67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462564958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1462564958
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3986574480
Short name T263
Test name
Test status
Simulation time 26552044756 ps
CPU time 16.51 seconds
Started Jul 15 05:49:56 PM PDT 24
Finished Jul 15 05:50:14 PM PDT 24
Peak memory 211380 kb
Host smart-0e614b11-c4dd-4ac3-adb0-5008bb40fd08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986574480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3986574480
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.998603220
Short name T348
Test name
Test status
Simulation time 15561639205 ps
CPU time 129.95 seconds
Started Jul 15 05:49:54 PM PDT 24
Finished Jul 15 05:52:05 PM PDT 24
Peak memory 225628 kb
Host smart-b5b9d2d0-161e-4989-866d-bddf69a2e78c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998603220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.998603220
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4065566693
Short name T243
Test name
Test status
Simulation time 12356977834 ps
CPU time 28.39 seconds
Started Jul 15 05:49:55 PM PDT 24
Finished Jul 15 05:50:25 PM PDT 24
Peak memory 212212 kb
Host smart-7ae655bb-025b-445c-969c-cfa99c0a1b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065566693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4065566693
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2254259461
Short name T357
Test name
Test status
Simulation time 970818266 ps
CPU time 11.2 seconds
Started Jul 15 05:49:55 PM PDT 24
Finished Jul 15 05:50:07 PM PDT 24
Peak memory 211340 kb
Host smart-873111f6-6af3-4faf-a1a5-3f6abed9b498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254259461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2254259461
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1685612656
Short name T25
Test name
Test status
Simulation time 189181274 ps
CPU time 10.65 seconds
Started Jul 15 05:50:01 PM PDT 24
Finished Jul 15 05:50:12 PM PDT 24
Peak memory 213420 kb
Host smart-8d0f4d56-5f22-4d77-856f-cd14a28b089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685612656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1685612656
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.501948195
Short name T31
Test name
Test status
Simulation time 3744135029 ps
CPU time 65.26 seconds
Started Jul 15 05:49:54 PM PDT 24
Finished Jul 15 05:51:00 PM PDT 24
Peak memory 216640 kb
Host smart-5204885c-6ef9-4127-be1a-7feae2d799d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501948195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.501948195
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.4281954219
Short name T190
Test name
Test status
Simulation time 2717683432 ps
CPU time 12.2 seconds
Started Jul 15 05:49:58 PM PDT 24
Finished Jul 15 05:50:10 PM PDT 24
Peak memory 211380 kb
Host smart-e2006992-00fd-41d2-81fa-89cfb7c781b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281954219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4281954219
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.13222493
Short name T198
Test name
Test status
Simulation time 56291799496 ps
CPU time 172.11 seconds
Started Jul 15 05:50:01 PM PDT 24
Finished Jul 15 05:52:53 PM PDT 24
Peak memory 237336 kb
Host smart-ce00367f-a698-4766-8c80-d7bfb53e38e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13222493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_co
rrupt_sig_fatal_chk.13222493
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3757357749
Short name T22
Test name
Test status
Simulation time 8908711443 ps
CPU time 23.89 seconds
Started Jul 15 05:49:56 PM PDT 24
Finished Jul 15 05:50:21 PM PDT 24
Peak memory 212344 kb
Host smart-7f17908a-04f5-46ee-8e77-f62ba2472862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757357749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3757357749
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4269158059
Short name T225
Test name
Test status
Simulation time 1072939168 ps
CPU time 12.29 seconds
Started Jul 15 05:49:54 PM PDT 24
Finished Jul 15 05:50:07 PM PDT 24
Peak memory 211292 kb
Host smart-b63fa874-8ec4-4122-a488-a20d4d381806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4269158059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4269158059
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.128934104
Short name T201
Test name
Test status
Simulation time 187105815 ps
CPU time 10.1 seconds
Started Jul 15 05:49:55 PM PDT 24
Finished Jul 15 05:50:06 PM PDT 24
Peak memory 212912 kb
Host smart-54e9957d-2363-4fa7-a234-e4390461093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128934104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.128934104
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.602257568
Short name T7
Test name
Test status
Simulation time 3488424544 ps
CPU time 18.48 seconds
Started Jul 15 05:49:55 PM PDT 24
Finished Jul 15 05:50:15 PM PDT 24
Peak memory 211284 kb
Host smart-670b815e-023a-424b-8d77-1191690a64c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602257568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.602257568
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3642288498
Short name T192
Test name
Test status
Simulation time 333569802 ps
CPU time 4.34 seconds
Started Jul 15 05:50:03 PM PDT 24
Finished Jul 15 05:50:08 PM PDT 24
Peak memory 211348 kb
Host smart-9c42cfa0-58cd-4bf7-b148-556191e5a8d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642288498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3642288498
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3317330532
Short name T172
Test name
Test status
Simulation time 372969356598 ps
CPU time 316.31 seconds
Started Jul 15 05:49:58 PM PDT 24
Finished Jul 15 05:55:15 PM PDT 24
Peak memory 228348 kb
Host smart-56765ad2-77cb-4d31-83d0-f985253323ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317330532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3317330532
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3240240936
Short name T218
Test name
Test status
Simulation time 26852075985 ps
CPU time 31.24 seconds
Started Jul 15 05:49:54 PM PDT 24
Finished Jul 15 05:50:27 PM PDT 24
Peak memory 212184 kb
Host smart-0a950c0e-a79e-45bb-8695-4a7d0ae5abbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240240936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3240240936
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3151352522
Short name T226
Test name
Test status
Simulation time 589793216 ps
CPU time 8.9 seconds
Started Jul 15 05:49:57 PM PDT 24
Finished Jul 15 05:50:06 PM PDT 24
Peak memory 211288 kb
Host smart-dcf08aaf-4892-4f5d-a778-f2567f798031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3151352522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3151352522
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1372273666
Short name T131
Test name
Test status
Simulation time 6971395312 ps
CPU time 27.7 seconds
Started Jul 15 05:49:55 PM PDT 24
Finished Jul 15 05:50:24 PM PDT 24
Peak memory 213892 kb
Host smart-9ced716f-df54-4c64-a5e1-d7172621d3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372273666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1372273666
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3971845083
Short name T169
Test name
Test status
Simulation time 969393318 ps
CPU time 12.65 seconds
Started Jul 15 05:50:02 PM PDT 24
Finished Jul 15 05:50:15 PM PDT 24
Peak memory 211396 kb
Host smart-46ece4c0-6a5e-42a8-b77b-e113c0fb2cc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971845083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3971845083
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3152250763
Short name T48
Test name
Test status
Simulation time 121157037783 ps
CPU time 367.46 seconds
Started Jul 15 05:49:55 PM PDT 24
Finished Jul 15 05:56:03 PM PDT 24
Peak memory 228888 kb
Host smart-57c3e2fa-66a2-4c6d-9bbb-defb6ef3a418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152250763 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3152250763
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.561729970
Short name T163
Test name
Test status
Simulation time 85445948 ps
CPU time 4.35 seconds
Started Jul 15 05:50:04 PM PDT 24
Finished Jul 15 05:50:09 PM PDT 24
Peak memory 211336 kb
Host smart-a3a4395c-2ca5-4f59-80ab-70488ff58a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561729970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.561729970
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1220831408
Short name T352
Test name
Test status
Simulation time 13331377128 ps
CPU time 125.17 seconds
Started Jul 15 05:50:05 PM PDT 24
Finished Jul 15 05:52:11 PM PDT 24
Peak memory 233760 kb
Host smart-db742442-8748-4fef-8eab-823a5a23c97a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220831408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1220831408
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2772788759
Short name T144
Test name
Test status
Simulation time 2211493257 ps
CPU time 22.3 seconds
Started Jul 15 05:50:02 PM PDT 24
Finished Jul 15 05:50:24 PM PDT 24
Peak memory 211844 kb
Host smart-b48c994a-d70e-484a-8a44-94a954711c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772788759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2772788759
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3056282569
Short name T183
Test name
Test status
Simulation time 4814626881 ps
CPU time 12.5 seconds
Started Jul 15 05:50:01 PM PDT 24
Finished Jul 15 05:50:14 PM PDT 24
Peak memory 211396 kb
Host smart-85df978d-019b-4a8c-a61b-481c5a02dbf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3056282569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3056282569
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.967054980
Short name T290
Test name
Test status
Simulation time 3624124568 ps
CPU time 38.67 seconds
Started Jul 15 05:50:05 PM PDT 24
Finished Jul 15 05:50:45 PM PDT 24
Peak memory 214044 kb
Host smart-5f1ee16f-2ae0-4a02-b1de-35152e965ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967054980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.967054980
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.402626148
Short name T232
Test name
Test status
Simulation time 9609424244 ps
CPU time 98.12 seconds
Started Jul 15 05:50:07 PM PDT 24
Finished Jul 15 05:51:45 PM PDT 24
Peak memory 219332 kb
Host smart-03e5a455-bf10-4977-aa64-dec0021cc093
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402626148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.402626148
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.334186397
Short name T283
Test name
Test status
Simulation time 495285230 ps
CPU time 7.57 seconds
Started Jul 15 05:50:06 PM PDT 24
Finished Jul 15 05:50:14 PM PDT 24
Peak memory 211260 kb
Host smart-001fad30-e8fc-439f-88a1-5e60173fe3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334186397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.334186397
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.750112505
Short name T4
Test name
Test status
Simulation time 7073145365 ps
CPU time 121.47 seconds
Started Jul 15 05:50:04 PM PDT 24
Finished Jul 15 05:52:06 PM PDT 24
Peak memory 237676 kb
Host smart-b7bada8f-9940-4519-93b4-eb889dc8732a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750112505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.750112505
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3584465648
Short name T343
Test name
Test status
Simulation time 792928343 ps
CPU time 9.33 seconds
Started Jul 15 05:50:05 PM PDT 24
Finished Jul 15 05:50:16 PM PDT 24
Peak memory 212140 kb
Host smart-a7a58251-7a8d-4526-8948-345c0ecda09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584465648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3584465648
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1885460334
Short name T98
Test name
Test status
Simulation time 1656600163 ps
CPU time 14.89 seconds
Started Jul 15 05:50:04 PM PDT 24
Finished Jul 15 05:50:20 PM PDT 24
Peak memory 211368 kb
Host smart-01520d0d-2d15-4fdc-8ec5-db57d31b1958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885460334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1885460334
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1172479288
Short name T346
Test name
Test status
Simulation time 10332459003 ps
CPU time 33.74 seconds
Started Jul 15 05:50:04 PM PDT 24
Finished Jul 15 05:50:38 PM PDT 24
Peak memory 215484 kb
Host smart-3b783e09-6e41-4030-994c-1e5bc095c418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172479288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1172479288
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2878839176
Short name T187
Test name
Test status
Simulation time 661967471 ps
CPU time 11.49 seconds
Started Jul 15 05:50:03 PM PDT 24
Finished Jul 15 05:50:16 PM PDT 24
Peak memory 212384 kb
Host smart-78bec930-7e24-43c9-8b13-ca59d40532ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878839176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2878839176
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2600047999
Short name T289
Test name
Test status
Simulation time 80015961636 ps
CPU time 6656.93 seconds
Started Jul 15 05:50:05 PM PDT 24
Finished Jul 15 07:41:03 PM PDT 24
Peak memory 231108 kb
Host smart-21d08fd4-8e3a-4907-8232-3df6b7b75d02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600047999 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2600047999
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1422875545
Short name T212
Test name
Test status
Simulation time 1879134703 ps
CPU time 5.71 seconds
Started Jul 15 05:50:05 PM PDT 24
Finished Jul 15 05:50:12 PM PDT 24
Peak memory 211268 kb
Host smart-5b1d1e5f-0b80-4446-96b4-763381d26f2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422875545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1422875545
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.219126804
Short name T224
Test name
Test status
Simulation time 25369903340 ps
CPU time 134.47 seconds
Started Jul 15 05:50:04 PM PDT 24
Finished Jul 15 05:52:20 PM PDT 24
Peak memory 225640 kb
Host smart-17a67ee3-9f6a-459a-8505-d210a0ca2054
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219126804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.219126804
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3632378875
Short name T321
Test name
Test status
Simulation time 4814378560 ps
CPU time 15.36 seconds
Started Jul 15 05:50:06 PM PDT 24
Finished Jul 15 05:50:22 PM PDT 24
Peak memory 212304 kb
Host smart-ec39d8b4-2236-40b4-abaa-3f3a621d0a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632378875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3632378875
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1638553189
Short name T170
Test name
Test status
Simulation time 5242312427 ps
CPU time 13.65 seconds
Started Jul 15 05:50:04 PM PDT 24
Finished Jul 15 05:50:18 PM PDT 24
Peak memory 211372 kb
Host smart-3a20d3e0-49bc-4ce8-afdd-02588f29bcec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638553189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1638553189
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2659147895
Short name T247
Test name
Test status
Simulation time 4669297697 ps
CPU time 30.29 seconds
Started Jul 15 05:50:03 PM PDT 24
Finished Jul 15 05:50:34 PM PDT 24
Peak memory 213844 kb
Host smart-72147926-9791-4a56-9c3d-3c1906f06acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659147895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2659147895
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3277507817
Short name T203
Test name
Test status
Simulation time 3525113027 ps
CPU time 34.72 seconds
Started Jul 15 05:50:07 PM PDT 24
Finished Jul 15 05:50:42 PM PDT 24
Peak memory 216792 kb
Host smart-d03ff4d9-d8ab-4707-a88d-20aa267dbcb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277507817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3277507817
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2703814013
Short name T334
Test name
Test status
Simulation time 85735274256 ps
CPU time 1305.92 seconds
Started Jul 15 05:50:04 PM PDT 24
Finished Jul 15 06:11:51 PM PDT 24
Peak memory 228960 kb
Host smart-e13ab04a-005e-40c1-89da-dc94ae71b76a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703814013 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2703814013
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3670332078
Short name T127
Test name
Test status
Simulation time 174983634 ps
CPU time 4.41 seconds
Started Jul 15 05:50:04 PM PDT 24
Finished Jul 15 05:50:09 PM PDT 24
Peak memory 211232 kb
Host smart-a52b0889-d37e-4515-a050-2e0e97ff6db6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670332078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3670332078
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3273121639
Short name T180
Test name
Test status
Simulation time 18080585412 ps
CPU time 201.21 seconds
Started Jul 15 05:50:03 PM PDT 24
Finished Jul 15 05:53:26 PM PDT 24
Peak memory 233768 kb
Host smart-57a07f8e-52b3-4391-a125-9f3d4dabffea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273121639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3273121639
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2968684937
Short name T326
Test name
Test status
Simulation time 12736116943 ps
CPU time 28.09 seconds
Started Jul 15 05:50:03 PM PDT 24
Finished Jul 15 05:50:31 PM PDT 24
Peak memory 212256 kb
Host smart-7f18f5eb-70e8-48e7-b3e3-fbb0bb9a1ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968684937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2968684937
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.836621520
Short name T177
Test name
Test status
Simulation time 658431357 ps
CPU time 5.62 seconds
Started Jul 15 05:50:03 PM PDT 24
Finished Jul 15 05:50:10 PM PDT 24
Peak memory 211296 kb
Host smart-56305595-b9a6-417b-8ac2-e8035a65ec51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836621520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.836621520
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3635681842
Short name T72
Test name
Test status
Simulation time 29396987807 ps
CPU time 29.4 seconds
Started Jul 15 05:50:03 PM PDT 24
Finished Jul 15 05:50:33 PM PDT 24
Peak memory 214392 kb
Host smart-1e1a5435-40a7-4838-a65b-d688de48b9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635681842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3635681842
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.359884297
Short name T279
Test name
Test status
Simulation time 11043518735 ps
CPU time 39.62 seconds
Started Jul 15 05:50:06 PM PDT 24
Finished Jul 15 05:50:46 PM PDT 24
Peak memory 214996 kb
Host smart-9a66d799-da64-46ca-873d-9be45ba51f62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359884297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.359884297
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3237803620
Short name T130
Test name
Test status
Simulation time 1892413201 ps
CPU time 13.33 seconds
Started Jul 15 05:50:11 PM PDT 24
Finished Jul 15 05:50:26 PM PDT 24
Peak memory 211272 kb
Host smart-6b2a3ece-583c-4d31-a60e-25e4075554fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237803620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3237803620
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2663869128
Short name T162
Test name
Test status
Simulation time 150525941752 ps
CPU time 507.35 seconds
Started Jul 15 05:50:11 PM PDT 24
Finished Jul 15 05:58:39 PM PDT 24
Peak memory 225180 kb
Host smart-d3c69d3b-b6d7-4b13-9294-207f6521a782
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663869128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2663869128
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.94430975
Short name T238
Test name
Test status
Simulation time 10209250486 ps
CPU time 24.9 seconds
Started Jul 15 05:50:12 PM PDT 24
Finished Jul 15 05:50:39 PM PDT 24
Peak memory 211444 kb
Host smart-1c11d44f-6655-461c-889d-add9f75704ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94430975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.94430975
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2495979465
Short name T307
Test name
Test status
Simulation time 1263247523 ps
CPU time 9.34 seconds
Started Jul 15 05:50:02 PM PDT 24
Finished Jul 15 05:50:12 PM PDT 24
Peak memory 211320 kb
Host smart-b9c07e51-3669-4f10-97a5-9c19a9472cdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2495979465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2495979465
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2488548600
Short name T204
Test name
Test status
Simulation time 1171469002 ps
CPU time 19.74 seconds
Started Jul 15 05:50:05 PM PDT 24
Finished Jul 15 05:50:26 PM PDT 24
Peak memory 213712 kb
Host smart-f95ecdd1-dfee-4935-a8d5-fc28b8f5ab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488548600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2488548600
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1164226903
Short name T353
Test name
Test status
Simulation time 2507685785 ps
CPU time 27.78 seconds
Started Jul 15 05:50:04 PM PDT 24
Finished Jul 15 05:50:33 PM PDT 24
Peak memory 213448 kb
Host smart-abde405c-5975-4392-a739-b6d4463ee867
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164226903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1164226903
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2779512335
Short name T344
Test name
Test status
Simulation time 175500780 ps
CPU time 4.31 seconds
Started Jul 15 05:49:09 PM PDT 24
Finished Jul 15 05:49:14 PM PDT 24
Peak memory 211292 kb
Host smart-a719d9af-fe38-499c-bfe2-fd3797b32dff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779512335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2779512335
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.75166794
Short name T199
Test name
Test status
Simulation time 11429465161 ps
CPU time 124.18 seconds
Started Jul 15 05:49:13 PM PDT 24
Finished Jul 15 05:51:18 PM PDT 24
Peak memory 236772 kb
Host smart-79cac034-96ed-45a8-a193-5f980a5b8105
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75166794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_cor
rupt_sig_fatal_chk.75166794
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1641865054
Short name T296
Test name
Test status
Simulation time 3073598505 ps
CPU time 27.52 seconds
Started Jul 15 05:49:11 PM PDT 24
Finished Jul 15 05:49:40 PM PDT 24
Peak memory 211956 kb
Host smart-32ad6204-4da6-4818-bec4-1fe26a1ec44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641865054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1641865054
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2785540383
Short name T298
Test name
Test status
Simulation time 707865975 ps
CPU time 7.55 seconds
Started Jul 15 05:49:14 PM PDT 24
Finished Jul 15 05:49:22 PM PDT 24
Peak memory 211408 kb
Host smart-5bbe26d8-df25-4b39-bf77-037ee4b5c390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785540383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2785540383
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.819288870
Short name T23
Test name
Test status
Simulation time 1214917425 ps
CPU time 105.46 seconds
Started Jul 15 05:49:14 PM PDT 24
Finished Jul 15 05:51:00 PM PDT 24
Peak memory 236860 kb
Host smart-f38f650d-a88d-4d0c-876b-e8514b50ff28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819288870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.819288870
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4062260381
Short name T181
Test name
Test status
Simulation time 189930867 ps
CPU time 10.73 seconds
Started Jul 15 05:49:10 PM PDT 24
Finished Jul 15 05:49:21 PM PDT 24
Peak memory 213384 kb
Host smart-7724b1dc-e5fc-43d3-9627-e209f38e1f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062260381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4062260381
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3152328585
Short name T319
Test name
Test status
Simulation time 6858510669 ps
CPU time 61.21 seconds
Started Jul 15 05:49:12 PM PDT 24
Finished Jul 15 05:50:14 PM PDT 24
Peak memory 216928 kb
Host smart-6840d0b1-0369-408e-8600-73d7665d048f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152328585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3152328585
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.889198387
Short name T12
Test name
Test status
Simulation time 166078442857 ps
CPU time 3163.17 seconds
Started Jul 15 05:49:13 PM PDT 24
Finished Jul 15 06:41:58 PM PDT 24
Peak memory 244048 kb
Host smart-5e0e2bb4-525a-439e-a854-90503b4ec028
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889198387 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.889198387
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1425904780
Short name T135
Test name
Test status
Simulation time 3084201429 ps
CPU time 8.92 seconds
Started Jul 15 05:50:12 PM PDT 24
Finished Jul 15 05:50:23 PM PDT 24
Peak memory 211364 kb
Host smart-ebf0df15-c8c3-41b0-8dfe-274f72dc6bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425904780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1425904780
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.105611061
Short name T219
Test name
Test status
Simulation time 8785071253 ps
CPU time 157.26 seconds
Started Jul 15 05:50:10 PM PDT 24
Finished Jul 15 05:52:48 PM PDT 24
Peak memory 236744 kb
Host smart-b3081eb2-e82f-4797-8512-9621c6911585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105611061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.105611061
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2744398034
Short name T282
Test name
Test status
Simulation time 2820266440 ps
CPU time 25.25 seconds
Started Jul 15 05:50:14 PM PDT 24
Finished Jul 15 05:50:40 PM PDT 24
Peak memory 212084 kb
Host smart-a2aff497-6266-40fe-8ff6-216f2fbb175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744398034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2744398034
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1260150578
Short name T143
Test name
Test status
Simulation time 8133987499 ps
CPU time 16.49 seconds
Started Jul 15 05:50:12 PM PDT 24
Finished Jul 15 05:50:30 PM PDT 24
Peak memory 211396 kb
Host smart-8838a29f-e6de-4a90-8cb4-2f8ccecfcf1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260150578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1260150578
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1912719006
Short name T223
Test name
Test status
Simulation time 12891247637 ps
CPU time 32.46 seconds
Started Jul 15 05:50:14 PM PDT 24
Finished Jul 15 05:50:48 PM PDT 24
Peak memory 213500 kb
Host smart-058578f5-52e0-4748-b533-d92bd1399d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912719006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1912719006
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2219804178
Short name T234
Test name
Test status
Simulation time 2245369359 ps
CPU time 24.22 seconds
Started Jul 15 05:50:11 PM PDT 24
Finished Jul 15 05:50:36 PM PDT 24
Peak memory 213752 kb
Host smart-e91ddeb2-da20-4ebe-9959-9e65589a4deb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219804178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2219804178
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3973726317
Short name T193
Test name
Test status
Simulation time 334173707 ps
CPU time 4.3 seconds
Started Jul 15 05:50:12 PM PDT 24
Finished Jul 15 05:50:18 PM PDT 24
Peak memory 211320 kb
Host smart-a88cf95b-9776-4309-b2a2-f4c4359cdc12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973726317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3973726317
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3147270879
Short name T122
Test name
Test status
Simulation time 62870547665 ps
CPU time 160.88 seconds
Started Jul 15 05:50:13 PM PDT 24
Finished Jul 15 05:52:55 PM PDT 24
Peak memory 232848 kb
Host smart-1671bbda-f8e7-4efc-bce0-4dc76525aed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147270879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3147270879
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.125775162
Short name T301
Test name
Test status
Simulation time 8227970322 ps
CPU time 22.03 seconds
Started Jul 15 05:50:16 PM PDT 24
Finished Jul 15 05:50:39 PM PDT 24
Peak memory 212952 kb
Host smart-683a7dc8-b999-4ea6-a64d-cf17e0be9672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125775162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.125775162
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.763316701
Short name T330
Test name
Test status
Simulation time 928685843 ps
CPU time 8.34 seconds
Started Jul 15 05:50:13 PM PDT 24
Finished Jul 15 05:50:23 PM PDT 24
Peak memory 211376 kb
Host smart-c75687da-403e-4590-a092-c6cc8d7e3aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=763316701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.763316701
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3903359128
Short name T178
Test name
Test status
Simulation time 1094627471 ps
CPU time 12.39 seconds
Started Jul 15 05:50:10 PM PDT 24
Finished Jul 15 05:50:24 PM PDT 24
Peak memory 212816 kb
Host smart-706000e8-d6fc-44cf-99c8-71c967d7f5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903359128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3903359128
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.786681126
Short name T349
Test name
Test status
Simulation time 9918972766 ps
CPU time 27.22 seconds
Started Jul 15 05:50:13 PM PDT 24
Finished Jul 15 05:50:42 PM PDT 24
Peak memory 214576 kb
Host smart-12a50e11-940f-4e05-8555-2c2a3755cd71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786681126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.786681126
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.426136583
Short name T46
Test name
Test status
Simulation time 89511868048 ps
CPU time 915.67 seconds
Started Jul 15 05:50:11 PM PDT 24
Finished Jul 15 06:05:28 PM PDT 24
Peak memory 235856 kb
Host smart-1b768c58-e271-4168-8439-c6cf5b09c1aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426136583 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.426136583
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2813883739
Short name T335
Test name
Test status
Simulation time 1836441612 ps
CPU time 15.34 seconds
Started Jul 15 05:50:12 PM PDT 24
Finished Jul 15 05:50:29 PM PDT 24
Peak memory 211340 kb
Host smart-9675b5ae-0353-4e3e-940a-c0e1eb0b93e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813883739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2813883739
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1479119916
Short name T191
Test name
Test status
Simulation time 206892261010 ps
CPU time 247.52 seconds
Started Jul 15 05:50:14 PM PDT 24
Finished Jul 15 05:54:23 PM PDT 24
Peak memory 236944 kb
Host smart-03ac9ba5-a176-480d-8266-ae7197fa69fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479119916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1479119916
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3025889845
Short name T21
Test name
Test status
Simulation time 1143993485 ps
CPU time 13.33 seconds
Started Jul 15 05:50:18 PM PDT 24
Finished Jul 15 05:50:32 PM PDT 24
Peak memory 211904 kb
Host smart-f1ec06f3-2721-4bca-965c-74f172a363af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025889845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3025889845
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1918236497
Short name T211
Test name
Test status
Simulation time 1064857973 ps
CPU time 7.11 seconds
Started Jul 15 05:50:14 PM PDT 24
Finished Jul 15 05:50:23 PM PDT 24
Peak memory 211292 kb
Host smart-e174927e-705e-4c96-992f-71bad376f4a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918236497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1918236497
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3633262813
Short name T314
Test name
Test status
Simulation time 1211307385 ps
CPU time 17.17 seconds
Started Jul 15 05:50:11 PM PDT 24
Finished Jul 15 05:50:30 PM PDT 24
Peak memory 213424 kb
Host smart-6bcf120e-b69d-448a-944c-670b805e0598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633262813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3633262813
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2129859123
Short name T338
Test name
Test status
Simulation time 6683200655 ps
CPU time 60.78 seconds
Started Jul 15 05:50:14 PM PDT 24
Finished Jul 15 05:51:16 PM PDT 24
Peak memory 216948 kb
Host smart-b02979fc-5ca7-4f48-b026-62bed0b7802f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129859123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2129859123
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.831738517
Short name T42
Test name
Test status
Simulation time 22253267950 ps
CPU time 3017.99 seconds
Started Jul 15 05:50:14 PM PDT 24
Finished Jul 15 06:40:34 PM PDT 24
Peak memory 227596 kb
Host smart-74ce52c4-daff-4578-9080-0024c214d949
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831738517 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.831738517
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1023161433
Short name T309
Test name
Test status
Simulation time 2239405952 ps
CPU time 7.28 seconds
Started Jul 15 05:50:14 PM PDT 24
Finished Jul 15 05:50:23 PM PDT 24
Peak memory 211432 kb
Host smart-4d30b1cf-88d1-494f-85f9-981a26b7fda5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023161433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1023161433
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1098303352
Short name T308
Test name
Test status
Simulation time 7874292730 ps
CPU time 150.66 seconds
Started Jul 15 05:50:09 PM PDT 24
Finished Jul 15 05:52:40 PM PDT 24
Peak memory 236836 kb
Host smart-ed144b57-7a8d-49b1-be50-d0c558a14ac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098303352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1098303352
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3018970730
Short name T239
Test name
Test status
Simulation time 695007336 ps
CPU time 9.43 seconds
Started Jul 15 05:50:13 PM PDT 24
Finished Jul 15 05:50:24 PM PDT 24
Peak memory 212472 kb
Host smart-47b0c9aa-e368-49ed-a743-88cf8708a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018970730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3018970730
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1724688934
Short name T59
Test name
Test status
Simulation time 731023055 ps
CPU time 9.73 seconds
Started Jul 15 05:50:12 PM PDT 24
Finished Jul 15 05:50:23 PM PDT 24
Peak memory 211360 kb
Host smart-ca2789a1-d50c-42c5-811e-8262d1bf618d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724688934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1724688934
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2971436031
Short name T323
Test name
Test status
Simulation time 3495678812 ps
CPU time 29.52 seconds
Started Jul 15 05:50:14 PM PDT 24
Finished Jul 15 05:50:45 PM PDT 24
Peak memory 213508 kb
Host smart-a4654c7b-0cc4-4ef0-ad65-cb605eb3f030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971436031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2971436031
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2436599653
Short name T124
Test name
Test status
Simulation time 9429523902 ps
CPU time 25.37 seconds
Started Jul 15 05:50:14 PM PDT 24
Finished Jul 15 05:50:41 PM PDT 24
Peak memory 214172 kb
Host smart-aa751b18-c7d6-4fb3-9067-05dbd8b569d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436599653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2436599653
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1701451608
Short name T47
Test name
Test status
Simulation time 64550028749 ps
CPU time 6547.66 seconds
Started Jul 15 05:50:10 PM PDT 24
Finished Jul 15 07:39:20 PM PDT 24
Peak memory 243900 kb
Host smart-1b21f1b0-8a92-4bc6-8a8c-e727ab8913bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701451608 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1701451608
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1630484740
Short name T304
Test name
Test status
Simulation time 579078133 ps
CPU time 6.35 seconds
Started Jul 15 05:50:12 PM PDT 24
Finished Jul 15 05:50:20 PM PDT 24
Peak memory 211328 kb
Host smart-7e76919d-78c1-401e-86c6-847f546b9e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630484740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1630484740
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2015933303
Short name T310
Test name
Test status
Simulation time 33476436045 ps
CPU time 324.99 seconds
Started Jul 15 05:50:15 PM PDT 24
Finished Jul 15 05:55:41 PM PDT 24
Peak memory 235796 kb
Host smart-ee365f39-5e43-4d45-8529-94bea5aaac7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015933303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2015933303
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.300621420
Short name T332
Test name
Test status
Simulation time 7863752233 ps
CPU time 22.33 seconds
Started Jul 15 05:50:18 PM PDT 24
Finished Jul 15 05:50:41 PM PDT 24
Peak memory 211440 kb
Host smart-b24ec08e-4755-458c-9da4-d60277148770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300621420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.300621420
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.234362705
Short name T26
Test name
Test status
Simulation time 15618549891 ps
CPU time 10.9 seconds
Started Jul 15 05:50:10 PM PDT 24
Finished Jul 15 05:50:21 PM PDT 24
Peak memory 211444 kb
Host smart-554c0d28-4316-4147-8707-239b2389ab91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234362705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.234362705
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3878069628
Short name T339
Test name
Test status
Simulation time 960312878 ps
CPU time 15.66 seconds
Started Jul 15 05:50:11 PM PDT 24
Finished Jul 15 05:50:28 PM PDT 24
Peak memory 212020 kb
Host smart-881ab1b4-7e46-4382-92ad-f1250b144b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878069628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3878069628
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.870700172
Short name T13
Test name
Test status
Simulation time 1413024644 ps
CPU time 25.81 seconds
Started Jul 15 05:50:11 PM PDT 24
Finished Jul 15 05:50:39 PM PDT 24
Peak memory 215324 kb
Host smart-e8070ad2-bce5-46d3-831a-1af303cdb99f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870700172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.870700172
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4046544340
Short name T303
Test name
Test status
Simulation time 53827104919 ps
CPU time 2229.72 seconds
Started Jul 15 05:50:18 PM PDT 24
Finished Jul 15 06:27:29 PM PDT 24
Peak memory 240700 kb
Host smart-5c3d5178-5c0f-41bd-8a57-db712e47ae23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046544340 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.4046544340
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3412677168
Short name T54
Test name
Test status
Simulation time 361233841 ps
CPU time 4.15 seconds
Started Jul 15 05:50:21 PM PDT 24
Finished Jul 15 05:50:27 PM PDT 24
Peak memory 211340 kb
Host smart-f1796930-f235-4e38-8ce2-f0b52780df2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412677168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3412677168
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3179518792
Short name T312
Test name
Test status
Simulation time 192906413177 ps
CPU time 277.13 seconds
Started Jul 15 05:50:12 PM PDT 24
Finished Jul 15 05:54:50 PM PDT 24
Peak memory 225168 kb
Host smart-45d7f90d-1402-4a76-bde5-8683b9241a58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179518792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3179518792
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2809689721
Short name T331
Test name
Test status
Simulation time 4143489883 ps
CPU time 32.44 seconds
Started Jul 15 05:50:12 PM PDT 24
Finished Jul 15 05:50:46 PM PDT 24
Peak memory 212040 kb
Host smart-2eb28d37-1817-4949-8955-d13eadf76f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809689721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2809689721
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.100252380
Short name T136
Test name
Test status
Simulation time 712704862 ps
CPU time 9.68 seconds
Started Jul 15 05:50:11 PM PDT 24
Finished Jul 15 05:50:22 PM PDT 24
Peak memory 211368 kb
Host smart-2b7cbe10-9033-4906-94bb-662258a7ce5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100252380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.100252380
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.862779345
Short name T267
Test name
Test status
Simulation time 188666658 ps
CPU time 10.28 seconds
Started Jul 15 05:50:13 PM PDT 24
Finished Jul 15 05:50:25 PM PDT 24
Peak memory 213352 kb
Host smart-7ed9aa5a-88db-492f-adc3-ef7f2a6557e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862779345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.862779345
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1689806678
Short name T215
Test name
Test status
Simulation time 378217382 ps
CPU time 21.74 seconds
Started Jul 15 05:50:09 PM PDT 24
Finished Jul 15 05:50:32 PM PDT 24
Peak memory 214576 kb
Host smart-ac40a41d-67cf-4170-803b-7465e551f1ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689806678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1689806678
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1725603686
Short name T114
Test name
Test status
Simulation time 30117280440 ps
CPU time 1199.86 seconds
Started Jul 15 05:50:14 PM PDT 24
Finished Jul 15 06:10:15 PM PDT 24
Peak memory 235764 kb
Host smart-723acc48-df51-45df-acbf-f0751519d3d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725603686 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1725603686
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2417734784
Short name T209
Test name
Test status
Simulation time 5020966382 ps
CPU time 12.17 seconds
Started Jul 15 05:50:25 PM PDT 24
Finished Jul 15 05:50:37 PM PDT 24
Peak memory 211372 kb
Host smart-166973d2-ba9b-4aa4-8069-14abe21cd849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417734784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2417734784
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3612963865
Short name T35
Test name
Test status
Simulation time 204938638807 ps
CPU time 428.37 seconds
Started Jul 15 05:50:24 PM PDT 24
Finished Jul 15 05:57:33 PM PDT 24
Peak memory 237196 kb
Host smart-1a0c6fbe-78f2-4f89-aaf9-78113814413b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612963865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3612963865
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.995267148
Short name T133
Test name
Test status
Simulation time 2653291520 ps
CPU time 25.42 seconds
Started Jul 15 05:50:22 PM PDT 24
Finished Jul 15 05:50:48 PM PDT 24
Peak memory 211856 kb
Host smart-6e7ebb00-96b8-4415-8750-e8450f4e4782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995267148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.995267148
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4287038874
Short name T159
Test name
Test status
Simulation time 2053545725 ps
CPU time 17.26 seconds
Started Jul 15 05:50:21 PM PDT 24
Finished Jul 15 05:50:40 PM PDT 24
Peak memory 211360 kb
Host smart-7d7b69f5-1de4-4d56-9d35-565439eeabd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287038874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4287038874
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.4116548893
Short name T295
Test name
Test status
Simulation time 4096421787 ps
CPU time 32.75 seconds
Started Jul 15 05:50:20 PM PDT 24
Finished Jul 15 05:50:54 PM PDT 24
Peak memory 213360 kb
Host smart-389a22c4-2e2f-432e-83ba-dae124201b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116548893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.4116548893
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1373515747
Short name T233
Test name
Test status
Simulation time 967988120 ps
CPU time 16.22 seconds
Started Jul 15 05:50:20 PM PDT 24
Finished Jul 15 05:50:37 PM PDT 24
Peak memory 215340 kb
Host smart-3fb5806c-429f-477c-8653-9eeb59fa7267
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373515747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1373515747
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2354507085
Short name T141
Test name
Test status
Simulation time 4600795158 ps
CPU time 11.37 seconds
Started Jul 15 05:50:22 PM PDT 24
Finished Jul 15 05:50:35 PM PDT 24
Peak memory 211228 kb
Host smart-3c5502ac-d762-4690-9187-55ece138d295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354507085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2354507085
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3638509041
Short name T315
Test name
Test status
Simulation time 43015831637 ps
CPU time 414.53 seconds
Started Jul 15 05:50:20 PM PDT 24
Finished Jul 15 05:57:15 PM PDT 24
Peak memory 234924 kb
Host smart-33cd7b9c-500f-46eb-93db-d2298914d1cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638509041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3638509041
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4023952335
Short name T40
Test name
Test status
Simulation time 4476182345 ps
CPU time 30.01 seconds
Started Jul 15 05:50:23 PM PDT 24
Finished Jul 15 05:50:54 PM PDT 24
Peak memory 212100 kb
Host smart-359d1f81-01fb-4b24-98ab-7d31562ed438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023952335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4023952335
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4048551553
Short name T229
Test name
Test status
Simulation time 99483241 ps
CPU time 5.6 seconds
Started Jul 15 05:50:23 PM PDT 24
Finished Jul 15 05:50:30 PM PDT 24
Peak memory 211380 kb
Host smart-4df7075d-c2fc-4763-95e7-b4c4f5e5ae7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048551553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4048551553
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1456633731
Short name T214
Test name
Test status
Simulation time 1081894186 ps
CPU time 16.09 seconds
Started Jul 15 05:50:21 PM PDT 24
Finished Jul 15 05:50:39 PM PDT 24
Peak memory 213592 kb
Host smart-dbc9edda-314f-47d6-9246-ced2b38f2409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456633731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1456633731
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1479399433
Short name T333
Test name
Test status
Simulation time 8659602397 ps
CPU time 34.91 seconds
Started Jul 15 05:50:19 PM PDT 24
Finished Jul 15 05:50:55 PM PDT 24
Peak memory 215144 kb
Host smart-126be20c-0b0c-499f-9ceb-b4768acfa4e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479399433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1479399433
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3285652810
Short name T280
Test name
Test status
Simulation time 330601759 ps
CPU time 6.65 seconds
Started Jul 15 05:50:22 PM PDT 24
Finished Jul 15 05:50:30 PM PDT 24
Peak memory 211324 kb
Host smart-cf39c669-3c09-4d40-8a3a-3377f82172e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285652810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3285652810
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1694816995
Short name T325
Test name
Test status
Simulation time 43449419136 ps
CPU time 438.46 seconds
Started Jul 15 05:50:20 PM PDT 24
Finished Jul 15 05:57:40 PM PDT 24
Peak memory 233724 kb
Host smart-8678bf15-abca-434a-897c-1d021e024cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694816995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1694816995
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1690644129
Short name T126
Test name
Test status
Simulation time 3191072126 ps
CPU time 27.73 seconds
Started Jul 15 05:50:18 PM PDT 24
Finished Jul 15 05:50:47 PM PDT 24
Peak memory 212384 kb
Host smart-ce7ebbd1-7b52-4e29-8e6e-9728d48afec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690644129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1690644129
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1032943871
Short name T221
Test name
Test status
Simulation time 1376385191 ps
CPU time 11.84 seconds
Started Jul 15 05:50:21 PM PDT 24
Finished Jul 15 05:50:34 PM PDT 24
Peak memory 211328 kb
Host smart-b11abc72-7976-4b89-8060-f7678b1d73d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032943871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1032943871
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1879763877
Short name T166
Test name
Test status
Simulation time 2571528488 ps
CPU time 25.23 seconds
Started Jul 15 05:50:20 PM PDT 24
Finished Jul 15 05:50:46 PM PDT 24
Peak memory 213632 kb
Host smart-8cd3a361-69df-48b1-987d-d8cf8d186b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879763877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1879763877
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.94426265
Short name T88
Test name
Test status
Simulation time 369242864 ps
CPU time 14.46 seconds
Started Jul 15 05:50:21 PM PDT 24
Finished Jul 15 05:50:36 PM PDT 24
Peak memory 214236 kb
Host smart-2573e5e0-f60e-4417-9466-0c942d3140f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94426265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 38.rom_ctrl_stress_all.94426265
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3790180518
Short name T10
Test name
Test status
Simulation time 5165191718 ps
CPU time 8.95 seconds
Started Jul 15 05:50:20 PM PDT 24
Finished Jul 15 05:50:30 PM PDT 24
Peak memory 211384 kb
Host smart-c2431cd3-ec15-48d9-a51b-0b4c8196ff5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790180518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3790180518
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3283216466
Short name T118
Test name
Test status
Simulation time 63221028573 ps
CPU time 357.73 seconds
Started Jul 15 05:50:23 PM PDT 24
Finished Jul 15 05:56:22 PM PDT 24
Peak memory 234020 kb
Host smart-f36bd6b8-14a6-45c7-8a29-bb91a743d6a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283216466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3283216466
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1943546572
Short name T134
Test name
Test status
Simulation time 264240291 ps
CPU time 7.14 seconds
Started Jul 15 05:50:20 PM PDT 24
Finished Jul 15 05:50:28 PM PDT 24
Peak memory 211324 kb
Host smart-97d9f355-d53e-4020-8b49-121410f63eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943546572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1943546572
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1922998335
Short name T140
Test name
Test status
Simulation time 7408705373 ps
CPU time 29.84 seconds
Started Jul 15 05:50:20 PM PDT 24
Finished Jul 15 05:50:51 PM PDT 24
Peak memory 214196 kb
Host smart-06065305-cafe-458b-a745-b6691c3240db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922998335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1922998335
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1181910486
Short name T241
Test name
Test status
Simulation time 4135918120 ps
CPU time 31.57 seconds
Started Jul 15 05:50:19 PM PDT 24
Finished Jul 15 05:50:51 PM PDT 24
Peak memory 214616 kb
Host smart-a6a727fb-5900-4547-a82a-6ea246a7f18e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181910486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1181910486
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1453252586
Short name T179
Test name
Test status
Simulation time 1318273529 ps
CPU time 12.56 seconds
Started Jul 15 05:49:24 PM PDT 24
Finished Jul 15 05:49:37 PM PDT 24
Peak memory 211340 kb
Host smart-bd884da8-cf64-48ba-8b21-cd97669e3365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453252586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1453252586
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.455638992
Short name T200
Test name
Test status
Simulation time 70360018812 ps
CPU time 162.98 seconds
Started Jul 15 05:49:19 PM PDT 24
Finished Jul 15 05:52:03 PM PDT 24
Peak memory 212652 kb
Host smart-fe45cca3-30fd-435f-b8ad-2c893ecaa320
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455638992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.455638992
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.133421037
Short name T360
Test name
Test status
Simulation time 640680522 ps
CPU time 9.39 seconds
Started Jul 15 05:49:18 PM PDT 24
Finished Jul 15 05:49:28 PM PDT 24
Peak memory 212028 kb
Host smart-caf5d809-7116-40db-bffc-cd847e7ded07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133421037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.133421037
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.279622345
Short name T268
Test name
Test status
Simulation time 4568209313 ps
CPU time 12.25 seconds
Started Jul 15 05:49:16 PM PDT 24
Finished Jul 15 05:49:30 PM PDT 24
Peak memory 211424 kb
Host smart-b466df05-8b0c-40ad-b448-1e0c625d7207
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279622345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.279622345
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4264335251
Short name T15
Test name
Test status
Simulation time 1470566060 ps
CPU time 105.84 seconds
Started Jul 15 05:49:18 PM PDT 24
Finished Jul 15 05:51:05 PM PDT 24
Peak memory 236168 kb
Host smart-d8562b6f-443e-4576-a291-e3d9116c7ca9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264335251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4264335251
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3091490470
Short name T246
Test name
Test status
Simulation time 3072176103 ps
CPU time 27.81 seconds
Started Jul 15 05:49:17 PM PDT 24
Finished Jul 15 05:49:45 PM PDT 24
Peak memory 212892 kb
Host smart-b4d1fe81-2077-48b0-b77b-089ab6e09fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091490470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3091490470
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3927038365
Short name T260
Test name
Test status
Simulation time 29718120620 ps
CPU time 56.31 seconds
Started Jul 15 05:49:17 PM PDT 24
Finished Jul 15 05:50:14 PM PDT 24
Peak memory 217292 kb
Host smart-07d3da3f-d7a1-4e2b-8192-ad1aaf68869a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927038365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3927038365
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1024122241
Short name T137
Test name
Test status
Simulation time 87395807 ps
CPU time 4.27 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:37 PM PDT 24
Peak memory 211312 kb
Host smart-2bc971bf-e1f7-41b2-be95-b50bde4d652b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024122241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1024122241
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3443277515
Short name T257
Test name
Test status
Simulation time 17017821961 ps
CPU time 176.59 seconds
Started Jul 15 05:50:21 PM PDT 24
Finished Jul 15 05:53:19 PM PDT 24
Peak memory 212668 kb
Host smart-3330f3a3-bc78-4583-bdda-981d1f9270f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443277515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3443277515
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2555240044
Short name T132
Test name
Test status
Simulation time 13332591566 ps
CPU time 28.07 seconds
Started Jul 15 05:50:20 PM PDT 24
Finished Jul 15 05:50:49 PM PDT 24
Peak memory 212248 kb
Host smart-685f01bd-6dbe-4661-b995-4b717bbe8515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555240044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2555240044
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3237337797
Short name T87
Test name
Test status
Simulation time 5804999436 ps
CPU time 13.4 seconds
Started Jul 15 05:50:22 PM PDT 24
Finished Jul 15 05:50:36 PM PDT 24
Peak memory 211428 kb
Host smart-9c5a0805-70ea-42d5-a557-8522c4567b7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237337797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3237337797
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2977505297
Short name T60
Test name
Test status
Simulation time 2798015057 ps
CPU time 15.14 seconds
Started Jul 15 05:50:21 PM PDT 24
Finished Jul 15 05:50:38 PM PDT 24
Peak memory 213840 kb
Host smart-fd7587b1-911e-4523-b091-5e7e5f0f8e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977505297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2977505297
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3926068269
Short name T30
Test name
Test status
Simulation time 654441771 ps
CPU time 19.3 seconds
Started Jul 15 05:50:24 PM PDT 24
Finished Jul 15 05:50:44 PM PDT 24
Peak memory 215148 kb
Host smart-7b169f2e-58cd-4a42-844a-0f2f3b0f811f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926068269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3926068269
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.950022534
Short name T138
Test name
Test status
Simulation time 2386271385 ps
CPU time 16.6 seconds
Started Jul 15 05:50:33 PM PDT 24
Finished Jul 15 05:50:51 PM PDT 24
Peak memory 211328 kb
Host smart-65945f8b-965f-47cb-9068-f41b449b9ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950022534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.950022534
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1915167373
Short name T337
Test name
Test status
Simulation time 291934510652 ps
CPU time 244.71 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:54:38 PM PDT 24
Peak memory 228608 kb
Host smart-e3802ff3-91a6-436e-addb-69bfe2acf792
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915167373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1915167373
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3267910141
Short name T342
Test name
Test status
Simulation time 273826307 ps
CPU time 11.2 seconds
Started Jul 15 05:50:33 PM PDT 24
Finished Jul 15 05:50:45 PM PDT 24
Peak memory 211908 kb
Host smart-8fb18ec8-6115-4899-bfdd-57f582d6501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267910141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3267910141
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3419923158
Short name T329
Test name
Test status
Simulation time 1132057458 ps
CPU time 5.57 seconds
Started Jul 15 05:50:35 PM PDT 24
Finished Jul 15 05:50:40 PM PDT 24
Peak memory 211340 kb
Host smart-f18bfaa6-766d-4ac3-9ef1-505736c4a8e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419923158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3419923158
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.188162801
Short name T71
Test name
Test status
Simulation time 936633004 ps
CPU time 16.67 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:49 PM PDT 24
Peak memory 213656 kb
Host smart-4b725c37-4ca0-4f6a-b589-2b2ad07ccdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188162801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.188162801
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1358452732
Short name T213
Test name
Test status
Simulation time 3390106112 ps
CPU time 19.21 seconds
Started Jul 15 05:50:29 PM PDT 24
Finished Jul 15 05:50:49 PM PDT 24
Peak memory 211980 kb
Host smart-2315e83d-8529-4d33-a89e-a4d87aa5a405
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358452732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1358452732
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2318397166
Short name T151
Test name
Test status
Simulation time 5212437712 ps
CPU time 11.62 seconds
Started Jul 15 05:50:31 PM PDT 24
Finished Jul 15 05:50:43 PM PDT 24
Peak memory 211408 kb
Host smart-fdf7f769-1d67-4a47-8586-3e32fce7aa10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318397166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2318397166
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.29464807
Short name T9
Test name
Test status
Simulation time 1912269784 ps
CPU time 127.72 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:52:41 PM PDT 24
Peak memory 236720 kb
Host smart-ade1bb95-c58b-4ede-8266-0cf43e86aa4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29464807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_co
rrupt_sig_fatal_chk.29464807
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.562030815
Short name T20
Test name
Test status
Simulation time 3940796719 ps
CPU time 16.05 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:49 PM PDT 24
Peak memory 212620 kb
Host smart-8e7af4b4-b91d-4456-8085-c4b0d23488ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562030815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.562030815
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4098269383
Short name T359
Test name
Test status
Simulation time 397032697 ps
CPU time 7.87 seconds
Started Jul 15 05:50:34 PM PDT 24
Finished Jul 15 05:50:42 PM PDT 24
Peak memory 211340 kb
Host smart-01d3fa4f-1cf3-471d-b19a-dde0f86b84be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098269383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4098269383
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2720622582
Short name T278
Test name
Test status
Simulation time 7717341229 ps
CPU time 34.35 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:51:08 PM PDT 24
Peak memory 213328 kb
Host smart-0f7bad28-2b3f-430c-ad65-6cbb49a0af43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720622582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2720622582
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1548594883
Short name T292
Test name
Test status
Simulation time 28542763713 ps
CPU time 14.11 seconds
Started Jul 15 05:50:31 PM PDT 24
Finished Jul 15 05:50:46 PM PDT 24
Peak memory 211384 kb
Host smart-aef199dc-1f9d-4ef6-b46b-cb44c48d5866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548594883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1548594883
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1911358479
Short name T317
Test name
Test status
Simulation time 8523521821 ps
CPU time 106.25 seconds
Started Jul 15 05:50:30 PM PDT 24
Finished Jul 15 05:52:17 PM PDT 24
Peak memory 237864 kb
Host smart-d8c26ddb-32d2-4eeb-9773-5fcc5be428aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911358479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1911358479
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3188121234
Short name T276
Test name
Test status
Simulation time 2104615137 ps
CPU time 22.43 seconds
Started Jul 15 05:50:37 PM PDT 24
Finished Jul 15 05:51:00 PM PDT 24
Peak memory 211812 kb
Host smart-b8376d80-6e1f-469d-b331-201632db4876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188121234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3188121234
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1949057806
Short name T116
Test name
Test status
Simulation time 2365819456 ps
CPU time 14.42 seconds
Started Jul 15 05:50:37 PM PDT 24
Finished Jul 15 05:50:52 PM PDT 24
Peak memory 212072 kb
Host smart-1ecaa2f8-39a1-41c1-ad23-d84377c8ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949057806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1949057806
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3575299490
Short name T249
Test name
Test status
Simulation time 1618538399 ps
CPU time 23.97 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:57 PM PDT 24
Peak memory 216596 kb
Host smart-2d6ebf0e-6ac2-4f51-a8d4-4a5b18051b3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575299490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3575299490
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.817832993
Short name T262
Test name
Test status
Simulation time 15679253524 ps
CPU time 15.71 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:49 PM PDT 24
Peak memory 211384 kb
Host smart-b13182f0-b766-493d-a652-efc66721a36a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817832993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.817832993
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.776870185
Short name T167
Test name
Test status
Simulation time 1635297205 ps
CPU time 90.96 seconds
Started Jul 15 05:50:30 PM PDT 24
Finished Jul 15 05:52:02 PM PDT 24
Peak memory 224536 kb
Host smart-236e32a6-fcb2-4243-9238-baa432213135
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776870185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.776870185
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2697190551
Short name T245
Test name
Test status
Simulation time 1887606638 ps
CPU time 20.39 seconds
Started Jul 15 05:50:37 PM PDT 24
Finished Jul 15 05:50:58 PM PDT 24
Peak memory 211816 kb
Host smart-e8056984-a317-4fbc-8dbb-738c87ab8012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697190551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2697190551
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3473962874
Short name T358
Test name
Test status
Simulation time 4715145834 ps
CPU time 12.88 seconds
Started Jul 15 05:50:30 PM PDT 24
Finished Jul 15 05:50:43 PM PDT 24
Peak memory 211364 kb
Host smart-3f171cb7-ef66-457e-ae46-09f750d0f81c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3473962874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3473962874
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4219266763
Short name T8
Test name
Test status
Simulation time 13850614423 ps
CPU time 35.78 seconds
Started Jul 15 05:50:31 PM PDT 24
Finished Jul 15 05:51:08 PM PDT 24
Peak memory 213300 kb
Host smart-9155e7e0-f2f4-44cb-a26b-75e3db623da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219266763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4219266763
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.438031461
Short name T139
Test name
Test status
Simulation time 2821213629 ps
CPU time 14.59 seconds
Started Jul 15 05:50:34 PM PDT 24
Finished Jul 15 05:50:49 PM PDT 24
Peak memory 212132 kb
Host smart-493c5896-ed15-449c-b95a-9049af1a786a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438031461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.438031461
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.888324073
Short name T291
Test name
Test status
Simulation time 58983468354 ps
CPU time 2177.1 seconds
Started Jul 15 05:50:35 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 236028 kb
Host smart-1fe23fc2-df49-44e5-9a9a-6faf0ea2fc3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888324073 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.888324073
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.187340249
Short name T300
Test name
Test status
Simulation time 333899679 ps
CPU time 4.32 seconds
Started Jul 15 05:50:40 PM PDT 24
Finished Jul 15 05:50:45 PM PDT 24
Peak memory 211456 kb
Host smart-ed1ce5c8-a80b-4916-a7a9-04fb08440bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187340249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.187340249
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.268691034
Short name T2
Test name
Test status
Simulation time 13146765965 ps
CPU time 161.01 seconds
Started Jul 15 05:50:40 PM PDT 24
Finished Jul 15 05:53:22 PM PDT 24
Peak memory 240592 kb
Host smart-091ad8d0-c430-4658-806c-f30efd7c3a76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268691034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.268691034
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1576190353
Short name T188
Test name
Test status
Simulation time 3664555892 ps
CPU time 20.34 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:54 PM PDT 24
Peak memory 212020 kb
Host smart-ddcae3dd-1aa5-4874-a0f9-8e5d867b256b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576190353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1576190353
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1851116135
Short name T324
Test name
Test status
Simulation time 6317536541 ps
CPU time 14.66 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:48 PM PDT 24
Peak memory 211392 kb
Host smart-c81a8a6a-f26a-48df-ab14-93ea22326342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851116135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1851116135
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1348025760
Short name T286
Test name
Test status
Simulation time 1999392675 ps
CPU time 11.8 seconds
Started Jul 15 05:50:30 PM PDT 24
Finished Jul 15 05:50:43 PM PDT 24
Peak memory 212272 kb
Host smart-9873c908-3908-4a28-9f11-473ebd82d872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348025760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1348025760
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.331906838
Short name T272
Test name
Test status
Simulation time 9551342628 ps
CPU time 32.08 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:51:05 PM PDT 24
Peak memory 216296 kb
Host smart-420fd019-d07b-4a03-82f8-667f9b1b752c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331906838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.331906838
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.798003206
Short name T44
Test name
Test status
Simulation time 47359829094 ps
CPU time 1711.73 seconds
Started Jul 15 05:50:31 PM PDT 24
Finished Jul 15 06:19:04 PM PDT 24
Peak memory 235848 kb
Host smart-6d803d0c-fc26-49b3-93c2-e5294a74e797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798003206 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.798003206
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3346690617
Short name T165
Test name
Test status
Simulation time 1242223608 ps
CPU time 11.62 seconds
Started Jul 15 05:50:31 PM PDT 24
Finished Jul 15 05:50:43 PM PDT 24
Peak memory 211292 kb
Host smart-e86b1640-e0b6-414f-8133-5026e8238420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346690617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3346690617
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3243326197
Short name T36
Test name
Test status
Simulation time 17623188441 ps
CPU time 178.35 seconds
Started Jul 15 05:50:36 PM PDT 24
Finished Jul 15 05:53:36 PM PDT 24
Peak memory 237836 kb
Host smart-839f573c-7d12-4a25-a36e-d295001b5c27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243326197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3243326197
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4144625963
Short name T322
Test name
Test status
Simulation time 24662727876 ps
CPU time 18.82 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:52 PM PDT 24
Peak memory 212196 kb
Host smart-80fa1f23-4e43-4762-bb2e-50bd2ed694be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144625963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4144625963
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2217862369
Short name T185
Test name
Test status
Simulation time 6877220650 ps
CPU time 15.77 seconds
Started Jul 15 05:50:30 PM PDT 24
Finished Jul 15 05:50:46 PM PDT 24
Peak memory 211428 kb
Host smart-13505401-8206-441b-8c07-7468a787d83a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217862369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2217862369
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1312328822
Short name T270
Test name
Test status
Simulation time 4370024872 ps
CPU time 22.93 seconds
Started Jul 15 05:50:30 PM PDT 24
Finished Jul 15 05:50:53 PM PDT 24
Peak memory 213264 kb
Host smart-bf466767-23ca-4d5a-bed2-c51fa40fc680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312328822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1312328822
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2775617202
Short name T176
Test name
Test status
Simulation time 490625617 ps
CPU time 26.85 seconds
Started Jul 15 05:50:33 PM PDT 24
Finished Jul 15 05:51:01 PM PDT 24
Peak memory 216192 kb
Host smart-c1ff006e-ec07-4e8d-aa3a-e378cb0e64ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775617202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2775617202
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1183150660
Short name T217
Test name
Test status
Simulation time 4195702230 ps
CPU time 16.72 seconds
Started Jul 15 05:50:41 PM PDT 24
Finished Jul 15 05:50:59 PM PDT 24
Peak memory 211408 kb
Host smart-eafe049a-1e87-47c4-8fd3-4fe09918131d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183150660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1183150660
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2577477055
Short name T32
Test name
Test status
Simulation time 1972255198 ps
CPU time 102.99 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:52:16 PM PDT 24
Peak memory 237804 kb
Host smart-c5b70029-8576-4d5c-8536-b5e57ba92095
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577477055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2577477055
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.872600212
Short name T39
Test name
Test status
Simulation time 218283951 ps
CPU time 9.55 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:42 PM PDT 24
Peak memory 211964 kb
Host smart-ae9fc04a-8858-4d6b-b939-01791910ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872600212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.872600212
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1769049362
Short name T101
Test name
Test status
Simulation time 812893396 ps
CPU time 10.32 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:44 PM PDT 24
Peak memory 211360 kb
Host smart-0b7bcfd4-7d46-4c1a-a94a-ff90f873509f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769049362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1769049362
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3646001687
Short name T259
Test name
Test status
Simulation time 9238301469 ps
CPU time 16.57 seconds
Started Jul 15 05:50:32 PM PDT 24
Finished Jul 15 05:50:50 PM PDT 24
Peak memory 214028 kb
Host smart-71c54d5e-3c5b-4d2e-b09d-a1733c51d024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646001687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3646001687
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.802345519
Short name T89
Test name
Test status
Simulation time 8240786963 ps
CPU time 18.52 seconds
Started Jul 15 05:50:33 PM PDT 24
Finished Jul 15 05:50:52 PM PDT 24
Peak memory 211584 kb
Host smart-18fd7a1e-33b8-4626-9c46-544304c3d779
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802345519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.802345519
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1582283649
Short name T164
Test name
Test status
Simulation time 208771457 ps
CPU time 5.79 seconds
Started Jul 15 05:50:40 PM PDT 24
Finished Jul 15 05:50:46 PM PDT 24
Peak memory 211288 kb
Host smart-3abb0e85-2fd4-4b5a-90ee-f29f10ecbaa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582283649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1582283649
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2918604619
Short name T228
Test name
Test status
Simulation time 1484950952 ps
CPU time 77.22 seconds
Started Jul 15 05:50:40 PM PDT 24
Finished Jul 15 05:51:57 PM PDT 24
Peak memory 227164 kb
Host smart-00134db0-5ab0-430c-bd3c-fa11a32096b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918604619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2918604619
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.942234659
Short name T41
Test name
Test status
Simulation time 179404510 ps
CPU time 9.5 seconds
Started Jul 15 05:50:42 PM PDT 24
Finished Jul 15 05:50:52 PM PDT 24
Peak memory 211840 kb
Host smart-cd202bb1-8fd8-4e28-b9e7-cca04a96efde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942234659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.942234659
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.365624274
Short name T129
Test name
Test status
Simulation time 3143105441 ps
CPU time 9.83 seconds
Started Jul 15 05:50:41 PM PDT 24
Finished Jul 15 05:50:52 PM PDT 24
Peak memory 211368 kb
Host smart-4d3570e5-f14c-409d-9944-337f24214962
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365624274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.365624274
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.81132630
Short name T207
Test name
Test status
Simulation time 1515735399 ps
CPU time 17.3 seconds
Started Jul 15 05:50:42 PM PDT 24
Finished Jul 15 05:51:00 PM PDT 24
Peak memory 213752 kb
Host smart-058154ac-b6ec-412e-98a7-bdb3abde08dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81132630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.81132630
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2888657283
Short name T327
Test name
Test status
Simulation time 17597473608 ps
CPU time 70.34 seconds
Started Jul 15 05:50:42 PM PDT 24
Finished Jul 15 05:51:53 PM PDT 24
Peak memory 217688 kb
Host smart-d6553c7a-3bbe-44e7-adfb-6a7562b4079f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888657283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2888657283
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3412881888
Short name T284
Test name
Test status
Simulation time 85574460 ps
CPU time 4.37 seconds
Started Jul 15 05:50:41 PM PDT 24
Finished Jul 15 05:50:46 PM PDT 24
Peak memory 211340 kb
Host smart-0c08c19f-5203-4316-a3ef-5c601c323db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412881888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3412881888
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1377081198
Short name T265
Test name
Test status
Simulation time 72182567355 ps
CPU time 184.85 seconds
Started Jul 15 05:50:41 PM PDT 24
Finished Jul 15 05:53:46 PM PDT 24
Peak memory 238880 kb
Host smart-b696f15a-2097-4e2e-8a51-69da084479d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377081198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1377081198
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.494393636
Short name T210
Test name
Test status
Simulation time 363347744 ps
CPU time 9.47 seconds
Started Jul 15 05:50:41 PM PDT 24
Finished Jul 15 05:50:51 PM PDT 24
Peak memory 211904 kb
Host smart-75e332dc-6c11-4965-a28b-3f757cb9aa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494393636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.494393636
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2240920262
Short name T250
Test name
Test status
Simulation time 7466564864 ps
CPU time 16.43 seconds
Started Jul 15 05:50:38 PM PDT 24
Finished Jul 15 05:50:54 PM PDT 24
Peak memory 211448 kb
Host smart-aa634712-10a9-49ce-be51-89033f017335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240920262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2240920262
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2197802956
Short name T70
Test name
Test status
Simulation time 1381052660 ps
CPU time 10.24 seconds
Started Jul 15 05:50:42 PM PDT 24
Finished Jul 15 05:50:53 PM PDT 24
Peak memory 213464 kb
Host smart-30e44a31-3ae5-43b3-ba6b-7cdcf4c56155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197802956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2197802956
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.455732617
Short name T248
Test name
Test status
Simulation time 14858557412 ps
CPU time 15.7 seconds
Started Jul 15 05:50:51 PM PDT 24
Finished Jul 15 05:51:08 PM PDT 24
Peak memory 211636 kb
Host smart-a7181c44-8566-493b-a60e-982aed9faa1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455732617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.455732617
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1893282797
Short name T55
Test name
Test status
Simulation time 3761694060 ps
CPU time 9.92 seconds
Started Jul 15 05:49:15 PM PDT 24
Finished Jul 15 05:49:26 PM PDT 24
Peak memory 211308 kb
Host smart-9a639f3b-525d-47d7-971c-f4092b764400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893282797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1893282797
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1336514618
Short name T237
Test name
Test status
Simulation time 148876580158 ps
CPU time 339.13 seconds
Started Jul 15 05:49:17 PM PDT 24
Finished Jul 15 05:54:57 PM PDT 24
Peak memory 234896 kb
Host smart-aba96ab4-f4af-4a81-b11c-c5afae0cefce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336514618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1336514618
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2590466928
Short name T350
Test name
Test status
Simulation time 21235392752 ps
CPU time 33.61 seconds
Started Jul 15 05:49:17 PM PDT 24
Finished Jul 15 05:49:52 PM PDT 24
Peak memory 212236 kb
Host smart-e33b9aef-d89e-4217-9436-e2592cef0146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590466928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2590466928
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4037143895
Short name T99
Test name
Test status
Simulation time 1292595597 ps
CPU time 12.54 seconds
Started Jul 15 05:49:17 PM PDT 24
Finished Jul 15 05:49:31 PM PDT 24
Peak memory 211376 kb
Host smart-a1c43b80-5e8b-40ae-9760-c72cd4b32c6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037143895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4037143895
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1122148692
Short name T242
Test name
Test status
Simulation time 6111358116 ps
CPU time 23.83 seconds
Started Jul 15 05:49:19 PM PDT 24
Finished Jul 15 05:49:44 PM PDT 24
Peak memory 213640 kb
Host smart-8268981e-0b7f-4205-a2fb-192d1525ec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122148692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1122148692
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2499647555
Short name T287
Test name
Test status
Simulation time 9248432697 ps
CPU time 54.48 seconds
Started Jul 15 05:49:18 PM PDT 24
Finished Jul 15 05:50:14 PM PDT 24
Peak memory 216272 kb
Host smart-2b1319e0-e819-4428-9009-914341a6f428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499647555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2499647555
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.407360821
Short name T43
Test name
Test status
Simulation time 142284380672 ps
CPU time 1401.97 seconds
Started Jul 15 05:49:20 PM PDT 24
Finished Jul 15 06:12:43 PM PDT 24
Peak memory 235780 kb
Host smart-e4622ea7-c674-4060-b579-984d6a00b387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407360821 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.407360821
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2683133565
Short name T56
Test name
Test status
Simulation time 6574990725 ps
CPU time 13.78 seconds
Started Jul 15 05:49:17 PM PDT 24
Finished Jul 15 05:49:32 PM PDT 24
Peak memory 211376 kb
Host smart-367b0924-257e-46ea-9cd2-d95086a31956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683133565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2683133565
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2179767373
Short name T37
Test name
Test status
Simulation time 209414024887 ps
CPU time 381.54 seconds
Started Jul 15 05:49:24 PM PDT 24
Finished Jul 15 05:55:46 PM PDT 24
Peak memory 234876 kb
Host smart-919a3ad2-f174-4a2f-be79-7c2b52fdf2fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179767373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2179767373
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2280333631
Short name T202
Test name
Test status
Simulation time 3748964445 ps
CPU time 27.12 seconds
Started Jul 15 05:49:18 PM PDT 24
Finished Jul 15 05:49:47 PM PDT 24
Peak memory 211884 kb
Host smart-6faa47e8-c8db-4ffc-9d03-9cc77ac646a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280333631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2280333631
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2975200999
Short name T318
Test name
Test status
Simulation time 2131974090 ps
CPU time 16.64 seconds
Started Jul 15 05:49:18 PM PDT 24
Finished Jul 15 05:49:36 PM PDT 24
Peak memory 211264 kb
Host smart-3da256c5-9a52-4565-ab98-e6c03f01aef8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975200999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2975200999
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2572504008
Short name T293
Test name
Test status
Simulation time 713770236 ps
CPU time 10.39 seconds
Started Jul 15 05:49:18 PM PDT 24
Finished Jul 15 05:49:29 PM PDT 24
Peak memory 213544 kb
Host smart-c7a8410a-c832-47f2-bde1-b64a38708ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572504008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2572504008
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2483050981
Short name T194
Test name
Test status
Simulation time 6079480359 ps
CPU time 52.09 seconds
Started Jul 15 05:49:17 PM PDT 24
Finished Jul 15 05:50:10 PM PDT 24
Peak memory 213060 kb
Host smart-b0afb9ed-e3f1-4ba4-83f1-bc8cf6d57f1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483050981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2483050981
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1585070685
Short name T288
Test name
Test status
Simulation time 133460041 ps
CPU time 5.08 seconds
Started Jul 15 05:49:28 PM PDT 24
Finished Jul 15 05:49:34 PM PDT 24
Peak memory 211240 kb
Host smart-0dc9ec45-d038-47f1-999b-c8405c3f77ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585070685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1585070685
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2224562291
Short name T297
Test name
Test status
Simulation time 2002909665 ps
CPU time 95.16 seconds
Started Jul 15 05:49:25 PM PDT 24
Finished Jul 15 05:51:00 PM PDT 24
Peak memory 237820 kb
Host smart-dd9d8837-d400-459f-b1ca-f8108d849006
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224562291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2224562291
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2648766079
Short name T320
Test name
Test status
Simulation time 11639476432 ps
CPU time 24.26 seconds
Started Jul 15 05:49:16 PM PDT 24
Finished Jul 15 05:49:40 PM PDT 24
Peak memory 212256 kb
Host smart-ba5aac84-1bfe-40de-aaaf-ccfacdb9782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648766079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2648766079
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3631746736
Short name T168
Test name
Test status
Simulation time 3486783402 ps
CPU time 10.49 seconds
Started Jul 15 05:49:19 PM PDT 24
Finished Jul 15 05:49:30 PM PDT 24
Peak memory 211464 kb
Host smart-63a060fd-f2d5-464d-b38d-922aacc5fe6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631746736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3631746736
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4051803561
Short name T336
Test name
Test status
Simulation time 3458533380 ps
CPU time 30.67 seconds
Started Jul 15 05:49:21 PM PDT 24
Finished Jul 15 05:49:52 PM PDT 24
Peak memory 211336 kb
Host smart-510496d7-eb04-461a-8c6a-983afaa73fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051803561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4051803561
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1045902419
Short name T273
Test name
Test status
Simulation time 6178183150 ps
CPU time 42.13 seconds
Started Jul 15 05:49:20 PM PDT 24
Finished Jul 15 05:50:03 PM PDT 24
Peak memory 217236 kb
Host smart-1657425a-95f1-434b-91b1-c548b3c4c332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045902419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1045902419
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2281722147
Short name T220
Test name
Test status
Simulation time 85890059 ps
CPU time 4.35 seconds
Started Jul 15 05:49:28 PM PDT 24
Finished Jul 15 05:49:33 PM PDT 24
Peak memory 211240 kb
Host smart-ece249d3-6bf9-49df-bcb3-8c4c7b23fb26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281722147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2281722147
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2531096881
Short name T157
Test name
Test status
Simulation time 20086558206 ps
CPU time 110.88 seconds
Started Jul 15 05:49:31 PM PDT 24
Finished Jul 15 05:51:23 PM PDT 24
Peak memory 212684 kb
Host smart-41ad7dcc-92cb-45bb-b8e8-59f4cc22aa12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531096881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2531096881
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2730250934
Short name T206
Test name
Test status
Simulation time 175538009 ps
CPU time 9.35 seconds
Started Jul 15 05:49:27 PM PDT 24
Finished Jul 15 05:49:37 PM PDT 24
Peak memory 211996 kb
Host smart-ec1b1664-bcb3-4e54-9ec4-a849ef1af845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730250934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2730250934
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3795665248
Short name T117
Test name
Test status
Simulation time 942556210 ps
CPU time 10.97 seconds
Started Jul 15 05:49:31 PM PDT 24
Finished Jul 15 05:49:42 PM PDT 24
Peak memory 211404 kb
Host smart-326a4b48-3bd5-4494-adda-837bf4767e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795665248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3795665248
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2256620317
Short name T75
Test name
Test status
Simulation time 3051358513 ps
CPU time 20.69 seconds
Started Jul 15 05:49:28 PM PDT 24
Finished Jul 15 05:49:49 PM PDT 24
Peak memory 213428 kb
Host smart-e8c6518d-0aff-48fb-ba07-a1c0b7e62649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256620317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2256620317
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2804138898
Short name T355
Test name
Test status
Simulation time 5590489280 ps
CPU time 44.34 seconds
Started Jul 15 05:49:27 PM PDT 24
Finished Jul 15 05:50:12 PM PDT 24
Peak memory 216480 kb
Host smart-f468718b-84ef-4c6b-acf7-c2338854867a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804138898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2804138898
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3814762968
Short name T6
Test name
Test status
Simulation time 1553606102 ps
CPU time 13.68 seconds
Started Jul 15 05:49:26 PM PDT 24
Finished Jul 15 05:49:40 PM PDT 24
Peak memory 211328 kb
Host smart-20276d03-3231-4814-8e69-1ac6ceca1940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814762968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3814762968
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.759251636
Short name T186
Test name
Test status
Simulation time 247381914298 ps
CPU time 310.41 seconds
Started Jul 15 05:49:25 PM PDT 24
Finished Jul 15 05:54:36 PM PDT 24
Peak memory 212664 kb
Host smart-d0a50802-e5bb-43af-b96a-59f3ea3224d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759251636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.759251636
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.331152425
Short name T345
Test name
Test status
Simulation time 3209451453 ps
CPU time 20.02 seconds
Started Jul 15 05:49:31 PM PDT 24
Finished Jul 15 05:49:52 PM PDT 24
Peak memory 211936 kb
Host smart-13d029dd-8014-40cb-92b6-26b8689164c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331152425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.331152425
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.565387449
Short name T175
Test name
Test status
Simulation time 8884214342 ps
CPU time 17.26 seconds
Started Jul 15 05:49:27 PM PDT 24
Finished Jul 15 05:49:44 PM PDT 24
Peak memory 211412 kb
Host smart-566d90b6-9eb8-46c5-a0fc-08be7d489319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565387449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.565387449
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2057649018
Short name T364
Test name
Test status
Simulation time 765260364 ps
CPU time 10.16 seconds
Started Jul 15 05:49:27 PM PDT 24
Finished Jul 15 05:49:38 PM PDT 24
Peak memory 213836 kb
Host smart-bae14677-16c8-41a5-84f0-28be64d29daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057649018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2057649018
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.540755935
Short name T173
Test name
Test status
Simulation time 11704773551 ps
CPU time 65.88 seconds
Started Jul 15 05:49:30 PM PDT 24
Finished Jul 15 05:50:37 PM PDT 24
Peak memory 216268 kb
Host smart-ba71ec15-7d89-4b3f-ae2b-ab1a6f6f64bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540755935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.540755935
Directory /workspace/9.rom_ctrl_stress_all/latest
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