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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 96.89 91.85 97.67 100.00 98.28 97.30 98.37


Total test records in report: 463
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T298 /workspace/coverage/default/17.rom_ctrl_smoke.2386208892 Jul 16 07:06:14 PM PDT 24 Jul 16 07:06:41 PM PDT 24 8540070377 ps
T299 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3096646983 Jul 16 07:06:13 PM PDT 24 Jul 16 07:06:46 PM PDT 24 4013966917 ps
T300 /workspace/coverage/default/11.rom_ctrl_alert_test.307200466 Jul 16 07:06:17 PM PDT 24 Jul 16 07:06:31 PM PDT 24 1150465437 ps
T301 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3265764919 Jul 16 07:06:42 PM PDT 24 Jul 16 07:06:52 PM PDT 24 5689859109 ps
T302 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.199718105 Jul 16 07:06:17 PM PDT 24 Jul 16 07:08:20 PM PDT 24 12422304312 ps
T303 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.324748404 Jul 16 07:06:38 PM PDT 24 Jul 16 07:06:45 PM PDT 24 371673724 ps
T304 /workspace/coverage/default/25.rom_ctrl_smoke.4229636794 Jul 16 07:06:36 PM PDT 24 Jul 16 07:07:01 PM PDT 24 2134812817 ps
T305 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2263758817 Jul 16 07:06:13 PM PDT 24 Jul 16 07:06:30 PM PDT 24 1790191099 ps
T306 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2388013617 Jul 16 07:06:00 PM PDT 24 Jul 16 07:08:02 PM PDT 24 4015876538 ps
T307 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1537597786 Jul 16 07:06:41 PM PDT 24 Jul 16 07:06:59 PM PDT 24 8156594543 ps
T308 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2899651594 Jul 16 07:06:39 PM PDT 24 Jul 16 07:06:47 PM PDT 24 380699534 ps
T309 /workspace/coverage/default/29.rom_ctrl_smoke.995744274 Jul 16 07:06:26 PM PDT 24 Jul 16 07:06:41 PM PDT 24 3280007749 ps
T310 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1394181015 Jul 16 07:06:00 PM PDT 24 Jul 16 07:06:07 PM PDT 24 98854304 ps
T311 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2189162775 Jul 16 07:06:50 PM PDT 24 Jul 16 07:08:22 PM PDT 24 2584384360 ps
T312 /workspace/coverage/default/42.rom_ctrl_smoke.2899749168 Jul 16 07:06:46 PM PDT 24 Jul 16 07:06:58 PM PDT 24 1283108731 ps
T313 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3093953877 Jul 16 07:06:39 PM PDT 24 Jul 16 07:10:12 PM PDT 24 23048474153 ps
T104 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.569407264 Jul 16 07:06:26 PM PDT 24 Jul 16 07:32:30 PM PDT 24 45837481861 ps
T314 /workspace/coverage/default/18.rom_ctrl_smoke.979097829 Jul 16 07:06:19 PM PDT 24 Jul 16 07:06:32 PM PDT 24 445039974 ps
T315 /workspace/coverage/default/1.rom_ctrl_smoke.793555063 Jul 16 07:06:01 PM PDT 24 Jul 16 07:06:36 PM PDT 24 4048081123 ps
T316 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1877261461 Jul 16 07:06:18 PM PDT 24 Jul 16 07:06:50 PM PDT 24 13144833874 ps
T317 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.875926262 Jul 16 07:06:57 PM PDT 24 Jul 16 07:10:52 PM PDT 24 24158293979 ps
T318 /workspace/coverage/default/10.rom_ctrl_smoke.2462629597 Jul 16 07:06:15 PM PDT 24 Jul 16 07:06:46 PM PDT 24 15643313905 ps
T319 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.395833092 Jul 16 07:06:15 PM PDT 24 Jul 16 07:06:27 PM PDT 24 692954461 ps
T320 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3804824433 Jul 16 07:06:27 PM PDT 24 Jul 16 07:06:44 PM PDT 24 7381232170 ps
T321 /workspace/coverage/default/35.rom_ctrl_smoke.3003706699 Jul 16 07:06:37 PM PDT 24 Jul 16 07:06:54 PM PDT 24 2949317072 ps
T322 /workspace/coverage/default/46.rom_ctrl_smoke.3339497537 Jul 16 07:07:04 PM PDT 24 Jul 16 07:07:38 PM PDT 24 7350366828 ps
T323 /workspace/coverage/default/25.rom_ctrl_stress_all.2135183931 Jul 16 07:06:38 PM PDT 24 Jul 16 07:07:41 PM PDT 24 7166289311 ps
T324 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2503159486 Jul 16 07:06:13 PM PDT 24 Jul 16 07:06:19 PM PDT 24 425184403 ps
T325 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3628734108 Jul 16 07:06:37 PM PDT 24 Jul 16 07:06:52 PM PDT 24 4666128872 ps
T326 /workspace/coverage/default/28.rom_ctrl_smoke.3753864827 Jul 16 07:06:44 PM PDT 24 Jul 16 07:06:55 PM PDT 24 1733351410 ps
T327 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1790590949 Jul 16 07:06:00 PM PDT 24 Jul 16 07:11:16 PM PDT 24 31467524394 ps
T328 /workspace/coverage/default/45.rom_ctrl_alert_test.344834787 Jul 16 07:06:59 PM PDT 24 Jul 16 07:07:13 PM PDT 24 1664071077 ps
T329 /workspace/coverage/default/12.rom_ctrl_smoke.2073053287 Jul 16 07:06:16 PM PDT 24 Jul 16 07:06:47 PM PDT 24 3069881755 ps
T330 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2009551268 Jul 16 07:05:53 PM PDT 24 Jul 16 07:06:11 PM PDT 24 10466672846 ps
T331 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4190015830 Jul 16 07:06:18 PM PDT 24 Jul 16 07:06:36 PM PDT 24 3331003879 ps
T332 /workspace/coverage/default/22.rom_ctrl_alert_test.2015273813 Jul 16 07:06:29 PM PDT 24 Jul 16 07:06:40 PM PDT 24 1077613247 ps
T333 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.605479048 Jul 16 07:06:39 PM PDT 24 Jul 16 07:06:55 PM PDT 24 6019830352 ps
T334 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.768174328 Jul 16 07:06:44 PM PDT 24 Jul 16 07:08:43 PM PDT 24 3707320134 ps
T335 /workspace/coverage/default/19.rom_ctrl_smoke.3906051084 Jul 16 07:06:25 PM PDT 24 Jul 16 07:06:44 PM PDT 24 1084891169 ps
T336 /workspace/coverage/default/43.rom_ctrl_smoke.1963991080 Jul 16 07:06:52 PM PDT 24 Jul 16 07:07:03 PM PDT 24 193919774 ps
T337 /workspace/coverage/default/48.rom_ctrl_smoke.177532558 Jul 16 07:06:57 PM PDT 24 Jul 16 07:07:34 PM PDT 24 4037686598 ps
T338 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2727575847 Jul 16 07:06:35 PM PDT 24 Jul 16 07:08:35 PM PDT 24 1917446746 ps
T339 /workspace/coverage/default/3.rom_ctrl_stress_all.1230191658 Jul 16 07:06:10 PM PDT 24 Jul 16 07:06:30 PM PDT 24 693492815 ps
T340 /workspace/coverage/default/2.rom_ctrl_stress_all.1479502224 Jul 16 07:05:57 PM PDT 24 Jul 16 07:06:32 PM PDT 24 12980760515 ps
T341 /workspace/coverage/default/0.rom_ctrl_smoke.4086508911 Jul 16 07:06:14 PM PDT 24 Jul 16 07:06:26 PM PDT 24 296508735 ps
T342 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3253631694 Jul 16 07:06:34 PM PDT 24 Jul 16 07:06:45 PM PDT 24 1433208136 ps
T343 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2674379973 Jul 16 07:06:13 PM PDT 24 Jul 16 07:06:22 PM PDT 24 3299014768 ps
T344 /workspace/coverage/default/4.rom_ctrl_alert_test.3354842162 Jul 16 07:06:08 PM PDT 24 Jul 16 07:06:24 PM PDT 24 1832684491 ps
T345 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1590910089 Jul 16 07:06:28 PM PDT 24 Jul 16 07:40:38 PM PDT 24 57671363524 ps
T346 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1060467487 Jul 16 07:06:39 PM PDT 24 Jul 16 07:10:44 PM PDT 24 22562123399 ps
T347 /workspace/coverage/default/23.rom_ctrl_smoke.3875166612 Jul 16 07:06:31 PM PDT 24 Jul 16 07:06:59 PM PDT 24 16153904830 ps
T348 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3735245571 Jul 16 07:07:01 PM PDT 24 Jul 16 07:09:46 PM PDT 24 77279550387 ps
T349 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2383209211 Jul 16 07:06:39 PM PDT 24 Jul 16 07:08:52 PM PDT 24 14919523539 ps
T350 /workspace/coverage/default/35.rom_ctrl_stress_all.767500198 Jul 16 07:06:39 PM PDT 24 Jul 16 07:06:56 PM PDT 24 11189371424 ps
T351 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.523957660 Jul 16 07:06:17 PM PDT 24 Jul 16 07:08:59 PM PDT 24 2468551506 ps
T352 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.997254121 Jul 16 07:07:07 PM PDT 24 Jul 16 07:07:24 PM PDT 24 5801176596 ps
T353 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2669130112 Jul 16 07:06:51 PM PDT 24 Jul 16 07:07:16 PM PDT 24 4985071771 ps
T354 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2310834744 Jul 16 07:06:37 PM PDT 24 Jul 16 07:11:03 PM PDT 24 96729314740 ps
T355 /workspace/coverage/default/5.rom_ctrl_stress_all.1939474179 Jul 16 07:06:13 PM PDT 24 Jul 16 07:06:54 PM PDT 24 3366858473 ps
T356 /workspace/coverage/default/47.rom_ctrl_smoke.3324675038 Jul 16 07:07:03 PM PDT 24 Jul 16 07:07:24 PM PDT 24 1653154649 ps
T357 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1715413573 Jul 16 07:06:26 PM PDT 24 Jul 16 07:36:13 PM PDT 24 197092956100 ps
T358 /workspace/coverage/default/29.rom_ctrl_alert_test.2906074213 Jul 16 07:06:37 PM PDT 24 Jul 16 07:06:47 PM PDT 24 1361528762 ps
T359 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2311391254 Jul 16 07:07:10 PM PDT 24 Jul 16 07:07:20 PM PDT 24 178416984 ps
T360 /workspace/coverage/default/49.rom_ctrl_stress_all.471152125 Jul 16 07:07:08 PM PDT 24 Jul 16 07:07:58 PM PDT 24 2855108986 ps
T361 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.853533314 Jul 16 07:06:07 PM PDT 24 Jul 16 07:08:19 PM PDT 24 10050612298 ps
T362 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3782216978 Jul 16 07:06:00 PM PDT 24 Jul 16 07:06:16 PM PDT 24 1726432589 ps
T363 /workspace/coverage/default/12.rom_ctrl_alert_test.1505787634 Jul 16 07:06:17 PM PDT 24 Jul 16 07:06:33 PM PDT 24 3882188507 ps
T364 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2699286133 Jul 16 07:06:47 PM PDT 24 Jul 16 07:10:31 PM PDT 24 17665204220 ps
T61 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3181682290 Jul 16 07:05:50 PM PDT 24 Jul 16 07:06:05 PM PDT 24 1737076887 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4279320959 Jul 16 07:05:41 PM PDT 24 Jul 16 07:05:52 PM PDT 24 172715366 ps
T62 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2185733481 Jul 16 07:05:53 PM PDT 24 Jul 16 07:06:45 PM PDT 24 7943497011 ps
T57 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1558178690 Jul 16 07:05:52 PM PDT 24 Jul 16 07:06:33 PM PDT 24 273476923 ps
T58 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.18012912 Jul 16 07:05:46 PM PDT 24 Jul 16 07:06:28 PM PDT 24 3823519816 ps
T100 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2042024579 Jul 16 07:05:41 PM PDT 24 Jul 16 07:05:52 PM PDT 24 1754661016 ps
T101 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.174888424 Jul 16 07:05:59 PM PDT 24 Jul 16 07:06:22 PM PDT 24 2120274367 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1261194851 Jul 16 07:05:43 PM PDT 24 Jul 16 07:05:49 PM PDT 24 89017981 ps
T367 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3739425202 Jul 16 07:05:41 PM PDT 24 Jul 16 07:05:55 PM PDT 24 5957556894 ps
T95 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4155861263 Jul 16 07:05:49 PM PDT 24 Jul 16 07:05:56 PM PDT 24 392399935 ps
T96 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2445481551 Jul 16 07:06:02 PM PDT 24 Jul 16 07:06:11 PM PDT 24 2589818166 ps
T368 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.953623608 Jul 16 07:05:35 PM PDT 24 Jul 16 07:05:43 PM PDT 24 982959409 ps
T59 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3870237622 Jul 16 07:05:37 PM PDT 24 Jul 16 07:06:57 PM PDT 24 4052814376 ps
T70 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3382349879 Jul 16 07:05:48 PM PDT 24 Jul 16 07:06:04 PM PDT 24 1922508876 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3593004404 Jul 16 07:05:36 PM PDT 24 Jul 16 07:05:48 PM PDT 24 1335443034 ps
T370 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2365120340 Jul 16 07:06:03 PM PDT 24 Jul 16 07:06:09 PM PDT 24 157597241 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1011574168 Jul 16 07:06:13 PM PDT 24 Jul 16 07:07:33 PM PDT 24 36038353836 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3301209755 Jul 16 07:05:33 PM PDT 24 Jul 16 07:05:41 PM PDT 24 1574201126 ps
T72 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1707913573 Jul 16 07:05:59 PM PDT 24 Jul 16 07:06:06 PM PDT 24 447051607 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1791677407 Jul 16 07:05:38 PM PDT 24 Jul 16 07:05:53 PM PDT 24 3750288006 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.837719040 Jul 16 07:05:40 PM PDT 24 Jul 16 07:05:51 PM PDT 24 1362727469 ps
T102 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1341358157 Jul 16 07:05:53 PM PDT 24 Jul 16 07:06:03 PM PDT 24 255884221 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1502221298 Jul 16 07:05:36 PM PDT 24 Jul 16 07:05:52 PM PDT 24 1711118724 ps
T73 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1604061395 Jul 16 07:05:58 PM PDT 24 Jul 16 07:07:23 PM PDT 24 183513216465 ps
T105 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2781936195 Jul 16 07:06:10 PM PDT 24 Jul 16 07:07:23 PM PDT 24 963608642 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.319002479 Jul 16 07:05:51 PM PDT 24 Jul 16 07:06:07 PM PDT 24 1652401591 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4286079456 Jul 16 07:05:35 PM PDT 24 Jul 16 07:05:46 PM PDT 24 4443608489 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.271493784 Jul 16 07:06:09 PM PDT 24 Jul 16 07:06:21 PM PDT 24 1691639467 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1803221346 Jul 16 07:05:52 PM PDT 24 Jul 16 07:06:00 PM PDT 24 182696919 ps
T74 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1538924053 Jul 16 07:05:56 PM PDT 24 Jul 16 07:06:13 PM PDT 24 3135979158 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.793353572 Jul 16 07:05:43 PM PDT 24 Jul 16 07:05:50 PM PDT 24 168162161 ps
T97 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3522005104 Jul 16 07:05:52 PM PDT 24 Jul 16 07:06:07 PM PDT 24 6339741344 ps
T106 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2816206945 Jul 16 07:05:53 PM PDT 24 Jul 16 07:06:34 PM PDT 24 2381982511 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.41853730 Jul 16 07:05:33 PM PDT 24 Jul 16 07:05:39 PM PDT 24 127080937 ps
T381 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1933768096 Jul 16 07:06:07 PM PDT 24 Jul 16 07:06:20 PM PDT 24 5268444692 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.783477281 Jul 16 07:05:45 PM PDT 24 Jul 16 07:07:01 PM PDT 24 14427423064 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2603151805 Jul 16 07:05:36 PM PDT 24 Jul 16 07:06:06 PM PDT 24 2336708786 ps
T111 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4068646852 Jul 16 07:05:57 PM PDT 24 Jul 16 07:07:14 PM PDT 24 5652181037 ps
T382 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3713435943 Jul 16 07:05:53 PM PDT 24 Jul 16 07:06:43 PM PDT 24 24019681666 ps
T383 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1824053570 Jul 16 07:05:56 PM PDT 24 Jul 16 07:06:13 PM PDT 24 2002616380 ps
T384 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3248228611 Jul 16 07:05:58 PM PDT 24 Jul 16 07:07:23 PM PDT 24 19182869032 ps
T385 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.189143627 Jul 16 07:05:52 PM PDT 24 Jul 16 07:05:58 PM PDT 24 361449335 ps
T76 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1221405959 Jul 16 07:05:44 PM PDT 24 Jul 16 07:05:50 PM PDT 24 85436306 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2374588045 Jul 16 07:06:06 PM PDT 24 Jul 16 07:06:18 PM PDT 24 8259015900 ps
T98 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1864137538 Jul 16 07:05:46 PM PDT 24 Jul 16 07:05:55 PM PDT 24 1598540513 ps
T77 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2798606321 Jul 16 07:05:46 PM PDT 24 Jul 16 07:06:07 PM PDT 24 380459979 ps
T109 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1901892055 Jul 16 07:06:06 PM PDT 24 Jul 16 07:06:52 PM PDT 24 3630248671 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.200529531 Jul 16 07:05:38 PM PDT 24 Jul 16 07:05:53 PM PDT 24 1448762464 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3335638780 Jul 16 07:05:39 PM PDT 24 Jul 16 07:05:54 PM PDT 24 10025252938 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1139407594 Jul 16 07:05:37 PM PDT 24 Jul 16 07:05:47 PM PDT 24 696824956 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3158466012 Jul 16 07:06:11 PM PDT 24 Jul 16 07:07:11 PM PDT 24 7403990969 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3624889239 Jul 16 07:05:40 PM PDT 24 Jul 16 07:05:50 PM PDT 24 2477898587 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3718557957 Jul 16 07:05:37 PM PDT 24 Jul 16 07:05:55 PM PDT 24 1620440877 ps
T110 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4159108732 Jul 16 07:05:44 PM PDT 24 Jul 16 07:06:55 PM PDT 24 1115094478 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.510880615 Jul 16 07:05:43 PM PDT 24 Jul 16 07:06:11 PM PDT 24 2126801215 ps
T392 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2905949065 Jul 16 07:05:54 PM PDT 24 Jul 16 07:06:07 PM PDT 24 2998290705 ps
T393 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2213044587 Jul 16 07:05:53 PM PDT 24 Jul 16 07:06:12 PM PDT 24 4011051662 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.79049078 Jul 16 07:05:52 PM PDT 24 Jul 16 07:05:58 PM PDT 24 85738348 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1772969129 Jul 16 07:06:05 PM PDT 24 Jul 16 07:06:17 PM PDT 24 1159901984 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2680063433 Jul 16 07:05:50 PM PDT 24 Jul 16 07:06:05 PM PDT 24 1824903623 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1646886262 Jul 16 07:05:40 PM PDT 24 Jul 16 07:05:48 PM PDT 24 1559301007 ps
T397 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2990175639 Jul 16 07:05:58 PM PDT 24 Jul 16 07:06:04 PM PDT 24 252403167 ps
T99 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2320033495 Jul 16 07:05:37 PM PDT 24 Jul 16 07:05:44 PM PDT 24 96942188 ps
T86 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2878312716 Jul 16 07:05:56 PM PDT 24 Jul 16 07:06:13 PM PDT 24 4266782709 ps
T89 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1384004970 Jul 16 07:05:42 PM PDT 24 Jul 16 07:07:03 PM PDT 24 9389073739 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.62413593 Jul 16 07:05:59 PM PDT 24 Jul 16 07:06:13 PM PDT 24 1391389512 ps
T92 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3965102674 Jul 16 07:05:55 PM PDT 24 Jul 16 07:06:03 PM PDT 24 472180058 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2719894719 Jul 16 07:05:53 PM PDT 24 Jul 16 07:06:04 PM PDT 24 851929334 ps
T400 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2331651291 Jul 16 07:06:04 PM PDT 24 Jul 16 07:06:14 PM PDT 24 2804691066 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.513713534 Jul 16 07:05:46 PM PDT 24 Jul 16 07:06:05 PM PDT 24 5869541748 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.134334479 Jul 16 07:05:33 PM PDT 24 Jul 16 07:05:48 PM PDT 24 2931264287 ps
T113 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2655812486 Jul 16 07:05:50 PM PDT 24 Jul 16 07:07:07 PM PDT 24 7486871820 ps
T112 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3761665978 Jul 16 07:05:50 PM PDT 24 Jul 16 07:07:03 PM PDT 24 1578717052 ps
T403 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.763996237 Jul 16 07:06:03 PM PDT 24 Jul 16 07:06:45 PM PDT 24 1495966789 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4137374578 Jul 16 07:05:50 PM PDT 24 Jul 16 07:05:58 PM PDT 24 429584101 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1185138052 Jul 16 07:05:38 PM PDT 24 Jul 16 07:05:44 PM PDT 24 168234248 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1829167012 Jul 16 07:05:53 PM PDT 24 Jul 16 07:07:34 PM PDT 24 12819195544 ps
T406 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2084138943 Jul 16 07:05:59 PM PDT 24 Jul 16 07:06:14 PM PDT 24 980469603 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2682187904 Jul 16 07:05:57 PM PDT 24 Jul 16 07:06:11 PM PDT 24 5683182128 ps
T408 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.67854625 Jul 16 07:06:04 PM PDT 24 Jul 16 07:06:15 PM PDT 24 1146741408 ps
T409 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1021394357 Jul 16 07:06:05 PM PDT 24 Jul 16 07:06:55 PM PDT 24 25526604882 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2434523792 Jul 16 07:05:40 PM PDT 24 Jul 16 07:05:53 PM PDT 24 5139657464 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.749693647 Jul 16 07:05:39 PM PDT 24 Jul 16 07:05:49 PM PDT 24 1236935815 ps
T90 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.867912328 Jul 16 07:06:07 PM PDT 24 Jul 16 07:07:28 PM PDT 24 17264811269 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3048037140 Jul 16 07:05:38 PM PDT 24 Jul 16 07:05:53 PM PDT 24 1111147984 ps
T115 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2131858980 Jul 16 07:05:43 PM PDT 24 Jul 16 07:07:00 PM PDT 24 702515832 ps
T413 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1259263827 Jul 16 07:06:02 PM PDT 24 Jul 16 07:06:20 PM PDT 24 5107899899 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1305238246 Jul 16 07:05:54 PM PDT 24 Jul 16 07:06:08 PM PDT 24 6008224498 ps
T415 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3162811820 Jul 16 07:06:04 PM PDT 24 Jul 16 07:06:15 PM PDT 24 3748722636 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3489613244 Jul 16 07:05:50 PM PDT 24 Jul 16 07:06:07 PM PDT 24 2119013606 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1002159528 Jul 16 07:05:51 PM PDT 24 Jul 16 07:06:39 PM PDT 24 2042068476 ps
T418 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1547190407 Jul 16 07:05:44 PM PDT 24 Jul 16 07:05:53 PM PDT 24 239933981 ps
T87 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2197231063 Jul 16 07:05:51 PM PDT 24 Jul 16 07:05:56 PM PDT 24 85554062 ps
T91 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.676873243 Jul 16 07:05:54 PM PDT 24 Jul 16 07:07:14 PM PDT 24 9005034105 ps
T419 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.645909032 Jul 16 07:06:07 PM PDT 24 Jul 16 07:06:17 PM PDT 24 532065545 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1350618444 Jul 16 07:06:01 PM PDT 24 Jul 16 07:06:09 PM PDT 24 2145925060 ps
T421 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2697405383 Jul 16 07:05:39 PM PDT 24 Jul 16 07:06:13 PM PDT 24 2077996703 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3494395702 Jul 16 07:05:52 PM PDT 24 Jul 16 07:06:04 PM PDT 24 2749767740 ps
T423 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.928430365 Jul 16 07:05:39 PM PDT 24 Jul 16 07:05:45 PM PDT 24 554940637 ps
T108 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1473925705 Jul 16 07:05:53 PM PDT 24 Jul 16 07:07:03 PM PDT 24 3833365682 ps
T424 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2791573562 Jul 16 07:05:44 PM PDT 24 Jul 16 07:06:05 PM PDT 24 22628957991 ps
T425 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2604543426 Jul 16 07:05:56 PM PDT 24 Jul 16 07:06:11 PM PDT 24 4942765726 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3036036065 Jul 16 07:05:46 PM PDT 24 Jul 16 07:05:52 PM PDT 24 101485361 ps
T114 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.274911979 Jul 16 07:05:53 PM PDT 24 Jul 16 07:07:03 PM PDT 24 815166622 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4070843387 Jul 16 07:05:49 PM PDT 24 Jul 16 07:05:59 PM PDT 24 809877259 ps
T428 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.331095516 Jul 16 07:05:52 PM PDT 24 Jul 16 07:06:05 PM PDT 24 877442185 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4030449021 Jul 16 07:05:53 PM PDT 24 Jul 16 07:06:05 PM PDT 24 1413786243 ps
T430 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.15705249 Jul 16 07:05:37 PM PDT 24 Jul 16 07:05:49 PM PDT 24 3788318122 ps
T431 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3198899578 Jul 16 07:05:52 PM PDT 24 Jul 16 07:06:09 PM PDT 24 3335831374 ps
T432 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.490858406 Jul 16 07:05:43 PM PDT 24 Jul 16 07:06:01 PM PDT 24 1328163695 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4045949517 Jul 16 07:05:45 PM PDT 24 Jul 16 07:06:01 PM PDT 24 6940470551 ps
T93 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4274635812 Jul 16 07:05:47 PM PDT 24 Jul 16 07:05:52 PM PDT 24 553273422 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.297221829 Jul 16 07:05:36 PM PDT 24 Jul 16 07:05:52 PM PDT 24 3884142892 ps
T434 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3093550299 Jul 16 07:06:01 PM PDT 24 Jul 16 07:06:44 PM PDT 24 1396081378 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4149622924 Jul 16 07:05:59 PM PDT 24 Jul 16 07:06:09 PM PDT 24 1400739370 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1909455130 Jul 16 07:05:38 PM PDT 24 Jul 16 07:05:55 PM PDT 24 1993585053 ps
T437 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2568652159 Jul 16 07:05:55 PM PDT 24 Jul 16 07:06:03 PM PDT 24 88989764 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2696401870 Jul 16 07:05:58 PM PDT 24 Jul 16 07:06:07 PM PDT 24 259921865 ps
T116 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.991718348 Jul 16 07:05:52 PM PDT 24 Jul 16 07:07:02 PM PDT 24 211639398 ps
T439 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.578093922 Jul 16 07:06:00 PM PDT 24 Jul 16 07:07:04 PM PDT 24 29437712064 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2042930379 Jul 16 07:05:52 PM PDT 24 Jul 16 07:07:07 PM PDT 24 7167028460 ps
T441 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.290792926 Jul 16 07:05:43 PM PDT 24 Jul 16 07:05:56 PM PDT 24 3594920218 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2237640629 Jul 16 07:05:45 PM PDT 24 Jul 16 07:07:10 PM PDT 24 4548226011 ps
T443 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2476156016 Jul 16 07:06:09 PM PDT 24 Jul 16 07:06:16 PM PDT 24 4404523847 ps
T117 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1064848886 Jul 16 07:05:50 PM PDT 24 Jul 16 07:06:32 PM PDT 24 4603345958 ps
T444 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1284228929 Jul 16 07:06:08 PM PDT 24 Jul 16 07:06:19 PM PDT 24 2019267933 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.463208400 Jul 16 07:05:48 PM PDT 24 Jul 16 07:05:54 PM PDT 24 87447275 ps
T446 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.580301595 Jul 16 07:05:49 PM PDT 24 Jul 16 07:06:04 PM PDT 24 5584556823 ps
T447 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3578238210 Jul 16 07:05:48 PM PDT 24 Jul 16 07:06:10 PM PDT 24 2059117946 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2188062207 Jul 16 07:05:43 PM PDT 24 Jul 16 07:06:00 PM PDT 24 8494950931 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1027396233 Jul 16 07:05:57 PM PDT 24 Jul 16 07:06:10 PM PDT 24 1403450985 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.180327320 Jul 16 07:05:39 PM PDT 24 Jul 16 07:05:45 PM PDT 24 333575622 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.209182033 Jul 16 07:06:00 PM PDT 24 Jul 16 07:07:08 PM PDT 24 16349374416 ps
T452 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3653507638 Jul 16 07:05:44 PM PDT 24 Jul 16 07:06:04 PM PDT 24 1891284293 ps
T453 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4207087945 Jul 16 07:05:56 PM PDT 24 Jul 16 07:06:11 PM PDT 24 7758076312 ps
T454 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3353646405 Jul 16 07:05:56 PM PDT 24 Jul 16 07:06:01 PM PDT 24 462930962 ps
T455 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3360393532 Jul 16 07:05:51 PM PDT 24 Jul 16 07:06:06 PM PDT 24 6091086504 ps
T456 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.716747663 Jul 16 07:05:36 PM PDT 24 Jul 16 07:06:33 PM PDT 24 34480220043 ps
T457 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4129001561 Jul 16 07:05:48 PM PDT 24 Jul 16 07:05:55 PM PDT 24 691145633 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1553518112 Jul 16 07:05:34 PM PDT 24 Jul 16 07:05:46 PM PDT 24 989535232 ps
T459 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3766780879 Jul 16 07:06:07 PM PDT 24 Jul 16 07:06:20 PM PDT 24 2678228552 ps
T460 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1782546172 Jul 16 07:05:49 PM PDT 24 Jul 16 07:06:05 PM PDT 24 2324302742 ps
T461 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1450373344 Jul 16 07:06:07 PM PDT 24 Jul 16 07:06:27 PM PDT 24 8840959700 ps
T462 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4202422513 Jul 16 07:05:54 PM PDT 24 Jul 16 07:06:06 PM PDT 24 1079748750 ps
T463 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1543293156 Jul 16 07:05:59 PM PDT 24 Jul 16 07:06:10 PM PDT 24 922899352 ps

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3413664949
Short name T7
Test name
Test status
Simulation time 29365588257 ps
CPU time 2616.22 seconds
Started Jul 16 07:06:27 PM PDT 24
Finished Jul 16 07:50:04 PM PDT 24
Peak memory 235740 kb
Host smart-24fb9db2-f744-4180-95f5-0c84b4578687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413664949 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3413664949
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3286910236
Short name T2
Test name
Test status
Simulation time 161101257962 ps
CPU time 355.29 seconds
Started Jul 16 07:06:53 PM PDT 24
Finished Jul 16 07:12:49 PM PDT 24
Peak memory 236716 kb
Host smart-931ecf01-1b35-418c-82aa-f6d8d011348b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286910236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3286910236
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3768075199
Short name T47
Test name
Test status
Simulation time 3459986927 ps
CPU time 16.69 seconds
Started Jul 16 07:06:29 PM PDT 24
Finished Jul 16 07:06:46 PM PDT 24
Peak memory 214176 kb
Host smart-534839f7-0bc0-42aa-a0e7-1a4805291e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768075199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3768075199
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2781936195
Short name T105
Test name
Test status
Simulation time 963608642 ps
CPU time 71.94 seconds
Started Jul 16 07:06:10 PM PDT 24
Finished Jul 16 07:07:23 PM PDT 24
Peak memory 218984 kb
Host smart-800231e7-a26a-4107-945a-74323d8ca2cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781936195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2781936195
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.950686411
Short name T39
Test name
Test status
Simulation time 4007294197 ps
CPU time 129.38 seconds
Started Jul 16 07:06:43 PM PDT 24
Finished Jul 16 07:08:54 PM PDT 24
Peak memory 225384 kb
Host smart-6f97bac9-2b8b-441c-bc8c-5db68a18e9eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950686411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.950686411
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2603151805
Short name T75
Test name
Test status
Simulation time 2336708786 ps
CPU time 28.78 seconds
Started Jul 16 07:05:36 PM PDT 24
Finished Jul 16 07:06:06 PM PDT 24
Peak memory 210864 kb
Host smart-7b7c1376-b223-46e4-9f2f-ebd2f5d8b28b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603151805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2603151805
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3721198732
Short name T29
Test name
Test status
Simulation time 8155856608 ps
CPU time 63.61 seconds
Started Jul 16 07:06:03 PM PDT 24
Finished Jul 16 07:07:07 PM PDT 24
Peak memory 237056 kb
Host smart-83d4d1df-c6bf-4421-952e-ac081dca5904
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721198732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3721198732
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1272725626
Short name T10
Test name
Test status
Simulation time 332913533 ps
CPU time 4.25 seconds
Started Jul 16 07:07:09 PM PDT 24
Finished Jul 16 07:07:14 PM PDT 24
Peak memory 211336 kb
Host smart-2133e874-2cd9-4941-8fd0-1df99ca4ab18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272725626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1272725626
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4159108732
Short name T110
Test name
Test status
Simulation time 1115094478 ps
CPU time 69.53 seconds
Started Jul 16 07:05:44 PM PDT 24
Finished Jul 16 07:06:55 PM PDT 24
Peak memory 218956 kb
Host smart-4360c80c-0100-4254-8dcb-1b5d975e3d6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159108732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4159108732
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1473925705
Short name T108
Test name
Test status
Simulation time 3833365682 ps
CPU time 68.13 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:07:03 PM PDT 24
Peak memory 219084 kb
Host smart-a934c98c-29d7-402d-bffa-e0b90ebc7988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473925705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1473925705
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2552937344
Short name T130
Test name
Test status
Simulation time 11938869477 ps
CPU time 27.21 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:06:42 PM PDT 24
Peak memory 212224 kb
Host smart-acd04b1d-840c-4f85-b818-86cd18825e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552937344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2552937344
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4235762205
Short name T220
Test name
Test status
Simulation time 7293334734 ps
CPU time 21.33 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:38 PM PDT 24
Peak memory 212412 kb
Host smart-872b79ea-9991-4728-923e-e85449ae7ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235762205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4235762205
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2729836483
Short name T25
Test name
Test status
Simulation time 188197025 ps
CPU time 5.46 seconds
Started Jul 16 07:06:53 PM PDT 24
Finished Jul 16 07:07:00 PM PDT 24
Peak memory 211288 kb
Host smart-aef43b73-8e23-4724-8c4a-c8e156d6b985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729836483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2729836483
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4074675841
Short name T137
Test name
Test status
Simulation time 1183070249 ps
CPU time 17.09 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 07:06:58 PM PDT 24
Peak memory 215464 kb
Host smart-bcd4e5eb-0969-43c8-bb37-060fdf3be278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074675841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4074675841
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2185733481
Short name T62
Test name
Test status
Simulation time 7943497011 ps
CPU time 50.42 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:06:45 PM PDT 24
Peak memory 210712 kb
Host smart-532440fb-2ec3-4158-92f9-6b0af5020b7f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185733481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2185733481
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4068646852
Short name T111
Test name
Test status
Simulation time 5652181037 ps
CPU time 75.23 seconds
Started Jul 16 07:05:57 PM PDT 24
Finished Jul 16 07:07:14 PM PDT 24
Peak memory 211420 kb
Host smart-df5f8dfb-5324-45a5-b13c-4c9b3e158055
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068646852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4068646852
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4279320959
Short name T365
Test name
Test status
Simulation time 172715366 ps
CPU time 9.6 seconds
Started Jul 16 07:05:41 PM PDT 24
Finished Jul 16 07:05:52 PM PDT 24
Peak memory 218904 kb
Host smart-d8641cea-9bba-4ed7-a0de-e854a99e0883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279320959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4279320959
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.15705249
Short name T430
Test name
Test status
Simulation time 3788318122 ps
CPU time 9.99 seconds
Started Jul 16 07:05:37 PM PDT 24
Finished Jul 16 07:05:49 PM PDT 24
Peak memory 210804 kb
Host smart-4ec9bd00-2ff6-49d9-aff1-023ddf3a97e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15705249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasi
ng.15705249
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1553518112
Short name T458
Test name
Test status
Simulation time 989535232 ps
CPU time 10.68 seconds
Started Jul 16 07:05:34 PM PDT 24
Finished Jul 16 07:05:46 PM PDT 24
Peak memory 210796 kb
Host smart-d47e98ef-e276-4873-b362-3119e3259a84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553518112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1553518112
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1803221346
Short name T378
Test name
Test status
Simulation time 182696919 ps
CPU time 5.86 seconds
Started Jul 16 07:05:52 PM PDT 24
Finished Jul 16 07:06:00 PM PDT 24
Peak memory 210680 kb
Host smart-cb16e0e7-e458-4b43-9ba2-56f6c0d51583
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803221346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1803221346
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.319002479
Short name T375
Test name
Test status
Simulation time 1652401591 ps
CPU time 14.26 seconds
Started Jul 16 07:05:51 PM PDT 24
Finished Jul 16 07:06:07 PM PDT 24
Peak memory 219044 kb
Host smart-6ee5ee7b-fb08-4a3b-9c73-64842d8374e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319002479 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.319002479
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.297221829
Short name T88
Test name
Test status
Simulation time 3884142892 ps
CPU time 15.26 seconds
Started Jul 16 07:05:36 PM PDT 24
Finished Jul 16 07:05:52 PM PDT 24
Peak memory 218880 kb
Host smart-4148e89b-2d29-443d-926c-e4dad39e7a0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297221829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.297221829
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3739425202
Short name T367
Test name
Test status
Simulation time 5957556894 ps
CPU time 12.67 seconds
Started Jul 16 07:05:41 PM PDT 24
Finished Jul 16 07:05:55 PM PDT 24
Peak memory 210568 kb
Host smart-c54334b1-4c10-4664-ac48-e124a0bb98cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739425202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3739425202
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1185138052
Short name T405
Test name
Test status
Simulation time 168234248 ps
CPU time 4.14 seconds
Started Jul 16 07:05:38 PM PDT 24
Finished Jul 16 07:05:44 PM PDT 24
Peak memory 210652 kb
Host smart-7e3c6df8-47e0-4f2b-a9a6-897ca1ec33e3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185138052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1185138052
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.209182033
Short name T451
Test name
Test status
Simulation time 16349374416 ps
CPU time 65.83 seconds
Started Jul 16 07:06:00 PM PDT 24
Finished Jul 16 07:07:08 PM PDT 24
Peak memory 210788 kb
Host smart-8c7f5ae6-bee1-4353-80af-71d3a3cc2f08
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209182033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.209182033
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1221405959
Short name T76
Test name
Test status
Simulation time 85436306 ps
CPU time 4.56 seconds
Started Jul 16 07:05:44 PM PDT 24
Finished Jul 16 07:05:50 PM PDT 24
Peak memory 218344 kb
Host smart-a780104d-ee4e-43a8-89b2-9eff235abdfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221405959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1221405959
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3048037140
Short name T412
Test name
Test status
Simulation time 1111147984 ps
CPU time 12.68 seconds
Started Jul 16 07:05:38 PM PDT 24
Finished Jul 16 07:05:53 PM PDT 24
Peak memory 219056 kb
Host smart-ef25e332-ead0-4470-8451-5d0384691764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048037140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3048037140
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1002159528
Short name T417
Test name
Test status
Simulation time 2042068476 ps
CPU time 47.73 seconds
Started Jul 16 07:05:51 PM PDT 24
Finished Jul 16 07:06:39 PM PDT 24
Peak memory 218972 kb
Host smart-d5297064-67ec-4c5f-9195-ce930e07fe39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002159528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1002159528
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2188062207
Short name T448
Test name
Test status
Simulation time 8494950931 ps
CPU time 16.02 seconds
Started Jul 16 07:05:43 PM PDT 24
Finished Jul 16 07:06:00 PM PDT 24
Peak memory 210744 kb
Host smart-6fbf8d2b-ade4-41b7-a9da-0e1a2d1eeca3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188062207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2188062207
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3624889239
Short name T390
Test name
Test status
Simulation time 2477898587 ps
CPU time 8.39 seconds
Started Jul 16 07:05:40 PM PDT 24
Finished Jul 16 07:05:50 PM PDT 24
Peak memory 210752 kb
Host smart-3ef087d7-d860-4d22-8f0f-c88c7e5ced52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624889239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3624889239
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3494395702
Short name T422
Test name
Test status
Simulation time 2749767740 ps
CPU time 10.23 seconds
Started Jul 16 07:05:52 PM PDT 24
Finished Jul 16 07:06:04 PM PDT 24
Peak memory 217584 kb
Host smart-15bee763-81b1-47cd-b290-36822e1aa3d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494395702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3494395702
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3335638780
Short name T388
Test name
Test status
Simulation time 10025252938 ps
CPU time 14.12 seconds
Started Jul 16 07:05:39 PM PDT 24
Finished Jul 16 07:05:54 PM PDT 24
Peak memory 219040 kb
Host smart-3a55d989-028a-4eba-a915-3d86392c3964
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335638780 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3335638780
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2680063433
Short name T85
Test name
Test status
Simulation time 1824903623 ps
CPU time 14.76 seconds
Started Jul 16 07:05:50 PM PDT 24
Finished Jul 16 07:06:05 PM PDT 24
Peak memory 210756 kb
Host smart-0f59fcef-c0fa-4da9-8d76-764e36a08785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680063433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2680063433
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1646886262
Short name T396
Test name
Test status
Simulation time 1559301007 ps
CPU time 6.68 seconds
Started Jul 16 07:05:40 PM PDT 24
Finished Jul 16 07:05:48 PM PDT 24
Peak memory 210648 kb
Host smart-38a1f641-c319-4696-8d73-bde6fe8046d9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646886262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1646886262
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1791677407
Short name T372
Test name
Test status
Simulation time 3750288006 ps
CPU time 13.47 seconds
Started Jul 16 07:05:38 PM PDT 24
Finished Jul 16 07:05:53 PM PDT 24
Peak memory 210716 kb
Host smart-16299a58-4a2e-4e3c-8d7d-f2c4c53c3664
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791677407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1791677407
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1829167012
Short name T94
Test name
Test status
Simulation time 12819195544 ps
CPU time 98.85 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:07:34 PM PDT 24
Peak memory 211808 kb
Host smart-2d54bdd6-58b0-4b16-b29f-e8a05eeb690c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829167012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1829167012
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.62413593
Short name T398
Test name
Test status
Simulation time 1391389512 ps
CPU time 13.22 seconds
Started Jul 16 07:05:59 PM PDT 24
Finished Jul 16 07:06:13 PM PDT 24
Peak memory 219128 kb
Host smart-932ad09c-07c8-4844-9945-fcaa4ab84b84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62413593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_same_csr_outstanding.62413593
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2237640629
Short name T442
Test name
Test status
Simulation time 4548226011 ps
CPU time 83.78 seconds
Started Jul 16 07:05:45 PM PDT 24
Finished Jul 16 07:07:10 PM PDT 24
Peak memory 212556 kb
Host smart-8568b84f-a203-463d-96e1-54c55d0b9430
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237640629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2237640629
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1772969129
Short name T395
Test name
Test status
Simulation time 1159901984 ps
CPU time 11.21 seconds
Started Jul 16 07:06:05 PM PDT 24
Finished Jul 16 07:06:17 PM PDT 24
Peak memory 219080 kb
Host smart-5d8dcb2c-3e57-4433-a99f-03861fa4230f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772969129 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1772969129
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1707913573
Short name T72
Test name
Test status
Simulation time 447051607 ps
CPU time 6.34 seconds
Started Jul 16 07:05:59 PM PDT 24
Finished Jul 16 07:06:06 PM PDT 24
Peak memory 210696 kb
Host smart-2410f206-dec5-4f52-8c6d-856c3d01de0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707913573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1707913573
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2682187904
Short name T407
Test name
Test status
Simulation time 5683182128 ps
CPU time 12.37 seconds
Started Jul 16 07:05:57 PM PDT 24
Finished Jul 16 07:06:11 PM PDT 24
Peak memory 218356 kb
Host smart-b66c9bac-8743-42e6-bc81-453c22c50431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682187904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2682187904
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2084138943
Short name T406
Test name
Test status
Simulation time 980469603 ps
CPU time 14.65 seconds
Started Jul 16 07:05:59 PM PDT 24
Finished Jul 16 07:06:14 PM PDT 24
Peak memory 218940 kb
Host smart-0b92b6bc-42af-4e2e-8548-6c486ab2de3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084138943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2084138943
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2476156016
Short name T443
Test name
Test status
Simulation time 4404523847 ps
CPU time 6.44 seconds
Started Jul 16 07:06:09 PM PDT 24
Finished Jul 16 07:06:16 PM PDT 24
Peak memory 219076 kb
Host smart-d923bb7d-f2fc-4de3-8b4c-7201fdf2c184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476156016 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2476156016
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3965102674
Short name T92
Test name
Test status
Simulation time 472180058 ps
CPU time 7.11 seconds
Started Jul 16 07:05:55 PM PDT 24
Finished Jul 16 07:06:03 PM PDT 24
Peak memory 217824 kb
Host smart-1d366d65-b7b9-4f9d-9661-7c7ed7cfe03b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965102674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3965102674
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.174888424
Short name T101
Test name
Test status
Simulation time 2120274367 ps
CPU time 22.6 seconds
Started Jul 16 07:05:59 PM PDT 24
Finished Jul 16 07:06:22 PM PDT 24
Peak memory 210704 kb
Host smart-c70b3459-0f87-4cf8-ad19-05f7650f6ce7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174888424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.174888424
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4155861263
Short name T95
Test name
Test status
Simulation time 392399935 ps
CPU time 6.72 seconds
Started Jul 16 07:05:49 PM PDT 24
Finished Jul 16 07:05:56 PM PDT 24
Peak memory 218132 kb
Host smart-be76364c-53cd-4357-beab-58d3e6469944
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155861263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4155861263
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.580301595
Short name T446
Test name
Test status
Simulation time 5584556823 ps
CPU time 14.19 seconds
Started Jul 16 07:05:49 PM PDT 24
Finished Jul 16 07:06:04 PM PDT 24
Peak memory 219016 kb
Host smart-dd80217c-59d9-45a4-948d-51387178442b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580301595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.580301595
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2655812486
Short name T113
Test name
Test status
Simulation time 7486871820 ps
CPU time 76.68 seconds
Started Jul 16 07:05:50 PM PDT 24
Finished Jul 16 07:07:07 PM PDT 24
Peak memory 218884 kb
Host smart-e8fa560a-3bb0-484f-b4f6-884a1c5bc871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655812486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2655812486
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1284228929
Short name T444
Test name
Test status
Simulation time 2019267933 ps
CPU time 9.78 seconds
Started Jul 16 07:06:08 PM PDT 24
Finished Jul 16 07:06:19 PM PDT 24
Peak memory 219016 kb
Host smart-3f3bb9c6-6039-46f8-8898-614e3a060b72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284228929 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1284228929
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1782546172
Short name T460
Test name
Test status
Simulation time 2324302742 ps
CPU time 15.91 seconds
Started Jul 16 07:05:49 PM PDT 24
Finished Jul 16 07:06:05 PM PDT 24
Peak memory 218648 kb
Host smart-06dce6e8-3129-483e-bd8d-45b5d398a8fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782546172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1782546172
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3158466012
Short name T78
Test name
Test status
Simulation time 7403990969 ps
CPU time 59.08 seconds
Started Jul 16 07:06:11 PM PDT 24
Finished Jul 16 07:07:11 PM PDT 24
Peak memory 210848 kb
Host smart-63d75608-766e-4f5a-a8bf-84753a9f37f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158466012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3158466012
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2445481551
Short name T96
Test name
Test status
Simulation time 2589818166 ps
CPU time 7.54 seconds
Started Jul 16 07:06:02 PM PDT 24
Finished Jul 16 07:06:11 PM PDT 24
Peak memory 210876 kb
Host smart-07e8a7fa-da9b-4bea-8671-33e69cb67992
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445481551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2445481551
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2213044587
Short name T393
Test name
Test status
Simulation time 4011051662 ps
CPU time 17.93 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:06:12 PM PDT 24
Peak memory 219092 kb
Host smart-b39a15f8-69d8-4c40-a03b-4ce45cf9724b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213044587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2213044587
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.763996237
Short name T403
Test name
Test status
Simulation time 1495966789 ps
CPU time 41.11 seconds
Started Jul 16 07:06:03 PM PDT 24
Finished Jul 16 07:06:45 PM PDT 24
Peak memory 218944 kb
Host smart-84b9bb4f-0c3c-42a0-b7d8-d5152106d7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763996237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.763996237
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2331651291
Short name T400
Test name
Test status
Simulation time 2804691066 ps
CPU time 9.02 seconds
Started Jul 16 07:06:04 PM PDT 24
Finished Jul 16 07:06:14 PM PDT 24
Peak memory 219028 kb
Host smart-a39d814e-bb44-4657-9b23-5fced1b1a992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331651291 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2331651291
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.189143627
Short name T385
Test name
Test status
Simulation time 361449335 ps
CPU time 4.17 seconds
Started Jul 16 07:05:52 PM PDT 24
Finished Jul 16 07:05:58 PM PDT 24
Peak memory 217220 kb
Host smart-088617e0-926d-4cc8-a223-f36a3ebc9a01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189143627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.189143627
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.867912328
Short name T90
Test name
Test status
Simulation time 17264811269 ps
CPU time 79.56 seconds
Started Jul 16 07:06:07 PM PDT 24
Finished Jul 16 07:07:28 PM PDT 24
Peak memory 210840 kb
Host smart-eefb1c08-e05b-41af-852c-88019446e577
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867912328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.867912328
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3382349879
Short name T70
Test name
Test status
Simulation time 1922508876 ps
CPU time 15.43 seconds
Started Jul 16 07:05:48 PM PDT 24
Finished Jul 16 07:06:04 PM PDT 24
Peak memory 219012 kb
Host smart-5d43a7b4-9806-4600-b9ff-ad1338ecefcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382349879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3382349879
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1547190407
Short name T418
Test name
Test status
Simulation time 239933981 ps
CPU time 8.16 seconds
Started Jul 16 07:05:44 PM PDT 24
Finished Jul 16 07:05:53 PM PDT 24
Peak memory 219000 kb
Host smart-42e6ddc7-3a7a-49bd-b20c-5ccdb3952d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547190407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1547190407
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2131858980
Short name T115
Test name
Test status
Simulation time 702515832 ps
CPU time 77.12 seconds
Started Jul 16 07:05:43 PM PDT 24
Finished Jul 16 07:07:00 PM PDT 24
Peak memory 213532 kb
Host smart-683522b7-e4a1-4116-95d6-3d8d6e609fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131858980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2131858980
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3036036065
Short name T426
Test name
Test status
Simulation time 101485361 ps
CPU time 5.07 seconds
Started Jul 16 07:05:46 PM PDT 24
Finished Jul 16 07:05:52 PM PDT 24
Peak memory 219052 kb
Host smart-23602716-7340-4b4e-8e8c-55a32a542d51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036036065 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3036036065
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4149622924
Short name T435
Test name
Test status
Simulation time 1400739370 ps
CPU time 9.02 seconds
Started Jul 16 07:05:59 PM PDT 24
Finished Jul 16 07:06:09 PM PDT 24
Peak memory 217780 kb
Host smart-54598152-0afd-47c0-bb09-3eda6548533a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149622924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4149622924
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1604061395
Short name T73
Test name
Test status
Simulation time 183513216465 ps
CPU time 84.94 seconds
Started Jul 16 07:05:58 PM PDT 24
Finished Jul 16 07:07:23 PM PDT 24
Peak memory 210824 kb
Host smart-4c5f8036-a36c-469b-ba64-c7afff5ba20d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604061395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1604061395
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4129001561
Short name T457
Test name
Test status
Simulation time 691145633 ps
CPU time 6.68 seconds
Started Jul 16 07:05:48 PM PDT 24
Finished Jul 16 07:05:55 PM PDT 24
Peak memory 218068 kb
Host smart-4aa83093-afab-4050-af04-c43ec4102ca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129001561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4129001561
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2905949065
Short name T392
Test name
Test status
Simulation time 2998290705 ps
CPU time 11.26 seconds
Started Jul 16 07:05:54 PM PDT 24
Finished Jul 16 07:06:07 PM PDT 24
Peak memory 218992 kb
Host smart-32fde7b3-8597-40bf-811d-925a01ca9690
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905949065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2905949065
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.274911979
Short name T114
Test name
Test status
Simulation time 815166622 ps
CPU time 68.75 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:07:03 PM PDT 24
Peak memory 212100 kb
Host smart-6ad2b7e8-322f-4150-b58a-abf04b2d3f98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274911979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.274911979
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1027396233
Short name T449
Test name
Test status
Simulation time 1403450985 ps
CPU time 12.28 seconds
Started Jul 16 07:05:57 PM PDT 24
Finished Jul 16 07:06:10 PM PDT 24
Peak memory 219068 kb
Host smart-81795352-0b79-415a-b2fc-63e242d06879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027396233 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1027396233
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2990175639
Short name T397
Test name
Test status
Simulation time 252403167 ps
CPU time 5.71 seconds
Started Jul 16 07:05:58 PM PDT 24
Finished Jul 16 07:06:04 PM PDT 24
Peak memory 218088 kb
Host smart-fb9cbfd2-d616-44cd-8d7b-271cb2bdd2f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990175639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2990175639
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1011574168
Short name T71
Test name
Test status
Simulation time 36038353836 ps
CPU time 78.7 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:07:33 PM PDT 24
Peak memory 210876 kb
Host smart-7d3e7d33-a966-4bac-866f-f1e8420da12a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011574168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1011574168
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3162811820
Short name T415
Test name
Test status
Simulation time 3748722636 ps
CPU time 9.94 seconds
Started Jul 16 07:06:04 PM PDT 24
Finished Jul 16 07:06:15 PM PDT 24
Peak memory 218600 kb
Host smart-7408c7e5-c82e-4089-955e-ee684c910a3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162811820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3162811820
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2604543426
Short name T425
Test name
Test status
Simulation time 4942765726 ps
CPU time 13.6 seconds
Started Jul 16 07:05:56 PM PDT 24
Finished Jul 16 07:06:11 PM PDT 24
Peak memory 219108 kb
Host smart-36ab3bd0-f086-4e47-8569-2601f0b062c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604543426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2604543426
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3181682290
Short name T61
Test name
Test status
Simulation time 1737076887 ps
CPU time 14.23 seconds
Started Jul 16 07:05:50 PM PDT 24
Finished Jul 16 07:06:05 PM PDT 24
Peak memory 218928 kb
Host smart-9e1ae4c4-aaf9-403b-b5b3-adf57252570f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181682290 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3181682290
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1933768096
Short name T381
Test name
Test status
Simulation time 5268444692 ps
CPU time 12.14 seconds
Started Jul 16 07:06:07 PM PDT 24
Finished Jul 16 07:06:20 PM PDT 24
Peak memory 218924 kb
Host smart-0d68e23c-e4ad-408a-a417-692c9125b820
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933768096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1933768096
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3248228611
Short name T384
Test name
Test status
Simulation time 19182869032 ps
CPU time 83.49 seconds
Started Jul 16 07:05:58 PM PDT 24
Finished Jul 16 07:07:23 PM PDT 24
Peak memory 211840 kb
Host smart-36a7f049-8849-4340-a5aa-a17311561191
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248228611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3248228611
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3198899578
Short name T431
Test name
Test status
Simulation time 3335831374 ps
CPU time 15.55 seconds
Started Jul 16 07:05:52 PM PDT 24
Finished Jul 16 07:06:09 PM PDT 24
Peak memory 210792 kb
Host smart-3db029f9-f026-430d-a626-74f406a127b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198899578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3198899578
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3578238210
Short name T447
Test name
Test status
Simulation time 2059117946 ps
CPU time 21.13 seconds
Started Jul 16 07:05:48 PM PDT 24
Finished Jul 16 07:06:10 PM PDT 24
Peak memory 219060 kb
Host smart-2748441c-1500-49b1-af4c-65b868b9d5ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578238210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3578238210
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3093550299
Short name T434
Test name
Test status
Simulation time 1396081378 ps
CPU time 41.97 seconds
Started Jul 16 07:06:01 PM PDT 24
Finished Jul 16 07:06:44 PM PDT 24
Peak memory 211828 kb
Host smart-05eeba64-7eda-47d5-9e39-160a878ecbc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093550299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3093550299
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1824053570
Short name T383
Test name
Test status
Simulation time 2002616380 ps
CPU time 15.84 seconds
Started Jul 16 07:05:56 PM PDT 24
Finished Jul 16 07:06:13 PM PDT 24
Peak memory 214904 kb
Host smart-f34420cb-a446-4a7a-8e62-ff93b993e6fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824053570 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1824053570
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2878312716
Short name T86
Test name
Test status
Simulation time 4266782709 ps
CPU time 15.78 seconds
Started Jul 16 07:05:56 PM PDT 24
Finished Jul 16 07:06:13 PM PDT 24
Peak memory 210856 kb
Host smart-02111a0f-f250-4c5d-852a-ee32aeada27e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878312716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2878312716
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.578093922
Short name T439
Test name
Test status
Simulation time 29437712064 ps
CPU time 62.29 seconds
Started Jul 16 07:06:00 PM PDT 24
Finished Jul 16 07:07:04 PM PDT 24
Peak memory 210788 kb
Host smart-577937de-d077-4633-9b8c-326f7713229a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578093922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.578093922
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3353646405
Short name T454
Test name
Test status
Simulation time 462930962 ps
CPU time 4.2 seconds
Started Jul 16 07:05:56 PM PDT 24
Finished Jul 16 07:06:01 PM PDT 24
Peak memory 218496 kb
Host smart-83af136c-d736-44b2-88bd-5ae81dc9fd0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353646405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3353646405
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4137374578
Short name T404
Test name
Test status
Simulation time 429584101 ps
CPU time 8.2 seconds
Started Jul 16 07:05:50 PM PDT 24
Finished Jul 16 07:05:58 PM PDT 24
Peak memory 218852 kb
Host smart-3d276989-858d-4072-a460-f4133a2b5849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137374578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4137374578
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3761665978
Short name T112
Test name
Test status
Simulation time 1578717052 ps
CPU time 73.14 seconds
Started Jul 16 07:05:50 PM PDT 24
Finished Jul 16 07:07:03 PM PDT 24
Peak memory 212112 kb
Host smart-3e328879-df30-4e0b-949d-2187992ec85e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761665978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3761665978
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2365120340
Short name T370
Test name
Test status
Simulation time 157597241 ps
CPU time 5.31 seconds
Started Jul 16 07:06:03 PM PDT 24
Finished Jul 16 07:06:09 PM PDT 24
Peak memory 218984 kb
Host smart-8aaa4aac-ecd9-4800-834b-5f4b03d3098c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365120340 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2365120340
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.79049078
Short name T394
Test name
Test status
Simulation time 85738348 ps
CPU time 4.21 seconds
Started Jul 16 07:05:52 PM PDT 24
Finished Jul 16 07:05:58 PM PDT 24
Peak memory 210716 kb
Host smart-02dcbeb9-ae46-4a86-b626-ce568881082b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79049078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.79049078
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1021394357
Short name T409
Test name
Test status
Simulation time 25526604882 ps
CPU time 49.9 seconds
Started Jul 16 07:06:05 PM PDT 24
Finished Jul 16 07:06:55 PM PDT 24
Peak memory 211840 kb
Host smart-9f09bb36-0434-47d9-8bc3-18abe59210cf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021394357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1021394357
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1538924053
Short name T74
Test name
Test status
Simulation time 3135979158 ps
CPU time 15.99 seconds
Started Jul 16 07:05:56 PM PDT 24
Finished Jul 16 07:06:13 PM PDT 24
Peak memory 219064 kb
Host smart-8b5c6d8e-1ea8-4f04-9015-b51889f9797b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538924053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1538924053
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1259263827
Short name T413
Test name
Test status
Simulation time 5107899899 ps
CPU time 16.13 seconds
Started Jul 16 07:06:02 PM PDT 24
Finished Jul 16 07:06:20 PM PDT 24
Peak memory 219072 kb
Host smart-5e7f172e-a7a1-4ced-bf97-7d87f2a305eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259263827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1259263827
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1558178690
Short name T57
Test name
Test status
Simulation time 273476923 ps
CPU time 38.46 seconds
Started Jul 16 07:05:52 PM PDT 24
Finished Jul 16 07:06:33 PM PDT 24
Peak memory 213124 kb
Host smart-6f929611-c331-4759-b9ab-38375cbd7e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558178690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1558178690
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2374588045
Short name T386
Test name
Test status
Simulation time 8259015900 ps
CPU time 11.19 seconds
Started Jul 16 07:06:06 PM PDT 24
Finished Jul 16 07:06:18 PM PDT 24
Peak memory 219116 kb
Host smart-cfa20d2e-14e5-4e0e-99cb-d3c762e9ab59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374588045 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2374588045
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3766780879
Short name T459
Test name
Test status
Simulation time 2678228552 ps
CPU time 11.93 seconds
Started Jul 16 07:06:07 PM PDT 24
Finished Jul 16 07:06:20 PM PDT 24
Peak memory 210756 kb
Host smart-ca3e18b1-86f8-4611-aa13-c97f0a200a9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766780879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3766780879
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3713435943
Short name T382
Test name
Test status
Simulation time 24019681666 ps
CPU time 48.39 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:06:43 PM PDT 24
Peak memory 210768 kb
Host smart-94256c73-aef5-4c60-bd7f-a9bddf0f93a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713435943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3713435943
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4030449021
Short name T429
Test name
Test status
Simulation time 1413786243 ps
CPU time 9.82 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:06:05 PM PDT 24
Peak memory 210784 kb
Host smart-e82762a9-6807-47fa-9f63-5ff76a08aa8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030449021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4030449021
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.67854625
Short name T408
Test name
Test status
Simulation time 1146741408 ps
CPU time 9.95 seconds
Started Jul 16 07:06:04 PM PDT 24
Finished Jul 16 07:06:15 PM PDT 24
Peak memory 218932 kb
Host smart-db420819-cc9f-48d0-9ee4-36a55dd06c78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67854625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.67854625
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2816206945
Short name T106
Test name
Test status
Simulation time 2381982511 ps
CPU time 39.19 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:06:34 PM PDT 24
Peak memory 219044 kb
Host smart-bb0c1d45-f924-48b9-9a58-c364d1b277dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816206945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2816206945
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.41853730
Short name T380
Test name
Test status
Simulation time 127080937 ps
CPU time 5.03 seconds
Started Jul 16 07:05:33 PM PDT 24
Finished Jul 16 07:05:39 PM PDT 24
Peak memory 210804 kb
Host smart-ac052d73-838d-4c2d-aa58-d4554eaa3ad6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41853730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasi
ng.41853730
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.749693647
Short name T411
Test name
Test status
Simulation time 1236935815 ps
CPU time 8.46 seconds
Started Jul 16 07:05:39 PM PDT 24
Finished Jul 16 07:05:49 PM PDT 24
Peak memory 217620 kb
Host smart-d8d6a4cf-8dda-4b5d-8a55-2bced4a4995d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749693647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.749693647
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1341358157
Short name T102
Test name
Test status
Simulation time 255884221 ps
CPU time 7.72 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:06:03 PM PDT 24
Peak memory 210808 kb
Host smart-2949aac1-98b0-436f-a408-8a90cc72cbf1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341358157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1341358157
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.200529531
Short name T387
Test name
Test status
Simulation time 1448762464 ps
CPU time 13 seconds
Started Jul 16 07:05:38 PM PDT 24
Finished Jul 16 07:05:53 PM PDT 24
Peak memory 219072 kb
Host smart-bc2fcc81-27ad-4cdc-ba32-b3e53cf3ae18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200529531 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.200529531
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.463208400
Short name T445
Test name
Test status
Simulation time 87447275 ps
CPU time 4.14 seconds
Started Jul 16 07:05:48 PM PDT 24
Finished Jul 16 07:05:54 PM PDT 24
Peak memory 217568 kb
Host smart-d20b4015-f063-4572-bcd4-034bd0aa89d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463208400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.463208400
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4202422513
Short name T462
Test name
Test status
Simulation time 1079748750 ps
CPU time 10.92 seconds
Started Jul 16 07:05:54 PM PDT 24
Finished Jul 16 07:06:06 PM PDT 24
Peak memory 210676 kb
Host smart-6f012731-db63-4009-beab-b9226d564b4d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202422513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4202422513
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1139407594
Short name T389
Test name
Test status
Simulation time 696824956 ps
CPU time 8.77 seconds
Started Jul 16 07:05:37 PM PDT 24
Finished Jul 16 07:05:47 PM PDT 24
Peak memory 210612 kb
Host smart-917f2d96-2f36-4b2f-a79d-a44debdd2c62
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139407594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1139407594
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.510880615
Short name T391
Test name
Test status
Simulation time 2126801215 ps
CPU time 26.21 seconds
Started Jul 16 07:05:43 PM PDT 24
Finished Jul 16 07:06:11 PM PDT 24
Peak memory 210780 kb
Host smart-c8f8f3f3-6f24-4c1e-a2f7-1456a60668bc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510880615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.510880615
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4070843387
Short name T427
Test name
Test status
Simulation time 809877259 ps
CPU time 9.36 seconds
Started Jul 16 07:05:49 PM PDT 24
Finished Jul 16 07:05:59 PM PDT 24
Peak memory 211000 kb
Host smart-21814436-73a2-4749-ba4b-a2819e0c2d17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070843387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4070843387
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3593004404
Short name T369
Test name
Test status
Simulation time 1335443034 ps
CPU time 10.34 seconds
Started Jul 16 07:05:36 PM PDT 24
Finished Jul 16 07:05:48 PM PDT 24
Peak memory 219052 kb
Host smart-5e1229a0-0171-4633-8165-827e644dd548
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593004404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3593004404
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1901892055
Short name T109
Test name
Test status
Simulation time 3630248671 ps
CPU time 44.67 seconds
Started Jul 16 07:06:06 PM PDT 24
Finished Jul 16 07:06:52 PM PDT 24
Peak memory 219060 kb
Host smart-daa1f595-551e-4090-a9e4-9746d6f3ded9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901892055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1901892055
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.793353572
Short name T379
Test name
Test status
Simulation time 168162161 ps
CPU time 5.36 seconds
Started Jul 16 07:05:43 PM PDT 24
Finished Jul 16 07:05:50 PM PDT 24
Peak memory 210696 kb
Host smart-33f85a70-ff64-434f-9532-477c2100e0f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793353572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.793353572
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.645909032
Short name T419
Test name
Test status
Simulation time 532065545 ps
CPU time 8.1 seconds
Started Jul 16 07:06:07 PM PDT 24
Finished Jul 16 07:06:17 PM PDT 24
Peak memory 217400 kb
Host smart-e1e0c24e-6ced-4b85-94ed-e1d7f9ae3274
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645909032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.645909032
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3718557957
Short name T84
Test name
Test status
Simulation time 1620440877 ps
CPU time 16.52 seconds
Started Jul 16 07:05:37 PM PDT 24
Finished Jul 16 07:05:55 PM PDT 24
Peak memory 218568 kb
Host smart-32d3faa2-5218-43cd-8f55-55783f09af58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718557957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3718557957
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4286079456
Short name T376
Test name
Test status
Simulation time 4443608489 ps
CPU time 9.74 seconds
Started Jul 16 07:05:35 PM PDT 24
Finished Jul 16 07:05:46 PM PDT 24
Peak memory 219112 kb
Host smart-e52ef104-67e7-4492-a318-516093e86d99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286079456 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4286079456
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1909455130
Short name T436
Test name
Test status
Simulation time 1993585053 ps
CPU time 15.69 seconds
Started Jul 16 07:05:38 PM PDT 24
Finished Jul 16 07:05:55 PM PDT 24
Peak memory 218828 kb
Host smart-4b1e498f-9eb9-4449-aa62-8d91501c59de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909455130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1909455130
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3301209755
Short name T371
Test name
Test status
Simulation time 1574201126 ps
CPU time 6.81 seconds
Started Jul 16 07:05:33 PM PDT 24
Finished Jul 16 07:05:41 PM PDT 24
Peak memory 210648 kb
Host smart-eab0f23b-570c-4b2c-83d7-fc73a287b942
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301209755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3301209755
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.134334479
Short name T402
Test name
Test status
Simulation time 2931264287 ps
CPU time 13.31 seconds
Started Jul 16 07:05:33 PM PDT 24
Finished Jul 16 07:05:48 PM PDT 24
Peak memory 210676 kb
Host smart-181f107d-23cb-4f5a-8386-2532a3a08b4e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134334479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
134334479
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2719894719
Short name T399
Test name
Test status
Simulation time 851929334 ps
CPU time 9.28 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:06:04 PM PDT 24
Peak memory 210844 kb
Host smart-25a5665d-e67d-44cc-b910-8a9bcf032fbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719894719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2719894719
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.513713534
Short name T401
Test name
Test status
Simulation time 5869541748 ps
CPU time 17.48 seconds
Started Jul 16 07:05:46 PM PDT 24
Finished Jul 16 07:06:05 PM PDT 24
Peak memory 219252 kb
Host smart-ca0297bf-63e2-4d72-9067-6d053f66864b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513713534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.513713534
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.991718348
Short name T116
Test name
Test status
Simulation time 211639398 ps
CPU time 68.32 seconds
Started Jul 16 07:05:52 PM PDT 24
Finished Jul 16 07:07:02 PM PDT 24
Peak memory 218992 kb
Host smart-8ecc8761-4691-4cd5-b927-989f31472eb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991718348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.991718348
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2042024579
Short name T100
Test name
Test status
Simulation time 1754661016 ps
CPU time 9.22 seconds
Started Jul 16 07:05:41 PM PDT 24
Finished Jul 16 07:05:52 PM PDT 24
Peak memory 217508 kb
Host smart-9c36d315-c1fe-408a-8864-517a2138e583
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042024579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2042024579
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4045949517
Short name T433
Test name
Test status
Simulation time 6940470551 ps
CPU time 14.5 seconds
Started Jul 16 07:05:45 PM PDT 24
Finished Jul 16 07:06:01 PM PDT 24
Peak memory 210820 kb
Host smart-06696b4a-f775-4afa-86e5-f4a64f3001e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045949517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.4045949517
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2696401870
Short name T438
Test name
Test status
Simulation time 259921865 ps
CPU time 8.4 seconds
Started Jul 16 07:05:58 PM PDT 24
Finished Jul 16 07:06:07 PM PDT 24
Peak memory 210756 kb
Host smart-c5ad5ff8-2e85-4b7a-9c6a-17e076702a81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696401870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2696401870
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1305238246
Short name T414
Test name
Test status
Simulation time 6008224498 ps
CPU time 12.17 seconds
Started Jul 16 07:05:54 PM PDT 24
Finished Jul 16 07:06:08 PM PDT 24
Peak memory 219120 kb
Host smart-53e47010-b918-46cd-ad18-96b37bec686b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305238246 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1305238246
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1350618444
Short name T420
Test name
Test status
Simulation time 2145925060 ps
CPU time 7.23 seconds
Started Jul 16 07:06:01 PM PDT 24
Finished Jul 16 07:06:09 PM PDT 24
Peak memory 217840 kb
Host smart-a6e693fc-d83d-48a1-8858-50ebf4b909f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350618444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1350618444
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1261194851
Short name T366
Test name
Test status
Simulation time 89017981 ps
CPU time 4.17 seconds
Started Jul 16 07:05:43 PM PDT 24
Finished Jul 16 07:05:49 PM PDT 24
Peak memory 210576 kb
Host smart-f4007d12-dcfc-42e0-9abd-b85db9e076ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261194851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1261194851
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3489613244
Short name T416
Test name
Test status
Simulation time 2119013606 ps
CPU time 16.38 seconds
Started Jul 16 07:05:50 PM PDT 24
Finished Jul 16 07:06:07 PM PDT 24
Peak memory 210608 kb
Host smart-15287493-0832-49eb-b96e-356f0d023108
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489613244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3489613244
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2042930379
Short name T440
Test name
Test status
Simulation time 7167028460 ps
CPU time 72.61 seconds
Started Jul 16 07:05:52 PM PDT 24
Finished Jul 16 07:07:07 PM PDT 24
Peak memory 210856 kb
Host smart-6d33e13c-a993-4bd4-9d56-2aa09792b606
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042930379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2042930379
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.180327320
Short name T450
Test name
Test status
Simulation time 333575622 ps
CPU time 4.41 seconds
Started Jul 16 07:05:39 PM PDT 24
Finished Jul 16 07:05:45 PM PDT 24
Peak memory 218444 kb
Host smart-57459ad1-a1c3-48fc-8100-7de78a41e1e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180327320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.180327320
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1502221298
Short name T374
Test name
Test status
Simulation time 1711118724 ps
CPU time 15.86 seconds
Started Jul 16 07:05:36 PM PDT 24
Finished Jul 16 07:05:52 PM PDT 24
Peak memory 218856 kb
Host smart-b64d8395-acab-408d-88a7-88a397e1251c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502221298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1502221298
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.953623608
Short name T368
Test name
Test status
Simulation time 982959409 ps
CPU time 7.91 seconds
Started Jul 16 07:05:35 PM PDT 24
Finished Jul 16 07:05:43 PM PDT 24
Peak memory 218996 kb
Host smart-fa985493-ccab-49cc-b14f-434caced789d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953623608 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.953623608
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3360393532
Short name T455
Test name
Test status
Simulation time 6091086504 ps
CPU time 14.15 seconds
Started Jul 16 07:05:51 PM PDT 24
Finished Jul 16 07:06:06 PM PDT 24
Peak memory 218904 kb
Host smart-256228f8-a516-41ab-b0d0-f609b770e6ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360393532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3360393532
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1384004970
Short name T89
Test name
Test status
Simulation time 9389073739 ps
CPU time 80.13 seconds
Started Jul 16 07:05:42 PM PDT 24
Finished Jul 16 07:07:03 PM PDT 24
Peak memory 210812 kb
Host smart-1e508edc-284f-4939-b287-d86b5b14702c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384004970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1384004970
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1864137538
Short name T98
Test name
Test status
Simulation time 1598540513 ps
CPU time 8.66 seconds
Started Jul 16 07:05:46 PM PDT 24
Finished Jul 16 07:05:55 PM PDT 24
Peak memory 210828 kb
Host smart-4f27746a-f34e-4b29-94b8-599a022ff2fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864137538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1864137538
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.837719040
Short name T373
Test name
Test status
Simulation time 1362727469 ps
CPU time 9.44 seconds
Started Jul 16 07:05:40 PM PDT 24
Finished Jul 16 07:05:51 PM PDT 24
Peak memory 219024 kb
Host smart-af43b0f6-ba68-4e4f-b9c7-a01cc2993126
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837719040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.837719040
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.18012912
Short name T58
Test name
Test status
Simulation time 3823519816 ps
CPU time 41.43 seconds
Started Jul 16 07:05:46 PM PDT 24
Finished Jul 16 07:06:28 PM PDT 24
Peak memory 219016 kb
Host smart-7fe46be2-7300-472a-b1bb-5fe0bd78eb5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18012912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg
_err.18012912
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.290792926
Short name T441
Test name
Test status
Simulation time 3594920218 ps
CPU time 12.11 seconds
Started Jul 16 07:05:43 PM PDT 24
Finished Jul 16 07:05:56 PM PDT 24
Peak memory 219088 kb
Host smart-7b132e04-08fc-4ad7-aba3-f539328b90ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290792926 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.290792926
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4274635812
Short name T93
Test name
Test status
Simulation time 553273422 ps
CPU time 4.12 seconds
Started Jul 16 07:05:47 PM PDT 24
Finished Jul 16 07:05:52 PM PDT 24
Peak memory 210760 kb
Host smart-992da228-26e3-400c-a902-027755d294bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274635812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4274635812
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.716747663
Short name T456
Test name
Test status
Simulation time 34480220043 ps
CPU time 54.77 seconds
Started Jul 16 07:05:36 PM PDT 24
Finished Jul 16 07:06:33 PM PDT 24
Peak memory 211864 kb
Host smart-2d69f9c7-1727-4bf6-88d8-dc8a18e0ffa9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716747663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.716747663
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2320033495
Short name T99
Test name
Test status
Simulation time 96942188 ps
CPU time 6.05 seconds
Started Jul 16 07:05:37 PM PDT 24
Finished Jul 16 07:05:44 PM PDT 24
Peak memory 210676 kb
Host smart-8374c47f-a5cf-4ac2-a657-6a8ea101d044
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320033495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2320033495
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2791573562
Short name T424
Test name
Test status
Simulation time 22628957991 ps
CPU time 19.08 seconds
Started Jul 16 07:05:44 PM PDT 24
Finished Jul 16 07:06:05 PM PDT 24
Peak memory 219076 kb
Host smart-362c4699-2aad-4106-80be-5ece9abb1cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791573562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2791573562
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3870237622
Short name T59
Test name
Test status
Simulation time 4052814376 ps
CPU time 78.08 seconds
Started Jul 16 07:05:37 PM PDT 24
Finished Jul 16 07:06:57 PM PDT 24
Peak memory 219036 kb
Host smart-027a3c79-ae43-472f-b2cd-1c61badcb565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870237622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3870237622
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2434523792
Short name T410
Test name
Test status
Simulation time 5139657464 ps
CPU time 11.52 seconds
Started Jul 16 07:05:40 PM PDT 24
Finished Jul 16 07:05:53 PM PDT 24
Peak memory 218992 kb
Host smart-94fd904b-939e-4478-808c-c6da644b011b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434523792 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2434523792
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2197231063
Short name T87
Test name
Test status
Simulation time 85554062 ps
CPU time 4.22 seconds
Started Jul 16 07:05:51 PM PDT 24
Finished Jul 16 07:05:56 PM PDT 24
Peak memory 210756 kb
Host smart-138f7422-ece1-4cb3-b39a-88a9ed5789e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197231063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2197231063
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.676873243
Short name T91
Test name
Test status
Simulation time 9005034105 ps
CPU time 78.08 seconds
Started Jul 16 07:05:54 PM PDT 24
Finished Jul 16 07:07:14 PM PDT 24
Peak memory 210844 kb
Host smart-3bdff10c-0389-423d-aaf9-6a7d5c94c9cb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676873243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.676873243
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.928430365
Short name T423
Test name
Test status
Simulation time 554940637 ps
CPU time 4.52 seconds
Started Jul 16 07:05:39 PM PDT 24
Finished Jul 16 07:05:45 PM PDT 24
Peak memory 218244 kb
Host smart-46b87656-0dfa-4f97-8f22-74c87413c88f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928430365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.928430365
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2568652159
Short name T437
Test name
Test status
Simulation time 88989764 ps
CPU time 6.63 seconds
Started Jul 16 07:05:55 PM PDT 24
Finished Jul 16 07:06:03 PM PDT 24
Peak memory 218880 kb
Host smart-e80c8ac3-8868-4638-91fa-410904d15fff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568652159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2568652159
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.783477281
Short name T107
Test name
Test status
Simulation time 14427423064 ps
CPU time 74.8 seconds
Started Jul 16 07:05:45 PM PDT 24
Finished Jul 16 07:07:01 PM PDT 24
Peak memory 219244 kb
Host smart-b0ae1c2e-ecce-4b59-a2ba-5df013807d87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783477281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.783477281
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4207087945
Short name T453
Test name
Test status
Simulation time 7758076312 ps
CPU time 14.24 seconds
Started Jul 16 07:05:56 PM PDT 24
Finished Jul 16 07:06:11 PM PDT 24
Peak memory 219108 kb
Host smart-b61348ab-d699-4c24-a5a9-90e836722ea6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207087945 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4207087945
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1543293156
Short name T463
Test name
Test status
Simulation time 922899352 ps
CPU time 10.15 seconds
Started Jul 16 07:05:59 PM PDT 24
Finished Jul 16 07:06:10 PM PDT 24
Peak memory 218780 kb
Host smart-11a04d0e-055a-427c-b3cd-4a4824defc9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543293156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1543293156
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2697405383
Short name T421
Test name
Test status
Simulation time 2077996703 ps
CPU time 32.15 seconds
Started Jul 16 07:05:39 PM PDT 24
Finished Jul 16 07:06:13 PM PDT 24
Peak memory 210720 kb
Host smart-c7dd633b-5a84-43f3-b872-5c90303f217d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697405383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2697405383
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3522005104
Short name T97
Test name
Test status
Simulation time 6339741344 ps
CPU time 14.28 seconds
Started Jul 16 07:05:52 PM PDT 24
Finished Jul 16 07:06:07 PM PDT 24
Peak memory 218916 kb
Host smart-145e45f1-ff50-48f5-b6fa-9b1f75f086e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522005104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3522005104
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.490858406
Short name T432
Test name
Test status
Simulation time 1328163695 ps
CPU time 16.51 seconds
Started Jul 16 07:05:43 PM PDT 24
Finished Jul 16 07:06:01 PM PDT 24
Peak memory 218832 kb
Host smart-4ae1369a-f398-4011-a6c7-f9a1b4a64aa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490858406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.490858406
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.331095516
Short name T428
Test name
Test status
Simulation time 877442185 ps
CPU time 10.33 seconds
Started Jul 16 07:05:52 PM PDT 24
Finished Jul 16 07:06:05 PM PDT 24
Peak memory 218952 kb
Host smart-22a0802a-44fa-424b-94a2-b24014df0099
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331095516 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.331095516
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.271493784
Short name T377
Test name
Test status
Simulation time 1691639467 ps
CPU time 10.69 seconds
Started Jul 16 07:06:09 PM PDT 24
Finished Jul 16 07:06:21 PM PDT 24
Peak memory 218992 kb
Host smart-88691ebe-9832-4531-b557-2b482b49189f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271493784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.271493784
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2798606321
Short name T77
Test name
Test status
Simulation time 380459979 ps
CPU time 19.34 seconds
Started Jul 16 07:05:46 PM PDT 24
Finished Jul 16 07:06:07 PM PDT 24
Peak memory 210768 kb
Host smart-e9523ebe-9ce1-4b6c-af5c-0b5cd2ea7c7e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798606321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2798606321
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1450373344
Short name T461
Test name
Test status
Simulation time 8840959700 ps
CPU time 18.33 seconds
Started Jul 16 07:06:07 PM PDT 24
Finished Jul 16 07:06:27 PM PDT 24
Peak memory 211156 kb
Host smart-58b6b03c-d43b-4f71-80bd-821a48d49b47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450373344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1450373344
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3653507638
Short name T452
Test name
Test status
Simulation time 1891284293 ps
CPU time 19.01 seconds
Started Jul 16 07:05:44 PM PDT 24
Finished Jul 16 07:06:04 PM PDT 24
Peak memory 219000 kb
Host smart-e827091e-6113-41b7-b2d7-daed7f35c26a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653507638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3653507638
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1064848886
Short name T117
Test name
Test status
Simulation time 4603345958 ps
CPU time 42.05 seconds
Started Jul 16 07:05:50 PM PDT 24
Finished Jul 16 07:06:32 PM PDT 24
Peak memory 218924 kb
Host smart-d8d3fea5-1079-48a8-bb70-9dd7bd6ab5ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064848886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1064848886
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3050255545
Short name T230
Test name
Test status
Simulation time 8255524467 ps
CPU time 9.26 seconds
Started Jul 16 07:06:00 PM PDT 24
Finished Jul 16 07:06:10 PM PDT 24
Peak memory 211416 kb
Host smart-d2616149-aa35-4dcf-8dfd-8bc18122a09a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050255545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3050255545
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1294440402
Short name T261
Test name
Test status
Simulation time 37929633406 ps
CPU time 352.87 seconds
Started Jul 16 07:06:06 PM PDT 24
Finished Jul 16 07:12:00 PM PDT 24
Peak memory 233052 kb
Host smart-a6483cc1-df89-4c5a-a8f8-757f20cce7d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294440402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1294440402
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2009551268
Short name T330
Test name
Test status
Simulation time 10466672846 ps
CPU time 16.07 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:06:11 PM PDT 24
Peak memory 211436 kb
Host smart-b1966f47-bfa0-49c0-a9c3-fe0b9c9db9ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009551268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2009551268
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4086508911
Short name T341
Test name
Test status
Simulation time 296508735 ps
CPU time 10.34 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:26 PM PDT 24
Peak memory 213576 kb
Host smart-ceda85cc-4a5b-4282-81a4-d6afe9f8609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086508911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4086508911
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4139982135
Short name T60
Test name
Test status
Simulation time 439206575 ps
CPU time 21.81 seconds
Started Jul 16 07:05:53 PM PDT 24
Finished Jul 16 07:06:17 PM PDT 24
Peak memory 215420 kb
Host smart-1f48d0cf-889e-4082-a7e3-e49e42dbd5a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139982135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4139982135
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2352729081
Short name T287
Test name
Test status
Simulation time 3642720013 ps
CPU time 10.35 seconds
Started Jul 16 07:06:00 PM PDT 24
Finished Jul 16 07:06:11 PM PDT 24
Peak memory 211396 kb
Host smart-4ca49276-c277-4f3e-9261-f90a5b2ac7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352729081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2352729081
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4002917489
Short name T190
Test name
Test status
Simulation time 27103460812 ps
CPU time 122.05 seconds
Started Jul 16 07:06:01 PM PDT 24
Finished Jul 16 07:08:04 PM PDT 24
Peak memory 216544 kb
Host smart-9d852f02-5daa-4ea9-b4aa-52eb6bd23cf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002917489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4002917489
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2264660548
Short name T276
Test name
Test status
Simulation time 347542450 ps
CPU time 9.82 seconds
Started Jul 16 07:06:16 PM PDT 24
Finished Jul 16 07:06:33 PM PDT 24
Peak memory 211932 kb
Host smart-37c61668-ce69-4a4d-9e09-db10b21f03f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264660548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2264660548
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1394181015
Short name T310
Test name
Test status
Simulation time 98854304 ps
CPU time 5.57 seconds
Started Jul 16 07:06:00 PM PDT 24
Finished Jul 16 07:06:07 PM PDT 24
Peak memory 211344 kb
Host smart-bef10446-99f6-4c8f-b1ad-6448fcc1422a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394181015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1394181015
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1174512700
Short name T22
Test name
Test status
Simulation time 1906659289 ps
CPU time 110.4 seconds
Started Jul 16 07:06:08 PM PDT 24
Finished Jul 16 07:08:00 PM PDT 24
Peak memory 238924 kb
Host smart-db92d1f4-40e9-49f5-ad7d-befe53b832c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174512700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1174512700
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.793555063
Short name T315
Test name
Test status
Simulation time 4048081123 ps
CPU time 33.96 seconds
Started Jul 16 07:06:01 PM PDT 24
Finished Jul 16 07:06:36 PM PDT 24
Peak memory 213208 kb
Host smart-f40ebec9-a4ec-473e-b88b-e446d66d6203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793555063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.793555063
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.636883102
Short name T142
Test name
Test status
Simulation time 5152494926 ps
CPU time 29.05 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:49 PM PDT 24
Peak memory 214896 kb
Host smart-2e43f202-ffbe-40bd-8d7b-118ade7accbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636883102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.636883102
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1884773360
Short name T8
Test name
Test status
Simulation time 85410301 ps
CPU time 4.28 seconds
Started Jul 16 07:06:25 PM PDT 24
Finished Jul 16 07:06:30 PM PDT 24
Peak memory 211520 kb
Host smart-b4f0e087-cae0-45c1-b8ab-dc1e305f133c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884773360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1884773360
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4247938422
Short name T42
Test name
Test status
Simulation time 84643036746 ps
CPU time 167.3 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:09:05 PM PDT 24
Peak memory 228464 kb
Host smart-a33ce0e7-ae8a-4c54-b596-3c823f1fe321
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247938422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4247938422
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2829152949
Short name T166
Test name
Test status
Simulation time 1959874199 ps
CPU time 21.59 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:37 PM PDT 24
Peak memory 211852 kb
Host smart-56956aa7-5d35-479b-9332-c54561b1af53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829152949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2829152949
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3465372628
Short name T120
Test name
Test status
Simulation time 191659176 ps
CPU time 5.65 seconds
Started Jul 16 07:06:24 PM PDT 24
Finished Jul 16 07:06:30 PM PDT 24
Peak memory 211380 kb
Host smart-0b2b2b9a-ce28-472d-8d76-cad2f0f442c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465372628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3465372628
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2462629597
Short name T318
Test name
Test status
Simulation time 15643313905 ps
CPU time 28.71 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:06:46 PM PDT 24
Peak memory 214444 kb
Host smart-d7fa280e-c21d-4c33-b4d9-65bf64f0c9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462629597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2462629597
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2037736287
Short name T79
Test name
Test status
Simulation time 7035901029 ps
CPU time 55.31 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:07:16 PM PDT 24
Peak memory 219360 kb
Host smart-2790798d-d41e-4d70-b4e0-b8f5415423c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037736287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2037736287
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.307200466
Short name T300
Test name
Test status
Simulation time 1150465437 ps
CPU time 10.8 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:31 PM PDT 24
Peak memory 211308 kb
Host smart-ac2ad1a0-f815-48a8-abef-edba863e465c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307200466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.307200466
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.574755150
Short name T257
Test name
Test status
Simulation time 103841123456 ps
CPU time 299.15 seconds
Started Jul 16 07:06:18 PM PDT 24
Finished Jul 16 07:11:20 PM PDT 24
Peak memory 238824 kb
Host smart-d8164440-4b6a-48d9-83bf-c308dfcba532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574755150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.574755150
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2480734528
Short name T151
Test name
Test status
Simulation time 398237483 ps
CPU time 5.73 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:26 PM PDT 24
Peak memory 211276 kb
Host smart-563a23bb-ecf0-4a0a-b8f3-e4fd0a61bd68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480734528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2480734528
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3483062259
Short name T260
Test name
Test status
Simulation time 13374706012 ps
CPU time 30.65 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:06:48 PM PDT 24
Peak memory 214304 kb
Host smart-182c76f2-216f-4e26-8cfe-284af2f6a786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483062259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3483062259
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2512852150
Short name T129
Test name
Test status
Simulation time 5012998007 ps
CPU time 33.77 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:06:49 PM PDT 24
Peak memory 216164 kb
Host smart-f5a11f73-1026-4d80-aebc-6bfe204d01ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512852150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2512852150
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1505787634
Short name T363
Test name
Test status
Simulation time 3882188507 ps
CPU time 13.47 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:33 PM PDT 24
Peak memory 211412 kb
Host smart-fa7cdb36-78f0-4738-ab8f-1f240c6ce6d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505787634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1505787634
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3007891931
Short name T128
Test name
Test status
Simulation time 84896525967 ps
CPU time 317.71 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:11:38 PM PDT 24
Peak memory 239280 kb
Host smart-53bdeb6d-9595-46fd-add0-3a77f48738d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007891931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3007891931
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3985041644
Short name T182
Test name
Test status
Simulation time 169029893 ps
CPU time 9.46 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:30 PM PDT 24
Peak memory 212204 kb
Host smart-37f8765b-0a45-451d-ac25-22c311b6c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985041644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3985041644
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3595133504
Short name T187
Test name
Test status
Simulation time 4400308152 ps
CPU time 18.08 seconds
Started Jul 16 07:06:18 PM PDT 24
Finished Jul 16 07:06:39 PM PDT 24
Peak memory 211476 kb
Host smart-ba93f149-f3a2-4fd4-9fae-5e1f41b0e5c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595133504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3595133504
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2073053287
Short name T329
Test name
Test status
Simulation time 3069881755 ps
CPU time 28.03 seconds
Started Jul 16 07:06:16 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 213740 kb
Host smart-a6547b06-304e-4859-ac41-9703a753138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073053287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2073053287
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2880792316
Short name T247
Test name
Test status
Simulation time 2279322438 ps
CPU time 12.14 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:33 PM PDT 24
Peak memory 211428 kb
Host smart-2626d2a0-4662-4657-827a-8fccd1f0f0d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880792316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2880792316
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1137077101
Short name T240
Test name
Test status
Simulation time 858576664 ps
CPU time 9.88 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:06:27 PM PDT 24
Peak memory 211356 kb
Host smart-14458c71-cbfb-4a70-b9ed-54fa1dd506e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137077101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1137077101
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3701024487
Short name T180
Test name
Test status
Simulation time 165616362686 ps
CPU time 404.61 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:13:01 PM PDT 24
Peak memory 238852 kb
Host smart-eebb7cc0-7a76-4f75-8342-3bfcdb05a3c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701024487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3701024487
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1668628936
Short name T198
Test name
Test status
Simulation time 3649250293 ps
CPU time 22.82 seconds
Started Jul 16 07:06:19 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 211996 kb
Host smart-d6bdc386-d3ef-48d1-809b-87909a472cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668628936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1668628936
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4190015830
Short name T331
Test name
Test status
Simulation time 3331003879 ps
CPU time 15.19 seconds
Started Jul 16 07:06:18 PM PDT 24
Finished Jul 16 07:06:36 PM PDT 24
Peak memory 211448 kb
Host smart-12b7e010-0386-4ffd-9261-16901e1fe2bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190015830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4190015830
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1413076869
Short name T197
Test name
Test status
Simulation time 5927689957 ps
CPU time 35.98 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:52 PM PDT 24
Peak memory 213852 kb
Host smart-3448b2bf-76b5-4ad1-a90b-2b7be30b75b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413076869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1413076869
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1778098467
Short name T83
Test name
Test status
Simulation time 2480072862 ps
CPU time 35.42 seconds
Started Jul 16 07:06:16 PM PDT 24
Finished Jul 16 07:06:54 PM PDT 24
Peak memory 215876 kb
Host smart-19f7eea1-8bd4-433d-87cb-24d4d0cae34a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778098467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1778098467
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2221738127
Short name T263
Test name
Test status
Simulation time 338538760 ps
CPU time 6.49 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:22 PM PDT 24
Peak memory 211352 kb
Host smart-fc4972c5-c9aa-4b64-a4f8-c248ad4d951b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221738127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2221738127
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.199718105
Short name T302
Test name
Test status
Simulation time 12422304312 ps
CPU time 120.65 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:08:20 PM PDT 24
Peak memory 212664 kb
Host smart-9434e5e7-fb8b-4914-a784-7c77556ed820
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199718105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.199718105
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3096646983
Short name T299
Test name
Test status
Simulation time 4013966917 ps
CPU time 30.86 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:06:46 PM PDT 24
Peak memory 212316 kb
Host smart-870e631e-7af5-4a80-a693-0afea98a5ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096646983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3096646983
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3438093619
Short name T210
Test name
Test status
Simulation time 608624483 ps
CPU time 5.4 seconds
Started Jul 16 07:06:20 PM PDT 24
Finished Jul 16 07:06:27 PM PDT 24
Peak memory 211324 kb
Host smart-b2370657-1092-4117-9767-c3b737829f40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438093619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3438093619
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4096914340
Short name T140
Test name
Test status
Simulation time 946545509 ps
CPU time 15.76 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:06:34 PM PDT 24
Peak memory 212076 kb
Host smart-866d02e7-962d-432f-a3ac-326dd90f4367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096914340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4096914340
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.848091607
Short name T232
Test name
Test status
Simulation time 8908437493 ps
CPU time 25.51 seconds
Started Jul 16 07:06:19 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 214924 kb
Host smart-36efac76-ecf2-457c-810f-1b54e214a039
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848091607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.848091607
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3288433488
Short name T295
Test name
Test status
Simulation time 629831464 ps
CPU time 8.33 seconds
Started Jul 16 07:06:20 PM PDT 24
Finished Jul 16 07:06:30 PM PDT 24
Peak memory 211292 kb
Host smart-8bbb0b2b-379b-41c9-b1e0-fb007feb365a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288433488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3288433488
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1993899104
Short name T211
Test name
Test status
Simulation time 13622379494 ps
CPU time 149.09 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:08:47 PM PDT 24
Peak memory 238852 kb
Host smart-03cd249b-d4b4-4ef9-837c-68aa0b38fbe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993899104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1993899104
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3694604280
Short name T262
Test name
Test status
Simulation time 15303974863 ps
CPU time 30.78 seconds
Started Jul 16 07:06:19 PM PDT 24
Finished Jul 16 07:06:52 PM PDT 24
Peak memory 212508 kb
Host smart-1baa6c79-13ad-457f-afe7-6a6cfb5e643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694604280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3694604280
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3636191818
Short name T250
Test name
Test status
Simulation time 1001105963 ps
CPU time 5.49 seconds
Started Jul 16 07:06:19 PM PDT 24
Finished Jul 16 07:06:27 PM PDT 24
Peak memory 211380 kb
Host smart-a882c7c9-6e89-4628-80b6-12a4d7188e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636191818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3636191818
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4086218182
Short name T284
Test name
Test status
Simulation time 3868910688 ps
CPU time 39.96 seconds
Started Jul 16 07:06:16 PM PDT 24
Finished Jul 16 07:06:58 PM PDT 24
Peak memory 214056 kb
Host smart-4db0b6cc-ec9a-4317-a517-bcd9979718fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086218182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4086218182
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3466003682
Short name T213
Test name
Test status
Simulation time 3350797352 ps
CPU time 18.12 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:39 PM PDT 24
Peak memory 211216 kb
Host smart-f32bf738-e0bf-45bf-ac21-6d2b7bc50c17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466003682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3466003682
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.595519898
Short name T52
Test name
Test status
Simulation time 109692399292 ps
CPU time 2320.7 seconds
Started Jul 16 07:06:19 PM PDT 24
Finished Jul 16 07:45:03 PM PDT 24
Peak memory 244692 kb
Host smart-ecc53a1b-499d-427a-b1e1-e2ed2ae63708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595519898 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.595519898
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.290323107
Short name T65
Test name
Test status
Simulation time 2628632964 ps
CPU time 8.55 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:06:25 PM PDT 24
Peak memory 211400 kb
Host smart-a8d538c2-e569-4b44-b324-6fae2058fa5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290323107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.290323107
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1634589767
Short name T245
Test name
Test status
Simulation time 24283650216 ps
CPU time 162.05 seconds
Started Jul 16 07:06:44 PM PDT 24
Finished Jul 16 07:09:27 PM PDT 24
Peak memory 237792 kb
Host smart-cd5a0fb6-8e55-491c-8dd0-9b59b55b7426
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634589767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1634589767
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.523499163
Short name T43
Test name
Test status
Simulation time 691689964 ps
CPU time 9.49 seconds
Started Jul 16 07:06:20 PM PDT 24
Finished Jul 16 07:06:32 PM PDT 24
Peak memory 211804 kb
Host smart-be920b78-0beb-4b09-876b-73ea14e211d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523499163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.523499163
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2263758817
Short name T305
Test name
Test status
Simulation time 1790191099 ps
CPU time 15.98 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:06:30 PM PDT 24
Peak memory 211292 kb
Host smart-a74db19c-a98e-4b81-9328-f9584606fa81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263758817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2263758817
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3280668634
Short name T20
Test name
Test status
Simulation time 3090810439 ps
CPU time 27.89 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:43 PM PDT 24
Peak memory 213356 kb
Host smart-298c41d6-8787-4b06-9acf-22dbd3b34910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280668634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3280668634
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.481966018
Short name T13
Test name
Test status
Simulation time 503497334 ps
CPU time 28.49 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:06:46 PM PDT 24
Peak memory 215508 kb
Host smart-dad80a7e-e263-4058-8fe6-30057511401e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481966018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.481966018
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3034897358
Short name T150
Test name
Test status
Simulation time 85731122 ps
CPU time 4.3 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:25 PM PDT 24
Peak memory 211340 kb
Host smart-8a479c18-ac81-4829-b188-2f9fc58f5f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034897358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3034897358
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1344373554
Short name T38
Test name
Test status
Simulation time 22681878915 ps
CPU time 111.49 seconds
Started Jul 16 07:06:18 PM PDT 24
Finished Jul 16 07:08:13 PM PDT 24
Peak memory 238088 kb
Host smart-ea22e565-3f6a-4977-a3b8-507695cac8c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344373554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1344373554
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1877261461
Short name T316
Test name
Test status
Simulation time 13144833874 ps
CPU time 29.59 seconds
Started Jul 16 07:06:18 PM PDT 24
Finished Jul 16 07:06:50 PM PDT 24
Peak memory 212476 kb
Host smart-24b6e8f6-4443-4c26-b2b0-772d2638b5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877261461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1877261461
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.664209938
Short name T178
Test name
Test status
Simulation time 4336288756 ps
CPU time 18.41 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:38 PM PDT 24
Peak memory 211420 kb
Host smart-e4c30c50-e845-41ef-b0a5-74bf7d737ee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=664209938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.664209938
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2386208892
Short name T298
Test name
Test status
Simulation time 8540070377 ps
CPU time 24.37 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:41 PM PDT 24
Peak memory 214152 kb
Host smart-8e2275bd-f64d-4acd-b933-ebd829f40c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386208892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2386208892
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.764771415
Short name T126
Test name
Test status
Simulation time 1300680754 ps
CPU time 14.86 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:31 PM PDT 24
Peak memory 215148 kb
Host smart-e6bcde30-0d13-46bd-be72-8488533631a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764771415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.764771415
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3772337626
Short name T208
Test name
Test status
Simulation time 1665486627 ps
CPU time 14 seconds
Started Jul 16 07:06:22 PM PDT 24
Finished Jul 16 07:06:37 PM PDT 24
Peak memory 211236 kb
Host smart-86322894-56eb-4d53-8926-c5c4410bbde7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772337626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3772337626
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.523957660
Short name T351
Test name
Test status
Simulation time 2468551506 ps
CPU time 159.24 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:08:59 PM PDT 24
Peak memory 237832 kb
Host smart-0bf41c7b-4b83-449c-8ec8-9e37c6185238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523957660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.523957660
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.542302654
Short name T215
Test name
Test status
Simulation time 15146357372 ps
CPU time 30.23 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:51 PM PDT 24
Peak memory 211448 kb
Host smart-847f336c-0af0-4090-ab65-5ac3ee9a81ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542302654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.542302654
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4203213461
Short name T179
Test name
Test status
Simulation time 2128251760 ps
CPU time 16.96 seconds
Started Jul 16 07:06:18 PM PDT 24
Finished Jul 16 07:06:38 PM PDT 24
Peak memory 211332 kb
Host smart-1f50007a-a18f-41ef-bbc4-d51aabed9e2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203213461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4203213461
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.979097829
Short name T314
Test name
Test status
Simulation time 445039974 ps
CPU time 10.53 seconds
Started Jul 16 07:06:19 PM PDT 24
Finished Jul 16 07:06:32 PM PDT 24
Peak memory 213500 kb
Host smart-14a60d04-5fc8-4c24-8f5b-1da950a42013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979097829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.979097829
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4074138194
Short name T127
Test name
Test status
Simulation time 3832744094 ps
CPU time 34.22 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:54 PM PDT 24
Peak memory 213740 kb
Host smart-80689c9c-b20b-44f7-a3ef-2315e5954821
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074138194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4074138194
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.536878884
Short name T219
Test name
Test status
Simulation time 2940162533 ps
CPU time 13.2 seconds
Started Jul 16 07:06:19 PM PDT 24
Finished Jul 16 07:06:35 PM PDT 24
Peak memory 211352 kb
Host smart-5edf88d1-c0e5-4b98-9410-6333c34a509c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536878884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.536878884
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.826684332
Short name T192
Test name
Test status
Simulation time 206320261776 ps
CPU time 493.67 seconds
Started Jul 16 07:06:19 PM PDT 24
Finished Jul 16 07:14:35 PM PDT 24
Peak memory 237224 kb
Host smart-47e6186e-623d-4601-82c5-98f5357360a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826684332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.826684332
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3009330957
Short name T161
Test name
Test status
Simulation time 692288482 ps
CPU time 9.28 seconds
Started Jul 16 07:06:19 PM PDT 24
Finished Jul 16 07:06:31 PM PDT 24
Peak memory 211928 kb
Host smart-d674be58-3c81-487a-a5ba-9884e5ec7bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009330957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3009330957
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3453346487
Short name T165
Test name
Test status
Simulation time 3613858848 ps
CPU time 15.59 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:32 PM PDT 24
Peak memory 211456 kb
Host smart-d92f0b3e-3149-433a-99e8-8177de79a274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453346487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3453346487
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3906051084
Short name T335
Test name
Test status
Simulation time 1084891169 ps
CPU time 18.4 seconds
Started Jul 16 07:06:25 PM PDT 24
Finished Jul 16 07:06:44 PM PDT 24
Peak memory 211800 kb
Host smart-04cb9611-6e94-41ff-a9e0-21e02a59ebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906051084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3906051084
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.682689765
Short name T30
Test name
Test status
Simulation time 3246294988 ps
CPU time 32.56 seconds
Started Jul 16 07:06:18 PM PDT 24
Finished Jul 16 07:06:57 PM PDT 24
Peak memory 214084 kb
Host smart-37b2142c-7ac6-471f-a58b-8ba690187540
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682689765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.682689765
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.162402201
Short name T35
Test name
Test status
Simulation time 5834165635 ps
CPU time 12.82 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:33 PM PDT 24
Peak memory 211400 kb
Host smart-7e7c0f0a-fcf0-4a4f-8063-6231d5962586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162402201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.162402201
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3319837885
Short name T6
Test name
Test status
Simulation time 17972649122 ps
CPU time 236.5 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:10:10 PM PDT 24
Peak memory 216312 kb
Host smart-ac78274e-cef0-4b22-a140-e2ae40124cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319837885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3319837885
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1278952616
Short name T188
Test name
Test status
Simulation time 10500057022 ps
CPU time 25.17 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:41 PM PDT 24
Peak memory 211408 kb
Host smart-a856d9cd-7e9c-46f7-a278-4b29e90213be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278952616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1278952616
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1192008482
Short name T148
Test name
Test status
Simulation time 748196192 ps
CPU time 10.12 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:06:28 PM PDT 24
Peak memory 211356 kb
Host smart-5fe7a568-dab3-4ee7-970f-4c09d65cbcff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192008482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1192008482
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3313626872
Short name T28
Test name
Test status
Simulation time 3328533662 ps
CPU time 103.01 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:08:00 PM PDT 24
Peak memory 238004 kb
Host smart-91ccc69e-25b9-4271-bcd3-8c0b35bb5d4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313626872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3313626872
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3352578968
Short name T248
Test name
Test status
Simulation time 12337849838 ps
CPU time 24.08 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:06:45 PM PDT 24
Peak memory 213968 kb
Host smart-621bdb20-7e50-4970-8462-7e47fc1849d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352578968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3352578968
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1479502224
Short name T340
Test name
Test status
Simulation time 12980760515 ps
CPU time 34.29 seconds
Started Jul 16 07:05:57 PM PDT 24
Finished Jul 16 07:06:32 PM PDT 24
Peak memory 213720 kb
Host smart-6598f65b-7664-48da-8fc3-f56bb6e257c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479502224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1479502224
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1963851862
Short name T228
Test name
Test status
Simulation time 8213944084 ps
CPU time 15.62 seconds
Started Jul 16 07:06:31 PM PDT 24
Finished Jul 16 07:06:48 PM PDT 24
Peak memory 211360 kb
Host smart-a8616385-03a9-477f-a035-80f3d8f7a1dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963851862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1963851862
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2536270617
Short name T135
Test name
Test status
Simulation time 12981120470 ps
CPU time 236.59 seconds
Started Jul 16 07:06:35 PM PDT 24
Finished Jul 16 07:10:32 PM PDT 24
Peak memory 236768 kb
Host smart-565cad7b-3dbe-4172-81b0-4a34d63291fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536270617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2536270617
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3518910379
Short name T233
Test name
Test status
Simulation time 10754670017 ps
CPU time 32.18 seconds
Started Jul 16 07:06:26 PM PDT 24
Finished Jul 16 07:07:00 PM PDT 24
Peak memory 213676 kb
Host smart-817b2d6e-5a02-40ce-bc41-ddacf0b5f708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518910379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3518910379
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3804824433
Short name T320
Test name
Test status
Simulation time 7381232170 ps
CPU time 15.59 seconds
Started Jul 16 07:06:27 PM PDT 24
Finished Jul 16 07:06:44 PM PDT 24
Peak memory 211388 kb
Host smart-b1fbff77-b686-476b-994e-f2c3e769a19f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804824433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3804824433
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.879346395
Short name T217
Test name
Test status
Simulation time 1372112566 ps
CPU time 12.83 seconds
Started Jul 16 07:06:20 PM PDT 24
Finished Jul 16 07:06:35 PM PDT 24
Peak memory 214000 kb
Host smart-008594f1-8801-4ad5-a036-c163fa23d367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879346395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.879346395
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2966784490
Short name T122
Test name
Test status
Simulation time 15457155215 ps
CPU time 33.55 seconds
Started Jul 16 07:06:31 PM PDT 24
Finished Jul 16 07:07:05 PM PDT 24
Peak memory 214780 kb
Host smart-dd8f7565-6d33-4954-990f-7347a08ec912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966784490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2966784490
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3737543530
Short name T149
Test name
Test status
Simulation time 1379813445 ps
CPU time 12.22 seconds
Started Jul 16 07:06:27 PM PDT 24
Finished Jul 16 07:06:40 PM PDT 24
Peak memory 211348 kb
Host smart-1c9beb62-c726-4f41-9c77-e5698cfb8c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737543530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3737543530
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3218752016
Short name T40
Test name
Test status
Simulation time 1575405970 ps
CPU time 92.61 seconds
Started Jul 16 07:06:43 PM PDT 24
Finished Jul 16 07:08:17 PM PDT 24
Peak memory 237796 kb
Host smart-a9de40b7-8182-403f-b9d6-aaa5fe8c84dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218752016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3218752016
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1579261192
Short name T283
Test name
Test status
Simulation time 7856634739 ps
CPU time 21.21 seconds
Started Jul 16 07:06:29 PM PDT 24
Finished Jul 16 07:06:51 PM PDT 24
Peak memory 212320 kb
Host smart-35d1cc68-8b61-49a1-b3e1-d353de881f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579261192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1579261192
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3265334440
Short name T204
Test name
Test status
Simulation time 102224125 ps
CPU time 5.86 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 07:06:46 PM PDT 24
Peak memory 211380 kb
Host smart-c1c46fd5-b2c9-4793-a1ef-9bec2be6afd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265334440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3265334440
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1070027304
Short name T271
Test name
Test status
Simulation time 14452263034 ps
CPU time 37.43 seconds
Started Jul 16 07:06:36 PM PDT 24
Finished Jul 16 07:07:15 PM PDT 24
Peak memory 213920 kb
Host smart-ceecb61e-85fd-4c2a-b722-f6f2d069cf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070027304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1070027304
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3343333138
Short name T14
Test name
Test status
Simulation time 11598106920 ps
CPU time 19.88 seconds
Started Jul 16 07:06:25 PM PDT 24
Finished Jul 16 07:06:45 PM PDT 24
Peak memory 214316 kb
Host smart-1bc2be5f-3daa-4b65-9896-7ea24cdc3fb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343333138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3343333138
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2015273813
Short name T332
Test name
Test status
Simulation time 1077613247 ps
CPU time 10.68 seconds
Started Jul 16 07:06:29 PM PDT 24
Finished Jul 16 07:06:40 PM PDT 24
Peak memory 211376 kb
Host smart-71629747-6eb7-4b95-8de5-95dbd99c2325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015273813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2015273813
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.867796105
Short name T209
Test name
Test status
Simulation time 214810434648 ps
CPU time 227.31 seconds
Started Jul 16 07:06:25 PM PDT 24
Finished Jul 16 07:10:13 PM PDT 24
Peak memory 238844 kb
Host smart-0ec6f977-4be3-42a1-b4dc-f35f55406128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867796105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.867796105
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1578174807
Short name T27
Test name
Test status
Simulation time 6869823573 ps
CPU time 19.9 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:06:59 PM PDT 24
Peak memory 211516 kb
Host smart-f425918b-801a-43fb-a578-8cd818c8ce97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578174807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1578174807
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2828115867
Short name T278
Test name
Test status
Simulation time 2576513959 ps
CPU time 13.39 seconds
Started Jul 16 07:06:33 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 211460 kb
Host smart-29bb8648-84d9-4edb-8406-b4c5d74bf6e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828115867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2828115867
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2175765018
Short name T131
Test name
Test status
Simulation time 43448902900 ps
CPU time 31.45 seconds
Started Jul 16 07:06:40 PM PDT 24
Finished Jul 16 07:07:13 PM PDT 24
Peak memory 214116 kb
Host smart-fee7d398-7fe0-4124-baf2-6ddbf1829cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175765018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2175765018
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3523794951
Short name T290
Test name
Test status
Simulation time 4032336191 ps
CPU time 42.47 seconds
Started Jul 16 07:06:26 PM PDT 24
Finished Jul 16 07:07:10 PM PDT 24
Peak memory 213460 kb
Host smart-ec7b87ff-4b5e-40ee-b098-4a9236b654ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523794951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3523794951
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1715413573
Short name T357
Test name
Test status
Simulation time 197092956100 ps
CPU time 1785.53 seconds
Started Jul 16 07:06:26 PM PDT 24
Finished Jul 16 07:36:13 PM PDT 24
Peak memory 235776 kb
Host smart-501c9ba2-8b36-4533-8c67-404ff2c0c0aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715413573 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1715413573
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1265301797
Short name T264
Test name
Test status
Simulation time 8476334928 ps
CPU time 17.25 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 07:06:58 PM PDT 24
Peak memory 211296 kb
Host smart-2ce7d8bb-89a8-483d-8b6f-8e8439625bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265301797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1265301797
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.285869335
Short name T234
Test name
Test status
Simulation time 7609641600 ps
CPU time 165.16 seconds
Started Jul 16 07:06:27 PM PDT 24
Finished Jul 16 07:09:13 PM PDT 24
Peak memory 237500 kb
Host smart-cd44c64d-2b37-4f36-8f14-11ff72cbb6e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285869335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.285869335
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.997764710
Short name T269
Test name
Test status
Simulation time 2904500892 ps
CPU time 26.13 seconds
Started Jul 16 07:06:26 PM PDT 24
Finished Jul 16 07:06:53 PM PDT 24
Peak memory 211960 kb
Host smart-82d77b85-800c-49c5-a755-c5220ce7fb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997764710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.997764710
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2087880290
Short name T181
Test name
Test status
Simulation time 1974915126 ps
CPU time 11.28 seconds
Started Jul 16 07:06:32 PM PDT 24
Finished Jul 16 07:06:44 PM PDT 24
Peak memory 211332 kb
Host smart-d299cc29-b483-4675-ad64-e97cf50c0916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087880290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2087880290
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3875166612
Short name T347
Test name
Test status
Simulation time 16153904830 ps
CPU time 28.02 seconds
Started Jul 16 07:06:31 PM PDT 24
Finished Jul 16 07:06:59 PM PDT 24
Peak memory 214088 kb
Host smart-e9502463-6fe0-480e-bc84-d959acdfdc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875166612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3875166612
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3037147331
Short name T5
Test name
Test status
Simulation time 13396330517 ps
CPU time 32.06 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:07:10 PM PDT 24
Peak memory 214620 kb
Host smart-5411a9f2-c7a6-4034-9299-e909daaf9dcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037147331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3037147331
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.569407264
Short name T104
Test name
Test status
Simulation time 45837481861 ps
CPU time 1562.71 seconds
Started Jul 16 07:06:26 PM PDT 24
Finished Jul 16 07:32:30 PM PDT 24
Peak memory 235880 kb
Host smart-73c3b37d-2cdd-4f6d-a19b-8976c6ce2ac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569407264 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.569407264
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2569431120
Short name T164
Test name
Test status
Simulation time 347177758 ps
CPU time 5.04 seconds
Started Jul 16 07:06:30 PM PDT 24
Finished Jul 16 07:06:36 PM PDT 24
Peak memory 211264 kb
Host smart-aa60e8d5-750e-4b59-8f03-8e5a64ed1d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569431120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2569431120
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2258393693
Short name T48
Test name
Test status
Simulation time 17978703884 ps
CPU time 215.72 seconds
Started Jul 16 07:06:29 PM PDT 24
Finished Jul 16 07:10:06 PM PDT 24
Peak memory 237832 kb
Host smart-3de12d2b-4898-4ad9-a049-de2cc6038789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258393693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2258393693
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.873383761
Short name T266
Test name
Test status
Simulation time 8689704323 ps
CPU time 19.41 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:06:58 PM PDT 24
Peak memory 212252 kb
Host smart-4531a327-c861-4699-9c2e-a7668ea4b003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873383761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.873383761
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.309984433
Short name T146
Test name
Test status
Simulation time 1853132501 ps
CPU time 15.28 seconds
Started Jul 16 07:06:32 PM PDT 24
Finished Jul 16 07:06:49 PM PDT 24
Peak memory 211280 kb
Host smart-e4584958-1a02-4123-bd8a-50ecb7e0b496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309984433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.309984433
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4067957722
Short name T18
Test name
Test status
Simulation time 3443802579 ps
CPU time 36.55 seconds
Started Jul 16 07:06:32 PM PDT 24
Finished Jul 16 07:07:09 PM PDT 24
Peak memory 213412 kb
Host smart-430c0465-3678-4d7f-935e-49754b1ac6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067957722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4067957722
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1639154241
Short name T82
Test name
Test status
Simulation time 17788882624 ps
CPU time 46.99 seconds
Started Jul 16 07:06:45 PM PDT 24
Finished Jul 16 07:07:33 PM PDT 24
Peak memory 216640 kb
Host smart-e1e54989-38f7-4cdd-81eb-e9fe64dc7212
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639154241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1639154241
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1521887131
Short name T154
Test name
Test status
Simulation time 4478785463 ps
CPU time 10.46 seconds
Started Jul 16 07:06:26 PM PDT 24
Finished Jul 16 07:06:37 PM PDT 24
Peak memory 211368 kb
Host smart-4b2a4487-c134-4606-bf2e-13281738525b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521887131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1521887131
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1437305283
Short name T229
Test name
Test status
Simulation time 31016402264 ps
CPU time 114.6 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:08:33 PM PDT 24
Peak memory 233168 kb
Host smart-e2ba421b-9690-4287-9939-969e06a9e976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437305283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1437305283
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3193808809
Short name T36
Test name
Test status
Simulation time 2629160808 ps
CPU time 14.23 seconds
Started Jul 16 07:06:32 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 211960 kb
Host smart-36d56c62-fe87-4111-b8e0-e9471eec7fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193808809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3193808809
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3628734108
Short name T325
Test name
Test status
Simulation time 4666128872 ps
CPU time 13.03 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:06:52 PM PDT 24
Peak memory 211408 kb
Host smart-899bab8d-eaac-4e77-a7e3-c077181cf768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3628734108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3628734108
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4229636794
Short name T304
Test name
Test status
Simulation time 2134812817 ps
CPU time 23.94 seconds
Started Jul 16 07:06:36 PM PDT 24
Finished Jul 16 07:07:01 PM PDT 24
Peak memory 213148 kb
Host smart-27ffe8d1-7e61-4d23-808c-bcfc8f259fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229636794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4229636794
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2135183931
Short name T323
Test name
Test status
Simulation time 7166289311 ps
CPU time 60.76 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 07:07:41 PM PDT 24
Peak memory 217364 kb
Host smart-cd1f1fa1-1f93-4f77-b626-bf22ad6803ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135183931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2135183931
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1450179747
Short name T32
Test name
Test status
Simulation time 7567378705 ps
CPU time 15.24 seconds
Started Jul 16 07:06:27 PM PDT 24
Finished Jul 16 07:06:43 PM PDT 24
Peak memory 211412 kb
Host smart-ced2d5cd-fd16-4809-9e3b-fad40d011f78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450179747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1450179747
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2310834744
Short name T354
Test name
Test status
Simulation time 96729314740 ps
CPU time 264.62 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:11:03 PM PDT 24
Peak memory 236904 kb
Host smart-4f7b22a0-5fb0-4bee-93ad-91ef617e0f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310834744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2310834744
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1537597786
Short name T307
Test name
Test status
Simulation time 8156594543 ps
CPU time 16.41 seconds
Started Jul 16 07:06:41 PM PDT 24
Finished Jul 16 07:06:59 PM PDT 24
Peak memory 212268 kb
Host smart-5ec615e4-d26b-4a5c-85db-f84cea272cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537597786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1537597786
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.324748404
Short name T303
Test name
Test status
Simulation time 371673724 ps
CPU time 5.23 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 07:06:45 PM PDT 24
Peak memory 211360 kb
Host smart-160bf343-b1bf-4879-a27f-5a053d53700b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324748404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.324748404
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.316509789
Short name T158
Test name
Test status
Simulation time 188766777 ps
CPU time 10.21 seconds
Started Jul 16 07:06:28 PM PDT 24
Finished Jul 16 07:06:39 PM PDT 24
Peak memory 213308 kb
Host smart-2c29da8b-ab8d-495c-9ebc-9774fbc3e3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316509789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.316509789
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1502079897
Short name T212
Test name
Test status
Simulation time 1787641251 ps
CPU time 36.27 seconds
Started Jul 16 07:06:36 PM PDT 24
Finished Jul 16 07:07:13 PM PDT 24
Peak memory 215612 kb
Host smart-31d033fe-da0a-49b8-8f22-ccc1fb761007
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502079897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1502079897
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2412766200
Short name T162
Test name
Test status
Simulation time 1728445216 ps
CPU time 14.1 seconds
Started Jul 16 07:06:32 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 211248 kb
Host smart-ed1662b0-e84c-4976-a50d-c5407c40a42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412766200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2412766200
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3093953877
Short name T313
Test name
Test status
Simulation time 23048474153 ps
CPU time 211.32 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:10:12 PM PDT 24
Peak memory 237844 kb
Host smart-3936b06a-6d01-43c8-8d4b-0eddd8fb7a99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093953877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3093953877
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2611898613
Short name T172
Test name
Test status
Simulation time 8296228213 ps
CPU time 12.49 seconds
Started Jul 16 07:06:33 PM PDT 24
Finished Jul 16 07:06:46 PM PDT 24
Peak memory 212628 kb
Host smart-facb30ce-9ab3-43f8-af45-ad6265dc477e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611898613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2611898613
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.626019526
Short name T156
Test name
Test status
Simulation time 569846401 ps
CPU time 5.4 seconds
Started Jul 16 07:06:41 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 211336 kb
Host smart-7ff47870-643e-45dd-92f6-d6555a2f2e78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626019526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.626019526
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.479021417
Short name T139
Test name
Test status
Simulation time 7040125114 ps
CPU time 23.46 seconds
Started Jul 16 07:06:32 PM PDT 24
Finished Jul 16 07:06:57 PM PDT 24
Peak memory 214140 kb
Host smart-b3c2f962-a8c8-4370-b18a-fbe10d455e3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479021417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.479021417
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.203328716
Short name T225
Test name
Test status
Simulation time 89103276 ps
CPU time 4.45 seconds
Started Jul 16 07:06:47 PM PDT 24
Finished Jul 16 07:06:53 PM PDT 24
Peak memory 211300 kb
Host smart-a24fe21a-59c4-4a6e-8264-15634dd32d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203328716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.203328716
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2727575847
Short name T338
Test name
Test status
Simulation time 1917446746 ps
CPU time 119.11 seconds
Started Jul 16 07:06:35 PM PDT 24
Finished Jul 16 07:08:35 PM PDT 24
Peak memory 237656 kb
Host smart-0b78c614-2d82-4024-8a46-2c5ba907a465
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727575847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2727575847
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.31672549
Short name T273
Test name
Test status
Simulation time 7197137914 ps
CPU time 20.25 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 07:07:00 PM PDT 24
Peak memory 211764 kb
Host smart-2ac1ec17-3e5d-47ea-aa18-36ae1a1d9e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31672549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.31672549
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.605479048
Short name T333
Test name
Test status
Simulation time 6019830352 ps
CPU time 14.13 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:06:55 PM PDT 24
Peak memory 211624 kb
Host smart-4fc5c76d-19a1-4339-823c-5551491ebcc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605479048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.605479048
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3753864827
Short name T326
Test name
Test status
Simulation time 1733351410 ps
CPU time 10.08 seconds
Started Jul 16 07:06:44 PM PDT 24
Finished Jul 16 07:06:55 PM PDT 24
Peak memory 213428 kb
Host smart-403e4a5f-1d5b-4714-bc78-9bf1effecee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753864827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3753864827
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2384169349
Short name T275
Test name
Test status
Simulation time 2951337427 ps
CPU time 30.49 seconds
Started Jul 16 07:06:27 PM PDT 24
Finished Jul 16 07:06:58 PM PDT 24
Peak memory 213924 kb
Host smart-4860c48a-18f4-4fae-a53e-ae41f2b6386a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384169349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2384169349
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1590910089
Short name T345
Test name
Test status
Simulation time 57671363524 ps
CPU time 2049.8 seconds
Started Jul 16 07:06:28 PM PDT 24
Finished Jul 16 07:40:38 PM PDT 24
Peak memory 236388 kb
Host smart-85e4131c-21e3-4f10-b8d4-f3c7a3fcd27a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590910089 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1590910089
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2906074213
Short name T358
Test name
Test status
Simulation time 1361528762 ps
CPU time 8.27 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 211328 kb
Host smart-1168abb6-76e5-4466-8d50-61f994d12389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906074213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2906074213
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1625691174
Short name T195
Test name
Test status
Simulation time 348769378378 ps
CPU time 240.95 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 07:10:42 PM PDT 24
Peak memory 234884 kb
Host smart-8581c335-cde0-4b2b-a1a7-345c05500094
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625691174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1625691174
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2916585571
Short name T268
Test name
Test status
Simulation time 348085805 ps
CPU time 9.46 seconds
Started Jul 16 07:06:41 PM PDT 24
Finished Jul 16 07:06:52 PM PDT 24
Peak memory 211844 kb
Host smart-2ae6dcfe-2403-436b-af81-710e5518af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916585571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2916585571
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4066751488
Short name T291
Test name
Test status
Simulation time 1005699025 ps
CPU time 11.69 seconds
Started Jul 16 07:06:32 PM PDT 24
Finished Jul 16 07:06:45 PM PDT 24
Peak memory 211568 kb
Host smart-63811b4d-91bd-486f-af5f-07d955d9c1ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066751488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4066751488
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.995744274
Short name T309
Test name
Test status
Simulation time 3280007749 ps
CPU time 14.24 seconds
Started Jul 16 07:06:26 PM PDT 24
Finished Jul 16 07:06:41 PM PDT 24
Peak memory 213556 kb
Host smart-5e8f9f08-604e-4c32-9cdd-96694389765b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995744274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.995744274
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.335623600
Short name T200
Test name
Test status
Simulation time 38536499048 ps
CPU time 76.16 seconds
Started Jul 16 07:06:33 PM PDT 24
Finished Jul 16 07:07:50 PM PDT 24
Peak memory 219380 kb
Host smart-cc55c3c2-78c5-46a6-911c-0c79e8009c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335623600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.335623600
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2002699292
Short name T253
Test name
Test status
Simulation time 172097421 ps
CPU time 5.5 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:06:19 PM PDT 24
Peak memory 211300 kb
Host smart-54946cb5-ac09-4c10-a63f-8a534f42caa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002699292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2002699292
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2388013617
Short name T306
Test name
Test status
Simulation time 4015876538 ps
CPU time 120.11 seconds
Started Jul 16 07:06:00 PM PDT 24
Finished Jul 16 07:08:02 PM PDT 24
Peak memory 234976 kb
Host smart-aab413e4-9864-48bd-b45d-f79afe3bd4ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388013617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2388013617
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.772886792
Short name T159
Test name
Test status
Simulation time 16460172892 ps
CPU time 33.54 seconds
Started Jul 16 07:05:57 PM PDT 24
Finished Jul 16 07:06:31 PM PDT 24
Peak memory 212252 kb
Host smart-c92d947b-39b3-4346-9503-6a842253d65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772886792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.772886792
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4074414793
Short name T222
Test name
Test status
Simulation time 2796103741 ps
CPU time 13.51 seconds
Started Jul 16 07:05:57 PM PDT 24
Finished Jul 16 07:06:11 PM PDT 24
Peak memory 211356 kb
Host smart-97ce5804-7635-4dbe-9ba3-bf12f96665e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074414793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4074414793
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4265322632
Short name T24
Test name
Test status
Simulation time 547575559 ps
CPU time 54.57 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:07:13 PM PDT 24
Peak memory 236812 kb
Host smart-01d9b6b3-6a80-43d3-9b17-a3ff719ba32d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265322632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4265322632
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3715518325
Short name T167
Test name
Test status
Simulation time 10634230125 ps
CPU time 25.85 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:43 PM PDT 24
Peak memory 214056 kb
Host smart-a6be5d35-43eb-4b53-8286-3dce327a8762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715518325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3715518325
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1230191658
Short name T339
Test name
Test status
Simulation time 693492815 ps
CPU time 19.1 seconds
Started Jul 16 07:06:10 PM PDT 24
Finished Jul 16 07:06:30 PM PDT 24
Peak memory 214796 kb
Host smart-7f458297-c167-41a4-a5ad-9389ad08b95d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230191658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1230191658
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1122028520
Short name T49
Test name
Test status
Simulation time 260757523834 ps
CPU time 2487.71 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:47:43 PM PDT 24
Peak memory 236584 kb
Host smart-5097b408-5a45-455f-a240-ea135dfc3e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122028520 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1122028520
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3720340123
Short name T241
Test name
Test status
Simulation time 88232450 ps
CPU time 4.23 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:06:43 PM PDT 24
Peak memory 211320 kb
Host smart-43c83fc6-86f4-4e65-954b-48c80d6a52f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720340123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3720340123
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2282264397
Short name T244
Test name
Test status
Simulation time 831935332 ps
CPU time 9.35 seconds
Started Jul 16 07:06:34 PM PDT 24
Finished Jul 16 07:06:44 PM PDT 24
Peak memory 212192 kb
Host smart-a523289b-8570-4584-a207-717bef1dd764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282264397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2282264397
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2899651594
Short name T308
Test name
Test status
Simulation time 380699534 ps
CPU time 5.87 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 211384 kb
Host smart-ab3db5a4-ec9b-4443-ba23-ecc2766238fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899651594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2899651594
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1211436608
Short name T255
Test name
Test status
Simulation time 3205485854 ps
CPU time 32.68 seconds
Started Jul 16 07:06:50 PM PDT 24
Finished Jul 16 07:07:23 PM PDT 24
Peak memory 213708 kb
Host smart-0712a734-dd4f-44c5-bf65-bd317bad02d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211436608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1211436608
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3826211963
Short name T124
Test name
Test status
Simulation time 5439599213 ps
CPU time 26.65 seconds
Started Jul 16 07:06:32 PM PDT 24
Finished Jul 16 07:07:00 PM PDT 24
Peak memory 213244 kb
Host smart-03c50f4f-5ebf-41e5-afc8-971fcea77356
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826211963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3826211963
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2538611540
Short name T168
Test name
Test status
Simulation time 14616909406 ps
CPU time 10.27 seconds
Started Jul 16 07:06:36 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 211352 kb
Host smart-3021fe4d-91ee-4125-933f-c7649c54a8d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538611540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2538611540
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.768174328
Short name T334
Test name
Test status
Simulation time 3707320134 ps
CPU time 117.6 seconds
Started Jul 16 07:06:44 PM PDT 24
Finished Jul 16 07:08:43 PM PDT 24
Peak memory 233856 kb
Host smart-1190502a-eae4-499d-83eb-a45676b277fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768174328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.768174328
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2198817032
Short name T44
Test name
Test status
Simulation time 10479368772 ps
CPU time 25.33 seconds
Started Jul 16 07:06:36 PM PDT 24
Finished Jul 16 07:07:02 PM PDT 24
Peak memory 212336 kb
Host smart-17ce434a-d28d-49e1-8d56-76314e9fafc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198817032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2198817032
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.248245473
Short name T183
Test name
Test status
Simulation time 5214186730 ps
CPU time 13.29 seconds
Started Jul 16 07:06:40 PM PDT 24
Finished Jul 16 07:06:55 PM PDT 24
Peak memory 211396 kb
Host smart-03cdf9d9-d915-4b8d-a480-37b28bb3ef05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248245473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.248245473
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2555291225
Short name T205
Test name
Test status
Simulation time 6504204218 ps
CPU time 27.44 seconds
Started Jul 16 07:06:28 PM PDT 24
Finished Jul 16 07:06:56 PM PDT 24
Peak memory 214820 kb
Host smart-050a153d-2dd1-41f2-80ff-bcb77422e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555291225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2555291225
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3551190965
Short name T17
Test name
Test status
Simulation time 465414254 ps
CPU time 27.06 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:07:05 PM PDT 24
Peak memory 215928 kb
Host smart-a04cc583-e6c3-42e7-8f5b-2b1d9302e804
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551190965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3551190965
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2276428519
Short name T134
Test name
Test status
Simulation time 89338114 ps
CPU time 4.23 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:06:44 PM PDT 24
Peak memory 211324 kb
Host smart-ce52d14c-6151-4c5a-a5ea-7f6b5ca6ab51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276428519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2276428519
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1060467487
Short name T346
Test name
Test status
Simulation time 22562123399 ps
CPU time 243.62 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:10:44 PM PDT 24
Peak memory 233140 kb
Host smart-f80149c7-db20-4d2d-b155-f9ffbb3e1f14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060467487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1060467487
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2049977634
Short name T206
Test name
Test status
Simulation time 4230266183 ps
CPU time 33.42 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:07:13 PM PDT 24
Peak memory 211956 kb
Host smart-9bc10c5b-0bc1-46a1-a54d-6b1912271259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049977634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2049977634
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3253631694
Short name T342
Test name
Test status
Simulation time 1433208136 ps
CPU time 10.15 seconds
Started Jul 16 07:06:34 PM PDT 24
Finished Jul 16 07:06:45 PM PDT 24
Peak memory 211568 kb
Host smart-6ea4835f-a079-4b87-9237-ae4a94b5628f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253631694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3253631694
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1769653525
Short name T274
Test name
Test status
Simulation time 3205291100 ps
CPU time 28.53 seconds
Started Jul 16 07:06:30 PM PDT 24
Finished Jul 16 07:06:59 PM PDT 24
Peak memory 212952 kb
Host smart-94a3b7b5-a78c-4d3e-b8cc-22bbc0f50e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769653525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1769653525
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3104911598
Short name T216
Test name
Test status
Simulation time 2173474024 ps
CPU time 27.57 seconds
Started Jul 16 07:06:41 PM PDT 24
Finished Jul 16 07:07:10 PM PDT 24
Peak memory 213616 kb
Host smart-79c3e0e2-539b-465b-837a-2afcf5022645
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104911598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3104911598
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2170711986
Short name T297
Test name
Test status
Simulation time 361890233 ps
CPU time 4.22 seconds
Started Jul 16 07:06:46 PM PDT 24
Finished Jul 16 07:06:51 PM PDT 24
Peak memory 211340 kb
Host smart-70d14743-e5ed-480c-89d7-d59481bd3d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170711986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2170711986
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3265992474
Short name T1
Test name
Test status
Simulation time 3537122621 ps
CPU time 112.67 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:08:31 PM PDT 24
Peak memory 237828 kb
Host smart-6d46b73b-1955-4102-a2c3-b8124d2a61aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265992474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3265992474
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2311391254
Short name T359
Test name
Test status
Simulation time 178416984 ps
CPU time 9.56 seconds
Started Jul 16 07:07:10 PM PDT 24
Finished Jul 16 07:07:20 PM PDT 24
Peak memory 212812 kb
Host smart-96fdca51-e050-4e2f-b34a-3909cd858416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311391254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2311391254
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3265764919
Short name T301
Test name
Test status
Simulation time 5689859109 ps
CPU time 9.54 seconds
Started Jul 16 07:06:42 PM PDT 24
Finished Jul 16 07:06:52 PM PDT 24
Peak memory 211448 kb
Host smart-809cd0bf-0f0f-4da5-b657-9a8834f8d492
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265764919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3265764919
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2843468205
Short name T201
Test name
Test status
Simulation time 1332959641 ps
CPU time 9.93 seconds
Started Jul 16 07:06:36 PM PDT 24
Finished Jul 16 07:06:46 PM PDT 24
Peak memory 213804 kb
Host smart-48442b52-07c2-455a-8222-79761195d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843468205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2843468205
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2028706759
Short name T50
Test name
Test status
Simulation time 21712901591 ps
CPU time 826.3 seconds
Started Jul 16 07:06:47 PM PDT 24
Finished Jul 16 07:20:35 PM PDT 24
Peak memory 235504 kb
Host smart-84bcd369-beef-4138-9b71-fbe6e4c1f651
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028706759 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2028706759
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1037852903
Short name T133
Test name
Test status
Simulation time 2874244863 ps
CPU time 13.5 seconds
Started Jul 16 07:06:51 PM PDT 24
Finished Jul 16 07:07:05 PM PDT 24
Peak memory 211364 kb
Host smart-54bada17-b880-4778-b7c6-9d91184d6f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037852903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1037852903
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.679054157
Short name T270
Test name
Test status
Simulation time 1459910272 ps
CPU time 87.8 seconds
Started Jul 16 07:06:41 PM PDT 24
Finished Jul 16 07:08:11 PM PDT 24
Peak memory 237692 kb
Host smart-785acad3-d270-498f-9694-a9a17d467898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679054157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.679054157
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4121406552
Short name T145
Test name
Test status
Simulation time 14393388468 ps
CPU time 31.03 seconds
Started Jul 16 07:06:48 PM PDT 24
Finished Jul 16 07:07:20 PM PDT 24
Peak memory 212172 kb
Host smart-a656eac8-77da-494e-832a-030793176035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121406552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4121406552
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2614836930
Short name T31
Test name
Test status
Simulation time 708508163 ps
CPU time 9.64 seconds
Started Jul 16 07:07:05 PM PDT 24
Finished Jul 16 07:07:17 PM PDT 24
Peak memory 211344 kb
Host smart-9d89b808-3c92-45b3-bad9-d31c2dc235f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614836930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2614836930
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2484496309
Short name T199
Test name
Test status
Simulation time 1638094517 ps
CPU time 19.35 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:07:00 PM PDT 24
Peak memory 213176 kb
Host smart-d96f5b47-3cd8-4c64-9090-c3f97c04a762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484496309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2484496309
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2504747604
Short name T292
Test name
Test status
Simulation time 26926755942 ps
CPU time 106.15 seconds
Started Jul 16 07:06:42 PM PDT 24
Finished Jul 16 07:08:29 PM PDT 24
Peak memory 219356 kb
Host smart-bd337e7f-532d-42bd-ac64-67ef8862ebc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504747604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2504747604
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1989702439
Short name T288
Test name
Test status
Simulation time 8886276949 ps
CPU time 17.51 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:06:58 PM PDT 24
Peak memory 211320 kb
Host smart-f44dfae0-6ba9-4e41-b878-b0f856511424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989702439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1989702439
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2383209211
Short name T349
Test name
Test status
Simulation time 14919523539 ps
CPU time 131.22 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:08:52 PM PDT 24
Peak memory 237796 kb
Host smart-319cd272-5464-4a2a-8022-896b8616c28b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383209211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2383209211
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1356534671
Short name T296
Test name
Test status
Simulation time 3627010793 ps
CPU time 28.75 seconds
Started Jul 16 07:06:40 PM PDT 24
Finished Jul 16 07:07:10 PM PDT 24
Peak memory 211948 kb
Host smart-ae673b84-7376-4f49-9582-962d6563e6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356534671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1356534671
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3685518948
Short name T157
Test name
Test status
Simulation time 1275519414 ps
CPU time 12.92 seconds
Started Jul 16 07:06:50 PM PDT 24
Finished Jul 16 07:07:03 PM PDT 24
Peak memory 211288 kb
Host smart-31e12df4-2fea-4e61-858d-f37e840487cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685518948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3685518948
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3003706699
Short name T321
Test name
Test status
Simulation time 2949317072 ps
CPU time 14.28 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:06:54 PM PDT 24
Peak memory 213316 kb
Host smart-b7fe5411-119b-43e8-b642-0739ee882402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003706699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3003706699
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.767500198
Short name T350
Test name
Test status
Simulation time 11189371424 ps
CPU time 15.6 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:06:56 PM PDT 24
Peak memory 211244 kb
Host smart-6c9ea4d4-6cbe-4c21-ab7f-d666b92ffab9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767500198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.767500198
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3165315950
Short name T16
Test name
Test status
Simulation time 86450692468 ps
CPU time 3631.75 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 08:07:12 PM PDT 24
Peak memory 250988 kb
Host smart-d22b4806-592f-4c2a-a46f-6a02276a695d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165315950 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3165315950
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1516744915
Short name T67
Test name
Test status
Simulation time 3939511313 ps
CPU time 10.9 seconds
Started Jul 16 07:06:35 PM PDT 24
Finished Jul 16 07:06:47 PM PDT 24
Peak memory 211408 kb
Host smart-a66195dd-02c3-4039-bc79-e8f12db13349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516744915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1516744915
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4099796700
Short name T218
Test name
Test status
Simulation time 15507372819 ps
CPU time 274.43 seconds
Started Jul 16 07:06:48 PM PDT 24
Finished Jul 16 07:11:23 PM PDT 24
Peak memory 237820 kb
Host smart-90917c4e-503b-469b-aace-d64a39ead42d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099796700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4099796700
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2038066857
Short name T193
Test name
Test status
Simulation time 7359401731 ps
CPU time 32.66 seconds
Started Jul 16 07:06:47 PM PDT 24
Finished Jul 16 07:07:21 PM PDT 24
Peak memory 212452 kb
Host smart-1cf17b22-48da-4793-b6a7-7c234029fe40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038066857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2038066857
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.863868305
Short name T254
Test name
Test status
Simulation time 180556067 ps
CPU time 5.49 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 07:06:45 PM PDT 24
Peak memory 211392 kb
Host smart-0d8dc2e1-119e-4aef-8d9c-d3f3ebe80ef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=863868305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.863868305
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1705166432
Short name T132
Test name
Test status
Simulation time 2681088606 ps
CPU time 14.34 seconds
Started Jul 16 07:06:48 PM PDT 24
Finished Jul 16 07:07:04 PM PDT 24
Peak memory 213528 kb
Host smart-fcc21b08-68de-4ee1-a794-0dbf3c3b7e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705166432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1705166432
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.693389911
Short name T196
Test name
Test status
Simulation time 369085147 ps
CPU time 13.41 seconds
Started Jul 16 07:06:50 PM PDT 24
Finished Jul 16 07:07:04 PM PDT 24
Peak memory 215256 kb
Host smart-ba9e0a04-9371-4deb-b890-6528a39ed886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693389911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.693389911
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.772530442
Short name T141
Test name
Test status
Simulation time 742381563 ps
CPU time 9.03 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 07:06:49 PM PDT 24
Peak memory 211288 kb
Host smart-42118004-bde7-4f5b-80ee-1b3308038784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772530442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.772530442
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.667322952
Short name T147
Test name
Test status
Simulation time 6483799931 ps
CPU time 91 seconds
Started Jul 16 07:06:49 PM PDT 24
Finished Jul 16 07:08:20 PM PDT 24
Peak memory 237840 kb
Host smart-9de5890e-dab9-457d-8f63-c8c66dc985d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667322952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.667322952
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2559651238
Short name T238
Test name
Test status
Simulation time 9177960687 ps
CPU time 15.55 seconds
Started Jul 16 07:07:02 PM PDT 24
Finished Jul 16 07:07:19 PM PDT 24
Peak memory 212012 kb
Host smart-c1b07977-ffc7-48d5-ade5-daf7826f3791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559651238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2559651238
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3315205315
Short name T242
Test name
Test status
Simulation time 4274660088 ps
CPU time 12.31 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:06:53 PM PDT 24
Peak memory 211476 kb
Host smart-a86ca940-37d1-47e9-b173-b1bedf1ff643
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3315205315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3315205315
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.314225320
Short name T221
Test name
Test status
Simulation time 7519658953 ps
CPU time 30.24 seconds
Started Jul 16 07:06:38 PM PDT 24
Finished Jul 16 07:07:10 PM PDT 24
Peak memory 213480 kb
Host smart-7b2e9525-bf37-4cf7-8d24-9857f333e889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314225320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.314225320
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3787846120
Short name T19
Test name
Test status
Simulation time 1024120313 ps
CPU time 15.39 seconds
Started Jul 16 07:07:02 PM PDT 24
Finished Jul 16 07:07:19 PM PDT 24
Peak memory 211644 kb
Host smart-7a7c6179-8417-425b-8892-4c8e2a56d974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787846120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3787846120
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2183789000
Short name T55
Test name
Test status
Simulation time 104462743515 ps
CPU time 7891.28 seconds
Started Jul 16 07:06:45 PM PDT 24
Finished Jul 16 09:18:18 PM PDT 24
Peak memory 233036 kb
Host smart-140840a4-7b6a-42e7-a1ce-34ff133dadba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183789000 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2183789000
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3960604390
Short name T186
Test name
Test status
Simulation time 594967724 ps
CPU time 4.19 seconds
Started Jul 16 07:06:37 PM PDT 24
Finished Jul 16 07:06:43 PM PDT 24
Peak memory 211340 kb
Host smart-455c123d-6be8-410c-a954-bec31facb55a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960604390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3960604390
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2341052330
Short name T237
Test name
Test status
Simulation time 139575961939 ps
CPU time 351.97 seconds
Started Jul 16 07:06:59 PM PDT 24
Finished Jul 16 07:12:51 PM PDT 24
Peak memory 237820 kb
Host smart-9afceb3b-c5f6-4d75-bba9-6395c62cd3f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341052330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2341052330
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3065542209
Short name T239
Test name
Test status
Simulation time 27920499259 ps
CPU time 25.4 seconds
Started Jul 16 07:06:41 PM PDT 24
Finished Jul 16 07:07:08 PM PDT 24
Peak memory 212216 kb
Host smart-62374aea-f816-47d9-9ddb-67129d39e8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065542209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3065542209
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3218085220
Short name T259
Test name
Test status
Simulation time 1484463029 ps
CPU time 13.42 seconds
Started Jul 16 07:06:49 PM PDT 24
Finished Jul 16 07:07:03 PM PDT 24
Peak memory 211356 kb
Host smart-6fae7ce7-ead6-4130-a2a4-84b2ecda02a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218085220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3218085220
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4212610941
Short name T289
Test name
Test status
Simulation time 2920083125 ps
CPU time 26.7 seconds
Started Jul 16 07:06:48 PM PDT 24
Finished Jul 16 07:07:16 PM PDT 24
Peak memory 213544 kb
Host smart-2b003feb-42d8-42f2-97fb-d600f4edff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212610941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4212610941
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3169866867
Short name T227
Test name
Test status
Simulation time 42939404829 ps
CPU time 93.83 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:08:15 PM PDT 24
Peak memory 217856 kb
Host smart-9fa3c840-3ddf-41ab-8141-97262920a356
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169866867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3169866867
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3891915059
Short name T54
Test name
Test status
Simulation time 84291903611 ps
CPU time 879.1 seconds
Started Jul 16 07:06:41 PM PDT 24
Finished Jul 16 07:21:22 PM PDT 24
Peak memory 235764 kb
Host smart-08aabaf8-86da-49f4-b4dc-5a0f770712e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891915059 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3891915059
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1494159645
Short name T63
Test name
Test status
Simulation time 905469835 ps
CPU time 9.48 seconds
Started Jul 16 07:06:47 PM PDT 24
Finished Jul 16 07:06:58 PM PDT 24
Peak memory 211340 kb
Host smart-7399ff50-fe12-45a2-9d03-d40985d539c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494159645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1494159645
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.74409772
Short name T256
Test name
Test status
Simulation time 3557395433 ps
CPU time 97.01 seconds
Started Jul 16 07:06:41 PM PDT 24
Finished Jul 16 07:08:19 PM PDT 24
Peak memory 233380 kb
Host smart-24b825be-0f6a-426a-ab6a-6108b7508426
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74409772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_co
rrupt_sig_fatal_chk.74409772
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1682429385
Short name T265
Test name
Test status
Simulation time 4250186022 ps
CPU time 17.33 seconds
Started Jul 16 07:07:02 PM PDT 24
Finished Jul 16 07:07:21 PM PDT 24
Peak memory 211964 kb
Host smart-4c1fceac-80ad-4d52-9aee-7bd548b960da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682429385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1682429385
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4123323477
Short name T176
Test name
Test status
Simulation time 1631211946 ps
CPU time 12.1 seconds
Started Jul 16 07:07:02 PM PDT 24
Finished Jul 16 07:07:15 PM PDT 24
Peak memory 211404 kb
Host smart-1d772f41-db10-4540-957a-35d2f8947240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123323477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4123323477
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2910299102
Short name T235
Test name
Test status
Simulation time 13159456171 ps
CPU time 31.91 seconds
Started Jul 16 07:06:46 PM PDT 24
Finished Jul 16 07:07:19 PM PDT 24
Peak memory 214284 kb
Host smart-4965f90c-394a-4c60-a404-6915e2311f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910299102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2910299102
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.135676597
Short name T175
Test name
Test status
Simulation time 221426200 ps
CPU time 12.52 seconds
Started Jul 16 07:06:51 PM PDT 24
Finished Jul 16 07:07:04 PM PDT 24
Peak memory 214132 kb
Host smart-d6ab34ba-c92f-49f6-8bd3-39efe9c3e728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135676597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.135676597
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3354842162
Short name T344
Test name
Test status
Simulation time 1832684491 ps
CPU time 15.03 seconds
Started Jul 16 07:06:08 PM PDT 24
Finished Jul 16 07:06:24 PM PDT 24
Peak memory 211268 kb
Host smart-95892485-bda0-4625-8eb5-33eb0b560330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354842162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3354842162
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.853533314
Short name T361
Test name
Test status
Simulation time 10050612298 ps
CPU time 130.59 seconds
Started Jul 16 07:06:07 PM PDT 24
Finished Jul 16 07:08:19 PM PDT 24
Peak memory 237768 kb
Host smart-950f0e81-7fc9-4625-a736-011e8817bc73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853533314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.853533314
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3742319393
Short name T177
Test name
Test status
Simulation time 45742271802 ps
CPU time 30.43 seconds
Started Jul 16 07:06:00 PM PDT 24
Finished Jul 16 07:06:31 PM PDT 24
Peak memory 212416 kb
Host smart-df94e36e-18ae-4bd6-874a-5944775367ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742319393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3742319393
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3232163121
Short name T267
Test name
Test status
Simulation time 529508642 ps
CPU time 8.66 seconds
Started Jul 16 07:06:18 PM PDT 24
Finished Jul 16 07:06:30 PM PDT 24
Peak memory 211340 kb
Host smart-5ed4cf12-ad53-48b1-8dab-0a645a0c947e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3232163121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3232163121
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3276723768
Short name T23
Test name
Test status
Simulation time 1387020862 ps
CPU time 52.1 seconds
Started Jul 16 07:06:00 PM PDT 24
Finished Jul 16 07:06:53 PM PDT 24
Peak memory 233772 kb
Host smart-54aef6dd-ad24-497c-9383-ef875aef130e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276723768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3276723768
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2033472127
Short name T46
Test name
Test status
Simulation time 13676331298 ps
CPU time 27.96 seconds
Started Jul 16 07:06:02 PM PDT 24
Finished Jul 16 07:06:31 PM PDT 24
Peak memory 213996 kb
Host smart-19cf2cf9-e086-4759-b6da-e29e5dfcc911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033472127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2033472127
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.759603395
Short name T279
Test name
Test status
Simulation time 3883853667 ps
CPU time 48.22 seconds
Started Jul 16 07:06:17 PM PDT 24
Finished Jul 16 07:07:09 PM PDT 24
Peak memory 216124 kb
Host smart-09c63809-1bc5-48c3-8303-2e02e990d99b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759603395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.759603395
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1157879195
Short name T51
Test name
Test status
Simulation time 19285496202 ps
CPU time 610.61 seconds
Started Jul 16 07:05:59 PM PDT 24
Finished Jul 16 07:16:11 PM PDT 24
Peak memory 224128 kb
Host smart-dd1a8fae-2681-4f2f-bf6d-d1201f732f4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157879195 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1157879195
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3591912881
Short name T66
Test name
Test status
Simulation time 2095108269 ps
CPU time 16.63 seconds
Started Jul 16 07:06:41 PM PDT 24
Finished Jul 16 07:06:59 PM PDT 24
Peak memory 211368 kb
Host smart-9f8bfe2a-6bb1-401a-a82f-a18a02b7ce8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591912881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3591912881
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.875926262
Short name T317
Test name
Test status
Simulation time 24158293979 ps
CPU time 233.85 seconds
Started Jul 16 07:06:57 PM PDT 24
Finished Jul 16 07:10:52 PM PDT 24
Peak memory 225272 kb
Host smart-bd8ffb8c-d14a-4216-8bdb-9d450967ea39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875926262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.875926262
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.138561937
Short name T4
Test name
Test status
Simulation time 24425820845 ps
CPU time 25.96 seconds
Started Jul 16 07:06:39 PM PDT 24
Finished Jul 16 07:07:07 PM PDT 24
Peak memory 212216 kb
Host smart-713f99e0-6e58-46ea-8617-d56d192243d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138561937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.138561937
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2059013555
Short name T202
Test name
Test status
Simulation time 5325023887 ps
CPU time 12.2 seconds
Started Jul 16 07:06:42 PM PDT 24
Finished Jul 16 07:06:56 PM PDT 24
Peak memory 211380 kb
Host smart-17cfa4ae-c1c6-4d09-b12e-d9b4b8b9ca0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059013555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2059013555
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2908047025
Short name T125
Test name
Test status
Simulation time 5259680293 ps
CPU time 25.86 seconds
Started Jul 16 07:06:41 PM PDT 24
Finished Jul 16 07:07:09 PM PDT 24
Peak memory 214076 kb
Host smart-58a1f611-a4ac-4082-b483-685e11baa2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908047025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2908047025
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3792837209
Short name T170
Test name
Test status
Simulation time 352609090 ps
CPU time 11.7 seconds
Started Jul 16 07:06:49 PM PDT 24
Finished Jul 16 07:07:01 PM PDT 24
Peak memory 212140 kb
Host smart-e7d5b9b7-a5c7-4110-b899-64c668c7025b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792837209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3792837209
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3943841149
Short name T64
Test name
Test status
Simulation time 9286275709 ps
CPU time 8.96 seconds
Started Jul 16 07:06:49 PM PDT 24
Finished Jul 16 07:06:58 PM PDT 24
Peak memory 211384 kb
Host smart-a2d68379-c047-4fb1-8b4c-96c6a2cf6e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943841149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3943841149
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2699286133
Short name T364
Test name
Test status
Simulation time 17665204220 ps
CPU time 222.37 seconds
Started Jul 16 07:06:47 PM PDT 24
Finished Jul 16 07:10:31 PM PDT 24
Peak memory 240772 kb
Host smart-23a18df3-451c-444d-b4fe-122b67873529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699286133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2699286133
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2669130112
Short name T353
Test name
Test status
Simulation time 4985071771 ps
CPU time 24.22 seconds
Started Jul 16 07:06:51 PM PDT 24
Finished Jul 16 07:07:16 PM PDT 24
Peak memory 212488 kb
Host smart-e2eecd8e-fd3b-4d8a-b722-9390374e2f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669130112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2669130112
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.4213928310
Short name T160
Test name
Test status
Simulation time 1413178727 ps
CPU time 13.38 seconds
Started Jul 16 07:07:01 PM PDT 24
Finished Jul 16 07:07:16 PM PDT 24
Peak memory 211344 kb
Host smart-bf19b371-7512-4121-b0c4-ef9c36e24719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213928310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.4213928310
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4005781555
Short name T81
Test name
Test status
Simulation time 1974217104 ps
CPU time 27.21 seconds
Started Jul 16 07:06:59 PM PDT 24
Finished Jul 16 07:07:27 PM PDT 24
Peak memory 212992 kb
Host smart-ca5a36e6-dc49-42ad-a3c1-fe011c3d0b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005781555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4005781555
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.504500830
Short name T243
Test name
Test status
Simulation time 17154894338 ps
CPU time 40.94 seconds
Started Jul 16 07:06:47 PM PDT 24
Finished Jul 16 07:07:29 PM PDT 24
Peak memory 216684 kb
Host smart-67601fab-cdaf-410c-bad2-3e456b5b6b8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504500830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.504500830
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1493999777
Short name T246
Test name
Test status
Simulation time 2304040249 ps
CPU time 11.02 seconds
Started Jul 16 07:06:52 PM PDT 24
Finished Jul 16 07:07:05 PM PDT 24
Peak memory 211396 kb
Host smart-3d3e7d95-a518-476d-a9e3-cd08b8dd2f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493999777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1493999777
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1440539783
Short name T169
Test name
Test status
Simulation time 39082535112 ps
CPU time 213.33 seconds
Started Jul 16 07:06:53 PM PDT 24
Finished Jul 16 07:10:28 PM PDT 24
Peak memory 233732 kb
Host smart-5798fe02-0def-42a1-a325-c894312f089c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440539783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1440539783
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2732882290
Short name T282
Test name
Test status
Simulation time 168271776 ps
CPU time 9.39 seconds
Started Jul 16 07:06:51 PM PDT 24
Finished Jul 16 07:07:02 PM PDT 24
Peak memory 211976 kb
Host smart-361364e1-9819-4964-9527-f9acbb966587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732882290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2732882290
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1794367265
Short name T121
Test name
Test status
Simulation time 1570096748 ps
CPU time 14.71 seconds
Started Jul 16 07:07:01 PM PDT 24
Finished Jul 16 07:07:17 PM PDT 24
Peak memory 211344 kb
Host smart-93d539b9-f970-4f08-b551-58135512bc43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794367265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1794367265
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2899749168
Short name T312
Test name
Test status
Simulation time 1283108731 ps
CPU time 10.05 seconds
Started Jul 16 07:06:46 PM PDT 24
Finished Jul 16 07:06:58 PM PDT 24
Peak memory 213780 kb
Host smart-8a4e7940-9b0a-42df-bbbd-9a4ce608d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899749168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2899749168
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1048196066
Short name T143
Test name
Test status
Simulation time 1897380076 ps
CPU time 20.48 seconds
Started Jul 16 07:06:49 PM PDT 24
Finished Jul 16 07:07:10 PM PDT 24
Peak memory 211980 kb
Host smart-4daf04d2-2f90-42b8-b633-f76ddea3212c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048196066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1048196066
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3394523516
Short name T163
Test name
Test status
Simulation time 3095265804 ps
CPU time 13.11 seconds
Started Jul 16 07:06:52 PM PDT 24
Finished Jul 16 07:07:07 PM PDT 24
Peak memory 211352 kb
Host smart-4fbb118d-a578-4b17-8e18-0e0c7115ebc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394523516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3394523516
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4218051670
Short name T3
Test name
Test status
Simulation time 8020585883 ps
CPU time 230.66 seconds
Started Jul 16 07:06:51 PM PDT 24
Finished Jul 16 07:10:42 PM PDT 24
Peak memory 235100 kb
Host smart-21af096e-ca5c-4c73-8092-97476cba2f55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218051670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4218051670
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1636312631
Short name T285
Test name
Test status
Simulation time 8142951864 ps
CPU time 33.37 seconds
Started Jul 16 07:06:51 PM PDT 24
Finished Jul 16 07:07:25 PM PDT 24
Peak memory 212560 kb
Host smart-58e8b598-774d-4f96-9b64-1afedcca536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636312631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1636312631
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1963991080
Short name T336
Test name
Test status
Simulation time 193919774 ps
CPU time 10.26 seconds
Started Jul 16 07:06:52 PM PDT 24
Finished Jul 16 07:07:03 PM PDT 24
Peak memory 213704 kb
Host smart-48af0b3d-e54e-46f5-83e1-26e056d4537c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963991080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1963991080
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2842941319
Short name T189
Test name
Test status
Simulation time 136968564 ps
CPU time 6.83 seconds
Started Jul 16 07:06:57 PM PDT 24
Finished Jul 16 07:07:05 PM PDT 24
Peak memory 211556 kb
Host smart-3ebb7e18-763c-4b98-b6ef-c92cfcc5c8b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842941319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2842941319
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3036275000
Short name T155
Test name
Test status
Simulation time 2943185734 ps
CPU time 9.36 seconds
Started Jul 16 07:06:52 PM PDT 24
Finished Jul 16 07:07:03 PM PDT 24
Peak memory 211368 kb
Host smart-cc0d2464-3197-41c5-927c-7bfc4ceaaeb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036275000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3036275000
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3480725342
Short name T207
Test name
Test status
Simulation time 67254935696 ps
CPU time 264.8 seconds
Started Jul 16 07:06:54 PM PDT 24
Finished Jul 16 07:11:20 PM PDT 24
Peak memory 237808 kb
Host smart-37014da5-4be4-4dff-81b2-ebf799d26065
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480725342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3480725342
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.928890155
Short name T251
Test name
Test status
Simulation time 346045547 ps
CPU time 9.93 seconds
Started Jul 16 07:06:50 PM PDT 24
Finished Jul 16 07:07:01 PM PDT 24
Peak memory 214352 kb
Host smart-0e7ba6c8-570b-4479-8919-ff7a7fce07a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928890155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.928890155
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.997254121
Short name T352
Test name
Test status
Simulation time 5801176596 ps
CPU time 14.3 seconds
Started Jul 16 07:07:07 PM PDT 24
Finished Jul 16 07:07:24 PM PDT 24
Peak memory 211444 kb
Host smart-4df529dd-649e-4248-8883-de1d937d16ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997254121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.997254121
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.425116811
Short name T223
Test name
Test status
Simulation time 343379401 ps
CPU time 9.83 seconds
Started Jul 16 07:06:53 PM PDT 24
Finished Jul 16 07:07:04 PM PDT 24
Peak memory 213292 kb
Host smart-ddf663fb-5f0f-4df0-9812-daf09b37c7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425116811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.425116811
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3327786063
Short name T69
Test name
Test status
Simulation time 22871606011 ps
CPU time 85.33 seconds
Started Jul 16 07:06:55 PM PDT 24
Finished Jul 16 07:08:21 PM PDT 24
Peak memory 218208 kb
Host smart-f9b09a2b-ef37-417c-bac9-bd62ab6c5268
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327786063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3327786063
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.344834787
Short name T328
Test name
Test status
Simulation time 1664071077 ps
CPU time 13.36 seconds
Started Jul 16 07:06:59 PM PDT 24
Finished Jul 16 07:07:13 PM PDT 24
Peak memory 211356 kb
Host smart-b75e3e9e-9fe0-4cce-ac18-13e3290c2d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344834787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.344834787
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3735245571
Short name T348
Test name
Test status
Simulation time 77279550387 ps
CPU time 163.06 seconds
Started Jul 16 07:07:01 PM PDT 24
Finished Jul 16 07:09:46 PM PDT 24
Peak memory 227828 kb
Host smart-005e0bb9-43c7-4f38-ab9a-8a73c36a8f0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735245571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3735245571
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.642522892
Short name T194
Test name
Test status
Simulation time 12725959735 ps
CPU time 17.24 seconds
Started Jul 16 07:06:51 PM PDT 24
Finished Jul 16 07:07:09 PM PDT 24
Peak memory 214176 kb
Host smart-5f04c748-80e3-4dbd-9540-a89cdea73fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642522892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.642522892
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2259663905
Short name T103
Test name
Test status
Simulation time 253696577 ps
CPU time 5.4 seconds
Started Jul 16 07:07:06 PM PDT 24
Finished Jul 16 07:07:13 PM PDT 24
Peak memory 211340 kb
Host smart-88133cc3-6c5b-401a-b700-23ce98fc43ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2259663905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2259663905
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1293125030
Short name T294
Test name
Test status
Simulation time 2737132007 ps
CPU time 35.04 seconds
Started Jul 16 07:07:03 PM PDT 24
Finished Jul 16 07:07:39 PM PDT 24
Peak memory 213384 kb
Host smart-18d157bb-3e19-45a2-a855-9ccff5c27db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293125030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1293125030
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1672080791
Short name T80
Test name
Test status
Simulation time 8568556184 ps
CPU time 25.23 seconds
Started Jul 16 07:07:01 PM PDT 24
Finished Jul 16 07:07:28 PM PDT 24
Peak memory 216112 kb
Host smart-11fcfaab-95bc-4bec-834e-144ff12655d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672080791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1672080791
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.4054303217
Short name T68
Test name
Test status
Simulation time 2466928190 ps
CPU time 8.56 seconds
Started Jul 16 07:07:01 PM PDT 24
Finished Jul 16 07:07:11 PM PDT 24
Peak memory 211364 kb
Host smart-a3374caf-5247-41fd-b0be-e092abecfdae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054303217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4054303217
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2189162775
Short name T311
Test name
Test status
Simulation time 2584384360 ps
CPU time 91.14 seconds
Started Jul 16 07:06:50 PM PDT 24
Finished Jul 16 07:08:22 PM PDT 24
Peak memory 237700 kb
Host smart-51cde5d4-95ea-4761-9b78-0437dbf82f14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189162775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2189162775
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3656186800
Short name T26
Test name
Test status
Simulation time 2318735072 ps
CPU time 23.84 seconds
Started Jul 16 07:06:53 PM PDT 24
Finished Jul 16 07:07:18 PM PDT 24
Peak memory 211880 kb
Host smart-9922703a-a622-416d-abd2-16888db0247c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656186800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3656186800
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1147254258
Short name T286
Test name
Test status
Simulation time 4141889906 ps
CPU time 11.67 seconds
Started Jul 16 07:07:02 PM PDT 24
Finished Jul 16 07:07:15 PM PDT 24
Peak memory 211440 kb
Host smart-c65f5eef-f1ac-42e4-910c-eb61504b6d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1147254258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1147254258
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3339497537
Short name T322
Test name
Test status
Simulation time 7350366828 ps
CPU time 31.75 seconds
Started Jul 16 07:07:04 PM PDT 24
Finished Jul 16 07:07:38 PM PDT 24
Peak memory 213832 kb
Host smart-eda3982a-7b22-40ac-b3b2-12c01992f93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339497537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3339497537
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2958710466
Short name T152
Test name
Test status
Simulation time 6387547375 ps
CPU time 60.02 seconds
Started Jul 16 07:06:51 PM PDT 24
Finished Jul 16 07:07:53 PM PDT 24
Peak memory 216244 kb
Host smart-165f1d95-f4f9-432a-a5ed-b227345c4b04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958710466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2958710466
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2967211616
Short name T226
Test name
Test status
Simulation time 6862890460 ps
CPU time 15.41 seconds
Started Jul 16 07:06:53 PM PDT 24
Finished Jul 16 07:07:10 PM PDT 24
Peak memory 211416 kb
Host smart-9b0e89ad-6673-4a07-9dda-31f6140c210e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967211616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2967211616
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2785660141
Short name T272
Test name
Test status
Simulation time 21085108921 ps
CPU time 31.22 seconds
Started Jul 16 07:07:07 PM PDT 24
Finished Jul 16 07:07:40 PM PDT 24
Peak memory 212420 kb
Host smart-38978f7b-3fc4-45f3-b9ed-78a50a82c96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785660141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2785660141
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4087513240
Short name T33
Test name
Test status
Simulation time 736288345 ps
CPU time 9.6 seconds
Started Jul 16 07:06:57 PM PDT 24
Finished Jul 16 07:07:07 PM PDT 24
Peak memory 211400 kb
Host smart-4a41cb1b-01ec-44ac-8f23-d59fb0049151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087513240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4087513240
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3324675038
Short name T356
Test name
Test status
Simulation time 1653154649 ps
CPU time 20.11 seconds
Started Jul 16 07:07:03 PM PDT 24
Finished Jul 16 07:07:24 PM PDT 24
Peak memory 213856 kb
Host smart-742a19e9-2ff9-4ae4-b490-f6893f64f4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324675038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3324675038
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1424703855
Short name T293
Test name
Test status
Simulation time 1949533128 ps
CPU time 22.37 seconds
Started Jul 16 07:06:50 PM PDT 24
Finished Jul 16 07:07:14 PM PDT 24
Peak memory 214172 kb
Host smart-04d5650a-1275-4ecb-8b84-d24145391c15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424703855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1424703855
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3125478391
Short name T191
Test name
Test status
Simulation time 5743580033 ps
CPU time 12.85 seconds
Started Jul 16 07:06:54 PM PDT 24
Finished Jul 16 07:07:08 PM PDT 24
Peak memory 211320 kb
Host smart-8aafce3c-3552-4b31-826c-3131558e5bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125478391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3125478391
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.135060875
Short name T252
Test name
Test status
Simulation time 38086419819 ps
CPU time 191.9 seconds
Started Jul 16 07:06:53 PM PDT 24
Finished Jul 16 07:10:07 PM PDT 24
Peak memory 237816 kb
Host smart-d6f199f6-d862-47bb-b72f-2d377cb8e87d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135060875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.135060875
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.838475135
Short name T171
Test name
Test status
Simulation time 5548921998 ps
CPU time 27.02 seconds
Started Jul 16 07:06:55 PM PDT 24
Finished Jul 16 07:07:23 PM PDT 24
Peak memory 212184 kb
Host smart-d4c9feec-a90c-4a90-85a0-453cea5f653f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838475135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.838475135
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3502301562
Short name T11
Test name
Test status
Simulation time 2117376340 ps
CPU time 11.64 seconds
Started Jul 16 07:06:52 PM PDT 24
Finished Jul 16 07:07:05 PM PDT 24
Peak memory 211372 kb
Host smart-d003e5a5-a6ca-44e3-9bf2-2d43769ad3d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502301562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3502301562
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.177532558
Short name T337
Test name
Test status
Simulation time 4037686598 ps
CPU time 37.2 seconds
Started Jul 16 07:06:57 PM PDT 24
Finished Jul 16 07:07:34 PM PDT 24
Peak memory 213388 kb
Host smart-8eaaeb6a-86ee-4823-82d3-145c1ce1851b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177532558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.177532558
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2584640012
Short name T144
Test name
Test status
Simulation time 3709518876 ps
CPU time 31.12 seconds
Started Jul 16 07:06:52 PM PDT 24
Finished Jul 16 07:07:24 PM PDT 24
Peak memory 214004 kb
Host smart-3af841c7-befe-490e-9703-07ce2dd2c428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584640012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2584640012
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2419947897
Short name T258
Test name
Test status
Simulation time 9716068486 ps
CPU time 152.61 seconds
Started Jul 16 07:07:06 PM PDT 24
Finished Jul 16 07:09:41 PM PDT 24
Peak memory 237796 kb
Host smart-54f1a19e-f052-4b7e-8f70-f76bcac92467
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419947897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2419947897
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1557364401
Short name T45
Test name
Test status
Simulation time 3274327509 ps
CPU time 28.4 seconds
Started Jul 16 07:07:24 PM PDT 24
Finished Jul 16 07:07:54 PM PDT 24
Peak memory 211440 kb
Host smart-55300d86-de50-4483-a980-7c9e61baf60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557364401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1557364401
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.160021285
Short name T174
Test name
Test status
Simulation time 1829536366 ps
CPU time 7.62 seconds
Started Jul 16 07:07:04 PM PDT 24
Finished Jul 16 07:07:13 PM PDT 24
Peak memory 211384 kb
Host smart-e7c95a3b-bfa7-46e8-be12-889ffa3e3ce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160021285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.160021285
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3487306774
Short name T56
Test name
Test status
Simulation time 194342556 ps
CPU time 10.48 seconds
Started Jul 16 07:06:52 PM PDT 24
Finished Jul 16 07:07:04 PM PDT 24
Peak memory 213440 kb
Host smart-e9937753-f562-4256-8cff-361ea3ff7e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487306774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3487306774
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.471152125
Short name T360
Test name
Test status
Simulation time 2855108986 ps
CPU time 47.88 seconds
Started Jul 16 07:07:08 PM PDT 24
Finished Jul 16 07:07:58 PM PDT 24
Peak memory 215536 kb
Host smart-810d836b-6dda-4894-96ed-d345dbf0b51b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471152125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.471152125
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3860813405
Short name T136
Test name
Test status
Simulation time 2061387575 ps
CPU time 15.21 seconds
Started Jul 16 07:06:16 PM PDT 24
Finished Jul 16 07:06:35 PM PDT 24
Peak memory 211292 kb
Host smart-fc4ae4c4-0185-435a-b18b-af0f30c67acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860813405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3860813405
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1600587772
Short name T118
Test name
Test status
Simulation time 81131645782 ps
CPU time 181.67 seconds
Started Jul 16 07:06:04 PM PDT 24
Finished Jul 16 07:09:07 PM PDT 24
Peak memory 237784 kb
Host smart-f11e4746-6c94-44fb-90fc-0df163f50349
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600587772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1600587772
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.395833092
Short name T319
Test name
Test status
Simulation time 692954461 ps
CPU time 9.44 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:06:27 PM PDT 24
Peak memory 212080 kb
Host smart-41c43b51-efd5-42ba-bc07-1235b27adfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395833092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.395833092
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2503159486
Short name T324
Test name
Test status
Simulation time 425184403 ps
CPU time 5.62 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:06:19 PM PDT 24
Peak memory 211380 kb
Host smart-761137c5-88b3-4682-9167-a8a0834b6c11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2503159486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2503159486
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1953391012
Short name T280
Test name
Test status
Simulation time 1093832822 ps
CPU time 18.09 seconds
Started Jul 16 07:06:03 PM PDT 24
Finished Jul 16 07:06:22 PM PDT 24
Peak memory 213080 kb
Host smart-b0c8f9b1-9d32-46c3-884e-468287b1cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953391012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1953391012
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1939474179
Short name T355
Test name
Test status
Simulation time 3366858473 ps
CPU time 38.98 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:06:54 PM PDT 24
Peak memory 213700 kb
Host smart-766e278b-2fe7-4590-9a63-a9279604ac6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939474179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1939474179
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3538113690
Short name T9
Test name
Test status
Simulation time 174813111 ps
CPU time 4.18 seconds
Started Jul 16 07:06:12 PM PDT 24
Finished Jul 16 07:06:17 PM PDT 24
Peak memory 211340 kb
Host smart-af33208e-3e9a-4cf5-ad20-adbb2268b7a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538113690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3538113690
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1796259085
Short name T41
Test name
Test status
Simulation time 31525061756 ps
CPU time 151.48 seconds
Started Jul 16 07:05:58 PM PDT 24
Finished Jul 16 07:08:31 PM PDT 24
Peak memory 237840 kb
Host smart-5bc9459f-7259-4ed8-8934-f008b5a80b8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796259085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1796259085
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2747295345
Short name T203
Test name
Test status
Simulation time 1787619693 ps
CPU time 11.2 seconds
Started Jul 16 07:06:06 PM PDT 24
Finished Jul 16 07:06:19 PM PDT 24
Peak memory 212248 kb
Host smart-9a986370-9778-49e5-9624-4dbfe5ff8bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747295345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2747295345
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3782216978
Short name T362
Test name
Test status
Simulation time 1726432589 ps
CPU time 14.85 seconds
Started Jul 16 07:06:00 PM PDT 24
Finished Jul 16 07:06:16 PM PDT 24
Peak memory 211388 kb
Host smart-01b51356-b825-409d-b0ec-7bfaf82d13a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782216978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3782216978
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2271900738
Short name T34
Test name
Test status
Simulation time 1127712890 ps
CPU time 11.54 seconds
Started Jul 16 07:06:01 PM PDT 24
Finished Jul 16 07:06:14 PM PDT 24
Peak memory 213516 kb
Host smart-30ccce30-a981-4a0d-88f0-11e944abd1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271900738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2271900738
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.20479794
Short name T138
Test name
Test status
Simulation time 9940331976 ps
CPU time 36.86 seconds
Started Jul 16 07:06:03 PM PDT 24
Finished Jul 16 07:06:41 PM PDT 24
Peak memory 217484 kb
Host smart-3710c809-0042-4621-92ab-cbc63100b956
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20479794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.rom_ctrl_stress_all.20479794
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1516694565
Short name T37
Test name
Test status
Simulation time 1238902836 ps
CPU time 12.02 seconds
Started Jul 16 07:06:02 PM PDT 24
Finished Jul 16 07:06:16 PM PDT 24
Peak memory 211376 kb
Host smart-7fb0b7ec-ca56-48ca-8da6-aba324648c35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516694565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1516694565
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1790590949
Short name T327
Test name
Test status
Simulation time 31467524394 ps
CPU time 314.87 seconds
Started Jul 16 07:06:00 PM PDT 24
Finished Jul 16 07:11:16 PM PDT 24
Peak memory 237808 kb
Host smart-433e1048-ba7e-4cdb-8a79-418779f64d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790590949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1790590949
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1606043037
Short name T173
Test name
Test status
Simulation time 168800735 ps
CPU time 9.58 seconds
Started Jul 16 07:06:07 PM PDT 24
Finished Jul 16 07:06:18 PM PDT 24
Peak memory 211832 kb
Host smart-a48f0cba-cce5-4bb9-8e35-fa3e6619e566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606043037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1606043037
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2674379973
Short name T343
Test name
Test status
Simulation time 3299014768 ps
CPU time 7.58 seconds
Started Jul 16 07:06:13 PM PDT 24
Finished Jul 16 07:06:22 PM PDT 24
Peak memory 211404 kb
Host smart-b1c8c9fe-208a-44e5-b2e4-8c7b802083d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674379973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2674379973
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2008778719
Short name T277
Test name
Test status
Simulation time 22235266664 ps
CPU time 27.76 seconds
Started Jul 16 07:06:06 PM PDT 24
Finished Jul 16 07:06:35 PM PDT 24
Peak memory 214628 kb
Host smart-6cef0897-7318-4d95-a93d-115fd02ec00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008778719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2008778719
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.848251695
Short name T185
Test name
Test status
Simulation time 46286552422 ps
CPU time 113.44 seconds
Started Jul 16 07:06:07 PM PDT 24
Finished Jul 16 07:08:02 PM PDT 24
Peak memory 217824 kb
Host smart-b37cbe6d-0b69-4f2d-ac93-b8ce9057e466
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848251695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.848251695
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1289846007
Short name T214
Test name
Test status
Simulation time 2122056084 ps
CPU time 16.44 seconds
Started Jul 16 07:06:09 PM PDT 24
Finished Jul 16 07:06:27 PM PDT 24
Peak memory 211304 kb
Host smart-6eaeaa71-3596-4ab0-9fec-8df21e28ed22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289846007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1289846007
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2895062574
Short name T249
Test name
Test status
Simulation time 7019853044 ps
CPU time 121.63 seconds
Started Jul 16 07:06:01 PM PDT 24
Finished Jul 16 07:08:04 PM PDT 24
Peak memory 224668 kb
Host smart-727bd07b-e255-49b5-ba4d-4695ce8d968f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895062574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2895062574
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4284493256
Short name T236
Test name
Test status
Simulation time 170514462 ps
CPU time 9.35 seconds
Started Jul 16 07:06:16 PM PDT 24
Finished Jul 16 07:06:29 PM PDT 24
Peak memory 212112 kb
Host smart-933e253f-a9d7-4aec-874c-42221ef9fc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284493256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4284493256
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4031150958
Short name T119
Test name
Test status
Simulation time 1619474656 ps
CPU time 14.03 seconds
Started Jul 16 07:06:01 PM PDT 24
Finished Jul 16 07:06:17 PM PDT 24
Peak memory 211328 kb
Host smart-39505ed4-4a5e-4998-86ea-5242a6d9a043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031150958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4031150958
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3412514012
Short name T231
Test name
Test status
Simulation time 13525194136 ps
CPU time 39.32 seconds
Started Jul 16 07:06:05 PM PDT 24
Finished Jul 16 07:06:45 PM PDT 24
Peak memory 213924 kb
Host smart-8b6a0ede-cc4d-498e-824a-98bd6015a6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412514012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3412514012
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2124826856
Short name T281
Test name
Test status
Simulation time 577928121 ps
CPU time 12.13 seconds
Started Jul 16 07:06:08 PM PDT 24
Finished Jul 16 07:06:21 PM PDT 24
Peak memory 212276 kb
Host smart-d7f4fa17-f999-4bf7-bf27-df63c0d69e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124826856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2124826856
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2842988529
Short name T15
Test name
Test status
Simulation time 54217836482 ps
CPU time 1949.81 seconds
Started Jul 16 07:06:08 PM PDT 24
Finished Jul 16 07:38:39 PM PDT 24
Peak memory 225396 kb
Host smart-47dfbda1-fa3d-4a4f-b0cc-8b72c3193990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842988529 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2842988529
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2534227509
Short name T184
Test name
Test status
Simulation time 852744987 ps
CPU time 7.89 seconds
Started Jul 16 07:06:15 PM PDT 24
Finished Jul 16 07:06:26 PM PDT 24
Peak memory 211336 kb
Host smart-d041ee57-f803-417b-9f40-377e06467f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534227509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2534227509
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2874202071
Short name T153
Test name
Test status
Simulation time 93675251027 ps
CPU time 197.82 seconds
Started Jul 16 07:05:59 PM PDT 24
Finished Jul 16 07:09:18 PM PDT 24
Peak memory 233476 kb
Host smart-5d379a2f-086e-440c-9b78-4bd7a5d7bd69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874202071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2874202071
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2067238999
Short name T224
Test name
Test status
Simulation time 172030210 ps
CPU time 9.78 seconds
Started Jul 16 07:06:01 PM PDT 24
Finished Jul 16 07:06:12 PM PDT 24
Peak memory 211892 kb
Host smart-ea1d9d7d-4cfe-4a97-b289-ed6bfaa7b01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067238999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2067238999
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3976991809
Short name T21
Test name
Test status
Simulation time 393952460 ps
CPU time 6.23 seconds
Started Jul 16 07:06:14 PM PDT 24
Finished Jul 16 07:06:22 PM PDT 24
Peak memory 211404 kb
Host smart-63924ce0-5e4c-4a75-86f2-a2eec200da78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976991809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3976991809
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1227482274
Short name T123
Test name
Test status
Simulation time 18474830230 ps
CPU time 27.25 seconds
Started Jul 16 07:06:10 PM PDT 24
Finished Jul 16 07:06:38 PM PDT 24
Peak memory 213888 kb
Host smart-d495c7cd-d362-4bec-9713-e4ab49d958b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227482274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1227482274
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1462176067
Short name T12
Test name
Test status
Simulation time 662704557 ps
CPU time 14.29 seconds
Started Jul 16 07:06:01 PM PDT 24
Finished Jul 16 07:06:17 PM PDT 24
Peak memory 211428 kb
Host smart-168a3ab7-61df-4f11-8641-d236e36fa3bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462176067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1462176067
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2452046783
Short name T53
Test name
Test status
Simulation time 193899010694 ps
CPU time 1666.06 seconds
Started Jul 16 07:06:18 PM PDT 24
Finished Jul 16 07:34:07 PM PDT 24
Peak memory 235820 kb
Host smart-f5d2557c-5d90-4e14-8398-63e4611f9223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452046783 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2452046783
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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