Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.27 96.89 92.28 97.67 100.00 98.62 97.30 98.14


Total test records in report: 469
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T297 /workspace/coverage/default/38.rom_ctrl_smoke.1850026341 Jul 17 07:02:30 PM PDT 24 Jul 17 07:02:47 PM PDT 24 187145595 ps
T298 /workspace/coverage/default/37.rom_ctrl_alert_test.1364973473 Jul 17 07:02:17 PM PDT 24 Jul 17 07:02:26 PM PDT 24 944751642 ps
T299 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3318254030 Jul 17 07:01:59 PM PDT 24 Jul 17 07:02:20 PM PDT 24 6631349081 ps
T300 /workspace/coverage/default/4.rom_ctrl_smoke.3791242251 Jul 17 07:01:42 PM PDT 24 Jul 17 07:02:15 PM PDT 24 3173574005 ps
T301 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1459715608 Jul 17 07:02:27 PM PDT 24 Jul 17 07:02:56 PM PDT 24 2752937851 ps
T302 /workspace/coverage/default/31.rom_ctrl_stress_all.1079353195 Jul 17 07:01:51 PM PDT 24 Jul 17 07:03:08 PM PDT 24 5616942974 ps
T303 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1597804400 Jul 17 07:02:29 PM PDT 24 Jul 17 07:09:18 PM PDT 24 166469541547 ps
T304 /workspace/coverage/default/37.rom_ctrl_smoke.3544192710 Jul 17 07:02:29 PM PDT 24 Jul 17 07:03:05 PM PDT 24 15006578204 ps
T305 /workspace/coverage/default/46.rom_ctrl_alert_test.1524785908 Jul 17 07:02:30 PM PDT 24 Jul 17 07:02:43 PM PDT 24 1652696683 ps
T306 /workspace/coverage/default/35.rom_ctrl_smoke.1611349654 Jul 17 07:02:00 PM PDT 24 Jul 17 07:02:25 PM PDT 24 3394899007 ps
T307 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.366528511 Jul 17 07:01:59 PM PDT 24 Jul 17 07:02:15 PM PDT 24 1045473632 ps
T308 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2722764401 Jul 17 07:01:53 PM PDT 24 Jul 17 07:02:06 PM PDT 24 2694918378 ps
T309 /workspace/coverage/default/12.rom_ctrl_stress_all.1663444284 Jul 17 07:01:58 PM PDT 24 Jul 17 07:03:46 PM PDT 24 44433692135 ps
T310 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2601998311 Jul 17 07:02:00 PM PDT 24 Jul 17 07:02:36 PM PDT 24 3020853153 ps
T311 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2674612919 Jul 17 07:02:03 PM PDT 24 Jul 17 07:10:26 PM PDT 24 46085629210 ps
T312 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1449279103 Jul 17 07:02:32 PM PDT 24 Jul 17 07:02:53 PM PDT 24 3513548553 ps
T313 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1881102301 Jul 17 07:02:00 PM PDT 24 Jul 17 07:02:19 PM PDT 24 177148251 ps
T314 /workspace/coverage/default/20.rom_ctrl_stress_all.426610175 Jul 17 07:01:59 PM PDT 24 Jul 17 07:02:35 PM PDT 24 491420505 ps
T315 /workspace/coverage/default/9.rom_ctrl_alert_test.1855133210 Jul 17 07:01:54 PM PDT 24 Jul 17 07:02:09 PM PDT 24 1065492881 ps
T316 /workspace/coverage/default/8.rom_ctrl_smoke.120642909 Jul 17 07:01:54 PM PDT 24 Jul 17 07:02:32 PM PDT 24 3856684936 ps
T317 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2951152227 Jul 17 07:01:51 PM PDT 24 Jul 17 07:06:02 PM PDT 24 139489556103 ps
T318 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3391768433 Jul 17 07:01:57 PM PDT 24 Jul 17 07:02:16 PM PDT 24 922512882 ps
T319 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3835127584 Jul 17 07:01:56 PM PDT 24 Jul 17 07:02:24 PM PDT 24 7202149482 ps
T320 /workspace/coverage/default/36.rom_ctrl_stress_all.821622458 Jul 17 07:01:57 PM PDT 24 Jul 17 07:04:43 PM PDT 24 69622032253 ps
T321 /workspace/coverage/default/21.rom_ctrl_stress_all.211129169 Jul 17 07:02:03 PM PDT 24 Jul 17 07:03:28 PM PDT 24 5966627244 ps
T322 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4283968495 Jul 17 07:01:55 PM PDT 24 Jul 17 07:02:16 PM PDT 24 3339842500 ps
T323 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3379909235 Jul 17 07:02:01 PM PDT 24 Jul 17 07:07:19 PM PDT 24 28546459164 ps
T324 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2008136 Jul 17 07:01:57 PM PDT 24 Jul 17 07:02:37 PM PDT 24 15633754860 ps
T325 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1487763240 Jul 17 07:01:58 PM PDT 24 Jul 17 07:05:36 PM PDT 24 27251490945 ps
T326 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2696708693 Jul 17 07:01:55 PM PDT 24 Jul 17 07:02:27 PM PDT 24 2788395210 ps
T327 /workspace/coverage/default/23.rom_ctrl_smoke.500615351 Jul 17 07:01:56 PM PDT 24 Jul 17 07:02:41 PM PDT 24 7389765384 ps
T328 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1918751725 Jul 17 07:02:32 PM PDT 24 Jul 17 07:08:59 PM PDT 24 11642233094 ps
T329 /workspace/coverage/default/49.rom_ctrl_smoke.1192942457 Jul 17 07:02:32 PM PDT 24 Jul 17 07:02:59 PM PDT 24 4991257197 ps
T330 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3473183604 Jul 17 07:01:53 PM PDT 24 Jul 17 07:03:41 PM PDT 24 94341590124 ps
T331 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1951513898 Jul 17 07:02:29 PM PDT 24 Jul 17 07:02:42 PM PDT 24 586681896 ps
T332 /workspace/coverage/default/2.rom_ctrl_stress_all.2631868462 Jul 17 07:01:51 PM PDT 24 Jul 17 07:02:09 PM PDT 24 3572870713 ps
T333 /workspace/coverage/default/17.rom_ctrl_smoke.710983054 Jul 17 07:02:00 PM PDT 24 Jul 17 07:02:19 PM PDT 24 807361792 ps
T334 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1051084440 Jul 17 07:01:59 PM PDT 24 Jul 17 08:14:00 PM PDT 24 100472246216 ps
T335 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.860030517 Jul 17 07:01:58 PM PDT 24 Jul 17 07:02:20 PM PDT 24 8005422341 ps
T336 /workspace/coverage/default/17.rom_ctrl_alert_test.1627564380 Jul 17 07:01:42 PM PDT 24 Jul 17 07:01:55 PM PDT 24 1237806324 ps
T337 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3584395853 Jul 17 07:01:55 PM PDT 24 Jul 17 07:02:35 PM PDT 24 8040110026 ps
T338 /workspace/coverage/default/33.rom_ctrl_stress_all.209805315 Jul 17 07:01:57 PM PDT 24 Jul 17 07:02:35 PM PDT 24 4724649202 ps
T339 /workspace/coverage/default/47.rom_ctrl_alert_test.1831800901 Jul 17 07:02:30 PM PDT 24 Jul 17 07:02:49 PM PDT 24 1317209017 ps
T340 /workspace/coverage/default/10.rom_ctrl_stress_all.1184419466 Jul 17 07:01:56 PM PDT 24 Jul 17 07:02:45 PM PDT 24 7613637492 ps
T341 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1967341340 Jul 17 07:01:57 PM PDT 24 Jul 17 07:07:52 PM PDT 24 164097356183 ps
T342 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1364287493 Jul 17 07:01:56 PM PDT 24 Jul 17 07:02:19 PM PDT 24 1014075449 ps
T343 /workspace/coverage/default/33.rom_ctrl_alert_test.3313437002 Jul 17 07:01:59 PM PDT 24 Jul 17 07:02:14 PM PDT 24 262916462 ps
T344 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1279083754 Jul 17 07:01:59 PM PDT 24 Jul 17 07:02:22 PM PDT 24 1645502893 ps
T345 /workspace/coverage/default/6.rom_ctrl_alert_test.449613982 Jul 17 07:01:56 PM PDT 24 Jul 17 07:02:13 PM PDT 24 768655252 ps
T346 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3351195067 Jul 17 07:02:29 PM PDT 24 Jul 17 07:05:44 PM PDT 24 73223497869 ps
T347 /workspace/coverage/default/23.rom_ctrl_alert_test.833367912 Jul 17 07:01:53 PM PDT 24 Jul 17 07:02:11 PM PDT 24 5419336871 ps
T348 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4273267206 Jul 17 07:02:29 PM PDT 24 Jul 17 07:02:56 PM PDT 24 3766955832 ps
T349 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2704981877 Jul 17 07:02:30 PM PDT 24 Jul 17 07:02:54 PM PDT 24 4613680892 ps
T350 /workspace/coverage/default/47.rom_ctrl_stress_all.3609229658 Jul 17 07:02:29 PM PDT 24 Jul 17 07:03:01 PM PDT 24 8754887747 ps
T351 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3685742309 Jul 17 07:01:43 PM PDT 24 Jul 17 07:05:19 PM PDT 24 20322055147 ps
T352 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3010049529 Jul 17 07:01:51 PM PDT 24 Jul 17 07:01:59 PM PDT 24 444317783 ps
T353 /workspace/coverage/default/49.rom_ctrl_alert_test.694856630 Jul 17 07:02:31 PM PDT 24 Jul 17 07:02:49 PM PDT 24 4141163634 ps
T354 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1112319080 Jul 17 07:02:30 PM PDT 24 Jul 17 07:40:00 PM PDT 24 62636567139 ps
T355 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2851294868 Jul 17 07:01:57 PM PDT 24 Jul 17 07:02:20 PM PDT 24 1763728262 ps
T356 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4018055841 Jul 17 07:01:52 PM PDT 24 Jul 17 07:02:21 PM PDT 24 2705839635 ps
T357 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1792969221 Jul 17 07:01:55 PM PDT 24 Jul 17 07:08:56 PM PDT 24 177508894735 ps
T358 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1417014977 Jul 17 07:01:57 PM PDT 24 Jul 17 07:02:19 PM PDT 24 6869348642 ps
T359 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2596762663 Jul 17 07:02:03 PM PDT 24 Jul 17 07:02:25 PM PDT 24 3012816576 ps
T360 /workspace/coverage/default/30.rom_ctrl_smoke.1769887650 Jul 17 07:01:54 PM PDT 24 Jul 17 07:02:18 PM PDT 24 1083481035 ps
T361 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1216405248 Jul 17 07:02:33 PM PDT 24 Jul 17 07:03:08 PM PDT 24 12939683038 ps
T362 /workspace/coverage/default/22.rom_ctrl_stress_all.2583405129 Jul 17 07:02:01 PM PDT 24 Jul 17 07:02:46 PM PDT 24 8040015026 ps
T363 /workspace/coverage/default/28.rom_ctrl_stress_all.2936096276 Jul 17 07:01:59 PM PDT 24 Jul 17 07:02:28 PM PDT 24 1843321507 ps
T364 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3341366243 Jul 17 07:01:43 PM PDT 24 Jul 17 07:02:01 PM PDT 24 4245373631 ps
T365 /workspace/coverage/default/13.rom_ctrl_smoke.1696175816 Jul 17 07:01:59 PM PDT 24 Jul 17 07:02:29 PM PDT 24 2122924904 ps
T366 /workspace/coverage/default/34.rom_ctrl_smoke.4056809838 Jul 17 07:02:03 PM PDT 24 Jul 17 07:02:41 PM PDT 24 6674160872 ps
T367 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.321137546 Jul 17 07:02:28 PM PDT 24 Jul 17 07:02:46 PM PDT 24 1312342282 ps
T368 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3393623032 Jul 17 07:02:20 PM PDT 24 Jul 17 07:02:44 PM PDT 24 1547729617 ps
T369 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.72218829 Jul 17 07:01:59 PM PDT 24 Jul 17 07:02:13 PM PDT 24 382767426 ps
T370 /workspace/coverage/default/6.rom_ctrl_smoke.3810410650 Jul 17 07:01:40 PM PDT 24 Jul 17 07:02:10 PM PDT 24 22229946818 ps
T63 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1248876461 Jul 17 05:50:22 PM PDT 24 Jul 17 05:51:09 PM PDT 24 7326141044 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.55953124 Jul 17 05:49:55 PM PDT 24 Jul 17 05:50:08 PM PDT 24 569701974 ps
T66 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2713228871 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:20 PM PDT 24 350392755 ps
T64 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.821173436 Jul 17 05:50:12 PM PDT 24 Jul 17 05:51:00 PM PDT 24 7081013673 ps
T71 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1202943492 Jul 17 05:50:16 PM PDT 24 Jul 17 05:50:21 PM PDT 24 88396018 ps
T72 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1537120160 Jul 17 05:50:08 PM PDT 24 Jul 17 05:50:22 PM PDT 24 6366023340 ps
T372 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.192482778 Jul 17 05:50:17 PM PDT 24 Jul 17 05:50:25 PM PDT 24 347723273 ps
T373 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1346860034 Jul 17 05:50:08 PM PDT 24 Jul 17 05:50:24 PM PDT 24 1164454440 ps
T374 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.706233688 Jul 17 05:50:22 PM PDT 24 Jul 17 05:50:38 PM PDT 24 3087309641 ps
T73 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1721367377 Jul 17 05:50:12 PM PDT 24 Jul 17 05:50:28 PM PDT 24 2791856950 ps
T103 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2906098602 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:27 PM PDT 24 3684623883 ps
T65 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.980440559 Jul 17 05:50:21 PM PDT 24 Jul 17 05:51:04 PM PDT 24 1116509383 ps
T74 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2307469113 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:48 PM PDT 24 4743460666 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2765863179 Jul 17 05:49:54 PM PDT 24 Jul 17 05:50:07 PM PDT 24 1502222004 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.90057978 Jul 17 05:50:08 PM PDT 24 Jul 17 05:50:15 PM PDT 24 85762078 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.411868731 Jul 17 05:50:26 PM PDT 24 Jul 17 05:50:41 PM PDT 24 1822013598 ps
T107 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1206188099 Jul 17 05:49:54 PM PDT 24 Jul 17 05:50:34 PM PDT 24 629343182 ps
T75 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.170416663 Jul 17 05:50:16 PM PDT 24 Jul 17 05:50:30 PM PDT 24 28433239784 ps
T378 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.882407159 Jul 17 05:50:12 PM PDT 24 Jul 17 05:50:30 PM PDT 24 5888558052 ps
T379 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1237594712 Jul 17 05:50:15 PM PDT 24 Jul 17 05:50:24 PM PDT 24 924709189 ps
T100 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1653463983 Jul 17 05:50:27 PM PDT 24 Jul 17 05:51:45 PM PDT 24 35069560685 ps
T104 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.445478661 Jul 17 05:50:23 PM PDT 24 Jul 17 05:50:29 PM PDT 24 168515709 ps
T380 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2587994715 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:20 PM PDT 24 126082652 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1818166454 Jul 17 05:50:18 PM PDT 24 Jul 17 05:50:28 PM PDT 24 88042615 ps
T76 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.823089843 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:19 PM PDT 24 500644070 ps
T110 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3428019339 Jul 17 05:50:21 PM PDT 24 Jul 17 05:51:39 PM PDT 24 1747818634 ps
T113 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2368594056 Jul 17 05:50:08 PM PDT 24 Jul 17 05:51:25 PM PDT 24 1713033163 ps
T101 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.43906967 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:27 PM PDT 24 5235468736 ps
T77 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2175408291 Jul 17 05:50:07 PM PDT 24 Jul 17 05:51:09 PM PDT 24 5704180813 ps
T78 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3033468913 Jul 17 05:50:11 PM PDT 24 Jul 17 05:51:15 PM PDT 24 27442660467 ps
T382 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.353029945 Jul 17 05:50:12 PM PDT 24 Jul 17 05:50:52 PM PDT 24 367809073 ps
T383 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.474602331 Jul 17 05:50:16 PM PDT 24 Jul 17 05:50:27 PM PDT 24 6819317413 ps
T79 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1383272469 Jul 17 05:50:16 PM PDT 24 Jul 17 05:50:24 PM PDT 24 389887500 ps
T106 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2095493580 Jul 17 05:50:08 PM PDT 24 Jul 17 05:51:47 PM PDT 24 21599508773 ps
T111 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.326108230 Jul 17 05:50:16 PM PDT 24 Jul 17 05:51:28 PM PDT 24 4137680677 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2498056066 Jul 17 05:49:53 PM PDT 24 Jul 17 05:50:06 PM PDT 24 3307305104 ps
T89 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2578831022 Jul 17 05:50:08 PM PDT 24 Jul 17 05:51:26 PM PDT 24 34626263009 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2487347950 Jul 17 05:49:59 PM PDT 24 Jul 17 05:51:00 PM PDT 24 7185001087 ps
T384 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.108733749 Jul 17 05:50:25 PM PDT 24 Jul 17 05:50:37 PM PDT 24 2626812065 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2746081586 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:32 PM PDT 24 2017053908 ps
T114 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2512133617 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:50 PM PDT 24 293583833 ps
T386 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3129299283 Jul 17 05:50:18 PM PDT 24 Jul 17 05:50:33 PM PDT 24 1188129737 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2123149654 Jul 17 05:50:10 PM PDT 24 Jul 17 05:50:20 PM PDT 24 2061595216 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3617797485 Jul 17 05:50:10 PM PDT 24 Jul 17 05:50:29 PM PDT 24 7516399476 ps
T112 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1641152617 Jul 17 05:50:30 PM PDT 24 Jul 17 05:51:43 PM PDT 24 6154820237 ps
T388 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3209634901 Jul 17 05:50:08 PM PDT 24 Jul 17 05:50:25 PM PDT 24 6955732878 ps
T389 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1135528552 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:29 PM PDT 24 2212747297 ps
T390 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.556825629 Jul 17 05:50:21 PM PDT 24 Jul 17 05:50:28 PM PDT 24 199739624 ps
T102 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1026614052 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:30 PM PDT 24 2719714517 ps
T391 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1503740948 Jul 17 05:50:26 PM PDT 24 Jul 17 05:50:36 PM PDT 24 676883477 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.438793926 Jul 17 05:49:59 PM PDT 24 Jul 17 05:50:07 PM PDT 24 525584297 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2951302162 Jul 17 05:49:54 PM PDT 24 Jul 17 05:50:08 PM PDT 24 8020638008 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3052081355 Jul 17 05:49:57 PM PDT 24 Jul 17 05:50:12 PM PDT 24 1370559005 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4002572370 Jul 17 05:49:54 PM PDT 24 Jul 17 05:50:09 PM PDT 24 1702075174 ps
T93 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1964781537 Jul 17 05:49:58 PM PDT 24 Jul 17 05:50:05 PM PDT 24 346894146 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1117109629 Jul 17 05:49:54 PM PDT 24 Jul 17 05:50:02 PM PDT 24 1310231199 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1540331345 Jul 17 05:49:56 PM PDT 24 Jul 17 05:50:13 PM PDT 24 1562547808 ps
T397 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1447215613 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:42 PM PDT 24 769212290 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.769338401 Jul 17 05:49:55 PM PDT 24 Jul 17 05:50:10 PM PDT 24 5554337556 ps
T399 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.807896569 Jul 17 05:50:25 PM PDT 24 Jul 17 05:50:36 PM PDT 24 2870022607 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3909720920 Jul 17 05:50:16 PM PDT 24 Jul 17 05:50:32 PM PDT 24 25230054591 ps
T401 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3762187644 Jul 17 05:50:20 PM PDT 24 Jul 17 05:50:33 PM PDT 24 7878846441 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4004299782 Jul 17 05:49:53 PM PDT 24 Jul 17 05:50:06 PM PDT 24 2070841889 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1816254 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:16 PM PDT 24 568116613 ps
T119 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3252899564 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:48 PM PDT 24 1127858703 ps
T404 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1070123326 Jul 17 05:50:24 PM PDT 24 Jul 17 05:51:42 PM PDT 24 17297765890 ps
T94 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1977458237 Jul 17 05:50:10 PM PDT 24 Jul 17 05:50:19 PM PDT 24 1781497916 ps
T97 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1039267745 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:32 PM PDT 24 1515023968 ps
T405 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.854840161 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:25 PM PDT 24 3757298789 ps
T406 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1374677387 Jul 17 05:50:08 PM PDT 24 Jul 17 05:50:22 PM PDT 24 4134749573 ps
T407 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4222312638 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:17 PM PDT 24 2627853888 ps
T95 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3126957447 Jul 17 05:50:27 PM PDT 24 Jul 17 05:52:06 PM PDT 24 47530341071 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3104825857 Jul 17 05:50:22 PM PDT 24 Jul 17 05:51:23 PM PDT 24 22746078651 ps
T409 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.415319476 Jul 17 05:50:20 PM PDT 24 Jul 17 05:50:32 PM PDT 24 784987973 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1138786558 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:29 PM PDT 24 23906687934 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.782870232 Jul 17 05:50:00 PM PDT 24 Jul 17 05:50:54 PM PDT 24 12119722866 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2757592962 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:25 PM PDT 24 2434556957 ps
T413 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2633367800 Jul 17 05:49:57 PM PDT 24 Jul 17 05:51:08 PM PDT 24 16775664786 ps
T414 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1230898888 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:19 PM PDT 24 1328157629 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3955721567 Jul 17 05:50:10 PM PDT 24 Jul 17 05:50:19 PM PDT 24 657804530 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1014574035 Jul 17 05:49:57 PM PDT 24 Jul 17 05:50:04 PM PDT 24 171510671 ps
T117 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1984384268 Jul 17 05:50:10 PM PDT 24 Jul 17 05:50:55 PM PDT 24 14946593127 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2851825260 Jul 17 05:49:59 PM PDT 24 Jul 17 05:50:09 PM PDT 24 2471294697 ps
T418 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4109939541 Jul 17 05:50:10 PM PDT 24 Jul 17 05:50:29 PM PDT 24 6065514575 ps
T116 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.940141146 Jul 17 05:50:15 PM PDT 24 Jul 17 05:51:27 PM PDT 24 872406001 ps
T419 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2599630468 Jul 17 05:50:15 PM PDT 24 Jul 17 05:50:24 PM PDT 24 2716094688 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1308433009 Jul 17 05:50:16 PM PDT 24 Jul 17 05:50:35 PM PDT 24 1568199201 ps
T108 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3397485866 Jul 17 05:50:22 PM PDT 24 Jul 17 05:51:06 PM PDT 24 10720688026 ps
T421 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.583774737 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:19 PM PDT 24 436991108 ps
T422 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2312884768 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:20 PM PDT 24 660683486 ps
T423 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2367634342 Jul 17 05:49:56 PM PDT 24 Jul 17 05:50:06 PM PDT 24 425074913 ps
T424 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1324993216 Jul 17 05:50:20 PM PDT 24 Jul 17 05:50:40 PM PDT 24 700016286 ps
T425 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1723951847 Jul 17 05:50:22 PM PDT 24 Jul 17 05:50:34 PM PDT 24 164691744 ps
T426 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2807996571 Jul 17 05:50:20 PM PDT 24 Jul 17 05:50:37 PM PDT 24 6915613126 ps
T427 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2484208413 Jul 17 05:50:18 PM PDT 24 Jul 17 05:50:36 PM PDT 24 8724180532 ps
T428 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1237176578 Jul 17 05:50:10 PM PDT 24 Jul 17 05:50:29 PM PDT 24 4281998800 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.125282302 Jul 17 05:49:59 PM PDT 24 Jul 17 05:50:09 PM PDT 24 1738249727 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.426336789 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:19 PM PDT 24 328974811 ps
T431 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2975684280 Jul 17 05:50:21 PM PDT 24 Jul 17 05:50:38 PM PDT 24 1909518337 ps
T432 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.936867316 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:29 PM PDT 24 1550400484 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.39833257 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:31 PM PDT 24 1816578124 ps
T120 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1511832496 Jul 17 05:50:18 PM PDT 24 Jul 17 05:50:55 PM PDT 24 566604863 ps
T434 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3942933182 Jul 17 05:49:58 PM PDT 24 Jul 17 05:50:07 PM PDT 24 188805093 ps
T435 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2990891891 Jul 17 05:50:22 PM PDT 24 Jul 17 05:50:36 PM PDT 24 6528519243 ps
T436 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.792928306 Jul 17 05:50:06 PM PDT 24 Jul 17 05:50:20 PM PDT 24 3004320497 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1634977712 Jul 17 05:50:07 PM PDT 24 Jul 17 05:50:12 PM PDT 24 692148740 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.118289968 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:19 PM PDT 24 168761854 ps
T109 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2939660691 Jul 17 05:49:59 PM PDT 24 Jul 17 05:51:20 PM PDT 24 2046803953 ps
T98 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2106133098 Jul 17 05:50:12 PM PDT 24 Jul 17 05:50:42 PM PDT 24 2263736941 ps
T439 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3447614288 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:20 PM PDT 24 743543316 ps
T440 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1981674896 Jul 17 05:50:22 PM PDT 24 Jul 17 05:50:28 PM PDT 24 246346110 ps
T441 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1623041383 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:24 PM PDT 24 4754344868 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4060329878 Jul 17 05:49:59 PM PDT 24 Jul 17 05:50:08 PM PDT 24 581272243 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4125740983 Jul 17 05:49:57 PM PDT 24 Jul 17 05:50:06 PM PDT 24 94608833 ps
T444 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3507655012 Jul 17 05:49:56 PM PDT 24 Jul 17 05:50:11 PM PDT 24 5125686295 ps
T99 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2258938498 Jul 17 05:49:55 PM PDT 24 Jul 17 05:50:05 PM PDT 24 881523928 ps
T445 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.268706839 Jul 17 05:50:20 PM PDT 24 Jul 17 05:50:39 PM PDT 24 3877572569 ps
T446 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.158560895 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:25 PM PDT 24 4245034663 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2859949277 Jul 17 05:50:21 PM PDT 24 Jul 17 05:50:33 PM PDT 24 968728262 ps
T448 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2642087063 Jul 17 05:50:08 PM PDT 24 Jul 17 05:50:19 PM PDT 24 2480752484 ps
T449 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.500635324 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:25 PM PDT 24 3570881282 ps
T450 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2513811594 Jul 17 05:49:57 PM PDT 24 Jul 17 05:50:08 PM PDT 24 297261413 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.619639600 Jul 17 05:49:55 PM PDT 24 Jul 17 05:50:06 PM PDT 24 383332929 ps
T452 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3243417130 Jul 17 05:49:53 PM PDT 24 Jul 17 05:49:59 PM PDT 24 298431939 ps
T453 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2050055465 Jul 17 05:50:21 PM PDT 24 Jul 17 05:50:38 PM PDT 24 2096087588 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1922579208 Jul 17 05:49:55 PM PDT 24 Jul 17 05:50:05 PM PDT 24 2064183468 ps
T121 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.834062272 Jul 17 05:49:53 PM PDT 24 Jul 17 05:50:33 PM PDT 24 426686463 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1284552445 Jul 17 05:49:56 PM PDT 24 Jul 17 05:50:10 PM PDT 24 414157915 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3055125067 Jul 17 05:50:08 PM PDT 24 Jul 17 05:50:24 PM PDT 24 17243650260 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1986568082 Jul 17 05:49:56 PM PDT 24 Jul 17 05:50:17 PM PDT 24 2162948899 ps
T458 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1202827563 Jul 17 05:50:20 PM PDT 24 Jul 17 05:50:28 PM PDT 24 347654357 ps
T459 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2315874012 Jul 17 05:50:22 PM PDT 24 Jul 17 05:50:40 PM PDT 24 5182736306 ps
T460 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1196884872 Jul 17 05:50:12 PM PDT 24 Jul 17 05:51:29 PM PDT 24 11786853496 ps
T461 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3824534675 Jul 17 05:50:09 PM PDT 24 Jul 17 05:50:21 PM PDT 24 978752921 ps
T462 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1206833327 Jul 17 05:50:08 PM PDT 24 Jul 17 05:50:17 PM PDT 24 107499583 ps
T463 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1496194053 Jul 17 05:50:20 PM PDT 24 Jul 17 05:50:31 PM PDT 24 493067507 ps
T464 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3211449104 Jul 17 05:50:18 PM PDT 24 Jul 17 05:50:30 PM PDT 24 1316889125 ps
T465 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2867459479 Jul 17 05:49:55 PM PDT 24 Jul 17 05:50:17 PM PDT 24 1509570340 ps
T466 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3836597183 Jul 17 05:49:55 PM PDT 24 Jul 17 05:50:12 PM PDT 24 1266073652 ps
T467 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3465954753 Jul 17 05:49:54 PM PDT 24 Jul 17 05:50:04 PM PDT 24 432651065 ps
T118 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3883324695 Jul 17 05:49:57 PM PDT 24 Jul 17 05:50:39 PM PDT 24 2782736008 ps
T96 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3186395746 Jul 17 05:50:11 PM PDT 24 Jul 17 05:50:43 PM PDT 24 548807586 ps
T468 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3277293877 Jul 17 05:49:58 PM PDT 24 Jul 17 05:50:07 PM PDT 24 171278573 ps
T469 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2711325593 Jul 17 05:50:10 PM PDT 24 Jul 17 05:51:19 PM PDT 24 30841645328 ps
T115 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1771171979 Jul 17 05:50:15 PM PDT 24 Jul 17 05:51:23 PM PDT 24 3360753563 ps

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.166295788
Short name T6
Test name
Test status
Simulation time 9399706184 ps
CPU time 59.95 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:03:04 PM PDT 24
Peak memory 237564 kb
Host smart-b6c0b5ba-0ebb-4bbd-8cef-d6f16b97a9cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166295788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.166295788
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.585319181
Short name T22
Test name
Test status
Simulation time 41485890028 ps
CPU time 6888.66 seconds
Started Jul 17 07:02:17 PM PDT 24
Finished Jul 17 08:57:08 PM PDT 24
Peak memory 233604 kb
Host smart-60601504-ea52-40df-ba74-67f2b8ef562c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585319181 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.585319181
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2370033491
Short name T36
Test name
Test status
Simulation time 72099882196 ps
CPU time 394.51 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 234816 kb
Host smart-32f81283-1323-4532-914c-141bc618e7c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370033491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2370033491
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.585486344
Short name T11
Test name
Test status
Simulation time 14721308632 ps
CPU time 34.69 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 214580 kb
Host smart-6c7933a4-f072-4b3d-a19a-769820531dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585486344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.585486344
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1206188099
Short name T107
Test name
Test status
Simulation time 629343182 ps
CPU time 37.22 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:50:34 PM PDT 24
Peak memory 211896 kb
Host smart-a89b9af8-13ef-4a19-9760-60dc9a4006b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206188099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1206188099
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1558311578
Short name T158
Test name
Test status
Simulation time 945843614 ps
CPU time 74.2 seconds
Started Jul 17 07:02:22 PM PDT 24
Finished Jul 17 07:03:40 PM PDT 24
Peak memory 228504 kb
Host smart-583bcd40-2a2b-4506-b43a-0a8a96206784
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558311578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1558311578
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4018656388
Short name T18
Test name
Test status
Simulation time 5821352224 ps
CPU time 113.95 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:03:57 PM PDT 24
Peak memory 240976 kb
Host smart-bc77cc9e-536e-4319-afa5-2b7a3620a302
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018656388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4018656388
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2175408291
Short name T77
Test name
Test status
Simulation time 5704180813 ps
CPU time 61.64 seconds
Started Jul 17 05:50:07 PM PDT 24
Finished Jul 17 05:51:09 PM PDT 24
Peak memory 210484 kb
Host smart-9d980bd4-61fe-43bb-9162-ff03dddd621a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175408291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2175408291
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.105602499
Short name T51
Test name
Test status
Simulation time 129476495062 ps
CPU time 1324.24 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:24:11 PM PDT 24
Peak memory 235856 kb
Host smart-4e413510-3357-4bb9-8b96-55f25f2b725e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105602499 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.105602499
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1196884872
Short name T460
Test name
Test status
Simulation time 11786853496 ps
CPU time 73.55 seconds
Started Jul 17 05:50:12 PM PDT 24
Finished Jul 17 05:51:29 PM PDT 24
Peak memory 218604 kb
Host smart-0f452dbb-92ba-474a-8522-4a6732f277fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196884872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1196884872
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2772039068
Short name T7
Test name
Test status
Simulation time 4553025575 ps
CPU time 12.67 seconds
Started Jul 17 07:02:22 PM PDT 24
Finished Jul 17 07:02:38 PM PDT 24
Peak memory 211392 kb
Host smart-5038ce89-def2-478a-b794-89a3a432934b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772039068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2772039068
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.821173436
Short name T64
Test name
Test status
Simulation time 7081013673 ps
CPU time 45.41 seconds
Started Jul 17 05:50:12 PM PDT 24
Finished Jul 17 05:51:00 PM PDT 24
Peak memory 211804 kb
Host smart-5e1fc82a-d435-4747-9a81-29df95267ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821173436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.821173436
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3612541741
Short name T27
Test name
Test status
Simulation time 2479897196 ps
CPU time 24.61 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:02:36 PM PDT 24
Peak memory 211948 kb
Host smart-eab43c0d-cc00-440a-a2a1-134f5eb6df87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612541741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3612541741
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.332235251
Short name T130
Test name
Test status
Simulation time 469567253 ps
CPU time 9.57 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:45 PM PDT 24
Peak memory 213812 kb
Host smart-bffdec0b-e046-4d0c-91ad-51df01307f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332235251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.332235251
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3883324695
Short name T118
Test name
Test status
Simulation time 2782736008 ps
CPU time 39.37 seconds
Started Jul 17 05:49:57 PM PDT 24
Finished Jul 17 05:50:39 PM PDT 24
Peak memory 218592 kb
Host smart-070c713f-c692-4f1d-a9ed-a017f042e972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883324695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3883324695
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2307469113
Short name T74
Test name
Test status
Simulation time 4743460666 ps
CPU time 33.16 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:48 PM PDT 24
Peak memory 210460 kb
Host smart-7488888e-3c6a-4195-94fe-f547b0795fef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307469113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2307469113
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3056119457
Short name T14
Test name
Test status
Simulation time 3338971078 ps
CPU time 13.26 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:02:45 PM PDT 24
Peak memory 211612 kb
Host smart-d80f0e29-54e2-4c31-b43f-7f575c48d44a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3056119457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3056119457
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2939660691
Short name T109
Test name
Test status
Simulation time 2046803953 ps
CPU time 78.42 seconds
Started Jul 17 05:49:59 PM PDT 24
Finished Jul 17 05:51:20 PM PDT 24
Peak memory 211880 kb
Host smart-5aa82acf-441b-43d2-b090-a917208da184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939660691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2939660691
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2074693356
Short name T59
Test name
Test status
Simulation time 172131393325 ps
CPU time 1743.27 seconds
Started Jul 17 07:02:33 PM PDT 24
Finished Jul 17 07:31:44 PM PDT 24
Peak memory 238376 kb
Host smart-9685bd6b-010b-4b08-a394-800bb31d4e81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074693356 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2074693356
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.769338401
Short name T398
Test name
Test status
Simulation time 5554337556 ps
CPU time 11.99 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:10 PM PDT 24
Peak memory 210356 kb
Host smart-229d96cc-d090-4ffb-a28f-146cc5b0db59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769338401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.769338401
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2367634342
Short name T423
Test name
Test status
Simulation time 425074913 ps
CPU time 7.14 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:06 PM PDT 24
Peak memory 210336 kb
Host smart-0ef57d57-340a-4070-8417-966c10fd5223
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367634342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2367634342
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.619639600
Short name T451
Test name
Test status
Simulation time 383332929 ps
CPU time 7.42 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:06 PM PDT 24
Peak memory 210320 kb
Host smart-71b47d81-4814-4abf-8dd6-1fdfa3a9c54a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619639600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.619639600
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2951302162
Short name T393
Test name
Test status
Simulation time 8020638008 ps
CPU time 11.61 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:50:08 PM PDT 24
Peak memory 218628 kb
Host smart-0ed41664-be59-46ce-a6af-f628b43ca85c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951302162 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2951302162
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2258938498
Short name T99
Test name
Test status
Simulation time 881523928 ps
CPU time 7.4 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:05 PM PDT 24
Peak memory 217292 kb
Host smart-ef73cd1e-693f-4091-87cf-2dcc24aaea6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258938498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2258938498
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3243417130
Short name T452
Test name
Test status
Simulation time 298431939 ps
CPU time 4.22 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:49:59 PM PDT 24
Peak memory 210176 kb
Host smart-fd0980d3-c9fc-4bd0-a576-65cf8c795ec3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243417130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3243417130
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1540331345
Short name T396
Test name
Test status
Simulation time 1562547808 ps
CPU time 13.3 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:13 PM PDT 24
Peak memory 210172 kb
Host smart-e5617ab3-2e04-4d27-8c97-087fab5c5ec9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540331345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1540331345
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2867459479
Short name T465
Test name
Test status
Simulation time 1509570340 ps
CPU time 18.95 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:17 PM PDT 24
Peak memory 210400 kb
Host smart-9e9d04cf-e401-4f2d-aed6-c3f67b6c4418
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867459479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2867459479
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1986568082
Short name T457
Test name
Test status
Simulation time 2162948899 ps
CPU time 17.45 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:17 PM PDT 24
Peak memory 218552 kb
Host smart-a3966a95-b61e-4616-84bd-8d82b786c443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986568082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1986568082
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1284552445
Short name T455
Test name
Test status
Simulation time 414157915 ps
CPU time 9.7 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:10 PM PDT 24
Peak memory 218576 kb
Host smart-2054f4e5-612a-4c1d-9f8e-cf72d8a0d8ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284552445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1284552445
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1964781537
Short name T93
Test name
Test status
Simulation time 346894146 ps
CPU time 4.27 seconds
Started Jul 17 05:49:58 PM PDT 24
Finished Jul 17 05:50:05 PM PDT 24
Peak memory 217332 kb
Host smart-9d7e656e-90d5-443b-9510-f539b47efa62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964781537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1964781537
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.125282302
Short name T429
Test name
Test status
Simulation time 1738249727 ps
CPU time 7.34 seconds
Started Jul 17 05:49:59 PM PDT 24
Finished Jul 17 05:50:09 PM PDT 24
Peak memory 210264 kb
Host smart-4672dfc1-1f17-4bf1-9558-9457ab781108
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125282302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.125282302
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3836597183
Short name T466
Test name
Test status
Simulation time 1266073652 ps
CPU time 13.12 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:12 PM PDT 24
Peak memory 210260 kb
Host smart-3cb65e1a-9cbc-47ed-825f-0552c28998d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836597183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3836597183
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2851825260
Short name T417
Test name
Test status
Simulation time 2471294697 ps
CPU time 8.07 seconds
Started Jul 17 05:49:59 PM PDT 24
Finished Jul 17 05:50:09 PM PDT 24
Peak memory 218644 kb
Host smart-7811879d-dbad-4b34-8fa6-eb68216944c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851825260 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2851825260
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3052081355
Short name T394
Test name
Test status
Simulation time 1370559005 ps
CPU time 11.76 seconds
Started Jul 17 05:49:57 PM PDT 24
Finished Jul 17 05:50:12 PM PDT 24
Peak memory 210348 kb
Host smart-f3596313-72ff-4f19-8372-ce1c36961b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052081355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3052081355
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1922579208
Short name T454
Test name
Test status
Simulation time 2064183468 ps
CPU time 6.02 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:05 PM PDT 24
Peak memory 210152 kb
Host smart-8e60d491-8fb6-482a-ac30-f1c5fd3bf284
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922579208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1922579208
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3465954753
Short name T467
Test name
Test status
Simulation time 432651065 ps
CPU time 6.86 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:50:04 PM PDT 24
Peak memory 210168 kb
Host smart-6d1d07e7-6b6e-4a25-936f-eaddcf598dde
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465954753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3465954753
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2633367800
Short name T413
Test name
Test status
Simulation time 16775664786 ps
CPU time 67.68 seconds
Started Jul 17 05:49:57 PM PDT 24
Finished Jul 17 05:51:08 PM PDT 24
Peak memory 210404 kb
Host smart-48799a4a-7f5f-4e12-a593-bcbf31a4f6cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633367800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2633367800
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3942933182
Short name T434
Test name
Test status
Simulation time 188805093 ps
CPU time 6.12 seconds
Started Jul 17 05:49:58 PM PDT 24
Finished Jul 17 05:50:07 PM PDT 24
Peak memory 210300 kb
Host smart-4b4af6a3-2d67-4b0e-9584-930f9139cdfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942933182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3942933182
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.55953124
Short name T371
Test name
Test status
Simulation time 569701974 ps
CPU time 9.58 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:08 PM PDT 24
Peak memory 218576 kb
Host smart-236d1c52-df11-4873-96d2-c9412fb77960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55953124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.55953124
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3209634901
Short name T388
Test name
Test status
Simulation time 6955732878 ps
CPU time 14.59 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:50:25 PM PDT 24
Peak memory 218616 kb
Host smart-e94b128f-9580-44a1-a9eb-40ee1f060113
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209634901 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3209634901
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1977458237
Short name T94
Test name
Test status
Simulation time 1781497916 ps
CPU time 5.11 seconds
Started Jul 17 05:50:10 PM PDT 24
Finished Jul 17 05:50:19 PM PDT 24
Peak memory 217580 kb
Host smart-3b67bf74-08f7-4029-b657-bc1145519804
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977458237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1977458237
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1447215613
Short name T397
Test name
Test status
Simulation time 769212290 ps
CPU time 27.98 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:42 PM PDT 24
Peak memory 210376 kb
Host smart-8b42439b-b8d4-472e-84d2-a826ee1aaf3c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447215613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1447215613
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.39833257
Short name T433
Test name
Test status
Simulation time 1816578124 ps
CPU time 16.78 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:31 PM PDT 24
Peak memory 218488 kb
Host smart-5c34c075-9e1b-44b2-ba14-1cc343b49275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39833257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ct
rl_same_csr_outstanding.39833257
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.792928306
Short name T436
Test name
Test status
Simulation time 3004320497 ps
CPU time 13.22 seconds
Started Jul 17 05:50:06 PM PDT 24
Finished Jul 17 05:50:20 PM PDT 24
Peak memory 218580 kb
Host smart-8a0b5b01-8534-4a1f-b33e-263fe3c59464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792928306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.792928306
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3252899564
Short name T119
Test name
Test status
Simulation time 1127858703 ps
CPU time 37.49 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:48 PM PDT 24
Peak memory 210700 kb
Host smart-76e712aa-ecf5-4fe2-a896-af82d0bf83be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252899564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3252899564
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1237176578
Short name T428
Test name
Test status
Simulation time 4281998800 ps
CPU time 15.28 seconds
Started Jul 17 05:50:10 PM PDT 24
Finished Jul 17 05:50:29 PM PDT 24
Peak memory 218612 kb
Host smart-ab4899b8-6c3d-4cfe-a0dd-c1f022f62d71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237176578 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1237176578
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3824534675
Short name T461
Test name
Test status
Simulation time 978752921 ps
CPU time 9.5 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:21 PM PDT 24
Peak memory 210324 kb
Host smart-1164c5f3-f985-4fce-a9aa-eff63054700c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824534675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3824534675
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2713228871
Short name T66
Test name
Test status
Simulation time 350392755 ps
CPU time 6.09 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:20 PM PDT 24
Peak memory 217824 kb
Host smart-c0dee709-9947-4892-81af-b1dda3e41afa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713228871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2713228871
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4109939541
Short name T418
Test name
Test status
Simulation time 6065514575 ps
CPU time 16.95 seconds
Started Jul 17 05:50:10 PM PDT 24
Finished Jul 17 05:50:29 PM PDT 24
Peak memory 218588 kb
Host smart-b0703e55-749e-4566-a4aa-02c51081af71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109939541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4109939541
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.353029945
Short name T382
Test name
Test status
Simulation time 367809073 ps
CPU time 36.8 seconds
Started Jul 17 05:50:12 PM PDT 24
Finished Jul 17 05:50:52 PM PDT 24
Peak memory 210584 kb
Host smart-7823cf1b-4b33-410e-8e2b-42eb0180cfb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353029945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.353029945
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.474602331
Short name T383
Test name
Test status
Simulation time 6819317413 ps
CPU time 9.17 seconds
Started Jul 17 05:50:16 PM PDT 24
Finished Jul 17 05:50:27 PM PDT 24
Peak memory 218660 kb
Host smart-64f90d61-ad35-4695-b93c-1825ac58af3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474602331 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.474602331
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1383272469
Short name T79
Test name
Test status
Simulation time 389887500 ps
CPU time 6.36 seconds
Started Jul 17 05:50:16 PM PDT 24
Finished Jul 17 05:50:24 PM PDT 24
Peak memory 216956 kb
Host smart-7a6ee8f3-be6e-4236-a417-11d5c180a61b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383272469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1383272469
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1039267745
Short name T97
Test name
Test status
Simulation time 1515023968 ps
CPU time 19.36 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:32 PM PDT 24
Peak memory 210256 kb
Host smart-301161e9-b21a-41e0-9b7c-39d87b1b3f6a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039267745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1039267745
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1202943492
Short name T71
Test name
Test status
Simulation time 88396018 ps
CPU time 4.26 seconds
Started Jul 17 05:50:16 PM PDT 24
Finished Jul 17 05:50:21 PM PDT 24
Peak memory 217872 kb
Host smart-e3168d6d-4244-4c67-8557-d8fc74a10977
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202943492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1202943492
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3211449104
Short name T464
Test name
Test status
Simulation time 1316889125 ps
CPU time 11.12 seconds
Started Jul 17 05:50:18 PM PDT 24
Finished Jul 17 05:50:30 PM PDT 24
Peak memory 218600 kb
Host smart-ae7e33c9-9eec-4535-8e1c-ed62facb7a22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211449104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3211449104
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.940141146
Short name T116
Test name
Test status
Simulation time 872406001 ps
CPU time 71.28 seconds
Started Jul 17 05:50:15 PM PDT 24
Finished Jul 17 05:51:27 PM PDT 24
Peak memory 211944 kb
Host smart-bb278503-1d12-4fbb-99ad-745bfd8fd53d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940141146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.940141146
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1237594712
Short name T379
Test name
Test status
Simulation time 924709189 ps
CPU time 7.44 seconds
Started Jul 17 05:50:15 PM PDT 24
Finished Jul 17 05:50:24 PM PDT 24
Peak memory 218600 kb
Host smart-30f1e5e2-66f1-4df5-8af0-48c7c3e2685d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237594712 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1237594712
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2484208413
Short name T427
Test name
Test status
Simulation time 8724180532 ps
CPU time 16.62 seconds
Started Jul 17 05:50:18 PM PDT 24
Finished Jul 17 05:50:36 PM PDT 24
Peak memory 218532 kb
Host smart-8c2920ab-aebc-4aea-9017-4ed7f5b1ac63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484208413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2484208413
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3033468913
Short name T78
Test name
Test status
Simulation time 27442660467 ps
CPU time 60.51 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:51:15 PM PDT 24
Peak memory 210428 kb
Host smart-31907d19-3db3-4330-b0fa-60614d4401bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033468913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3033468913
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.936867316
Short name T432
Test name
Test status
Simulation time 1550400484 ps
CPU time 14.92 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:29 PM PDT 24
Peak memory 210412 kb
Host smart-a4d7da51-7da8-483e-9eea-acf1673aba38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936867316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.936867316
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3129299283
Short name T386
Test name
Test status
Simulation time 1188129737 ps
CPU time 14.24 seconds
Started Jul 17 05:50:18 PM PDT 24
Finished Jul 17 05:50:33 PM PDT 24
Peak memory 218596 kb
Host smart-757aa956-12fa-4350-8492-141caa056a64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129299283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3129299283
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1511832496
Short name T120
Test name
Test status
Simulation time 566604863 ps
CPU time 36.34 seconds
Started Jul 17 05:50:18 PM PDT 24
Finished Jul 17 05:50:55 PM PDT 24
Peak memory 211884 kb
Host smart-07271095-589f-4f41-bdd4-2b4e62a12c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511832496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1511832496
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.556825629
Short name T390
Test name
Test status
Simulation time 199739624 ps
CPU time 5.24 seconds
Started Jul 17 05:50:21 PM PDT 24
Finished Jul 17 05:50:28 PM PDT 24
Peak memory 218652 kb
Host smart-5376ee6a-2391-4a84-8be6-069f0b37eabb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556825629 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.556825629
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2599630468
Short name T419
Test name
Test status
Simulation time 2716094688 ps
CPU time 8.2 seconds
Started Jul 17 05:50:15 PM PDT 24
Finished Jul 17 05:50:24 PM PDT 24
Peak memory 216968 kb
Host smart-4bfbc1f9-b081-4544-b4c5-89271588b648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599630468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2599630468
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2106133098
Short name T98
Test name
Test status
Simulation time 2263736941 ps
CPU time 27.26 seconds
Started Jul 17 05:50:12 PM PDT 24
Finished Jul 17 05:50:42 PM PDT 24
Peak memory 210416 kb
Host smart-c742dde7-efae-4a04-8b1a-b9932455d7bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106133098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2106133098
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.170416663
Short name T75
Test name
Test status
Simulation time 28433239784 ps
CPU time 13.09 seconds
Started Jul 17 05:50:16 PM PDT 24
Finished Jul 17 05:50:30 PM PDT 24
Peak memory 218276 kb
Host smart-b658454f-4dfa-42a6-8096-5c084a61648d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170416663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.170416663
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.882407159
Short name T378
Test name
Test status
Simulation time 5888558052 ps
CPU time 15.35 seconds
Started Jul 17 05:50:12 PM PDT 24
Finished Jul 17 05:50:30 PM PDT 24
Peak memory 218600 kb
Host smart-596ab234-38f3-4ed3-beb9-1f862185932c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882407159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.882407159
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2859949277
Short name T447
Test name
Test status
Simulation time 968728262 ps
CPU time 10.47 seconds
Started Jul 17 05:50:21 PM PDT 24
Finished Jul 17 05:50:33 PM PDT 24
Peak memory 218528 kb
Host smart-a0e9791a-11ea-4e06-9b9b-b1a01e4d4371
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859949277 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2859949277
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2975684280
Short name T431
Test name
Test status
Simulation time 1909518337 ps
CPU time 14.92 seconds
Started Jul 17 05:50:21 PM PDT 24
Finished Jul 17 05:50:38 PM PDT 24
Peak memory 210440 kb
Host smart-c1afedbf-25f1-451d-8fba-5c067a6764b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975684280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2975684280
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3126957447
Short name T95
Test name
Test status
Simulation time 47530341071 ps
CPU time 97.89 seconds
Started Jul 17 05:50:27 PM PDT 24
Finished Jul 17 05:52:06 PM PDT 24
Peak memory 210412 kb
Host smart-3721143d-5495-43df-994f-8b484282c4b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126957447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3126957447
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.268706839
Short name T445
Test name
Test status
Simulation time 3877572569 ps
CPU time 17.19 seconds
Started Jul 17 05:50:20 PM PDT 24
Finished Jul 17 05:50:39 PM PDT 24
Peak memory 210476 kb
Host smart-fb4c505e-86d5-4325-af7e-4351e354b872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268706839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.268706839
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.706233688
Short name T374
Test name
Test status
Simulation time 3087309641 ps
CPU time 15.05 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:50:38 PM PDT 24
Peak memory 218636 kb
Host smart-b6118e87-6737-45f3-bf35-78747ad4da49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706233688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.706233688
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3397485866
Short name T108
Test name
Test status
Simulation time 10720688026 ps
CPU time 42.58 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:51:06 PM PDT 24
Peak memory 218640 kb
Host smart-bfbf1662-bd5a-42eb-a192-b9cbe8123981
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397485866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3397485866
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2807996571
Short name T426
Test name
Test status
Simulation time 6915613126 ps
CPU time 15.02 seconds
Started Jul 17 05:50:20 PM PDT 24
Finished Jul 17 05:50:37 PM PDT 24
Peak memory 215484 kb
Host smart-9ac3e30a-55eb-42ea-b2ed-93dd9e553549
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807996571 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2807996571
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.807896569
Short name T399
Test name
Test status
Simulation time 2870022607 ps
CPU time 8.86 seconds
Started Jul 17 05:50:25 PM PDT 24
Finished Jul 17 05:50:36 PM PDT 24
Peak memory 210412 kb
Host smart-4d8814c7-ce43-408f-9e5e-10621355c07a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807896569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.807896569
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1070123326
Short name T404
Test name
Test status
Simulation time 17297765890 ps
CPU time 76.17 seconds
Started Jul 17 05:50:24 PM PDT 24
Finished Jul 17 05:51:42 PM PDT 24
Peak memory 210440 kb
Host smart-43eebe5d-25ab-4866-bf60-ca0b29815ab4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070123326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1070123326
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3762187644
Short name T401
Test name
Test status
Simulation time 7878846441 ps
CPU time 11.78 seconds
Started Jul 17 05:50:20 PM PDT 24
Finished Jul 17 05:50:33 PM PDT 24
Peak memory 210920 kb
Host smart-f1188d24-9a1b-490c-9502-798e267458bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762187644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3762187644
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1723951847
Short name T425
Test name
Test status
Simulation time 164691744 ps
CPU time 9.42 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:50:34 PM PDT 24
Peak memory 218496 kb
Host smart-4ea3e87f-05f7-4a34-a237-7290098c2c11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723951847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1723951847
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3428019339
Short name T110
Test name
Test status
Simulation time 1747818634 ps
CPU time 76.36 seconds
Started Jul 17 05:50:21 PM PDT 24
Finished Jul 17 05:51:39 PM PDT 24
Peak memory 218568 kb
Host smart-bd6ca635-690a-40a6-af29-3b9c0d9e92d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428019339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3428019339
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.108733749
Short name T384
Test name
Test status
Simulation time 2626812065 ps
CPU time 11.24 seconds
Started Jul 17 05:50:25 PM PDT 24
Finished Jul 17 05:50:37 PM PDT 24
Peak memory 218696 kb
Host smart-e8e57c9c-93f1-47a1-9739-dbf4fa2f6a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108733749 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.108733749
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.445478661
Short name T104
Test name
Test status
Simulation time 168515709 ps
CPU time 4.42 seconds
Started Jul 17 05:50:23 PM PDT 24
Finished Jul 17 05:50:29 PM PDT 24
Peak memory 210308 kb
Host smart-557d0a97-63f0-4889-a1ca-5c2e0a93f879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445478661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.445478661
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3104825857
Short name T408
Test name
Test status
Simulation time 22746078651 ps
CPU time 59.03 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:51:23 PM PDT 24
Peak memory 211472 kb
Host smart-73b1feaa-9a90-49f8-bb0d-dbf484fcbf9e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104825857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3104825857
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1981674896
Short name T440
Test name
Test status
Simulation time 246346110 ps
CPU time 4.31 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:50:28 PM PDT 24
Peak memory 217920 kb
Host smart-c7f485a2-2bf9-453c-b531-657566073bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981674896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1981674896
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.192482778
Short name T372
Test name
Test status
Simulation time 347723273 ps
CPU time 6.69 seconds
Started Jul 17 05:50:17 PM PDT 24
Finished Jul 17 05:50:25 PM PDT 24
Peak memory 218572 kb
Host smart-a454f038-688c-48fd-8ade-7884a27b1a52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192482778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.192482778
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.980440559
Short name T65
Test name
Test status
Simulation time 1116509383 ps
CPU time 41.43 seconds
Started Jul 17 05:50:21 PM PDT 24
Finished Jul 17 05:51:04 PM PDT 24
Peak memory 218552 kb
Host smart-0dce3af7-6ce7-4545-aafc-114e261ff27f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980440559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.980440559
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2315874012
Short name T459
Test name
Test status
Simulation time 5182736306 ps
CPU time 16.2 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:50:40 PM PDT 24
Peak memory 218616 kb
Host smart-4d3337d6-71ef-4f39-81bf-a405f363314b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315874012 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2315874012
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2990891891
Short name T435
Test name
Test status
Simulation time 6528519243 ps
CPU time 12.9 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:50:36 PM PDT 24
Peak memory 218540 kb
Host smart-3efaa6da-3797-4cca-b6dd-9c960d7bb4b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990891891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2990891891
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1324993216
Short name T424
Test name
Test status
Simulation time 700016286 ps
CPU time 18.71 seconds
Started Jul 17 05:50:20 PM PDT 24
Finished Jul 17 05:50:40 PM PDT 24
Peak memory 210404 kb
Host smart-f72bb1d7-8457-4943-a2d9-afe01c5286cb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324993216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1324993216
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2050055465
Short name T453
Test name
Test status
Simulation time 2096087588 ps
CPU time 15.95 seconds
Started Jul 17 05:50:21 PM PDT 24
Finished Jul 17 05:50:38 PM PDT 24
Peak memory 210412 kb
Host smart-a7ac2ae9-143e-4752-8a5c-7c9b066680ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050055465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2050055465
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1496194053
Short name T463
Test name
Test status
Simulation time 493067507 ps
CPU time 9.34 seconds
Started Jul 17 05:50:20 PM PDT 24
Finished Jul 17 05:50:31 PM PDT 24
Peak memory 218596 kb
Host smart-4b600a93-8355-4f60-a0b3-1aca26db61a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496194053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1496194053
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1248876461
Short name T63
Test name
Test status
Simulation time 7326141044 ps
CPU time 45.78 seconds
Started Jul 17 05:50:22 PM PDT 24
Finished Jul 17 05:51:09 PM PDT 24
Peak memory 218552 kb
Host smart-fef0b3ca-2b94-40d5-bfa1-00be2f63b52f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248876461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1248876461
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.411868731
Short name T377
Test name
Test status
Simulation time 1822013598 ps
CPU time 14.31 seconds
Started Jul 17 05:50:26 PM PDT 24
Finished Jul 17 05:50:41 PM PDT 24
Peak memory 213548 kb
Host smart-e5aabf75-e86d-4f82-aced-706a6312c2e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411868731 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.411868731
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1503740948
Short name T391
Test name
Test status
Simulation time 676883477 ps
CPU time 8.29 seconds
Started Jul 17 05:50:26 PM PDT 24
Finished Jul 17 05:50:36 PM PDT 24
Peak memory 210276 kb
Host smart-231c6f98-0ecb-4c7f-829f-6a1d2d900a02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503740948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1503740948
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1653463983
Short name T100
Test name
Test status
Simulation time 35069560685 ps
CPU time 77.19 seconds
Started Jul 17 05:50:27 PM PDT 24
Finished Jul 17 05:51:45 PM PDT 24
Peak memory 210472 kb
Host smart-5d3ed784-5fa0-4229-bc0e-d17459b88b99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653463983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1653463983
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.415319476
Short name T409
Test name
Test status
Simulation time 784987973 ps
CPU time 10.47 seconds
Started Jul 17 05:50:20 PM PDT 24
Finished Jul 17 05:50:32 PM PDT 24
Peak memory 210420 kb
Host smart-49ba871b-00e7-48a5-852d-6101a1ee85ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415319476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.415319476
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1202827563
Short name T458
Test name
Test status
Simulation time 347654357 ps
CPU time 6.38 seconds
Started Jul 17 05:50:20 PM PDT 24
Finished Jul 17 05:50:28 PM PDT 24
Peak memory 218584 kb
Host smart-67f11d01-724b-42cc-9499-9a9d2ad2bc38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202827563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1202827563
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1641152617
Short name T112
Test name
Test status
Simulation time 6154820237 ps
CPU time 70.89 seconds
Started Jul 17 05:50:30 PM PDT 24
Finished Jul 17 05:51:43 PM PDT 24
Peak memory 218624 kb
Host smart-2a37f5bb-cb5f-448c-9067-d95300912263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641152617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1641152617
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4002572370
Short name T92
Test name
Test status
Simulation time 1702075174 ps
CPU time 12.24 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:50:09 PM PDT 24
Peak memory 210296 kb
Host smart-8ac12785-1b39-43b5-ba01-3215ada29805
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002572370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4002572370
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4060329878
Short name T442
Test name
Test status
Simulation time 581272243 ps
CPU time 6.47 seconds
Started Jul 17 05:49:59 PM PDT 24
Finished Jul 17 05:50:08 PM PDT 24
Peak memory 210300 kb
Host smart-7c151d30-4718-443d-a7a6-4e24cc95b893
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060329878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4060329878
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2513811594
Short name T450
Test name
Test status
Simulation time 297261413 ps
CPU time 7.62 seconds
Started Jul 17 05:49:57 PM PDT 24
Finished Jul 17 05:50:08 PM PDT 24
Peak memory 210272 kb
Host smart-d3535297-0830-480d-b8de-5116eedbe319
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513811594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2513811594
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2765863179
Short name T375
Test name
Test status
Simulation time 1502222004 ps
CPU time 9.32 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:50:07 PM PDT 24
Peak memory 218596 kb
Host smart-c34b0295-f62d-4db7-bbcb-f7d0f87a8413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765863179 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2765863179
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1014574035
Short name T416
Test name
Test status
Simulation time 171510671 ps
CPU time 4.22 seconds
Started Jul 17 05:49:57 PM PDT 24
Finished Jul 17 05:50:04 PM PDT 24
Peak memory 210268 kb
Host smart-b333ca97-b5e5-43d9-8d0f-793cd4050a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014574035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1014574035
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1117109629
Short name T395
Test name
Test status
Simulation time 1310231199 ps
CPU time 6.32 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:50:02 PM PDT 24
Peak memory 210164 kb
Host smart-80162896-1e9d-4578-a274-21fd278c3722
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117109629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1117109629
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4004299782
Short name T402
Test name
Test status
Simulation time 2070841889 ps
CPU time 10.57 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:50:06 PM PDT 24
Peak memory 210200 kb
Host smart-07e675e6-0a8d-49e2-b8b7-d09df9a68d79
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004299782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4004299782
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.782870232
Short name T411
Test name
Test status
Simulation time 12119722866 ps
CPU time 52.52 seconds
Started Jul 17 05:50:00 PM PDT 24
Finished Jul 17 05:50:54 PM PDT 24
Peak memory 210412 kb
Host smart-bec881a2-54b4-402f-8d9c-d6d826ee2694
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782870232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.782870232
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2498056066
Short name T80
Test name
Test status
Simulation time 3307305104 ps
CPU time 11.63 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:50:06 PM PDT 24
Peak memory 210492 kb
Host smart-a107ca88-1c2c-4613-be00-0a1b87827c9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498056066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2498056066
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3277293877
Short name T468
Test name
Test status
Simulation time 171278573 ps
CPU time 6.38 seconds
Started Jul 17 05:49:58 PM PDT 24
Finished Jul 17 05:50:07 PM PDT 24
Peak memory 218572 kb
Host smart-2a5c8171-af59-4011-9668-5f286ee5c417
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277293877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3277293877
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1537120160
Short name T72
Test name
Test status
Simulation time 6366023340 ps
CPU time 13.33 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:50:22 PM PDT 24
Peak memory 210384 kb
Host smart-b045b65d-2554-4996-b3d9-65a23332a056
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537120160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1537120160
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3909720920
Short name T400
Test name
Test status
Simulation time 25230054591 ps
CPU time 15.23 seconds
Started Jul 17 05:50:16 PM PDT 24
Finished Jul 17 05:50:32 PM PDT 24
Peak memory 210136 kb
Host smart-653268e0-5482-4f7e-8820-c99e9b90fd46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909720920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3909720920
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.118289968
Short name T438
Test name
Test status
Simulation time 168761854 ps
CPU time 6.73 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:19 PM PDT 24
Peak memory 210336 kb
Host smart-0f81a923-ab79-4b13-854e-b50670278288
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118289968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.118289968
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.426336789
Short name T430
Test name
Test status
Simulation time 328974811 ps
CPU time 4.8 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:19 PM PDT 24
Peak memory 218588 kb
Host smart-4cd83bb5-d3f8-44ee-bf30-2d55e3f0fb4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426336789 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.426336789
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.90057978
Short name T376
Test name
Test status
Simulation time 85762078 ps
CPU time 4.31 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:50:15 PM PDT 24
Peak memory 217468 kb
Host smart-337df55b-932d-4948-ac3b-e1dd75734021
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90057978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.90057978
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3507655012
Short name T444
Test name
Test status
Simulation time 5125686295 ps
CPU time 12 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:11 PM PDT 24
Peak memory 210236 kb
Host smart-84dac3fc-93c4-4202-8404-6aca3bd6f308
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507655012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3507655012
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.438793926
Short name T392
Test name
Test status
Simulation time 525584297 ps
CPU time 6.33 seconds
Started Jul 17 05:49:59 PM PDT 24
Finished Jul 17 05:50:07 PM PDT 24
Peak memory 210192 kb
Host smart-b5c710aa-6003-4742-b96b-730381a262b3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438793926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
438793926
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2487347950
Short name T90
Test name
Test status
Simulation time 7185001087 ps
CPU time 59.09 seconds
Started Jul 17 05:49:59 PM PDT 24
Finished Jul 17 05:51:00 PM PDT 24
Peak memory 210460 kb
Host smart-6408ce0a-f773-4bd0-84e1-ad805282c580
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487347950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2487347950
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1634977712
Short name T437
Test name
Test status
Simulation time 692148740 ps
CPU time 4.22 seconds
Started Jul 17 05:50:07 PM PDT 24
Finished Jul 17 05:50:12 PM PDT 24
Peak memory 210420 kb
Host smart-c428e850-b0ad-4239-9c3b-57eded0edc50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634977712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1634977712
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4125740983
Short name T443
Test name
Test status
Simulation time 94608833 ps
CPU time 6.27 seconds
Started Jul 17 05:49:57 PM PDT 24
Finished Jul 17 05:50:06 PM PDT 24
Peak memory 218568 kb
Host smart-4076158f-d8de-4b2a-a951-fcf7851acacd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125740983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4125740983
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.834062272
Short name T121
Test name
Test status
Simulation time 426686463 ps
CPU time 38.85 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:50:33 PM PDT 24
Peak memory 210940 kb
Host smart-7e48f149-58e5-4811-bcda-0ab3920f06f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834062272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.834062272
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3617797485
Short name T91
Test name
Test status
Simulation time 7516399476 ps
CPU time 15.54 seconds
Started Jul 17 05:50:10 PM PDT 24
Finished Jul 17 05:50:29 PM PDT 24
Peak memory 218540 kb
Host smart-fdfcb97e-24a4-4156-a924-f343225fe546
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617797485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3617797485
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2123149654
Short name T387
Test name
Test status
Simulation time 2061595216 ps
CPU time 7.35 seconds
Started Jul 17 05:50:10 PM PDT 24
Finished Jul 17 05:50:20 PM PDT 24
Peak memory 210260 kb
Host smart-1f1af4ac-f436-4421-86ee-a6a578e86c87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123149654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2123149654
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1721367377
Short name T73
Test name
Test status
Simulation time 2791856950 ps
CPU time 13.33 seconds
Started Jul 17 05:50:12 PM PDT 24
Finished Jul 17 05:50:28 PM PDT 24
Peak memory 210388 kb
Host smart-8f1f2351-2c8e-48e2-8553-ebc7fed4a999
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721367377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1721367377
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2757592962
Short name T412
Test name
Test status
Simulation time 2434556957 ps
CPU time 10.91 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:25 PM PDT 24
Peak memory 218716 kb
Host smart-76281d26-8470-47d2-a3f7-1449c28b09f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757592962 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2757592962
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1816254
Short name T403
Test name
Test status
Simulation time 568116613 ps
CPU time 5.27 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:16 PM PDT 24
Peak memory 217352 kb
Host smart-02dec2c4-5c0a-478a-bc55-35d6a0ae871e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1816254
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3055125067
Short name T456
Test name
Test status
Simulation time 17243650260 ps
CPU time 14.15 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:50:24 PM PDT 24
Peak memory 210228 kb
Host smart-c06390e7-1844-44e6-91c1-a37dd53fe3ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055125067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3055125067
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3955721567
Short name T415
Test name
Test status
Simulation time 657804530 ps
CPU time 6.27 seconds
Started Jul 17 05:50:10 PM PDT 24
Finished Jul 17 05:50:19 PM PDT 24
Peak memory 210092 kb
Host smart-bb976f22-7e1b-41df-8f13-19a2afd706cb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955721567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3955721567
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1308433009
Short name T420
Test name
Test status
Simulation time 1568199201 ps
CPU time 17.83 seconds
Started Jul 17 05:50:16 PM PDT 24
Finished Jul 17 05:50:35 PM PDT 24
Peak memory 210256 kb
Host smart-247a0681-fa9d-42ed-a64b-367993b066fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308433009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1308433009
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.823089843
Short name T76
Test name
Test status
Simulation time 500644070 ps
CPU time 7.74 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:19 PM PDT 24
Peak memory 210384 kb
Host smart-8403303e-21c8-4dce-bd61-ab81fa8a408d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823089843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.823089843
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2746081586
Short name T385
Test name
Test status
Simulation time 2017053908 ps
CPU time 20.28 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:32 PM PDT 24
Peak memory 218568 kb
Host smart-7e6d6092-965a-457c-bf01-31c950656c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746081586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2746081586
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.326108230
Short name T111
Test name
Test status
Simulation time 4137680677 ps
CPU time 70.75 seconds
Started Jul 17 05:50:16 PM PDT 24
Finished Jul 17 05:51:28 PM PDT 24
Peak memory 218420 kb
Host smart-2f9f8a1b-ca7b-4b84-be2a-8a9663708c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326108230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.326108230
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1374677387
Short name T406
Test name
Test status
Simulation time 4134749573 ps
CPU time 11.91 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:50:22 PM PDT 24
Peak memory 218704 kb
Host smart-0d97c0f2-2353-4839-816e-bde4555d49fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374677387 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1374677387
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2906098602
Short name T103
Test name
Test status
Simulation time 3684623883 ps
CPU time 15.57 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:27 PM PDT 24
Peak memory 218444 kb
Host smart-531b5e12-d302-4930-a4bf-e210f55d80b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906098602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2906098602
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2095493580
Short name T106
Test name
Test status
Simulation time 21599508773 ps
CPU time 98.24 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:51:47 PM PDT 24
Peak memory 210484 kb
Host smart-ee53dd72-5b65-4f32-93bd-95a3f64b1910
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095493580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2095493580
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.158560895
Short name T446
Test name
Test status
Simulation time 4245034663 ps
CPU time 10.43 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:25 PM PDT 24
Peak memory 217992 kb
Host smart-e7327ae3-cdd0-4b9b-bb86-f83457ffd6b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158560895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.158560895
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1206833327
Short name T462
Test name
Test status
Simulation time 107499583 ps
CPU time 7.11 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:50:17 PM PDT 24
Peak memory 218600 kb
Host smart-636d38eb-caa8-4c98-8f06-89a07ebcd88e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206833327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1206833327
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2368594056
Short name T113
Test name
Test status
Simulation time 1713033163 ps
CPU time 75.44 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:51:25 PM PDT 24
Peak memory 211892 kb
Host smart-e9c9733d-f38c-4e42-af87-8832a6ac6638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368594056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2368594056
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4222312638
Short name T407
Test name
Test status
Simulation time 2627853888 ps
CPU time 5.4 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:17 PM PDT 24
Peak memory 213444 kb
Host smart-ee6031cb-1cd2-4e6d-92b0-a7a505de2c6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222312638 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4222312638
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2312884768
Short name T422
Test name
Test status
Simulation time 660683486 ps
CPU time 8.39 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:20 PM PDT 24
Peak memory 210276 kb
Host smart-868808d8-7a43-440c-87e3-752a3ffd982f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312884768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2312884768
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2578831022
Short name T89
Test name
Test status
Simulation time 34626263009 ps
CPU time 76.17 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:51:26 PM PDT 24
Peak memory 210432 kb
Host smart-34888f2b-6608-4c5f-99d8-ac848a85521a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578831022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2578831022
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1026614052
Short name T102
Test name
Test status
Simulation time 2719714517 ps
CPU time 16.15 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:30 PM PDT 24
Peak memory 218524 kb
Host smart-8b5597ef-4b0a-47ff-a47e-78eae605d23d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026614052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1026614052
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2587994715
Short name T380
Test name
Test status
Simulation time 126082652 ps
CPU time 8.6 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:20 PM PDT 24
Peak memory 218596 kb
Host smart-e250b974-a7fb-4a0f-9a9d-d5e56f69a3b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587994715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2587994715
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3447614288
Short name T439
Test name
Test status
Simulation time 743543316 ps
CPU time 8.74 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:20 PM PDT 24
Peak memory 218528 kb
Host smart-787e2575-3d01-4b03-8702-29cbafc7525a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447614288 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3447614288
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1138786558
Short name T410
Test name
Test status
Simulation time 23906687934 ps
CPU time 14.54 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:29 PM PDT 24
Peak memory 218484 kb
Host smart-48f30f82-03fe-4e1f-a008-4bb0357ab699
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138786558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1138786558
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3186395746
Short name T96
Test name
Test status
Simulation time 548807586 ps
CPU time 27.83 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:43 PM PDT 24
Peak memory 210356 kb
Host smart-0c7a0c44-0001-4322-84c4-0e9e6e2d740d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186395746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3186395746
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.43906967
Short name T101
Test name
Test status
Simulation time 5235468736 ps
CPU time 13.52 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:27 PM PDT 24
Peak memory 218584 kb
Host smart-8e8f368a-fcf1-47d5-bba5-2ee3454b938e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43906967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctr
l_same_csr_outstanding.43906967
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.500635324
Short name T449
Test name
Test status
Simulation time 3570881282 ps
CPU time 14.16 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:25 PM PDT 24
Peak memory 218612 kb
Host smart-22479b3a-52d2-4d58-ab26-719d6adcaea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500635324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.500635324
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1771171979
Short name T115
Test name
Test status
Simulation time 3360753563 ps
CPU time 67.07 seconds
Started Jul 17 05:50:15 PM PDT 24
Finished Jul 17 05:51:23 PM PDT 24
Peak memory 218572 kb
Host smart-0bc891d3-15e1-4136-8e96-f2c243b54253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771171979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1771171979
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1135528552
Short name T389
Test name
Test status
Simulation time 2212747297 ps
CPU time 14.77 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:29 PM PDT 24
Peak memory 212560 kb
Host smart-1e8fee3e-4df2-4bca-8728-9816038b901e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135528552 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1135528552
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1623041383
Short name T441
Test name
Test status
Simulation time 4754344868 ps
CPU time 11.64 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:24 PM PDT 24
Peak memory 210312 kb
Host smart-ee370363-ff6a-4370-b4e3-526c489fb1be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623041383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1623041383
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1230898888
Short name T414
Test name
Test status
Simulation time 1328157629 ps
CPU time 7.54 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:19 PM PDT 24
Peak memory 217420 kb
Host smart-e269657c-4f6d-42ce-b7c1-71c38177707f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230898888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1230898888
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1346860034
Short name T373
Test name
Test status
Simulation time 1164454440 ps
CPU time 13.34 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:50:24 PM PDT 24
Peak memory 218552 kb
Host smart-2471d4a5-70e6-4c5c-bc14-2db4da25b1f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346860034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1346860034
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2512133617
Short name T114
Test name
Test status
Simulation time 293583833 ps
CPU time 37.29 seconds
Started Jul 17 05:50:09 PM PDT 24
Finished Jul 17 05:50:50 PM PDT 24
Peak memory 218488 kb
Host smart-5a686749-57b0-4c22-9d54-fe9480e2aba6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512133617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2512133617
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2642087063
Short name T448
Test name
Test status
Simulation time 2480752484 ps
CPU time 8.62 seconds
Started Jul 17 05:50:08 PM PDT 24
Finished Jul 17 05:50:19 PM PDT 24
Peak memory 218640 kb
Host smart-918981a1-6969-4a16-9509-0421b60a84ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642087063 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2642087063
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.583774737
Short name T421
Test name
Test status
Simulation time 436991108 ps
CPU time 4.19 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:19 PM PDT 24
Peak memory 218368 kb
Host smart-4f94af90-1cd6-4c31-81b3-3e866e75565a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583774737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.583774737
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2711325593
Short name T469
Test name
Test status
Simulation time 30841645328 ps
CPU time 66.77 seconds
Started Jul 17 05:50:10 PM PDT 24
Finished Jul 17 05:51:19 PM PDT 24
Peak memory 210372 kb
Host smart-791ac085-8db8-4786-a8bd-94ff011bca90
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711325593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2711325593
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.854840161
Short name T405
Test name
Test status
Simulation time 3757298789 ps
CPU time 10.57 seconds
Started Jul 17 05:50:11 PM PDT 24
Finished Jul 17 05:50:25 PM PDT 24
Peak memory 210412 kb
Host smart-f631d74e-0884-4494-a30c-72c4e1475722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854840161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.854840161
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1818166454
Short name T381
Test name
Test status
Simulation time 88042615 ps
CPU time 8.51 seconds
Started Jul 17 05:50:18 PM PDT 24
Finished Jul 17 05:50:28 PM PDT 24
Peak memory 218596 kb
Host smart-94234599-9e95-4d83-a9d7-1ba5faaa1f84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818166454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1818166454
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1984384268
Short name T117
Test name
Test status
Simulation time 14946593127 ps
CPU time 41.82 seconds
Started Jul 17 05:50:10 PM PDT 24
Finished Jul 17 05:50:55 PM PDT 24
Peak memory 211740 kb
Host smart-de006e41-01de-4f81-8e58-05d12aaec5dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984384268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1984384268
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3029536798
Short name T220
Test name
Test status
Simulation time 2165947381 ps
CPU time 10.96 seconds
Started Jul 17 07:01:50 PM PDT 24
Finished Jul 17 07:02:02 PM PDT 24
Peak memory 211384 kb
Host smart-6d20f124-689e-4fd2-9b58-2a03fd7900bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029536798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3029536798
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1979453351
Short name T229
Test name
Test status
Simulation time 71530641688 ps
CPU time 155.49 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:04:31 PM PDT 24
Peak memory 236900 kb
Host smart-6d725b77-6c7a-4225-85b0-1c6341866892
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979453351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1979453351
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2696708693
Short name T326
Test name
Test status
Simulation time 2788395210 ps
CPU time 25.98 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 07:02:27 PM PDT 24
Peak memory 211880 kb
Host smart-b483f732-2801-4ae3-b8b7-9d15a5e2df70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696708693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2696708693
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3010049529
Short name T352
Test name
Test status
Simulation time 444317783 ps
CPU time 5.82 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:01:59 PM PDT 24
Peak memory 211368 kb
Host smart-f824765b-bc0d-4280-91d4-1f835667b209
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010049529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3010049529
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1772578363
Short name T25
Test name
Test status
Simulation time 3461418517 ps
CPU time 54.94 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:02:50 PM PDT 24
Peak memory 235720 kb
Host smart-2ef4d610-acfd-49c6-9043-7bfa60b43ec7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772578363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1772578363
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1145538261
Short name T256
Test name
Test status
Simulation time 3582982690 ps
CPU time 10.86 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:02:04 PM PDT 24
Peak memory 213788 kb
Host smart-b4c9362d-7c49-475a-9679-d3d4d9752a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145538261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1145538261
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2744679746
Short name T146
Test name
Test status
Simulation time 415962755 ps
CPU time 9.48 seconds
Started Jul 17 07:01:49 PM PDT 24
Finished Jul 17 07:02:00 PM PDT 24
Peak memory 211388 kb
Host smart-588850cf-71a0-4732-a49f-8512ae70567f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744679746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2744679746
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4153355441
Short name T131
Test name
Test status
Simulation time 1834798241 ps
CPU time 7.35 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:02:03 PM PDT 24
Peak memory 211320 kb
Host smart-61166cda-2dcb-4adb-a505-99f49442bef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153355441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4153355441
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2935776376
Short name T183
Test name
Test status
Simulation time 397195848771 ps
CPU time 294.19 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:06:49 PM PDT 24
Peak memory 212664 kb
Host smart-2fa961e6-fd2e-432d-95f8-234c19519172
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935776376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2935776376
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2731481866
Short name T262
Test name
Test status
Simulation time 179776756 ps
CPU time 9.56 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:02:04 PM PDT 24
Peak memory 212244 kb
Host smart-bac78bec-b63d-4d61-8ffa-f886551fbfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731481866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2731481866
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.854278552
Short name T196
Test name
Test status
Simulation time 11749159562 ps
CPU time 15.12 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:02:08 PM PDT 24
Peak memory 211460 kb
Host smart-94688ebf-2fac-43e4-ba3e-52dffabebe3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854278552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.854278552
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.170899709
Short name T26
Test name
Test status
Simulation time 9231943473 ps
CPU time 61.3 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 237988 kb
Host smart-589a5312-4c0a-47a1-a015-d2f5c06f0d56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170899709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.170899709
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2461918699
Short name T283
Test name
Test status
Simulation time 12283213753 ps
CPU time 29.23 seconds
Started Jul 17 07:01:46 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 214116 kb
Host smart-0a5cb94b-8240-4c65-a6f2-faba8eabb6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461918699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2461918699
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3755338624
Short name T240
Test name
Test status
Simulation time 387035996 ps
CPU time 19.99 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:02:13 PM PDT 24
Peak memory 215108 kb
Host smart-25e675aa-cefd-4754-bdc5-3965d0314c8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755338624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3755338624
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2508074283
Short name T138
Test name
Test status
Simulation time 374033591 ps
CPU time 6.73 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:13 PM PDT 24
Peak memory 211336 kb
Host smart-f818e9dd-0e10-4cb7-8c30-afc72f7df950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508074283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2508074283
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1046662222
Short name T30
Test name
Test status
Simulation time 51703927813 ps
CPU time 168.13 seconds
Started Jul 17 07:01:42 PM PDT 24
Finished Jul 17 07:04:33 PM PDT 24
Peak memory 227812 kb
Host smart-a54ffbaf-d50c-4d7d-82c5-46b6fe176937
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046662222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1046662222
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1166164387
Short name T5
Test name
Test status
Simulation time 638758045 ps
CPU time 9.28 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 212016 kb
Host smart-f637b0f2-aa20-4c98-b604-6fff57fb99a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166164387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1166164387
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1504903207
Short name T216
Test name
Test status
Simulation time 2077792033 ps
CPU time 16.11 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:20 PM PDT 24
Peak memory 211400 kb
Host smart-35502f86-471d-4dbc-b71e-d65b7ca1e3cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504903207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1504903207
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.900358089
Short name T227
Test name
Test status
Simulation time 5914913438 ps
CPU time 33.79 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 07:02:36 PM PDT 24
Peak memory 213624 kb
Host smart-9d66a1bd-60be-4276-9d9f-16e48b6f8e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900358089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.900358089
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1184419466
Short name T340
Test name
Test status
Simulation time 7613637492 ps
CPU time 41.63 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:45 PM PDT 24
Peak memory 215032 kb
Host smart-74e30782-4c99-4f36-a89e-a08e1dfac960
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184419466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1184419466
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3176003342
Short name T149
Test name
Test status
Simulation time 2840620081 ps
CPU time 12.56 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 211356 kb
Host smart-5569698e-1eda-4f12-9b01-b8f58341b77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176003342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3176003342
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1487763240
Short name T325
Test name
Test status
Simulation time 27251490945 ps
CPU time 208.55 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:05:36 PM PDT 24
Peak memory 212648 kb
Host smart-e96383d2-75a2-44ca-b494-57629a300893
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487763240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1487763240
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3391768433
Short name T318
Test name
Test status
Simulation time 922512882 ps
CPU time 9.44 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 211904 kb
Host smart-df8af406-efc3-4e74-9066-5a983b0012ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391768433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3391768433
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.860030517
Short name T335
Test name
Test status
Simulation time 8005422341 ps
CPU time 13.23 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:20 PM PDT 24
Peak memory 211428 kb
Host smart-b0c06992-953c-4af0-afcb-5d34d4b1ff74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860030517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.860030517
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1526430481
Short name T157
Test name
Test status
Simulation time 61824761966 ps
CPU time 35.03 seconds
Started Jul 17 07:01:39 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 214076 kb
Host smart-d303489a-455c-4742-9fad-cab4cc14baf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526430481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1526430481
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2023303562
Short name T126
Test name
Test status
Simulation time 442046139 ps
CPU time 6.66 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:13 PM PDT 24
Peak memory 211260 kb
Host smart-a87ca3b2-53ff-4dc0-9b8c-65b4ac0e1397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023303562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2023303562
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2157467424
Short name T226
Test name
Test status
Simulation time 1071187255 ps
CPU time 10.68 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 211324 kb
Host smart-a6e091f5-f29e-4498-8721-6baef518e28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157467424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2157467424
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1993290294
Short name T41
Test name
Test status
Simulation time 23141762754 ps
CPU time 321.2 seconds
Started Jul 17 07:01:37 PM PDT 24
Finished Jul 17 07:06:59 PM PDT 24
Peak memory 225732 kb
Host smart-7db67d65-da09-4bc3-965e-16061ed379da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993290294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1993290294
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3146505383
Short name T292
Test name
Test status
Simulation time 1187690263 ps
CPU time 9.43 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:14 PM PDT 24
Peak memory 211996 kb
Host smart-8a07da28-2d2b-4bc9-84da-b15b580e259e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146505383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3146505383
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2353446106
Short name T144
Test name
Test status
Simulation time 2738736586 ps
CPU time 9.24 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 211412 kb
Host smart-4dad431c-0752-4e43-bb59-1552563839c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353446106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2353446106
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1663444284
Short name T309
Test name
Test status
Simulation time 44433692135 ps
CPU time 99 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:03:46 PM PDT 24
Peak memory 219388 kb
Host smart-e0ad8cf9-f0b1-4a35-b6c5-44f34d632dac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663444284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1663444284
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3687174181
Short name T260
Test name
Test status
Simulation time 499514555 ps
CPU time 5.01 seconds
Started Jul 17 07:01:40 PM PDT 24
Finished Jul 17 07:01:47 PM PDT 24
Peak memory 211368 kb
Host smart-e6f97cde-69d8-48a9-8172-3ef2bce3f5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687174181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3687174181
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3678867823
Short name T32
Test name
Test status
Simulation time 63174545038 ps
CPU time 246.48 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:06:18 PM PDT 24
Peak memory 237804 kb
Host smart-9349b579-0503-4404-a5c5-f0684d1438d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678867823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3678867823
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.568034704
Short name T251
Test name
Test status
Simulation time 17714327540 ps
CPU time 33.36 seconds
Started Jul 17 07:02:04 PM PDT 24
Finished Jul 17 07:02:45 PM PDT 24
Peak memory 212224 kb
Host smart-f18881a8-2393-49fa-aaf0-fa02bc1d25ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568034704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.568034704
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2353697867
Short name T142
Test name
Test status
Simulation time 11278620567 ps
CPU time 15.65 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:24 PM PDT 24
Peak memory 211420 kb
Host smart-1644d43c-a9d8-415b-acec-00be5e57fc41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353697867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2353697867
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1696175816
Short name T365
Test name
Test status
Simulation time 2122924904 ps
CPU time 20.72 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:29 PM PDT 24
Peak memory 213068 kb
Host smart-f3b44868-4b45-4c59-9433-a86c7f5e1b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696175816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1696175816
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2376794955
Short name T254
Test name
Test status
Simulation time 19181586469 ps
CPU time 51.77 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 215848 kb
Host smart-32c732cc-47c5-48f2-a4ac-5aa15e6180c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376794955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2376794955
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.919603571
Short name T218
Test name
Test status
Simulation time 10979349562 ps
CPU time 408.24 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:09:00 PM PDT 24
Peak memory 230220 kb
Host smart-89fc1954-ea6c-4bca-81bb-a145acf1383e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919603571 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.919603571
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.4198443352
Short name T132
Test name
Test status
Simulation time 3862681412 ps
CPU time 15.62 seconds
Started Jul 17 07:01:42 PM PDT 24
Finished Jul 17 07:01:59 PM PDT 24
Peak memory 211548 kb
Host smart-4d970b4d-5ec1-4b63-8375-1b941fc4871e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198443352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.4198443352
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3164448514
Short name T250
Test name
Test status
Simulation time 1858637210 ps
CPU time 111.56 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:04:00 PM PDT 24
Peak memory 237832 kb
Host smart-679fb21d-1582-44f9-a136-b6004842e098
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164448514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3164448514
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1315920713
Short name T211
Test name
Test status
Simulation time 11913960904 ps
CPU time 23.9 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:02:36 PM PDT 24
Peak memory 212260 kb
Host smart-e0a0be47-98ad-46a6-9425-ca8f915c4917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315920713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1315920713
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1762082792
Short name T29
Test name
Test status
Simulation time 32198999472 ps
CPU time 16.3 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:25 PM PDT 24
Peak memory 211464 kb
Host smart-32490b73-e6de-44e0-8901-ef77429ba5c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762082792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1762082792
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2573489552
Short name T81
Test name
Test status
Simulation time 16453688174 ps
CPU time 36.39 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:44 PM PDT 24
Peak memory 213636 kb
Host smart-b25eeb96-c21d-4177-a174-6e54f1d1b309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573489552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2573489552
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.4133592580
Short name T245
Test name
Test status
Simulation time 3631490708 ps
CPU time 38.16 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:02:50 PM PDT 24
Peak memory 216132 kb
Host smart-f1859b10-e81d-4e8c-8505-c40446c4decd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133592580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.4133592580
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1600316300
Short name T61
Test name
Test status
Simulation time 147574121757 ps
CPU time 2885.61 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:50:14 PM PDT 24
Peak memory 244072 kb
Host smart-d59a7b69-c8d0-445c-9266-f81cfba7e356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600316300 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1600316300
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2570396384
Short name T47
Test name
Test status
Simulation time 1100658120 ps
CPU time 10.56 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 211144 kb
Host smart-74a7fe8c-6310-40d0-84b6-42dc6f7dab0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570396384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2570396384
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2674612919
Short name T311
Test name
Test status
Simulation time 46085629210 ps
CPU time 495.04 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:10:26 PM PDT 24
Peak memory 236940 kb
Host smart-c1cf0927-432c-42b3-9f2e-255552964674
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674612919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2674612919
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2223473494
Short name T33
Test name
Test status
Simulation time 2897930555 ps
CPU time 25.81 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:32 PM PDT 24
Peak memory 212716 kb
Host smart-96844685-b3eb-4899-ad4f-c81d623d6f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223473494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2223473494
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3318254030
Short name T299
Test name
Test status
Simulation time 6631349081 ps
CPU time 11.5 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:20 PM PDT 24
Peak memory 211444 kb
Host smart-34c29b5f-5ccf-48d9-b716-330f7e2ea9d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3318254030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3318254030
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1705226820
Short name T271
Test name
Test status
Simulation time 1775768611 ps
CPU time 19.09 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:27 PM PDT 24
Peak memory 213416 kb
Host smart-99777f90-bb0a-4fa6-bf18-fb96134a7a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705226820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1705226820
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1178496268
Short name T122
Test name
Test status
Simulation time 18197432901 ps
CPU time 40.66 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:49 PM PDT 24
Peak memory 217032 kb
Host smart-b6d4d66c-3bd3-4e5c-8843-970003236d5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178496268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1178496268
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2136706676
Short name T105
Test name
Test status
Simulation time 43599356506 ps
CPU time 1590.51 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:28:36 PM PDT 24
Peak memory 235816 kb
Host smart-6c9e94d9-a905-4b59-98ff-bfb22e378efd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136706676 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2136706676
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.760877284
Short name T272
Test name
Test status
Simulation time 7896591908 ps
CPU time 15.59 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:13 PM PDT 24
Peak memory 211420 kb
Host smart-c3a80fcc-0380-45b1-ae79-b924ff101c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760877284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.760877284
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3091761456
Short name T263
Test name
Test status
Simulation time 14581804897 ps
CPU time 125.51 seconds
Started Jul 17 07:01:43 PM PDT 24
Finished Jul 17 07:03:50 PM PDT 24
Peak memory 236928 kb
Host smart-06271372-c8a1-441b-855e-039a5079ab0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091761456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3091761456
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1364287493
Short name T342
Test name
Test status
Simulation time 1014075449 ps
CPU time 15.96 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 212196 kb
Host smart-de3a6a8a-2db8-46bc-a21c-1643db0bcff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364287493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1364287493
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2100025017
Short name T248
Test name
Test status
Simulation time 2908734754 ps
CPU time 14.8 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 211356 kb
Host smart-b8dc7884-b841-49e0-9029-89388049061f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100025017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2100025017
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2324172485
Short name T294
Test name
Test status
Simulation time 1637999345 ps
CPU time 15.44 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:20 PM PDT 24
Peak memory 213044 kb
Host smart-5c24533b-999c-4e73-8f61-709245adfbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324172485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2324172485
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.188791634
Short name T171
Test name
Test status
Simulation time 2709143684 ps
CPU time 39.63 seconds
Started Jul 17 07:01:42 PM PDT 24
Finished Jul 17 07:02:24 PM PDT 24
Peak memory 215280 kb
Host smart-18a9c614-9e8e-4980-b8e6-6becf9a6ab03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188791634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.188791634
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.4151104957
Short name T249
Test name
Test status
Simulation time 190124181182 ps
CPU time 1980.49 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:35:06 PM PDT 24
Peak memory 239620 kb
Host smart-9a7f16cf-107a-4e61-93c1-9f1a7b572c24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151104957 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.4151104957
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1627564380
Short name T336
Test name
Test status
Simulation time 1237806324 ps
CPU time 10.9 seconds
Started Jul 17 07:01:42 PM PDT 24
Finished Jul 17 07:01:55 PM PDT 24
Peak memory 211312 kb
Host smart-7543a9cb-2925-49bf-b8d3-9b52691cb6bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627564380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1627564380
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4045955205
Short name T221
Test name
Test status
Simulation time 244062837241 ps
CPU time 345.96 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:07:50 PM PDT 24
Peak memory 225108 kb
Host smart-50487142-eca9-4742-84ed-f792a585667c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045955205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4045955205
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2231606163
Short name T184
Test name
Test status
Simulation time 2584324316 ps
CPU time 23.73 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:30 PM PDT 24
Peak memory 211912 kb
Host smart-da337443-2f90-4461-8d55-8facbdfbe232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231606163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2231606163
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1582453215
Short name T128
Test name
Test status
Simulation time 101046745 ps
CPU time 5.76 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:09 PM PDT 24
Peak memory 211368 kb
Host smart-9961601e-39e1-4c3e-b385-3150a26f85b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582453215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1582453215
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.710983054
Short name T333
Test name
Test status
Simulation time 807361792 ps
CPU time 9.83 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 213588 kb
Host smart-2ee75e74-1df6-4615-a8bc-b9aa2c1bd1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710983054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.710983054
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3432022428
Short name T163
Test name
Test status
Simulation time 9300172994 ps
CPU time 78.82 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:03:23 PM PDT 24
Peak memory 218320 kb
Host smart-f0b2b3c1-22ae-4f59-aeb5-20406de60077
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432022428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3432022428
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3918278729
Short name T2
Test name
Test status
Simulation time 530075176 ps
CPU time 5.65 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:14 PM PDT 24
Peak memory 211320 kb
Host smart-be9ab275-ea57-4a6a-bbbf-ae5a1c1af2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918278729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3918278729
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.71107253
Short name T199
Test name
Test status
Simulation time 61638534810 ps
CPU time 303.13 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:07:10 PM PDT 24
Peak memory 237896 kb
Host smart-a705e213-a7e9-4abb-8013-b21b16e66e4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71107253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_co
rrupt_sig_fatal_chk.71107253
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2554467263
Short name T276
Test name
Test status
Simulation time 2212624480 ps
CPU time 22.54 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:02:34 PM PDT 24
Peak memory 212080 kb
Host smart-f82678b2-778c-47b8-a71a-fb8373793bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554467263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2554467263
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1215642527
Short name T8
Test name
Test status
Simulation time 18327062278 ps
CPU time 14.63 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:22 PM PDT 24
Peak memory 211456 kb
Host smart-1176017e-4551-4578-a113-4a6b01d9c3b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215642527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1215642527
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1815490743
Short name T281
Test name
Test status
Simulation time 388481111 ps
CPU time 12.99 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:20 PM PDT 24
Peak memory 213680 kb
Host smart-48861cfa-f769-4c25-890b-416d53ea3654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815490743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1815490743
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2651338436
Short name T84
Test name
Test status
Simulation time 16171430734 ps
CPU time 35 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 215304 kb
Host smart-ac2fab1a-86f5-488b-893e-cc5a7e811eaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651338436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2651338436
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1803669294
Short name T139
Test name
Test status
Simulation time 171179325 ps
CPU time 4.29 seconds
Started Jul 17 07:01:39 PM PDT 24
Finished Jul 17 07:01:45 PM PDT 24
Peak memory 211356 kb
Host smart-3cec6e75-549d-4b28-89ae-42597c299935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803669294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1803669294
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3236420533
Short name T247
Test name
Test status
Simulation time 2138270849 ps
CPU time 125.34 seconds
Started Jul 17 07:01:38 PM PDT 24
Finished Jul 17 07:03:44 PM PDT 24
Peak memory 212592 kb
Host smart-43de3371-8052-4475-aeda-44c07d6ea15b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236420533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3236420533
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1349839792
Short name T174
Test name
Test status
Simulation time 17190066394 ps
CPU time 34.39 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:42 PM PDT 24
Peak memory 212372 kb
Host smart-5d8e2146-59a5-482e-8cb7-895bd443269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349839792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1349839792
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1417014977
Short name T358
Test name
Test status
Simulation time 6869348642 ps
CPU time 12.75 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 211396 kb
Host smart-9a58c5c9-6da5-4860-bafe-8de971225722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417014977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1417014977
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2190118486
Short name T278
Test name
Test status
Simulation time 1125892598 ps
CPU time 10.02 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:02:22 PM PDT 24
Peak memory 213200 kb
Host smart-107f4264-741c-4395-8862-122b3da85fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190118486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2190118486
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1255246634
Short name T270
Test name
Test status
Simulation time 10303826135 ps
CPU time 31.16 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:36 PM PDT 24
Peak memory 214648 kb
Host smart-d652a5e0-8fe4-4184-9028-9eef29f7ae48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255246634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1255246634
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4132845686
Short name T204
Test name
Test status
Simulation time 13496510059 ps
CPU time 11.12 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:15 PM PDT 24
Peak memory 211396 kb
Host smart-c715f817-9907-4e77-be90-f12a1ebffc9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132845686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4132845686
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3835127584
Short name T319
Test name
Test status
Simulation time 7202149482 ps
CPU time 20.15 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:24 PM PDT 24
Peak memory 212496 kb
Host smart-6f27c4fe-4657-4b32-8436-3263c9a12dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835127584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3835127584
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2571666007
Short name T4
Test name
Test status
Simulation time 8880496345 ps
CPU time 17.57 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:02:11 PM PDT 24
Peak memory 211424 kb
Host smart-3c3385d5-e966-4f8e-815e-e3523177aace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571666007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2571666007
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4197732175
Short name T19
Test name
Test status
Simulation time 22966544331 ps
CPU time 59.37 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 07:03:00 PM PDT 24
Peak memory 236856 kb
Host smart-60cff62a-21e2-4bf3-962d-ad8142d32afc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197732175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4197732175
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.18844217
Short name T159
Test name
Test status
Simulation time 1155197086 ps
CPU time 17.27 seconds
Started Jul 17 07:01:49 PM PDT 24
Finished Jul 17 07:02:07 PM PDT 24
Peak memory 213172 kb
Host smart-2f2820a2-14ee-474b-964b-9aa6f0b8689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18844217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.18844217
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2631868462
Short name T332
Test name
Test status
Simulation time 3572870713 ps
CPU time 15.57 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:02:09 PM PDT 24
Peak memory 216724 kb
Host smart-02c2e03c-5c4d-40a0-b666-5d70c1dcf583
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631868462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2631868462
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.467444267
Short name T164
Test name
Test status
Simulation time 6409049050 ps
CPU time 13.14 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:02:25 PM PDT 24
Peak memory 211408 kb
Host smart-89e9336c-9c64-4576-ba69-142c00cfa62d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467444267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.467444267
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2338308724
Short name T42
Test name
Test status
Simulation time 150826318597 ps
CPU time 325.4 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:07:34 PM PDT 24
Peak memory 228588 kb
Host smart-c11cbf81-d5c1-4d40-8f1d-3a4691b76c22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338308724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2338308724
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1279083754
Short name T344
Test name
Test status
Simulation time 1645502893 ps
CPU time 14.28 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:22 PM PDT 24
Peak memory 212048 kb
Host smart-37102feb-fb48-4346-953d-f0f6d8d6956b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279083754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1279083754
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4240318887
Short name T179
Test name
Test status
Simulation time 5886606233 ps
CPU time 13.4 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:20 PM PDT 24
Peak memory 211416 kb
Host smart-7f22de98-e3de-4442-b2d2-ad163c766b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240318887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4240318887
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2825706136
Short name T134
Test name
Test status
Simulation time 8067672154 ps
CPU time 40.36 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 07:02:42 PM PDT 24
Peak memory 213776 kb
Host smart-445473ef-e9cb-4667-98bc-f6a9d08b3675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825706136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2825706136
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.426610175
Short name T314
Test name
Test status
Simulation time 491420505 ps
CPU time 26.64 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:35 PM PDT 24
Peak memory 219324 kb
Host smart-915112f0-39cc-4571-bdb6-edb5fa30bad3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426610175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.426610175
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1512367188
Short name T62
Test name
Test status
Simulation time 114497311608 ps
CPU time 3216.54 seconds
Started Jul 17 07:02:02 PM PDT 24
Finished Jul 17 07:55:47 PM PDT 24
Peak memory 244060 kb
Host smart-c50afe78-aa04-4d1b-a15a-74c04e660824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512367188 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1512367188
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1376605036
Short name T214
Test name
Test status
Simulation time 89299914 ps
CPU time 4.26 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:01 PM PDT 24
Peak memory 211332 kb
Host smart-6b4ce662-c1f3-4e02-b7a0-8c9fb4b3b8b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376605036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1376605036
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2268251774
Short name T238
Test name
Test status
Simulation time 4664302920 ps
CPU time 72.13 seconds
Started Jul 17 07:01:41 PM PDT 24
Finished Jul 17 07:02:55 PM PDT 24
Peak memory 237880 kb
Host smart-545cb6e2-a9c2-4db3-9a9b-19ae9c3e4c6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268251774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2268251774
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2601998311
Short name T310
Test name
Test status
Simulation time 3020853153 ps
CPU time 27.07 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:36 PM PDT 24
Peak memory 212036 kb
Host smart-a65d2415-1070-4fe8-b47d-b21ec292adea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601998311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2601998311
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1742944840
Short name T244
Test name
Test status
Simulation time 1931027115 ps
CPU time 15.84 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 07:02:25 PM PDT 24
Peak memory 211404 kb
Host smart-f4777bb5-2147-46da-a67a-1380d538d27d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742944840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1742944840
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.610450877
Short name T201
Test name
Test status
Simulation time 3805746800 ps
CPU time 31.58 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 212972 kb
Host smart-d09ac6ae-8e66-44f4-b2ca-0b97ecd10ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610450877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.610450877
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.211129169
Short name T321
Test name
Test status
Simulation time 5966627244 ps
CPU time 76.96 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:03:28 PM PDT 24
Peak memory 218364 kb
Host smart-f2743f68-bcdb-4318-aea6-fad9c74c8c44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211129169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.211129169
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1921850589
Short name T200
Test name
Test status
Simulation time 1228015079 ps
CPU time 11.52 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:14 PM PDT 24
Peak memory 211308 kb
Host smart-51dcde93-9f24-4396-9749-4794828c73ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921850589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1921850589
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2951152227
Short name T317
Test name
Test status
Simulation time 139489556103 ps
CPU time 247.42 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:06:02 PM PDT 24
Peak memory 212720 kb
Host smart-69a7836c-cdad-4155-9335-3b9eef3331a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951152227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2951152227
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4018055841
Short name T356
Test name
Test status
Simulation time 2705839635 ps
CPU time 26.34 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:02:21 PM PDT 24
Peak memory 212024 kb
Host smart-abd37c14-01ac-4fd4-bad8-f79c4e9384e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018055841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4018055841
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2691520797
Short name T170
Test name
Test status
Simulation time 892695955 ps
CPU time 9.21 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 211380 kb
Host smart-3fa23023-691e-46bd-aeb7-610082f73cce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691520797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2691520797
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1313366298
Short name T173
Test name
Test status
Simulation time 18077782237 ps
CPU time 23.89 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:31 PM PDT 24
Peak memory 213572 kb
Host smart-406ec34f-f5a7-4b0d-98ba-453a23017f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313366298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1313366298
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2583405129
Short name T362
Test name
Test status
Simulation time 8040015026 ps
CPU time 36.16 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 07:02:46 PM PDT 24
Peak memory 215884 kb
Host smart-550e2da0-5fd9-4b7e-afe3-5d54928bd82a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583405129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2583405129
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.833367912
Short name T347
Test name
Test status
Simulation time 5419336871 ps
CPU time 12.07 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:11 PM PDT 24
Peak memory 211420 kb
Host smart-0be1aec3-8d5d-4b2a-b405-5ee0e0f607ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833367912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.833367912
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1515765572
Short name T280
Test name
Test status
Simulation time 41304071939 ps
CPU time 264.38 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:06:28 PM PDT 24
Peak memory 212796 kb
Host smart-0ab6c402-9ac8-4f54-b264-7c63c2eb3f66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515765572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1515765572
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2008136
Short name T324
Test name
Test status
Simulation time 15633754860 ps
CPU time 31.97 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:37 PM PDT 24
Peak memory 212244 kb
Host smart-8acfa0f7-199b-4ad2-9932-e657674215e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2008136
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2175102401
Short name T177
Test name
Test status
Simulation time 419665536 ps
CPU time 5.58 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:04 PM PDT 24
Peak memory 211404 kb
Host smart-b33b22db-d221-4b3e-96d3-134e81b27fea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2175102401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2175102401
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.500615351
Short name T327
Test name
Test status
Simulation time 7389765384 ps
CPU time 37.56 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 214544 kb
Host smart-54bca8c7-3df7-4a2b-b639-6c508fa2f05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500615351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.500615351
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4117258024
Short name T152
Test name
Test status
Simulation time 2580945305 ps
CPU time 27.24 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:33 PM PDT 24
Peak memory 213756 kb
Host smart-724b5e59-606b-4ce9-92a9-cf82d8dec13c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117258024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4117258024
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3248676347
Short name T21
Test name
Test status
Simulation time 2027800573 ps
CPU time 16.27 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 07:02:26 PM PDT 24
Peak memory 210752 kb
Host smart-6c20de98-5e27-4d63-9399-af65001c84b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248676347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3248676347
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2433760746
Short name T56
Test name
Test status
Simulation time 2078522569 ps
CPU time 88.31 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:03:32 PM PDT 24
Peak memory 232676 kb
Host smart-4d3994c1-b673-48cf-8bee-ec976853233b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433760746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2433760746
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4251186810
Short name T52
Test name
Test status
Simulation time 171976768 ps
CPU time 9.42 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:15 PM PDT 24
Peak memory 212016 kb
Host smart-59c8ff87-25b5-4ab0-9a83-faed249136ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251186810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4251186810
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2838819301
Short name T210
Test name
Test status
Simulation time 190937245 ps
CPU time 5.48 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:11 PM PDT 24
Peak memory 211368 kb
Host smart-b65f7c80-c3cd-4284-91c6-5fd286c93e2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838819301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2838819301
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.679304191
Short name T133
Test name
Test status
Simulation time 20409236873 ps
CPU time 33.46 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:39 PM PDT 24
Peak memory 214248 kb
Host smart-874a8d01-86bc-4db4-a4e3-565cad77aeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679304191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.679304191
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3638472202
Short name T206
Test name
Test status
Simulation time 5437168557 ps
CPU time 61.21 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:03:06 PM PDT 24
Peak memory 216936 kb
Host smart-e904c5c1-069d-4138-897e-db9f66675558
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638472202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3638472202
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2232298268
Short name T273
Test name
Test status
Simulation time 30338708167 ps
CPU time 1125.09 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:20:51 PM PDT 24
Peak memory 235852 kb
Host smart-eed11fe0-1eee-47ee-ae39-2fc9ac5ed4d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232298268 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2232298268
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2994925082
Short name T207
Test name
Test status
Simulation time 333360663 ps
CPU time 4.21 seconds
Started Jul 17 07:02:02 PM PDT 24
Finished Jul 17 07:02:14 PM PDT 24
Peak memory 211296 kb
Host smart-22843f77-8e0e-476f-aef1-d9933b2c4687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994925082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2994925082
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1353084660
Short name T28
Test name
Test status
Simulation time 42747955325 ps
CPU time 158.78 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:04:44 PM PDT 24
Peak memory 237844 kb
Host smart-6e1b0c54-a2f5-41c6-a1d4-1afb41a10113
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353084660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1353084660
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.389748331
Short name T237
Test name
Test status
Simulation time 413773814 ps
CPU time 12.29 seconds
Started Jul 17 07:01:42 PM PDT 24
Finished Jul 17 07:01:56 PM PDT 24
Peak memory 212184 kb
Host smart-c7d66a2f-ef00-41af-9424-ba19d557480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389748331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.389748331
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.349361624
Short name T235
Test name
Test status
Simulation time 19537968124 ps
CPU time 11.31 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 211420 kb
Host smart-0b516345-4c95-4d78-b46b-ee9c91da4c69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349361624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.349361624
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3301691905
Short name T243
Test name
Test status
Simulation time 690410720 ps
CPU time 9.85 seconds
Started Jul 17 07:01:47 PM PDT 24
Finished Jul 17 07:01:58 PM PDT 24
Peak memory 213672 kb
Host smart-6067f4b7-6c93-4a8d-9a7f-0607b1750149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301691905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3301691905
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2397981030
Short name T252
Test name
Test status
Simulation time 32849924568 ps
CPU time 64.14 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:03:11 PM PDT 24
Peak memory 217068 kb
Host smart-156cd79b-f545-4f09-91b3-90613860935c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397981030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2397981030
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.178260077
Short name T69
Test name
Test status
Simulation time 1893710640 ps
CPU time 15.03 seconds
Started Jul 17 07:01:40 PM PDT 24
Finished Jul 17 07:01:57 PM PDT 24
Peak memory 211360 kb
Host smart-33065812-bd7b-42a4-9079-d9f4374a88fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178260077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.178260077
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2811145644
Short name T293
Test name
Test status
Simulation time 20356659194 ps
CPU time 197.8 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:05:24 PM PDT 24
Peak memory 237792 kb
Host smart-4c932c0a-b38c-4bbd-b5a5-c5071bbdc840
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811145644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2811145644
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3865538619
Short name T225
Test name
Test status
Simulation time 15029944419 ps
CPU time 31.56 seconds
Started Jul 17 07:01:50 PM PDT 24
Finished Jul 17 07:02:23 PM PDT 24
Peak memory 212268 kb
Host smart-504350dc-6284-45a9-9927-54458c66b6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865538619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3865538619
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.72218829
Short name T369
Test name
Test status
Simulation time 382767426 ps
CPU time 5.14 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:13 PM PDT 24
Peak memory 211356 kb
Host smart-365040b2-460d-4084-9fee-ab009edaa187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72218829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.72218829
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1972325848
Short name T189
Test name
Test status
Simulation time 1087988084 ps
CPU time 17.14 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 07:02:27 PM PDT 24
Peak memory 213312 kb
Host smart-62c89a2a-84f3-435e-9ead-2b971bb9a9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972325848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1972325848
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3091008371
Short name T70
Test name
Test status
Simulation time 321950262 ps
CPU time 9.22 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:02:21 PM PDT 24
Peak memory 211408 kb
Host smart-6c112d81-46d8-4b27-b5e9-12a759546b57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091008371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3091008371
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.535727606
Short name T289
Test name
Test status
Simulation time 977991094 ps
CPU time 9.87 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 211360 kb
Host smart-c50c066e-f2fa-4d6a-9763-8ad80a770f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535727606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.535727606
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4006539715
Short name T257
Test name
Test status
Simulation time 16924188010 ps
CPU time 173.95 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:05:03 PM PDT 24
Peak memory 225764 kb
Host smart-a664c482-2810-4b63-912c-23984b3e6d2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006539715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4006539715
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3600208817
Short name T1
Test name
Test status
Simulation time 168823922 ps
CPU time 9.39 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:17 PM PDT 24
Peak memory 211840 kb
Host smart-70c494bd-8d45-4296-84b7-3347fa86fd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600208817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3600208817
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.769431532
Short name T127
Test name
Test status
Simulation time 8699957933 ps
CPU time 16.46 seconds
Started Jul 17 07:02:04 PM PDT 24
Finished Jul 17 07:02:28 PM PDT 24
Peak memory 211428 kb
Host smart-2f423d2b-9585-4de1-88a4-ecf12f9d0619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769431532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.769431532
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3425540266
Short name T147
Test name
Test status
Simulation time 2931935528 ps
CPU time 18.06 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:25 PM PDT 24
Peak memory 213488 kb
Host smart-327d8b60-93db-40f5-83d6-04148259d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425540266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3425540266
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3965563297
Short name T212
Test name
Test status
Simulation time 5054243514 ps
CPU time 22.3 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:31 PM PDT 24
Peak memory 216916 kb
Host smart-f798397c-41db-4d3d-bc39-3678ce649f98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965563297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3965563297
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1051084440
Short name T334
Test name
Test status
Simulation time 100472246216 ps
CPU time 4310.81 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 08:14:00 PM PDT 24
Peak memory 235892 kb
Host smart-aad8efd7-2702-4c86-bce6-56eceb331369
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051084440 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1051084440
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2767055502
Short name T68
Test name
Test status
Simulation time 1285843492 ps
CPU time 11.7 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 07:02:21 PM PDT 24
Peak memory 211336 kb
Host smart-679dd1e9-3851-410b-8cff-139f46731b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767055502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2767055502
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3685742309
Short name T351
Test name
Test status
Simulation time 20322055147 ps
CPU time 214.47 seconds
Started Jul 17 07:01:43 PM PDT 24
Finished Jul 17 07:05:19 PM PDT 24
Peak memory 237676 kb
Host smart-0ade1f87-d2aa-46ec-a203-71057b027ce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685742309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3685742309
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2937667358
Short name T219
Test name
Test status
Simulation time 4079708136 ps
CPU time 21.4 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 07:02:31 PM PDT 24
Peak memory 211940 kb
Host smart-ae59cf9f-f4f4-4349-8ccc-5f1eadca020f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937667358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2937667358
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3910201513
Short name T215
Test name
Test status
Simulation time 2307056794 ps
CPU time 12.04 seconds
Started Jul 17 07:03:36 PM PDT 24
Finished Jul 17 07:03:51 PM PDT 24
Peak memory 211416 kb
Host smart-5bd1ae6c-5e36-4bbf-a409-fdcef941bebd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910201513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3910201513
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1667859963
Short name T242
Test name
Test status
Simulation time 2329738550 ps
CPU time 23.55 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:32 PM PDT 24
Peak memory 213492 kb
Host smart-1a1e0e1e-fb25-4d31-b00b-589dd671992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667859963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1667859963
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2936096276
Short name T363
Test name
Test status
Simulation time 1843321507 ps
CPU time 20.58 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:28 PM PDT 24
Peak memory 215436 kb
Host smart-5557f031-1104-4ce1-9b81-289ccb809616
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936096276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2936096276
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3624656545
Short name T23
Test name
Test status
Simulation time 261731306189 ps
CPU time 2967.8 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:51:39 PM PDT 24
Peak memory 248312 kb
Host smart-ff9d49df-3161-4b86-9522-2b5bd1fcc39c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624656545 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3624656545
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1894388186
Short name T50
Test name
Test status
Simulation time 812288939 ps
CPU time 9.12 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:06 PM PDT 24
Peak memory 211332 kb
Host smart-90dedc90-7390-44b7-bf0e-b7dfd2b8f15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894388186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1894388186
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2146483541
Short name T296
Test name
Test status
Simulation time 11219057679 ps
CPU time 164.04 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:04:43 PM PDT 24
Peak memory 237012 kb
Host smart-7d701fd1-25a1-4942-8da6-cc4df8d3a9c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146483541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2146483541
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3341366243
Short name T364
Test name
Test status
Simulation time 4245373631 ps
CPU time 16.41 seconds
Started Jul 17 07:01:43 PM PDT 24
Finished Jul 17 07:02:01 PM PDT 24
Peak memory 212180 kb
Host smart-a6d91dac-fa4c-44fa-91eb-bd090cb58455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341366243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3341366243
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.769634719
Short name T285
Test name
Test status
Simulation time 1925711058 ps
CPU time 16.45 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:26 PM PDT 24
Peak memory 211384 kb
Host smart-85f8d540-45db-4cfc-bff6-dc359af177cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769634719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.769634719
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.758144253
Short name T148
Test name
Test status
Simulation time 2109681330 ps
CPU time 24.19 seconds
Started Jul 17 07:02:02 PM PDT 24
Finished Jul 17 07:02:34 PM PDT 24
Peak memory 214048 kb
Host smart-36eb4770-54c6-42ce-8c9d-2444cd5582b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758144253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.758144253
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.595414612
Short name T182
Test name
Test status
Simulation time 17118662287 ps
CPU time 77.16 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 217664 kb
Host smart-81436c77-7623-404c-b942-ea0cd4affeff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595414612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.595414612
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3261315957
Short name T209
Test name
Test status
Simulation time 7225609507 ps
CPU time 14.93 seconds
Started Jul 17 07:02:09 PM PDT 24
Finished Jul 17 07:02:28 PM PDT 24
Peak memory 211408 kb
Host smart-7b624513-296c-4fcf-8cc9-2c553a844c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261315957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3261315957
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2995286398
Short name T38
Test name
Test status
Simulation time 64753837171 ps
CPU time 477.2 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 224712 kb
Host smart-7ed9b039-676d-4fa8-8a72-c1e3a2ebb9bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995286398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2995286398
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2302869531
Short name T54
Test name
Test status
Simulation time 4143180240 ps
CPU time 26.82 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:02:22 PM PDT 24
Peak memory 211972 kb
Host smart-cfcdc74b-6873-4a10-9080-227487060605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302869531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2302869531
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3698671299
Short name T282
Test name
Test status
Simulation time 8253277749 ps
CPU time 15.27 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:14 PM PDT 24
Peak memory 211448 kb
Host smart-cc2c6ac5-cf88-4cc0-a35f-f7229ff57574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698671299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3698671299
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3468985315
Short name T20
Test name
Test status
Simulation time 7114877867 ps
CPU time 106.82 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:03:51 PM PDT 24
Peak memory 234316 kb
Host smart-739f7d8d-9869-4204-88d9-3c118cddcf68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468985315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3468985315
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.722436030
Short name T269
Test name
Test status
Simulation time 183894027 ps
CPU time 10.07 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:07 PM PDT 24
Peak memory 213352 kb
Host smart-8eb1dd6b-c08d-462d-8943-22495e62578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722436030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.722436030
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1226389564
Short name T13
Test name
Test status
Simulation time 10198355170 ps
CPU time 45.92 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:02:40 PM PDT 24
Peak memory 219372 kb
Host smart-05cbf8d7-9080-40e7-b478-fe1b4db813c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226389564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1226389564
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.4073605910
Short name T60
Test name
Test status
Simulation time 97882821256 ps
CPU time 3732.12 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 08:04:14 PM PDT 24
Peak memory 246328 kb
Host smart-2624e544-474e-42b3-b42b-beecac79ce7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073605910 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.4073605910
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1637736669
Short name T259
Test name
Test status
Simulation time 8407395580 ps
CPU time 16.48 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:22 PM PDT 24
Peak memory 211380 kb
Host smart-4c6b8d0b-bf05-4ca0-86a5-4caeff0f8e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637736669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1637736669
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1448848046
Short name T153
Test name
Test status
Simulation time 3704668710 ps
CPU time 156.84 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:04:36 PM PDT 24
Peak memory 212824 kb
Host smart-543e3375-08da-42da-95b3-2da5db25a284
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448848046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1448848046
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3872691069
Short name T185
Test name
Test status
Simulation time 1103601924 ps
CPU time 16.55 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:13 PM PDT 24
Peak memory 211964 kb
Host smart-2c87b808-cac0-47a0-aa42-95df05aca187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872691069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3872691069
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2851294868
Short name T355
Test name
Test status
Simulation time 1763728262 ps
CPU time 14.99 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:20 PM PDT 24
Peak memory 211352 kb
Host smart-883ec3f0-c42e-4d44-9867-418c4cf631e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851294868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2851294868
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1769887650
Short name T360
Test name
Test status
Simulation time 1083481035 ps
CPU time 18.99 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:02:18 PM PDT 24
Peak memory 213516 kb
Host smart-a97af218-8157-4fd0-b941-7af8b24fc6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769887650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1769887650
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.582086113
Short name T266
Test name
Test status
Simulation time 1592502809 ps
CPU time 13.27 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:10 PM PDT 24
Peak memory 215360 kb
Host smart-807fcfb4-afcf-4c72-8aa4-fa7493ef4754
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582086113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.582086113
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3455117180
Short name T186
Test name
Test status
Simulation time 133487088 ps
CPU time 5.1 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:11 PM PDT 24
Peak memory 211312 kb
Host smart-8821ccfc-edf9-4844-a02e-fc3db8fb79b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455117180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3455117180
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3043909574
Short name T291
Test name
Test status
Simulation time 86920247167 ps
CPU time 211.28 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 07:05:33 PM PDT 24
Peak memory 237832 kb
Host smart-abb59967-1596-4f4d-b480-50e7e22c9682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043909574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3043909574
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1436699040
Short name T150
Test name
Test status
Simulation time 417988038 ps
CPU time 9.28 seconds
Started Jul 17 07:02:04 PM PDT 24
Finished Jul 17 07:02:21 PM PDT 24
Peak memory 211980 kb
Host smart-fe8df6cd-d7d0-4804-a593-4e08f9ae79cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436699040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1436699040
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2722764401
Short name T308
Test name
Test status
Simulation time 2694918378 ps
CPU time 9.6 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:06 PM PDT 24
Peak memory 211464 kb
Host smart-91ab6194-5aca-4927-840e-9c903c8d5820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722764401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2722764401
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3619216310
Short name T169
Test name
Test status
Simulation time 1517151897 ps
CPU time 15.53 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 213748 kb
Host smart-cc198d1d-d902-4266-b392-2502504a5be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619216310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3619216310
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1079353195
Short name T302
Test name
Test status
Simulation time 5616942974 ps
CPU time 74.31 seconds
Started Jul 17 07:01:51 PM PDT 24
Finished Jul 17 07:03:08 PM PDT 24
Peak memory 219400 kb
Host smart-61e9e9c3-aae5-4101-b1dc-9a673c488087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079353195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1079353195
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3711622733
Short name T228
Test name
Test status
Simulation time 5783806264 ps
CPU time 11.6 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 211380 kb
Host smart-081d8596-398e-496b-a22f-aaee104bfc8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711622733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3711622733
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1967341340
Short name T341
Test name
Test status
Simulation time 164097356183 ps
CPU time 346.11 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:07:52 PM PDT 24
Peak memory 213648 kb
Host smart-deb988d9-f198-4e44-af4f-4b063a80db67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967341340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1967341340
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1404096412
Short name T176
Test name
Test status
Simulation time 1653908540 ps
CPU time 9.61 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 211876 kb
Host smart-5ed2578f-3b43-48f1-b310-7f04554ebe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404096412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1404096412
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4189948829
Short name T46
Test name
Test status
Simulation time 5960112087 ps
CPU time 14.23 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:21 PM PDT 24
Peak memory 211124 kb
Host smart-d33d3baf-63a6-4758-9f56-fb7ba3b511a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189948829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4189948829
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2346545317
Short name T208
Test name
Test status
Simulation time 12445575028 ps
CPU time 19.1 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:26 PM PDT 24
Peak memory 214460 kb
Host smart-50856c39-bc50-44e6-b732-93c3c9a698fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346545317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2346545317
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3071674633
Short name T12
Test name
Test status
Simulation time 749554758 ps
CPU time 10.38 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 214116 kb
Host smart-74547236-0816-4787-8533-3302be206ee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071674633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3071674633
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2155044122
Short name T58
Test name
Test status
Simulation time 48721726471 ps
CPU time 4281.25 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 08:13:31 PM PDT 24
Peak memory 237852 kb
Host smart-5c91c00a-d26b-446b-8f55-2fd5335b23e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155044122 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2155044122
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3313437002
Short name T343
Test name
Test status
Simulation time 262916462 ps
CPU time 5.99 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:14 PM PDT 24
Peak memory 211316 kb
Host smart-125c8b38-2397-4756-99b9-f158c72d219b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313437002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3313437002
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.531855047
Short name T136
Test name
Test status
Simulation time 961251132 ps
CPU time 63.76 seconds
Started Jul 17 07:01:39 PM PDT 24
Finished Jul 17 07:02:45 PM PDT 24
Peak memory 233756 kb
Host smart-37d13a64-30cd-4280-9799-d7a78a377fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531855047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.531855047
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2181796326
Short name T236
Test name
Test status
Simulation time 905078964 ps
CPU time 15.23 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:18 PM PDT 24
Peak memory 211976 kb
Host smart-632e48ba-9300-42c5-832a-23aeb5b0ab5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181796326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2181796326
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.366528511
Short name T307
Test name
Test status
Simulation time 1045473632 ps
CPU time 7.05 seconds
Started Jul 17 07:01:59 PM PDT 24
Finished Jul 17 07:02:15 PM PDT 24
Peak memory 211360 kb
Host smart-511278d0-fb42-4bb7-8e94-efaf2809bb5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=366528511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.366528511
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.670707252
Short name T160
Test name
Test status
Simulation time 11737286732 ps
CPU time 26.2 seconds
Started Jul 17 07:01:40 PM PDT 24
Finished Jul 17 07:02:08 PM PDT 24
Peak memory 213832 kb
Host smart-9c506f31-6839-4282-9adb-6873dc3a33e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670707252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.670707252
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.209805315
Short name T338
Test name
Test status
Simulation time 4724649202 ps
CPU time 30.41 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:35 PM PDT 24
Peak memory 212820 kb
Host smart-61fc4d05-1d8b-447d-9c1e-cf497adb3630
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209805315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.209805315
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4037864800
Short name T234
Test name
Test status
Simulation time 9687618697 ps
CPU time 13.17 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 07:02:23 PM PDT 24
Peak memory 211396 kb
Host smart-78ec0f0e-cc7b-4cc4-ac45-7ccbb21f7f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037864800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4037864800
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1366722803
Short name T268
Test name
Test status
Simulation time 317814263269 ps
CPU time 167.48 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:04:55 PM PDT 24
Peak memory 237824 kb
Host smart-05be7518-ba2b-4186-90a4-d47f3423a2f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366722803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1366722803
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2596762663
Short name T359
Test name
Test status
Simulation time 3012816576 ps
CPU time 13.72 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:02:25 PM PDT 24
Peak memory 211420 kb
Host smart-d198cce9-a445-414a-8bf5-68c3b723c36c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596762663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2596762663
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4056809838
Short name T366
Test name
Test status
Simulation time 6674160872 ps
CPU time 28.8 seconds
Started Jul 17 07:02:03 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 214724 kb
Host smart-e6bcd617-6a6a-459e-b82c-ccf3b71b5a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056809838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4056809838
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1719377911
Short name T145
Test name
Test status
Simulation time 1881210984 ps
CPU time 27.82 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:35 PM PDT 24
Peak memory 216912 kb
Host smart-92cd8797-a23c-41c1-92f1-d95d22a13677
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719377911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1719377911
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3757501831
Short name T267
Test name
Test status
Simulation time 2281856983 ps
CPU time 7.96 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:12 PM PDT 24
Peak memory 211392 kb
Host smart-c2932e9a-4355-4d5e-8572-9158f27613d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757501831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3757501831
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1523348333
Short name T17
Test name
Test status
Simulation time 124631999800 ps
CPU time 274.48 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:06:35 PM PDT 24
Peak memory 212744 kb
Host smart-94302ef6-1906-4073-a049-7e77133ed340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523348333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1523348333
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3584395853
Short name T337
Test name
Test status
Simulation time 8040110026 ps
CPU time 32.87 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 07:02:35 PM PDT 24
Peak memory 212440 kb
Host smart-09a0161f-8874-4eb9-bc21-61b136139d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584395853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3584395853
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4283968495
Short name T322
Test name
Test status
Simulation time 3339842500 ps
CPU time 14.44 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 211360 kb
Host smart-75e8ba69-ff33-4a67-ba15-5e88644fb89f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283968495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4283968495
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1611349654
Short name T306
Test name
Test status
Simulation time 3394899007 ps
CPU time 15.79 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:25 PM PDT 24
Peak memory 213440 kb
Host smart-07de2c57-f6a0-40e6-996c-66d1b6588cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611349654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1611349654
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3987821319
Short name T284
Test name
Test status
Simulation time 1205889843 ps
CPU time 14.79 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:24 PM PDT 24
Peak memory 211832 kb
Host smart-d05ec5c9-982f-4d39-9af0-7460767221d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987821319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3987821319
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.449385041
Short name T141
Test name
Test status
Simulation time 2697290127 ps
CPU time 12.39 seconds
Started Jul 17 07:02:19 PM PDT 24
Finished Jul 17 07:02:35 PM PDT 24
Peak memory 211432 kb
Host smart-4efbbfe2-1a4d-4a90-84c0-409a0a7abf24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449385041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.449385041
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1318497462
Short name T16
Test name
Test status
Simulation time 248443810941 ps
CPU time 230.53 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:05:57 PM PDT 24
Peak memory 228632 kb
Host smart-199bb509-5a69-476c-99fe-c3f5ad7a8d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318497462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1318497462
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2660710762
Short name T124
Test name
Test status
Simulation time 9868370134 ps
CPU time 25.27 seconds
Started Jul 17 07:01:42 PM PDT 24
Finished Jul 17 07:02:09 PM PDT 24
Peak memory 212252 kb
Host smart-1ba44b8e-b2ad-4c51-91a0-e9898f63b97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660710762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2660710762
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2840973528
Short name T129
Test name
Test status
Simulation time 1796992517 ps
CPU time 15.37 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 211360 kb
Host smart-61a1a907-e391-4156-98e8-36efdeeaa7dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2840973528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2840973528
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.4055075027
Short name T162
Test name
Test status
Simulation time 33529753931 ps
CPU time 39.97 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 07:02:50 PM PDT 24
Peak memory 214268 kb
Host smart-9e6e4549-d8ef-4a1d-b877-a1b7cd8e21f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055075027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.4055075027
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.821622458
Short name T320
Test name
Test status
Simulation time 69622032253 ps
CPU time 157.51 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:04:43 PM PDT 24
Peak memory 219400 kb
Host smart-1a2f31f9-ca3d-41c4-b583-23029bee54ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821622458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.821622458
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1364973473
Short name T298
Test name
Test status
Simulation time 944751642 ps
CPU time 7.22 seconds
Started Jul 17 07:02:17 PM PDT 24
Finished Jul 17 07:02:26 PM PDT 24
Peak memory 211544 kb
Host smart-4d75ca9e-0dfd-4f96-9b0b-713712394f97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364973473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1364973473
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.302596217
Short name T222
Test name
Test status
Simulation time 1969112490 ps
CPU time 130.13 seconds
Started Jul 17 07:02:16 PM PDT 24
Finished Jul 17 07:04:28 PM PDT 24
Peak memory 236968 kb
Host smart-8db48a53-d9c8-46bf-87fe-734759de2633
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302596217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.302596217
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2652478245
Short name T287
Test name
Test status
Simulation time 640701302 ps
CPU time 9.69 seconds
Started Jul 17 07:02:19 PM PDT 24
Finished Jul 17 07:02:32 PM PDT 24
Peak memory 211872 kb
Host smart-c6f2d58c-fa95-43b7-a46e-8eb39ea63ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652478245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2652478245
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1951513898
Short name T331
Test name
Test status
Simulation time 586681896 ps
CPU time 5.55 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:42 PM PDT 24
Peak memory 211408 kb
Host smart-ae7b5922-41fd-43fc-9bb4-f6a071571e75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951513898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1951513898
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3544192710
Short name T304
Test name
Test status
Simulation time 15006578204 ps
CPU time 29.12 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:03:05 PM PDT 24
Peak memory 214332 kb
Host smart-1cc2fbd2-52dc-41a9-bdef-80308ea170b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544192710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3544192710
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3294628288
Short name T161
Test name
Test status
Simulation time 4841711490 ps
CPU time 30.33 seconds
Started Jul 17 07:02:22 PM PDT 24
Finished Jul 17 07:02:56 PM PDT 24
Peak memory 219400 kb
Host smart-2b131b73-18d4-4ad6-964c-cece632ff4e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294628288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3294628288
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1700700388
Short name T31
Test name
Test status
Simulation time 321283532 ps
CPU time 4.2 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:40 PM PDT 24
Peak memory 211428 kb
Host smart-abb8d1f2-c94d-4fd3-8f57-a8698db13d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700700388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1700700388
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3120112595
Short name T232
Test name
Test status
Simulation time 172083028 ps
CPU time 9.34 seconds
Started Jul 17 07:02:19 PM PDT 24
Finished Jul 17 07:02:33 PM PDT 24
Peak memory 211940 kb
Host smart-7757abbb-2d54-46c8-87d2-1d859b1360ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120112595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3120112595
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3771396330
Short name T231
Test name
Test status
Simulation time 3182010280 ps
CPU time 10.32 seconds
Started Jul 17 07:02:17 PM PDT 24
Finished Jul 17 07:02:29 PM PDT 24
Peak memory 211460 kb
Host smart-3775adc3-0a51-4d00-8547-83f56d20a53c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771396330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3771396330
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1850026341
Short name T297
Test name
Test status
Simulation time 187145595 ps
CPU time 9.97 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:47 PM PDT 24
Peak memory 213220 kb
Host smart-ca029778-9a49-4276-b6c4-c43d3b98d3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850026341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1850026341
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.813911361
Short name T15
Test name
Test status
Simulation time 13015790893 ps
CPU time 46.4 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:03:26 PM PDT 24
Peak memory 219564 kb
Host smart-8f70fe7c-dfd2-451a-80aa-f9b90410710b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813911361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.813911361
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.436769870
Short name T140
Test name
Test status
Simulation time 6231183351 ps
CPU time 14.01 seconds
Started Jul 17 07:02:18 PM PDT 24
Finished Jul 17 07:02:33 PM PDT 24
Peak memory 211400 kb
Host smart-076617ec-3895-4f41-a607-f695d3639cfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436769870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.436769870
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1865429507
Short name T39
Test name
Test status
Simulation time 26691795764 ps
CPU time 312.08 seconds
Started Jul 17 07:02:19 PM PDT 24
Finished Jul 17 07:07:35 PM PDT 24
Peak memory 212624 kb
Host smart-d3141faa-5df1-458d-865e-ceab3a12d27d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865429507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1865429507
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.39758797
Short name T258
Test name
Test status
Simulation time 96771614 ps
CPU time 5.5 seconds
Started Jul 17 07:02:34 PM PDT 24
Finished Jul 17 07:02:47 PM PDT 24
Peak memory 211404 kb
Host smart-47fc109a-6da2-4a36-8959-a7af1d58177a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39758797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.39758797
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1071666266
Short name T87
Test name
Test status
Simulation time 6702288877 ps
CPU time 36.24 seconds
Started Jul 17 07:02:19 PM PDT 24
Finished Jul 17 07:02:59 PM PDT 24
Peak memory 213832 kb
Host smart-f90beb12-82ee-4941-9e4f-68b301f51a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071666266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1071666266
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2369066944
Short name T167
Test name
Test status
Simulation time 8132526824 ps
CPU time 43.71 seconds
Started Jul 17 07:02:22 PM PDT 24
Finished Jul 17 07:03:10 PM PDT 24
Peak memory 216948 kb
Host smart-b319a934-f7d7-4016-992e-d4ff20abdbb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369066944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2369066944
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1496061811
Short name T192
Test name
Test status
Simulation time 170723778096 ps
CPU time 3031.58 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:53:07 PM PDT 24
Peak memory 244900 kb
Host smart-2d648740-7014-469d-b46a-587a7b153c8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496061811 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1496061811
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1622460434
Short name T261
Test name
Test status
Simulation time 3589802823 ps
CPU time 14.01 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:02:13 PM PDT 24
Peak memory 211396 kb
Host smart-8a1a79e5-eed7-415e-8e71-339700c6661d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622460434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1622460434
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.121224084
Short name T34
Test name
Test status
Simulation time 3078006491 ps
CPU time 14.58 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:02:10 PM PDT 24
Peak memory 211856 kb
Host smart-8a20b38c-8537-4c0b-939d-2043391bbd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121224084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.121224084
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1834832733
Short name T35
Test name
Test status
Simulation time 150410361 ps
CPU time 5.4 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:03 PM PDT 24
Peak memory 211384 kb
Host smart-2200cd3f-a14a-4073-9de3-6968cf5e9604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1834832733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1834832733
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3791242251
Short name T300
Test name
Test status
Simulation time 3173574005 ps
CPU time 30.97 seconds
Started Jul 17 07:01:42 PM PDT 24
Finished Jul 17 07:02:15 PM PDT 24
Peak memory 213280 kb
Host smart-69e7a32f-88f6-4434-89b7-31c8edd581de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791242251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3791242251
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.69282341
Short name T123
Test name
Test status
Simulation time 801197027 ps
CPU time 20.35 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:25 PM PDT 24
Peak memory 215376 kb
Host smart-ab69bec0-7680-4b33-82b5-92c5d36b20b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69282341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.rom_ctrl_stress_all.69282341
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3418126802
Short name T37
Test name
Test status
Simulation time 4718418990 ps
CPU time 105.3 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:04:21 PM PDT 24
Peak memory 212572 kb
Host smart-f4184bc7-321a-42ef-8b11-fe448973e31b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418126802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3418126802
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1459715608
Short name T301
Test name
Test status
Simulation time 2752937851 ps
CPU time 25.18 seconds
Started Jul 17 07:02:27 PM PDT 24
Finished Jul 17 07:02:56 PM PDT 24
Peak memory 212052 kb
Host smart-ed059ac4-e33a-468f-b5bd-4e141bbaa446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459715608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1459715608
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.56901135
Short name T265
Test name
Test status
Simulation time 922619367 ps
CPU time 15.94 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:02:49 PM PDT 24
Peak memory 213708 kb
Host smart-01f56ff5-d27c-4975-aef2-ff77b92ef2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56901135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.56901135
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2999615212
Short name T203
Test name
Test status
Simulation time 3474137851 ps
CPU time 16.27 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:53 PM PDT 24
Peak memory 211316 kb
Host smart-1a4dbf02-bb8b-426a-9d5b-aa8e5ed3c2fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999615212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2999615212
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1124474922
Short name T57
Test name
Test status
Simulation time 35547187174 ps
CPU time 10454.8 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 09:56:52 PM PDT 24
Peak memory 235704 kb
Host smart-a1e35aa9-20aa-4cc6-9702-b7c8e4a21e6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124474922 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1124474922
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2378333094
Short name T155
Test name
Test status
Simulation time 462063459 ps
CPU time 4.22 seconds
Started Jul 17 07:02:19 PM PDT 24
Finished Jul 17 07:02:27 PM PDT 24
Peak memory 211332 kb
Host smart-6da9d86b-c2d2-43c5-89fd-0dd4abc4c745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378333094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2378333094
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2714868586
Short name T202
Test name
Test status
Simulation time 32174406473 ps
CPU time 367.98 seconds
Started Jul 17 07:02:20 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 236756 kb
Host smart-9b2f3fad-9ea8-458d-9771-15c462beafbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714868586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2714868586
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4273267206
Short name T348
Test name
Test status
Simulation time 3766955832 ps
CPU time 20.71 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:56 PM PDT 24
Peak memory 212040 kb
Host smart-2614dd44-38f0-4ff1-af6c-8e123aa86d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273267206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4273267206
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1604153351
Short name T48
Test name
Test status
Simulation time 2004119418 ps
CPU time 15.5 seconds
Started Jul 17 07:02:26 PM PDT 24
Finished Jul 17 07:02:46 PM PDT 24
Peak memory 211412 kb
Host smart-449afcb4-fef2-417b-a91f-15a13a1262c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604153351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1604153351
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2676330172
Short name T154
Test name
Test status
Simulation time 30827737994 ps
CPU time 30.39 seconds
Started Jul 17 07:02:26 PM PDT 24
Finished Jul 17 07:03:00 PM PDT 24
Peak memory 214324 kb
Host smart-5702669e-07cb-4b73-be9b-4c563f8f362d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676330172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2676330172
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3727566889
Short name T194
Test name
Test status
Simulation time 31952356497 ps
CPU time 73.43 seconds
Started Jul 17 07:02:22 PM PDT 24
Finished Jul 17 07:03:39 PM PDT 24
Peak memory 216664 kb
Host smart-cbde4c65-cdd9-4f73-9b6f-e82369be5e82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727566889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3727566889
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2151500211
Short name T180
Test name
Test status
Simulation time 8185551010 ps
CPU time 12.63 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:49 PM PDT 24
Peak memory 211492 kb
Host smart-4a35b72b-7ea1-4ffb-b1d9-6b9792d59f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151500211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2151500211
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1359513064
Short name T246
Test name
Test status
Simulation time 106367504840 ps
CPU time 269.47 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:07:05 PM PDT 24
Peak memory 237300 kb
Host smart-3481431e-cc25-4489-a556-bdc16a9dd00e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359513064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1359513064
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3393623032
Short name T368
Test name
Test status
Simulation time 1547729617 ps
CPU time 19.6 seconds
Started Jul 17 07:02:20 PM PDT 24
Finished Jul 17 07:02:44 PM PDT 24
Peak memory 211984 kb
Host smart-54e9b800-4b46-4ac8-8e75-42681c842f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393623032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3393623032
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.321137546
Short name T367
Test name
Test status
Simulation time 1312342282 ps
CPU time 12.92 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:02:46 PM PDT 24
Peak memory 211476 kb
Host smart-871ad271-8d93-4167-bf5d-6500672f482f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=321137546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.321137546
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2691449649
Short name T86
Test name
Test status
Simulation time 809687265 ps
CPU time 13.74 seconds
Started Jul 17 07:02:27 PM PDT 24
Finished Jul 17 07:02:45 PM PDT 24
Peak memory 212460 kb
Host smart-710120b9-5182-477f-b2d8-601e66fbb055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691449649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2691449649
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.378585157
Short name T166
Test name
Test status
Simulation time 423338269 ps
CPU time 21.6 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 214380 kb
Host smart-4e58697f-fc0b-4178-b9d1-49e4967e0fdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378585157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.378585157
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.824059065
Short name T175
Test name
Test status
Simulation time 742391625 ps
CPU time 7.44 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:42 PM PDT 24
Peak memory 211432 kb
Host smart-ffa3f4ae-5026-4f52-823e-42e6e9254ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824059065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.824059065
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.637415381
Short name T205
Test name
Test status
Simulation time 7702402302 ps
CPU time 104.53 seconds
Started Jul 17 07:02:22 PM PDT 24
Finished Jul 17 07:04:10 PM PDT 24
Peak memory 237812 kb
Host smart-acb4af66-0173-42c3-a604-cb6f9de5ed5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637415381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.637415381
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2704981877
Short name T349
Test name
Test status
Simulation time 4613680892 ps
CPU time 17.46 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:54 PM PDT 24
Peak memory 212556 kb
Host smart-6111f9d3-9542-477f-98e0-456e9448ed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704981877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2704981877
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3170661809
Short name T295
Test name
Test status
Simulation time 3676410927 ps
CPU time 10.87 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:02:44 PM PDT 24
Peak memory 211612 kb
Host smart-4856ea84-2731-4951-873f-daced1f0f016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170661809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3170661809
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2476378774
Short name T195
Test name
Test status
Simulation time 3980674073 ps
CPU time 16.78 seconds
Started Jul 17 07:02:27 PM PDT 24
Finished Jul 17 07:02:47 PM PDT 24
Peak memory 212052 kb
Host smart-729035c9-e8cc-40d0-858e-0dc575b84fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476378774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2476378774
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2219374634
Short name T44
Test name
Test status
Simulation time 7376305615 ps
CPU time 31.98 seconds
Started Jul 17 07:02:26 PM PDT 24
Finished Jul 17 07:03:01 PM PDT 24
Peak memory 215204 kb
Host smart-c6811bb6-fe4c-4977-809f-c2a3668ca83b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219374634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2219374634
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1178266346
Short name T253
Test name
Test status
Simulation time 178656791 ps
CPU time 4.3 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:40 PM PDT 24
Peak memory 211364 kb
Host smart-7031cce5-26c3-4031-9656-35b5b98d7b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178266346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1178266346
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1597804400
Short name T303
Test name
Test status
Simulation time 166469541547 ps
CPU time 402.4 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:09:18 PM PDT 24
Peak memory 225068 kb
Host smart-1785db6b-493b-49da-9efd-44260cf7857e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597804400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1597804400
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3021493684
Short name T143
Test name
Test status
Simulation time 2539602539 ps
CPU time 13.99 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:50 PM PDT 24
Peak memory 211892 kb
Host smart-e81c152e-4946-42c7-8715-65cdb83d004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021493684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3021493684
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1049069863
Short name T233
Test name
Test status
Simulation time 390021249 ps
CPU time 5.54 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:42 PM PDT 24
Peak memory 211384 kb
Host smart-213cbed8-0d4d-4d4a-84bf-c8fc735485fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049069863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1049069863
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2856162205
Short name T279
Test name
Test status
Simulation time 3321398454 ps
CPU time 15.5 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:52 PM PDT 24
Peak memory 213592 kb
Host smart-5bde67f8-6bee-475c-a3eb-4b2cdcc18658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856162205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2856162205
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.390973116
Short name T53
Test name
Test status
Simulation time 26403619540 ps
CPU time 46.69 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:03:21 PM PDT 24
Peak memory 217004 kb
Host smart-d4647c60-507b-48bd-8953-e163dedc1c19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390973116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.390973116
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.4159989901
Short name T198
Test name
Test status
Simulation time 5032625938 ps
CPU time 10.57 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 211560 kb
Host smart-ec91be3b-0e26-47f3-b41d-04909bca1795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159989901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4159989901
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3351195067
Short name T346
Test name
Test status
Simulation time 73223497869 ps
CPU time 188.01 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:05:44 PM PDT 24
Peak memory 236656 kb
Host smart-9d0ccf4c-2e7f-417d-b5f3-be03953481fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351195067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3351195067
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3233289786
Short name T197
Test name
Test status
Simulation time 168807972 ps
CPU time 9.27 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:45 PM PDT 24
Peak memory 212112 kb
Host smart-d8abbd10-b5ca-4598-95c1-0cea29d4a6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233289786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3233289786
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3157436188
Short name T190
Test name
Test status
Simulation time 6480183648 ps
CPU time 17.02 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:02:49 PM PDT 24
Peak memory 211600 kb
Host smart-fedd98f4-1914-4fa1-8fc6-a83a926d1d82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157436188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3157436188
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.771724690
Short name T10
Test name
Test status
Simulation time 3621904076 ps
CPU time 29.96 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:03:03 PM PDT 24
Peak memory 213100 kb
Host smart-c0947120-ccef-4b92-b110-5318e225a8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771724690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.771724690
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2572096399
Short name T82
Test name
Test status
Simulation time 8608698527 ps
CPU time 53.22 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:03:26 PM PDT 24
Peak memory 216000 kb
Host smart-ad08b8b8-7b07-4384-94ba-77a501b8fa32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572096399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2572096399
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1112319080
Short name T354
Test name
Test status
Simulation time 62636567139 ps
CPU time 2242.18 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:40:00 PM PDT 24
Peak memory 237936 kb
Host smart-8408cbd0-951c-4672-86f2-b591e80024b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112319080 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1112319080
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1524785908
Short name T305
Test name
Test status
Simulation time 1652696683 ps
CPU time 6.07 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 211364 kb
Host smart-874803bc-c2bd-43fc-9933-0d5a4180eee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524785908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1524785908
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2322498951
Short name T274
Test name
Test status
Simulation time 65186652653 ps
CPU time 309.13 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:07:44 PM PDT 24
Peak memory 237836 kb
Host smart-def1c54f-7822-4122-8f9f-0df1971b493f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322498951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2322498951
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1216405248
Short name T361
Test name
Test status
Simulation time 12939683038 ps
CPU time 28.14 seconds
Started Jul 17 07:02:33 PM PDT 24
Finished Jul 17 07:03:08 PM PDT 24
Peak memory 212152 kb
Host smart-b1d42320-b8c9-41e5-aa93-9bb54f602dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216405248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1216405248
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2769595425
Short name T275
Test name
Test status
Simulation time 1660471366 ps
CPU time 8.36 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 211552 kb
Host smart-ecf3e647-40f8-4462-90c1-d42c53ab1e9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769595425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2769595425
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1907933712
Short name T3
Test name
Test status
Simulation time 4275004503 ps
CPU time 34.45 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:03:08 PM PDT 24
Peak memory 213312 kb
Host smart-1f64120b-81bc-4e6b-bd03-672af172b556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907933712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1907933712
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.969249493
Short name T213
Test name
Test status
Simulation time 635927362 ps
CPU time 12.09 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:48 PM PDT 24
Peak memory 211224 kb
Host smart-18a1c642-5da5-40e9-ac12-cc29581e286f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969249493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.969249493
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1918751725
Short name T328
Test name
Test status
Simulation time 11642233094 ps
CPU time 379.62 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:08:59 PM PDT 24
Peak memory 224784 kb
Host smart-195257d7-8cdd-4268-9741-fddd325c362c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918751725 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1918751725
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1831800901
Short name T339
Test name
Test status
Simulation time 1317209017 ps
CPU time 12.12 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:49 PM PDT 24
Peak memory 211348 kb
Host smart-939cf45c-8a5d-4d16-9425-f765e63ac0e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831800901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1831800901
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.180113534
Short name T288
Test name
Test status
Simulation time 116983869204 ps
CPU time 112.27 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:04:27 PM PDT 24
Peak memory 237596 kb
Host smart-a10d5159-f7ce-49a6-88db-dff71d38fab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180113534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.180113534
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.369659598
Short name T9
Test name
Test status
Simulation time 2996301635 ps
CPU time 26.81 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:03:04 PM PDT 24
Peak memory 211892 kb
Host smart-49a5c281-dd44-4cb7-bc86-9a581f3b7ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369659598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.369659598
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.809792422
Short name T137
Test name
Test status
Simulation time 10022549418 ps
CPU time 12.64 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:52 PM PDT 24
Peak memory 211428 kb
Host smart-9ef2be60-3382-4b41-97f7-110796261457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809792422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.809792422
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2265304743
Short name T255
Test name
Test status
Simulation time 45955769641 ps
CPU time 35.85 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:03:14 PM PDT 24
Peak memory 213944 kb
Host smart-08561f92-5a03-4a42-b281-67e0c318cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265304743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2265304743
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3609229658
Short name T350
Test name
Test status
Simulation time 8754887747 ps
CPU time 25.51 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:03:01 PM PDT 24
Peak memory 214620 kb
Host smart-f1c3c913-0608-402d-a40f-5e9c659b9d3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609229658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3609229658
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1871454802
Short name T187
Test name
Test status
Simulation time 185162503452 ps
CPU time 1821.89 seconds
Started Jul 17 07:02:33 PM PDT 24
Finished Jul 17 07:33:02 PM PDT 24
Peak memory 243860 kb
Host smart-5f09372f-07ff-4530-9fc6-c238d31901df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871454802 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1871454802
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3816582986
Short name T67
Test name
Test status
Simulation time 226506193 ps
CPU time 4.28 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 211324 kb
Host smart-6114824f-1005-4763-a99a-4421c9d60159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816582986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3816582986
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.672679906
Short name T286
Test name
Test status
Simulation time 39612394780 ps
CPU time 299.18 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:07:38 PM PDT 24
Peak memory 237820 kb
Host smart-4d9c6a9d-c429-499e-ada3-0552519f52b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672679906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.672679906
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.644785308
Short name T290
Test name
Test status
Simulation time 4570553333 ps
CPU time 32.56 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:03:10 PM PDT 24
Peak memory 212252 kb
Host smart-70b0f142-ccf6-4e8b-a18c-21a6cce96df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644785308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.644785308
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1670509526
Short name T181
Test name
Test status
Simulation time 20139064241 ps
CPU time 13.27 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:53 PM PDT 24
Peak memory 211428 kb
Host smart-99b3a15f-d9ce-4ad4-8272-829391310088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670509526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1670509526
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2173361830
Short name T85
Test name
Test status
Simulation time 2385647299 ps
CPU time 25.03 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:03:03 PM PDT 24
Peak memory 213136 kb
Host smart-7ce8b4cb-2ab7-4da9-8a55-687b71a50a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173361830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2173361830
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.257090217
Short name T83
Test name
Test status
Simulation time 2936446213 ps
CPU time 44.02 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:03:22 PM PDT 24
Peak memory 219416 kb
Host smart-0318ebf9-a6ae-4e42-a631-8a9dcf663d90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257090217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.257090217
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.694856630
Short name T353
Test name
Test status
Simulation time 4141163634 ps
CPU time 11.16 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:49 PM PDT 24
Peak memory 211488 kb
Host smart-7da9a3e1-97c6-46a0-b567-352c4da7c2e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694856630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.694856630
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1348711888
Short name T264
Test name
Test status
Simulation time 1911754060 ps
CPU time 112.4 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:04:30 PM PDT 24
Peak memory 212696 kb
Host smart-7572a4d6-b393-4e6e-a9b2-c7e08d6f26f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348711888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1348711888
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1421473750
Short name T178
Test name
Test status
Simulation time 18199691508 ps
CPU time 25.03 seconds
Started Jul 17 07:02:33 PM PDT 24
Finished Jul 17 07:03:05 PM PDT 24
Peak memory 212224 kb
Host smart-4a62dd0c-7a05-4794-8e40-ce267051568f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421473750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1421473750
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1449279103
Short name T312
Test name
Test status
Simulation time 3513548553 ps
CPU time 14.01 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:53 PM PDT 24
Peak memory 211464 kb
Host smart-d5b20a7b-85c2-4edc-a52c-4b2d530cf90c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449279103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1449279103
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1192942457
Short name T329
Test name
Test status
Simulation time 4991257197 ps
CPU time 19.16 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:59 PM PDT 24
Peak memory 213312 kb
Host smart-6bc3dfd0-402d-4683-94d8-a3fc0a4802ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192942457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1192942457
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2321167782
Short name T230
Test name
Test status
Simulation time 15929307182 ps
CPU time 47.03 seconds
Started Jul 17 07:02:33 PM PDT 24
Finished Jul 17 07:03:28 PM PDT 24
Peak memory 214704 kb
Host smart-ef11bc3e-931b-489e-807d-e3395b60231a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321167782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2321167782
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2857425062
Short name T193
Test name
Test status
Simulation time 1324723662 ps
CPU time 6.67 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:10 PM PDT 24
Peak memory 211188 kb
Host smart-65a56f66-7c00-4ee2-a4c4-931fd6bbd382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857425062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2857425062
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.326367152
Short name T40
Test name
Test status
Simulation time 213083757486 ps
CPU time 282.76 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:06:41 PM PDT 24
Peak memory 228640 kb
Host smart-408b51ab-9129-4b7b-a0df-674cf29bc6ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326367152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.326367152
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1431225265
Short name T277
Test name
Test status
Simulation time 17539345874 ps
CPU time 24.32 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:02:25 PM PDT 24
Peak memory 211424 kb
Host smart-e105c903-57e8-4ff6-9786-a1599d35acd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431225265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1431225265
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3176799297
Short name T224
Test name
Test status
Simulation time 5536572451 ps
CPU time 9.71 seconds
Started Jul 17 07:01:52 PM PDT 24
Finished Jul 17 07:02:06 PM PDT 24
Peak memory 211292 kb
Host smart-47e2fe84-489d-4a9c-958b-152626a240ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176799297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3176799297
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2065031781
Short name T88
Test name
Test status
Simulation time 2151600470 ps
CPU time 25.46 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:22 PM PDT 24
Peak memory 213452 kb
Host smart-38de985b-3dd7-44ad-a8d4-eed4d9a07e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065031781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2065031781
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1526151443
Short name T151
Test name
Test status
Simulation time 8277918299 ps
CPU time 69.62 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:03:10 PM PDT 24
Peak memory 215868 kb
Host smart-3aa523df-1031-4964-ae37-55a2d8c92d42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526151443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1526151443
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.449613982
Short name T345
Test name
Test status
Simulation time 768655252 ps
CPU time 8.95 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:13 PM PDT 24
Peak memory 211320 kb
Host smart-0ce71691-ab19-4eff-bd20-c0f3947a75fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449613982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.449613982
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3379909235
Short name T323
Test name
Test status
Simulation time 28546459164 ps
CPU time 309.45 seconds
Started Jul 17 07:02:01 PM PDT 24
Finished Jul 17 07:07:19 PM PDT 24
Peak memory 233768 kb
Host smart-b4d6bb59-5e01-415b-876b-c15495125bbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379909235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3379909235
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1881102301
Short name T313
Test name
Test status
Simulation time 177148251 ps
CPU time 9.45 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:19 PM PDT 24
Peak memory 211704 kb
Host smart-cbe99cfd-4de8-470e-985b-0624b907edce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881102301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1881102301
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2146703636
Short name T49
Test name
Test status
Simulation time 388706119 ps
CPU time 5.75 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:15 PM PDT 24
Peak memory 211364 kb
Host smart-a756cfa1-27d0-459d-a90b-22b936698a1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146703636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2146703636
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3810410650
Short name T370
Test name
Test status
Simulation time 22229946818 ps
CPU time 28.43 seconds
Started Jul 17 07:01:40 PM PDT 24
Finished Jul 17 07:02:10 PM PDT 24
Peak memory 214448 kb
Host smart-7d64f916-c36d-40a5-995a-88d1d8a72dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810410650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3810410650
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2227665350
Short name T241
Test name
Test status
Simulation time 14099168184 ps
CPU time 33.66 seconds
Started Jul 17 07:02:00 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 213428 kb
Host smart-6310339d-a3f2-4788-8825-1852e4682781
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227665350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2227665350
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.199122084
Short name T24
Test name
Test status
Simulation time 85368848575 ps
CPU time 1527.37 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:27:35 PM PDT 24
Peak memory 235860 kb
Host smart-ed10d075-7ec2-4efa-ad99-fea2882abb5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199122084 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.199122084
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1647159509
Short name T191
Test name
Test status
Simulation time 2012388473 ps
CPU time 16.68 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:13 PM PDT 24
Peak memory 211356 kb
Host smart-8202bc46-de1f-4ef8-bed9-2e961c7da266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647159509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1647159509
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3563607265
Short name T223
Test name
Test status
Simulation time 73173361773 ps
CPU time 360.72 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:08:06 PM PDT 24
Peak memory 234212 kb
Host smart-2c8ccb67-a7e0-488b-8855-aa08954b6c9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563607265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3563607265
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.817371945
Short name T55
Test name
Test status
Simulation time 252227374 ps
CPU time 11.04 seconds
Started Jul 17 07:01:58 PM PDT 24
Finished Jul 17 07:02:18 PM PDT 24
Peak memory 211824 kb
Host smart-5969ffe3-4b22-4b1e-9f75-6fa422018653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817371945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.817371945
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2073905518
Short name T43
Test name
Test status
Simulation time 6370661309 ps
CPU time 11.83 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:16 PM PDT 24
Peak memory 211424 kb
Host smart-9419efd0-4b68-48ad-85ec-909034318bde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073905518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2073905518
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.125746421
Short name T188
Test name
Test status
Simulation time 3833506315 ps
CPU time 31.26 seconds
Started Jul 17 07:01:57 PM PDT 24
Finished Jul 17 07:02:37 PM PDT 24
Peak memory 213572 kb
Host smart-d230062b-dd9b-428f-a760-94d4e231e412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125746421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.125746421
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2729537022
Short name T172
Test name
Test status
Simulation time 5405776363 ps
CPU time 13.36 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:17 PM PDT 24
Peak memory 213500 kb
Host smart-b17429e6-6c30-4428-9310-7c4c456293ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729537022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2729537022
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3850698081
Short name T125
Test name
Test status
Simulation time 126777350 ps
CPU time 5.05 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:08 PM PDT 24
Peak memory 211320 kb
Host smart-8242fc4c-9111-4cf2-b916-f31ab69d4b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850698081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3850698081
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1792969221
Short name T357
Test name
Test status
Simulation time 177508894735 ps
CPU time 415.02 seconds
Started Jul 17 07:01:55 PM PDT 24
Finished Jul 17 07:08:56 PM PDT 24
Peak memory 233756 kb
Host smart-4ad410d1-d6ee-4808-ab6b-6c81c2fcd73c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792969221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1792969221
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3211607277
Short name T165
Test name
Test status
Simulation time 4938664111 ps
CPU time 23.73 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:27 PM PDT 24
Peak memory 212632 kb
Host smart-39b45392-f44a-42b9-8827-caf04ba8c837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211607277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3211607277
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3470343466
Short name T156
Test name
Test status
Simulation time 3776929652 ps
CPU time 10.5 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:09 PM PDT 24
Peak memory 211460 kb
Host smart-feb06661-697f-4fe6-a9cd-47038fae3cf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3470343466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3470343466
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.120642909
Short name T316
Test name
Test status
Simulation time 3856684936 ps
CPU time 33.73 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:02:32 PM PDT 24
Peak memory 213600 kb
Host smart-63d9fac0-375b-4fa0-a560-ff5baadd2f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120642909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.120642909
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2490467162
Short name T168
Test name
Test status
Simulation time 10308176682 ps
CPU time 27.06 seconds
Started Jul 17 07:01:46 PM PDT 24
Finished Jul 17 07:02:14 PM PDT 24
Peak memory 214528 kb
Host smart-dd3b89c5-652a-4852-97e0-946af6e8bed2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490467162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2490467162
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1855133210
Short name T315
Test name
Test status
Simulation time 1065492881 ps
CPU time 10.35 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:02:09 PM PDT 24
Peak memory 211352 kb
Host smart-d1140599-7834-48b5-8e3d-e3d37dd8d543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855133210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1855133210
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3473183604
Short name T330
Test name
Test status
Simulation time 94341590124 ps
CPU time 101.86 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:03:41 PM PDT 24
Peak memory 225780 kb
Host smart-c3906c18-e685-4c73-a799-8b14181e235e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473183604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3473183604
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4045484274
Short name T239
Test name
Test status
Simulation time 640678542 ps
CPU time 9.27 seconds
Started Jul 17 07:01:54 PM PDT 24
Finished Jul 17 07:02:08 PM PDT 24
Peak memory 211980 kb
Host smart-46e65b8f-af61-4c5c-ab95-4b1bf70ca2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045484274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4045484274
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2639235744
Short name T45
Test name
Test status
Simulation time 2465885556 ps
CPU time 10.1 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:14 PM PDT 24
Peak memory 211424 kb
Host smart-a9abb244-2a90-4f67-ab25-0f36a38ec1e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2639235744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2639235744
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2695467698
Short name T135
Test name
Test status
Simulation time 3037764144 ps
CPU time 27.09 seconds
Started Jul 17 07:01:53 PM PDT 24
Finished Jul 17 07:02:24 PM PDT 24
Peak memory 213088 kb
Host smart-3b195604-0bd1-4989-8a07-a2e97f90f38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695467698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2695467698
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2961479381
Short name T217
Test name
Test status
Simulation time 2532583114 ps
CPU time 10.16 seconds
Started Jul 17 07:01:56 PM PDT 24
Finished Jul 17 07:02:14 PM PDT 24
Peak memory 211432 kb
Host smart-3380745b-7eea-4782-9e0f-9ce72f74ac0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961479381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2961479381
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%