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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 96.89 91.99 97.67 100.00 98.28 97.30 99.07


Total test records in report: 470
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T308 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.701472992 Jul 18 06:07:03 PM PDT 24 Jul 18 06:07:17 PM PDT 24 334259623 ps
T28 /workspace/coverage/default/1.rom_ctrl_sec_cm.1673861827 Jul 18 06:06:33 PM PDT 24 Jul 18 06:07:39 PM PDT 24 1718706019 ps
T309 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1149742815 Jul 18 06:07:21 PM PDT 24 Jul 18 06:07:53 PM PDT 24 14008086328 ps
T310 /workspace/coverage/default/36.rom_ctrl_smoke.911132519 Jul 18 06:07:05 PM PDT 24 Jul 18 06:07:20 PM PDT 24 718474172 ps
T311 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.877772260 Jul 18 06:06:34 PM PDT 24 Jul 18 06:06:59 PM PDT 24 31104530309 ps
T312 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1887820544 Jul 18 06:06:49 PM PDT 24 Jul 18 06:07:25 PM PDT 24 3682871677 ps
T313 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3270474218 Jul 18 06:07:26 PM PDT 24 Jul 18 06:07:39 PM PDT 24 775797959 ps
T314 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.182891884 Jul 18 06:07:26 PM PDT 24 Jul 18 06:07:42 PM PDT 24 823535289 ps
T315 /workspace/coverage/default/13.rom_ctrl_stress_all.4053642068 Jul 18 06:06:43 PM PDT 24 Jul 18 06:07:23 PM PDT 24 6969784780 ps
T316 /workspace/coverage/default/20.rom_ctrl_smoke.737707925 Jul 18 06:06:43 PM PDT 24 Jul 18 06:06:57 PM PDT 24 618111457 ps
T317 /workspace/coverage/default/43.rom_ctrl_smoke.1933709667 Jul 18 06:07:26 PM PDT 24 Jul 18 06:08:14 PM PDT 24 15756131430 ps
T318 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.98543769 Jul 18 06:06:40 PM PDT 24 Jul 18 06:06:50 PM PDT 24 500260028 ps
T319 /workspace/coverage/default/45.rom_ctrl_smoke.4020056098 Jul 18 06:07:14 PM PDT 24 Jul 18 06:07:44 PM PDT 24 3234823939 ps
T320 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3719712614 Jul 18 06:07:19 PM PDT 24 Jul 18 06:07:36 PM PDT 24 3310248685 ps
T321 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1089995984 Jul 18 06:07:10 PM PDT 24 Jul 18 06:09:54 PM PDT 24 229334952412 ps
T322 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1900433442 Jul 18 06:07:03 PM PDT 24 Jul 18 06:07:25 PM PDT 24 14797408871 ps
T323 /workspace/coverage/default/13.rom_ctrl_alert_test.1263846955 Jul 18 06:06:43 PM PDT 24 Jul 18 06:06:58 PM PDT 24 1159457539 ps
T324 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2325708552 Jul 18 06:06:18 PM PDT 24 Jul 18 06:06:34 PM PDT 24 1386071662 ps
T325 /workspace/coverage/default/16.rom_ctrl_alert_test.1647442899 Jul 18 06:06:46 PM PDT 24 Jul 18 06:07:02 PM PDT 24 4287426482 ps
T326 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1547719533 Jul 18 06:07:15 PM PDT 24 Jul 18 06:07:29 PM PDT 24 1813642366 ps
T327 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2429808540 Jul 18 06:06:46 PM PDT 24 Jul 18 07:21:05 PM PDT 24 29888560226 ps
T328 /workspace/coverage/default/13.rom_ctrl_smoke.1096604584 Jul 18 06:06:35 PM PDT 24 Jul 18 06:07:09 PM PDT 24 3291361196 ps
T329 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1836328069 Jul 18 06:07:07 PM PDT 24 Jul 18 06:07:30 PM PDT 24 8954483959 ps
T330 /workspace/coverage/default/14.rom_ctrl_stress_all.3778689957 Jul 18 06:06:47 PM PDT 24 Jul 18 06:07:51 PM PDT 24 25698831893 ps
T331 /workspace/coverage/default/3.rom_ctrl_smoke.1665067069 Jul 18 06:06:33 PM PDT 24 Jul 18 06:06:48 PM PDT 24 610806971 ps
T332 /workspace/coverage/default/43.rom_ctrl_alert_test.266322161 Jul 18 06:07:20 PM PDT 24 Jul 18 06:07:30 PM PDT 24 760613671 ps
T333 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4109798723 Jul 18 06:07:05 PM PDT 24 Jul 18 06:10:22 PM PDT 24 18934668100 ps
T334 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1233782588 Jul 18 06:06:38 PM PDT 24 Jul 18 06:06:53 PM PDT 24 1018763358 ps
T335 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2605002087 Jul 18 06:06:48 PM PDT 24 Jul 18 06:11:53 PM PDT 24 31195093098 ps
T336 /workspace/coverage/default/4.rom_ctrl_smoke.281591368 Jul 18 06:06:34 PM PDT 24 Jul 18 06:06:58 PM PDT 24 1467584017 ps
T337 /workspace/coverage/default/17.rom_ctrl_alert_test.670984718 Jul 18 06:06:46 PM PDT 24 Jul 18 06:07:05 PM PDT 24 5753572678 ps
T338 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1778624674 Jul 18 06:06:47 PM PDT 24 Jul 18 06:07:03 PM PDT 24 691801446 ps
T339 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2534259532 Jul 18 06:06:32 PM PDT 24 Jul 18 06:07:08 PM PDT 24 38218400120 ps
T340 /workspace/coverage/default/7.rom_ctrl_stress_all.1916493378 Jul 18 06:06:31 PM PDT 24 Jul 18 06:07:07 PM PDT 24 1232534994 ps
T341 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3359309352 Jul 18 06:06:32 PM PDT 24 Jul 18 06:07:10 PM PDT 24 83761459337 ps
T342 /workspace/coverage/default/30.rom_ctrl_stress_all.2228066478 Jul 18 06:06:59 PM PDT 24 Jul 18 06:07:51 PM PDT 24 21183137578 ps
T343 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3137090439 Jul 18 06:07:19 PM PDT 24 Jul 18 06:08:49 PM PDT 24 2961051742 ps
T344 /workspace/coverage/default/34.rom_ctrl_stress_all.490421290 Jul 18 06:07:08 PM PDT 24 Jul 18 06:07:43 PM PDT 24 2640345118 ps
T345 /workspace/coverage/default/40.rom_ctrl_smoke.3940599813 Jul 18 06:07:04 PM PDT 24 Jul 18 06:07:37 PM PDT 24 3350688533 ps
T346 /workspace/coverage/default/31.rom_ctrl_stress_all.1780900437 Jul 18 06:06:59 PM PDT 24 Jul 18 06:08:09 PM PDT 24 16480865010 ps
T347 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2214762554 Jul 18 06:06:41 PM PDT 24 Jul 18 06:11:26 PM PDT 24 102401543615 ps
T29 /workspace/coverage/default/3.rom_ctrl_sec_cm.3633490159 Jul 18 06:06:35 PM PDT 24 Jul 18 06:07:42 PM PDT 24 7217732369 ps
T348 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1577900794 Jul 18 06:07:00 PM PDT 24 Jul 18 06:07:11 PM PDT 24 366051905 ps
T349 /workspace/coverage/default/1.rom_ctrl_smoke.1429687884 Jul 18 06:06:18 PM PDT 24 Jul 18 06:06:40 PM PDT 24 22077608552 ps
T350 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1753439453 Jul 18 06:07:09 PM PDT 24 Jul 18 06:51:41 PM PDT 24 49656138923 ps
T351 /workspace/coverage/default/18.rom_ctrl_stress_all.269753481 Jul 18 06:06:45 PM PDT 24 Jul 18 06:06:58 PM PDT 24 604749960 ps
T352 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1439567299 Jul 18 06:06:43 PM PDT 24 Jul 18 06:11:20 PM PDT 24 31276624008 ps
T353 /workspace/coverage/default/34.rom_ctrl_smoke.3841161108 Jul 18 06:07:02 PM PDT 24 Jul 18 06:07:23 PM PDT 24 961919983 ps
T354 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4201358390 Jul 18 06:07:10 PM PDT 24 Jul 18 06:09:09 PM PDT 24 6591971594 ps
T355 /workspace/coverage/default/38.rom_ctrl_smoke.79294031 Jul 18 06:07:05 PM PDT 24 Jul 18 06:07:20 PM PDT 24 772411720 ps
T356 /workspace/coverage/default/29.rom_ctrl_smoke.410026602 Jul 18 06:06:57 PM PDT 24 Jul 18 06:07:24 PM PDT 24 2658047612 ps
T357 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1794958357 Jul 18 06:06:34 PM PDT 24 Jul 18 06:11:18 PM PDT 24 526078453456 ps
T358 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4266405274 Jul 18 06:06:36 PM PDT 24 Jul 18 06:07:04 PM PDT 24 2202452491 ps
T359 /workspace/coverage/default/18.rom_ctrl_smoke.3445548305 Jul 18 06:06:44 PM PDT 24 Jul 18 06:07:21 PM PDT 24 4257892097 ps
T360 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2236746067 Jul 18 06:06:34 PM PDT 24 Jul 18 06:07:13 PM PDT 24 4143112564 ps
T361 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4186113585 Jul 18 06:06:51 PM PDT 24 Jul 18 06:59:19 PM PDT 24 323389550059 ps
T362 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3028783855 Jul 18 06:07:03 PM PDT 24 Jul 18 06:09:10 PM PDT 24 2115123405 ps
T363 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2690183362 Jul 18 06:06:43 PM PDT 24 Jul 18 06:10:18 PM PDT 24 20375948260 ps
T364 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3501660245 Jul 18 06:06:32 PM PDT 24 Jul 18 06:06:48 PM PDT 24 1663697433 ps
T365 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2731601348 Jul 18 06:06:58 PM PDT 24 Jul 18 06:07:21 PM PDT 24 2683338162 ps
T366 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4229619514 Jul 18 06:06:47 PM PDT 24 Jul 18 06:07:03 PM PDT 24 693332472 ps
T367 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.648195513 Jul 18 06:06:34 PM PDT 24 Jul 18 06:06:46 PM PDT 24 1532409044 ps
T368 /workspace/coverage/default/23.rom_ctrl_stress_all.2723778800 Jul 18 06:06:45 PM PDT 24 Jul 18 06:07:05 PM PDT 24 605665042 ps
T369 /workspace/coverage/default/49.rom_ctrl_smoke.920304849 Jul 18 06:07:27 PM PDT 24 Jul 18 06:07:46 PM PDT 24 1873585666 ps
T370 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4148102219 Jul 18 06:06:34 PM PDT 24 Jul 18 06:06:46 PM PDT 24 1171024631 ps
T371 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4141020839 Jul 18 06:06:48 PM PDT 24 Jul 18 06:07:02 PM PDT 24 3668063003 ps
T90 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1282530607 Jul 18 06:06:39 PM PDT 24 Jul 18 06:40:04 PM PDT 24 114810296124 ps
T91 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1748336914 Jul 18 06:07:14 PM PDT 24 Jul 18 06:07:48 PM PDT 24 20717910778 ps
T92 /workspace/coverage/default/41.rom_ctrl_stress_all.3185288551 Jul 18 06:07:10 PM PDT 24 Jul 18 06:08:18 PM PDT 24 5980721553 ps
T93 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1849446932 Jul 18 06:06:58 PM PDT 24 Jul 18 06:07:16 PM PDT 24 1405779974 ps
T94 /workspace/coverage/default/26.rom_ctrl_stress_all.2683546224 Jul 18 06:07:00 PM PDT 24 Jul 18 06:07:17 PM PDT 24 3433270449 ps
T95 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2005549379 Jul 18 06:07:10 PM PDT 24 Jul 18 06:07:21 PM PDT 24 438861229 ps
T96 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1925680492 Jul 18 06:07:01 PM PDT 24 Jul 18 06:07:28 PM PDT 24 2132108988 ps
T97 /workspace/coverage/default/9.rom_ctrl_smoke.3451972949 Jul 18 06:06:34 PM PDT 24 Jul 18 06:06:49 PM PDT 24 250196593 ps
T98 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3276518099 Jul 18 06:07:07 PM PDT 24 Jul 18 06:07:18 PM PDT 24 100042921 ps
T54 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2263781397 Jul 18 05:42:47 PM PDT 24 Jul 18 05:43:48 PM PDT 24 3604859298 ps
T57 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2486448865 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:04 PM PDT 24 1214524465 ps
T58 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.313600307 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:14 PM PDT 24 3867518052 ps
T100 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4078801556 Jul 18 05:42:54 PM PDT 24 Jul 18 05:43:26 PM PDT 24 3932710062 ps
T60 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2336018896 Jul 18 05:42:58 PM PDT 24 Jul 18 05:43:24 PM PDT 24 4668217025 ps
T101 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2526622779 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:01 PM PDT 24 309018637 ps
T61 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2835482161 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:03 PM PDT 24 87307002 ps
T372 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4193183042 Jul 18 05:42:59 PM PDT 24 Jul 18 05:43:32 PM PDT 24 6267544035 ps
T55 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.367089513 Jul 18 05:43:06 PM PDT 24 Jul 18 05:44:32 PM PDT 24 433137018 ps
T373 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2301315601 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:28 PM PDT 24 925902982 ps
T62 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2411874431 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:06 PM PDT 24 801121877 ps
T63 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3440843632 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:50 PM PDT 24 16601363718 ps
T64 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.824952752 Jul 18 05:42:59 PM PDT 24 Jul 18 05:43:18 PM PDT 24 1378494821 ps
T102 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4123018549 Jul 18 05:43:01 PM PDT 24 Jul 18 05:44:09 PM PDT 24 23299973689 ps
T65 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3371274658 Jul 18 05:42:54 PM PDT 24 Jul 18 05:43:57 PM PDT 24 43588566771 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2924665989 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:14 PM PDT 24 8765770989 ps
T84 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3540903754 Jul 18 05:42:55 PM PDT 24 Jul 18 05:43:26 PM PDT 24 3690359055 ps
T66 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3449338594 Jul 18 05:42:59 PM PDT 24 Jul 18 05:43:29 PM PDT 24 21561332206 ps
T56 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3442769669 Jul 18 05:42:53 PM PDT 24 Jul 18 05:44:23 PM PDT 24 5135547199 ps
T104 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2041299712 Jul 18 05:42:55 PM PDT 24 Jul 18 05:43:59 PM PDT 24 8550026605 ps
T85 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1720691739 Jul 18 05:42:55 PM PDT 24 Jul 18 05:43:20 PM PDT 24 836803188 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.722005835 Jul 18 05:42:47 PM PDT 24 Jul 18 05:43:20 PM PDT 24 2188302352 ps
T67 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3312647832 Jul 18 05:43:01 PM PDT 24 Jul 18 05:43:46 PM PDT 24 555546347 ps
T68 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.649186860 Jul 18 05:42:54 PM PDT 24 Jul 18 05:43:22 PM PDT 24 6052469712 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4019845297 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:11 PM PDT 24 1515949652 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1814407593 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:02 PM PDT 24 161433148 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3093137808 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:07 PM PDT 24 2574134007 ps
T108 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1577345047 Jul 18 05:42:42 PM PDT 24 Jul 18 05:44:08 PM PDT 24 210232449 ps
T71 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2144338006 Jul 18 05:43:05 PM PDT 24 Jul 18 05:44:33 PM PDT 24 25547039152 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.907525393 Jul 18 05:42:49 PM PDT 24 Jul 18 05:43:18 PM PDT 24 1506975207 ps
T86 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3777322975 Jul 18 05:43:06 PM PDT 24 Jul 18 05:43:28 PM PDT 24 1034503667 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4175800749 Jul 18 05:42:41 PM PDT 24 Jul 18 05:43:12 PM PDT 24 2127644449 ps
T72 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3987181508 Jul 18 05:43:04 PM PDT 24 Jul 18 05:44:07 PM PDT 24 19046436410 ps
T73 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1792623172 Jul 18 05:43:00 PM PDT 24 Jul 18 05:44:26 PM PDT 24 7504992572 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.504167315 Jul 18 05:42:53 PM PDT 24 Jul 18 05:43:17 PM PDT 24 866020419 ps
T88 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.945061150 Jul 18 05:43:02 PM PDT 24 Jul 18 05:43:25 PM PDT 24 212718149 ps
T106 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2736400266 Jul 18 05:43:08 PM PDT 24 Jul 18 05:44:44 PM PDT 24 2323491707 ps
T74 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4215581005 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:17 PM PDT 24 786125656 ps
T89 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1751558575 Jul 18 05:42:53 PM PDT 24 Jul 18 05:43:20 PM PDT 24 4883728824 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2222611189 Jul 18 05:42:41 PM PDT 24 Jul 18 05:43:03 PM PDT 24 333245553 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2507461849 Jul 18 05:42:38 PM PDT 24 Jul 18 05:43:10 PM PDT 24 2037763693 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3472590497 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:33 PM PDT 24 6731388308 ps
T384 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3823397514 Jul 18 05:42:58 PM PDT 24 Jul 18 05:43:24 PM PDT 24 3385519643 ps
T385 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1979864604 Jul 18 05:42:48 PM PDT 24 Jul 18 05:43:08 PM PDT 24 111687738 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2780282795 Jul 18 05:42:53 PM PDT 24 Jul 18 05:43:16 PM PDT 24 168701828 ps
T387 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2355518822 Jul 18 05:42:57 PM PDT 24 Jul 18 05:43:56 PM PDT 24 5563138186 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.192900947 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:05 PM PDT 24 652227695 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.714018854 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:05 PM PDT 24 510397274 ps
T390 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2544983719 Jul 18 05:42:58 PM PDT 24 Jul 18 05:43:25 PM PDT 24 541873150 ps
T391 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2265208798 Jul 18 05:43:04 PM PDT 24 Jul 18 05:43:31 PM PDT 24 4262287746 ps
T392 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3631070247 Jul 18 05:43:02 PM PDT 24 Jul 18 05:43:30 PM PDT 24 4969206541 ps
T75 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3273252333 Jul 18 05:43:01 PM PDT 24 Jul 18 05:44:44 PM PDT 24 22213833356 ps
T393 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.808075891 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:20 PM PDT 24 106329840 ps
T394 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3596786901 Jul 18 05:43:05 PM PDT 24 Jul 18 05:43:34 PM PDT 24 2737102997 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1134603778 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:29 PM PDT 24 7013809424 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3499549300 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:13 PM PDT 24 1716450176 ps
T107 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1108882742 Jul 18 05:43:01 PM PDT 24 Jul 18 05:44:27 PM PDT 24 964105574 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3439934801 Jul 18 05:42:53 PM PDT 24 Jul 18 05:43:12 PM PDT 24 92685667 ps
T398 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.155409953 Jul 18 05:43:06 PM PDT 24 Jul 18 05:44:39 PM PDT 24 7393214882 ps
T399 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4008633377 Jul 18 05:42:59 PM PDT 24 Jul 18 05:43:20 PM PDT 24 1378748139 ps
T400 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1863609758 Jul 18 05:43:08 PM PDT 24 Jul 18 05:43:33 PM PDT 24 333259210 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2999125995 Jul 18 05:42:41 PM PDT 24 Jul 18 05:43:03 PM PDT 24 519085552 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4040156193 Jul 18 05:42:54 PM PDT 24 Jul 18 05:43:19 PM PDT 24 3954047061 ps
T403 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1075681657 Jul 18 05:43:08 PM PDT 24 Jul 18 05:43:37 PM PDT 24 9802010055 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1725124866 Jul 18 05:42:57 PM PDT 24 Jul 18 05:44:24 PM PDT 24 16252295533 ps
T404 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2120367880 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:11 PM PDT 24 732767686 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4294757969 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:13 PM PDT 24 24221644248 ps
T109 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.365773255 Jul 18 05:42:58 PM PDT 24 Jul 18 05:44:26 PM PDT 24 1967169558 ps
T406 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3591248953 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:33 PM PDT 24 21516450746 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1004600748 Jul 18 05:43:01 PM PDT 24 Jul 18 05:43:56 PM PDT 24 1247163031 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1457066486 Jul 18 05:42:54 PM PDT 24 Jul 18 05:43:12 PM PDT 24 94023383 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.629650263 Jul 18 05:43:06 PM PDT 24 Jul 18 05:43:38 PM PDT 24 1787331059 ps
T409 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2455719448 Jul 18 05:42:45 PM PDT 24 Jul 18 05:43:06 PM PDT 24 1761899594 ps
T410 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3395693427 Jul 18 05:42:59 PM PDT 24 Jul 18 05:43:29 PM PDT 24 1515543680 ps
T411 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.174505566 Jul 18 05:43:03 PM PDT 24 Jul 18 05:43:31 PM PDT 24 1310574501 ps
T77 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1474361728 Jul 18 05:42:47 PM PDT 24 Jul 18 05:43:45 PM PDT 24 3966533066 ps
T412 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.172297526 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:17 PM PDT 24 3863440519 ps
T413 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2644856075 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:11 PM PDT 24 10354181184 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.185445692 Jul 18 05:42:39 PM PDT 24 Jul 18 05:43:01 PM PDT 24 85880274 ps
T415 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3121627886 Jul 18 05:42:48 PM PDT 24 Jul 18 05:43:11 PM PDT 24 515625973 ps
T112 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1415553235 Jul 18 05:43:01 PM PDT 24 Jul 18 05:44:32 PM PDT 24 5725284299 ps
T113 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2312612081 Jul 18 05:42:47 PM PDT 24 Jul 18 05:44:15 PM PDT 24 1546855571 ps
T416 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.964538890 Jul 18 05:42:48 PM PDT 24 Jul 18 05:43:12 PM PDT 24 558829731 ps
T82 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1651889233 Jul 18 05:42:44 PM PDT 24 Jul 18 05:44:39 PM PDT 24 12924930842 ps
T417 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.802302036 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:11 PM PDT 24 1557666136 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1564781321 Jul 18 05:42:59 PM PDT 24 Jul 18 05:43:55 PM PDT 24 7103898456 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.980615766 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:33 PM PDT 24 1797595948 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1174541142 Jul 18 05:42:44 PM PDT 24 Jul 18 05:43:14 PM PDT 24 6882195279 ps
T421 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.13338731 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:54 PM PDT 24 14886214740 ps
T422 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2550995952 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:03 PM PDT 24 400136505 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3600980009 Jul 18 05:42:49 PM PDT 24 Jul 18 05:43:48 PM PDT 24 1371110252 ps
T424 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4106642730 Jul 18 05:42:46 PM PDT 24 Jul 18 05:43:08 PM PDT 24 514628584 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.177537904 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:04 PM PDT 24 106732822 ps
T426 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3402081316 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:13 PM PDT 24 8130601959 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3641311128 Jul 18 05:42:50 PM PDT 24 Jul 18 05:43:19 PM PDT 24 1810631011 ps
T79 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.664826934 Jul 18 05:42:57 PM PDT 24 Jul 18 05:43:56 PM PDT 24 2278276261 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1094564491 Jul 18 05:42:42 PM PDT 24 Jul 18 05:44:31 PM PDT 24 75872877714 ps
T429 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3496518277 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:43 PM PDT 24 1409555490 ps
T430 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1480480983 Jul 18 05:43:02 PM PDT 24 Jul 18 05:43:30 PM PDT 24 1115924372 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.58874839 Jul 18 05:42:38 PM PDT 24 Jul 18 05:43:12 PM PDT 24 4102373334 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3199462465 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:12 PM PDT 24 6710311578 ps
T433 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.107183854 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:15 PM PDT 24 5014554059 ps
T434 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1054341732 Jul 18 05:43:04 PM PDT 24 Jul 18 05:43:31 PM PDT 24 2309723581 ps
T435 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1484036974 Jul 18 05:42:57 PM PDT 24 Jul 18 05:43:17 PM PDT 24 348296342 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1563603760 Jul 18 05:42:50 PM PDT 24 Jul 18 05:44:36 PM PDT 24 22699675780 ps
T437 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1763256103 Jul 18 05:43:04 PM PDT 24 Jul 18 05:43:31 PM PDT 24 4312402443 ps
T438 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1573622186 Jul 18 05:42:56 PM PDT 24 Jul 18 05:43:27 PM PDT 24 8432508456 ps
T439 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2150511187 Jul 18 05:42:59 PM PDT 24 Jul 18 05:43:22 PM PDT 24 428411136 ps
T440 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2881279474 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:12 PM PDT 24 3467630586 ps
T441 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1643497699 Jul 18 05:42:58 PM PDT 24 Jul 18 05:43:21 PM PDT 24 2254448879 ps
T442 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3145450828 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:51 PM PDT 24 595029181 ps
T443 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3448399530 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:34 PM PDT 24 2809114928 ps
T444 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3115517371 Jul 18 05:42:59 PM PDT 24 Jul 18 05:43:32 PM PDT 24 1299460749 ps
T445 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3358769880 Jul 18 05:42:56 PM PDT 24 Jul 18 05:43:30 PM PDT 24 15138931653 ps
T83 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1282678334 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:21 PM PDT 24 175548805 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4248277928 Jul 18 05:42:59 PM PDT 24 Jul 18 05:43:56 PM PDT 24 16726414155 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2158300831 Jul 18 05:42:46 PM PDT 24 Jul 18 05:43:16 PM PDT 24 2000544623 ps
T80 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3927249092 Jul 18 05:42:55 PM PDT 24 Jul 18 05:43:29 PM PDT 24 2277138673 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.139647548 Jul 18 05:42:52 PM PDT 24 Jul 18 05:43:11 PM PDT 24 91142227 ps
T449 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.702843658 Jul 18 05:42:42 PM PDT 24 Jul 18 05:44:09 PM PDT 24 224959843 ps
T450 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2419682058 Jul 18 05:42:58 PM PDT 24 Jul 18 05:43:23 PM PDT 24 866527496 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.736717125 Jul 18 05:42:47 PM PDT 24 Jul 18 05:43:20 PM PDT 24 6794562869 ps
T452 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3114183490 Jul 18 05:42:44 PM PDT 24 Jul 18 05:43:12 PM PDT 24 2686105268 ps
T81 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.851818140 Jul 18 05:42:47 PM PDT 24 Jul 18 05:43:38 PM PDT 24 8518436261 ps
T453 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.663493902 Jul 18 05:42:57 PM PDT 24 Jul 18 05:43:27 PM PDT 24 1743286749 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.456277334 Jul 18 05:42:41 PM PDT 24 Jul 18 05:43:10 PM PDT 24 7671133102 ps
T78 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1527050279 Jul 18 05:42:46 PM PDT 24 Jul 18 05:43:06 PM PDT 24 87960023 ps
T455 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2187222142 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:14 PM PDT 24 3807090034 ps
T456 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3355118345 Jul 18 05:42:56 PM PDT 24 Jul 18 05:43:55 PM PDT 24 2021495596 ps
T457 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2405125046 Jul 18 05:42:42 PM PDT 24 Jul 18 05:43:02 PM PDT 24 334247858 ps
T458 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.747249107 Jul 18 05:42:50 PM PDT 24 Jul 18 05:43:15 PM PDT 24 1041394415 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2776496886 Jul 18 05:42:43 PM PDT 24 Jul 18 05:43:08 PM PDT 24 3734897895 ps
T460 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2633870046 Jul 18 05:42:52 PM PDT 24 Jul 18 05:43:17 PM PDT 24 390143696 ps
T461 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2855860075 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:32 PM PDT 24 3399042969 ps
T110 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1029337224 Jul 18 05:42:52 PM PDT 24 Jul 18 05:43:48 PM PDT 24 873518629 ps
T462 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3156538157 Jul 18 05:42:54 PM PDT 24 Jul 18 05:43:14 PM PDT 24 297845988 ps
T463 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2499371987 Jul 18 05:42:55 PM PDT 24 Jul 18 05:43:21 PM PDT 24 1049326590 ps
T111 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1170017194 Jul 18 05:42:59 PM PDT 24 Jul 18 05:43:54 PM PDT 24 3302448246 ps
T464 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2447571737 Jul 18 05:43:08 PM PDT 24 Jul 18 05:43:35 PM PDT 24 3114492913 ps
T465 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2216057643 Jul 18 05:42:55 PM PDT 24 Jul 18 05:43:18 PM PDT 24 1170781413 ps
T466 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3504807368 Jul 18 05:43:07 PM PDT 24 Jul 18 05:43:33 PM PDT 24 142073289 ps
T467 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.854307048 Jul 18 05:42:56 PM PDT 24 Jul 18 05:43:17 PM PDT 24 1332602126 ps
T468 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.654062523 Jul 18 05:42:39 PM PDT 24 Jul 18 05:43:02 PM PDT 24 2519174122 ps
T469 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3632280856 Jul 18 05:43:00 PM PDT 24 Jul 18 05:43:29 PM PDT 24 1678533517 ps
T470 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1306823114 Jul 18 05:43:01 PM PDT 24 Jul 18 05:43:22 PM PDT 24 102124127 ps

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.642249582
Short name T4
Test name
Test status
Simulation time 131468050074 ps
CPU time 277.42 seconds
Started Jul 18 06:07:27 PM PDT 24
Finished Jul 18 06:12:08 PM PDT 24
Peak memory 225052 kb
Host smart-d7579039-d851-45c2-a5e0-39f9742dba7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642249582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.642249582
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3264647443
Short name T11
Test name
Test status
Simulation time 28329754534 ps
CPU time 1063.63 seconds
Started Jul 18 06:07:20 PM PDT 24
Finished Jul 18 06:25:07 PM PDT 24
Peak memory 232724 kb
Host smart-f4e2866d-59f3-4aae-9a5d-cf3de9ef52c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264647443 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3264647443
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1386399099
Short name T2
Test name
Test status
Simulation time 118323383 ps
CPU time 9.02 seconds
Started Jul 18 06:06:31 PM PDT 24
Finished Jul 18 06:06:42 PM PDT 24
Peak memory 211428 kb
Host smart-b7c6151a-71a9-4835-9b37-4527ce4f9e84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386399099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1386399099
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3442769669
Short name T56
Test name
Test status
Simulation time 5135547199 ps
CPU time 74.82 seconds
Started Jul 18 05:42:53 PM PDT 24
Finished Jul 18 05:44:23 PM PDT 24
Peak memory 218920 kb
Host smart-6abc9ffb-0e62-4aa5-be78-8633a87950c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442769669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3442769669
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3439970764
Short name T38
Test name
Test status
Simulation time 2237509788 ps
CPU time 107.28 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:08:49 PM PDT 24
Peak memory 233956 kb
Host smart-62fa37c8-dc98-424d-9316-c3473e980a11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439970764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3439970764
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.138024718
Short name T20
Test name
Test status
Simulation time 894743767 ps
CPU time 53.84 seconds
Started Jul 18 06:06:29 PM PDT 24
Finished Jul 18 06:07:24 PM PDT 24
Peak memory 236872 kb
Host smart-bc1a56a2-d2f4-474e-aec4-5c8797360e4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138024718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.138024718
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.779039464
Short name T33
Test name
Test status
Simulation time 1230408533 ps
CPU time 6.93 seconds
Started Jul 18 06:07:08 PM PDT 24
Finished Jul 18 06:07:19 PM PDT 24
Peak memory 211320 kb
Host smart-977c4d1a-34b8-4a65-a76e-6be601223c32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779039464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.779039464
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2835482161
Short name T61
Test name
Test status
Simulation time 87307002 ps
CPU time 4.44 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:03 PM PDT 24
Peak memory 217352 kb
Host smart-b998e58f-42f2-4ea6-8e15-ddec104a006d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835482161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2835482161
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1832879859
Short name T14
Test name
Test status
Simulation time 80453568602 ps
CPU time 3153.03 seconds
Started Jul 18 06:07:16 PM PDT 24
Finished Jul 18 06:59:52 PM PDT 24
Peak memory 244128 kb
Host smart-9da46e08-24b6-4326-8557-b3c64605773a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832879859 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1832879859
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.775786766
Short name T23
Test name
Test status
Simulation time 2307804913 ps
CPU time 17.16 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:07:11 PM PDT 24
Peak memory 211944 kb
Host smart-ded838ef-9085-4bea-a069-dcc8cd7a9eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775786766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.775786766
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.483207526
Short name T172
Test name
Test status
Simulation time 7917916871 ps
CPU time 24.52 seconds
Started Jul 18 06:06:39 PM PDT 24
Finished Jul 18 06:07:07 PM PDT 24
Peak memory 212288 kb
Host smart-e1ad3b75-b357-44ab-9c54-2e98e0ecfa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483207526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.483207526
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1094564491
Short name T428
Test name
Test status
Simulation time 75872877714 ps
CPU time 93.79 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:44:31 PM PDT 24
Peak memory 210772 kb
Host smart-a0a50c17-9b47-49e5-b0ee-efb2917fdc3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094564491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1094564491
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2041299712
Short name T104
Test name
Test status
Simulation time 8550026605 ps
CPU time 48.14 seconds
Started Jul 18 05:42:55 PM PDT 24
Finished Jul 18 05:43:59 PM PDT 24
Peak memory 211320 kb
Host smart-deead92c-4c8b-4b72-87be-dd46ca5edfd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041299712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2041299712
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2108272338
Short name T6
Test name
Test status
Simulation time 1853497154 ps
CPU time 22.42 seconds
Started Jul 18 06:07:03 PM PDT 24
Finished Jul 18 06:07:31 PM PDT 24
Peak memory 213680 kb
Host smart-27b18c6d-0f2b-47ea-b161-38207f0a5147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108272338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2108272338
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1415553235
Short name T112
Test name
Test status
Simulation time 5725284299 ps
CPU time 74.99 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:44:32 PM PDT 24
Peak memory 218884 kb
Host smart-adf37898-1e91-4e4a-8a86-389cc666f130
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415553235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1415553235
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2736400266
Short name T106
Test name
Test status
Simulation time 2323491707 ps
CPU time 78.52 seconds
Started Jul 18 05:43:08 PM PDT 24
Finished Jul 18 05:44:44 PM PDT 24
Peak memory 211060 kb
Host smart-0d8064f2-e4cd-4eb9-80e4-5818d413da91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736400266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2736400266
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2312612081
Short name T113
Test name
Test status
Simulation time 1546855571 ps
CPU time 72.5 seconds
Started Jul 18 05:42:47 PM PDT 24
Finished Jul 18 05:44:15 PM PDT 24
Peak memory 211108 kb
Host smart-1dce1788-4e6c-45cf-b8f9-6310d3253de9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312612081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2312612081
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.824952752
Short name T64
Test name
Test status
Simulation time 1378494821 ps
CPU time 4.37 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:18 PM PDT 24
Peak memory 218160 kb
Host smart-96a80ea0-8a31-4fec-a62b-5a7b7fa67629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824952752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.824952752
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2526622779
Short name T101
Test name
Test status
Simulation time 309018637 ps
CPU time 4.26 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:01 PM PDT 24
Peak memory 210564 kb
Host smart-d7cd4cac-9547-45cc-8976-1ad8accd9434
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526622779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2526622779
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.907525393
Short name T379
Test name
Test status
Simulation time 1506975207 ps
CPU time 13.42 seconds
Started Jul 18 05:42:49 PM PDT 24
Finished Jul 18 05:43:18 PM PDT 24
Peak memory 210748 kb
Host smart-f65ce213-a578-4088-9fde-c29642529b6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907525393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.907525393
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3121627886
Short name T415
Test name
Test status
Simulation time 515625973 ps
CPU time 8.25 seconds
Started Jul 18 05:42:48 PM PDT 24
Finished Jul 18 05:43:11 PM PDT 24
Peak memory 210524 kb
Host smart-7e9f9723-bdb1-47a1-8c5c-7e5fb0a97b34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121627886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3121627886
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.313600307
Short name T58
Test name
Test status
Simulation time 3867518052 ps
CPU time 15.81 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:14 PM PDT 24
Peak memory 218880 kb
Host smart-6720732d-a2d1-4051-87f2-0dc3d5b00929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313600307 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.313600307
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2158300831
Short name T447
Test name
Test status
Simulation time 2000544623 ps
CPU time 15.51 seconds
Started Jul 18 05:42:46 PM PDT 24
Finished Jul 18 05:43:16 PM PDT 24
Peak memory 210492 kb
Host smart-95655849-30cd-4e91-b230-efbea965746e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158300831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2158300831
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.964538890
Short name T416
Test name
Test status
Simulation time 558829731 ps
CPU time 7.62 seconds
Started Jul 18 05:42:48 PM PDT 24
Finished Jul 18 05:43:12 PM PDT 24
Peak memory 210576 kb
Host smart-40d1d091-aa7f-4867-baf0-0298f5dba7e6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964538890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.964538890
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3093137808
Short name T378
Test name
Test status
Simulation time 2574134007 ps
CPU time 8.4 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:07 PM PDT 24
Peak memory 210484 kb
Host smart-4a784cd6-2c95-44c5-aa16-4d39fadd9030
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093137808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3093137808
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1474361728
Short name T77
Test name
Test status
Simulation time 3966533066 ps
CPU time 41.94 seconds
Started Jul 18 05:42:47 PM PDT 24
Finished Jul 18 05:43:45 PM PDT 24
Peak memory 210656 kb
Host smart-96dda5ed-48a9-48f5-99e5-0cd890af5205
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474361728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1474361728
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2776496886
Short name T459
Test name
Test status
Simulation time 3734897895 ps
CPU time 9.27 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:08 PM PDT 24
Peak memory 218788 kb
Host smart-b36af5c2-379b-4ef2-9b60-400b34b388ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776496886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2776496886
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.58874839
Short name T431
Test name
Test status
Simulation time 4102373334 ps
CPU time 17.76 seconds
Started Jul 18 05:42:38 PM PDT 24
Finished Jul 18 05:43:12 PM PDT 24
Peak memory 218836 kb
Host smart-a1bb97bc-3039-4bef-8950-750812d5e2a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58874839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.58874839
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1577345047
Short name T108
Test name
Test status
Simulation time 210232449 ps
CPU time 70.11 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 212192 kb
Host smart-124d80c1-c8c8-4f57-b1a0-d90cb519b3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577345047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1577345047
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3641311128
Short name T427
Test name
Test status
Simulation time 1810631011 ps
CPU time 14.96 seconds
Started Jul 18 05:42:50 PM PDT 24
Finished Jul 18 05:43:19 PM PDT 24
Peak memory 218488 kb
Host smart-96308189-07b6-4be3-9a91-969f8145ee85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641311128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3641311128
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2187222142
Short name T455
Test name
Test status
Simulation time 3807090034 ps
CPU time 14.88 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:14 PM PDT 24
Peak memory 210560 kb
Host smart-0a3723b3-3045-45b1-b43a-d0839ca7124f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187222142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2187222142
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2507461849
Short name T382
Test name
Test status
Simulation time 2037763693 ps
CPU time 15.78 seconds
Started Jul 18 05:42:38 PM PDT 24
Finished Jul 18 05:43:10 PM PDT 24
Peak memory 218880 kb
Host smart-cc847af7-053e-4ada-9b65-48028b8d1633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507461849 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2507461849
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1814407593
Short name T377
Test name
Test status
Simulation time 161433148 ps
CPU time 4.18 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:02 PM PDT 24
Peak memory 210572 kb
Host smart-6de1e4c6-e879-4871-b787-53003d8c3067
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814407593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1814407593
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1174541142
Short name T420
Test name
Test status
Simulation time 6882195279 ps
CPU time 14.27 seconds
Started Jul 18 05:42:44 PM PDT 24
Finished Jul 18 05:43:14 PM PDT 24
Peak memory 210532 kb
Host smart-829d9901-087d-4b2a-b80a-7ff126a4ecb3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174541142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1174541142
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4019845297
Short name T376
Test name
Test status
Simulation time 1515949652 ps
CPU time 13.25 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:11 PM PDT 24
Peak memory 210400 kb
Host smart-38ce4906-8742-4c1c-9f66-cd31311b670f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019845297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4019845297
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2644856075
Short name T413
Test name
Test status
Simulation time 10354181184 ps
CPU time 13.08 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:11 PM PDT 24
Peak memory 210752 kb
Host smart-bedd67ac-126b-47c8-b9e7-f0449b49dd7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644856075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2644856075
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.736717125
Short name T451
Test name
Test status
Simulation time 6794562869 ps
CPU time 16.31 seconds
Started Jul 18 05:42:47 PM PDT 24
Finished Jul 18 05:43:20 PM PDT 24
Peak memory 218884 kb
Host smart-ce5d1fe0-51ef-4b9e-af6b-62e2a2545084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736717125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.736717125
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2499371987
Short name T463
Test name
Test status
Simulation time 1049326590 ps
CPU time 10.42 seconds
Started Jul 18 05:42:55 PM PDT 24
Finished Jul 18 05:43:21 PM PDT 24
Peak memory 214036 kb
Host smart-f61335a3-7584-4e6c-a88d-ebd7f37b20bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499371987 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2499371987
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.649186860
Short name T68
Test name
Test status
Simulation time 6052469712 ps
CPU time 13.14 seconds
Started Jul 18 05:42:54 PM PDT 24
Finished Jul 18 05:43:22 PM PDT 24
Peak memory 210540 kb
Host smart-b170827f-faaf-4d8c-aa71-65760a5048de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649186860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.649186860
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1792623172
Short name T73
Test name
Test status
Simulation time 7504992572 ps
CPU time 70.54 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:44:26 PM PDT 24
Peak memory 210732 kb
Host smart-2eb6afd6-3629-4342-8e06-8f6503e3a53f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792623172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1792623172
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1134603778
Short name T395
Test name
Test status
Simulation time 7013809424 ps
CPU time 14.05 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:29 PM PDT 24
Peak memory 210812 kb
Host smart-72da3096-280c-4cc0-a079-a4a8b1b208fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134603778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1134603778
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2855860075
Short name T461
Test name
Test status
Simulation time 3399042969 ps
CPU time 16.43 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:32 PM PDT 24
Peak memory 218836 kb
Host smart-2ec18a70-5c90-4372-834c-bfdf054cb0d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855860075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2855860075
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.365773255
Short name T109
Test name
Test status
Simulation time 1967169558 ps
CPU time 72.69 seconds
Started Jul 18 05:42:58 PM PDT 24
Finished Jul 18 05:44:26 PM PDT 24
Peak memory 218736 kb
Host smart-0c53049d-0235-405f-ab9b-2ed657286df5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365773255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.365773255
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.854307048
Short name T467
Test name
Test status
Simulation time 1332602126 ps
CPU time 6.03 seconds
Started Jul 18 05:42:56 PM PDT 24
Finished Jul 18 05:43:17 PM PDT 24
Peak memory 218796 kb
Host smart-3469618b-53ae-4c6e-892e-6ecf286f53c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854307048 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.854307048
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1484036974
Short name T435
Test name
Test status
Simulation time 348296342 ps
CPU time 4.22 seconds
Started Jul 18 05:42:57 PM PDT 24
Finished Jul 18 05:43:17 PM PDT 24
Peak memory 210508 kb
Host smart-e38da183-1103-4739-bce2-02c0458d6f9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484036974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1484036974
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3927249092
Short name T80
Test name
Test status
Simulation time 2277138673 ps
CPU time 18.91 seconds
Started Jul 18 05:42:55 PM PDT 24
Finished Jul 18 05:43:29 PM PDT 24
Peak memory 210692 kb
Host smart-91bea095-e603-4192-ab78-563835617ca7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927249092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3927249092
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3472590497
Short name T383
Test name
Test status
Simulation time 6731388308 ps
CPU time 17.86 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:33 PM PDT 24
Peak memory 218280 kb
Host smart-4308ebfa-a9be-4aee-b12a-4abba4c095f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472590497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3472590497
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.663493902
Short name T453
Test name
Test status
Simulation time 1743286749 ps
CPU time 14.61 seconds
Started Jul 18 05:42:57 PM PDT 24
Finished Jul 18 05:43:27 PM PDT 24
Peak memory 218848 kb
Host smart-728ac161-25d0-4155-abc6-b668c7b2b762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663493902 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.663493902
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2216057643
Short name T465
Test name
Test status
Simulation time 1170781413 ps
CPU time 6.76 seconds
Started Jul 18 05:42:55 PM PDT 24
Finished Jul 18 05:43:18 PM PDT 24
Peak memory 217828 kb
Host smart-92e52af1-ba46-47d3-ba71-ccc82e21d4d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216057643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2216057643
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.664826934
Short name T79
Test name
Test status
Simulation time 2278276261 ps
CPU time 43.52 seconds
Started Jul 18 05:42:57 PM PDT 24
Finished Jul 18 05:43:56 PM PDT 24
Peak memory 210620 kb
Host smart-d6f67fbe-5511-4d3a-a7f8-7bf61a6c8e18
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664826934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.664826934
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3358769880
Short name T445
Test name
Test status
Simulation time 15138931653 ps
CPU time 17.93 seconds
Started Jul 18 05:42:56 PM PDT 24
Finished Jul 18 05:43:30 PM PDT 24
Peak memory 210800 kb
Host smart-b0cf6fe1-9325-4c97-9125-48efd46656e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358769880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3358769880
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4193183042
Short name T372
Test name
Test status
Simulation time 6267544035 ps
CPU time 17.72 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:32 PM PDT 24
Peak memory 218940 kb
Host smart-ecda19fc-c3dd-4363-a6df-da5112e0c3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193183042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4193183042
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2355518822
Short name T387
Test name
Test status
Simulation time 5563138186 ps
CPU time 43.64 seconds
Started Jul 18 05:42:57 PM PDT 24
Finished Jul 18 05:43:56 PM PDT 24
Peak memory 218924 kb
Host smart-a33c2b0b-22e2-4c6a-9edb-9c1482e95f86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355518822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2355518822
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3823397514
Short name T384
Test name
Test status
Simulation time 3385519643 ps
CPU time 10.23 seconds
Started Jul 18 05:42:58 PM PDT 24
Finished Jul 18 05:43:24 PM PDT 24
Peak memory 218860 kb
Host smart-44436a42-a5e7-4bc6-8d86-eac1853ea33a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823397514 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3823397514
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1282678334
Short name T83
Test name
Test status
Simulation time 175548805 ps
CPU time 4.32 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:21 PM PDT 24
Peak memory 210492 kb
Host smart-81758fbb-6460-46e2-a52d-583f2a573610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282678334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1282678334
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3355118345
Short name T456
Test name
Test status
Simulation time 2021495596 ps
CPU time 42.65 seconds
Started Jul 18 05:42:56 PM PDT 24
Finished Jul 18 05:43:55 PM PDT 24
Peak memory 210556 kb
Host smart-91c61527-5c73-4b2a-b94a-be5de203a4fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355118345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3355118345
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1720691739
Short name T85
Test name
Test status
Simulation time 836803188 ps
CPU time 9.83 seconds
Started Jul 18 05:42:55 PM PDT 24
Finished Jul 18 05:43:20 PM PDT 24
Peak memory 218712 kb
Host smart-6d4dc7b7-edf9-4c1a-a0d0-eb86352293ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720691739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1720691739
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2544983719
Short name T390
Test name
Test status
Simulation time 541873150 ps
CPU time 11.53 seconds
Started Jul 18 05:42:58 PM PDT 24
Finished Jul 18 05:43:25 PM PDT 24
Peak memory 218824 kb
Host smart-c0a0d4b9-4868-463c-a5d7-ab5b05b92359
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544983719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2544983719
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1306823114
Short name T470
Test name
Test status
Simulation time 102124127 ps
CPU time 4.76 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:43:22 PM PDT 24
Peak memory 218804 kb
Host smart-b03de31d-76b4-4658-a4fa-ffdf3b6644c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306823114 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1306823114
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2419682058
Short name T450
Test name
Test status
Simulation time 866527496 ps
CPU time 9.58 seconds
Started Jul 18 05:42:58 PM PDT 24
Finished Jul 18 05:43:23 PM PDT 24
Peak memory 210524 kb
Host smart-aa6b23b9-5c95-453f-98af-5f43870fc83f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419682058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2419682058
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3440843632
Short name T63
Test name
Test status
Simulation time 16601363718 ps
CPU time 34.91 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:50 PM PDT 24
Peak memory 210728 kb
Host smart-b03a16d9-ae14-4fef-adf8-6736a6cba65f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440843632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3440843632
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3632280856
Short name T469
Test name
Test status
Simulation time 1678533517 ps
CPU time 12.51 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:29 PM PDT 24
Peak memory 218760 kb
Host smart-511c3b2c-a3a3-469b-9f1a-4219f873fd8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632280856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3632280856
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3395693427
Short name T410
Test name
Test status
Simulation time 1515543680 ps
CPU time 15.3 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:29 PM PDT 24
Peak memory 218824 kb
Host smart-e84f68d7-b38d-4f2b-a7b7-a85c5ea8fe9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395693427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3395693427
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3145450828
Short name T442
Test name
Test status
Simulation time 595029181 ps
CPU time 35.98 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:51 PM PDT 24
Peak memory 218728 kb
Host smart-a1c591f8-1070-496b-8e86-8e68b9ec2568
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145450828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3145450828
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1480480983
Short name T430
Test name
Test status
Simulation time 1115924372 ps
CPU time 11.3 seconds
Started Jul 18 05:43:02 PM PDT 24
Finished Jul 18 05:43:30 PM PDT 24
Peak memory 218756 kb
Host smart-46541293-70d1-4ccc-9837-5a7062f28595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480480983 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1480480983
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3449338594
Short name T66
Test name
Test status
Simulation time 21561332206 ps
CPU time 13.32 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:29 PM PDT 24
Peak memory 210644 kb
Host smart-0168a951-f188-446b-a2ce-3fc45ed47ee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449338594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3449338594
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4123018549
Short name T102
Test name
Test status
Simulation time 23299973689 ps
CPU time 51.84 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:44:09 PM PDT 24
Peak memory 210736 kb
Host smart-ad650afb-2a28-4153-8f23-b19ceb293f47
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123018549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4123018549
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3631070247
Short name T392
Test name
Test status
Simulation time 4969206541 ps
CPU time 11.92 seconds
Started Jul 18 05:43:02 PM PDT 24
Finished Jul 18 05:43:30 PM PDT 24
Peak memory 210772 kb
Host smart-ae4a3543-4c45-4bfb-80c2-a5956fecb6eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631070247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3631070247
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3448399530
Short name T443
Test name
Test status
Simulation time 2809114928 ps
CPU time 17.81 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:34 PM PDT 24
Peak memory 218856 kb
Host smart-a89075d6-4280-42c6-8ab4-f50ae1ac45a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448399530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3448399530
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1108882742
Short name T107
Test name
Test status
Simulation time 964105574 ps
CPU time 69.85 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:44:27 PM PDT 24
Peak memory 212132 kb
Host smart-a197f12d-8ca3-4818-bf36-31f25dbbc2b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108882742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1108882742
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3115517371
Short name T444
Test name
Test status
Simulation time 1299460749 ps
CPU time 10.12 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:32 PM PDT 24
Peak memory 218840 kb
Host smart-c43812b3-722b-4ae1-877e-bf4e983a4f4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115517371 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3115517371
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3596786901
Short name T394
Test name
Test status
Simulation time 2737102997 ps
CPU time 11.62 seconds
Started Jul 18 05:43:05 PM PDT 24
Finished Jul 18 05:43:34 PM PDT 24
Peak memory 218772 kb
Host smart-637ee257-24b6-4f16-b740-006c40483e9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596786901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3596786901
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3312647832
Short name T67
Test name
Test status
Simulation time 555546347 ps
CPU time 28.21 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:43:46 PM PDT 24
Peak memory 210628 kb
Host smart-4e330d77-ba42-426e-b472-03cb03b8c8a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312647832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3312647832
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4008633377
Short name T399
Test name
Test status
Simulation time 1378748139 ps
CPU time 4.27 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:20 PM PDT 24
Peak memory 210572 kb
Host smart-575d756f-b17e-4387-8c82-a77a44944373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008633377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4008633377
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.980615766
Short name T419
Test name
Test status
Simulation time 1797595948 ps
CPU time 16.93 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:33 PM PDT 24
Peak memory 218776 kb
Host smart-49000a39-540a-4f4d-a897-ede0955cd980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980615766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.980615766
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4248277928
Short name T446
Test name
Test status
Simulation time 16726414155 ps
CPU time 40.34 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:56 PM PDT 24
Peak memory 212060 kb
Host smart-f5a17976-ed09-4716-9311-d10ff24df205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248277928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4248277928
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.629650263
Short name T408
Test name
Test status
Simulation time 1787331059 ps
CPU time 14.87 seconds
Started Jul 18 05:43:06 PM PDT 24
Finished Jul 18 05:43:38 PM PDT 24
Peak memory 218848 kb
Host smart-6470a9c6-8b81-4f60-91ba-9c91765d6063
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629650263 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.629650263
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1763256103
Short name T437
Test name
Test status
Simulation time 4312402443 ps
CPU time 10.48 seconds
Started Jul 18 05:43:04 PM PDT 24
Finished Jul 18 05:43:31 PM PDT 24
Peak memory 210708 kb
Host smart-a8312672-0deb-43f2-a782-638dfb1651ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763256103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1763256103
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3273252333
Short name T75
Test name
Test status
Simulation time 22213833356 ps
CPU time 86.52 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:44:44 PM PDT 24
Peak memory 211860 kb
Host smart-1d05870f-9585-4b91-bbc9-2ea4f59df8b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273252333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3273252333
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.174505566
Short name T411
Test name
Test status
Simulation time 1310574501 ps
CPU time 11.83 seconds
Started Jul 18 05:43:03 PM PDT 24
Finished Jul 18 05:43:31 PM PDT 24
Peak memory 210620 kb
Host smart-f5ca7825-f648-4695-9b9b-cc65b0d3d3ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174505566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.174505566
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2301315601
Short name T373
Test name
Test status
Simulation time 925902982 ps
CPU time 12.97 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:28 PM PDT 24
Peak memory 218820 kb
Host smart-f9072027-0205-4f6b-8063-5fb477fbb089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301315601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2301315601
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.155409953
Short name T398
Test name
Test status
Simulation time 7393214882 ps
CPU time 76.02 seconds
Started Jul 18 05:43:06 PM PDT 24
Finished Jul 18 05:44:39 PM PDT 24
Peak memory 218896 kb
Host smart-a8af9451-6ffc-432d-b1b4-e9d130a06563
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155409953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.155409953
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1075681657
Short name T403
Test name
Test status
Simulation time 9802010055 ps
CPU time 11.47 seconds
Started Jul 18 05:43:08 PM PDT 24
Finished Jul 18 05:43:37 PM PDT 24
Peak memory 218984 kb
Host smart-a127ce38-9626-40e3-ac59-b0577b8d8dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075681657 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1075681657
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2447571737
Short name T464
Test name
Test status
Simulation time 3114492913 ps
CPU time 8.97 seconds
Started Jul 18 05:43:08 PM PDT 24
Finished Jul 18 05:43:35 PM PDT 24
Peak memory 210620 kb
Host smart-41100590-df63-403f-9497-187a299e95bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447571737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2447571737
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2144338006
Short name T71
Test name
Test status
Simulation time 25547039152 ps
CPU time 70.63 seconds
Started Jul 18 05:43:05 PM PDT 24
Finished Jul 18 05:44:33 PM PDT 24
Peak memory 210780 kb
Host smart-4134cffb-ae28-4463-b953-65aa6d0bde09
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144338006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2144338006
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2150511187
Short name T439
Test name
Test status
Simulation time 428411136 ps
CPU time 7.12 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:22 PM PDT 24
Peak memory 217820 kb
Host smart-4f7d6e3e-d1f6-42c6-a94f-b2f03043ab16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150511187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2150511187
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3504807368
Short name T466
Test name
Test status
Simulation time 142073289 ps
CPU time 9.13 seconds
Started Jul 18 05:43:07 PM PDT 24
Finished Jul 18 05:43:33 PM PDT 24
Peak memory 218804 kb
Host smart-3d898232-49d9-4a8b-b95a-3cc9f2bdbfaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504807368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3504807368
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1054341732
Short name T434
Test name
Test status
Simulation time 2309723581 ps
CPU time 11.25 seconds
Started Jul 18 05:43:04 PM PDT 24
Finished Jul 18 05:43:31 PM PDT 24
Peak memory 218976 kb
Host smart-cce09ba3-1cdd-4aaf-905b-e09fa6c040e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054341732 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1054341732
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2265208798
Short name T391
Test name
Test status
Simulation time 4262287746 ps
CPU time 10.63 seconds
Started Jul 18 05:43:04 PM PDT 24
Finished Jul 18 05:43:31 PM PDT 24
Peak memory 210620 kb
Host smart-3aa3dbaf-68f7-4122-bffe-4031e3de0701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265208798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2265208798
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3987181508
Short name T72
Test name
Test status
Simulation time 19046436410 ps
CPU time 46.69 seconds
Started Jul 18 05:43:04 PM PDT 24
Finished Jul 18 05:44:07 PM PDT 24
Peak memory 210828 kb
Host smart-0b98b1a2-af54-4d3a-b46f-575476de2df2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987181508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3987181508
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3777322975
Short name T86
Test name
Test status
Simulation time 1034503667 ps
CPU time 4.36 seconds
Started Jul 18 05:43:06 PM PDT 24
Finished Jul 18 05:43:28 PM PDT 24
Peak memory 210620 kb
Host smart-e5c599e3-ad6d-4db8-9621-689eef7fbeed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777322975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3777322975
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1863609758
Short name T400
Test name
Test status
Simulation time 333259210 ps
CPU time 6.37 seconds
Started Jul 18 05:43:08 PM PDT 24
Finished Jul 18 05:43:33 PM PDT 24
Peak memory 218864 kb
Host smart-debb6cc6-1da8-479c-8061-8a19bbb280fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863609758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1863609758
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.367089513
Short name T55
Test name
Test status
Simulation time 433137018 ps
CPU time 68.5 seconds
Started Jul 18 05:43:06 PM PDT 24
Finished Jul 18 05:44:32 PM PDT 24
Peak memory 218804 kb
Host smart-8eb5a41b-dea2-4b2b-a822-d97059251518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367089513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.367089513
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1527050279
Short name T78
Test name
Test status
Simulation time 87960023 ps
CPU time 4.42 seconds
Started Jul 18 05:42:46 PM PDT 24
Finished Jul 18 05:43:06 PM PDT 24
Peak memory 210512 kb
Host smart-8f6ac33c-b2c4-47d4-aa31-b6994bf2dbaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527050279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1527050279
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2924665989
Short name T374
Test name
Test status
Simulation time 8765770989 ps
CPU time 16.16 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:14 PM PDT 24
Peak memory 210616 kb
Host smart-66a65c18-787a-436c-ad0e-d67008306c6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924665989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2924665989
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2486448865
Short name T57
Test name
Test status
Simulation time 1214524465 ps
CPU time 5.86 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:04 PM PDT 24
Peak memory 210508 kb
Host smart-9ddeb5fb-dac0-4d15-9263-cc2071f477ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486448865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2486448865
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.456277334
Short name T454
Test name
Test status
Simulation time 7671133102 ps
CPU time 14.7 seconds
Started Jul 18 05:42:41 PM PDT 24
Finished Jul 18 05:43:10 PM PDT 24
Peak memory 218964 kb
Host smart-32934453-1a3a-4026-89eb-72ca7894ec44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456277334 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.456277334
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.654062523
Short name T468
Test name
Test status
Simulation time 2519174122 ps
CPU time 7.21 seconds
Started Jul 18 05:42:39 PM PDT 24
Finished Jul 18 05:43:02 PM PDT 24
Peak memory 210564 kb
Host smart-37684510-d246-496c-adfc-53807dc1f870
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654062523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.654062523
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.722005835
Short name T375
Test name
Test status
Simulation time 2188302352 ps
CPU time 17.26 seconds
Started Jul 18 05:42:47 PM PDT 24
Finished Jul 18 05:43:20 PM PDT 24
Peak memory 210456 kb
Host smart-bc4cc7ef-754c-4443-a1c7-d3c5f070973e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722005835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.722005835
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4294757969
Short name T405
Test name
Test status
Simulation time 24221644248 ps
CPU time 14.77 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:13 PM PDT 24
Peak memory 210524 kb
Host smart-7a8d03f3-3a20-4754-8a19-f6eb0fe81dc2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294757969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4294757969
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1564781321
Short name T418
Test name
Test status
Simulation time 7103898456 ps
CPU time 40.35 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:55 PM PDT 24
Peak memory 210712 kb
Host smart-baa058b5-bbb9-4675-8a63-3ce558c32c62
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564781321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1564781321
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.747249107
Short name T458
Test name
Test status
Simulation time 1041394415 ps
CPU time 10.66 seconds
Started Jul 18 05:42:50 PM PDT 24
Finished Jul 18 05:43:15 PM PDT 24
Peak memory 218932 kb
Host smart-cd3bd89a-2693-4e67-8d6e-70880189e327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747249107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.747249107
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2780282795
Short name T386
Test name
Test status
Simulation time 168701828 ps
CPU time 8.31 seconds
Started Jul 18 05:42:53 PM PDT 24
Finished Jul 18 05:43:16 PM PDT 24
Peak memory 218600 kb
Host smart-4f04e9cf-a8b7-4b6d-b7d3-a197f13a9674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780282795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2780282795
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3600980009
Short name T423
Test name
Test status
Simulation time 1371110252 ps
CPU time 44.7 seconds
Started Jul 18 05:42:49 PM PDT 24
Finished Jul 18 05:43:48 PM PDT 24
Peak memory 218980 kb
Host smart-f52ca882-1d22-4356-95ae-ba9110273331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600980009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3600980009
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3199462465
Short name T432
Test name
Test status
Simulation time 6710311578 ps
CPU time 14.25 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:12 PM PDT 24
Peak memory 218804 kb
Host smart-99dc831f-7583-4685-9f18-888d942ebf7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199462465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3199462465
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4175800749
Short name T380
Test name
Test status
Simulation time 2127644449 ps
CPU time 15.92 seconds
Started Jul 18 05:42:41 PM PDT 24
Finished Jul 18 05:43:12 PM PDT 24
Peak memory 210572 kb
Host smart-8302b47f-27c0-49b1-98bc-f42df7de76bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175800749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4175800749
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2633870046
Short name T460
Test name
Test status
Simulation time 390143696 ps
CPU time 9.78 seconds
Started Jul 18 05:42:52 PM PDT 24
Finished Jul 18 05:43:17 PM PDT 24
Peak memory 210432 kb
Host smart-6695f453-7aaa-4640-9a53-265e089fd325
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633870046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2633870046
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.714018854
Short name T389
Test name
Test status
Simulation time 510397274 ps
CPU time 6.78 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:05 PM PDT 24
Peak memory 214620 kb
Host smart-902b1144-24a0-4d2f-a018-2b915bba8bd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714018854 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.714018854
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4040156193
Short name T402
Test name
Test status
Simulation time 3954047061 ps
CPU time 9.73 seconds
Started Jul 18 05:42:54 PM PDT 24
Finished Jul 18 05:43:19 PM PDT 24
Peak memory 218744 kb
Host smart-06e05f49-6f66-4728-8c5b-5609a4cc7e18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040156193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4040156193
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3402081316
Short name T426
Test name
Test status
Simulation time 8130601959 ps
CPU time 15.45 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:13 PM PDT 24
Peak memory 210492 kb
Host smart-6f371878-d643-4995-86ed-190e54ca8f83
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402081316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3402081316
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.192900947
Short name T388
Test name
Test status
Simulation time 652227695 ps
CPU time 7.45 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:05 PM PDT 24
Peak memory 210388 kb
Host smart-3efe58bc-816c-431c-8f49-3cbaaf20a3a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192900947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
192900947
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1563603760
Short name T436
Test name
Test status
Simulation time 22699675780 ps
CPU time 91.03 seconds
Started Jul 18 05:42:50 PM PDT 24
Finished Jul 18 05:44:36 PM PDT 24
Peak memory 211020 kb
Host smart-f2936822-f375-421b-bedb-d7abbd54ae8a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563603760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1563603760
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1751558575
Short name T89
Test name
Test status
Simulation time 4883728824 ps
CPU time 11.53 seconds
Started Jul 18 05:42:53 PM PDT 24
Finished Jul 18 05:43:20 PM PDT 24
Peak memory 210580 kb
Host smart-1e092587-990f-43b3-a027-bec42bb2ef1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751558575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1751558575
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.185445692
Short name T414
Test name
Test status
Simulation time 85880274 ps
CPU time 6.56 seconds
Started Jul 18 05:42:39 PM PDT 24
Finished Jul 18 05:43:01 PM PDT 24
Peak memory 215208 kb
Host smart-2a3de6d1-6a9e-4ba9-bdae-dc286998baf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185445692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.185445692
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3439934801
Short name T397
Test name
Test status
Simulation time 92685667 ps
CPU time 4.21 seconds
Started Jul 18 05:42:53 PM PDT 24
Finished Jul 18 05:43:12 PM PDT 24
Peak memory 210464 kb
Host smart-776d5a6d-20ec-4bfc-80f6-e0e9383e8f3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439934801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3439934801
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2999125995
Short name T401
Test name
Test status
Simulation time 519085552 ps
CPU time 7.57 seconds
Started Jul 18 05:42:41 PM PDT 24
Finished Jul 18 05:43:03 PM PDT 24
Peak memory 217240 kb
Host smart-64ad3809-770b-4547-a0f7-83eca3ed5835
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999125995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2999125995
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4078801556
Short name T100
Test name
Test status
Simulation time 3932710062 ps
CPU time 16.22 seconds
Started Jul 18 05:42:54 PM PDT 24
Finished Jul 18 05:43:26 PM PDT 24
Peak memory 218680 kb
Host smart-c9da29b8-c5fe-4be1-a905-698335b082d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078801556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4078801556
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.177537904
Short name T425
Test name
Test status
Simulation time 106732822 ps
CPU time 5.22 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:04 PM PDT 24
Peak memory 218812 kb
Host smart-79a5c80a-d217-4f53-b218-cfa0553090de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177537904 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.177537904
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3156538157
Short name T462
Test name
Test status
Simulation time 297845988 ps
CPU time 4.47 seconds
Started Jul 18 05:42:54 PM PDT 24
Finished Jul 18 05:43:14 PM PDT 24
Peak memory 210556 kb
Host smart-e16eca3e-c1f4-43cc-96ce-01b8de5386ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156538157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3156538157
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1457066486
Short name T407
Test name
Test status
Simulation time 94023383 ps
CPU time 4.14 seconds
Started Jul 18 05:42:54 PM PDT 24
Finished Jul 18 05:43:12 PM PDT 24
Peak memory 210428 kb
Host smart-29889ff6-3187-4d68-b00e-5cf606d38ecd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457066486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1457066486
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.139647548
Short name T448
Test name
Test status
Simulation time 91142227 ps
CPU time 4.11 seconds
Started Jul 18 05:42:52 PM PDT 24
Finished Jul 18 05:43:11 PM PDT 24
Peak memory 210424 kb
Host smart-01ca0809-6ab6-4edb-85f0-1c3be0f44fec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139647548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
139647548
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3371274658
Short name T65
Test name
Test status
Simulation time 43588566771 ps
CPU time 48.61 seconds
Started Jul 18 05:42:54 PM PDT 24
Finished Jul 18 05:43:57 PM PDT 24
Peak memory 210748 kb
Host smart-6d4e1968-8d83-4da4-ad93-d47c782b3863
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371274658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3371274658
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.504167315
Short name T87
Test name
Test status
Simulation time 866020419 ps
CPU time 9.63 seconds
Started Jul 18 05:42:53 PM PDT 24
Finished Jul 18 05:43:17 PM PDT 24
Peak memory 217916 kb
Host smart-ca62457d-0579-4401-880b-fc3a9d691c53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504167315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.504167315
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2222611189
Short name T381
Test name
Test status
Simulation time 333245553 ps
CPU time 6.21 seconds
Started Jul 18 05:42:41 PM PDT 24
Finished Jul 18 05:43:03 PM PDT 24
Peak memory 218820 kb
Host smart-2fc1b85f-6858-4f37-a0f1-0c309d09849c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222611189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2222611189
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1029337224
Short name T110
Test name
Test status
Simulation time 873518629 ps
CPU time 40.7 seconds
Started Jul 18 05:42:52 PM PDT 24
Finished Jul 18 05:43:48 PM PDT 24
Peak memory 210808 kb
Host smart-36d4875f-6824-4c80-b646-88aa2f43e57d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029337224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1029337224
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2550995952
Short name T422
Test name
Test status
Simulation time 400136505 ps
CPU time 4.4 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:03 PM PDT 24
Peak memory 218752 kb
Host smart-24567316-7742-4fef-a786-ed9abfa8ecc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550995952 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2550995952
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2405125046
Short name T457
Test name
Test status
Simulation time 334247858 ps
CPU time 4.2 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:02 PM PDT 24
Peak memory 210552 kb
Host smart-bc294ef6-a294-4683-93fb-eac325be3642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405125046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2405125046
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.851818140
Short name T81
Test name
Test status
Simulation time 8518436261 ps
CPU time 36.5 seconds
Started Jul 18 05:42:47 PM PDT 24
Finished Jul 18 05:43:38 PM PDT 24
Peak memory 210688 kb
Host smart-4b00f826-1b1a-490b-999c-44a2138736d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851818140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.851818140
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.802302036
Short name T417
Test name
Test status
Simulation time 1557666136 ps
CPU time 13.78 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:11 PM PDT 24
Peak memory 218756 kb
Host smart-5170ea06-2b38-4322-9f75-4f3eded67ed4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802302036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.802302036
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2120367880
Short name T404
Test name
Test status
Simulation time 732767686 ps
CPU time 13.14 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:43:11 PM PDT 24
Peak memory 218804 kb
Host smart-829f3036-78dc-4f74-a6d2-59a91dd5045c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120367880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2120367880
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3496518277
Short name T429
Test name
Test status
Simulation time 1409555490 ps
CPU time 44.25 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:43 PM PDT 24
Peak memory 210664 kb
Host smart-34b61008-3350-4119-8db9-20f04ebbb9c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496518277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3496518277
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2881279474
Short name T440
Test name
Test status
Simulation time 3467630586 ps
CPU time 14.12 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:12 PM PDT 24
Peak memory 218868 kb
Host smart-e06c34a0-bbe9-4232-b630-0c2b9885a47b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881279474 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2881279474
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3499549300
Short name T396
Test name
Test status
Simulation time 1716450176 ps
CPU time 14.4 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:13 PM PDT 24
Peak memory 210560 kb
Host smart-8e775aca-e66b-4a25-8e40-688f6b7fd824
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499549300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3499549300
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1651889233
Short name T82
Test name
Test status
Simulation time 12924930842 ps
CPU time 99.43 seconds
Started Jul 18 05:42:44 PM PDT 24
Finished Jul 18 05:44:39 PM PDT 24
Peak memory 211760 kb
Host smart-21e6f351-1531-44af-bc97-cd05d05a4309
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651889233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1651889233
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4106642730
Short name T424
Test name
Test status
Simulation time 514628584 ps
CPU time 6.35 seconds
Started Jul 18 05:42:46 PM PDT 24
Finished Jul 18 05:43:08 PM PDT 24
Peak memory 218220 kb
Host smart-c23d843d-9135-4b4f-a81d-e98056bc2dff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106642730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4106642730
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.107183854
Short name T433
Test name
Test status
Simulation time 5014554059 ps
CPU time 16.54 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:15 PM PDT 24
Peak memory 218852 kb
Host smart-503eda54-e7b8-4911-947c-f3b5c968916f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107183854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.107183854
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.702843658
Short name T449
Test name
Test status
Simulation time 224959843 ps
CPU time 70.99 seconds
Started Jul 18 05:42:42 PM PDT 24
Finished Jul 18 05:44:09 PM PDT 24
Peak memory 212204 kb
Host smart-74135040-208f-4ca3-a999-e5f61573bd00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702843658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.702843658
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1979864604
Short name T385
Test name
Test status
Simulation time 111687738 ps
CPU time 5.02 seconds
Started Jul 18 05:42:48 PM PDT 24
Finished Jul 18 05:43:08 PM PDT 24
Peak memory 218784 kb
Host smart-5751554b-d7bb-4c65-b502-ca8b1a7e6268
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979864604 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1979864604
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2411874431
Short name T62
Test name
Test status
Simulation time 801121877 ps
CPU time 6.73 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:06 PM PDT 24
Peak memory 217452 kb
Host smart-edc1ffd5-fe12-4d18-8d34-f987d64d00b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411874431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2411874431
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.13338731
Short name T421
Test name
Test status
Simulation time 14886214740 ps
CPU time 55.55 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:54 PM PDT 24
Peak memory 210744 kb
Host smart-fce394cc-5420-4c48-b0ab-77d0291b5cdd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13338731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pass
thru_mem_tl_intg_err.13338731
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2455719448
Short name T409
Test name
Test status
Simulation time 1761899594 ps
CPU time 6.2 seconds
Started Jul 18 05:42:45 PM PDT 24
Finished Jul 18 05:43:06 PM PDT 24
Peak memory 217892 kb
Host smart-fc7f1b32-a38d-4637-81de-e55259e47f07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455719448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2455719448
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.172297526
Short name T412
Test name
Test status
Simulation time 3863440519 ps
CPU time 19.09 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:17 PM PDT 24
Peak memory 218880 kb
Host smart-afa14889-c353-44db-86d5-59662db5d430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172297526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.172297526
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2263781397
Short name T54
Test name
Test status
Simulation time 3604859298 ps
CPU time 45.61 seconds
Started Jul 18 05:42:47 PM PDT 24
Finished Jul 18 05:43:48 PM PDT 24
Peak memory 218824 kb
Host smart-225a1393-3046-487d-b4e7-dc07fd56df93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263781397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2263781397
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1643497699
Short name T441
Test name
Test status
Simulation time 2254448879 ps
CPU time 7.81 seconds
Started Jul 18 05:42:58 PM PDT 24
Finished Jul 18 05:43:21 PM PDT 24
Peak memory 211904 kb
Host smart-eab74b99-99b3-4a56-b7b9-d5091ebf09c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643497699 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1643497699
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2336018896
Short name T60
Test name
Test status
Simulation time 4668217025 ps
CPU time 10.81 seconds
Started Jul 18 05:42:58 PM PDT 24
Finished Jul 18 05:43:24 PM PDT 24
Peak memory 210612 kb
Host smart-0e39bfd4-60f9-4287-a67e-78b5c4d47c6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336018896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2336018896
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4215581005
Short name T74
Test name
Test status
Simulation time 786125656 ps
CPU time 18.18 seconds
Started Jul 18 05:42:43 PM PDT 24
Finished Jul 18 05:43:17 PM PDT 24
Peak memory 210576 kb
Host smart-276f130b-4061-41e5-8692-584ead267072
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215581005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4215581005
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3540903754
Short name T84
Test name
Test status
Simulation time 3690359055 ps
CPU time 15.14 seconds
Started Jul 18 05:42:55 PM PDT 24
Finished Jul 18 05:43:26 PM PDT 24
Peak memory 218828 kb
Host smart-298895c3-a8bc-4db2-a28d-6fd59be3ee18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540903754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3540903754
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3114183490
Short name T452
Test name
Test status
Simulation time 2686105268 ps
CPU time 12.31 seconds
Started Jul 18 05:42:44 PM PDT 24
Finished Jul 18 05:43:12 PM PDT 24
Peak memory 218848 kb
Host smart-81d88512-3061-4a30-9d98-e99e1c6b2182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114183490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3114183490
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1170017194
Short name T111
Test name
Test status
Simulation time 3302448246 ps
CPU time 39.52 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:54 PM PDT 24
Peak memory 211048 kb
Host smart-aa1eb4fa-f528-4205-b2a1-2e459ebc748c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170017194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1170017194
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.808075891
Short name T393
Test name
Test status
Simulation time 106329840 ps
CPU time 5.01 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:20 PM PDT 24
Peak memory 213936 kb
Host smart-56f90812-402d-48c2-b213-ec660d4fcc4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808075891 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.808075891
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1573622186
Short name T438
Test name
Test status
Simulation time 8432508456 ps
CPU time 15.67 seconds
Started Jul 18 05:42:56 PM PDT 24
Finished Jul 18 05:43:27 PM PDT 24
Peak memory 210560 kb
Host smart-43781c88-85e0-4197-9469-2cfd49f1f4b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573622186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1573622186
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1725124866
Short name T76
Test name
Test status
Simulation time 16252295533 ps
CPU time 71.53 seconds
Started Jul 18 05:42:57 PM PDT 24
Finished Jul 18 05:44:24 PM PDT 24
Peak memory 210724 kb
Host smart-0a42064e-b1a0-477c-8932-9783a0f7dc7a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725124866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1725124866
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.945061150
Short name T88
Test name
Test status
Simulation time 212718149 ps
CPU time 6.06 seconds
Started Jul 18 05:43:02 PM PDT 24
Finished Jul 18 05:43:25 PM PDT 24
Peak memory 218744 kb
Host smart-b08b8e0c-9900-417e-9a15-cfdd1fdccc2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945061150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.945061150
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3591248953
Short name T406
Test name
Test status
Simulation time 21516450746 ps
CPU time 17.38 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:33 PM PDT 24
Peak memory 217944 kb
Host smart-9a362285-1bd3-4971-99dd-276580f16211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591248953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3591248953
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1004600748
Short name T105
Test name
Test status
Simulation time 1247163031 ps
CPU time 39.11 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:43:56 PM PDT 24
Peak memory 218796 kb
Host smart-87b98d47-b8d6-4543-813b-dc08288938ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004600748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1004600748
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3874604311
Short name T193
Test name
Test status
Simulation time 496228532 ps
CPU time 7.48 seconds
Started Jul 18 06:06:19 PM PDT 24
Finished Jul 18 06:06:31 PM PDT 24
Peak memory 211380 kb
Host smart-05c6a3c2-d67b-4b63-9aaf-2b783d971186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874604311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3874604311
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4114775498
Short name T156
Test name
Test status
Simulation time 131551151654 ps
CPU time 236.6 seconds
Started Jul 18 06:06:10 PM PDT 24
Finished Jul 18 06:10:11 PM PDT 24
Peak memory 237116 kb
Host smart-d4c4ca7c-7b0c-4a98-ba78-3a2c446d5116
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114775498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4114775498
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2325708552
Short name T324
Test name
Test status
Simulation time 1386071662 ps
CPU time 11.62 seconds
Started Jul 18 06:06:18 PM PDT 24
Finished Jul 18 06:06:34 PM PDT 24
Peak memory 211876 kb
Host smart-31497660-3fe1-4ff1-bf58-6a4b20021c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325708552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2325708552
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1049582593
Short name T139
Test name
Test status
Simulation time 1627779468 ps
CPU time 15.25 seconds
Started Jul 18 06:06:12 PM PDT 24
Finished Jul 18 06:06:31 PM PDT 24
Peak memory 211420 kb
Host smart-3c2f1406-3eb0-4c26-a239-3c5000bd2fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049582593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1049582593
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1706702793
Short name T22
Test name
Test status
Simulation time 5501308684 ps
CPU time 58.38 seconds
Started Jul 18 06:06:10 PM PDT 24
Finished Jul 18 06:07:12 PM PDT 24
Peak memory 236036 kb
Host smart-f83ba477-5b56-4e53-8ced-4a4596b7975e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706702793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1706702793
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.344846908
Short name T69
Test name
Test status
Simulation time 14967279257 ps
CPU time 33.65 seconds
Started Jul 18 06:06:11 PM PDT 24
Finished Jul 18 06:06:49 PM PDT 24
Peak memory 213696 kb
Host smart-a4239421-645b-4246-b36e-5e1136f96451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344846908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.344846908
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3923543554
Short name T18
Test name
Test status
Simulation time 2409558355 ps
CPU time 17.67 seconds
Started Jul 18 06:06:15 PM PDT 24
Finished Jul 18 06:06:37 PM PDT 24
Peak memory 213512 kb
Host smart-fb4aeb50-ff5a-4b4f-a095-d7d10f60a17c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923543554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3923543554
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.770826230
Short name T13
Test name
Test status
Simulation time 34998150058 ps
CPU time 2372.78 seconds
Started Jul 18 06:06:27 PM PDT 24
Finished Jul 18 06:46:01 PM PDT 24
Peak memory 235100 kb
Host smart-e9ff0e36-470a-4a21-9693-460a9d690894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770826230 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.770826230
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3520479666
Short name T293
Test name
Test status
Simulation time 437019068 ps
CPU time 4.25 seconds
Started Jul 18 06:06:35 PM PDT 24
Finished Jul 18 06:06:44 PM PDT 24
Peak memory 211372 kb
Host smart-e9826264-6511-4c9d-9ec8-6906bb7c3e98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520479666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3520479666
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3283379223
Short name T180
Test name
Test status
Simulation time 30597187293 ps
CPU time 263.84 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:11:03 PM PDT 24
Peak memory 212664 kb
Host smart-a204de45-e737-4c0b-97d7-ce0af1661c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283379223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3283379223
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3365329527
Short name T235
Test name
Test status
Simulation time 1038791505 ps
CPU time 11.25 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:50 PM PDT 24
Peak memory 211968 kb
Host smart-f5ce552e-72c8-48bb-a544-c8166c4335c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365329527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3365329527
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2950239742
Short name T241
Test name
Test status
Simulation time 3033566143 ps
CPU time 14.21 seconds
Started Jul 18 06:06:10 PM PDT 24
Finished Jul 18 06:06:28 PM PDT 24
Peak memory 211456 kb
Host smart-9a9e2a63-0249-4a23-a1d5-04c1c5b16d4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950239742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2950239742
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1673861827
Short name T28
Test name
Test status
Simulation time 1718706019 ps
CPU time 61.64 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 06:07:39 PM PDT 24
Peak memory 237784 kb
Host smart-45043623-6321-45a8-932f-4be3f1732478
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673861827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1673861827
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1429687884
Short name T349
Test name
Test status
Simulation time 22077608552 ps
CPU time 18.12 seconds
Started Jul 18 06:06:18 PM PDT 24
Finished Jul 18 06:06:40 PM PDT 24
Peak memory 214372 kb
Host smart-b3a65918-f5ac-407f-8b2c-e56a983df7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429687884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1429687884
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3814768790
Short name T151
Test name
Test status
Simulation time 4802251824 ps
CPU time 47.69 seconds
Started Jul 18 06:06:10 PM PDT 24
Finished Jul 18 06:07:02 PM PDT 24
Peak memory 216532 kb
Host smart-64370078-cd92-4ca0-8318-f9ec976bda1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814768790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3814768790
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1057504023
Short name T45
Test name
Test status
Simulation time 144992792498 ps
CPU time 502.11 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 06:15:00 PM PDT 24
Peak memory 235876 kb
Host smart-23056a7d-8fb0-4eda-9108-a0723b7c6cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057504023 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1057504023
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3115652947
Short name T152
Test name
Test status
Simulation time 8187602720 ps
CPU time 16.1 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:06:53 PM PDT 24
Peak memory 211444 kb
Host smart-717e78a8-7d6a-4c14-a235-a12ce328ed36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115652947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3115652947
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2587651657
Short name T147
Test name
Test status
Simulation time 19761199954 ps
CPU time 96.39 seconds
Started Jul 18 06:06:29 PM PDT 24
Finished Jul 18 06:08:06 PM PDT 24
Peak memory 211616 kb
Host smart-cce86e8e-db9d-443b-b665-912cf037ce99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587651657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2587651657
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2534259532
Short name T339
Test name
Test status
Simulation time 38218400120 ps
CPU time 31.09 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:07:08 PM PDT 24
Peak memory 212272 kb
Host smart-1aa5063a-3781-4237-bc59-292e5587218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534259532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2534259532
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1233782588
Short name T334
Test name
Test status
Simulation time 1018763358 ps
CPU time 11.24 seconds
Started Jul 18 06:06:38 PM PDT 24
Finished Jul 18 06:06:53 PM PDT 24
Peak memory 211396 kb
Host smart-ed6e313f-d800-41a8-9c99-56873ecb6b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233782588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1233782588
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3617441530
Short name T217
Test name
Test status
Simulation time 4112433199 ps
CPU time 31.06 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:07:10 PM PDT 24
Peak memory 212696 kb
Host smart-c1f9ce77-1ee0-415f-995f-f6ca4922a915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617441530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3617441530
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3255411431
Short name T298
Test name
Test status
Simulation time 593776598 ps
CPU time 32.74 seconds
Started Jul 18 06:06:38 PM PDT 24
Finished Jul 18 06:07:14 PM PDT 24
Peak memory 215964 kb
Host smart-45e945a6-b4d9-4688-9336-33e99aa5d5d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255411431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3255411431
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1282530607
Short name T90
Test name
Test status
Simulation time 114810296124 ps
CPU time 2001.4 seconds
Started Jul 18 06:06:39 PM PDT 24
Finished Jul 18 06:40:04 PM PDT 24
Peak memory 235856 kb
Host smart-07d19515-73ee-450e-9fa5-a60246f3492d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282530607 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1282530607
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.209591434
Short name T176
Test name
Test status
Simulation time 166331557 ps
CPU time 5.05 seconds
Started Jul 18 06:06:36 PM PDT 24
Finished Jul 18 06:06:45 PM PDT 24
Peak memory 211296 kb
Host smart-f54e6e64-a0a2-4379-8cb4-352802a502a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209591434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.209591434
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3495449736
Short name T275
Test name
Test status
Simulation time 156011176216 ps
CPU time 452.15 seconds
Started Jul 18 06:06:31 PM PDT 24
Finished Jul 18 06:14:07 PM PDT 24
Peak memory 237908 kb
Host smart-1e959193-4958-42a2-86e8-495082340e44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495449736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3495449736
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1301325927
Short name T296
Test name
Test status
Simulation time 1520942049 ps
CPU time 9.32 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:48 PM PDT 24
Peak memory 211396 kb
Host smart-d3163349-064a-4ce6-8287-b6bd768f5996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301325927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1301325927
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3464166005
Short name T138
Test name
Test status
Simulation time 4067434028 ps
CPU time 33.44 seconds
Started Jul 18 06:06:38 PM PDT 24
Finished Jul 18 06:07:15 PM PDT 24
Peak memory 213316 kb
Host smart-b6d3e7c1-0dfc-4358-b87f-b2a914c30aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464166005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3464166005
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1939093507
Short name T252
Test name
Test status
Simulation time 402665006 ps
CPU time 22.94 seconds
Started Jul 18 06:06:38 PM PDT 24
Finished Jul 18 06:07:05 PM PDT 24
Peak memory 216048 kb
Host smart-3cf914f7-42b3-4def-89a4-9ee49456559e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939093507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1939093507
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1373664162
Short name T46
Test name
Test status
Simulation time 228529832207 ps
CPU time 2154.67 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:42:31 PM PDT 24
Peak memory 235904 kb
Host smart-685b2394-4490-4db4-8a46-c252e0cc610f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373664162 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1373664162
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2262087306
Short name T145
Test name
Test status
Simulation time 333948638 ps
CPU time 4.33 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 06:06:42 PM PDT 24
Peak memory 211388 kb
Host smart-bbf03c9e-1d50-4837-90d9-56d668b519fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262087306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2262087306
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2214762554
Short name T347
Test name
Test status
Simulation time 102401543615 ps
CPU time 282.03 seconds
Started Jul 18 06:06:41 PM PDT 24
Finished Jul 18 06:11:26 PM PDT 24
Peak memory 212656 kb
Host smart-4c02354a-7608-425c-9d97-9803076628af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214762554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2214762554
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1693008577
Short name T243
Test name
Test status
Simulation time 1028244015 ps
CPU time 15.82 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:06:52 PM PDT 24
Peak memory 211860 kb
Host smart-cbcc246a-be67-420a-9750-3d75aee61ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693008577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1693008577
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.98543769
Short name T318
Test name
Test status
Simulation time 500260028 ps
CPU time 7.55 seconds
Started Jul 18 06:06:40 PM PDT 24
Finished Jul 18 06:06:50 PM PDT 24
Peak memory 211404 kb
Host smart-5f10049d-6476-4c5e-a2d3-bfc37835b0b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98543769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.98543769
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1138373776
Short name T117
Test name
Test status
Simulation time 12166550456 ps
CPU time 28.45 seconds
Started Jul 18 06:06:31 PM PDT 24
Finished Jul 18 06:07:03 PM PDT 24
Peak memory 215516 kb
Host smart-7b88e9c7-3c7a-408e-99a8-77253ed6c6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138373776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1138373776
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.998059846
Short name T244
Test name
Test status
Simulation time 11687545362 ps
CPU time 117.01 seconds
Started Jul 18 06:06:39 PM PDT 24
Finished Jul 18 06:08:40 PM PDT 24
Peak memory 219416 kb
Host smart-093ba38a-3a08-4660-a945-ad61b17c935c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998059846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.998059846
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1263846955
Short name T323
Test name
Test status
Simulation time 1159457539 ps
CPU time 11.73 seconds
Started Jul 18 06:06:43 PM PDT 24
Finished Jul 18 06:06:58 PM PDT 24
Peak memory 211392 kb
Host smart-08bc93fa-babd-4a8c-b80d-b454ca6e16fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263846955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1263846955
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.14470162
Short name T221
Test name
Test status
Simulation time 41571579334 ps
CPU time 182.4 seconds
Started Jul 18 06:06:43 PM PDT 24
Finished Jul 18 06:09:48 PM PDT 24
Peak memory 234952 kb
Host smart-48a80ba5-c043-4d8c-ab0a-e128bab3ae6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14470162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_co
rrupt_sig_fatal_chk.14470162
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.964917693
Short name T183
Test name
Test status
Simulation time 2829324313 ps
CPU time 25.37 seconds
Started Jul 18 06:06:45 PM PDT 24
Finished Jul 18 06:07:15 PM PDT 24
Peak memory 211904 kb
Host smart-ffa27727-76ce-4712-b0ab-5354cea4873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964917693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.964917693
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2305094948
Short name T283
Test name
Test status
Simulation time 5230167511 ps
CPU time 11.29 seconds
Started Jul 18 06:06:42 PM PDT 24
Finished Jul 18 06:06:56 PM PDT 24
Peak memory 211480 kb
Host smart-d67f22cc-eabd-46c2-a453-8d61b2c8dced
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305094948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2305094948
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1096604584
Short name T328
Test name
Test status
Simulation time 3291361196 ps
CPU time 29.26 seconds
Started Jul 18 06:06:35 PM PDT 24
Finished Jul 18 06:07:09 PM PDT 24
Peak memory 213608 kb
Host smart-92dd3724-0aae-472b-8f23-e774f1c34059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096604584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1096604584
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4053642068
Short name T315
Test name
Test status
Simulation time 6969784780 ps
CPU time 36.76 seconds
Started Jul 18 06:06:43 PM PDT 24
Finished Jul 18 06:07:23 PM PDT 24
Peak memory 215604 kb
Host smart-3274ef44-1fe2-4fa0-b992-603d7ad13b24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053642068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4053642068
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.87890882
Short name T59
Test name
Test status
Simulation time 22089413475 ps
CPU time 11.66 seconds
Started Jul 18 06:06:43 PM PDT 24
Finished Jul 18 06:06:58 PM PDT 24
Peak memory 211440 kb
Host smart-8a98e76d-f49e-435d-ab2f-9eecf74708eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87890882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.87890882
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1439567299
Short name T352
Test name
Test status
Simulation time 31276624008 ps
CPU time 272.84 seconds
Started Jul 18 06:06:43 PM PDT 24
Finished Jul 18 06:11:20 PM PDT 24
Peak memory 234976 kb
Host smart-a92055b1-a682-44aa-b4f5-0bfb9fec4bdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439567299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1439567299
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3091866214
Short name T234
Test name
Test status
Simulation time 12825838542 ps
CPU time 28.49 seconds
Started Jul 18 06:06:46 PM PDT 24
Finished Jul 18 06:07:20 PM PDT 24
Peak memory 212200 kb
Host smart-7742be22-aca8-4d00-b6cb-98f4079e901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091866214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3091866214
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3045188706
Short name T250
Test name
Test status
Simulation time 3324040210 ps
CPU time 14.68 seconds
Started Jul 18 06:06:44 PM PDT 24
Finished Jul 18 06:07:03 PM PDT 24
Peak memory 211484 kb
Host smart-1bab3e6d-1aad-4bac-94e9-630234dbe58f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045188706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3045188706
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.684911663
Short name T31
Test name
Test status
Simulation time 8914820824 ps
CPU time 26.81 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:07:20 PM PDT 24
Peak memory 214492 kb
Host smart-ba6a0d21-3582-4523-8085-656a7e81437f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684911663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.684911663
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3778689957
Short name T330
Test name
Test status
Simulation time 25698831893 ps
CPU time 57.52 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:07:51 PM PDT 24
Peak memory 217208 kb
Host smart-eb87fe3e-527a-48d6-89ee-90ce38fa7a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778689957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3778689957
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1907130054
Short name T212
Test name
Test status
Simulation time 3148706642 ps
CPU time 8.79 seconds
Started Jul 18 06:06:41 PM PDT 24
Finished Jul 18 06:06:52 PM PDT 24
Peak memory 211624 kb
Host smart-4ddaf3de-2e2b-4d2c-bf81-9f6f07df65ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907130054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1907130054
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1650838082
Short name T220
Test name
Test status
Simulation time 12752562785 ps
CPU time 154.11 seconds
Started Jul 18 06:06:46 PM PDT 24
Finished Jul 18 06:09:26 PM PDT 24
Peak memory 237872 kb
Host smart-e09218e1-7f67-4b58-9e5e-0103f73c9ccd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650838082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1650838082
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1135403606
Short name T255
Test name
Test status
Simulation time 1497500087 ps
CPU time 11.97 seconds
Started Jul 18 06:06:44 PM PDT 24
Finished Jul 18 06:06:59 PM PDT 24
Peak memory 212088 kb
Host smart-ae648c5f-e167-4f62-80f8-f43ec9474c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135403606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1135403606
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.520412189
Short name T187
Test name
Test status
Simulation time 1636063745 ps
CPU time 14.08 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:07:07 PM PDT 24
Peak memory 211432 kb
Host smart-9b62e984-0d2d-4648-90b4-68aadbf55552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520412189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.520412189
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.753501144
Short name T127
Test name
Test status
Simulation time 693597742 ps
CPU time 10.07 seconds
Started Jul 18 06:06:42 PM PDT 24
Finished Jul 18 06:06:55 PM PDT 24
Peak memory 213904 kb
Host smart-3b080998-c39e-49e6-8094-52babf4b9cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753501144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.753501144
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1721572990
Short name T125
Test name
Test status
Simulation time 20401162673 ps
CPU time 51.54 seconds
Started Jul 18 06:06:43 PM PDT 24
Finished Jul 18 06:07:38 PM PDT 24
Peak memory 217100 kb
Host smart-14f8f491-9b97-4d6c-b241-127a054fbcad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721572990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1721572990
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.993650056
Short name T257
Test name
Test status
Simulation time 70540990416 ps
CPU time 2604.92 seconds
Started Jul 18 06:06:44 PM PDT 24
Finished Jul 18 06:50:13 PM PDT 24
Peak memory 238768 kb
Host smart-836e544d-2825-4db8-ad2b-ce686d49491c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993650056 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.993650056
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1647442899
Short name T325
Test name
Test status
Simulation time 4287426482 ps
CPU time 10.74 seconds
Started Jul 18 06:06:46 PM PDT 24
Finished Jul 18 06:07:02 PM PDT 24
Peak memory 211424 kb
Host smart-9a9efb83-311b-471f-996b-bf7b2326b9ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647442899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1647442899
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2690183362
Short name T363
Test name
Test status
Simulation time 20375948260 ps
CPU time 211.85 seconds
Started Jul 18 06:06:43 PM PDT 24
Finished Jul 18 06:10:18 PM PDT 24
Peak memory 233832 kb
Host smart-55471652-7ab3-4aa2-b2f0-c3d8e11f544b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690183362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2690183362
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2205193923
Short name T41
Test name
Test status
Simulation time 5416823118 ps
CPU time 24.3 seconds
Started Jul 18 06:06:45 PM PDT 24
Finished Jul 18 06:07:14 PM PDT 24
Peak memory 212420 kb
Host smart-c6a7e03d-76f6-4a67-9af0-07508f97f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205193923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2205193923
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4141020839
Short name T371
Test name
Test status
Simulation time 3668063003 ps
CPU time 7.45 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:07:02 PM PDT 24
Peak memory 211516 kb
Host smart-380fc57d-9969-43dc-9616-5fe0f5e07b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4141020839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4141020839
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1474417383
Short name T205
Test name
Test status
Simulation time 438468093 ps
CPU time 10.09 seconds
Started Jul 18 06:06:43 PM PDT 24
Finished Jul 18 06:06:56 PM PDT 24
Peak memory 213336 kb
Host smart-acfda12d-11d4-48f6-a264-ee98824fe805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474417383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1474417383
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2377375950
Short name T227
Test name
Test status
Simulation time 390790041 ps
CPU time 22.21 seconds
Started Jul 18 06:06:40 PM PDT 24
Finished Jul 18 06:07:06 PM PDT 24
Peak memory 215384 kb
Host smart-1ed6aa6c-aa37-49d9-a9d4-fdf8c3d13163
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377375950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2377375950
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.670984718
Short name T337
Test name
Test status
Simulation time 5753572678 ps
CPU time 13.23 seconds
Started Jul 18 06:06:46 PM PDT 24
Finished Jul 18 06:07:05 PM PDT 24
Peak memory 211392 kb
Host smart-8b3a727a-9e40-4113-9842-8d9976a3c80b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670984718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.670984718
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3416861200
Short name T175
Test name
Test status
Simulation time 60281994700 ps
CPU time 173.84 seconds
Started Jul 18 06:06:42 PM PDT 24
Finished Jul 18 06:09:39 PM PDT 24
Peak memory 238212 kb
Host smart-2ddd924d-2cd6-402f-b734-b8339fe2ef26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416861200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3416861200
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.633210587
Short name T282
Test name
Test status
Simulation time 1878575237 ps
CPU time 15.57 seconds
Started Jul 18 06:06:42 PM PDT 24
Finished Jul 18 06:07:00 PM PDT 24
Peak memory 212036 kb
Host smart-b30f8a4a-fa50-4508-9a95-d90ced621c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633210587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.633210587
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.239443707
Short name T9
Test name
Test status
Simulation time 764374999 ps
CPU time 9.32 seconds
Started Jul 18 06:06:46 PM PDT 24
Finished Jul 18 06:07:01 PM PDT 24
Peak memory 211424 kb
Host smart-8b9252b7-0c11-47cc-a86a-1e5a3b39d7b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239443707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.239443707
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3346867081
Short name T120
Test name
Test status
Simulation time 8267445014 ps
CPU time 22.29 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:07:17 PM PDT 24
Peak memory 214376 kb
Host smart-ec24bd2f-c6b4-42c9-ab2b-a373e69e9b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346867081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3346867081
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2620668170
Short name T162
Test name
Test status
Simulation time 3999725712 ps
CPU time 18.13 seconds
Started Jul 18 06:06:42 PM PDT 24
Finished Jul 18 06:07:03 PM PDT 24
Peak memory 211932 kb
Host smart-6bffe8cc-0eb7-48d4-8849-ba36f07e177d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620668170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2620668170
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2429808540
Short name T327
Test name
Test status
Simulation time 29888560226 ps
CPU time 4452.67 seconds
Started Jul 18 06:06:46 PM PDT 24
Finished Jul 18 07:21:05 PM PDT 24
Peak memory 231116 kb
Host smart-bcc1b317-9aa9-452a-8248-2c000aaf6782
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429808540 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2429808540
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4124414057
Short name T24
Test name
Test status
Simulation time 127027445 ps
CPU time 5.11 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:06:59 PM PDT 24
Peak memory 211388 kb
Host smart-c0149736-6a90-4e45-bf1b-e1ffe34e7381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124414057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4124414057
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2960088422
Short name T40
Test name
Test status
Simulation time 82686250709 ps
CPU time 251.39 seconds
Started Jul 18 06:07:09 PM PDT 24
Finished Jul 18 06:11:25 PM PDT 24
Peak memory 225124 kb
Host smart-1e7c9db2-518d-489c-a4b1-68eee944ea77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960088422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2960088422
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.442798117
Short name T26
Test name
Test status
Simulation time 13651783349 ps
CPU time 24.06 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:07:18 PM PDT 24
Peak memory 212284 kb
Host smart-7e020cac-0042-4db4-b3e6-b8086d6e5de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442798117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.442798117
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2222989360
Short name T201
Test name
Test status
Simulation time 2455777219 ps
CPU time 9.53 seconds
Started Jul 18 06:06:40 PM PDT 24
Finished Jul 18 06:06:53 PM PDT 24
Peak memory 211464 kb
Host smart-f92207d5-0052-4b64-b739-95d0ed8c6d1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2222989360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2222989360
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3445548305
Short name T359
Test name
Test status
Simulation time 4257892097 ps
CPU time 34.02 seconds
Started Jul 18 06:06:44 PM PDT 24
Finished Jul 18 06:07:21 PM PDT 24
Peak memory 213536 kb
Host smart-54e6560e-50ea-4b67-b77f-9c5ad484e3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445548305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3445548305
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.269753481
Short name T351
Test name
Test status
Simulation time 604749960 ps
CPU time 7.41 seconds
Started Jul 18 06:06:45 PM PDT 24
Finished Jul 18 06:06:58 PM PDT 24
Peak memory 211452 kb
Host smart-374834b9-1ff6-4ecf-9669-d619302734ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269753481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.269753481
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3609972553
Short name T3
Test name
Test status
Simulation time 460818796 ps
CPU time 4.25 seconds
Started Jul 18 06:06:44 PM PDT 24
Finished Jul 18 06:06:53 PM PDT 24
Peak memory 211388 kb
Host smart-1ea3fb2a-84b4-4cf8-b29b-b6044effc126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609972553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3609972553
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3331118367
Short name T39
Test name
Test status
Simulation time 4596844722 ps
CPU time 123.6 seconds
Started Jul 18 06:06:46 PM PDT 24
Finished Jul 18 06:08:55 PM PDT 24
Peak memory 228676 kb
Host smart-6a094383-cb54-427c-baa1-bc8ef415f3e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331118367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3331118367
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1778624674
Short name T338
Test name
Test status
Simulation time 691801446 ps
CPU time 9.73 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:07:03 PM PDT 24
Peak memory 211908 kb
Host smart-9b2a8280-55a9-4719-8fbc-12f8b1c794a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778624674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1778624674
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3039116229
Short name T301
Test name
Test status
Simulation time 6047845323 ps
CPU time 13.65 seconds
Started Jul 18 06:06:42 PM PDT 24
Finished Jul 18 06:06:59 PM PDT 24
Peak memory 211672 kb
Host smart-c5fbc62d-0891-4af3-b5b7-de9e4d7bf5bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3039116229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3039116229
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.560829907
Short name T179
Test name
Test status
Simulation time 358941275 ps
CPU time 10.04 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:07:04 PM PDT 24
Peak memory 212912 kb
Host smart-2ac5da46-9ff4-45a9-8b50-131fc94761b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560829907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.560829907
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3995057123
Short name T239
Test name
Test status
Simulation time 1359241733 ps
CPU time 16.54 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:07:11 PM PDT 24
Peak memory 211444 kb
Host smart-16678c31-dfe4-4049-b7bd-6db41d1cfae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995057123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3995057123
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1011835206
Short name T182
Test name
Test status
Simulation time 1488493297 ps
CPU time 11.54 seconds
Started Jul 18 06:06:29 PM PDT 24
Finished Jul 18 06:06:42 PM PDT 24
Peak memory 211376 kb
Host smart-2daa214d-3ee1-40ea-a3fb-96cbc4abe2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011835206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1011835206
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1472751638
Short name T202
Test name
Test status
Simulation time 109315738451 ps
CPU time 251.06 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:10:50 PM PDT 24
Peak memory 212764 kb
Host smart-cff27df7-623f-45f6-baf5-38733aa6a0c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472751638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1472751638
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3868629539
Short name T286
Test name
Test status
Simulation time 223372967 ps
CPU time 9.74 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:06:45 PM PDT 24
Peak memory 211900 kb
Host smart-f8f11806-e6a3-4fd1-b5b3-49c4af0b9d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868629539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3868629539
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.302527659
Short name T137
Test name
Test status
Simulation time 1114843105 ps
CPU time 11.53 seconds
Started Jul 18 06:06:31 PM PDT 24
Finished Jul 18 06:06:45 PM PDT 24
Peak memory 211424 kb
Host smart-48f6b22c-aa8a-445e-b35d-0a80b486d7e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302527659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.302527659
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1595655856
Short name T21
Test name
Test status
Simulation time 3534072042 ps
CPU time 56.44 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:07:33 PM PDT 24
Peak memory 235784 kb
Host smart-fabafb82-25e6-4fc9-8bad-ef155440fbe6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595655856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1595655856
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2590926080
Short name T119
Test name
Test status
Simulation time 2229938983 ps
CPU time 22.98 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 06:07:00 PM PDT 24
Peak memory 215104 kb
Host smart-102cc801-991c-4446-b29b-539b7b22ce27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590926080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2590926080
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.678453590
Short name T303
Test name
Test status
Simulation time 12421680934 ps
CPU time 31.72 seconds
Started Jul 18 06:06:30 PM PDT 24
Finished Jul 18 06:07:03 PM PDT 24
Peak memory 214476 kb
Host smart-a99fed87-ba3a-408f-8d2b-52ae027e7b05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678453590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.678453590
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2429316893
Short name T278
Test name
Test status
Simulation time 1681298005 ps
CPU time 6.54 seconds
Started Jul 18 06:06:42 PM PDT 24
Finished Jul 18 06:06:52 PM PDT 24
Peak memory 211360 kb
Host smart-82dfb772-b745-4f96-9468-2135933d0088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429316893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2429316893
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2605002087
Short name T335
Test name
Test status
Simulation time 31195093098 ps
CPU time 298.87 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:11:53 PM PDT 24
Peak memory 237900 kb
Host smart-9257b4a8-e2bb-4829-a69a-53e103b8b04e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605002087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2605002087
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.120147670
Short name T238
Test name
Test status
Simulation time 3429472304 ps
CPU time 14.39 seconds
Started Jul 18 06:06:46 PM PDT 24
Finished Jul 18 06:07:06 PM PDT 24
Peak memory 211352 kb
Host smart-7279bf86-41ba-4f02-b9b6-e8e12b202599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=120147670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.120147670
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.737707925
Short name T316
Test name
Test status
Simulation time 618111457 ps
CPU time 10.23 seconds
Started Jul 18 06:06:43 PM PDT 24
Finished Jul 18 06:06:57 PM PDT 24
Peak memory 213392 kb
Host smart-44b91b38-fa2e-4da5-a7d4-164288e9132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737707925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.737707925
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4009537420
Short name T200
Test name
Test status
Simulation time 12172998355 ps
CPU time 31.6 seconds
Started Jul 18 06:06:54 PM PDT 24
Finished Jul 18 06:07:29 PM PDT 24
Peak memory 216036 kb
Host smart-3da5aeb1-c2ba-4d06-ba20-2a8bcc4c43eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009537420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4009537420
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.577809820
Short name T35
Test name
Test status
Simulation time 1350325812 ps
CPU time 8.35 seconds
Started Jul 18 06:06:49 PM PDT 24
Finished Jul 18 06:07:04 PM PDT 24
Peak memory 211384 kb
Host smart-514b906e-21d7-42c0-bc5c-47f212d4a658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577809820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.577809820
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2516179879
Short name T181
Test name
Test status
Simulation time 97757694786 ps
CPU time 232.2 seconds
Started Jul 18 06:06:45 PM PDT 24
Finished Jul 18 06:10:42 PM PDT 24
Peak memory 233984 kb
Host smart-b024e431-db3f-47d9-971d-c8f611dda8f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516179879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2516179879
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3085998908
Short name T224
Test name
Test status
Simulation time 2429908789 ps
CPU time 23.6 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:07:18 PM PDT 24
Peak memory 212088 kb
Host smart-627e1631-bc43-462a-a93b-6ac80cefb894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085998908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3085998908
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1930537829
Short name T260
Test name
Test status
Simulation time 1635971778 ps
CPU time 13.88 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:07:08 PM PDT 24
Peak memory 211428 kb
Host smart-ff5bcce3-797f-460d-bd9a-3d03d8c52113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930537829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1930537829
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3840798487
Short name T15
Test name
Test status
Simulation time 1803524015 ps
CPU time 10.3 seconds
Started Jul 18 06:06:45 PM PDT 24
Finished Jul 18 06:07:00 PM PDT 24
Peak memory 214100 kb
Host smart-1500f955-aacb-442e-92da-691c95f5d6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840798487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3840798487
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.354802806
Short name T285
Test name
Test status
Simulation time 39610899549 ps
CPU time 47.27 seconds
Started Jul 18 06:06:46 PM PDT 24
Finished Jul 18 06:07:39 PM PDT 24
Peak memory 219304 kb
Host smart-060f781e-2aa1-45c8-8b65-7d0f6dded38c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354802806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.354802806
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2433369291
Short name T262
Test name
Test status
Simulation time 2172071977 ps
CPU time 16.76 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:07:11 PM PDT 24
Peak memory 211424 kb
Host smart-d19a9893-906c-4211-97d6-d7599b7f3e8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433369291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2433369291
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1187723334
Short name T307
Test name
Test status
Simulation time 39546189229 ps
CPU time 215.97 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:10:29 PM PDT 24
Peak memory 237932 kb
Host smart-bda9adf3-f968-45db-bfe2-23d1c49e8ebc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187723334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1187723334
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1498206562
Short name T291
Test name
Test status
Simulation time 665938027 ps
CPU time 9.41 seconds
Started Jul 18 06:06:45 PM PDT 24
Finished Jul 18 06:06:59 PM PDT 24
Peak memory 211908 kb
Host smart-47d140ca-1531-451d-a062-b892b276dbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498206562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1498206562
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1779201389
Short name T204
Test name
Test status
Simulation time 377817048 ps
CPU time 4.97 seconds
Started Jul 18 06:06:45 PM PDT 24
Finished Jul 18 06:06:55 PM PDT 24
Peak memory 211320 kb
Host smart-96e3972f-eddd-4eec-98d8-61a520d0a549
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779201389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1779201389
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2575964152
Short name T297
Test name
Test status
Simulation time 2318637524 ps
CPU time 23 seconds
Started Jul 18 06:06:54 PM PDT 24
Finished Jul 18 06:07:20 PM PDT 24
Peak memory 213400 kb
Host smart-d53a2d59-5ea6-48f7-92e2-464c4eea0205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575964152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2575964152
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3082247855
Short name T123
Test name
Test status
Simulation time 15091317452 ps
CPU time 35.04 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:07:29 PM PDT 24
Peak memory 214084 kb
Host smart-d68c6948-b59a-4346-8dc8-a01b730f657f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082247855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3082247855
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4008681068
Short name T115
Test name
Test status
Simulation time 67712545669 ps
CPU time 1400.4 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:30:15 PM PDT 24
Peak memory 235868 kb
Host smart-8e97cb6e-7162-456c-abf4-488f416c05cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008681068 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.4008681068
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3922372852
Short name T124
Test name
Test status
Simulation time 2465787185 ps
CPU time 11.52 seconds
Started Jul 18 06:06:49 PM PDT 24
Finished Jul 18 06:07:06 PM PDT 24
Peak memory 211552 kb
Host smart-85cc47db-5313-4413-ab22-1fd1bf164c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922372852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3922372852
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3548738892
Short name T114
Test name
Test status
Simulation time 54388007941 ps
CPU time 257.51 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:11:12 PM PDT 24
Peak memory 237808 kb
Host smart-7df7bab3-1cdb-4dd6-afb8-7aa92b4164ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548738892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3548738892
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1004027991
Short name T27
Test name
Test status
Simulation time 173554860 ps
CPU time 9.41 seconds
Started Jul 18 06:06:48 PM PDT 24
Finished Jul 18 06:07:04 PM PDT 24
Peak memory 212164 kb
Host smart-976e86b9-b884-4a56-915c-fa9b0995ca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004027991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1004027991
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3867664834
Short name T99
Test name
Test status
Simulation time 2089835015 ps
CPU time 17.36 seconds
Started Jul 18 06:06:50 PM PDT 24
Finished Jul 18 06:07:13 PM PDT 24
Peak memory 211540 kb
Host smart-0ce84142-f2c4-4238-b7c9-8f81f12fa467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867664834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3867664834
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1332208499
Short name T160
Test name
Test status
Simulation time 7902239287 ps
CPU time 31.2 seconds
Started Jul 18 06:06:45 PM PDT 24
Finished Jul 18 06:07:21 PM PDT 24
Peak memory 213460 kb
Host smart-00785636-d47e-490c-9335-d4dbdf74ac5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332208499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1332208499
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2723778800
Short name T368
Test name
Test status
Simulation time 605665042 ps
CPU time 15.7 seconds
Started Jul 18 06:06:45 PM PDT 24
Finished Jul 18 06:07:05 PM PDT 24
Peak memory 215072 kb
Host smart-a6558a69-e9ba-4985-98ba-79df6e9fdb3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723778800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2723778800
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3949759786
Short name T248
Test name
Test status
Simulation time 6640344446 ps
CPU time 13.39 seconds
Started Jul 18 06:06:50 PM PDT 24
Finished Jul 18 06:07:09 PM PDT 24
Peak memory 211432 kb
Host smart-1948ed96-9907-4e80-b42b-07efebe998c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949759786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3949759786
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2629349821
Short name T174
Test name
Test status
Simulation time 23799036602 ps
CPU time 172.18 seconds
Started Jul 18 06:06:50 PM PDT 24
Finished Jul 18 06:09:48 PM PDT 24
Peak memory 228560 kb
Host smart-826268fb-5598-46c9-9eb2-0300049a95ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629349821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2629349821
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1887820544
Short name T312
Test name
Test status
Simulation time 3682871677 ps
CPU time 29.93 seconds
Started Jul 18 06:06:49 PM PDT 24
Finished Jul 18 06:07:25 PM PDT 24
Peak memory 211972 kb
Host smart-a97c70b6-eb7c-491b-bb7b-d070b3909037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887820544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1887820544
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1804744765
Short name T237
Test name
Test status
Simulation time 1439187560 ps
CPU time 12.86 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:07:06 PM PDT 24
Peak memory 211456 kb
Host smart-fbd48fa0-9534-48ea-8c9f-2699d3ce9cff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1804744765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1804744765
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.351120769
Short name T10
Test name
Test status
Simulation time 8505125557 ps
CPU time 28.58 seconds
Started Jul 18 06:06:50 PM PDT 24
Finished Jul 18 06:07:24 PM PDT 24
Peak memory 214328 kb
Host smart-c966a440-5980-4ade-b8d0-8ca41c61c6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351120769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.351120769
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1748944458
Short name T141
Test name
Test status
Simulation time 9253629396 ps
CPU time 15.19 seconds
Started Jul 18 06:06:49 PM PDT 24
Finished Jul 18 06:07:10 PM PDT 24
Peak memory 212524 kb
Host smart-f8af5674-0133-4584-8892-5126cd27ed86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748944458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1748944458
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4186113585
Short name T361
Test name
Test status
Simulation time 323389550059 ps
CPU time 3142.88 seconds
Started Jul 18 06:06:51 PM PDT 24
Finished Jul 18 06:59:19 PM PDT 24
Peak memory 242620 kb
Host smart-370c99e5-2d30-4a28-8e76-1a628f5f2ea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186113585 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.4186113585
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.350621711
Short name T144
Test name
Test status
Simulation time 1058796326 ps
CPU time 10.57 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:07:20 PM PDT 24
Peak memory 211328 kb
Host smart-00f92182-c794-4370-8b98-7790e949b1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350621711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.350621711
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3236113786
Short name T5
Test name
Test status
Simulation time 36506239617 ps
CPU time 352.12 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:12:45 PM PDT 24
Peak memory 228652 kb
Host smart-f0236db9-b1aa-41c2-831f-37eb5cebdc3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236113786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3236113786
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4229619514
Short name T366
Test name
Test status
Simulation time 693332472 ps
CPU time 9.4 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:07:03 PM PDT 24
Peak memory 212044 kb
Host smart-ef154fd7-66b2-4a55-97d8-91bae5852987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229619514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4229619514
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3182343200
Short name T165
Test name
Test status
Simulation time 4128056900 ps
CPU time 10.43 seconds
Started Jul 18 06:06:50 PM PDT 24
Finished Jul 18 06:07:06 PM PDT 24
Peak memory 211364 kb
Host smart-ddf44944-4723-4181-a895-875ab495f751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182343200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3182343200
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1337665617
Short name T270
Test name
Test status
Simulation time 17080251847 ps
CPU time 35.68 seconds
Started Jul 18 06:06:46 PM PDT 24
Finished Jul 18 06:07:27 PM PDT 24
Peak memory 214208 kb
Host smart-104cf852-07c0-400d-a967-422c57840089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337665617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1337665617
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.481079359
Short name T240
Test name
Test status
Simulation time 18142763533 ps
CPU time 99.57 seconds
Started Jul 18 06:06:47 PM PDT 24
Finished Jul 18 06:08:33 PM PDT 24
Peak memory 217972 kb
Host smart-9f1f714f-a670-44f0-9c00-a079a24dc19c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481079359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.481079359
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3308186004
Short name T25
Test name
Test status
Simulation time 90702125 ps
CPU time 4.31 seconds
Started Jul 18 06:06:57 PM PDT 24
Finished Jul 18 06:07:04 PM PDT 24
Peak memory 211352 kb
Host smart-d7b7d5d0-0ab9-4595-be49-62ba6844d954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308186004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3308186004
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.403850829
Short name T259
Test name
Test status
Simulation time 42062848338 ps
CPU time 227.62 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:10:51 PM PDT 24
Peak memory 237888 kb
Host smart-4ed63e80-600a-4719-9c40-b78ad243e8c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403850829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.403850829
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3355243719
Short name T44
Test name
Test status
Simulation time 9958929462 ps
CPU time 22.59 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:07:25 PM PDT 24
Peak memory 211456 kb
Host smart-78b781fc-1ae5-4f35-b34a-bff18a447c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355243719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3355243719
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1849446932
Short name T93
Test name
Test status
Simulation time 1405779974 ps
CPU time 12.94 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:07:16 PM PDT 24
Peak memory 211416 kb
Host smart-31850f78-1de4-4f77-8373-11277c2d2c19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849446932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1849446932
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2339372924
Short name T168
Test name
Test status
Simulation time 194519994 ps
CPU time 10.46 seconds
Started Jul 18 06:06:57 PM PDT 24
Finished Jul 18 06:07:11 PM PDT 24
Peak memory 213480 kb
Host smart-9779f373-57fc-4dbc-85eb-46de04cefb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339372924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2339372924
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2683546224
Short name T94
Test name
Test status
Simulation time 3433270449 ps
CPU time 12.85 seconds
Started Jul 18 06:07:00 PM PDT 24
Finished Jul 18 06:07:17 PM PDT 24
Peak memory 212260 kb
Host smart-ebf5f7de-b6ac-4faf-92a3-dccbbc5252e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683546224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2683546224
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.822361004
Short name T135
Test name
Test status
Simulation time 2934779884 ps
CPU time 13.83 seconds
Started Jul 18 06:07:07 PM PDT 24
Finished Jul 18 06:07:26 PM PDT 24
Peak memory 211424 kb
Host smart-01bb4a49-d805-46a9-96b0-707f4ae948ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822361004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.822361004
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3452218442
Short name T153
Test name
Test status
Simulation time 8563757751 ps
CPU time 132.57 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:09:15 PM PDT 24
Peak memory 233788 kb
Host smart-0847303f-a68a-481e-806c-36fd51de0ef1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452218442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3452218442
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.562474193
Short name T163
Test name
Test status
Simulation time 2207815742 ps
CPU time 21.64 seconds
Started Jul 18 06:07:03 PM PDT 24
Finished Jul 18 06:07:30 PM PDT 24
Peak memory 212244 kb
Host smart-35ae6ead-338a-435d-8982-5b2d43df607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562474193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.562474193
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1284356848
Short name T173
Test name
Test status
Simulation time 188220063 ps
CPU time 5.93 seconds
Started Jul 18 06:06:57 PM PDT 24
Finished Jul 18 06:07:07 PM PDT 24
Peak memory 211420 kb
Host smart-b8b2cacb-9775-4ad6-bafe-59d2d47dcc94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1284356848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1284356848
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1808300467
Short name T216
Test name
Test status
Simulation time 366673275 ps
CPU time 10.22 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:07:13 PM PDT 24
Peak memory 213616 kb
Host smart-f1678fe7-aee9-4641-afcc-349cfe95283b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808300467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1808300467
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.343803397
Short name T211
Test name
Test status
Simulation time 26844711988 ps
CPU time 66.56 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:08:11 PM PDT 24
Peak memory 217208 kb
Host smart-2207f76d-b0b1-4e84-8041-7d4b06af389f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343803397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.343803397
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.523454515
Short name T1
Test name
Test status
Simulation time 3455842247 ps
CPU time 14.06 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:07:15 PM PDT 24
Peak memory 211404 kb
Host smart-977f7d33-2f13-49b5-86a3-488acf7d1b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523454515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.523454515
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.128032292
Short name T265
Test name
Test status
Simulation time 24862027975 ps
CPU time 297.67 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:12:00 PM PDT 24
Peak memory 228660 kb
Host smart-5d17f087-94c1-4057-918f-037527cfa3ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128032292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.128032292
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2731601348
Short name T365
Test name
Test status
Simulation time 2683338162 ps
CPU time 18.05 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:07:21 PM PDT 24
Peak memory 212156 kb
Host smart-8b2a3591-e36b-41d8-b2df-b276a458cce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731601348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2731601348
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2355840443
Short name T103
Test name
Test status
Simulation time 1360203627 ps
CPU time 13.19 seconds
Started Jul 18 06:06:56 PM PDT 24
Finished Jul 18 06:07:12 PM PDT 24
Peak memory 211396 kb
Host smart-f9cb8ce4-959b-4ebe-827c-0a398d24a913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355840443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2355840443
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.260126692
Short name T146
Test name
Test status
Simulation time 3610081453 ps
CPU time 35.25 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:07:37 PM PDT 24
Peak memory 212240 kb
Host smart-f300eb48-9d3b-42f7-bb58-fa1550f2ab00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260126692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.260126692
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.472623039
Short name T207
Test name
Test status
Simulation time 20775312550 ps
CPU time 45.55 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 214276 kb
Host smart-2355e713-b247-4b90-8051-69a9c65ce761
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472623039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.472623039
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3865466437
Short name T164
Test name
Test status
Simulation time 984486521 ps
CPU time 10.09 seconds
Started Jul 18 06:07:02 PM PDT 24
Finished Jul 18 06:07:18 PM PDT 24
Peak memory 211492 kb
Host smart-cd75f877-d7cf-4d37-8198-35938dec76a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865466437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3865466437
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2611266838
Short name T208
Test name
Test status
Simulation time 2372591885 ps
CPU time 24.13 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:07:28 PM PDT 24
Peak memory 212008 kb
Host smart-c628e5a0-dac4-4fd3-8f35-2c3d232e4451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611266838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2611266838
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1161739241
Short name T116
Test name
Test status
Simulation time 386174200 ps
CPU time 5.54 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:07:15 PM PDT 24
Peak memory 211404 kb
Host smart-eb26ea71-f3e3-4029-8da1-152108fd2cab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1161739241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1161739241
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.410026602
Short name T356
Test name
Test status
Simulation time 2658047612 ps
CPU time 24.43 seconds
Started Jul 18 06:06:57 PM PDT 24
Finished Jul 18 06:07:24 PM PDT 24
Peak memory 212116 kb
Host smart-402a957c-dee6-4644-aec3-e033a63c5229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410026602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.410026602
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2257715013
Short name T228
Test name
Test status
Simulation time 2543391359 ps
CPU time 17.79 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:07:22 PM PDT 24
Peak memory 211376 kb
Host smart-a1711256-5cb2-4dc9-8b55-85fc9339e7c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257715013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2257715013
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.402676947
Short name T158
Test name
Test status
Simulation time 254221717 ps
CPU time 6.15 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:45 PM PDT 24
Peak memory 211368 kb
Host smart-49c301af-3470-4daa-ad1f-acd3fe89addc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402676947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.402676947
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2087747939
Short name T218
Test name
Test status
Simulation time 52351006169 ps
CPU time 248.84 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:10:48 PM PDT 24
Peak memory 228680 kb
Host smart-0b8d92e6-d662-4f83-87cc-4d39705837db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087747939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2087747939
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3359309352
Short name T341
Test name
Test status
Simulation time 83761459337 ps
CPU time 34.19 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:07:10 PM PDT 24
Peak memory 212536 kb
Host smart-9d889b69-6e6f-4ff7-85d1-454125c05846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359309352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3359309352
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.648195513
Short name T367
Test name
Test status
Simulation time 1532409044 ps
CPU time 5.87 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:46 PM PDT 24
Peak memory 211480 kb
Host smart-898b7649-424a-4e66-a9ee-27d5bc675bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=648195513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.648195513
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3633490159
Short name T29
Test name
Test status
Simulation time 7217732369 ps
CPU time 61.65 seconds
Started Jul 18 06:06:35 PM PDT 24
Finished Jul 18 06:07:42 PM PDT 24
Peak memory 234048 kb
Host smart-3b390527-dee3-4e4c-97b1-8e18aeb36397
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633490159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3633490159
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1665067069
Short name T331
Test name
Test status
Simulation time 610806971 ps
CPU time 9.79 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 06:06:48 PM PDT 24
Peak memory 213292 kb
Host smart-adfecb0e-61a1-49c0-80da-fc756e53dd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665067069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1665067069
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1681009935
Short name T280
Test name
Test status
Simulation time 196507268669 ps
CPU time 3736.15 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 07:08:54 PM PDT 24
Peak memory 245004 kb
Host smart-59c81919-2835-46c1-917c-5ba778263e2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681009935 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1681009935
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2893356142
Short name T150
Test name
Test status
Simulation time 7359135626 ps
CPU time 15.06 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:07:19 PM PDT 24
Peak memory 211452 kb
Host smart-2f2d1291-10ff-4a1d-b964-656bf4295930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893356142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2893356142
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2316494681
Short name T281
Test name
Test status
Simulation time 30321971560 ps
CPU time 352.09 seconds
Started Jul 18 06:07:02 PM PDT 24
Finished Jul 18 06:13:00 PM PDT 24
Peak memory 237956 kb
Host smart-35ec3a42-fb05-4109-8e4d-56f26c70954c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316494681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2316494681
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.142383971
Short name T206
Test name
Test status
Simulation time 4515074318 ps
CPU time 23.56 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:07:26 PM PDT 24
Peak memory 211480 kb
Host smart-959bcc3d-2725-421c-87bb-e973a30ce0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142383971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.142383971
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3435083606
Short name T294
Test name
Test status
Simulation time 650542695 ps
CPU time 8.98 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:07:19 PM PDT 24
Peak memory 211408 kb
Host smart-0f51efb4-31e3-44d4-9073-f2b4cda53fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435083606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3435083606
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2076746892
Short name T289
Test name
Test status
Simulation time 3846832069 ps
CPU time 30.77 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:07:33 PM PDT 24
Peak memory 213716 kb
Host smart-5c59bc84-7db8-42fb-8a5e-7c4a0aa6e291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076746892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2076746892
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2228066478
Short name T342
Test name
Test status
Simulation time 21183137578 ps
CPU time 47.77 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:07:51 PM PDT 24
Peak memory 217240 kb
Host smart-306d2659-ff65-4a0f-846d-d3ef05faacb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228066478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2228066478
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4181531794
Short name T251
Test name
Test status
Simulation time 7633196597 ps
CPU time 14.49 seconds
Started Jul 18 06:07:01 PM PDT 24
Finished Jul 18 06:07:21 PM PDT 24
Peak memory 211448 kb
Host smart-663e0d08-d15d-4eaa-a465-e7b909ef9098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181531794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4181531794
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3967825428
Short name T287
Test name
Test status
Simulation time 8396173680 ps
CPU time 115.91 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:09:05 PM PDT 24
Peak memory 225504 kb
Host smart-252d9962-91bf-480b-9032-099c017d3e7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967825428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3967825428
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1815918209
Short name T246
Test name
Test status
Simulation time 173260820 ps
CPU time 9.68 seconds
Started Jul 18 06:07:06 PM PDT 24
Finished Jul 18 06:07:21 PM PDT 24
Peak memory 211832 kb
Host smart-9009d342-dc3f-4513-977c-0d6ace8de5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815918209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1815918209
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4291922467
Short name T177
Test name
Test status
Simulation time 374682252 ps
CPU time 5.65 seconds
Started Jul 18 06:06:57 PM PDT 24
Finished Jul 18 06:07:07 PM PDT 24
Peak memory 211420 kb
Host smart-78a8a201-2f6f-407d-90e3-5824a7ebeeca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291922467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4291922467
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3445705254
Short name T121
Test name
Test status
Simulation time 3436519228 ps
CPU time 15.07 seconds
Started Jul 18 06:07:02 PM PDT 24
Finished Jul 18 06:07:23 PM PDT 24
Peak memory 212928 kb
Host smart-c6b0ebf0-80e8-49d2-8fad-ba56351ec04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445705254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3445705254
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1780900437
Short name T346
Test name
Test status
Simulation time 16480865010 ps
CPU time 65.3 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:08:09 PM PDT 24
Peak memory 215692 kb
Host smart-4a0d8f94-7f31-4f39-a519-fbad9cee58f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780900437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1780900437
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2711249259
Short name T184
Test name
Test status
Simulation time 35918111727 ps
CPU time 5948.74 seconds
Started Jul 18 06:07:07 PM PDT 24
Finished Jul 18 07:46:21 PM PDT 24
Peak memory 235880 kb
Host smart-a7c153f6-b00c-425c-bcb6-0e824e13ed0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711249259 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2711249259
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.668163627
Short name T7
Test name
Test status
Simulation time 2022831026 ps
CPU time 15.76 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:07:25 PM PDT 24
Peak memory 211360 kb
Host smart-12d27323-b9e8-44e2-9c20-810207ab9d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668163627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.668163627
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.786361437
Short name T219
Test name
Test status
Simulation time 11855576869 ps
CPU time 144.27 seconds
Started Jul 18 06:06:58 PM PDT 24
Finished Jul 18 06:09:26 PM PDT 24
Peak memory 237864 kb
Host smart-d1fc6216-592c-47b7-a861-21c717cec550
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786361437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.786361437
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2447622243
Short name T170
Test name
Test status
Simulation time 577378443 ps
CPU time 13.29 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:07:23 PM PDT 24
Peak memory 212004 kb
Host smart-649abaf0-f64d-4ed6-b71e-2b2eaed80951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447622243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2447622243
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2483538604
Short name T236
Test name
Test status
Simulation time 3988430034 ps
CPU time 16.11 seconds
Started Jul 18 06:07:02 PM PDT 24
Finished Jul 18 06:07:24 PM PDT 24
Peak memory 211600 kb
Host smart-c3956c92-e48a-458f-b3cb-3751bc03517e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483538604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2483538604
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.480552674
Short name T305
Test name
Test status
Simulation time 809204054 ps
CPU time 10.08 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:07:13 PM PDT 24
Peak memory 213556 kb
Host smart-8377be17-156f-4c7d-8b3c-9d6c15d3adfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480552674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.480552674
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.976709794
Short name T53
Test name
Test status
Simulation time 143976580503 ps
CPU time 115.56 seconds
Started Jul 18 06:07:07 PM PDT 24
Finished Jul 18 06:09:07 PM PDT 24
Peak memory 216788 kb
Host smart-44d12275-09c7-4252-8cda-68b0b45852bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976709794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.976709794
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3536806010
Short name T268
Test name
Test status
Simulation time 84732926315 ps
CPU time 1626.82 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:34:11 PM PDT 24
Peak memory 235772 kb
Host smart-e62045e4-b886-4900-a231-6aee105730cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536806010 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3536806010
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.392339594
Short name T128
Test name
Test status
Simulation time 85619912 ps
CPU time 4.14 seconds
Started Jul 18 06:07:07 PM PDT 24
Finished Jul 18 06:07:16 PM PDT 24
Peak memory 211276 kb
Host smart-4e30b622-5d1e-4b51-9897-1c4267599675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392339594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.392339594
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4109798723
Short name T333
Test name
Test status
Simulation time 18934668100 ps
CPU time 191.88 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:10:22 PM PDT 24
Peak memory 228668 kb
Host smart-c4336baf-c054-4df1-88d8-14824d5c142a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109798723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4109798723
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1925680492
Short name T96
Test name
Test status
Simulation time 2132108988 ps
CPU time 22.27 seconds
Started Jul 18 06:07:01 PM PDT 24
Finished Jul 18 06:07:28 PM PDT 24
Peak memory 212364 kb
Host smart-a3825f1d-24e2-4857-b89e-be7f6c0afd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925680492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1925680492
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1577900794
Short name T348
Test name
Test status
Simulation time 366051905 ps
CPU time 5.4 seconds
Started Jul 18 06:07:00 PM PDT 24
Finished Jul 18 06:07:11 PM PDT 24
Peak memory 211424 kb
Host smart-96546095-cf45-4b38-9c2d-73928841fad8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577900794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1577900794
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.23865249
Short name T16
Test name
Test status
Simulation time 3394291600 ps
CPU time 15.72 seconds
Started Jul 18 06:06:57 PM PDT 24
Finished Jul 18 06:07:17 PM PDT 24
Peak memory 213200 kb
Host smart-9b3612d9-18f0-4734-8939-801f038fa4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23865249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.23865249
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1155646846
Short name T8
Test name
Test status
Simulation time 225134431 ps
CPU time 7.38 seconds
Started Jul 18 06:07:02 PM PDT 24
Finished Jul 18 06:07:14 PM PDT 24
Peak memory 211440 kb
Host smart-a13f2bf2-556a-4464-ad52-b0ce52604958
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155646846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1155646846
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2043320884
Short name T245
Test name
Test status
Simulation time 288886371 ps
CPU time 6.23 seconds
Started Jul 18 06:07:07 PM PDT 24
Finished Jul 18 06:07:19 PM PDT 24
Peak memory 211376 kb
Host smart-ec25fd85-b3db-408f-9b82-e057cec6fe02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043320884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2043320884
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4058096974
Short name T19
Test name
Test status
Simulation time 26069964704 ps
CPU time 279.06 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:11:43 PM PDT 24
Peak memory 237920 kb
Host smart-def5f3af-05d3-4696-99b8-dcb91a3ebe1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058096974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4058096974
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3623702628
Short name T223
Test name
Test status
Simulation time 299292268 ps
CPU time 9.44 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:07:19 PM PDT 24
Peak memory 211976 kb
Host smart-b5d9f632-fab1-4ced-a4f1-1a54f033a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623702628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3623702628
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2362650136
Short name T266
Test name
Test status
Simulation time 97322520 ps
CPU time 5.77 seconds
Started Jul 18 06:07:01 PM PDT 24
Finished Jul 18 06:07:12 PM PDT 24
Peak memory 211412 kb
Host smart-89b8a24a-3886-42d9-8a14-cbab209dd193
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362650136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2362650136
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3841161108
Short name T353
Test name
Test status
Simulation time 961919983 ps
CPU time 15.78 seconds
Started Jul 18 06:07:02 PM PDT 24
Finished Jul 18 06:07:23 PM PDT 24
Peak memory 213548 kb
Host smart-f192add7-d37f-4115-9ccd-01ef34c9e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841161108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3841161108
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.490421290
Short name T344
Test name
Test status
Simulation time 2640345118 ps
CPU time 30.79 seconds
Started Jul 18 06:07:08 PM PDT 24
Finished Jul 18 06:07:43 PM PDT 24
Peak memory 214244 kb
Host smart-f8bf5a79-b6a0-4984-817f-95b60c2261e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490421290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.490421290
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3085199170
Short name T132
Test name
Test status
Simulation time 1195615411 ps
CPU time 11.51 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:07:22 PM PDT 24
Peak memory 211392 kb
Host smart-76484adc-6a86-45d8-a874-97f65241c848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085199170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3085199170
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3028783855
Short name T362
Test name
Test status
Simulation time 2115123405 ps
CPU time 121.54 seconds
Started Jul 18 06:07:03 PM PDT 24
Finished Jul 18 06:09:10 PM PDT 24
Peak memory 233752 kb
Host smart-12bda124-7d8b-4225-a5de-576f59598820
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028783855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3028783855
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3527701070
Short name T192
Test name
Test status
Simulation time 3750913131 ps
CPU time 32.18 seconds
Started Jul 18 06:07:03 PM PDT 24
Finished Jul 18 06:07:40 PM PDT 24
Peak memory 212012 kb
Host smart-24903652-d868-47fb-b54b-b052a9cf1c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527701070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3527701070
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1836328069
Short name T329
Test name
Test status
Simulation time 8954483959 ps
CPU time 17.71 seconds
Started Jul 18 06:07:07 PM PDT 24
Finished Jul 18 06:07:30 PM PDT 24
Peak memory 211468 kb
Host smart-de0c3bfd-3990-4533-bc61-635fccb3a1db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1836328069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1836328069
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.560162641
Short name T34
Test name
Test status
Simulation time 11902196783 ps
CPU time 29.89 seconds
Started Jul 18 06:07:10 PM PDT 24
Finished Jul 18 06:07:44 PM PDT 24
Peak memory 214600 kb
Host smart-e6bed881-d8be-4758-9b17-951b82ea004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560162641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.560162641
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1023315149
Short name T169
Test name
Test status
Simulation time 7323903213 ps
CPU time 52.63 seconds
Started Jul 18 06:07:01 PM PDT 24
Finished Jul 18 06:07:59 PM PDT 24
Peak memory 216368 kb
Host smart-d5c817e8-516c-4c9a-abde-978a450c439c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023315149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1023315149
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3048634020
Short name T48
Test name
Test status
Simulation time 218448443638 ps
CPU time 2107.77 seconds
Started Jul 18 06:07:03 PM PDT 24
Finished Jul 18 06:42:16 PM PDT 24
Peak memory 230656 kb
Host smart-8339a5f4-95ec-49c5-b0f7-c3e97f6a9464
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048634020 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3048634020
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.889829321
Short name T190
Test name
Test status
Simulation time 34147894314 ps
CPU time 16.2 seconds
Started Jul 18 06:07:04 PM PDT 24
Finished Jul 18 06:07:26 PM PDT 24
Peak memory 211356 kb
Host smart-2f67526d-7873-472c-ab69-a3d1be0bf0a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889829321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.889829321
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4201358390
Short name T354
Test name
Test status
Simulation time 6591971594 ps
CPU time 115.16 seconds
Started Jul 18 06:07:10 PM PDT 24
Finished Jul 18 06:09:09 PM PDT 24
Peak memory 212632 kb
Host smart-1da40541-2557-49f3-ac54-33af960dd9e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201358390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4201358390
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.701472992
Short name T308
Test name
Test status
Simulation time 334259623 ps
CPU time 9.56 seconds
Started Jul 18 06:07:03 PM PDT 24
Finished Jul 18 06:07:17 PM PDT 24
Peak memory 212244 kb
Host smart-a617c402-8f94-4cc6-94d8-6959b8fda002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701472992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.701472992
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2282849438
Short name T306
Test name
Test status
Simulation time 9830825718 ps
CPU time 13.1 seconds
Started Jul 18 06:07:09 PM PDT 24
Finished Jul 18 06:07:26 PM PDT 24
Peak memory 211480 kb
Host smart-5b09d8ca-db1a-4bed-b034-c1d93701aab8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282849438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2282849438
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.911132519
Short name T310
Test name
Test status
Simulation time 718474172 ps
CPU time 9.98 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:07:20 PM PDT 24
Peak memory 213912 kb
Host smart-bfed58f5-60b3-4c83-8ce5-f3293b6a334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911132519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.911132519
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3648219488
Short name T198
Test name
Test status
Simulation time 4775468569 ps
CPU time 30.32 seconds
Started Jul 18 06:07:09 PM PDT 24
Finished Jul 18 06:07:43 PM PDT 24
Peak memory 214132 kb
Host smart-b6813465-cdc8-4061-b005-99821146b8f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648219488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3648219488
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1753439453
Short name T350
Test name
Test status
Simulation time 49656138923 ps
CPU time 2667.55 seconds
Started Jul 18 06:07:09 PM PDT 24
Finished Jul 18 06:51:41 PM PDT 24
Peak memory 233916 kb
Host smart-9d955066-e16e-495a-8b3d-5fce101f17ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753439453 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1753439453
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3785194604
Short name T276
Test name
Test status
Simulation time 1491979092 ps
CPU time 13.59 seconds
Started Jul 18 06:07:09 PM PDT 24
Finished Jul 18 06:07:27 PM PDT 24
Peak memory 211380 kb
Host smart-3d0ed0a1-1e9c-41a4-9079-7136daa9386f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785194604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3785194604
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1089995984
Short name T321
Test name
Test status
Simulation time 229334952412 ps
CPU time 160.63 seconds
Started Jul 18 06:07:10 PM PDT 24
Finished Jul 18 06:09:54 PM PDT 24
Peak memory 233412 kb
Host smart-11597ab5-32a5-4a0f-b492-65581e1bbf8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089995984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1089995984
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3612852399
Short name T277
Test name
Test status
Simulation time 14502195642 ps
CPU time 27.53 seconds
Started Jul 18 06:07:10 PM PDT 24
Finished Jul 18 06:07:41 PM PDT 24
Peak memory 213028 kb
Host smart-da34ba5a-5893-436d-b37b-b9fb7dae5f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612852399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3612852399
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2005549379
Short name T95
Test name
Test status
Simulation time 438861229 ps
CPU time 7.85 seconds
Started Jul 18 06:07:10 PM PDT 24
Finished Jul 18 06:07:21 PM PDT 24
Peak memory 211420 kb
Host smart-4547ba20-bd7e-4c73-a840-4218845c632b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005549379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2005549379
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.405255064
Short name T130
Test name
Test status
Simulation time 1527302911 ps
CPU time 15.44 seconds
Started Jul 18 06:07:03 PM PDT 24
Finished Jul 18 06:07:24 PM PDT 24
Peak memory 211280 kb
Host smart-baf4a4b8-1c79-497a-b2d6-82400744adad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405255064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.405255064
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2789016889
Short name T143
Test name
Test status
Simulation time 1331571492 ps
CPU time 8.49 seconds
Started Jul 18 06:07:09 PM PDT 24
Finished Jul 18 06:07:22 PM PDT 24
Peak memory 211380 kb
Host smart-067d9742-599e-4179-b63e-a1b43bc1b8c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789016889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2789016889
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4285186652
Short name T299
Test name
Test status
Simulation time 31156173709 ps
CPU time 349.74 seconds
Started Jul 18 06:07:08 PM PDT 24
Finished Jul 18 06:13:03 PM PDT 24
Peak memory 212692 kb
Host smart-8289a6bb-dcf3-4b65-b583-77452aa8ff4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285186652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4285186652
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3567339500
Short name T194
Test name
Test status
Simulation time 11817206131 ps
CPU time 26.88 seconds
Started Jul 18 06:07:08 PM PDT 24
Finished Jul 18 06:07:40 PM PDT 24
Peak memory 212432 kb
Host smart-5b1e0740-c890-476f-a15e-150d88040721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567339500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3567339500
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.960389555
Short name T229
Test name
Test status
Simulation time 3187284375 ps
CPU time 14.57 seconds
Started Jul 18 06:07:09 PM PDT 24
Finished Jul 18 06:07:28 PM PDT 24
Peak memory 211464 kb
Host smart-9667597f-ee1c-496b-8b78-54f0a00a603b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960389555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.960389555
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.79294031
Short name T355
Test name
Test status
Simulation time 772411720 ps
CPU time 10.33 seconds
Started Jul 18 06:07:05 PM PDT 24
Finished Jul 18 06:07:20 PM PDT 24
Peak memory 213552 kb
Host smart-7074f50b-821c-469b-b1fd-b7775a7c0f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79294031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.79294031
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1360339407
Short name T159
Test name
Test status
Simulation time 5511005463 ps
CPU time 50.43 seconds
Started Jul 18 06:07:09 PM PDT 24
Finished Jul 18 06:08:04 PM PDT 24
Peak memory 216748 kb
Host smart-bc4e2899-5989-4470-9883-1835804bf425
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360339407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1360339407
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2658419674
Short name T49
Test name
Test status
Simulation time 10053849027 ps
CPU time 1212.54 seconds
Started Jul 18 06:07:03 PM PDT 24
Finished Jul 18 06:27:21 PM PDT 24
Peak memory 227688 kb
Host smart-88a6adf4-1734-47b9-9aae-b4829cb70762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658419674 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2658419674
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4256371156
Short name T230
Test name
Test status
Simulation time 10840040255 ps
CPU time 201.13 seconds
Started Jul 18 06:07:08 PM PDT 24
Finished Jul 18 06:10:34 PM PDT 24
Peak memory 237828 kb
Host smart-c9c95452-f109-452f-aab6-05db5089d666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256371156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4256371156
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2364840437
Short name T134
Test name
Test status
Simulation time 5623202273 ps
CPU time 26.06 seconds
Started Jul 18 06:07:08 PM PDT 24
Finished Jul 18 06:07:39 PM PDT 24
Peak memory 212196 kb
Host smart-f1b3d24c-51e9-478d-a90e-5ce1523cd1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364840437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2364840437
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3276518099
Short name T98
Test name
Test status
Simulation time 100042921 ps
CPU time 5.55 seconds
Started Jul 18 06:07:07 PM PDT 24
Finished Jul 18 06:07:18 PM PDT 24
Peak memory 211364 kb
Host smart-9212a8b9-74e6-47a9-8c44-ad21d97b7b63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276518099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3276518099
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1668690435
Short name T126
Test name
Test status
Simulation time 19295990704 ps
CPU time 29.12 seconds
Started Jul 18 06:07:10 PM PDT 24
Finished Jul 18 06:07:43 PM PDT 24
Peak memory 214352 kb
Host smart-c2d2981b-fe71-43c2-bec9-fdc999ffedb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668690435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1668690435
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4175308911
Short name T17
Test name
Test status
Simulation time 49702272139 ps
CPU time 107.54 seconds
Started Jul 18 06:07:08 PM PDT 24
Finished Jul 18 06:09:00 PM PDT 24
Peak memory 219392 kb
Host smart-8d0dff29-8606-4e77-b21f-85aa52a35d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175308911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4175308911
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3386461381
Short name T226
Test name
Test status
Simulation time 7042201561 ps
CPU time 15.74 seconds
Started Jul 18 06:06:31 PM PDT 24
Finished Jul 18 06:06:50 PM PDT 24
Peak memory 211440 kb
Host smart-884bf1f1-f970-45ad-b409-c30f46802302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386461381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3386461381
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3617564564
Short name T222
Test name
Test status
Simulation time 51955790051 ps
CPU time 245.52 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:10:45 PM PDT 24
Peak memory 225264 kb
Host smart-98cee006-eed2-4d50-b2d0-8223129ecf2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617564564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3617564564
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.563998606
Short name T185
Test name
Test status
Simulation time 693688731 ps
CPU time 9.32 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:06:44 PM PDT 24
Peak memory 212164 kb
Host smart-df361f6f-95af-4551-803b-56a371f2bb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563998606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.563998606
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4245531218
Short name T42
Test name
Test status
Simulation time 5619472955 ps
CPU time 13.48 seconds
Started Jul 18 06:06:35 PM PDT 24
Finished Jul 18 06:06:54 PM PDT 24
Peak memory 211476 kb
Host smart-871012b6-3b84-429b-ba3b-940efc588311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245531218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4245531218
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.281591368
Short name T336
Test name
Test status
Simulation time 1467584017 ps
CPU time 19.04 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:58 PM PDT 24
Peak memory 213920 kb
Host smart-4be467cc-7abe-4c8c-bec9-41c4992c155b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281591368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.281591368
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.116285652
Short name T166
Test name
Test status
Simulation time 5668387055 ps
CPU time 28.43 seconds
Started Jul 18 06:06:31 PM PDT 24
Finished Jul 18 06:07:02 PM PDT 24
Peak memory 215872 kb
Host smart-59199e98-0d6d-4cb8-8407-7da548dda521
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116285652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.116285652
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.767899405
Short name T122
Test name
Test status
Simulation time 2727187663 ps
CPU time 12.01 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:07:16 PM PDT 24
Peak memory 211424 kb
Host smart-85fc9958-3d28-4442-9d9d-81014196cadf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767899405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.767899405
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1572441489
Short name T203
Test name
Test status
Simulation time 44077315631 ps
CPU time 245.64 seconds
Started Jul 18 06:06:57 PM PDT 24
Finished Jul 18 06:11:07 PM PDT 24
Peak memory 237568 kb
Host smart-3a8a4b09-a69a-4599-a3f0-38770f04ce71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572441489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1572441489
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2171388520
Short name T195
Test name
Test status
Simulation time 10790809503 ps
CPU time 25.22 seconds
Started Jul 18 06:07:02 PM PDT 24
Finished Jul 18 06:07:33 PM PDT 24
Peak memory 212208 kb
Host smart-54e36051-4799-4110-a7cc-2833192d05d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171388520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2171388520
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1900433442
Short name T322
Test name
Test status
Simulation time 14797408871 ps
CPU time 16.67 seconds
Started Jul 18 06:07:03 PM PDT 24
Finished Jul 18 06:07:25 PM PDT 24
Peak memory 211476 kb
Host smart-4810141c-6afb-41c0-9a1b-0b5aa330a33d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900433442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1900433442
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3940599813
Short name T345
Test name
Test status
Simulation time 3350688533 ps
CPU time 28.55 seconds
Started Jul 18 06:07:04 PM PDT 24
Finished Jul 18 06:07:37 PM PDT 24
Peak memory 213464 kb
Host smart-5da2e7c9-0255-4226-8dd6-30897a1acc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940599813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3940599813
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2220855238
Short name T249
Test name
Test status
Simulation time 8151380587 ps
CPU time 53.19 seconds
Started Jul 18 06:07:06 PM PDT 24
Finished Jul 18 06:08:03 PM PDT 24
Peak memory 213820 kb
Host smart-8afe27f5-c244-45b8-bbdd-28bc2fb7a3bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220855238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2220855238
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1924422634
Short name T253
Test name
Test status
Simulation time 1198974496 ps
CPU time 11.49 seconds
Started Jul 18 06:07:15 PM PDT 24
Finished Jul 18 06:07:29 PM PDT 24
Peak memory 211376 kb
Host smart-61296609-611a-4284-adf7-4b602121d9da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924422634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1924422634
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3319242173
Short name T273
Test name
Test status
Simulation time 30946108446 ps
CPU time 184.7 seconds
Started Jul 18 06:07:06 PM PDT 24
Finished Jul 18 06:10:15 PM PDT 24
Peak memory 234940 kb
Host smart-a2744197-8d6a-4c09-b521-e63a4a039d88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319242173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3319242173
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.169747936
Short name T196
Test name
Test status
Simulation time 6562939873 ps
CPU time 28.79 seconds
Started Jul 18 06:07:00 PM PDT 24
Finished Jul 18 06:07:33 PM PDT 24
Peak memory 212452 kb
Host smart-3701107b-ef6d-4676-a552-daff37b0789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169747936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.169747936
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.944039242
Short name T133
Test name
Test status
Simulation time 101005044 ps
CPU time 5.54 seconds
Started Jul 18 06:06:59 PM PDT 24
Finished Jul 18 06:07:10 PM PDT 24
Peak memory 211424 kb
Host smart-e61cef43-c717-4b75-bc82-9944ba9b0112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944039242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.944039242
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.118888985
Short name T213
Test name
Test status
Simulation time 180760038 ps
CPU time 10.14 seconds
Started Jul 18 06:07:07 PM PDT 24
Finished Jul 18 06:07:22 PM PDT 24
Peak memory 213992 kb
Host smart-d1302d46-557c-4321-b6fd-a5711ff10200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118888985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.118888985
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3185288551
Short name T92
Test name
Test status
Simulation time 5980721553 ps
CPU time 64.2 seconds
Started Jul 18 06:07:10 PM PDT 24
Finished Jul 18 06:08:18 PM PDT 24
Peak memory 219448 kb
Host smart-5f4e7122-ea00-41b4-9feb-a797d0fb441a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185288551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3185288551
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3035263097
Short name T232
Test name
Test status
Simulation time 780620129 ps
CPU time 9.16 seconds
Started Jul 18 06:07:15 PM PDT 24
Finished Jul 18 06:07:26 PM PDT 24
Peak memory 211372 kb
Host smart-29ea92d7-d43c-4ddb-a692-7006d21d2666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035263097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3035263097
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.592540578
Short name T148
Test name
Test status
Simulation time 38640968771 ps
CPU time 69.84 seconds
Started Jul 18 06:07:15 PM PDT 24
Finished Jul 18 06:08:27 PM PDT 24
Peak memory 212676 kb
Host smart-98e80392-8d63-4e94-b699-a6da388b8306
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592540578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.592540578
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1797782534
Short name T129
Test name
Test status
Simulation time 3799586853 ps
CPU time 21.35 seconds
Started Jul 18 06:07:14 PM PDT 24
Finished Jul 18 06:07:38 PM PDT 24
Peak memory 211948 kb
Host smart-20c795db-880c-4f18-93dd-442827919015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797782534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1797782534
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1547719533
Short name T326
Test name
Test status
Simulation time 1813642366 ps
CPU time 10.9 seconds
Started Jul 18 06:07:15 PM PDT 24
Finished Jul 18 06:07:29 PM PDT 24
Peak memory 211412 kb
Host smart-da68e27c-07dd-42f3-947c-bfc6cd6f4db0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547719533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1547719533
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1504330776
Short name T209
Test name
Test status
Simulation time 534097190 ps
CPU time 11.67 seconds
Started Jul 18 06:07:15 PM PDT 24
Finished Jul 18 06:07:29 PM PDT 24
Peak memory 213424 kb
Host smart-6ff2a5a9-6ae8-4702-adbe-6072b4701678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504330776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1504330776
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.341223022
Short name T155
Test name
Test status
Simulation time 5428459486 ps
CPU time 34.58 seconds
Started Jul 18 06:07:15 PM PDT 24
Finished Jul 18 06:07:52 PM PDT 24
Peak memory 216468 kb
Host smart-cd80b9d2-d2c2-4422-bd0a-3ac6e7d1c456
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341223022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.341223022
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.266322161
Short name T332
Test name
Test status
Simulation time 760613671 ps
CPU time 6.69 seconds
Started Jul 18 06:07:20 PM PDT 24
Finished Jul 18 06:07:30 PM PDT 24
Peak memory 211380 kb
Host smart-8d9bbd10-f5f0-4311-9a2c-b88cf592cb1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266322161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.266322161
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.182891884
Short name T314
Test name
Test status
Simulation time 823535289 ps
CPU time 12.37 seconds
Started Jul 18 06:07:26 PM PDT 24
Finished Jul 18 06:07:42 PM PDT 24
Peak memory 212328 kb
Host smart-bb0e5345-cbd9-4844-b57f-eda9a8424086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182891884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.182891884
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.58095933
Short name T30
Test name
Test status
Simulation time 726399292 ps
CPU time 6.68 seconds
Started Jul 18 06:07:27 PM PDT 24
Finished Jul 18 06:07:37 PM PDT 24
Peak memory 211428 kb
Host smart-3157f9be-e69f-4fb6-8651-ef97a33f8348
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58095933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.58095933
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1933709667
Short name T317
Test name
Test status
Simulation time 15756131430 ps
CPU time 44.65 seconds
Started Jul 18 06:07:26 PM PDT 24
Finished Jul 18 06:08:14 PM PDT 24
Peak memory 214556 kb
Host smart-8fff7335-268b-4b14-8176-21ca1f302e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933709667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1933709667
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.671248407
Short name T267
Test name
Test status
Simulation time 69875994899 ps
CPU time 65.4 seconds
Started Jul 18 06:07:14 PM PDT 24
Finished Jul 18 06:08:22 PM PDT 24
Peak memory 218008 kb
Host smart-f395efad-fd66-4543-ab2f-7470ddb1101e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671248407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.671248407
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.843851698
Short name T258
Test name
Test status
Simulation time 41355944878 ps
CPU time 1056.55 seconds
Started Jul 18 06:07:26 PM PDT 24
Finished Jul 18 06:25:07 PM PDT 24
Peak memory 229636 kb
Host smart-075cbe0e-90b8-4baa-a23e-c9ccd7758ecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843851698 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.843851698
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3147395593
Short name T288
Test name
Test status
Simulation time 1798954715 ps
CPU time 14.53 seconds
Started Jul 18 06:07:17 PM PDT 24
Finished Jul 18 06:07:34 PM PDT 24
Peak memory 211372 kb
Host smart-d34f5f2b-a57c-4efc-a48c-29b36b612c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147395593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3147395593
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4129679393
Short name T188
Test name
Test status
Simulation time 34196180294 ps
CPU time 202.24 seconds
Started Jul 18 06:07:14 PM PDT 24
Finished Jul 18 06:10:39 PM PDT 24
Peak memory 237644 kb
Host smart-d9aa435c-321d-4c5a-946d-ea5ffc210b61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129679393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.4129679393
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1149742815
Short name T309
Test name
Test status
Simulation time 14008086328 ps
CPU time 29.1 seconds
Started Jul 18 06:07:21 PM PDT 24
Finished Jul 18 06:07:53 PM PDT 24
Peak memory 213096 kb
Host smart-40ebb7da-4ec8-4b64-add1-4a92b722c94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149742815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1149742815
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.963511755
Short name T254
Test name
Test status
Simulation time 1493256740 ps
CPU time 13.35 seconds
Started Jul 18 06:07:23 PM PDT 24
Finished Jul 18 06:07:39 PM PDT 24
Peak memory 211420 kb
Host smart-420a9fcc-9893-47b8-83ed-06508aea8ffc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963511755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.963511755
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.439881454
Short name T269
Test name
Test status
Simulation time 1711801917 ps
CPU time 20.62 seconds
Started Jul 18 06:07:15 PM PDT 24
Finished Jul 18 06:07:38 PM PDT 24
Peak memory 213272 kb
Host smart-830f7f5d-4723-4981-9648-fbc1a40bb53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439881454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.439881454
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.782171609
Short name T154
Test name
Test status
Simulation time 1279378902 ps
CPU time 19.68 seconds
Started Jul 18 06:07:14 PM PDT 24
Finished Jul 18 06:07:36 PM PDT 24
Peak memory 219364 kb
Host smart-871a1209-489f-42aa-abfb-b665abd90481
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782171609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.782171609
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1107600483
Short name T186
Test name
Test status
Simulation time 9293027541 ps
CPU time 10.82 seconds
Started Jul 18 06:07:27 PM PDT 24
Finished Jul 18 06:07:42 PM PDT 24
Peak memory 211388 kb
Host smart-fd11bebd-4fec-4b82-9895-270513d42d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107600483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1107600483
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2031980992
Short name T304
Test name
Test status
Simulation time 34955109247 ps
CPU time 192.16 seconds
Started Jul 18 06:07:19 PM PDT 24
Finished Jul 18 06:10:34 PM PDT 24
Peak memory 212624 kb
Host smart-7b793bdd-9699-452f-87b5-13290a1e9f27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031980992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2031980992
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1748336914
Short name T91
Test name
Test status
Simulation time 20717910778 ps
CPU time 30.8 seconds
Started Jul 18 06:07:14 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 212360 kb
Host smart-a84475d9-ae01-4497-a554-cddb4fd8c48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748336914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1748336914
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3719712614
Short name T320
Test name
Test status
Simulation time 3310248685 ps
CPU time 14.14 seconds
Started Jul 18 06:07:19 PM PDT 24
Finished Jul 18 06:07:36 PM PDT 24
Peak memory 211428 kb
Host smart-72e5daf1-437d-434d-9ad3-724107ffe5e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719712614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3719712614
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4020056098
Short name T319
Test name
Test status
Simulation time 3234823939 ps
CPU time 27.38 seconds
Started Jul 18 06:07:14 PM PDT 24
Finished Jul 18 06:07:44 PM PDT 24
Peak memory 213376 kb
Host smart-27f2de94-924c-49e0-885d-8565e73fd50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020056098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4020056098
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2134660404
Short name T167
Test name
Test status
Simulation time 7899149076 ps
CPU time 74.98 seconds
Started Jul 18 06:07:20 PM PDT 24
Finished Jul 18 06:08:38 PM PDT 24
Peak memory 219452 kb
Host smart-f51583cb-514d-4407-b06b-387e2eb15b43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134660404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2134660404
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.684999952
Short name T47
Test name
Test status
Simulation time 107162175509 ps
CPU time 1049.57 seconds
Started Jul 18 06:07:21 PM PDT 24
Finished Jul 18 06:24:54 PM PDT 24
Peak memory 235812 kb
Host smart-af19af7d-380e-4cf1-8ea0-64f25e2ecf81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684999952 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.684999952
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1309492039
Short name T131
Test name
Test status
Simulation time 4139670728 ps
CPU time 16.02 seconds
Started Jul 18 06:07:27 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 211452 kb
Host smart-85076f86-a33d-420b-8af7-6dfc916f29df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309492039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1309492039
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3352616565
Short name T37
Test name
Test status
Simulation time 79963769496 ps
CPU time 228.92 seconds
Started Jul 18 06:07:26 PM PDT 24
Finished Jul 18 06:11:19 PM PDT 24
Peak memory 237944 kb
Host smart-8813a6b2-f3ef-4034-8c24-ff9076d40bd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352616565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3352616565
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.160491183
Short name T197
Test name
Test status
Simulation time 7828282143 ps
CPU time 20.27 seconds
Started Jul 18 06:07:19 PM PDT 24
Finished Jul 18 06:07:43 PM PDT 24
Peak memory 211868 kb
Host smart-86afe266-e14a-45ba-922c-a1d8af4178e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160491183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.160491183
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.812062630
Short name T263
Test name
Test status
Simulation time 1132372151 ps
CPU time 8.92 seconds
Started Jul 18 06:07:15 PM PDT 24
Finished Jul 18 06:07:27 PM PDT 24
Peak memory 211396 kb
Host smart-85b16e41-7eac-440f-9fe3-2a1da936f929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812062630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.812062630
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2866131535
Short name T295
Test name
Test status
Simulation time 357554040 ps
CPU time 10.03 seconds
Started Jul 18 06:07:13 PM PDT 24
Finished Jul 18 06:07:25 PM PDT 24
Peak memory 213464 kb
Host smart-0047d2ac-72dd-4c29-853c-885b4cf72fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866131535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2866131535
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1742938744
Short name T284
Test name
Test status
Simulation time 668590611 ps
CPU time 18.99 seconds
Started Jul 18 06:07:16 PM PDT 24
Finished Jul 18 06:07:37 PM PDT 24
Peak memory 212316 kb
Host smart-947ede51-1ccc-47c2-9e62-c0868fda6bf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742938744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1742938744
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2581941038
Short name T242
Test name
Test status
Simulation time 1900208475 ps
CPU time 7.26 seconds
Started Jul 18 06:07:23 PM PDT 24
Finished Jul 18 06:07:33 PM PDT 24
Peak memory 211376 kb
Host smart-8a725892-14a8-49fc-ab30-73b96af4578f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581941038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2581941038
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1436685474
Short name T36
Test name
Test status
Simulation time 213611972533 ps
CPU time 502.05 seconds
Started Jul 18 06:07:13 PM PDT 24
Finished Jul 18 06:15:38 PM PDT 24
Peak memory 213692 kb
Host smart-e84bbecc-89e8-41c2-baf8-f90c932164d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436685474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1436685474
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1605355037
Short name T136
Test name
Test status
Simulation time 4002619719 ps
CPU time 33 seconds
Started Jul 18 06:07:27 PM PDT 24
Finished Jul 18 06:08:04 PM PDT 24
Peak memory 212012 kb
Host smart-7aa35437-62e6-4e92-9967-7c53cffe0dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605355037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1605355037
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2451780349
Short name T32
Test name
Test status
Simulation time 1235067927 ps
CPU time 12.74 seconds
Started Jul 18 06:07:19 PM PDT 24
Finished Jul 18 06:07:35 PM PDT 24
Peak memory 211424 kb
Host smart-c8094e30-d80a-4e22-b997-008d4e24b184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451780349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2451780349
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1375255311
Short name T233
Test name
Test status
Simulation time 16326718471 ps
CPU time 29.65 seconds
Started Jul 18 06:07:16 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 214788 kb
Host smart-59863061-f3c9-4487-a1cf-99df895663ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375255311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1375255311
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3009623491
Short name T191
Test name
Test status
Simulation time 2238746483 ps
CPU time 25.24 seconds
Started Jul 18 06:07:15 PM PDT 24
Finished Jul 18 06:07:42 PM PDT 24
Peak memory 216480 kb
Host smart-2c21e3f5-b4c5-4338-9426-5abc1f1d287b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009623491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3009623491
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3227182616
Short name T290
Test name
Test status
Simulation time 12038516282 ps
CPU time 15.39 seconds
Started Jul 18 06:07:27 PM PDT 24
Finished Jul 18 06:07:46 PM PDT 24
Peak memory 211380 kb
Host smart-70f13495-d843-438e-ba16-4d9dcddb4ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227182616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3227182616
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3137090439
Short name T343
Test name
Test status
Simulation time 2961051742 ps
CPU time 86.91 seconds
Started Jul 18 06:07:19 PM PDT 24
Finished Jul 18 06:08:49 PM PDT 24
Peak memory 224572 kb
Host smart-86a305ee-450f-488d-a718-d4ce74570788
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137090439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3137090439
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2912715953
Short name T214
Test name
Test status
Simulation time 1741590688 ps
CPU time 12.04 seconds
Started Jul 18 06:07:19 PM PDT 24
Finished Jul 18 06:07:34 PM PDT 24
Peak memory 212068 kb
Host smart-8abcbb47-3890-499e-8f4f-b45da7440577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912715953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2912715953
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3270474218
Short name T313
Test name
Test status
Simulation time 775797959 ps
CPU time 9.74 seconds
Started Jul 18 06:07:26 PM PDT 24
Finished Jul 18 06:07:39 PM PDT 24
Peak memory 211424 kb
Host smart-e23bc097-1cb2-476a-b13b-a3456d2db68a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3270474218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3270474218
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1347650634
Short name T256
Test name
Test status
Simulation time 4056315596 ps
CPU time 38.74 seconds
Started Jul 18 06:07:15 PM PDT 24
Finished Jul 18 06:07:56 PM PDT 24
Peak memory 213532 kb
Host smart-085363d1-5aaa-4eed-8393-083d9f9ad76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347650634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1347650634
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2620474882
Short name T142
Test name
Test status
Simulation time 4745705711 ps
CPU time 41.87 seconds
Started Jul 18 06:07:19 PM PDT 24
Finished Jul 18 06:08:04 PM PDT 24
Peak memory 213416 kb
Host smart-e979d57a-0566-419e-86fc-e68d4300914f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620474882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2620474882
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2360159053
Short name T300
Test name
Test status
Simulation time 87373687 ps
CPU time 4.26 seconds
Started Jul 18 06:07:42 PM PDT 24
Finished Jul 18 06:07:52 PM PDT 24
Peak memory 211380 kb
Host smart-9b2a8b82-fa22-40e4-ba54-df39625720ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360159053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2360159053
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.160610014
Short name T161
Test name
Test status
Simulation time 39691218377 ps
CPU time 394.49 seconds
Started Jul 18 06:07:37 PM PDT 24
Finished Jul 18 06:14:13 PM PDT 24
Peak memory 233828 kb
Host smart-5bf8f777-274b-4105-87e9-f4dfd6868d94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160610014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.160610014
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2508669421
Short name T43
Test name
Test status
Simulation time 3717819901 ps
CPU time 28.62 seconds
Started Jul 18 06:07:39 PM PDT 24
Finished Jul 18 06:08:11 PM PDT 24
Peak memory 212016 kb
Host smart-0de18e65-0a83-451f-9f64-d02d3d962340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508669421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2508669421
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2601720910
Short name T118
Test name
Test status
Simulation time 2107979385 ps
CPU time 17.02 seconds
Started Jul 18 06:07:27 PM PDT 24
Finished Jul 18 06:07:48 PM PDT 24
Peak memory 211364 kb
Host smart-aee9c6b7-ee56-463c-8a6a-07e63d4c192c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601720910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2601720910
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.920304849
Short name T369
Test name
Test status
Simulation time 1873585666 ps
CPU time 15.73 seconds
Started Jul 18 06:07:27 PM PDT 24
Finished Jul 18 06:07:46 PM PDT 24
Peak memory 213716 kb
Host smart-e8524fcc-6646-4374-af2c-eefbd9e99d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920304849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.920304849
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1304905214
Short name T261
Test name
Test status
Simulation time 25701354276 ps
CPU time 71.35 seconds
Started Jul 18 06:07:27 PM PDT 24
Finished Jul 18 06:08:42 PM PDT 24
Peak memory 218312 kb
Host smart-47953820-08f5-48fa-903b-111abb5f8ba0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304905214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1304905214
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.360862735
Short name T171
Test name
Test status
Simulation time 6976762618 ps
CPU time 13.95 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:06:51 PM PDT 24
Peak memory 211436 kb
Host smart-58f0ea15-c605-4608-b677-f0e09aed6a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360862735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.360862735
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4239705852
Short name T149
Test name
Test status
Simulation time 13951078938 ps
CPU time 181.8 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:09:41 PM PDT 24
Peak memory 229716 kb
Host smart-14251707-d0ae-4798-ae41-59b491749aac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239705852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4239705852
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4266405274
Short name T358
Test name
Test status
Simulation time 2202452491 ps
CPU time 23.83 seconds
Started Jul 18 06:06:36 PM PDT 24
Finished Jul 18 06:07:04 PM PDT 24
Peak memory 212044 kb
Host smart-758845b7-e465-45bb-8352-cc2f6f3a4490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266405274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4266405274
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3151376593
Short name T247
Test name
Test status
Simulation time 1411747051 ps
CPU time 7.97 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:48 PM PDT 24
Peak memory 211524 kb
Host smart-67396ff9-942c-407d-a2ff-c44861d8c3dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3151376593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3151376593
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.268011858
Short name T199
Test name
Test status
Simulation time 2029345541 ps
CPU time 15.85 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:06:52 PM PDT 24
Peak memory 213484 kb
Host smart-97bcb348-3e88-405a-b8b8-1ba6e4995860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268011858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.268011858
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3571245534
Short name T52
Test name
Test status
Simulation time 11695696504 ps
CPU time 15.62 seconds
Started Jul 18 06:06:31 PM PDT 24
Finished Jul 18 06:06:49 PM PDT 24
Peak memory 212864 kb
Host smart-bceb5b18-2bb8-4c68-b796-200c90e886bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571245534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3571245534
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3448672716
Short name T51
Test name
Test status
Simulation time 1983153302 ps
CPU time 15.87 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:55 PM PDT 24
Peak memory 211380 kb
Host smart-40f26aeb-11b5-4849-ad78-32424c6b7abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448672716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3448672716
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2867934730
Short name T271
Test name
Test status
Simulation time 144785488814 ps
CPU time 249.68 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 06:10:48 PM PDT 24
Peak memory 212700 kb
Host smart-dc42aa2b-b53b-457a-b2c4-fc3899015da9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867934730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2867934730
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3501660245
Short name T364
Test name
Test status
Simulation time 1663697433 ps
CPU time 12.64 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:06:48 PM PDT 24
Peak memory 211996 kb
Host smart-e4182aca-8df1-4d4e-88a4-8649dca96df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501660245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3501660245
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2112611643
Short name T302
Test name
Test status
Simulation time 2873901274 ps
CPU time 8.99 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:48 PM PDT 24
Peak memory 211480 kb
Host smart-a8ef448b-94c8-4186-8b21-f0d0c358e2a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112611643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2112611643
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1705174401
Short name T178
Test name
Test status
Simulation time 4304281372 ps
CPU time 38.29 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:07:18 PM PDT 24
Peak memory 213564 kb
Host smart-37378477-2849-4728-ac44-74c71b9d229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705174401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1705174401
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2567963198
Short name T279
Test name
Test status
Simulation time 15757037876 ps
CPU time 62.33 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:07:42 PM PDT 24
Peak memory 214944 kb
Host smart-15b0a556-10c2-41de-9527-1ce8d6203ea7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567963198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2567963198
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3464801436
Short name T50
Test name
Test status
Simulation time 85605029344 ps
CPU time 3693.32 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 07:08:11 PM PDT 24
Peak memory 250612 kb
Host smart-ff57adca-c0ad-49ca-b976-4f2681aa781b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464801436 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3464801436
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.501139536
Short name T272
Test name
Test status
Simulation time 347001629 ps
CPU time 4.24 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 06:06:42 PM PDT 24
Peak memory 211364 kb
Host smart-7e289f71-86a3-420c-a171-39213ad1f3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501139536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.501139536
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2412936301
Short name T225
Test name
Test status
Simulation time 51825413717 ps
CPU time 330.31 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 06:12:08 PM PDT 24
Peak memory 234964 kb
Host smart-17292ef9-f226-4431-bf81-4681b63376c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412936301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2412936301
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1235883616
Short name T157
Test name
Test status
Simulation time 3361533190 ps
CPU time 28.16 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:07:05 PM PDT 24
Peak memory 212340 kb
Host smart-6d638140-2f45-438f-be31-290ef9b881f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235883616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1235883616
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1349524275
Short name T215
Test name
Test status
Simulation time 1867426389 ps
CPU time 15.6 seconds
Started Jul 18 06:06:30 PM PDT 24
Finished Jul 18 06:06:48 PM PDT 24
Peak memory 211428 kb
Host smart-d52f9070-8a32-4b6c-ab65-3adebe4a8e23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349524275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1349524275
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3993542833
Short name T140
Test name
Test status
Simulation time 183132674 ps
CPU time 10.43 seconds
Started Jul 18 06:06:30 PM PDT 24
Finished Jul 18 06:06:42 PM PDT 24
Peak memory 213592 kb
Host smart-3d04f02f-2652-430f-ab5b-46c82fcd6f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993542833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3993542833
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1916493378
Short name T340
Test name
Test status
Simulation time 1232534994 ps
CPU time 32.17 seconds
Started Jul 18 06:06:31 PM PDT 24
Finished Jul 18 06:07:07 PM PDT 24
Peak memory 213880 kb
Host smart-ae74ea24-306d-4c58-b6ee-ddeefacc24be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916493378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1916493378
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.65356915
Short name T12
Test name
Test status
Simulation time 133347402505 ps
CPU time 3294.99 seconds
Started Jul 18 06:06:31 PM PDT 24
Finished Jul 18 07:01:28 PM PDT 24
Peak memory 232916 kb
Host smart-1469b9cc-bc37-4e0d-8b4c-c46a3f32b008
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65356915 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.65356915
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.837913800
Short name T210
Test name
Test status
Simulation time 3956165995 ps
CPU time 15.33 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:06:52 PM PDT 24
Peak memory 211436 kb
Host smart-ea695137-9387-42ad-8341-f9fd15473467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837913800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.837913800
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1794958357
Short name T357
Test name
Test status
Simulation time 526078453456 ps
CPU time 279.39 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:11:18 PM PDT 24
Peak memory 236828 kb
Host smart-93e2ec20-3a7a-4554-9d40-f5df93573864
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794958357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1794958357
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.877772260
Short name T311
Test name
Test status
Simulation time 31104530309 ps
CPU time 20.19 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:59 PM PDT 24
Peak memory 212236 kb
Host smart-0e4e9091-ac5a-4869-98c4-5c1af3cf7b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877772260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.877772260
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4148102219
Short name T370
Test name
Test status
Simulation time 1171024631 ps
CPU time 7.47 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:46 PM PDT 24
Peak memory 211396 kb
Host smart-ad1e2216-a1db-428c-8681-93579076e6d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148102219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4148102219
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2080034232
Short name T264
Test name
Test status
Simulation time 619376717 ps
CPU time 14.59 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:06:50 PM PDT 24
Peak memory 211988 kb
Host smart-575765bb-3589-4788-9f8a-f88ca8d720f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080034232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2080034232
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3662370537
Short name T189
Test name
Test status
Simulation time 635726809 ps
CPU time 33.9 seconds
Started Jul 18 06:06:33 PM PDT 24
Finished Jul 18 06:07:12 PM PDT 24
Peak memory 215528 kb
Host smart-956c1896-0efd-4a41-a422-d97720031606
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662370537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3662370537
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2819947446
Short name T292
Test name
Test status
Simulation time 25905812731 ps
CPU time 16.94 seconds
Started Jul 18 06:06:35 PM PDT 24
Finished Jul 18 06:06:57 PM PDT 24
Peak memory 211432 kb
Host smart-9025d684-ae74-4647-b702-167472dd5bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819947446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2819947446
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.760552184
Short name T231
Test name
Test status
Simulation time 110121965671 ps
CPU time 228.5 seconds
Started Jul 18 06:06:30 PM PDT 24
Finished Jul 18 06:10:21 PM PDT 24
Peak memory 232672 kb
Host smart-e8e1be81-7e76-4d9a-8aec-8455c249f43e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760552184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.760552184
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2236746067
Short name T360
Test name
Test status
Simulation time 4143112564 ps
CPU time 33.46 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:07:13 PM PDT 24
Peak memory 211920 kb
Host smart-6507afa3-216b-4be0-a3b9-7007aaf7cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236746067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2236746067
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4284941510
Short name T274
Test name
Test status
Simulation time 1227105909 ps
CPU time 8.8 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:06:45 PM PDT 24
Peak memory 211400 kb
Host smart-aec51e07-2769-4e35-8e73-cbd0f09cd235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284941510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4284941510
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3451972949
Short name T97
Test name
Test status
Simulation time 250196593 ps
CPU time 10.03 seconds
Started Jul 18 06:06:34 PM PDT 24
Finished Jul 18 06:06:49 PM PDT 24
Peak memory 212992 kb
Host smart-18da587b-d101-4c05-904b-e6b50b4440c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451972949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3451972949
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1638576137
Short name T70
Test name
Test status
Simulation time 6247967802 ps
CPU time 66.3 seconds
Started Jul 18 06:06:32 PM PDT 24
Finished Jul 18 06:07:42 PM PDT 24
Peak memory 217308 kb
Host smart-19b71261-8c21-4809-8f4c-41f79057eaeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638576137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1638576137
Directory /workspace/9.rom_ctrl_stress_all/latest
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