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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.34 96.89 91.99 97.67 100.00 98.28 97.45 99.07


Total test records in report: 466
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T300 /workspace/coverage/default/6.rom_ctrl_stress_all.2580205025 Jul 19 04:52:06 PM PDT 24 Jul 19 04:52:44 PM PDT 24 1937981901 ps
T301 /workspace/coverage/default/3.rom_ctrl_alert_test.338610735 Jul 19 04:51:56 PM PDT 24 Jul 19 04:52:05 PM PDT 24 1706748417 ps
T302 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2868362654 Jul 19 04:53:39 PM PDT 24 Jul 19 04:54:01 PM PDT 24 27343338861 ps
T303 /workspace/coverage/default/32.rom_ctrl_alert_test.1909795556 Jul 19 04:53:10 PM PDT 24 Jul 19 04:53:17 PM PDT 24 487727212 ps
T42 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.996562452 Jul 19 04:52:43 PM PDT 24 Jul 19 05:22:55 PM PDT 24 28294796497 ps
T43 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3228643191 Jul 19 04:52:34 PM PDT 24 Jul 19 05:33:49 PM PDT 24 748870802852 ps
T304 /workspace/coverage/default/16.rom_ctrl_alert_test.586132078 Jul 19 04:52:34 PM PDT 24 Jul 19 04:52:42 PM PDT 24 347710705 ps
T305 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3667850142 Jul 19 04:52:25 PM PDT 24 Jul 19 04:52:49 PM PDT 24 3102088617 ps
T306 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.219870016 Jul 19 04:53:00 PM PDT 24 Jul 19 04:57:32 PM PDT 24 44163680466 ps
T307 /workspace/coverage/default/23.rom_ctrl_stress_all.203081479 Jul 19 04:52:53 PM PDT 24 Jul 19 04:53:10 PM PDT 24 813249934 ps
T308 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2547512308 Jul 19 04:52:25 PM PDT 24 Jul 19 04:52:49 PM PDT 24 1899916492 ps
T309 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4246535659 Jul 19 04:52:34 PM PDT 24 Jul 19 04:56:31 PM PDT 24 30360930037 ps
T310 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2525802980 Jul 19 04:53:03 PM PDT 24 Jul 19 04:53:12 PM PDT 24 94235507 ps
T311 /workspace/coverage/default/34.rom_ctrl_stress_all.1957021703 Jul 19 04:53:08 PM PDT 24 Jul 19 04:53:47 PM PDT 24 12417066767 ps
T312 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3360661800 Jul 19 04:53:19 PM PDT 24 Jul 19 05:46:01 PM PDT 24 123600701077 ps
T313 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3889150555 Jul 19 04:52:54 PM PDT 24 Jul 19 04:53:26 PM PDT 24 3591250792 ps
T314 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3291877128 Jul 19 04:52:52 PM PDT 24 Jul 19 05:21:55 PM PDT 24 43629453473 ps
T315 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.329943481 Jul 19 04:53:09 PM PDT 24 Jul 19 05:52:53 PM PDT 24 14716292700 ps
T316 /workspace/coverage/default/36.rom_ctrl_smoke.3099483942 Jul 19 04:53:08 PM PDT 24 Jul 19 04:53:38 PM PDT 24 6979860982 ps
T317 /workspace/coverage/default/39.rom_ctrl_smoke.4073203149 Jul 19 04:53:18 PM PDT 24 Jul 19 04:53:47 PM PDT 24 4385778393 ps
T318 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.118009081 Jul 19 04:51:53 PM PDT 24 Jul 19 04:52:20 PM PDT 24 11150402686 ps
T319 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.938233657 Jul 19 04:52:25 PM PDT 24 Jul 19 04:57:29 PM PDT 24 90173837372 ps
T320 /workspace/coverage/default/25.rom_ctrl_alert_test.3496841669 Jul 19 04:52:56 PM PDT 24 Jul 19 04:53:15 PM PDT 24 4095760617 ps
T321 /workspace/coverage/default/29.rom_ctrl_stress_all.1787218167 Jul 19 04:53:01 PM PDT 24 Jul 19 04:53:25 PM PDT 24 5731598509 ps
T322 /workspace/coverage/default/38.rom_ctrl_alert_test.2028165020 Jul 19 04:53:19 PM PDT 24 Jul 19 04:53:25 PM PDT 24 86382087 ps
T323 /workspace/coverage/default/27.rom_ctrl_stress_all.3288956800 Jul 19 04:52:55 PM PDT 24 Jul 19 04:53:34 PM PDT 24 3641726446 ps
T324 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2108892939 Jul 19 04:52:33 PM PDT 24 Jul 19 04:52:45 PM PDT 24 639239179 ps
T325 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.534714547 Jul 19 04:52:46 PM PDT 24 Jul 19 05:00:02 PM PDT 24 282816551577 ps
T326 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1419271541 Jul 19 04:52:23 PM PDT 24 Jul 19 04:52:41 PM PDT 24 1504209179 ps
T327 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.198628437 Jul 19 04:53:40 PM PDT 24 Jul 19 04:53:51 PM PDT 24 666088447 ps
T328 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2454569688 Jul 19 04:53:38 PM PDT 24 Jul 19 04:53:57 PM PDT 24 2219859246 ps
T329 /workspace/coverage/default/44.rom_ctrl_stress_all.3386666626 Jul 19 04:53:27 PM PDT 24 Jul 19 04:54:34 PM PDT 24 38527472416 ps
T330 /workspace/coverage/default/22.rom_ctrl_smoke.1068244606 Jul 19 04:52:45 PM PDT 24 Jul 19 04:52:57 PM PDT 24 422836718 ps
T331 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3340378697 Jul 19 04:53:09 PM PDT 24 Jul 19 05:44:01 PM PDT 24 108342269729 ps
T332 /workspace/coverage/default/41.rom_ctrl_smoke.790363767 Jul 19 04:53:17 PM PDT 24 Jul 19 04:53:37 PM PDT 24 4185394012 ps
T333 /workspace/coverage/default/46.rom_ctrl_alert_test.1568749248 Jul 19 04:53:40 PM PDT 24 Jul 19 04:53:53 PM PDT 24 1193063352 ps
T334 /workspace/coverage/default/36.rom_ctrl_alert_test.103595566 Jul 19 04:53:10 PM PDT 24 Jul 19 04:53:27 PM PDT 24 15646261774 ps
T335 /workspace/coverage/default/39.rom_ctrl_stress_all.207182878 Jul 19 04:53:18 PM PDT 24 Jul 19 04:53:36 PM PDT 24 1136077565 ps
T336 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.94209235 Jul 19 04:53:00 PM PDT 24 Jul 19 04:53:28 PM PDT 24 11239446100 ps
T337 /workspace/coverage/default/26.rom_ctrl_alert_test.108491286 Jul 19 04:52:52 PM PDT 24 Jul 19 04:53:03 PM PDT 24 986656825 ps
T338 /workspace/coverage/default/10.rom_ctrl_smoke.1851894948 Jul 19 04:52:21 PM PDT 24 Jul 19 04:52:53 PM PDT 24 9946197609 ps
T339 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4149382307 Jul 19 04:53:38 PM PDT 24 Jul 19 04:53:54 PM PDT 24 4063371429 ps
T340 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.4087077235 Jul 19 04:53:27 PM PDT 24 Jul 19 05:32:48 PM PDT 24 143876637406 ps
T341 /workspace/coverage/default/40.rom_ctrl_stress_all.2683675080 Jul 19 04:53:19 PM PDT 24 Jul 19 04:53:36 PM PDT 24 758672134 ps
T342 /workspace/coverage/default/4.rom_ctrl_stress_all.320020977 Jul 19 04:51:59 PM PDT 24 Jul 19 04:52:38 PM PDT 24 23438059624 ps
T343 /workspace/coverage/default/47.rom_ctrl_smoke.1721934517 Jul 19 04:53:40 PM PDT 24 Jul 19 04:53:52 PM PDT 24 183660982 ps
T344 /workspace/coverage/default/5.rom_ctrl_stress_all.3851788673 Jul 19 04:52:07 PM PDT 24 Jul 19 04:53:58 PM PDT 24 11073554463 ps
T345 /workspace/coverage/default/29.rom_ctrl_smoke.1929747875 Jul 19 04:53:02 PM PDT 24 Jul 19 04:53:19 PM PDT 24 535991347 ps
T346 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2840339778 Jul 19 04:53:36 PM PDT 24 Jul 19 04:55:52 PM PDT 24 10002824018 ps
T347 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3758397760 Jul 19 04:53:03 PM PDT 24 Jul 19 04:53:22 PM PDT 24 23593570597 ps
T348 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1437968480 Jul 19 04:52:16 PM PDT 24 Jul 19 04:52:23 PM PDT 24 715783054 ps
T349 /workspace/coverage/default/11.rom_ctrl_alert_test.1957258569 Jul 19 04:52:23 PM PDT 24 Jul 19 04:52:39 PM PDT 24 2617819009 ps
T350 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3808093235 Jul 19 04:53:03 PM PDT 24 Jul 19 04:53:17 PM PDT 24 872389084 ps
T351 /workspace/coverage/default/41.rom_ctrl_stress_all.869705911 Jul 19 04:53:25 PM PDT 24 Jul 19 04:53:45 PM PDT 24 1293193810 ps
T352 /workspace/coverage/default/15.rom_ctrl_smoke.3789225527 Jul 19 04:52:33 PM PDT 24 Jul 19 04:53:11 PM PDT 24 8731171160 ps
T353 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2254490114 Jul 19 04:52:53 PM PDT 24 Jul 19 04:53:23 PM PDT 24 16762887670 ps
T95 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1446584541 Jul 19 04:52:24 PM PDT 24 Jul 19 04:52:39 PM PDT 24 2474660942 ps
T354 /workspace/coverage/default/11.rom_ctrl_stress_all.444724203 Jul 19 04:52:26 PM PDT 24 Jul 19 04:53:04 PM PDT 24 9368801780 ps
T355 /workspace/coverage/default/28.rom_ctrl_stress_all.3386717982 Jul 19 04:53:02 PM PDT 24 Jul 19 04:54:10 PM PDT 24 44618813425 ps
T356 /workspace/coverage/default/6.rom_ctrl_alert_test.3155515395 Jul 19 04:52:07 PM PDT 24 Jul 19 04:52:22 PM PDT 24 2805837912 ps
T357 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3551263880 Jul 19 04:52:17 PM PDT 24 Jul 19 04:52:48 PM PDT 24 22165857350 ps
T358 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.846646460 Jul 19 04:53:40 PM PDT 24 Jul 19 04:53:55 PM PDT 24 3863486369 ps
T359 /workspace/coverage/default/9.rom_ctrl_smoke.124623839 Jul 19 04:52:21 PM PDT 24 Jul 19 04:52:55 PM PDT 24 14258901590 ps
T360 /workspace/coverage/default/42.rom_ctrl_alert_test.127332618 Jul 19 04:53:27 PM PDT 24 Jul 19 04:53:39 PM PDT 24 3641006313 ps
T361 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1607929489 Jul 19 04:53:02 PM PDT 24 Jul 19 04:53:33 PM PDT 24 13334380814 ps
T362 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3213687606 Jul 19 04:53:20 PM PDT 24 Jul 19 04:53:51 PM PDT 24 11893739409 ps
T363 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3169162163 Jul 19 04:52:33 PM PDT 24 Jul 19 04:52:51 PM PDT 24 6605211435 ps
T17 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1247849788 Jul 19 04:52:32 PM PDT 24 Jul 19 05:19:19 PM PDT 24 161248124549 ps
T364 /workspace/coverage/default/24.rom_ctrl_stress_all.1151251428 Jul 19 04:52:55 PM PDT 24 Jul 19 04:53:55 PM PDT 24 22680567999 ps
T365 /workspace/coverage/default/24.rom_ctrl_alert_test.3570762105 Jul 19 04:52:53 PM PDT 24 Jul 19 04:53:03 PM PDT 24 555831987 ps
T366 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1527378036 Jul 19 04:52:34 PM PDT 24 Jul 19 04:52:53 PM PDT 24 3281546209 ps
T47 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3333252494 Jul 19 04:38:03 PM PDT 24 Jul 19 04:39:50 PM PDT 24 13186024212 ps
T367 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.13097840 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:19 PM PDT 24 5928625772 ps
T44 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2012383243 Jul 19 04:38:02 PM PDT 24 Jul 19 04:39:19 PM PDT 24 6139956180 ps
T368 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2267830601 Jul 19 04:38:23 PM PDT 24 Jul 19 04:38:51 PM PDT 24 7432311064 ps
T48 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1652596048 Jul 19 04:38:01 PM PDT 24 Jul 19 04:38:10 PM PDT 24 357007326 ps
T45 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3373575125 Jul 19 04:38:32 PM PDT 24 Jul 19 04:40:00 PM PDT 24 12424174620 ps
T55 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2652081410 Jul 19 04:38:19 PM PDT 24 Jul 19 04:38:33 PM PDT 24 1077111908 ps
T369 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4079067306 Jul 19 04:38:05 PM PDT 24 Jul 19 04:38:24 PM PDT 24 5071896433 ps
T96 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1192892509 Jul 19 04:37:55 PM PDT 24 Jul 19 04:38:03 PM PDT 24 671615724 ps
T97 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1944339716 Jul 19 04:37:48 PM PDT 24 Jul 19 04:38:00 PM PDT 24 7401823871 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.418684583 Jul 19 04:38:01 PM PDT 24 Jul 19 04:38:20 PM PDT 24 2130158985 ps
T92 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4182444335 Jul 19 04:38:18 PM PDT 24 Jul 19 04:38:33 PM PDT 24 6531568838 ps
T99 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.801624665 Jul 19 04:38:21 PM PDT 24 Jul 19 04:38:32 PM PDT 24 743646628 ps
T370 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2896879724 Jul 19 04:38:25 PM PDT 24 Jul 19 04:38:42 PM PDT 24 3766363478 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2390286020 Jul 19 04:37:55 PM PDT 24 Jul 19 04:38:05 PM PDT 24 1635317521 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3707745360 Jul 19 04:37:53 PM PDT 24 Jul 19 04:38:11 PM PDT 24 13352055734 ps
T373 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.738838614 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:19 PM PDT 24 1630337410 ps
T93 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.50871847 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:25 PM PDT 24 14779050339 ps
T100 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.309681165 Jul 19 04:38:04 PM PDT 24 Jul 19 04:38:12 PM PDT 24 89172940 ps
T46 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.443187001 Jul 19 04:38:00 PM PDT 24 Jul 19 04:39:19 PM PDT 24 1875893593 ps
T374 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2972074197 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:20 PM PDT 24 4661432407 ps
T102 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1280633482 Jul 19 04:38:20 PM PDT 24 Jul 19 04:39:09 PM PDT 24 2858789188 ps
T375 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4253477649 Jul 19 04:38:30 PM PDT 24 Jul 19 04:38:52 PM PDT 24 1479549094 ps
T376 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3810280152 Jul 19 04:38:17 PM PDT 24 Jul 19 04:38:32 PM PDT 24 1616026525 ps
T56 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2393574450 Jul 19 04:38:05 PM PDT 24 Jul 19 04:38:20 PM PDT 24 16990056524 ps
T57 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4108900564 Jul 19 04:38:00 PM PDT 24 Jul 19 04:38:17 PM PDT 24 1734097247 ps
T94 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.850503885 Jul 19 04:38:28 PM PDT 24 Jul 19 04:39:50 PM PDT 24 22065088721 ps
T106 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.366321984 Jul 19 04:38:04 PM PDT 24 Jul 19 04:38:47 PM PDT 24 677969854 ps
T58 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2872399572 Jul 19 04:38:01 PM PDT 24 Jul 19 04:38:19 PM PDT 24 12542183754 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.943863950 Jul 19 04:38:06 PM PDT 24 Jul 19 04:38:24 PM PDT 24 4117137116 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3477236224 Jul 19 04:38:11 PM PDT 24 Jul 19 04:38:20 PM PDT 24 2050594846 ps
T379 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3906221055 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:19 PM PDT 24 3532320571 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3860688238 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:17 PM PDT 24 1110361292 ps
T59 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2267865418 Jul 19 04:38:23 PM PDT 24 Jul 19 04:38:32 PM PDT 24 347253246 ps
T60 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2613203735 Jul 19 04:38:26 PM PDT 24 Jul 19 04:38:38 PM PDT 24 492753351 ps
T61 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3136164814 Jul 19 04:38:19 PM PDT 24 Jul 19 04:39:21 PM PDT 24 28032216475 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2238295035 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:11 PM PDT 24 329711015 ps
T62 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.565921206 Jul 19 04:38:18 PM PDT 24 Jul 19 04:38:31 PM PDT 24 1147103766 ps
T382 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3024648981 Jul 19 04:38:19 PM PDT 24 Jul 19 04:38:37 PM PDT 24 1695932302 ps
T383 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2428248962 Jul 19 04:38:24 PM PDT 24 Jul 19 04:38:38 PM PDT 24 1544074345 ps
T384 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.131679481 Jul 19 04:38:04 PM PDT 24 Jul 19 04:38:27 PM PDT 24 2071392235 ps
T105 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.822978448 Jul 19 04:38:18 PM PDT 24 Jul 19 04:39:35 PM PDT 24 1812054820 ps
T385 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2272538502 Jul 19 04:38:01 PM PDT 24 Jul 19 04:38:10 PM PDT 24 511184052 ps
T386 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1749171345 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:15 PM PDT 24 915023483 ps
T63 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2431410253 Jul 19 04:38:29 PM PDT 24 Jul 19 04:39:33 PM PDT 24 6419635481 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.122219853 Jul 19 04:38:06 PM PDT 24 Jul 19 04:38:13 PM PDT 24 593054721 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2473793070 Jul 19 04:38:00 PM PDT 24 Jul 19 04:38:05 PM PDT 24 519634712 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2882820418 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:12 PM PDT 24 1712182881 ps
T70 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3630079010 Jul 19 04:38:11 PM PDT 24 Jul 19 04:38:19 PM PDT 24 1094184577 ps
T390 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3864911120 Jul 19 04:38:06 PM PDT 24 Jul 19 04:38:18 PM PDT 24 690924109 ps
T391 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.134910230 Jul 19 04:38:11 PM PDT 24 Jul 19 04:39:23 PM PDT 24 6321277709 ps
T392 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2669822844 Jul 19 04:38:04 PM PDT 24 Jul 19 04:39:02 PM PDT 24 25973610124 ps
T393 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4156612685 Jul 19 04:38:19 PM PDT 24 Jul 19 04:38:34 PM PDT 24 900517294 ps
T394 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1302561854 Jul 19 04:38:11 PM PDT 24 Jul 19 04:38:23 PM PDT 24 5354748370 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2782358475 Jul 19 04:37:50 PM PDT 24 Jul 19 04:37:57 PM PDT 24 1945259131 ps
T396 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2990361716 Jul 19 04:38:05 PM PDT 24 Jul 19 04:38:20 PM PDT 24 7507883795 ps
T397 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1740506670 Jul 19 04:38:28 PM PDT 24 Jul 19 04:38:45 PM PDT 24 208907394 ps
T398 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1441592008 Jul 19 04:38:27 PM PDT 24 Jul 19 04:38:49 PM PDT 24 4231288741 ps
T71 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2859896921 Jul 19 04:37:53 PM PDT 24 Jul 19 04:38:41 PM PDT 24 6688300397 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.230211591 Jul 19 04:38:00 PM PDT 24 Jul 19 04:38:15 PM PDT 24 1422780276 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3147332869 Jul 19 04:38:03 PM PDT 24 Jul 19 04:39:22 PM PDT 24 13922392767 ps
T400 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.339585871 Jul 19 04:38:08 PM PDT 24 Jul 19 04:38:27 PM PDT 24 1899797314 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2755140666 Jul 19 04:37:59 PM PDT 24 Jul 19 04:38:38 PM PDT 24 369262635 ps
T103 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3931331914 Jul 19 04:37:52 PM PDT 24 Jul 19 04:39:05 PM PDT 24 1141237345 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2863630444 Jul 19 04:38:08 PM PDT 24 Jul 19 04:38:24 PM PDT 24 6459395360 ps
T112 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4062707663 Jul 19 04:38:08 PM PDT 24 Jul 19 04:38:54 PM PDT 24 3213761448 ps
T402 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1634692194 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:17 PM PDT 24 1471408929 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1360418471 Jul 19 04:38:04 PM PDT 24 Jul 19 04:38:25 PM PDT 24 4164669551 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3093790375 Jul 19 04:38:00 PM PDT 24 Jul 19 04:38:18 PM PDT 24 15429131944 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3121401654 Jul 19 04:38:21 PM PDT 24 Jul 19 04:38:37 PM PDT 24 1419494882 ps
T406 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.531699087 Jul 19 04:38:17 PM PDT 24 Jul 19 04:38:28 PM PDT 24 5758913609 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3625403582 Jul 19 04:37:58 PM PDT 24 Jul 19 04:38:05 PM PDT 24 170579418 ps
T408 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2235764843 Jul 19 04:38:01 PM PDT 24 Jul 19 04:38:15 PM PDT 24 1303683385 ps
T409 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.922368235 Jul 19 04:38:20 PM PDT 24 Jul 19 04:38:43 PM PDT 24 2082717665 ps
T410 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1475583333 Jul 19 04:38:18 PM PDT 24 Jul 19 04:38:32 PM PDT 24 10270223011 ps
T73 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3440695399 Jul 19 04:38:05 PM PDT 24 Jul 19 04:38:48 PM PDT 24 3468919881 ps
T74 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.17966071 Jul 19 04:38:07 PM PDT 24 Jul 19 04:38:22 PM PDT 24 1431561439 ps
T411 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2424975796 Jul 19 04:38:04 PM PDT 24 Jul 19 04:38:22 PM PDT 24 1559864151 ps
T412 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3770435746 Jul 19 04:38:01 PM PDT 24 Jul 19 04:38:49 PM PDT 24 4623813000 ps
T413 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.518162108 Jul 19 04:38:18 PM PDT 24 Jul 19 04:38:26 PM PDT 24 2270466197 ps
T75 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1302643931 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:20 PM PDT 24 2420472137 ps
T414 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1807104898 Jul 19 04:38:20 PM PDT 24 Jul 19 04:38:41 PM PDT 24 1808573671 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2724290857 Jul 19 04:37:50 PM PDT 24 Jul 19 04:38:40 PM PDT 24 5581917872 ps
T416 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.71842251 Jul 19 04:37:45 PM PDT 24 Jul 19 04:37:59 PM PDT 24 1515437859 ps
T417 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2948283041 Jul 19 04:38:28 PM PDT 24 Jul 19 04:38:51 PM PDT 24 7072073942 ps
T418 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2593732821 Jul 19 04:38:19 PM PDT 24 Jul 19 04:39:10 PM PDT 24 20472181148 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3315725359 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:17 PM PDT 24 130809980 ps
T420 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3451933263 Jul 19 04:38:19 PM PDT 24 Jul 19 04:39:05 PM PDT 24 15895577934 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2382949758 Jul 19 04:37:44 PM PDT 24 Jul 19 04:37:58 PM PDT 24 871582508 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3988892096 Jul 19 04:37:51 PM PDT 24 Jul 19 04:38:00 PM PDT 24 3220940063 ps
T423 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1015235752 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:21 PM PDT 24 6355679425 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1490908539 Jul 19 04:37:45 PM PDT 24 Jul 19 04:37:50 PM PDT 24 346759252 ps
T76 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2303767936 Jul 19 04:37:56 PM PDT 24 Jul 19 04:38:00 PM PDT 24 346538296 ps
T425 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.597605625 Jul 19 04:38:23 PM PDT 24 Jul 19 04:38:51 PM PDT 24 715880567 ps
T77 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4049720961 Jul 19 04:38:04 PM PDT 24 Jul 19 04:38:46 PM PDT 24 12600509772 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1042278887 Jul 19 04:38:12 PM PDT 24 Jul 19 04:39:23 PM PDT 24 341590437 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.408162486 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:56 PM PDT 24 20386909919 ps
T428 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3234478447 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:33 PM PDT 24 1057699004 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.463076 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:19 PM PDT 24 6703279066 ps
T430 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3769228379 Jul 19 04:37:58 PM PDT 24 Jul 19 04:38:17 PM PDT 24 538836197 ps
T80 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2132981249 Jul 19 04:38:01 PM PDT 24 Jul 19 04:38:55 PM PDT 24 3289300812 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.417154378 Jul 19 04:38:00 PM PDT 24 Jul 19 04:38:11 PM PDT 24 822719530 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2495065258 Jul 19 04:37:59 PM PDT 24 Jul 19 04:38:05 PM PDT 24 347820339 ps
T107 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.394978849 Jul 19 04:38:20 PM PDT 24 Jul 19 04:39:08 PM PDT 24 202945108 ps
T433 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.217002884 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:48 PM PDT 24 4058631399 ps
T434 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3477900821 Jul 19 04:38:19 PM PDT 24 Jul 19 04:38:40 PM PDT 24 8160016556 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3170763006 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:19 PM PDT 24 3585832176 ps
T436 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3347917288 Jul 19 04:38:00 PM PDT 24 Jul 19 04:38:20 PM PDT 24 2310267548 ps
T81 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4200771231 Jul 19 04:38:12 PM PDT 24 Jul 19 04:39:00 PM PDT 24 47580781220 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1102257277 Jul 19 04:38:01 PM PDT 24 Jul 19 04:38:17 PM PDT 24 5611136766 ps
T111 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.49648505 Jul 19 04:38:28 PM PDT 24 Jul 19 04:39:21 PM PDT 24 1742286056 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1646707778 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:10 PM PDT 24 85807696 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.932312205 Jul 19 04:37:47 PM PDT 24 Jul 19 04:37:53 PM PDT 24 347084787 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2120665713 Jul 19 04:38:06 PM PDT 24 Jul 19 04:39:22 PM PDT 24 1338386039 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.672991788 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:14 PM PDT 24 1901674833 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1019977165 Jul 19 04:38:05 PM PDT 24 Jul 19 04:38:16 PM PDT 24 1637478081 ps
T442 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2223136678 Jul 19 04:38:17 PM PDT 24 Jul 19 04:38:34 PM PDT 24 2133539197 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1338519531 Jul 19 04:37:48 PM PDT 24 Jul 19 04:39:04 PM PDT 24 524782460 ps
T443 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.27463171 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:52 PM PDT 24 1948952158 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1964422402 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:15 PM PDT 24 1567937834 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1982590872 Jul 19 04:37:48 PM PDT 24 Jul 19 04:38:01 PM PDT 24 3161501641 ps
T446 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.978982856 Jul 19 04:38:04 PM PDT 24 Jul 19 04:38:25 PM PDT 24 19893378156 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2806776778 Jul 19 04:37:53 PM PDT 24 Jul 19 04:38:12 PM PDT 24 6667087262 ps
T448 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3825667695 Jul 19 04:38:14 PM PDT 24 Jul 19 04:38:29 PM PDT 24 1777496143 ps
T449 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3979493103 Jul 19 04:38:06 PM PDT 24 Jul 19 04:38:15 PM PDT 24 1038482085 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4005926770 Jul 19 04:38:00 PM PDT 24 Jul 19 04:38:14 PM PDT 24 2790694574 ps
T78 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1185083286 Jul 19 04:38:02 PM PDT 24 Jul 19 04:39:08 PM PDT 24 6342606256 ps
T451 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2979386623 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:15 PM PDT 24 2949944867 ps
T452 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2645771172 Jul 19 04:38:02 PM PDT 24 Jul 19 04:38:14 PM PDT 24 6444048510 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1547842856 Jul 19 04:38:28 PM PDT 24 Jul 19 04:38:40 PM PDT 24 409633083 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3384847956 Jul 19 04:38:05 PM PDT 24 Jul 19 04:38:17 PM PDT 24 1188647367 ps
T455 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3895103171 Jul 19 04:38:18 PM PDT 24 Jul 19 04:39:03 PM PDT 24 9056728915 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2268209096 Jul 19 04:37:53 PM PDT 24 Jul 19 04:38:02 PM PDT 24 1098563204 ps
T79 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2089036847 Jul 19 04:37:58 PM PDT 24 Jul 19 04:39:00 PM PDT 24 15458722482 ps
T457 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.69628485 Jul 19 04:38:19 PM PDT 24 Jul 19 04:38:34 PM PDT 24 2605541011 ps
T458 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3115698599 Jul 19 04:38:04 PM PDT 24 Jul 19 04:38:23 PM PDT 24 8542319431 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3790604490 Jul 19 04:37:51 PM PDT 24 Jul 19 04:38:03 PM PDT 24 820310139 ps
T460 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.193318195 Jul 19 04:38:28 PM PDT 24 Jul 19 04:38:47 PM PDT 24 5563027456 ps
T461 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2213504211 Jul 19 04:38:24 PM PDT 24 Jul 19 04:38:44 PM PDT 24 3793169197 ps
T108 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2418756179 Jul 19 04:38:19 PM PDT 24 Jul 19 04:39:38 PM PDT 24 5220803094 ps
T462 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.577146728 Jul 19 04:38:03 PM PDT 24 Jul 19 04:38:19 PM PDT 24 1310993867 ps
T463 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.513386077 Jul 19 04:38:04 PM PDT 24 Jul 19 04:39:22 PM PDT 24 1660987346 ps
T464 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3900118353 Jul 19 04:37:53 PM PDT 24 Jul 19 04:37:58 PM PDT 24 637856830 ps
T465 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.876304765 Jul 19 04:38:00 PM PDT 24 Jul 19 04:38:09 PM PDT 24 96584812 ps
T466 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2068523057 Jul 19 04:37:55 PM PDT 24 Jul 19 04:38:05 PM PDT 24 817009148 ps

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3714138055
Short name T3
Test name
Test status
Simulation time 80582441558 ps
CPU time 4147.75 seconds
Started Jul 19 04:53:12 PM PDT 24
Finished Jul 19 06:02:22 PM PDT 24
Peak memory 230616 kb
Host smart-cac3710d-a0ac-41de-a200-a1e385aa1198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714138055 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3714138055
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1896409654
Short name T20
Test name
Test status
Simulation time 64224549842 ps
CPU time 384.25 seconds
Started Jul 19 04:53:09 PM PDT 24
Finished Jul 19 04:59:35 PM PDT 24
Peak memory 234912 kb
Host smart-27b44d95-004a-41c6-85d6-8d89ac3ca640
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896409654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1896409654
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2228809880
Short name T148
Test name
Test status
Simulation time 38052706632 ps
CPU time 80.74 seconds
Started Jul 19 04:52:22 PM PDT 24
Finished Jul 19 04:53:45 PM PDT 24
Peak memory 219428 kb
Host smart-e2c7e033-4e00-4f30-bcb2-4f7c33a2afa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228809880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2228809880
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3373575125
Short name T45
Test name
Test status
Simulation time 12424174620 ps
CPU time 78.51 seconds
Started Jul 19 04:38:32 PM PDT 24
Finished Jul 19 04:40:00 PM PDT 24
Peak memory 218840 kb
Host smart-1cdeee86-b032-44cb-8c8e-91168ca66a42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373575125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3373575125
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2811104283
Short name T5
Test name
Test status
Simulation time 8938073797 ps
CPU time 25.4 seconds
Started Jul 19 04:52:56 PM PDT 24
Finished Jul 19 04:53:24 PM PDT 24
Peak memory 214396 kb
Host smart-89bd796a-552b-4b02-b8b8-2452dc2f5dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811104283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2811104283
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1674623015
Short name T8
Test name
Test status
Simulation time 5253519230 ps
CPU time 105.79 seconds
Started Jul 19 04:51:59 PM PDT 24
Finished Jul 19 04:53:47 PM PDT 24
Peak memory 236752 kb
Host smart-eea225b1-ac5c-4246-8b3a-cac9e24fd8b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674623015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1674623015
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2836617730
Short name T13
Test name
Test status
Simulation time 310356573 ps
CPU time 16.47 seconds
Started Jul 19 04:52:45 PM PDT 24
Finished Jul 19 04:53:03 PM PDT 24
Peak memory 214548 kb
Host smart-a6b6f211-61ff-439b-b152-885c7a1409c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836617730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2836617730
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.822978448
Short name T105
Test name
Test status
Simulation time 1812054820 ps
CPU time 73.43 seconds
Started Jul 19 04:38:18 PM PDT 24
Finished Jul 19 04:39:35 PM PDT 24
Peak memory 218768 kb
Host smart-eb0abac3-ba3d-4f1b-af43-e1ccc4ae92d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822978448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.822978448
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2303767936
Short name T76
Test name
Test status
Simulation time 346538296 ps
CPU time 4.12 seconds
Started Jul 19 04:37:56 PM PDT 24
Finished Jul 19 04:38:00 PM PDT 24
Peak memory 217500 kb
Host smart-52de29b1-28fe-4658-911e-5ffc612d584e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303767936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2303767936
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3393559418
Short name T114
Test name
Test status
Simulation time 197091916 ps
CPU time 6.22 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:53:19 PM PDT 24
Peak memory 211420 kb
Host smart-983aab36-f895-4a1c-9a7c-64ac3ced8c17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393559418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3393559418
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2714588341
Short name T51
Test name
Test status
Simulation time 174715222 ps
CPU time 4.37 seconds
Started Jul 19 04:52:55 PM PDT 24
Finished Jul 19 04:53:02 PM PDT 24
Peak memory 211304 kb
Host smart-43cf7473-dfde-4cb1-ab6b-008b5c8f9fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714588341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2714588341
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2896443015
Short name T4
Test name
Test status
Simulation time 1028927355 ps
CPU time 15.92 seconds
Started Jul 19 04:52:53 PM PDT 24
Finished Jul 19 04:53:11 PM PDT 24
Peak memory 211956 kb
Host smart-359b139d-4af2-41a2-ad04-8d1eff4545a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896443015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2896443015
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.199835249
Short name T35
Test name
Test status
Simulation time 173421479 ps
CPU time 9.63 seconds
Started Jul 19 04:51:59 PM PDT 24
Finished Jul 19 04:52:11 PM PDT 24
Peak memory 211928 kb
Host smart-fee8d64d-38f8-4c89-a509-57d22309ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199835249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.199835249
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1280633482
Short name T102
Test name
Test status
Simulation time 2858789188 ps
CPU time 43.46 seconds
Started Jul 19 04:38:20 PM PDT 24
Finished Jul 19 04:39:09 PM PDT 24
Peak memory 218772 kb
Host smart-883dfeee-da31-4185-91df-e0b6639fd621
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280633482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1280633482
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3333252494
Short name T47
Test name
Test status
Simulation time 13186024212 ps
CPU time 102.33 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:39:50 PM PDT 24
Peak memory 210720 kb
Host smart-dfe81635-c8d2-4b0d-9b34-ecb5b603e191
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333252494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3333252494
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3056770197
Short name T165
Test name
Test status
Simulation time 21013145729 ps
CPU time 208.58 seconds
Started Jul 19 04:52:38 PM PDT 24
Finished Jul 19 04:56:08 PM PDT 24
Peak memory 212616 kb
Host smart-378e9c5d-b2ac-48a4-94b9-f1ea27f17ab5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056770197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3056770197
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2089036847
Short name T79
Test name
Test status
Simulation time 15458722482 ps
CPU time 61.63 seconds
Started Jul 19 04:37:58 PM PDT 24
Finished Jul 19 04:39:00 PM PDT 24
Peak memory 217792 kb
Host smart-5e434e54-7d45-47f8-be37-f5b3541e2cd1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089036847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2089036847
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2418756179
Short name T108
Test name
Test status
Simulation time 5220803094 ps
CPU time 75.15 seconds
Started Jul 19 04:38:19 PM PDT 24
Finished Jul 19 04:39:38 PM PDT 24
Peak memory 212560 kb
Host smart-764e8afe-0dab-4b7d-9939-40d09ac10307
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418756179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2418756179
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2859896921
Short name T71
Test name
Test status
Simulation time 6688300397 ps
CPU time 47.07 seconds
Started Jul 19 04:37:53 PM PDT 24
Finished Jul 19 04:38:41 PM PDT 24
Peak memory 210728 kb
Host smart-76153f7e-ab3c-4e49-8c73-78c78fa7af0b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859896921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2859896921
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1446584541
Short name T95
Test name
Test status
Simulation time 2474660942 ps
CPU time 11.72 seconds
Started Jul 19 04:52:24 PM PDT 24
Finished Jul 19 04:52:39 PM PDT 24
Peak memory 211460 kb
Host smart-17e1f044-bd53-4c99-9edf-221bed19b29e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446584541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1446584541
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.942759733
Short name T16
Test name
Test status
Simulation time 233307561334 ps
CPU time 1300.88 seconds
Started Jul 19 04:52:33 PM PDT 24
Finished Jul 19 05:14:17 PM PDT 24
Peak memory 235864 kb
Host smart-62c5bc58-faab-4e04-b910-88d4f54ecf8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942759733 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.942759733
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3900118353
Short name T464
Test name
Test status
Simulation time 637856830 ps
CPU time 4.16 seconds
Started Jul 19 04:37:53 PM PDT 24
Finished Jul 19 04:37:58 PM PDT 24
Peak memory 217280 kb
Host smart-0675971f-a643-42f5-a548-f6cacde993e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900118353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3900118353
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.71842251
Short name T416
Test name
Test status
Simulation time 1515437859 ps
CPU time 13.21 seconds
Started Jul 19 04:37:45 PM PDT 24
Finished Jul 19 04:37:59 PM PDT 24
Peak memory 218184 kb
Host smart-74439398-3f47-45d0-98c0-3e5e6b3e8531
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71842251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_ba
sh.71842251
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3790604490
Short name T459
Test name
Test status
Simulation time 820310139 ps
CPU time 12.03 seconds
Started Jul 19 04:37:51 PM PDT 24
Finished Jul 19 04:38:03 PM PDT 24
Peak memory 218444 kb
Host smart-ab9acd1b-c6b0-4619-b71d-718b36d6e895
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790604490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3790604490
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3707745360
Short name T372
Test name
Test status
Simulation time 13352055734 ps
CPU time 16.85 seconds
Started Jul 19 04:37:53 PM PDT 24
Finished Jul 19 04:38:11 PM PDT 24
Peak memory 215596 kb
Host smart-86b98563-9fcc-4fcd-b2ce-7e16bb9d03be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707745360 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3707745360
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1982590872
Short name T445
Test name
Test status
Simulation time 3161501641 ps
CPU time 12.56 seconds
Started Jul 19 04:37:48 PM PDT 24
Finished Jul 19 04:38:01 PM PDT 24
Peak memory 210536 kb
Host smart-5911d5c5-3d05-433b-a91f-4ed86f5254ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982590872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1982590872
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3988892096
Short name T422
Test name
Test status
Simulation time 3220940063 ps
CPU time 8.74 seconds
Started Jul 19 04:37:51 PM PDT 24
Finished Jul 19 04:38:00 PM PDT 24
Peak memory 210464 kb
Host smart-8a3d124f-4111-4225-b54d-f96eae6d99d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988892096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3988892096
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.932312205
Short name T439
Test name
Test status
Simulation time 347084787 ps
CPU time 4.21 seconds
Started Jul 19 04:37:47 PM PDT 24
Finished Jul 19 04:37:53 PM PDT 24
Peak memory 210316 kb
Host smart-346515a3-eec0-4e1f-ab74-6b3864e592ed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932312205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
932312205
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2268209096
Short name T456
Test name
Test status
Simulation time 1098563204 ps
CPU time 8.1 seconds
Started Jul 19 04:37:53 PM PDT 24
Finished Jul 19 04:38:02 PM PDT 24
Peak memory 210620 kb
Host smart-195294fb-4bf3-4cef-9b57-1505e7ffa879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268209096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2268209096
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2382949758
Short name T421
Test name
Test status
Simulation time 871582508 ps
CPU time 13.18 seconds
Started Jul 19 04:37:44 PM PDT 24
Finished Jul 19 04:37:58 PM PDT 24
Peak memory 218776 kb
Host smart-7ded2588-71d0-486c-af10-394bc7e2e4ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382949758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2382949758
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1338519531
Short name T104
Test name
Test status
Simulation time 524782460 ps
CPU time 75.43 seconds
Started Jul 19 04:37:48 PM PDT 24
Finished Jul 19 04:39:04 PM PDT 24
Peak memory 211968 kb
Host smart-4aa6c98d-c800-4b3f-9c55-11afc92659b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338519531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1338519531
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1944339716
Short name T97
Test name
Test status
Simulation time 7401823871 ps
CPU time 11.84 seconds
Started Jul 19 04:37:48 PM PDT 24
Finished Jul 19 04:38:00 PM PDT 24
Peak memory 218636 kb
Host smart-5dfeffd1-e892-4141-a623-e00176a222d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944339716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1944339716
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1192892509
Short name T96
Test name
Test status
Simulation time 671615724 ps
CPU time 7.38 seconds
Started Jul 19 04:37:55 PM PDT 24
Finished Jul 19 04:38:03 PM PDT 24
Peak memory 218600 kb
Host smart-16a3b32f-95a7-4a32-a8b6-c93a42f49cd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192892509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1192892509
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2390286020
Short name T371
Test name
Test status
Simulation time 1635317521 ps
CPU time 9.42 seconds
Started Jul 19 04:37:55 PM PDT 24
Finished Jul 19 04:38:05 PM PDT 24
Peak memory 218708 kb
Host smart-f32a15ca-2489-427f-96ae-476c6673c37d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390286020 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2390286020
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2782358475
Short name T395
Test name
Test status
Simulation time 1945259131 ps
CPU time 6.83 seconds
Started Jul 19 04:37:50 PM PDT 24
Finished Jul 19 04:37:57 PM PDT 24
Peak memory 210468 kb
Host smart-e9b3292c-a345-4e82-8332-92d6ca78b8a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782358475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2782358475
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2068523057
Short name T466
Test name
Test status
Simulation time 817009148 ps
CPU time 9.14 seconds
Started Jul 19 04:37:55 PM PDT 24
Finished Jul 19 04:38:05 PM PDT 24
Peak memory 210324 kb
Host smart-2b848c2e-78ca-49ba-a1c1-b91b384aa98f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068523057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2068523057
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1490908539
Short name T424
Test name
Test status
Simulation time 346759252 ps
CPU time 4.01 seconds
Started Jul 19 04:37:45 PM PDT 24
Finished Jul 19 04:37:50 PM PDT 24
Peak memory 210376 kb
Host smart-2522dc9e-9ee0-4fee-951f-4969f8dbf742
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490908539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1490908539
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2724290857
Short name T415
Test name
Test status
Simulation time 5581917872 ps
CPU time 48.29 seconds
Started Jul 19 04:37:50 PM PDT 24
Finished Jul 19 04:38:40 PM PDT 24
Peak memory 210732 kb
Host smart-82dd24c1-1de7-4c1b-8e60-6e06fac09210
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724290857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2724290857
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3625403582
Short name T407
Test name
Test status
Simulation time 170579418 ps
CPU time 5.38 seconds
Started Jul 19 04:37:58 PM PDT 24
Finished Jul 19 04:38:05 PM PDT 24
Peak memory 210532 kb
Host smart-72f8ba7c-d243-4a35-b32d-b6d51af2cc9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625403582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3625403582
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2806776778
Short name T447
Test name
Test status
Simulation time 6667087262 ps
CPU time 17.94 seconds
Started Jul 19 04:37:53 PM PDT 24
Finished Jul 19 04:38:12 PM PDT 24
Peak memory 218884 kb
Host smart-8a8b26a1-445a-4536-969d-fa1d8fbe1c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806776778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2806776778
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3931331914
Short name T103
Test name
Test status
Simulation time 1141237345 ps
CPU time 72.01 seconds
Started Jul 19 04:37:52 PM PDT 24
Finished Jul 19 04:39:05 PM PDT 24
Peak memory 211904 kb
Host smart-323ea83d-88bb-4a85-9c28-88efefb08987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931331914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3931331914
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2424975796
Short name T411
Test name
Test status
Simulation time 1559864151 ps
CPU time 13.76 seconds
Started Jul 19 04:38:04 PM PDT 24
Finished Jul 19 04:38:22 PM PDT 24
Peak memory 218856 kb
Host smart-70b57906-43c9-484d-b691-673ea258eae7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424975796 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2424975796
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2979386623
Short name T451
Test name
Test status
Simulation time 2949944867 ps
CPU time 9.15 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:15 PM PDT 24
Peak memory 210520 kb
Host smart-38830008-a54a-4e89-82a2-213e8a4a0179
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979386623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2979386623
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3234478447
Short name T428
Test name
Test status
Simulation time 1057699004 ps
CPU time 27.04 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:33 PM PDT 24
Peak memory 210592 kb
Host smart-89252e3e-80f2-4474-9bbc-dd05f5f6ad1a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234478447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3234478447
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4108900564
Short name T57
Test name
Test status
Simulation time 1734097247 ps
CPU time 14.47 seconds
Started Jul 19 04:38:00 PM PDT 24
Finished Jul 19 04:38:17 PM PDT 24
Peak memory 218704 kb
Host smart-510f7703-32b6-4a7e-b985-a29ca457f1f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108900564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4108900564
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3906221055
Short name T379
Test name
Test status
Simulation time 3532320571 ps
CPU time 11.5 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:19 PM PDT 24
Peak memory 218852 kb
Host smart-d5a93efa-e487-403e-a7e2-a473985a9b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906221055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3906221055
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3147332869
Short name T110
Test name
Test status
Simulation time 13922392767 ps
CPU time 74.61 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:39:22 PM PDT 24
Peak memory 218808 kb
Host smart-90f6c7b2-8bf9-4fc5-b394-8c4721f2f6f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147332869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3147332869
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3979493103
Short name T449
Test name
Test status
Simulation time 1038482085 ps
CPU time 6.1 seconds
Started Jul 19 04:38:06 PM PDT 24
Finished Jul 19 04:38:15 PM PDT 24
Peak memory 211592 kb
Host smart-e1066a6c-87b9-4ed2-a8d0-7f835ec75cac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979493103 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3979493103
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1634692194
Short name T402
Test name
Test status
Simulation time 1471408929 ps
CPU time 12.58 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:17 PM PDT 24
Peak memory 210452 kb
Host smart-33d31ce5-a897-4b93-b06f-a6ab9895aa4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634692194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1634692194
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2132981249
Short name T80
Test name
Test status
Simulation time 3289300812 ps
CPU time 50.11 seconds
Started Jul 19 04:38:01 PM PDT 24
Finished Jul 19 04:38:55 PM PDT 24
Peak memory 210752 kb
Host smart-8d6bd290-faae-456b-8a80-fcceed2c4511
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132981249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2132981249
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.50871847
Short name T93
Test name
Test status
Simulation time 14779050339 ps
CPU time 17.99 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:25 PM PDT 24
Peak memory 210944 kb
Host smart-9bb11e92-9ac8-4f5d-bf41-47fcbf839c67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50871847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ct
rl_same_csr_outstanding.50871847
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.131679481
Short name T384
Test name
Test status
Simulation time 2071392235 ps
CPU time 19.55 seconds
Started Jul 19 04:38:04 PM PDT 24
Finished Jul 19 04:38:27 PM PDT 24
Peak memory 218796 kb
Host smart-bda0f87a-f6b7-4e96-814d-f8da4a91310c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131679481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.131679481
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4062707663
Short name T112
Test name
Test status
Simulation time 3213761448 ps
CPU time 43.84 seconds
Started Jul 19 04:38:08 PM PDT 24
Finished Jul 19 04:38:54 PM PDT 24
Peak memory 218804 kb
Host smart-78b8875f-58cf-4b11-ac90-e2f00b2fe52b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062707663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4062707663
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2428248962
Short name T383
Test name
Test status
Simulation time 1544074345 ps
CPU time 9.12 seconds
Started Jul 19 04:38:24 PM PDT 24
Finished Jul 19 04:38:38 PM PDT 24
Peak memory 218780 kb
Host smart-6580723f-f4d4-41d9-bc2f-f3e1ffee6a11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428248962 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2428248962
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2652081410
Short name T55
Test name
Test status
Simulation time 1077111908 ps
CPU time 10.3 seconds
Started Jul 19 04:38:19 PM PDT 24
Finished Jul 19 04:38:33 PM PDT 24
Peak memory 210448 kb
Host smart-a3621220-d973-4af9-95d5-94154c15ac49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652081410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2652081410
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3440695399
Short name T73
Test name
Test status
Simulation time 3468919881 ps
CPU time 39.37 seconds
Started Jul 19 04:38:05 PM PDT 24
Finished Jul 19 04:38:48 PM PDT 24
Peak memory 210588 kb
Host smart-8d2b4b0c-a33a-4b62-ab80-db1b44ebd53e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440695399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3440695399
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2223136678
Short name T442
Test name
Test status
Simulation time 2133539197 ps
CPU time 16.84 seconds
Started Jul 19 04:38:17 PM PDT 24
Finished Jul 19 04:38:34 PM PDT 24
Peak memory 210576 kb
Host smart-383c308c-56cc-45b6-97c2-7c50ed2c7234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223136678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2223136678
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3864911120
Short name T390
Test name
Test status
Simulation time 690924109 ps
CPU time 8.84 seconds
Started Jul 19 04:38:06 PM PDT 24
Finished Jul 19 04:38:18 PM PDT 24
Peak memory 218788 kb
Host smart-a9efc58c-f076-4bcf-b8fc-655d88448c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864911120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3864911120
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3825667695
Short name T448
Test name
Test status
Simulation time 1777496143 ps
CPU time 14.03 seconds
Started Jul 19 04:38:14 PM PDT 24
Finished Jul 19 04:38:29 PM PDT 24
Peak memory 215320 kb
Host smart-7b15d3e6-c4de-45b2-9f7b-fed12fa3d75d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825667695 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3825667695
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3630079010
Short name T70
Test name
Test status
Simulation time 1094184577 ps
CPU time 7.54 seconds
Started Jul 19 04:38:11 PM PDT 24
Finished Jul 19 04:38:19 PM PDT 24
Peak memory 210504 kb
Host smart-19c3abee-ca2c-4985-8330-da3f538557fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630079010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3630079010
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3895103171
Short name T455
Test name
Test status
Simulation time 9056728915 ps
CPU time 42.61 seconds
Started Jul 19 04:38:18 PM PDT 24
Finished Jul 19 04:39:03 PM PDT 24
Peak memory 210648 kb
Host smart-e5a1b43c-0cbf-4943-b0fa-cc59b9fa8168
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895103171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3895103171
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2613203735
Short name T60
Test name
Test status
Simulation time 492753351 ps
CPU time 6.06 seconds
Started Jul 19 04:38:26 PM PDT 24
Finished Jul 19 04:38:38 PM PDT 24
Peak memory 218080 kb
Host smart-e46a38cc-2ffc-42aa-bb62-282d643974bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613203735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2613203735
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2267830601
Short name T368
Test name
Test status
Simulation time 7432311064 ps
CPU time 15.93 seconds
Started Jul 19 04:38:23 PM PDT 24
Finished Jul 19 04:38:51 PM PDT 24
Peak memory 218892 kb
Host smart-48edd3dc-59d4-43f5-a66d-26ed955ca303
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267830601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2267830601
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.134910230
Short name T391
Test name
Test status
Simulation time 6321277709 ps
CPU time 71.43 seconds
Started Jul 19 04:38:11 PM PDT 24
Finished Jul 19 04:39:23 PM PDT 24
Peak memory 211480 kb
Host smart-1079b42c-4fe5-4160-a30a-b4c6e32062c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134910230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.134910230
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3024648981
Short name T382
Test name
Test status
Simulation time 1695932302 ps
CPU time 13.82 seconds
Started Jul 19 04:38:19 PM PDT 24
Finished Jul 19 04:38:37 PM PDT 24
Peak memory 218948 kb
Host smart-4fcec53c-8deb-4c44-9386-78e446a681a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024648981 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3024648981
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1302561854
Short name T394
Test name
Test status
Simulation time 5354748370 ps
CPU time 11.97 seconds
Started Jul 19 04:38:11 PM PDT 24
Finished Jul 19 04:38:23 PM PDT 24
Peak memory 218864 kb
Host smart-1ab86122-e365-4832-bca2-22e5ad783aca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302561854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1302561854
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.597605625
Short name T425
Test name
Test status
Simulation time 715880567 ps
CPU time 23.44 seconds
Started Jul 19 04:38:23 PM PDT 24
Finished Jul 19 04:38:51 PM PDT 24
Peak memory 210592 kb
Host smart-dd3d24e2-6126-412b-ac29-8d6e2481a8a2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597605625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.597605625
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3121401654
Short name T405
Test name
Test status
Simulation time 1419494882 ps
CPU time 12.23 seconds
Started Jul 19 04:38:21 PM PDT 24
Finished Jul 19 04:38:37 PM PDT 24
Peak memory 210532 kb
Host smart-aa2e8432-5996-4d28-9152-d8588c15f82c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121401654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3121401654
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4156612685
Short name T393
Test name
Test status
Simulation time 900517294 ps
CPU time 11.14 seconds
Started Jul 19 04:38:19 PM PDT 24
Finished Jul 19 04:38:34 PM PDT 24
Peak memory 218800 kb
Host smart-2c537827-1b5f-4acb-8ffe-514f737441c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156612685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4156612685
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2213504211
Short name T461
Test name
Test status
Simulation time 3793169197 ps
CPU time 15.14 seconds
Started Jul 19 04:38:24 PM PDT 24
Finished Jul 19 04:38:44 PM PDT 24
Peak memory 218872 kb
Host smart-ce7e9829-4b49-4f01-bb60-914b12e6d6a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213504211 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2213504211
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1475583333
Short name T410
Test name
Test status
Simulation time 10270223011 ps
CPU time 11.62 seconds
Started Jul 19 04:38:18 PM PDT 24
Finished Jul 19 04:38:32 PM PDT 24
Peak memory 210592 kb
Host smart-d24e45a4-09a0-4709-a9bd-03f682b8e8bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475583333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1475583333
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3451933263
Short name T420
Test name
Test status
Simulation time 15895577934 ps
CPU time 41.32 seconds
Started Jul 19 04:38:19 PM PDT 24
Finished Jul 19 04:39:05 PM PDT 24
Peak memory 210644 kb
Host smart-d9ceed57-cade-4edc-95ff-e60cb0695211
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451933263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3451933263
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.518162108
Short name T413
Test name
Test status
Simulation time 2270466197 ps
CPU time 6.95 seconds
Started Jul 19 04:38:18 PM PDT 24
Finished Jul 19 04:38:26 PM PDT 24
Peak memory 217568 kb
Host smart-dbd17159-e3d9-4158-a7b1-24636ff8e3d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518162108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.518162108
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.531699087
Short name T406
Test name
Test status
Simulation time 5758913609 ps
CPU time 10.15 seconds
Started Jul 19 04:38:17 PM PDT 24
Finished Jul 19 04:38:28 PM PDT 24
Peak memory 218888 kb
Host smart-14c2dcd9-80cf-4b56-86da-d8f1c580b160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531699087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.531699087
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1042278887
Short name T426
Test name
Test status
Simulation time 341590437 ps
CPU time 69.56 seconds
Started Jul 19 04:38:12 PM PDT 24
Finished Jul 19 04:39:23 PM PDT 24
Peak memory 212204 kb
Host smart-75ef282a-ced8-4c9a-b44c-c977db350f48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042278887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1042278887
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3810280152
Short name T376
Test name
Test status
Simulation time 1616026525 ps
CPU time 13.97 seconds
Started Jul 19 04:38:17 PM PDT 24
Finished Jul 19 04:38:32 PM PDT 24
Peak memory 216100 kb
Host smart-2e3d4deb-05a9-4207-8298-ce0d28e6036b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810280152 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3810280152
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.69628485
Short name T457
Test name
Test status
Simulation time 2605541011 ps
CPU time 11.9 seconds
Started Jul 19 04:38:19 PM PDT 24
Finished Jul 19 04:38:34 PM PDT 24
Peak memory 210532 kb
Host smart-f39b7e36-f15e-4e2e-a806-ac88e41caa63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69628485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.69628485
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2593732821
Short name T418
Test name
Test status
Simulation time 20472181148 ps
CPU time 47.64 seconds
Started Jul 19 04:38:19 PM PDT 24
Finished Jul 19 04:39:10 PM PDT 24
Peak memory 210664 kb
Host smart-73a27402-e694-4f94-993b-2891103a89f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593732821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2593732821
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2267865418
Short name T59
Test name
Test status
Simulation time 347253246 ps
CPU time 4.31 seconds
Started Jul 19 04:38:23 PM PDT 24
Finished Jul 19 04:38:32 PM PDT 24
Peak memory 217872 kb
Host smart-e76814da-541c-4605-8895-173c715c8ed3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267865418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2267865418
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1807104898
Short name T414
Test name
Test status
Simulation time 1808573671 ps
CPU time 16.72 seconds
Started Jul 19 04:38:20 PM PDT 24
Finished Jul 19 04:38:41 PM PDT 24
Peak memory 218756 kb
Host smart-2e8887d8-58a3-415a-8df8-31e6b33a2161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807104898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1807104898
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1547842856
Short name T453
Test name
Test status
Simulation time 409633083 ps
CPU time 5.04 seconds
Started Jul 19 04:38:28 PM PDT 24
Finished Jul 19 04:38:40 PM PDT 24
Peak memory 218688 kb
Host smart-c8e8de82-625e-4bc9-a0cf-315280c86f66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547842856 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1547842856
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.801624665
Short name T99
Test name
Test status
Simulation time 743646628 ps
CPU time 6.68 seconds
Started Jul 19 04:38:21 PM PDT 24
Finished Jul 19 04:38:32 PM PDT 24
Peak memory 217228 kb
Host smart-d2e79524-b931-4e61-a78d-ad2627544271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801624665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.801624665
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3136164814
Short name T61
Test name
Test status
Simulation time 28032216475 ps
CPU time 57.84 seconds
Started Jul 19 04:38:19 PM PDT 24
Finished Jul 19 04:39:21 PM PDT 24
Peak memory 210664 kb
Host smart-f95b5a7d-bf85-4774-8450-ad67a725e5ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136164814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3136164814
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4182444335
Short name T92
Test name
Test status
Simulation time 6531568838 ps
CPU time 13.24 seconds
Started Jul 19 04:38:18 PM PDT 24
Finished Jul 19 04:38:33 PM PDT 24
Peak memory 210708 kb
Host smart-2ac01f93-5296-4e85-aeee-430b4287ed4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182444335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4182444335
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.922368235
Short name T409
Test name
Test status
Simulation time 2082717665 ps
CPU time 18.65 seconds
Started Jul 19 04:38:20 PM PDT 24
Finished Jul 19 04:38:43 PM PDT 24
Peak memory 218752 kb
Host smart-a9b6e8ca-8ca8-428c-9949-21b9fbb2fabd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922368235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.922368235
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.49648505
Short name T111
Test name
Test status
Simulation time 1742286056 ps
CPU time 45.54 seconds
Started Jul 19 04:38:28 PM PDT 24
Finished Jul 19 04:39:21 PM PDT 24
Peak memory 218744 kb
Host smart-9c6975ca-25d4-4d10-871c-a5e3708d3c10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49648505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_int
g_err.49648505
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4253477649
Short name T375
Test name
Test status
Simulation time 1479549094 ps
CPU time 14.09 seconds
Started Jul 19 04:38:30 PM PDT 24
Finished Jul 19 04:38:52 PM PDT 24
Peak memory 218704 kb
Host smart-91acf8bf-86ec-42fb-822e-a2a38057a083
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253477649 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4253477649
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2948283041
Short name T417
Test name
Test status
Simulation time 7072073942 ps
CPU time 15.83 seconds
Started Jul 19 04:38:28 PM PDT 24
Finished Jul 19 04:38:51 PM PDT 24
Peak memory 210724 kb
Host smart-e09a9184-2387-46ad-ad14-b5cab6167d73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948283041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2948283041
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.850503885
Short name T94
Test name
Test status
Simulation time 22065088721 ps
CPU time 75.32 seconds
Started Jul 19 04:38:28 PM PDT 24
Finished Jul 19 04:39:50 PM PDT 24
Peak memory 210732 kb
Host smart-7cc7699b-e361-415d-b79d-8cf549104e94
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850503885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.850503885
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1441592008
Short name T398
Test name
Test status
Simulation time 4231288741 ps
CPU time 15.35 seconds
Started Jul 19 04:38:27 PM PDT 24
Finished Jul 19 04:38:49 PM PDT 24
Peak memory 218776 kb
Host smart-40806baf-1c9e-4f81-ae3e-6043bdbe3242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441592008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1441592008
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1740506670
Short name T397
Test name
Test status
Simulation time 208907394 ps
CPU time 9.92 seconds
Started Jul 19 04:38:28 PM PDT 24
Finished Jul 19 04:38:45 PM PDT 24
Peak memory 215420 kb
Host smart-d334cf34-99de-4e55-95fb-0f72347afc76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740506670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1740506670
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3477900821
Short name T434
Test name
Test status
Simulation time 8160016556 ps
CPU time 16.92 seconds
Started Jul 19 04:38:19 PM PDT 24
Finished Jul 19 04:38:40 PM PDT 24
Peak memory 218904 kb
Host smart-de63c491-4d78-4d7a-a53e-158d06ab9efa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477900821 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3477900821
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.193318195
Short name T460
Test name
Test status
Simulation time 5563027456 ps
CPU time 12.17 seconds
Started Jul 19 04:38:28 PM PDT 24
Finished Jul 19 04:38:47 PM PDT 24
Peak memory 210652 kb
Host smart-3d443a2a-51c6-4b1a-adbf-f7d1c93a2b82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193318195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.193318195
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2431410253
Short name T63
Test name
Test status
Simulation time 6419635481 ps
CPU time 56.48 seconds
Started Jul 19 04:38:29 PM PDT 24
Finished Jul 19 04:39:33 PM PDT 24
Peak memory 210724 kb
Host smart-8924683b-e10e-4503-aa72-33cce5fc07c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431410253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2431410253
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.565921206
Short name T62
Test name
Test status
Simulation time 1147103766 ps
CPU time 11.06 seconds
Started Jul 19 04:38:18 PM PDT 24
Finished Jul 19 04:38:31 PM PDT 24
Peak memory 218724 kb
Host smart-48f83fb9-c6e8-4fb2-85f1-95eccb121bd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565921206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.565921206
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2896879724
Short name T370
Test name
Test status
Simulation time 3766363478 ps
CPU time 12.29 seconds
Started Jul 19 04:38:25 PM PDT 24
Finished Jul 19 04:38:42 PM PDT 24
Peak memory 218840 kb
Host smart-507831c1-5679-46bb-ae13-b85d23f5a10c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896879724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2896879724
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.394978849
Short name T107
Test name
Test status
Simulation time 202945108 ps
CPU time 38.22 seconds
Started Jul 19 04:38:20 PM PDT 24
Finished Jul 19 04:39:08 PM PDT 24
Peak memory 211848 kb
Host smart-54e7d0d8-e38a-4e03-8dec-17a6c1e3fdff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394978849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.394978849
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2272538502
Short name T385
Test name
Test status
Simulation time 511184052 ps
CPU time 6.25 seconds
Started Jul 19 04:38:01 PM PDT 24
Finished Jul 19 04:38:10 PM PDT 24
Peak memory 217488 kb
Host smart-e3dcd94a-5977-4bf0-a048-fbeb15ff3cc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272538502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2272538502
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.417154378
Short name T431
Test name
Test status
Simulation time 822719530 ps
CPU time 10.14 seconds
Started Jul 19 04:38:00 PM PDT 24
Finished Jul 19 04:38:11 PM PDT 24
Peak memory 210532 kb
Host smart-e0496f58-53f5-48ba-a539-9cb23d73ec21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417154378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.417154378
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1652596048
Short name T48
Test name
Test status
Simulation time 357007326 ps
CPU time 5.79 seconds
Started Jul 19 04:38:01 PM PDT 24
Finished Jul 19 04:38:10 PM PDT 24
Peak memory 217500 kb
Host smart-8c64c18d-6bec-4c1a-ac69-f504e5f3fb2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652596048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1652596048
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1019977165
Short name T441
Test name
Test status
Simulation time 1637478081 ps
CPU time 7.2 seconds
Started Jul 19 04:38:05 PM PDT 24
Finished Jul 19 04:38:16 PM PDT 24
Peak memory 218776 kb
Host smart-42e13767-fa6c-4178-942f-0f1f59c1c592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019977165 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1019977165
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.122219853
Short name T387
Test name
Test status
Simulation time 593054721 ps
CPU time 4.27 seconds
Started Jul 19 04:38:06 PM PDT 24
Finished Jul 19 04:38:13 PM PDT 24
Peak memory 210540 kb
Host smart-74211c86-61c4-48d3-a385-2e77152c51cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122219853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.122219853
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.13097840
Short name T367
Test name
Test status
Simulation time 5928625772 ps
CPU time 12.85 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:19 PM PDT 24
Peak memory 210516 kb
Host smart-ba2c74cd-dd0a-451f-8b06-57829c1432d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13097840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_
mem_partial_access.13097840
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.230211591
Short name T399
Test name
Test status
Simulation time 1422780276 ps
CPU time 12.15 seconds
Started Jul 19 04:38:00 PM PDT 24
Finished Jul 19 04:38:15 PM PDT 24
Peak memory 210372 kb
Host smart-9e9bae1e-36b3-4845-9ae2-b4d7106dcb81
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230211591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
230211591
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3093790375
Short name T404
Test name
Test status
Simulation time 15429131944 ps
CPU time 16.34 seconds
Started Jul 19 04:38:00 PM PDT 24
Finished Jul 19 04:38:18 PM PDT 24
Peak memory 218864 kb
Host smart-8b2dd928-6143-453d-ae23-d6e4e6957708
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093790375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3093790375
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.943863950
Short name T377
Test name
Test status
Simulation time 4117137116 ps
CPU time 15.23 seconds
Started Jul 19 04:38:06 PM PDT 24
Finished Jul 19 04:38:24 PM PDT 24
Peak memory 218828 kb
Host smart-a11d88c9-c56a-4c39-83dd-33c1fb3521f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943863950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.943863950
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.513386077
Short name T463
Test name
Test status
Simulation time 1660987346 ps
CPU time 73.77 seconds
Started Jul 19 04:38:04 PM PDT 24
Finished Jul 19 04:39:22 PM PDT 24
Peak memory 218716 kb
Host smart-26068d65-bf89-48c3-a47f-6609fe165595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513386077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.513386077
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.463076
Short name T429
Test name
Test status
Simulation time 6703279066 ps
CPU time 14.34 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:19 PM PDT 24
Peak memory 210596 kb
Host smart-ae4fd446-3e1c-4072-b0fc-c804f06de372
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.463076
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1646707778
Short name T438
Test name
Test status
Simulation time 85807696 ps
CPU time 4.55 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:10 PM PDT 24
Peak memory 210516 kb
Host smart-904d510b-4672-4810-a8a7-18cdb11bbc05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646707778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1646707778
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3477236224
Short name T378
Test name
Test status
Simulation time 2050594846 ps
CPU time 8.81 seconds
Started Jul 19 04:38:11 PM PDT 24
Finished Jul 19 04:38:20 PM PDT 24
Peak memory 210516 kb
Host smart-f4be0d73-2616-4542-bfdc-8cda6f5758a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477236224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3477236224
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2238295035
Short name T381
Test name
Test status
Simulation time 329711015 ps
CPU time 4.96 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:11 PM PDT 24
Peak memory 218752 kb
Host smart-0cc2dc59-36fd-4a69-a913-3b050715491c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238295035 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2238295035
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3384847956
Short name T454
Test name
Test status
Simulation time 1188647367 ps
CPU time 7.78 seconds
Started Jul 19 04:38:05 PM PDT 24
Finished Jul 19 04:38:17 PM PDT 24
Peak memory 210560 kb
Host smart-14976396-3cb2-4f23-b751-c0adc9b1c5ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384847956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3384847956
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2495065258
Short name T432
Test name
Test status
Simulation time 347820339 ps
CPU time 4.1 seconds
Started Jul 19 04:37:59 PM PDT 24
Finished Jul 19 04:38:05 PM PDT 24
Peak memory 210340 kb
Host smart-c2b16180-5e0c-43d7-ad8a-345d80707f21
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495065258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2495065258
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2473793070
Short name T388
Test name
Test status
Simulation time 519634712 ps
CPU time 4.18 seconds
Started Jul 19 04:38:00 PM PDT 24
Finished Jul 19 04:38:05 PM PDT 24
Peak memory 210348 kb
Host smart-5a3ca425-76d4-46b6-9107-cc69e2ff7863
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473793070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2473793070
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.408162486
Short name T427
Test name
Test status
Simulation time 20386909919 ps
CPU time 48.88 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:56 PM PDT 24
Peak memory 210708 kb
Host smart-dfbba2a5-c7ad-4dcc-9d69-b5e3855927a8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408162486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.408162486
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2872399572
Short name T58
Test name
Test status
Simulation time 12542183754 ps
CPU time 15 seconds
Started Jul 19 04:38:01 PM PDT 24
Finished Jul 19 04:38:19 PM PDT 24
Peak memory 210724 kb
Host smart-16dcdf0a-676e-486b-8f98-ca8d948913fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872399572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2872399572
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4005926770
Short name T450
Test name
Test status
Simulation time 2790694574 ps
CPU time 12.68 seconds
Started Jul 19 04:38:00 PM PDT 24
Finished Jul 19 04:38:14 PM PDT 24
Peak memory 218864 kb
Host smart-f7c2b59c-97f8-4218-91c7-2b237cbaa109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005926770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4005926770
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2755140666
Short name T401
Test name
Test status
Simulation time 369262635 ps
CPU time 38.1 seconds
Started Jul 19 04:37:59 PM PDT 24
Finished Jul 19 04:38:38 PM PDT 24
Peak memory 211836 kb
Host smart-00946b5c-2a20-440a-8e35-94db41229f42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755140666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2755140666
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2863630444
Short name T72
Test name
Test status
Simulation time 6459395360 ps
CPU time 13.89 seconds
Started Jul 19 04:38:08 PM PDT 24
Finished Jul 19 04:38:24 PM PDT 24
Peak memory 218784 kb
Host smart-9dc340d5-9b84-4c6e-8bd4-1ab48d78b589
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863630444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2863630444
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3860688238
Short name T380
Test name
Test status
Simulation time 1110361292 ps
CPU time 9.36 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:17 PM PDT 24
Peak memory 210472 kb
Host smart-d2ea547f-4f02-4641-9bab-6b86f87cedcb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860688238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3860688238
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1102257277
Short name T437
Test name
Test status
Simulation time 5611136766 ps
CPU time 13.38 seconds
Started Jul 19 04:38:01 PM PDT 24
Finished Jul 19 04:38:17 PM PDT 24
Peak memory 210752 kb
Host smart-06bac881-d6b5-4870-92ac-521ed8107ccd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102257277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1102257277
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1015235752
Short name T423
Test name
Test status
Simulation time 6355679425 ps
CPU time 14 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:21 PM PDT 24
Peak memory 218836 kb
Host smart-61dbcbc1-8797-4601-a6eb-b15b0fcd9b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015235752 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1015235752
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.418684583
Short name T98
Test name
Test status
Simulation time 2130158985 ps
CPU time 16.42 seconds
Started Jul 19 04:38:01 PM PDT 24
Finished Jul 19 04:38:20 PM PDT 24
Peak memory 210472 kb
Host smart-99407598-2756-4e77-b581-78e1573abd91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418684583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.418684583
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.672991788
Short name T440
Test name
Test status
Simulation time 1901674833 ps
CPU time 7.01 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:14 PM PDT 24
Peak memory 210392 kb
Host smart-6671f355-5c7b-493f-b91c-766cf7ef549f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672991788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.672991788
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1749171345
Short name T386
Test name
Test status
Simulation time 915023483 ps
CPU time 9.73 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:15 PM PDT 24
Peak memory 210388 kb
Host smart-328dd6c6-8492-4ad6-9305-2695ff2d09c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749171345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1749171345
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1185083286
Short name T78
Test name
Test status
Simulation time 6342606256 ps
CPU time 63.15 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:39:08 PM PDT 24
Peak memory 210732 kb
Host smart-5c5a046d-9d07-4f91-805d-fd9d29758313
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185083286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1185083286
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2393574450
Short name T56
Test name
Test status
Simulation time 16990056524 ps
CPU time 10.96 seconds
Started Jul 19 04:38:05 PM PDT 24
Finished Jul 19 04:38:20 PM PDT 24
Peak memory 210728 kb
Host smart-6a4570b6-54d9-4ec4-8e20-dfcb63797f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393574450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2393574450
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3315725359
Short name T419
Test name
Test status
Simulation time 130809980 ps
CPU time 9.43 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:17 PM PDT 24
Peak memory 218708 kb
Host smart-2c161818-c959-4d09-aff9-d2589c26fda8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315725359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3315725359
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.366321984
Short name T106
Test name
Test status
Simulation time 677969854 ps
CPU time 39.08 seconds
Started Jul 19 04:38:04 PM PDT 24
Finished Jul 19 04:38:47 PM PDT 24
Peak memory 211856 kb
Host smart-bd017513-8931-4f42-9b2d-af9591349829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366321984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.366321984
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.577146728
Short name T462
Test name
Test status
Simulation time 1310993867 ps
CPU time 11.71 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:19 PM PDT 24
Peak memory 218752 kb
Host smart-ac80482c-dbb7-4829-bb53-835e6ccb6ea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577146728 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.577146728
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1964422402
Short name T444
Test name
Test status
Simulation time 1567937834 ps
CPU time 9.42 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:15 PM PDT 24
Peak memory 210520 kb
Host smart-de8192e2-adfc-46ea-a6bb-ea19bdbdbb9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964422402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1964422402
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4049720961
Short name T77
Test name
Test status
Simulation time 12600509772 ps
CPU time 37.19 seconds
Started Jul 19 04:38:04 PM PDT 24
Finished Jul 19 04:38:46 PM PDT 24
Peak memory 210720 kb
Host smart-f1d6c38e-cae6-4e87-8f00-b29f9aa3a076
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049720961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4049720961
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3769228379
Short name T430
Test name
Test status
Simulation time 538836197 ps
CPU time 9.58 seconds
Started Jul 19 04:37:58 PM PDT 24
Finished Jul 19 04:38:17 PM PDT 24
Peak memory 210600 kb
Host smart-157e016c-6232-4927-941b-d75b41aebcc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769228379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3769228379
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3170763006
Short name T435
Test name
Test status
Simulation time 3585832176 ps
CPU time 13.21 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:19 PM PDT 24
Peak memory 218848 kb
Host smart-2a8ee570-349e-44a2-a851-8fde6494228f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170763006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3170763006
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2120665713
Short name T109
Test name
Test status
Simulation time 1338386039 ps
CPU time 73.11 seconds
Started Jul 19 04:38:06 PM PDT 24
Finished Jul 19 04:39:22 PM PDT 24
Peak memory 218740 kb
Host smart-c397fd37-75ba-4290-980c-8ba8520a29c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120665713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2120665713
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2235764843
Short name T408
Test name
Test status
Simulation time 1303683385 ps
CPU time 11.1 seconds
Started Jul 19 04:38:01 PM PDT 24
Finished Jul 19 04:38:15 PM PDT 24
Peak memory 218788 kb
Host smart-6025f63f-c2d7-4cd2-b313-655521fe1247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235764843 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2235764843
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.17966071
Short name T74
Test name
Test status
Simulation time 1431561439 ps
CPU time 12.42 seconds
Started Jul 19 04:38:07 PM PDT 24
Finished Jul 19 04:38:22 PM PDT 24
Peak memory 218544 kb
Host smart-56fca18a-c74f-47fd-80a7-abb627a32c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17966071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.17966071
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.876304765
Short name T465
Test name
Test status
Simulation time 96584812 ps
CPU time 6.1 seconds
Started Jul 19 04:38:00 PM PDT 24
Finished Jul 19 04:38:09 PM PDT 24
Peak memory 210560 kb
Host smart-86b8f509-231a-4e39-b891-5454b0b64231
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876304765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.876304765
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4079067306
Short name T369
Test name
Test status
Simulation time 5071896433 ps
CPU time 15.22 seconds
Started Jul 19 04:38:05 PM PDT 24
Finished Jul 19 04:38:24 PM PDT 24
Peak memory 219084 kb
Host smart-db7cf0fd-49fa-4022-979d-e2cd8380dd8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079067306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4079067306
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2012383243
Short name T44
Test name
Test status
Simulation time 6139956180 ps
CPU time 73.66 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:39:19 PM PDT 24
Peak memory 218864 kb
Host smart-f2af403b-2d79-4e5c-a0db-3e430ff006b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012383243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2012383243
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2882820418
Short name T389
Test name
Test status
Simulation time 1712182881 ps
CPU time 5.13 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:12 PM PDT 24
Peak memory 218824 kb
Host smart-4122b896-442c-44aa-a0c4-6bef6134be10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882820418 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2882820418
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1302643931
Short name T75
Test name
Test status
Simulation time 2420472137 ps
CPU time 14.67 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:20 PM PDT 24
Peak memory 210568 kb
Host smart-0f9fbc6b-a807-4909-a0a5-0dd21ce2f387
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302643931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1302643931
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2669822844
Short name T392
Test name
Test status
Simulation time 25973610124 ps
CPU time 53 seconds
Started Jul 19 04:38:04 PM PDT 24
Finished Jul 19 04:39:02 PM PDT 24
Peak memory 210740 kb
Host smart-f25068cb-8124-45e6-aafc-4adbac025e3c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669822844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2669822844
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3115698599
Short name T458
Test name
Test status
Simulation time 8542319431 ps
CPU time 15.52 seconds
Started Jul 19 04:38:04 PM PDT 24
Finished Jul 19 04:38:23 PM PDT 24
Peak memory 210704 kb
Host smart-360e55aa-fff6-4fa5-9114-5f877492e956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115698599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3115698599
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1360418471
Short name T403
Test name
Test status
Simulation time 4164669551 ps
CPU time 17.52 seconds
Started Jul 19 04:38:04 PM PDT 24
Finished Jul 19 04:38:25 PM PDT 24
Peak memory 218728 kb
Host smart-bb8c6f6b-e88b-4c84-b855-8a06feee506a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360418471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1360418471
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.217002884
Short name T433
Test name
Test status
Simulation time 4058631399 ps
CPU time 41.69 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:48 PM PDT 24
Peak memory 211944 kb
Host smart-3cbdd20f-c239-43cd-b5d4-7f2e04459b5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217002884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.217002884
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.978982856
Short name T446
Test name
Test status
Simulation time 19893378156 ps
CPU time 16.39 seconds
Started Jul 19 04:38:04 PM PDT 24
Finished Jul 19 04:38:25 PM PDT 24
Peak memory 218916 kb
Host smart-1ed2c5b3-d076-4a1f-9396-885b018e0f7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978982856 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.978982856
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.738838614
Short name T373
Test name
Test status
Simulation time 1630337410 ps
CPU time 14.27 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:19 PM PDT 24
Peak memory 218364 kb
Host smart-99c3d1a1-9b7d-404b-80a4-8e76b293e3c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738838614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.738838614
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4200771231
Short name T81
Test name
Test status
Simulation time 47580781220 ps
CPU time 46.93 seconds
Started Jul 19 04:38:12 PM PDT 24
Finished Jul 19 04:39:00 PM PDT 24
Peak memory 210832 kb
Host smart-fc212f06-99d2-44a3-b8b2-785c3f1760e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200771231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4200771231
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2990361716
Short name T396
Test name
Test status
Simulation time 7507883795 ps
CPU time 11.06 seconds
Started Jul 19 04:38:05 PM PDT 24
Finished Jul 19 04:38:20 PM PDT 24
Peak memory 211004 kb
Host smart-66f402b7-9aa4-4830-b06a-011f73534609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990361716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2990361716
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3347917288
Short name T436
Test name
Test status
Simulation time 2310267548 ps
CPU time 17.58 seconds
Started Jul 19 04:38:00 PM PDT 24
Finished Jul 19 04:38:20 PM PDT 24
Peak memory 218780 kb
Host smart-92eba000-59e1-4bec-a7f7-c47dd8fe6bc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347917288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3347917288
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.443187001
Short name T46
Test name
Test status
Simulation time 1875893593 ps
CPU time 77.11 seconds
Started Jul 19 04:38:00 PM PDT 24
Finished Jul 19 04:39:19 PM PDT 24
Peak memory 212028 kb
Host smart-805bbfad-c206-41fa-9ac1-25c8fdfc77af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443187001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.443187001
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2972074197
Short name T374
Test name
Test status
Simulation time 4661432407 ps
CPU time 13.62 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:20 PM PDT 24
Peak memory 218980 kb
Host smart-426c9605-e4be-4c68-9791-0a52451fc16a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972074197 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2972074197
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.309681165
Short name T100
Test name
Test status
Simulation time 89172940 ps
CPU time 4.31 seconds
Started Jul 19 04:38:04 PM PDT 24
Finished Jul 19 04:38:12 PM PDT 24
Peak memory 210468 kb
Host smart-d6064931-c6a8-4181-8ad9-096db984f9b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309681165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.309681165
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3770435746
Short name T412
Test name
Test status
Simulation time 4623813000 ps
CPU time 45.62 seconds
Started Jul 19 04:38:01 PM PDT 24
Finished Jul 19 04:38:49 PM PDT 24
Peak memory 210732 kb
Host smart-da1230ad-92a2-4ba3-b3ea-a8f54c6f0d67
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770435746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3770435746
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2645771172
Short name T452
Test name
Test status
Simulation time 6444048510 ps
CPU time 9.44 seconds
Started Jul 19 04:38:02 PM PDT 24
Finished Jul 19 04:38:14 PM PDT 24
Peak memory 218852 kb
Host smart-d79e751c-1774-4465-a7a1-4dc4081b1e8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645771172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2645771172
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.339585871
Short name T400
Test name
Test status
Simulation time 1899797314 ps
CPU time 17.74 seconds
Started Jul 19 04:38:08 PM PDT 24
Finished Jul 19 04:38:27 PM PDT 24
Peak memory 218800 kb
Host smart-96b89695-adf3-456a-b801-ba7dde58ec24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339585871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.339585871
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.27463171
Short name T443
Test name
Test status
Simulation time 1948952158 ps
CPU time 44.91 seconds
Started Jul 19 04:38:03 PM PDT 24
Finished Jul 19 04:38:52 PM PDT 24
Peak memory 218780 kb
Host smart-e6477b16-fc9c-4701-9f90-dc9c2a2d8fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27463171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg
_err.27463171
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2216519804
Short name T136
Test name
Test status
Simulation time 88844443 ps
CPU time 4.36 seconds
Started Jul 19 04:51:46 PM PDT 24
Finished Jul 19 04:51:53 PM PDT 24
Peak memory 211332 kb
Host smart-48eaf21d-b632-4520-b7ad-3f21f99d410d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216519804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2216519804
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2948490507
Short name T248
Test name
Test status
Simulation time 9956949024 ps
CPU time 113.22 seconds
Started Jul 19 04:51:45 PM PDT 24
Finished Jul 19 04:53:41 PM PDT 24
Peak memory 237800 kb
Host smart-196fc9fb-a594-4dcc-9da5-32b767dc1803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948490507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2948490507
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2575368217
Short name T172
Test name
Test status
Simulation time 4149095245 ps
CPU time 21.68 seconds
Started Jul 19 04:51:44 PM PDT 24
Finished Jul 19 04:52:08 PM PDT 24
Peak memory 212044 kb
Host smart-56f968ca-442d-40c8-b413-964ab4f0242b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575368217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2575368217
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.211951160
Short name T115
Test name
Test status
Simulation time 4305249376 ps
CPU time 11.61 seconds
Started Jul 19 04:51:43 PM PDT 24
Finished Jul 19 04:51:56 PM PDT 24
Peak memory 211548 kb
Host smart-71b1c01c-b922-4214-8003-3511dbe81069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211951160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.211951160
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.267981205
Short name T28
Test name
Test status
Simulation time 20784482005 ps
CPU time 104.5 seconds
Started Jul 19 04:51:46 PM PDT 24
Finished Jul 19 04:53:34 PM PDT 24
Peak memory 236920 kb
Host smart-76d1e10d-5596-4513-8c17-e20f37cfaf3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267981205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.267981205
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.545968991
Short name T11
Test name
Test status
Simulation time 2892291330 ps
CPU time 26.58 seconds
Started Jul 19 04:51:43 PM PDT 24
Finished Jul 19 04:52:10 PM PDT 24
Peak memory 213924 kb
Host smart-b909e071-b74c-4e93-847e-a4fe76ddbfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545968991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.545968991
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2122492907
Short name T268
Test name
Test status
Simulation time 11834935518 ps
CPU time 51.49 seconds
Started Jul 19 04:51:47 PM PDT 24
Finished Jul 19 04:52:41 PM PDT 24
Peak memory 219416 kb
Host smart-ef10ef74-4827-4b6d-9a3f-54a736a82f4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122492907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2122492907
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4093556734
Short name T133
Test name
Test status
Simulation time 85468696 ps
CPU time 4.39 seconds
Started Jul 19 04:51:59 PM PDT 24
Finished Jul 19 04:52:05 PM PDT 24
Peak memory 211380 kb
Host smart-97533f5b-d52a-4b36-9d96-19c6b43f9e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093556734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4093556734
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2320988217
Short name T29
Test name
Test status
Simulation time 5902722899 ps
CPU time 150.67 seconds
Started Jul 19 04:51:44 PM PDT 24
Finished Jul 19 04:54:18 PM PDT 24
Peak memory 234408 kb
Host smart-f1c993a4-147f-4897-9ae2-586549336423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320988217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2320988217
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1813765112
Short name T242
Test name
Test status
Simulation time 2984050271 ps
CPU time 10 seconds
Started Jul 19 04:51:46 PM PDT 24
Finished Jul 19 04:51:58 PM PDT 24
Peak memory 211448 kb
Host smart-5ab40109-fc62-4ee0-b13d-0deabd9272a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813765112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1813765112
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1959561914
Short name T27
Test name
Test status
Simulation time 10415384387 ps
CPU time 108.27 seconds
Started Jul 19 04:51:54 PM PDT 24
Finished Jul 19 04:53:44 PM PDT 24
Peak memory 238292 kb
Host smart-d8c480ea-b029-4fb3-8544-a7cc4f7cd2d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959561914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1959561914
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3850439977
Short name T183
Test name
Test status
Simulation time 1570594714 ps
CPU time 19.3 seconds
Started Jul 19 04:51:44 PM PDT 24
Finished Jul 19 04:52:06 PM PDT 24
Peak memory 212904 kb
Host smart-80aa6060-e534-4212-97b1-d5012ebf8447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850439977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3850439977
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3546182212
Short name T178
Test name
Test status
Simulation time 21019531950 ps
CPU time 53.57 seconds
Started Jul 19 04:51:44 PM PDT 24
Finished Jul 19 04:52:39 PM PDT 24
Peak memory 216660 kb
Host smart-e163ff76-9a94-49a7-9fbd-b1be7cff7fdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546182212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3546182212
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2521734679
Short name T203
Test name
Test status
Simulation time 85446536 ps
CPU time 4.23 seconds
Started Jul 19 04:52:24 PM PDT 24
Finished Jul 19 04:52:32 PM PDT 24
Peak memory 211356 kb
Host smart-aefec7f4-4879-48cc-ba8e-cc5abba8b2f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521734679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2521734679
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.938233657
Short name T319
Test name
Test status
Simulation time 90173837372 ps
CPU time 300.27 seconds
Started Jul 19 04:52:25 PM PDT 24
Finished Jul 19 04:57:29 PM PDT 24
Peak memory 228720 kb
Host smart-63c63e0f-1771-4dbe-ae52-7d6a94d1b46d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938233657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.938233657
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2547512308
Short name T308
Test name
Test status
Simulation time 1899916492 ps
CPU time 20.24 seconds
Started Jul 19 04:52:25 PM PDT 24
Finished Jul 19 04:52:49 PM PDT 24
Peak memory 211800 kb
Host smart-165f88b9-bd21-4434-b85f-349c5a4504ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547512308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2547512308
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.247951933
Short name T149
Test name
Test status
Simulation time 1834714104 ps
CPU time 14.64 seconds
Started Jul 19 04:52:23 PM PDT 24
Finished Jul 19 04:52:40 PM PDT 24
Peak memory 211408 kb
Host smart-c495fe9a-a33b-4e1b-9a88-545810076274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247951933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.247951933
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1851894948
Short name T338
Test name
Test status
Simulation time 9946197609 ps
CPU time 31.45 seconds
Started Jul 19 04:52:21 PM PDT 24
Finished Jul 19 04:52:53 PM PDT 24
Peak memory 214092 kb
Host smart-f3fb69f5-e237-472c-9a2e-19fd1c7d54c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851894948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1851894948
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1957258569
Short name T349
Test name
Test status
Simulation time 2617819009 ps
CPU time 12.9 seconds
Started Jul 19 04:52:23 PM PDT 24
Finished Jul 19 04:52:39 PM PDT 24
Peak memory 211392 kb
Host smart-048e3e9f-3ff7-447d-96c7-9365b532582c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957258569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1957258569
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2685315795
Short name T216
Test name
Test status
Simulation time 50515713964 ps
CPU time 457.57 seconds
Started Jul 19 04:52:24 PM PDT 24
Finished Jul 19 05:00:05 PM PDT 24
Peak memory 213108 kb
Host smart-1f64d806-92b1-4a65-97ec-ee3497ed1b63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685315795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2685315795
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.538077747
Short name T86
Test name
Test status
Simulation time 8847422398 ps
CPU time 34.98 seconds
Started Jul 19 04:52:24 PM PDT 24
Finished Jul 19 04:53:03 PM PDT 24
Peak memory 212152 kb
Host smart-be72f2ee-63aa-4699-b7b0-182c31d1211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538077747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.538077747
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2704722093
Short name T164
Test name
Test status
Simulation time 9989147393 ps
CPU time 34.95 seconds
Started Jul 19 04:52:21 PM PDT 24
Finished Jul 19 04:52:56 PM PDT 24
Peak memory 214368 kb
Host smart-68818346-509d-4ffe-a115-2613d9060b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704722093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2704722093
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.444724203
Short name T354
Test name
Test status
Simulation time 9368801780 ps
CPU time 34.32 seconds
Started Jul 19 04:52:26 PM PDT 24
Finished Jul 19 04:53:04 PM PDT 24
Peak memory 214404 kb
Host smart-e3e1f9d8-4e9e-4d26-9972-aee001cfc948
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444724203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.444724203
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3269284335
Short name T15
Test name
Test status
Simulation time 154966078981 ps
CPU time 2888.67 seconds
Started Jul 19 04:52:24 PM PDT 24
Finished Jul 19 05:40:37 PM PDT 24
Peak memory 241512 kb
Host smart-4010d064-914e-4e38-a5aa-f356f4ccaf8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269284335 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3269284335
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4091994187
Short name T134
Test name
Test status
Simulation time 6579812463 ps
CPU time 11.6 seconds
Started Jul 19 04:52:24 PM PDT 24
Finished Jul 19 04:52:40 PM PDT 24
Peak memory 211424 kb
Host smart-289fcaa5-9610-4e22-8a73-f7ad88d9931a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091994187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4091994187
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.979717833
Short name T31
Test name
Test status
Simulation time 87794058586 ps
CPU time 222.06 seconds
Started Jul 19 04:52:26 PM PDT 24
Finished Jul 19 04:56:12 PM PDT 24
Peak memory 238828 kb
Host smart-70bfb080-f452-41df-90de-fe00d87699a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979717833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.979717833
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.780136578
Short name T232
Test name
Test status
Simulation time 3195829229 ps
CPU time 28.88 seconds
Started Jul 19 04:52:24 PM PDT 24
Finished Jul 19 04:52:57 PM PDT 24
Peak memory 211916 kb
Host smart-550da2dc-e562-4431-a1b1-14495f6237cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780136578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.780136578
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1419271541
Short name T326
Test name
Test status
Simulation time 1504209179 ps
CPU time 14.09 seconds
Started Jul 19 04:52:23 PM PDT 24
Finished Jul 19 04:52:41 PM PDT 24
Peak memory 211368 kb
Host smart-97d28e58-8e2b-445f-b2b8-950b1950d50f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1419271541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1419271541
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4081886804
Short name T256
Test name
Test status
Simulation time 4786175425 ps
CPU time 17.29 seconds
Started Jul 19 04:52:25 PM PDT 24
Finished Jul 19 04:52:46 PM PDT 24
Peak memory 213416 kb
Host smart-d6cea979-caca-4c6b-8703-16e0cf8eaebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081886804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4081886804
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2918434341
Short name T158
Test name
Test status
Simulation time 203638820 ps
CPU time 13.67 seconds
Started Jul 19 04:52:23 PM PDT 24
Finished Jul 19 04:52:40 PM PDT 24
Peak memory 213940 kb
Host smart-30ee5de0-2b48-4b56-94fb-5f5569781c0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918434341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2918434341
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.919870511
Short name T150
Test name
Test status
Simulation time 3576910852 ps
CPU time 9.82 seconds
Started Jul 19 04:52:34 PM PDT 24
Finished Jul 19 04:52:47 PM PDT 24
Peak memory 211416 kb
Host smart-a34b0441-2b3a-4a66-b1dc-72e1b28a14cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919870511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.919870511
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2412501160
Short name T296
Test name
Test status
Simulation time 11975996303 ps
CPU time 88.28 seconds
Started Jul 19 04:52:26 PM PDT 24
Finished Jul 19 04:53:57 PM PDT 24
Peak memory 237436 kb
Host smart-83e8019e-d711-47b3-886e-81f601b1ebb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412501160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2412501160
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3667850142
Short name T305
Test name
Test status
Simulation time 3102088617 ps
CPU time 20.57 seconds
Started Jul 19 04:52:25 PM PDT 24
Finished Jul 19 04:52:49 PM PDT 24
Peak memory 212424 kb
Host smart-fcc2705b-f021-4353-a355-7269added85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667850142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3667850142
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1729210150
Short name T189
Test name
Test status
Simulation time 1005085726 ps
CPU time 11.25 seconds
Started Jul 19 04:52:26 PM PDT 24
Finished Jul 19 04:52:41 PM PDT 24
Peak memory 211320 kb
Host smart-440f9f36-65ec-4ce6-8335-365ba76e68f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729210150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1729210150
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.922688278
Short name T214
Test name
Test status
Simulation time 363680578 ps
CPU time 10.37 seconds
Started Jul 19 04:52:24 PM PDT 24
Finished Jul 19 04:52:39 PM PDT 24
Peak memory 213384 kb
Host smart-be326376-0d73-4dda-843e-77f94c342b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922688278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.922688278
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.309946312
Short name T153
Test name
Test status
Simulation time 7056112921 ps
CPU time 35.31 seconds
Started Jul 19 04:52:25 PM PDT 24
Finished Jul 19 04:53:04 PM PDT 24
Peak memory 216040 kb
Host smart-ac9b7d32-4e71-47cd-9098-114ce5064212
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309946312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.309946312
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.737985652
Short name T143
Test name
Test status
Simulation time 23062181633 ps
CPU time 16.09 seconds
Started Jul 19 04:52:32 PM PDT 24
Finished Jul 19 04:52:50 PM PDT 24
Peak memory 211416 kb
Host smart-f56280cf-4dda-4d0b-a34b-9b0bacb9658d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737985652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.737985652
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1155063611
Short name T113
Test name
Test status
Simulation time 575234731 ps
CPU time 56.75 seconds
Started Jul 19 04:52:34 PM PDT 24
Finished Jul 19 04:53:34 PM PDT 24
Peak memory 239528 kb
Host smart-e82ca93f-f76b-43f8-bf09-e55b887435b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155063611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1155063611
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2117940669
Short name T170
Test name
Test status
Simulation time 4360389389 ps
CPU time 21.85 seconds
Started Jul 19 04:52:33 PM PDT 24
Finished Jul 19 04:52:57 PM PDT 24
Peak memory 212204 kb
Host smart-781f77af-b593-45a2-9905-9c4d6e71baf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117940669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2117940669
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3169162163
Short name T363
Test name
Test status
Simulation time 6605211435 ps
CPU time 15.1 seconds
Started Jul 19 04:52:33 PM PDT 24
Finished Jul 19 04:52:51 PM PDT 24
Peak memory 211476 kb
Host smart-ab497715-fbe2-4fdd-acd7-2c7ed8abb107
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169162163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3169162163
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2803673714
Short name T140
Test name
Test status
Simulation time 2948751904 ps
CPU time 26.66 seconds
Started Jul 19 04:52:33 PM PDT 24
Finished Jul 19 04:53:03 PM PDT 24
Peak memory 213180 kb
Host smart-2b1c37a8-6264-4dd6-b3a6-ebbfcf9ff31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803673714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2803673714
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1798334826
Short name T266
Test name
Test status
Simulation time 286352509 ps
CPU time 19.25 seconds
Started Jul 19 04:52:33 PM PDT 24
Finished Jul 19 04:52:56 PM PDT 24
Peak memory 213656 kb
Host smart-1b21b4f8-7337-483e-be20-657718045cac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798334826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1798334826
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2644056634
Short name T152
Test name
Test status
Simulation time 1016628943 ps
CPU time 7.74 seconds
Started Jul 19 04:52:32 PM PDT 24
Finished Jul 19 04:52:42 PM PDT 24
Peak memory 211312 kb
Host smart-5b63627d-e3be-4213-86ee-9882077e7418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644056634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2644056634
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1724619177
Short name T244
Test name
Test status
Simulation time 31776910850 ps
CPU time 149.63 seconds
Started Jul 19 04:52:33 PM PDT 24
Finished Jul 19 04:55:06 PM PDT 24
Peak memory 228428 kb
Host smart-f93b063b-302d-4b50-a62e-043d0cbabc32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724619177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1724619177
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3045461379
Short name T179
Test name
Test status
Simulation time 664146982 ps
CPU time 9.74 seconds
Started Jul 19 04:52:31 PM PDT 24
Finished Jul 19 04:52:42 PM PDT 24
Peak memory 211900 kb
Host smart-b98276b7-0b35-40ef-82dd-f405378ccc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045461379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3045461379
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1423168840
Short name T208
Test name
Test status
Simulation time 3752372671 ps
CPU time 14.95 seconds
Started Jul 19 04:52:36 PM PDT 24
Finished Jul 19 04:52:54 PM PDT 24
Peak memory 211404 kb
Host smart-2fdc51e9-2aa0-4648-8ceb-929b5676a29f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423168840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1423168840
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3789225527
Short name T352
Test name
Test status
Simulation time 8731171160 ps
CPU time 34.37 seconds
Started Jul 19 04:52:33 PM PDT 24
Finished Jul 19 04:53:11 PM PDT 24
Peak memory 213692 kb
Host smart-87c9d6a0-0015-4ae0-8d11-83d6b1a6ba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789225527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3789225527
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2830715749
Short name T229
Test name
Test status
Simulation time 1732089303 ps
CPU time 15.06 seconds
Started Jul 19 04:52:35 PM PDT 24
Finished Jul 19 04:52:53 PM PDT 24
Peak memory 211824 kb
Host smart-92e878e6-4cd6-4ffa-b6e1-79133a2a6d87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830715749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2830715749
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.586132078
Short name T304
Test name
Test status
Simulation time 347710705 ps
CPU time 4.39 seconds
Started Jul 19 04:52:34 PM PDT 24
Finished Jul 19 04:52:42 PM PDT 24
Peak memory 211304 kb
Host smart-3950bd7c-67b5-4e29-b026-0c2d4ce95aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586132078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.586132078
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4246535659
Short name T309
Test name
Test status
Simulation time 30360930037 ps
CPU time 233.42 seconds
Started Jul 19 04:52:34 PM PDT 24
Finished Jul 19 04:56:31 PM PDT 24
Peak memory 237776 kb
Host smart-a5ce4d74-e2e4-4230-ae39-01a8d3b53c23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246535659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4246535659
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1527378036
Short name T366
Test name
Test status
Simulation time 3281546209 ps
CPU time 15.6 seconds
Started Jul 19 04:52:34 PM PDT 24
Finished Jul 19 04:52:53 PM PDT 24
Peak memory 212084 kb
Host smart-62c8d2b9-6310-41e6-a1de-8196a83b71d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527378036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1527378036
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2055062193
Short name T228
Test name
Test status
Simulation time 4224494719 ps
CPU time 17.41 seconds
Started Jul 19 04:52:34 PM PDT 24
Finished Jul 19 04:52:54 PM PDT 24
Peak memory 211456 kb
Host smart-58769a18-9651-4414-b359-5ffdcb13fdf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055062193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2055062193
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3122858459
Short name T258
Test name
Test status
Simulation time 4021146012 ps
CPU time 34.04 seconds
Started Jul 19 04:52:34 PM PDT 24
Finished Jul 19 04:53:11 PM PDT 24
Peak memory 213752 kb
Host smart-8c390115-4f99-4867-823f-fe6b718d04b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122858459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3122858459
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3759248409
Short name T174
Test name
Test status
Simulation time 4869006154 ps
CPU time 22.92 seconds
Started Jul 19 04:52:36 PM PDT 24
Finished Jul 19 04:53:01 PM PDT 24
Peak memory 217528 kb
Host smart-d5028c3c-cc53-4949-9e7f-2fc08df29358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759248409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3759248409
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3228643191
Short name T43
Test name
Test status
Simulation time 748870802852 ps
CPU time 2471.95 seconds
Started Jul 19 04:52:34 PM PDT 24
Finished Jul 19 05:33:49 PM PDT 24
Peak memory 238084 kb
Host smart-16a2412f-b1bb-4dd4-840d-5775e4e5da7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228643191 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.3228643191
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3643533
Short name T154
Test name
Test status
Simulation time 34496112493 ps
CPU time 17.41 seconds
Started Jul 19 04:52:36 PM PDT 24
Finished Jul 19 04:52:56 PM PDT 24
Peak memory 211360 kb
Host smart-0c307632-593d-4955-860f-32e2f5a8636d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3643533
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1446220980
Short name T298
Test name
Test status
Simulation time 1976779597 ps
CPU time 21.01 seconds
Started Jul 19 04:52:35 PM PDT 24
Finished Jul 19 04:52:59 PM PDT 24
Peak memory 212384 kb
Host smart-cc3ddfb8-a03d-4a9f-9efb-8daea6a52100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446220980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1446220980
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3481559927
Short name T192
Test name
Test status
Simulation time 1227930378 ps
CPU time 12.18 seconds
Started Jul 19 04:52:35 PM PDT 24
Finished Jul 19 04:52:50 PM PDT 24
Peak memory 211396 kb
Host smart-d9e2bdca-229a-45fd-8b36-5b8e9b8b6b4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481559927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3481559927
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2266767950
Short name T116
Test name
Test status
Simulation time 1618274382 ps
CPU time 10.33 seconds
Started Jul 19 04:52:32 PM PDT 24
Finished Jul 19 04:52:45 PM PDT 24
Peak memory 213592 kb
Host smart-c5e30dd4-455e-480e-90bc-48f812aa312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266767950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2266767950
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.974780262
Short name T289
Test name
Test status
Simulation time 1243876978 ps
CPU time 30.88 seconds
Started Jul 19 04:52:33 PM PDT 24
Finished Jul 19 04:53:07 PM PDT 24
Peak memory 215368 kb
Host smart-8bc87c25-4312-4107-8819-4f6dc0950f57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974780262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.974780262
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1247849788
Short name T17
Test name
Test status
Simulation time 161248124549 ps
CPU time 1604.39 seconds
Started Jul 19 04:52:32 PM PDT 24
Finished Jul 19 05:19:19 PM PDT 24
Peak memory 236572 kb
Host smart-b67e3683-ed72-4d45-96f8-458b39248ada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247849788 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1247849788
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1951163426
Short name T50
Test name
Test status
Simulation time 823713980 ps
CPU time 5.79 seconds
Started Jul 19 04:52:45 PM PDT 24
Finished Jul 19 04:52:52 PM PDT 24
Peak memory 211344 kb
Host smart-8c30b377-53bb-45ee-895e-39b5f14c42c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951163426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1951163426
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1260837134
Short name T281
Test name
Test status
Simulation time 4971506771 ps
CPU time 74.22 seconds
Started Jul 19 04:52:36 PM PDT 24
Finished Jul 19 04:53:53 PM PDT 24
Peak memory 233780 kb
Host smart-75d34ab0-059a-4d1d-90ac-72e0cda9f55d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260837134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1260837134
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2108892939
Short name T324
Test name
Test status
Simulation time 639239179 ps
CPU time 9.47 seconds
Started Jul 19 04:52:33 PM PDT 24
Finished Jul 19 04:52:45 PM PDT 24
Peak memory 211936 kb
Host smart-ac367446-a3fd-4b65-9fb5-c36470134ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108892939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2108892939
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.91406714
Short name T265
Test name
Test status
Simulation time 5593386722 ps
CPU time 13.46 seconds
Started Jul 19 04:52:33 PM PDT 24
Finished Jul 19 04:52:50 PM PDT 24
Peak memory 211460 kb
Host smart-733edb09-9647-4b71-997a-932e4303107d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91406714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.91406714
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1942941665
Short name T117
Test name
Test status
Simulation time 4755952964 ps
CPU time 23.3 seconds
Started Jul 19 04:52:40 PM PDT 24
Finished Jul 19 04:53:04 PM PDT 24
Peak memory 213384 kb
Host smart-72b157c2-b4a2-4a1b-9416-5512048df4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942941665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1942941665
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2161584525
Short name T132
Test name
Test status
Simulation time 252017305 ps
CPU time 13.55 seconds
Started Jul 19 04:52:35 PM PDT 24
Finished Jul 19 04:52:51 PM PDT 24
Peak memory 211292 kb
Host smart-147f33d9-8464-4fd8-81e3-2539e7495b20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161584525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2161584525
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2193163142
Short name T223
Test name
Test status
Simulation time 3205503751 ps
CPU time 13.97 seconds
Started Jul 19 04:52:44 PM PDT 24
Finished Jul 19 04:53:00 PM PDT 24
Peak memory 211312 kb
Host smart-ddfcb80f-a1e1-4aa4-938a-df2463011ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193163142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2193163142
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.299871531
Short name T198
Test name
Test status
Simulation time 19400718020 ps
CPU time 191.08 seconds
Started Jul 19 04:52:45 PM PDT 24
Finished Jul 19 04:55:57 PM PDT 24
Peak memory 238904 kb
Host smart-09020274-9d23-4998-96f1-d8d95f6c4c22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299871531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.299871531
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.7314172
Short name T263
Test name
Test status
Simulation time 1665838838 ps
CPU time 9.54 seconds
Started Jul 19 04:52:44 PM PDT 24
Finished Jul 19 04:52:55 PM PDT 24
Peak memory 212292 kb
Host smart-d44dc784-9107-4451-84c7-ddc19cd9548a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7314172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.7314172
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3874749328
Short name T142
Test name
Test status
Simulation time 1246598219 ps
CPU time 9.63 seconds
Started Jul 19 04:52:43 PM PDT 24
Finished Jul 19 04:52:54 PM PDT 24
Peak memory 211352 kb
Host smart-7fa400d7-5e6c-49bd-8791-ad9711834a7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874749328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3874749328
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2248356110
Short name T220
Test name
Test status
Simulation time 361660354 ps
CPU time 12.38 seconds
Started Jul 19 04:52:42 PM PDT 24
Finished Jul 19 04:52:55 PM PDT 24
Peak memory 213564 kb
Host smart-2c2bda34-2416-449d-a8b4-0cf4204adecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248356110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2248356110
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.896633381
Short name T187
Test name
Test status
Simulation time 26373811221 ps
CPU time 63 seconds
Started Jul 19 04:52:43 PM PDT 24
Finished Jul 19 04:53:47 PM PDT 24
Peak memory 217280 kb
Host smart-7b6ab076-5ed2-4427-ba99-b7730f1ef044
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896633381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.896633381
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.996562452
Short name T42
Test name
Test status
Simulation time 28294796497 ps
CPU time 1811.44 seconds
Started Jul 19 04:52:43 PM PDT 24
Finished Jul 19 05:22:55 PM PDT 24
Peak memory 234136 kb
Host smart-b1a108c7-1af6-4561-b417-888c2ecb500f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996562452 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.996562452
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2098806622
Short name T247
Test name
Test status
Simulation time 2064703444 ps
CPU time 15.87 seconds
Started Jul 19 04:51:53 PM PDT 24
Finished Jul 19 04:52:10 PM PDT 24
Peak memory 211296 kb
Host smart-159286df-660b-4334-8668-50d668252d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098806622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2098806622
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1439685231
Short name T36
Test name
Test status
Simulation time 3843624683 ps
CPU time 75.47 seconds
Started Jul 19 04:51:57 PM PDT 24
Finished Jul 19 04:53:14 PM PDT 24
Peak memory 233740 kb
Host smart-2be61f70-9679-42fd-ad21-b7f1e96ca033
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439685231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1439685231
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.118009081
Short name T318
Test name
Test status
Simulation time 11150402686 ps
CPU time 26.33 seconds
Started Jul 19 04:51:53 PM PDT 24
Finished Jul 19 04:52:20 PM PDT 24
Peak memory 212236 kb
Host smart-82c8723c-c10e-4550-be34-72db96476f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118009081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.118009081
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.337204062
Short name T215
Test name
Test status
Simulation time 1022896419 ps
CPU time 5.93 seconds
Started Jul 19 04:52:00 PM PDT 24
Finished Jul 19 04:52:07 PM PDT 24
Peak memory 211424 kb
Host smart-4c6b286b-72d5-40ea-96a4-9202c1275a5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337204062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.337204062
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.267605660
Short name T1
Test name
Test status
Simulation time 11506227396 ps
CPU time 108.6 seconds
Started Jul 19 04:51:53 PM PDT 24
Finished Jul 19 04:53:43 PM PDT 24
Peak memory 238364 kb
Host smart-aedf9846-8a53-4eb7-b2f7-2acc24cf96f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267605660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.267605660
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1207501262
Short name T118
Test name
Test status
Simulation time 919943841 ps
CPU time 10.18 seconds
Started Jul 19 04:51:54 PM PDT 24
Finished Jul 19 04:52:06 PM PDT 24
Peak memory 213088 kb
Host smart-11b47c69-9eec-4a2e-90df-6a66e0c5cf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207501262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1207501262
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4288007914
Short name T147
Test name
Test status
Simulation time 1469771234 ps
CPU time 25.71 seconds
Started Jul 19 04:51:58 PM PDT 24
Finished Jul 19 04:52:25 PM PDT 24
Peak memory 216112 kb
Host smart-e8c08138-ccbe-4b35-a259-6cc3e65039e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288007914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4288007914
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3401694388
Short name T12
Test name
Test status
Simulation time 84963457268 ps
CPU time 842.93 seconds
Started Jul 19 04:51:55 PM PDT 24
Finished Jul 19 05:06:00 PM PDT 24
Peak memory 235756 kb
Host smart-6061440c-dc84-4ca5-b9f0-f21205ab3524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401694388 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3401694388
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2076590718
Short name T127
Test name
Test status
Simulation time 12281902904 ps
CPU time 13.5 seconds
Started Jul 19 04:52:43 PM PDT 24
Finished Jul 19 04:52:58 PM PDT 24
Peak memory 211376 kb
Host smart-4bc6f837-192b-42d4-a23d-f924402c1aea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076590718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2076590718
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3439705060
Short name T238
Test name
Test status
Simulation time 132330503974 ps
CPU time 330.59 seconds
Started Jul 19 04:52:44 PM PDT 24
Finished Jul 19 04:58:15 PM PDT 24
Peak memory 212680 kb
Host smart-7bc9f2db-e09d-4a8a-82e0-e2694e3a4ef0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439705060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3439705060
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1905159644
Short name T162
Test name
Test status
Simulation time 3352134959 ps
CPU time 28.82 seconds
Started Jul 19 04:52:43 PM PDT 24
Finished Jul 19 04:53:13 PM PDT 24
Peak memory 211992 kb
Host smart-8fade4ab-fce8-4bb0-ac88-9c2a5b520757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905159644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1905159644
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2974472113
Short name T279
Test name
Test status
Simulation time 461187733 ps
CPU time 8.5 seconds
Started Jul 19 04:52:43 PM PDT 24
Finished Jul 19 04:52:53 PM PDT 24
Peak memory 211400 kb
Host smart-81f1c71f-10c2-4f3f-8330-5709aee7c504
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974472113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2974472113
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3547405422
Short name T87
Test name
Test status
Simulation time 4861384306 ps
CPU time 19.84 seconds
Started Jul 19 04:52:46 PM PDT 24
Finished Jul 19 04:53:07 PM PDT 24
Peak memory 214104 kb
Host smart-ea8f30ec-7873-47a2-8668-8ab673a533bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547405422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3547405422
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4001871982
Short name T159
Test name
Test status
Simulation time 940483461 ps
CPU time 28.54 seconds
Started Jul 19 04:52:43 PM PDT 24
Finished Jul 19 04:53:13 PM PDT 24
Peak memory 216128 kb
Host smart-a17ac7e9-2877-4e70-bca3-12fb8cd50f99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001871982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4001871982
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1839741961
Short name T18
Test name
Test status
Simulation time 215890767660 ps
CPU time 1587.78 seconds
Started Jul 19 04:52:44 PM PDT 24
Finished Jul 19 05:19:13 PM PDT 24
Peak memory 236548 kb
Host smart-09824193-8dda-48b9-b882-e3b63954ef16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839741961 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1839741961
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3846772063
Short name T250
Test name
Test status
Simulation time 102382613 ps
CPU time 4.23 seconds
Started Jul 19 04:52:46 PM PDT 24
Finished Jul 19 04:52:51 PM PDT 24
Peak memory 211368 kb
Host smart-d0441849-15f3-451a-a01d-034f5a75f9a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846772063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3846772063
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3715339501
Short name T249
Test name
Test status
Simulation time 48384123560 ps
CPU time 184.02 seconds
Started Jul 19 04:52:45 PM PDT 24
Finished Jul 19 04:55:50 PM PDT 24
Peak memory 237764 kb
Host smart-6f5c30a8-0168-4af9-b6f2-c429f4640bfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715339501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3715339501
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.642336396
Short name T33
Test name
Test status
Simulation time 20717321651 ps
CPU time 30.79 seconds
Started Jul 19 04:52:46 PM PDT 24
Finished Jul 19 04:53:18 PM PDT 24
Peak memory 211900 kb
Host smart-914d196a-6a62-423f-b5cb-51409e532664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642336396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.642336396
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.38990218
Short name T253
Test name
Test status
Simulation time 1112903320 ps
CPU time 12.01 seconds
Started Jul 19 04:52:46 PM PDT 24
Finished Jul 19 04:52:59 PM PDT 24
Peak memory 211376 kb
Host smart-7d7bf433-e294-45a1-835a-01e7236a4f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38990218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.38990218
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2900780804
Short name T53
Test name
Test status
Simulation time 2189484244 ps
CPU time 25.15 seconds
Started Jul 19 04:52:47 PM PDT 24
Finished Jul 19 04:53:13 PM PDT 24
Peak memory 213416 kb
Host smart-c8d517ff-961e-489d-8df2-cc8e520e4a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900780804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2900780804
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.742347581
Short name T91
Test name
Test status
Simulation time 2966986709 ps
CPU time 41.54 seconds
Started Jul 19 04:52:45 PM PDT 24
Finished Jul 19 04:53:27 PM PDT 24
Peak memory 216040 kb
Host smart-11cf1f24-8200-4af4-8575-68a1a437b976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742347581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.742347581
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1238559956
Short name T255
Test name
Test status
Simulation time 89187234 ps
CPU time 4.33 seconds
Started Jul 19 04:52:45 PM PDT 24
Finished Jul 19 04:52:51 PM PDT 24
Peak memory 211364 kb
Host smart-db6e67ed-4f6c-42b3-9956-80f80ef38b37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238559956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1238559956
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.534714547
Short name T325
Test name
Test status
Simulation time 282816551577 ps
CPU time 434.02 seconds
Started Jul 19 04:52:46 PM PDT 24
Finished Jul 19 05:00:02 PM PDT 24
Peak memory 234252 kb
Host smart-9fc097eb-c6c6-43ed-b050-62b15ac69fa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534714547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.534714547
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.178649686
Short name T231
Test name
Test status
Simulation time 10271129607 ps
CPU time 25.61 seconds
Started Jul 19 04:52:46 PM PDT 24
Finished Jul 19 04:53:13 PM PDT 24
Peak memory 212284 kb
Host smart-6886336c-c635-41fb-a0e5-6999a8e2f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178649686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.178649686
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.964635336
Short name T245
Test name
Test status
Simulation time 1424412660 ps
CPU time 13.21 seconds
Started Jul 19 04:52:47 PM PDT 24
Finished Jul 19 04:53:01 PM PDT 24
Peak memory 211388 kb
Host smart-8d749c99-9bb3-400d-8971-5f6eae94da88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964635336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.964635336
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1068244606
Short name T330
Test name
Test status
Simulation time 422836718 ps
CPU time 10.47 seconds
Started Jul 19 04:52:45 PM PDT 24
Finished Jul 19 04:52:57 PM PDT 24
Peak memory 213964 kb
Host smart-49268b9c-20c9-411d-ba3a-a7cb0fef4f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068244606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1068244606
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.762539191
Short name T240
Test name
Test status
Simulation time 37972310429 ps
CPU time 225.43 seconds
Started Jul 19 04:52:54 PM PDT 24
Finished Jul 19 04:56:41 PM PDT 24
Peak memory 234912 kb
Host smart-065a890d-f17a-49be-833b-625eba1dbd57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762539191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.762539191
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.94209235
Short name T336
Test name
Test status
Simulation time 11239446100 ps
CPU time 24.97 seconds
Started Jul 19 04:53:00 PM PDT 24
Finished Jul 19 04:53:28 PM PDT 24
Peak memory 211648 kb
Host smart-3951c40d-fda0-446c-bb22-d70759249893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94209235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.94209235
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1160505111
Short name T83
Test name
Test status
Simulation time 1077530935 ps
CPU time 8.24 seconds
Started Jul 19 04:52:53 PM PDT 24
Finished Jul 19 04:53:03 PM PDT 24
Peak memory 211340 kb
Host smart-0d422367-7b5c-43ba-8192-1d8901a4e4b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160505111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1160505111
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3164717537
Short name T243
Test name
Test status
Simulation time 5048905997 ps
CPU time 27.9 seconds
Started Jul 19 04:52:46 PM PDT 24
Finished Jul 19 04:53:15 PM PDT 24
Peak memory 213812 kb
Host smart-cf81bc3d-d27f-4f53-b11e-93521919ceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164717537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3164717537
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.203081479
Short name T307
Test name
Test status
Simulation time 813249934 ps
CPU time 14.96 seconds
Started Jul 19 04:52:53 PM PDT 24
Finished Jul 19 04:53:10 PM PDT 24
Peak memory 213332 kb
Host smart-6c8e4f02-35d6-4980-b634-f0020b5258cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203081479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.203081479
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3291877128
Short name T314
Test name
Test status
Simulation time 43629453473 ps
CPU time 1741.73 seconds
Started Jul 19 04:52:52 PM PDT 24
Finished Jul 19 05:21:55 PM PDT 24
Peak memory 235880 kb
Host smart-e13cd341-c7d5-4ac7-8054-06814cb804ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291877128 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3291877128
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3570762105
Short name T365
Test name
Test status
Simulation time 555831987 ps
CPU time 8.08 seconds
Started Jul 19 04:52:53 PM PDT 24
Finished Jul 19 04:53:03 PM PDT 24
Peak memory 211316 kb
Host smart-7caa45af-999a-466c-9a30-ba55cb98baf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570762105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3570762105
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2620523583
Short name T21
Test name
Test status
Simulation time 20259641170 ps
CPU time 162.63 seconds
Started Jul 19 04:52:55 PM PDT 24
Finished Jul 19 04:55:40 PM PDT 24
Peak memory 236768 kb
Host smart-eb5caf12-a316-4977-9c1b-5ff8e515575c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620523583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2620523583
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3889150555
Short name T313
Test name
Test status
Simulation time 3591250792 ps
CPU time 29.27 seconds
Started Jul 19 04:52:54 PM PDT 24
Finished Jul 19 04:53:26 PM PDT 24
Peak memory 211900 kb
Host smart-22ebf4ca-7fa4-4b2a-96d7-899ef4bd8295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889150555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3889150555
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1263740627
Short name T166
Test name
Test status
Simulation time 5485382329 ps
CPU time 14.15 seconds
Started Jul 19 04:52:54 PM PDT 24
Finished Jul 19 04:53:10 PM PDT 24
Peak memory 211432 kb
Host smart-c4af5254-c363-49f5-95fe-11d71d5b132e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1263740627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1263740627
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2779061755
Short name T66
Test name
Test status
Simulation time 2994618811 ps
CPU time 14.52 seconds
Started Jul 19 04:52:52 PM PDT 24
Finished Jul 19 04:53:07 PM PDT 24
Peak memory 214032 kb
Host smart-01b4e0a0-2989-4e59-be4c-94e90cd0a98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779061755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2779061755
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1151251428
Short name T364
Test name
Test status
Simulation time 22680567999 ps
CPU time 57.02 seconds
Started Jul 19 04:52:55 PM PDT 24
Finished Jul 19 04:53:55 PM PDT 24
Peak memory 216604 kb
Host smart-6cd6cbb7-3275-4263-9ef1-a1d12255545c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151251428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1151251428
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3496841669
Short name T320
Test name
Test status
Simulation time 4095760617 ps
CPU time 16.44 seconds
Started Jul 19 04:52:56 PM PDT 24
Finished Jul 19 04:53:15 PM PDT 24
Peak memory 211380 kb
Host smart-cde6d8ed-6141-47e6-8a6f-8a3fa6bfe894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496841669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3496841669
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.219870016
Short name T306
Test name
Test status
Simulation time 44163680466 ps
CPU time 270.61 seconds
Started Jul 19 04:53:00 PM PDT 24
Finished Jul 19 04:57:32 PM PDT 24
Peak memory 233816 kb
Host smart-7e243421-0cb9-4d0d-9a81-35bf06abf87d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219870016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.219870016
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.401625446
Short name T135
Test name
Test status
Simulation time 3604174116 ps
CPU time 20.32 seconds
Started Jul 19 04:53:01 PM PDT 24
Finished Jul 19 04:53:23 PM PDT 24
Peak memory 211404 kb
Host smart-4320b58b-35eb-4e0c-83e1-1bc7aad4f00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401625446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.401625446
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.11625318
Short name T212
Test name
Test status
Simulation time 2277647451 ps
CPU time 9.92 seconds
Started Jul 19 04:52:54 PM PDT 24
Finished Jul 19 04:53:06 PM PDT 24
Peak memory 211412 kb
Host smart-f6b2c89d-a907-4d56-a090-5e59e0b2ef11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11625318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.11625318
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1154104955
Short name T2
Test name
Test status
Simulation time 14915592146 ps
CPU time 53.03 seconds
Started Jul 19 04:52:52 PM PDT 24
Finished Jul 19 04:53:46 PM PDT 24
Peak memory 216576 kb
Host smart-0b4028e2-fd87-4edf-9e35-d768e6de3113
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154104955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1154104955
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.108491286
Short name T337
Test name
Test status
Simulation time 986656825 ps
CPU time 10.19 seconds
Started Jul 19 04:52:52 PM PDT 24
Finished Jul 19 04:53:03 PM PDT 24
Peak memory 211280 kb
Host smart-9c80d024-82a2-4168-b86b-1c50dbc62e1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108491286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.108491286
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.830994645
Short name T194
Test name
Test status
Simulation time 473089351867 ps
CPU time 259.35 seconds
Started Jul 19 04:52:53 PM PDT 24
Finished Jul 19 04:57:14 PM PDT 24
Peak memory 236884 kb
Host smart-be907164-1c3c-4ef5-aaa2-7cd9e7c83d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830994645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.830994645
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2254490114
Short name T353
Test name
Test status
Simulation time 16762887670 ps
CPU time 28.37 seconds
Started Jul 19 04:52:53 PM PDT 24
Finished Jul 19 04:53:23 PM PDT 24
Peak memory 212152 kb
Host smart-fcb32d97-8672-4c1c-97f7-d8ea866e72bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254490114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2254490114
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3387800111
Short name T267
Test name
Test status
Simulation time 344329783 ps
CPU time 8.12 seconds
Started Jul 19 04:52:54 PM PDT 24
Finished Jul 19 04:53:03 PM PDT 24
Peak memory 211340 kb
Host smart-2d58ede2-ac4a-42fc-b83e-8c38e87b2283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387800111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3387800111
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1749230805
Short name T188
Test name
Test status
Simulation time 725729796 ps
CPU time 13.02 seconds
Started Jul 19 04:53:00 PM PDT 24
Finished Jul 19 04:53:16 PM PDT 24
Peak memory 213740 kb
Host smart-d6550757-0964-434e-9d1a-c287ac48a14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749230805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1749230805
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.525748009
Short name T151
Test name
Test status
Simulation time 3975706602 ps
CPU time 63.26 seconds
Started Jul 19 04:52:53 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 219416 kb
Host smart-656b723a-06fc-4c87-98c7-e7920ac1b2f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525748009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.525748009
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1220001518
Short name T211
Test name
Test status
Simulation time 899154835 ps
CPU time 9.38 seconds
Started Jul 19 04:52:53 PM PDT 24
Finished Jul 19 04:53:04 PM PDT 24
Peak memory 211504 kb
Host smart-c9da8d8e-c17b-435a-8506-6d2a2d765b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220001518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1220001518
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.423630905
Short name T7
Test name
Test status
Simulation time 15906919720 ps
CPU time 126.45 seconds
Started Jul 19 04:52:53 PM PDT 24
Finished Jul 19 04:55:01 PM PDT 24
Peak memory 233780 kb
Host smart-180655aa-aff2-467b-ac9c-f2b2cdc2eb34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423630905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.423630905
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3076022791
Short name T6
Test name
Test status
Simulation time 2144972482 ps
CPU time 16.39 seconds
Started Jul 19 04:52:59 PM PDT 24
Finished Jul 19 04:53:17 PM PDT 24
Peak memory 210964 kb
Host smart-a10ae22a-658b-49a4-83ce-86aea1719429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3076022791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3076022791
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2211850322
Short name T64
Test name
Test status
Simulation time 13470722032 ps
CPU time 39.29 seconds
Started Jul 19 04:52:52 PM PDT 24
Finished Jul 19 04:53:32 PM PDT 24
Peak memory 213184 kb
Host smart-e044d84a-6964-4b96-89a6-610663e999f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211850322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2211850322
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3288956800
Short name T323
Test name
Test status
Simulation time 3641726446 ps
CPU time 36.34 seconds
Started Jul 19 04:52:55 PM PDT 24
Finished Jul 19 04:53:34 PM PDT 24
Peak memory 215320 kb
Host smart-c59d6d9d-e37e-4c3a-aa05-f50b5c44bb48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288956800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3288956800
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4229553
Short name T234
Test name
Test status
Simulation time 432364736 ps
CPU time 7.24 seconds
Started Jul 19 04:53:07 PM PDT 24
Finished Jul 19 04:53:15 PM PDT 24
Peak memory 211276 kb
Host smart-abad2d85-c34d-482a-a2f0-b328f151dad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4229553
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1364844638
Short name T222
Test name
Test status
Simulation time 57883951623 ps
CPU time 513.4 seconds
Started Jul 19 04:53:01 PM PDT 24
Finished Jul 19 05:01:37 PM PDT 24
Peak memory 225480 kb
Host smart-6a2b6a5b-0b3e-4348-be79-009f694bd3b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364844638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1364844638
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1549130738
Short name T34
Test name
Test status
Simulation time 694629369 ps
CPU time 9.85 seconds
Started Jul 19 04:53:02 PM PDT 24
Finished Jul 19 04:53:15 PM PDT 24
Peak memory 211952 kb
Host smart-0467f079-2676-4a64-8e37-c622e67d07e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549130738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1549130738
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2525802980
Short name T310
Test name
Test status
Simulation time 94235507 ps
CPU time 5.55 seconds
Started Jul 19 04:53:03 PM PDT 24
Finished Jul 19 04:53:12 PM PDT 24
Peak memory 211400 kb
Host smart-075f104c-a6fd-46d3-892b-23d254aeeb7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525802980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2525802980
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3443721923
Short name T182
Test name
Test status
Simulation time 1305704628 ps
CPU time 17.97 seconds
Started Jul 19 04:53:01 PM PDT 24
Finished Jul 19 04:53:22 PM PDT 24
Peak memory 213344 kb
Host smart-94a7f88f-36b1-4976-935f-f783ee0faeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443721923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3443721923
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3386717982
Short name T355
Test name
Test status
Simulation time 44618813425 ps
CPU time 64.58 seconds
Started Jul 19 04:53:02 PM PDT 24
Finished Jul 19 04:54:10 PM PDT 24
Peak memory 219360 kb
Host smart-c5cf249f-deec-455b-be47-6197e9be3ec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386717982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3386717982
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2954282788
Short name T292
Test name
Test status
Simulation time 86253903 ps
CPU time 4.38 seconds
Started Jul 19 04:53:03 PM PDT 24
Finished Jul 19 04:53:10 PM PDT 24
Peak memory 211364 kb
Host smart-dc4f3f64-3f4a-4b9d-93fb-141fcec884c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954282788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2954282788
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3911998594
Short name T206
Test name
Test status
Simulation time 100081120511 ps
CPU time 183.75 seconds
Started Jul 19 04:53:07 PM PDT 24
Finished Jul 19 04:56:12 PM PDT 24
Peak memory 236736 kb
Host smart-cd80cf28-0cfa-4034-9868-2659c50f83b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911998594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3911998594
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1387500061
Short name T124
Test name
Test status
Simulation time 415655033 ps
CPU time 12.45 seconds
Started Jul 19 04:53:01 PM PDT 24
Finished Jul 19 04:53:17 PM PDT 24
Peak memory 211900 kb
Host smart-f2805a22-496f-478f-ac43-7498c1d278f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387500061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1387500061
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3808093235
Short name T350
Test name
Test status
Simulation time 872389084 ps
CPU time 10.66 seconds
Started Jul 19 04:53:03 PM PDT 24
Finished Jul 19 04:53:17 PM PDT 24
Peak memory 211412 kb
Host smart-d2f4e45b-a578-4a0f-bdfb-cada1430454a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808093235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3808093235
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1929747875
Short name T345
Test name
Test status
Simulation time 535991347 ps
CPU time 13.87 seconds
Started Jul 19 04:53:02 PM PDT 24
Finished Jul 19 04:53:19 PM PDT 24
Peak memory 213704 kb
Host smart-01729c6c-9cc4-43e7-9317-ce291f87e662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929747875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1929747875
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1787218167
Short name T321
Test name
Test status
Simulation time 5731598509 ps
CPU time 21.96 seconds
Started Jul 19 04:53:01 PM PDT 24
Finished Jul 19 04:53:25 PM PDT 24
Peak memory 214456 kb
Host smart-1bf18aac-96e4-4aa1-b78c-24582ed96a21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787218167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1787218167
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.338610735
Short name T301
Test name
Test status
Simulation time 1706748417 ps
CPU time 7.11 seconds
Started Jul 19 04:51:56 PM PDT 24
Finished Jul 19 04:52:05 PM PDT 24
Peak memory 211164 kb
Host smart-afe9d514-547d-42eb-ba71-de43b14f2d52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338610735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.338610735
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4086481748
Short name T294
Test name
Test status
Simulation time 115220670351 ps
CPU time 246.04 seconds
Started Jul 19 04:51:54 PM PDT 24
Finished Jul 19 04:56:02 PM PDT 24
Peak memory 233792 kb
Host smart-a725fddb-18e3-426a-80a6-4aeac558bb72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086481748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4086481748
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2630160005
Short name T190
Test name
Test status
Simulation time 34619584506 ps
CPU time 34.99 seconds
Started Jul 19 04:51:56 PM PDT 24
Finished Jul 19 04:52:33 PM PDT 24
Peak memory 212216 kb
Host smart-cb4650c0-9866-4a9e-83a2-709fd4c2b85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630160005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2630160005
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2815176813
Short name T291
Test name
Test status
Simulation time 186774899 ps
CPU time 5.28 seconds
Started Jul 19 04:51:54 PM PDT 24
Finished Jul 19 04:52:01 PM PDT 24
Peak memory 211404 kb
Host smart-31623747-ce81-40c0-a99e-696a1ec470e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815176813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2815176813
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3238855363
Short name T202
Test name
Test status
Simulation time 1161918437 ps
CPU time 17.19 seconds
Started Jul 19 04:51:53 PM PDT 24
Finished Jul 19 04:52:12 PM PDT 24
Peak memory 211836 kb
Host smart-13351fdf-8831-44f1-b192-cd87a70ea6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238855363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3238855363
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2222066934
Short name T280
Test name
Test status
Simulation time 19667911682 ps
CPU time 52.52 seconds
Started Jul 19 04:51:55 PM PDT 24
Finished Jul 19 04:52:49 PM PDT 24
Peak memory 217344 kb
Host smart-d7b932a8-2c42-46e0-ba84-b517d660f48a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222066934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2222066934
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3049769685
Short name T201
Test name
Test status
Simulation time 759325144 ps
CPU time 8.87 seconds
Started Jul 19 04:53:07 PM PDT 24
Finished Jul 19 04:53:17 PM PDT 24
Peak memory 211288 kb
Host smart-6fa183b7-5506-4009-91c3-09ee3e5feea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049769685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3049769685
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.475593777
Short name T163
Test name
Test status
Simulation time 145865100948 ps
CPU time 413.5 seconds
Started Jul 19 04:53:02 PM PDT 24
Finished Jul 19 04:59:59 PM PDT 24
Peak memory 228636 kb
Host smart-79bf0d8c-7bd5-4aab-adc0-0c7f1c931151
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475593777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.475593777
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1607929489
Short name T361
Test name
Test status
Simulation time 13334380814 ps
CPU time 28.87 seconds
Started Jul 19 04:53:02 PM PDT 24
Finished Jul 19 04:53:33 PM PDT 24
Peak memory 212344 kb
Host smart-77d58270-d989-4b86-91f3-e55cf8319437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607929489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1607929489
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2804653360
Short name T233
Test name
Test status
Simulation time 1534969799 ps
CPU time 8.16 seconds
Started Jul 19 04:53:00 PM PDT 24
Finished Jul 19 04:53:09 PM PDT 24
Peak memory 211400 kb
Host smart-d72a8487-f9e3-4af9-8df4-9e4265d46db5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804653360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2804653360
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3609662078
Short name T185
Test name
Test status
Simulation time 4023380055 ps
CPU time 21.3 seconds
Started Jul 19 04:53:00 PM PDT 24
Finished Jul 19 04:53:24 PM PDT 24
Peak memory 213616 kb
Host smart-526a9265-a763-4144-afaa-a484c5109868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609662078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3609662078
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2188249959
Short name T273
Test name
Test status
Simulation time 2347816312 ps
CPU time 29.11 seconds
Started Jul 19 04:53:07 PM PDT 24
Finished Jul 19 04:53:37 PM PDT 24
Peak memory 215916 kb
Host smart-916ead12-4c2f-4681-b2e8-465b019599b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188249959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2188249959
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1294160145
Short name T39
Test name
Test status
Simulation time 32184992659 ps
CPU time 1741.68 seconds
Started Jul 19 04:53:02 PM PDT 24
Finished Jul 19 05:22:08 PM PDT 24
Peak memory 235828 kb
Host smart-a31c6f2c-6dac-473d-aaf7-8c237ac3c6f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294160145 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1294160145
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.905248187
Short name T84
Test name
Test status
Simulation time 1115735840 ps
CPU time 10.58 seconds
Started Jul 19 04:53:02 PM PDT 24
Finished Jul 19 04:53:15 PM PDT 24
Peak memory 211368 kb
Host smart-7e06a561-0aca-4ea1-8b8d-c8b4f376370c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905248187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.905248187
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1144216707
Short name T286
Test name
Test status
Simulation time 18382318355 ps
CPU time 258.35 seconds
Started Jul 19 04:53:07 PM PDT 24
Finished Jul 19 04:57:27 PM PDT 24
Peak memory 212656 kb
Host smart-ce8e195c-5682-49c5-9470-52e2bbc04043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144216707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1144216707
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1385727075
Short name T131
Test name
Test status
Simulation time 791612043 ps
CPU time 9.55 seconds
Started Jul 19 04:53:01 PM PDT 24
Finished Jul 19 04:53:14 PM PDT 24
Peak memory 212364 kb
Host smart-8bb81b8f-86ce-47f7-aff4-dd8d2bb5da3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385727075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1385727075
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3758397760
Short name T347
Test name
Test status
Simulation time 23593570597 ps
CPU time 16 seconds
Started Jul 19 04:53:03 PM PDT 24
Finished Jul 19 04:53:22 PM PDT 24
Peak memory 211472 kb
Host smart-c99d6aab-d180-4120-9c6f-aa312d13ffb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758397760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3758397760
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3166619392
Short name T68
Test name
Test status
Simulation time 3252149622 ps
CPU time 32.86 seconds
Started Jul 19 04:53:08 PM PDT 24
Finished Jul 19 04:53:42 PM PDT 24
Peak memory 213096 kb
Host smart-07342f1f-5405-408e-8c9c-83e7332d0151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166619392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3166619392
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1144393910
Short name T205
Test name
Test status
Simulation time 5649173089 ps
CPU time 15.06 seconds
Started Jul 19 04:53:03 PM PDT 24
Finished Jul 19 04:53:21 PM PDT 24
Peak memory 211276 kb
Host smart-735acd38-27c7-4526-a7f2-5a9b36a98ad6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144393910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1144393910
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1909795556
Short name T303
Test name
Test status
Simulation time 487727212 ps
CPU time 4.27 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:53:17 PM PDT 24
Peak memory 211344 kb
Host smart-c22059fc-06f9-47c2-b549-af0a5b9ac077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909795556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1909795556
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.465150272
Short name T252
Test name
Test status
Simulation time 1497047204 ps
CPU time 69.82 seconds
Started Jul 19 04:53:02 PM PDT 24
Finished Jul 19 04:54:15 PM PDT 24
Peak memory 236748 kb
Host smart-82be8deb-4fb3-4aca-a95b-340ee15378cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465150272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.465150272
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.16673236
Short name T156
Test name
Test status
Simulation time 7159760500 ps
CPU time 29.8 seconds
Started Jul 19 04:53:01 PM PDT 24
Finished Jul 19 04:53:33 PM PDT 24
Peak memory 212552 kb
Host smart-fa9c4243-e221-495c-b4d6-a7b65569bb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16673236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.16673236
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2669623189
Short name T14
Test name
Test status
Simulation time 2506718468 ps
CPU time 12.05 seconds
Started Jul 19 04:53:02 PM PDT 24
Finished Jul 19 04:53:17 PM PDT 24
Peak memory 211460 kb
Host smart-94129501-5a40-4534-8ff6-bf4b4922a85b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669623189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2669623189
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3144662275
Short name T121
Test name
Test status
Simulation time 3571257520 ps
CPU time 9.85 seconds
Started Jul 19 04:53:01 PM PDT 24
Finished Jul 19 04:53:14 PM PDT 24
Peak memory 213640 kb
Host smart-99f4d757-1fe4-4afc-a5c5-020294c87a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144662275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3144662275
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.982422198
Short name T271
Test name
Test status
Simulation time 60482379990 ps
CPU time 80.32 seconds
Started Jul 19 04:53:00 PM PDT 24
Finished Jul 19 04:54:21 PM PDT 24
Peak memory 216860 kb
Host smart-40e6f8a9-b580-42df-bf4a-17fc7edccb14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982422198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.982422198
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.329943481
Short name T315
Test name
Test status
Simulation time 14716292700 ps
CPU time 3581.09 seconds
Started Jul 19 04:53:09 PM PDT 24
Finished Jul 19 05:52:53 PM PDT 24
Peak memory 224404 kb
Host smart-05abff93-b271-4a3f-aa98-d669e09e3736
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329943481 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.329943481
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.344792968
Short name T49
Test name
Test status
Simulation time 334516374 ps
CPU time 4.2 seconds
Started Jul 19 04:53:09 PM PDT 24
Finished Jul 19 04:53:16 PM PDT 24
Peak memory 211292 kb
Host smart-cdffcd98-8854-4bbe-8fd2-0e165d796cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344792968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.344792968
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3921836650
Short name T130
Test name
Test status
Simulation time 3985982914 ps
CPU time 32.69 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:53:46 PM PDT 24
Peak memory 211892 kb
Host smart-a93b23ec-837c-435e-9a9f-f06ca8d8992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921836650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3921836650
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.522386751
Short name T85
Test name
Test status
Simulation time 4319536852 ps
CPU time 17.04 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:53:29 PM PDT 24
Peak memory 211384 kb
Host smart-b056783f-58db-4405-b0f3-55d8fbf86c92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522386751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.522386751
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.4013052097
Short name T241
Test name
Test status
Simulation time 316658957 ps
CPU time 11.59 seconds
Started Jul 19 04:53:11 PM PDT 24
Finished Jul 19 04:53:25 PM PDT 24
Peak memory 213156 kb
Host smart-548b93fb-fe4f-4d02-a146-2de8c7ca304e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013052097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.4013052097
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2057033299
Short name T210
Test name
Test status
Simulation time 2689882085 ps
CPU time 10.94 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:53:24 PM PDT 24
Peak memory 212188 kb
Host smart-ad0298eb-ec7c-4e24-a8f7-ba9636257d11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057033299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2057033299
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3340378697
Short name T331
Test name
Test status
Simulation time 108342269729 ps
CPU time 3050.03 seconds
Started Jul 19 04:53:09 PM PDT 24
Finished Jul 19 05:44:01 PM PDT 24
Peak memory 235844 kb
Host smart-e01809ee-457d-47bf-8068-83849a51b2a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340378697 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3340378697
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1261478380
Short name T261
Test name
Test status
Simulation time 1427523941 ps
CPU time 11.04 seconds
Started Jul 19 04:53:12 PM PDT 24
Finished Jul 19 04:53:25 PM PDT 24
Peak memory 211344 kb
Host smart-bf1b2ea6-7933-4f72-9158-e49843758f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261478380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1261478380
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.535055555
Short name T145
Test name
Test status
Simulation time 17625066501 ps
CPU time 201.45 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:56:34 PM PDT 24
Peak memory 236924 kb
Host smart-43ea417a-7295-4a6a-8a94-6c171fa307e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535055555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.535055555
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.376093498
Short name T254
Test name
Test status
Simulation time 429295189 ps
CPU time 12.29 seconds
Started Jul 19 04:53:09 PM PDT 24
Finished Jul 19 04:53:24 PM PDT 24
Peak memory 211956 kb
Host smart-87e81f75-4764-4b00-8163-809f8d03c7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376093498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.376093498
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.580939458
Short name T19
Test name
Test status
Simulation time 3951671264 ps
CPU time 11.57 seconds
Started Jul 19 04:53:12 PM PDT 24
Finished Jul 19 04:53:26 PM PDT 24
Peak memory 211444 kb
Host smart-45622849-8e3a-4f52-9710-c78b4495f84e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580939458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.580939458
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2709475538
Short name T168
Test name
Test status
Simulation time 15768275621 ps
CPU time 31.23 seconds
Started Jul 19 04:53:11 PM PDT 24
Finished Jul 19 04:53:45 PM PDT 24
Peak memory 214068 kb
Host smart-66b7163b-29df-47aa-9a2d-aa9c9ea6afcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709475538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2709475538
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1957021703
Short name T311
Test name
Test status
Simulation time 12417066767 ps
CPU time 37.45 seconds
Started Jul 19 04:53:08 PM PDT 24
Finished Jul 19 04:53:47 PM PDT 24
Peak memory 217456 kb
Host smart-1d752563-47a4-4816-bf58-6afc6e40c905
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957021703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1957021703
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1581487652
Short name T285
Test name
Test status
Simulation time 1236064187 ps
CPU time 11.7 seconds
Started Jul 19 04:53:09 PM PDT 24
Finished Jul 19 04:53:22 PM PDT 24
Peak memory 211332 kb
Host smart-65f6e677-0b3f-4172-aef3-489d068c9e6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581487652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1581487652
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1662853614
Short name T209
Test name
Test status
Simulation time 4835614137 ps
CPU time 75.01 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 236856 kb
Host smart-a194d6f5-00e1-4da4-ba60-25ad35af0204
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662853614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1662853614
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3509208391
Short name T37
Test name
Test status
Simulation time 9485237789 ps
CPU time 25.14 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:53:37 PM PDT 24
Peak memory 212256 kb
Host smart-82993f70-56d8-478c-a55a-fead1c3215d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509208391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3509208391
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.722289299
Short name T277
Test name
Test status
Simulation time 553242677 ps
CPU time 8.46 seconds
Started Jul 19 04:53:11 PM PDT 24
Finished Jul 19 04:53:21 PM PDT 24
Peak memory 211384 kb
Host smart-6edc712e-d101-4062-9f12-f50b01ae9eab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722289299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.722289299
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1569151041
Short name T137
Test name
Test status
Simulation time 356944943 ps
CPU time 9.92 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:53:22 PM PDT 24
Peak memory 213612 kb
Host smart-dc918280-4f76-4ba7-b38b-cb0766397d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569151041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1569151041
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1189088
Short name T191
Test name
Test status
Simulation time 3794370373 ps
CPU time 30.26 seconds
Started Jul 19 04:53:12 PM PDT 24
Finished Jul 19 04:53:45 PM PDT 24
Peak memory 214928 kb
Host smart-18566ff1-cf18-4f63-ade0-f79bcd8f10d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.rom_ctrl_stress_all.1189088
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.103595566
Short name T334
Test name
Test status
Simulation time 15646261774 ps
CPU time 14.6 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:53:27 PM PDT 24
Peak memory 211288 kb
Host smart-4f42bbc5-87ec-42c0-81ad-ce0904f0e290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103595566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.103595566
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1498459923
Short name T180
Test name
Test status
Simulation time 59070317196 ps
CPU time 174.55 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:56:07 PM PDT 24
Peak memory 234072 kb
Host smart-1f749fab-7dfc-4291-aea3-a1b76971b0fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498459923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1498459923
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3205626684
Short name T264
Test name
Test status
Simulation time 261599623 ps
CPU time 9.25 seconds
Started Jul 19 04:53:12 PM PDT 24
Finished Jul 19 04:53:23 PM PDT 24
Peak memory 211824 kb
Host smart-e15417e1-981b-4256-be7a-ae45d7a10502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205626684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3205626684
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1692421052
Short name T283
Test name
Test status
Simulation time 346300787 ps
CPU time 8.01 seconds
Started Jul 19 04:53:10 PM PDT 24
Finished Jul 19 04:53:20 PM PDT 24
Peak memory 211400 kb
Host smart-19cb2cb3-a1cd-4a00-b127-11237a718e61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692421052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1692421052
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3099483942
Short name T316
Test name
Test status
Simulation time 6979860982 ps
CPU time 28.9 seconds
Started Jul 19 04:53:08 PM PDT 24
Finished Jul 19 04:53:38 PM PDT 24
Peak memory 213364 kb
Host smart-96d44ba0-7d57-4449-906b-1bdb89f37e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099483942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3099483942
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2437912776
Short name T24
Test name
Test status
Simulation time 1841083750 ps
CPU time 15.35 seconds
Started Jul 19 04:53:19 PM PDT 24
Finished Jul 19 04:53:36 PM PDT 24
Peak memory 211356 kb
Host smart-df0ae6c5-f2d3-420c-b4fb-29d52d59c344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437912776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2437912776
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3134743958
Short name T246
Test name
Test status
Simulation time 12210949248 ps
CPU time 187.12 seconds
Started Jul 19 04:53:18 PM PDT 24
Finished Jul 19 04:56:27 PM PDT 24
Peak memory 225692 kb
Host smart-83a8d81d-16f7-4454-b7ba-65fea6db30ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134743958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3134743958
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.701577050
Short name T269
Test name
Test status
Simulation time 7529392241 ps
CPU time 30.53 seconds
Started Jul 19 04:53:24 PM PDT 24
Finished Jul 19 04:53:56 PM PDT 24
Peak memory 212284 kb
Host smart-e158fb4e-68ac-49a8-879d-cb2cde597e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701577050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.701577050
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1404005782
Short name T197
Test name
Test status
Simulation time 2045315533 ps
CPU time 16.67 seconds
Started Jul 19 04:53:12 PM PDT 24
Finished Jul 19 04:53:31 PM PDT 24
Peak memory 211412 kb
Host smart-74585635-4132-41a8-ab89-1e94b4edaadb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404005782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1404005782
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2108604362
Short name T69
Test name
Test status
Simulation time 5484720876 ps
CPU time 31.92 seconds
Started Jul 19 04:53:09 PM PDT 24
Finished Jul 19 04:53:44 PM PDT 24
Peak memory 213816 kb
Host smart-ee6995a1-c29d-4cb2-93b2-2a8d837f09a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108604362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2108604362
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1136182922
Short name T173
Test name
Test status
Simulation time 8749432665 ps
CPU time 26.8 seconds
Started Jul 19 04:53:12 PM PDT 24
Finished Jul 19 04:53:41 PM PDT 24
Peak memory 214496 kb
Host smart-4a520294-dd0c-446b-9210-a03f26e427cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136182922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1136182922
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2028165020
Short name T322
Test name
Test status
Simulation time 86382087 ps
CPU time 4.34 seconds
Started Jul 19 04:53:19 PM PDT 24
Finished Jul 19 04:53:25 PM PDT 24
Peak memory 211292 kb
Host smart-91ab93c2-edfb-49c1-80ee-aaf793c1cc60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028165020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2028165020
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2520185515
Short name T221
Test name
Test status
Simulation time 57013450812 ps
CPU time 532.28 seconds
Started Jul 19 04:53:20 PM PDT 24
Finished Jul 19 05:02:14 PM PDT 24
Peak memory 225164 kb
Host smart-3b4ce35c-439f-4116-8430-415a3161674b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520185515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2520185515
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.330634533
Short name T204
Test name
Test status
Simulation time 4258538920 ps
CPU time 33.42 seconds
Started Jul 19 04:53:20 PM PDT 24
Finished Jul 19 04:53:55 PM PDT 24
Peak memory 211932 kb
Host smart-e9d3c01f-727d-40b8-ba89-45d6ae7ef44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330634533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.330634533
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1814396638
Short name T270
Test name
Test status
Simulation time 340915811 ps
CPU time 5.61 seconds
Started Jul 19 04:53:25 PM PDT 24
Finished Jul 19 04:53:32 PM PDT 24
Peak memory 211424 kb
Host smart-a24233d5-4623-46ae-a2d6-f2e1b68e92c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814396638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1814396638
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.329372773
Short name T225
Test name
Test status
Simulation time 15133480074 ps
CPU time 30.89 seconds
Started Jul 19 04:53:19 PM PDT 24
Finished Jul 19 04:53:52 PM PDT 24
Peak memory 214160 kb
Host smart-75e7850b-42a3-4717-ba33-3f08246fd29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329372773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.329372773
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4100769612
Short name T195
Test name
Test status
Simulation time 1746063496 ps
CPU time 27.15 seconds
Started Jul 19 04:53:24 PM PDT 24
Finished Jul 19 04:53:53 PM PDT 24
Peak memory 215720 kb
Host smart-ea7f794d-c2a3-4ec6-a1be-55d3c13f161e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100769612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4100769612
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3360661800
Short name T312
Test name
Test status
Simulation time 123600701077 ps
CPU time 3160.36 seconds
Started Jul 19 04:53:19 PM PDT 24
Finished Jul 19 05:46:01 PM PDT 24
Peak memory 228528 kb
Host smart-f176f0e8-8822-4437-87cb-8b18ef138e56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360661800 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3360661800
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3030188026
Short name T275
Test name
Test status
Simulation time 1938189146 ps
CPU time 14.88 seconds
Started Jul 19 04:53:18 PM PDT 24
Finished Jul 19 04:53:35 PM PDT 24
Peak memory 211348 kb
Host smart-0133db95-bc64-42ad-9e92-a4b677758bee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030188026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3030188026
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3429558224
Short name T181
Test name
Test status
Simulation time 22018264445 ps
CPU time 272.53 seconds
Started Jul 19 04:53:19 PM PDT 24
Finished Jul 19 04:57:53 PM PDT 24
Peak memory 213688 kb
Host smart-fa85b44c-a1c0-4554-9914-29f2cadfea32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429558224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3429558224
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1372797566
Short name T167
Test name
Test status
Simulation time 21234185804 ps
CPU time 22.35 seconds
Started Jul 19 04:53:24 PM PDT 24
Finished Jul 19 04:53:48 PM PDT 24
Peak memory 212392 kb
Host smart-e8be13d3-02a5-4fdc-a4e8-50a989055760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372797566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1372797566
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1492496378
Short name T235
Test name
Test status
Simulation time 8227408562 ps
CPU time 15.04 seconds
Started Jul 19 04:53:17 PM PDT 24
Finished Jul 19 04:53:33 PM PDT 24
Peak memory 211460 kb
Host smart-b0e7fefc-999c-4ea0-aa08-495f51e0388c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492496378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1492496378
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4073203149
Short name T317
Test name
Test status
Simulation time 4385778393 ps
CPU time 27.88 seconds
Started Jul 19 04:53:18 PM PDT 24
Finished Jul 19 04:53:47 PM PDT 24
Peak memory 213860 kb
Host smart-b069d9dd-58d9-4cf7-862d-6add47a16155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073203149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4073203149
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.207182878
Short name T335
Test name
Test status
Simulation time 1136077565 ps
CPU time 17.12 seconds
Started Jul 19 04:53:18 PM PDT 24
Finished Jul 19 04:53:36 PM PDT 24
Peak memory 215124 kb
Host smart-f3e7a0a0-478e-48c3-975d-641953b460e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207182878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.207182878
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.519208709
Short name T9
Test name
Test status
Simulation time 1349276379 ps
CPU time 11.84 seconds
Started Jul 19 04:52:06 PM PDT 24
Finished Jul 19 04:52:20 PM PDT 24
Peak memory 211296 kb
Host smart-f6885279-e2f9-4513-b99f-19da171d5317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519208709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.519208709
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2378513655
Short name T30
Test name
Test status
Simulation time 109568800411 ps
CPU time 272.53 seconds
Started Jul 19 04:51:55 PM PDT 24
Finished Jul 19 04:56:29 PM PDT 24
Peak memory 232864 kb
Host smart-137190c4-db22-4218-b4eb-fb3caf4f4a85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378513655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2378513655
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.503435411
Short name T288
Test name
Test status
Simulation time 1166503266 ps
CPU time 17.25 seconds
Started Jul 19 04:51:57 PM PDT 24
Finished Jul 19 04:52:16 PM PDT 24
Peak memory 211964 kb
Host smart-c40df529-7132-4347-8514-ac0b8ab7c82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503435411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.503435411
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2506218654
Short name T293
Test name
Test status
Simulation time 353947808 ps
CPU time 5.62 seconds
Started Jul 19 04:51:57 PM PDT 24
Finished Jul 19 04:52:04 PM PDT 24
Peak memory 211404 kb
Host smart-7b144034-c243-4ecc-bb6d-5622d642a2bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506218654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2506218654
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2028915182
Short name T22
Test name
Test status
Simulation time 563717955 ps
CPU time 50.68 seconds
Started Jul 19 04:51:57 PM PDT 24
Finished Jul 19 04:52:50 PM PDT 24
Peak memory 236716 kb
Host smart-0663c811-c14e-4d50-9d13-20882968020e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028915182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2028915182
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1531316023
Short name T138
Test name
Test status
Simulation time 337171659 ps
CPU time 10.02 seconds
Started Jul 19 04:52:00 PM PDT 24
Finished Jul 19 04:52:11 PM PDT 24
Peak memory 212664 kb
Host smart-8072998c-28e1-482b-bacb-07ff914f1e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531316023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1531316023
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.320020977
Short name T342
Test name
Test status
Simulation time 23438059624 ps
CPU time 37.05 seconds
Started Jul 19 04:51:59 PM PDT 24
Finished Jul 19 04:52:38 PM PDT 24
Peak memory 214460 kb
Host smart-ec8a8757-d745-472b-b222-a61bdf3fc09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320020977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.320020977
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3385842879
Short name T41
Test name
Test status
Simulation time 146604462178 ps
CPU time 1483.2 seconds
Started Jul 19 04:52:07 PM PDT 24
Finished Jul 19 05:16:52 PM PDT 24
Peak memory 235856 kb
Host smart-45050cd1-b32c-431c-8f97-ad996b44d699
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385842879 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3385842879
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1088078828
Short name T52
Test name
Test status
Simulation time 333173937 ps
CPU time 4.18 seconds
Started Jul 19 04:53:18 PM PDT 24
Finished Jul 19 04:53:24 PM PDT 24
Peak memory 211344 kb
Host smart-296b5a48-915d-4bff-a879-a60ff96a9dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088078828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1088078828
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3017444371
Short name T88
Test name
Test status
Simulation time 37334126981 ps
CPU time 249.37 seconds
Started Jul 19 04:53:18 PM PDT 24
Finished Jul 19 04:57:29 PM PDT 24
Peak memory 212588 kb
Host smart-d2127031-4de3-4c19-b54a-72d3df68aa60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017444371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3017444371
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2742939839
Short name T26
Test name
Test status
Simulation time 1377268103 ps
CPU time 14.29 seconds
Started Jul 19 04:53:19 PM PDT 24
Finished Jul 19 04:53:35 PM PDT 24
Peak memory 211988 kb
Host smart-2e53f998-e98f-4282-96c4-adc8d9bbd41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742939839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2742939839
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1316344122
Short name T186
Test name
Test status
Simulation time 7654393965 ps
CPU time 14.94 seconds
Started Jul 19 04:53:18 PM PDT 24
Finished Jul 19 04:53:34 PM PDT 24
Peak memory 211408 kb
Host smart-db86a394-9e70-4b93-8839-433e875c2099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1316344122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1316344122
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1090881241
Short name T123
Test name
Test status
Simulation time 16055733712 ps
CPU time 26.67 seconds
Started Jul 19 04:53:24 PM PDT 24
Finished Jul 19 04:53:52 PM PDT 24
Peak memory 214204 kb
Host smart-7d79bce7-e81e-4045-b687-4a95c77e67f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090881241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1090881241
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2683675080
Short name T341
Test name
Test status
Simulation time 758672134 ps
CPU time 15.54 seconds
Started Jul 19 04:53:19 PM PDT 24
Finished Jul 19 04:53:36 PM PDT 24
Peak memory 214940 kb
Host smart-b308bfa7-4727-44dc-851c-bbfb53a11900
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683675080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2683675080
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3406523317
Short name T144
Test name
Test status
Simulation time 11799966786 ps
CPU time 17.55 seconds
Started Jul 19 04:53:17 PM PDT 24
Finished Jul 19 04:53:35 PM PDT 24
Peak memory 211400 kb
Host smart-5b1da524-6a85-4d2b-8a33-d55242a56b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406523317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3406523317
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3674301599
Short name T38
Test name
Test status
Simulation time 1624420266 ps
CPU time 104.35 seconds
Started Jul 19 04:53:17 PM PDT 24
Finished Jul 19 04:55:02 PM PDT 24
Peak memory 237776 kb
Host smart-414e6d4f-ecd0-4167-801e-cd20fb16216a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674301599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3674301599
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3213687606
Short name T362
Test name
Test status
Simulation time 11893739409 ps
CPU time 28.65 seconds
Started Jul 19 04:53:20 PM PDT 24
Finished Jul 19 04:53:51 PM PDT 24
Peak memory 211460 kb
Host smart-6643b5c6-8993-4fd9-a4c6-02fe4380f14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213687606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3213687606
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3737195950
Short name T175
Test name
Test status
Simulation time 2595125635 ps
CPU time 11.08 seconds
Started Jul 19 04:53:18 PM PDT 24
Finished Jul 19 04:53:30 PM PDT 24
Peak memory 211464 kb
Host smart-fc01acd4-528f-4409-8812-e9fbf610b1e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737195950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3737195950
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.790363767
Short name T332
Test name
Test status
Simulation time 4185394012 ps
CPU time 18.4 seconds
Started Jul 19 04:53:17 PM PDT 24
Finished Jul 19 04:53:37 PM PDT 24
Peak memory 213800 kb
Host smart-09d8ff27-3d85-4d8e-bc3f-d8f0a93064a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790363767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.790363767
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.869705911
Short name T351
Test name
Test status
Simulation time 1293193810 ps
CPU time 18.71 seconds
Started Jul 19 04:53:25 PM PDT 24
Finished Jul 19 04:53:45 PM PDT 24
Peak memory 215200 kb
Host smart-1eb66328-9d70-4df4-81ac-be2d630d2ada
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869705911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.869705911
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.127332618
Short name T360
Test name
Test status
Simulation time 3641006313 ps
CPU time 10.56 seconds
Started Jul 19 04:53:27 PM PDT 24
Finished Jul 19 04:53:39 PM PDT 24
Peak memory 211312 kb
Host smart-02b84b95-f299-4159-8bf9-8a73257cc287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127332618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.127332618
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3018671092
Short name T128
Test name
Test status
Simulation time 24272500575 ps
CPU time 215.12 seconds
Started Jul 19 04:53:27 PM PDT 24
Finished Jul 19 04:57:04 PM PDT 24
Peak memory 238908 kb
Host smart-486b9b77-086d-4b5e-af0e-7087224d5b0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018671092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3018671092
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3058349489
Short name T25
Test name
Test status
Simulation time 15708234673 ps
CPU time 33.12 seconds
Started Jul 19 04:53:27 PM PDT 24
Finished Jul 19 04:54:01 PM PDT 24
Peak memory 212284 kb
Host smart-8cd8be38-27bd-4f83-b69b-3dab390f0356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058349489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3058349489
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1394930042
Short name T219
Test name
Test status
Simulation time 16970866344 ps
CPU time 14.75 seconds
Started Jul 19 04:53:27 PM PDT 24
Finished Jul 19 04:53:43 PM PDT 24
Peak memory 211464 kb
Host smart-53b57e8e-861b-4904-937a-7762666cfd4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394930042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1394930042
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.695750939
Short name T299
Test name
Test status
Simulation time 275646382 ps
CPU time 11.33 seconds
Started Jul 19 04:53:26 PM PDT 24
Finished Jul 19 04:53:38 PM PDT 24
Peak memory 211996 kb
Host smart-ade6bf00-c616-4416-bc42-0efb51a51405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695750939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.695750939
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2890878244
Short name T236
Test name
Test status
Simulation time 7379384955 ps
CPU time 73.17 seconds
Started Jul 19 04:53:28 PM PDT 24
Finished Jul 19 04:54:42 PM PDT 24
Peak memory 217080 kb
Host smart-a98b8406-6dd4-4adb-898b-962d514b9a48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890878244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2890878244
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1642501585
Short name T139
Test name
Test status
Simulation time 3382448851 ps
CPU time 8.78 seconds
Started Jul 19 04:53:26 PM PDT 24
Finished Jul 19 04:53:36 PM PDT 24
Peak memory 211404 kb
Host smart-e806ec8b-1a5c-47e8-a5aa-9239d75227ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642501585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1642501585
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1208171195
Short name T239
Test name
Test status
Simulation time 3439024756 ps
CPU time 112.77 seconds
Started Jul 19 04:53:26 PM PDT 24
Finished Jul 19 04:55:20 PM PDT 24
Peak memory 237592 kb
Host smart-e78a6dc2-2415-45c1-8a61-df4d2fa4d187
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208171195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1208171195
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.906797141
Short name T207
Test name
Test status
Simulation time 1512425620 ps
CPU time 9.36 seconds
Started Jul 19 04:53:28 PM PDT 24
Finished Jul 19 04:53:38 PM PDT 24
Peak memory 211860 kb
Host smart-004df9dd-25bc-4eaf-a222-41cda09a83c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906797141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.906797141
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1235121063
Short name T224
Test name
Test status
Simulation time 4750893231 ps
CPU time 18.11 seconds
Started Jul 19 04:53:28 PM PDT 24
Finished Jul 19 04:53:47 PM PDT 24
Peak memory 211400 kb
Host smart-fb348dfc-cf23-4f55-92a8-5b8b7f95b10c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235121063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1235121063
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3694512145
Short name T120
Test name
Test status
Simulation time 7230286900 ps
CPU time 29.53 seconds
Started Jul 19 04:53:26 PM PDT 24
Finished Jul 19 04:53:57 PM PDT 24
Peak memory 214300 kb
Host smart-e3abe441-0b05-4af1-885d-742406968dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694512145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3694512145
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3036052332
Short name T184
Test name
Test status
Simulation time 3621057507 ps
CPU time 21.57 seconds
Started Jul 19 04:53:27 PM PDT 24
Finished Jul 19 04:53:50 PM PDT 24
Peak memory 214024 kb
Host smart-b7cac420-fee4-4fac-96ac-4dfdd7b53ce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036052332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3036052332
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.4087077235
Short name T340
Test name
Test status
Simulation time 143876637406 ps
CPU time 2359.02 seconds
Started Jul 19 04:53:27 PM PDT 24
Finished Jul 19 05:32:48 PM PDT 24
Peak memory 252204 kb
Host smart-4114dc8b-5f5d-420d-9135-3f03c3d1d222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087077235 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.4087077235
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1259357480
Short name T146
Test name
Test status
Simulation time 217878434 ps
CPU time 5.89 seconds
Started Jul 19 04:53:41 PM PDT 24
Finished Jul 19 04:53:48 PM PDT 24
Peak memory 211380 kb
Host smart-963e1afc-c953-4dee-81a2-08eb815032ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259357480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1259357480
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.363414761
Short name T196
Test name
Test status
Simulation time 92043141145 ps
CPU time 279.15 seconds
Started Jul 19 04:53:37 PM PDT 24
Finished Jul 19 04:58:18 PM PDT 24
Peak memory 237876 kb
Host smart-8695a83a-046a-4ac4-a7e8-4e497cf1f0b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363414761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.363414761
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.198628437
Short name T327
Test name
Test status
Simulation time 666088447 ps
CPU time 9.2 seconds
Started Jul 19 04:53:40 PM PDT 24
Finished Jul 19 04:53:51 PM PDT 24
Peak memory 211864 kb
Host smart-72e46f92-0493-44bf-b3e3-f27f610fb726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198628437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.198628437
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4149382307
Short name T339
Test name
Test status
Simulation time 4063371429 ps
CPU time 14.01 seconds
Started Jul 19 04:53:38 PM PDT 24
Finished Jul 19 04:53:54 PM PDT 24
Peak memory 211460 kb
Host smart-ffe13f8a-f998-46a8-8457-513bf068e42a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4149382307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4149382307
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1456090456
Short name T287
Test name
Test status
Simulation time 9454458757 ps
CPU time 20.16 seconds
Started Jul 19 04:53:27 PM PDT 24
Finished Jul 19 04:53:49 PM PDT 24
Peak memory 214476 kb
Host smart-6c75912d-37ce-4d38-aeff-e451ee5edcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456090456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1456090456
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3386666626
Short name T329
Test name
Test status
Simulation time 38527472416 ps
CPU time 65.78 seconds
Started Jul 19 04:53:27 PM PDT 24
Finished Jul 19 04:54:34 PM PDT 24
Peak memory 217504 kb
Host smart-49ec6962-2c48-4ae0-b3b5-e519a31a57a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386666626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3386666626
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1941231925
Short name T251
Test name
Test status
Simulation time 396612380 ps
CPU time 4.37 seconds
Started Jul 19 04:53:36 PM PDT 24
Finished Jul 19 04:53:42 PM PDT 24
Peak memory 211356 kb
Host smart-c9c6f492-c7d4-4410-a624-eaf5fbb86f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941231925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1941231925
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2002139300
Short name T141
Test name
Test status
Simulation time 40728041607 ps
CPU time 142.4 seconds
Started Jul 19 04:53:38 PM PDT 24
Finished Jul 19 04:56:02 PM PDT 24
Peak memory 238080 kb
Host smart-8d9c57cf-cb04-4250-a0f5-6b9557d247a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002139300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2002139300
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3971080060
Short name T259
Test name
Test status
Simulation time 6372279879 ps
CPU time 26.68 seconds
Started Jul 19 04:53:36 PM PDT 24
Finished Jul 19 04:54:04 PM PDT 24
Peak memory 213248 kb
Host smart-a4dc1efa-3c4a-4dbf-92c4-4dcd25e473f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971080060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3971080060
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2454569688
Short name T328
Test name
Test status
Simulation time 2219859246 ps
CPU time 16.82 seconds
Started Jul 19 04:53:38 PM PDT 24
Finished Jul 19 04:53:57 PM PDT 24
Peak memory 211392 kb
Host smart-6e6cda32-8132-41c1-a910-19aa09f660a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454569688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2454569688
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2086377592
Short name T161
Test name
Test status
Simulation time 183013195 ps
CPU time 9.95 seconds
Started Jul 19 04:53:36 PM PDT 24
Finished Jul 19 04:53:47 PM PDT 24
Peak memory 213488 kb
Host smart-5182f73e-ba51-497e-a264-d31f550c8b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086377592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2086377592
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1150288028
Short name T278
Test name
Test status
Simulation time 8930679805 ps
CPU time 42.76 seconds
Started Jul 19 04:53:37 PM PDT 24
Finished Jul 19 04:54:22 PM PDT 24
Peak memory 214380 kb
Host smart-71b515de-a5a6-4182-a92e-ae84adaafd05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150288028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1150288028
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1568749248
Short name T333
Test name
Test status
Simulation time 1193063352 ps
CPU time 11.48 seconds
Started Jul 19 04:53:40 PM PDT 24
Finished Jul 19 04:53:53 PM PDT 24
Peak memory 211380 kb
Host smart-a8b6000a-c561-4387-aa0f-638bf8cf7901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568749248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1568749248
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2933653569
Short name T90
Test name
Test status
Simulation time 157813944123 ps
CPU time 221.76 seconds
Started Jul 19 04:53:37 PM PDT 24
Finished Jul 19 04:57:21 PM PDT 24
Peak memory 228636 kb
Host smart-c39b40db-f4e9-475c-ab3e-00b5a72f6dbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933653569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2933653569
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4235621345
Short name T125
Test name
Test status
Simulation time 13449878421 ps
CPU time 30.39 seconds
Started Jul 19 04:53:37 PM PDT 24
Finished Jul 19 04:54:09 PM PDT 24
Peak memory 212336 kb
Host smart-29736b90-84d2-4817-8f83-f5af6941b03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235621345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4235621345
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2817693158
Short name T295
Test name
Test status
Simulation time 1916897756 ps
CPU time 8.24 seconds
Started Jul 19 04:53:37 PM PDT 24
Finished Jul 19 04:53:47 PM PDT 24
Peak memory 211400 kb
Host smart-13ce4720-2b4b-482b-85b8-b82317c1156b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2817693158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2817693158
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4196124916
Short name T218
Test name
Test status
Simulation time 1708234337 ps
CPU time 19.43 seconds
Started Jul 19 04:53:37 PM PDT 24
Finished Jul 19 04:53:59 PM PDT 24
Peak memory 213632 kb
Host smart-90162659-6eec-4fff-9356-646b601ca40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196124916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4196124916
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.938666711
Short name T67
Test name
Test status
Simulation time 19770827699 ps
CPU time 35.74 seconds
Started Jul 19 04:53:40 PM PDT 24
Finished Jul 19 04:54:18 PM PDT 24
Peak memory 214008 kb
Host smart-937994e1-6840-42d5-9faa-63ef0db0d48b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938666711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.938666711
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4208139043
Short name T226
Test name
Test status
Simulation time 690807138 ps
CPU time 6.74 seconds
Started Jul 19 04:53:37 PM PDT 24
Finished Jul 19 04:53:45 PM PDT 24
Peak memory 211376 kb
Host smart-578c7e16-16ba-4b8d-9704-47aad08791e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208139043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4208139043
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2840339778
Short name T346
Test name
Test status
Simulation time 10002824018 ps
CPU time 135.59 seconds
Started Jul 19 04:53:36 PM PDT 24
Finished Jul 19 04:55:52 PM PDT 24
Peak memory 213720 kb
Host smart-6f0f1614-5638-4a33-bfd0-9fd7b45bf5af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840339778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2840339778
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2868362654
Short name T302
Test name
Test status
Simulation time 27343338861 ps
CPU time 20.46 seconds
Started Jul 19 04:53:39 PM PDT 24
Finished Jul 19 04:54:01 PM PDT 24
Peak memory 212284 kb
Host smart-5d8c456d-6809-4680-af98-b98d4e1b93cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868362654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2868362654
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1891454543
Short name T169
Test name
Test status
Simulation time 8538419624 ps
CPU time 16.92 seconds
Started Jul 19 04:53:37 PM PDT 24
Finished Jul 19 04:53:56 PM PDT 24
Peak memory 211408 kb
Host smart-e73b7dd8-5278-4a9e-92aa-9003d0b7155e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1891454543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1891454543
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1721934517
Short name T343
Test name
Test status
Simulation time 183660982 ps
CPU time 9.81 seconds
Started Jul 19 04:53:40 PM PDT 24
Finished Jul 19 04:53:52 PM PDT 24
Peak memory 212080 kb
Host smart-b33c7889-614a-4e4c-9e3f-46f01ef12078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721934517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1721934517
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1910308910
Short name T119
Test name
Test status
Simulation time 2160647169 ps
CPU time 14.52 seconds
Started Jul 19 04:53:40 PM PDT 24
Finished Jul 19 04:53:56 PM PDT 24
Peak memory 211088 kb
Host smart-8f154179-0910-42f6-a152-f5132edbd3e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910308910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1910308910
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4135359524
Short name T160
Test name
Test status
Simulation time 3205476961 ps
CPU time 14.32 seconds
Started Jul 19 04:53:38 PM PDT 24
Finished Jul 19 04:53:55 PM PDT 24
Peak memory 211352 kb
Host smart-29a9481e-5315-4593-8c6f-86460d4fa24f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135359524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4135359524
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3556131051
Short name T177
Test name
Test status
Simulation time 102322015485 ps
CPU time 311.37 seconds
Started Jul 19 04:53:37 PM PDT 24
Finished Jul 19 04:58:50 PM PDT 24
Peak memory 239612 kb
Host smart-4abc223a-4071-4af5-b6ad-31c03a513f76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556131051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3556131051
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.846646460
Short name T358
Test name
Test status
Simulation time 3863486369 ps
CPU time 13.47 seconds
Started Jul 19 04:53:40 PM PDT 24
Finished Jul 19 04:53:55 PM PDT 24
Peak memory 212024 kb
Host smart-f690ed82-b290-412c-8ffd-41e02035fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846646460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.846646460
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.203125591
Short name T129
Test name
Test status
Simulation time 8427448823 ps
CPU time 16.91 seconds
Started Jul 19 04:53:38 PM PDT 24
Finished Jul 19 04:53:57 PM PDT 24
Peak memory 211436 kb
Host smart-83f95c0c-dea1-4bf3-924f-f0b07c507371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203125591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.203125591
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3159511766
Short name T230
Test name
Test status
Simulation time 8206663420 ps
CPU time 25.48 seconds
Started Jul 19 04:53:38 PM PDT 24
Finished Jul 19 04:54:06 PM PDT 24
Peak memory 213964 kb
Host smart-ac43a730-29a3-4462-893f-f540d3693e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159511766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3159511766
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.384333699
Short name T193
Test name
Test status
Simulation time 307555511 ps
CPU time 15.8 seconds
Started Jul 19 04:53:38 PM PDT 24
Finished Jul 19 04:53:55 PM PDT 24
Peak memory 214804 kb
Host smart-aee8accf-4015-41a8-9319-7deb3f3c1c89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384333699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.384333699
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3516603801
Short name T40
Test name
Test status
Simulation time 64239685448 ps
CPU time 2318.79 seconds
Started Jul 19 04:53:40 PM PDT 24
Finished Jul 19 05:32:21 PM PDT 24
Peak memory 248072 kb
Host smart-8b1788da-c50e-4f69-8999-4e157e829cee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516603801 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3516603801
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1268032051
Short name T282
Test name
Test status
Simulation time 1454870302 ps
CPU time 12.74 seconds
Started Jul 19 04:53:47 PM PDT 24
Finished Jul 19 04:54:03 PM PDT 24
Peak memory 211248 kb
Host smart-60bb2b9d-be5b-4140-8d74-4595790c926e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268032051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1268032051
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.245220292
Short name T276
Test name
Test status
Simulation time 35581286010 ps
CPU time 354.18 seconds
Started Jul 19 04:53:38 PM PDT 24
Finished Jul 19 04:59:34 PM PDT 24
Peak memory 236812 kb
Host smart-daee3de9-abd4-45e0-a168-656f4204acb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245220292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.245220292
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1193100511
Short name T257
Test name
Test status
Simulation time 741293923 ps
CPU time 13.94 seconds
Started Jul 19 04:53:39 PM PDT 24
Finished Jul 19 04:53:55 PM PDT 24
Peak memory 211908 kb
Host smart-2023d7a4-2422-4667-8cd7-60fd2036b419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193100511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1193100511
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3405674944
Short name T101
Test name
Test status
Simulation time 2362534361 ps
CPU time 12.05 seconds
Started Jul 19 04:53:40 PM PDT 24
Finished Jul 19 04:53:54 PM PDT 24
Peak memory 211404 kb
Host smart-50e2c0ff-5163-4af0-9e9f-9338d97067ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3405674944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3405674944
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3186378019
Short name T126
Test name
Test status
Simulation time 3694413976 ps
CPU time 30.32 seconds
Started Jul 19 04:53:38 PM PDT 24
Finished Jul 19 04:54:11 PM PDT 24
Peak memory 212904 kb
Host smart-05c7309a-1c79-4d8d-a1ba-dfd6b3a1bc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186378019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3186378019
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.269228783
Short name T54
Test name
Test status
Simulation time 14177400411 ps
CPU time 38.66 seconds
Started Jul 19 04:53:36 PM PDT 24
Finished Jul 19 04:54:16 PM PDT 24
Peak memory 219360 kb
Host smart-272be41a-25f8-46f1-b2f8-f60ec108d00a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269228783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.269228783
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3707409192
Short name T262
Test name
Test status
Simulation time 332548447 ps
CPU time 4.3 seconds
Started Jul 19 04:52:07 PM PDT 24
Finished Jul 19 04:52:13 PM PDT 24
Peak memory 211300 kb
Host smart-c149b663-498f-4cd2-a0f7-899c9a64de2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707409192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3707409192
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.285069338
Short name T32
Test name
Test status
Simulation time 8526955601 ps
CPU time 174.82 seconds
Started Jul 19 04:52:03 PM PDT 24
Finished Jul 19 04:55:00 PM PDT 24
Peak memory 234940 kb
Host smart-fcbc1f43-3a5e-4dfa-bc78-c72f72082fa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285069338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.285069338
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2729039214
Short name T284
Test name
Test status
Simulation time 1981471903 ps
CPU time 21.67 seconds
Started Jul 19 04:52:07 PM PDT 24
Finished Jul 19 04:52:32 PM PDT 24
Peak memory 211816 kb
Host smart-28b65b64-aab3-4068-90a1-8f29dc09a270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729039214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2729039214
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1061690645
Short name T272
Test name
Test status
Simulation time 1811958931 ps
CPU time 14.88 seconds
Started Jul 19 04:51:57 PM PDT 24
Finished Jul 19 04:52:14 PM PDT 24
Peak memory 211404 kb
Host smart-28a4b7c6-fec2-4e2a-8b14-b98a291a2d4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1061690645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1061690645
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3838732004
Short name T171
Test name
Test status
Simulation time 4014783961 ps
CPU time 31.22 seconds
Started Jul 19 04:51:59 PM PDT 24
Finished Jul 19 04:52:32 PM PDT 24
Peak memory 212168 kb
Host smart-d972eea2-468a-4222-8054-0d62fe27fd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838732004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3838732004
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3851788673
Short name T344
Test name
Test status
Simulation time 11073554463 ps
CPU time 108.49 seconds
Started Jul 19 04:52:07 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 219360 kb
Host smart-949a48ac-f990-4b1a-a624-70e17f052cf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851788673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3851788673
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3155515395
Short name T356
Test name
Test status
Simulation time 2805837912 ps
CPU time 12.3 seconds
Started Jul 19 04:52:07 PM PDT 24
Finished Jul 19 04:52:22 PM PDT 24
Peak memory 211416 kb
Host smart-45726991-ec9a-4c3e-a574-3846c747c46d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155515395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3155515395
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1076219846
Short name T274
Test name
Test status
Simulation time 15803343683 ps
CPU time 201.8 seconds
Started Jul 19 04:52:06 PM PDT 24
Finished Jul 19 04:55:30 PM PDT 24
Peak memory 237884 kb
Host smart-cdbc7fdd-d050-4520-8b4b-b7e8e72eaa40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076219846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1076219846
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3172581629
Short name T213
Test name
Test status
Simulation time 5798637863 ps
CPU time 19.24 seconds
Started Jul 19 04:52:06 PM PDT 24
Finished Jul 19 04:52:28 PM PDT 24
Peak memory 212408 kb
Host smart-f6ca8c27-aec5-40a2-a43d-3ceb9614f45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172581629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3172581629
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.831018489
Short name T82
Test name
Test status
Simulation time 1797423619 ps
CPU time 14.73 seconds
Started Jul 19 04:52:06 PM PDT 24
Finished Jul 19 04:52:22 PM PDT 24
Peak memory 211344 kb
Host smart-12dd4dff-fb06-4d90-a8f2-6299da568b3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831018489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.831018489
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.487798263
Short name T217
Test name
Test status
Simulation time 2951296066 ps
CPU time 30.66 seconds
Started Jul 19 04:52:07 PM PDT 24
Finished Jul 19 04:52:40 PM PDT 24
Peak memory 213588 kb
Host smart-0b252b19-b702-4bef-bc65-4472c00c1111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487798263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.487798263
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2580205025
Short name T300
Test name
Test status
Simulation time 1937981901 ps
CPU time 37.69 seconds
Started Jul 19 04:52:06 PM PDT 24
Finished Jul 19 04:52:44 PM PDT 24
Peak memory 216004 kb
Host smart-c3cb69e0-bb2b-424a-9424-0db01bcba029
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580205025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2580205025
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.541173351
Short name T227
Test name
Test status
Simulation time 838135523 ps
CPU time 8.74 seconds
Started Jul 19 04:52:17 PM PDT 24
Finished Jul 19 04:52:27 PM PDT 24
Peak memory 211332 kb
Host smart-c0c12e80-93ac-44c5-9fcd-186ad86ac6b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541173351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.541173351
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3383567611
Short name T290
Test name
Test status
Simulation time 14296415391 ps
CPU time 75.99 seconds
Started Jul 19 04:52:15 PM PDT 24
Finished Jul 19 04:53:33 PM PDT 24
Peak memory 237888 kb
Host smart-1df0d517-bf86-47f2-844d-193bbc671fbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383567611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3383567611
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3551263880
Short name T357
Test name
Test status
Simulation time 22165857350 ps
CPU time 30.11 seconds
Started Jul 19 04:52:17 PM PDT 24
Finished Jul 19 04:52:48 PM PDT 24
Peak memory 212488 kb
Host smart-6f9535dd-31bc-4db9-8540-41355565ecd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551263880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3551263880
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1437968480
Short name T348
Test name
Test status
Simulation time 715783054 ps
CPU time 5.57 seconds
Started Jul 19 04:52:16 PM PDT 24
Finished Jul 19 04:52:23 PM PDT 24
Peak memory 211376 kb
Host smart-0e8f2db1-9574-4aad-a458-78f2a64f8506
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1437968480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1437968480
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1422822713
Short name T199
Test name
Test status
Simulation time 3207161886 ps
CPU time 28.4 seconds
Started Jul 19 04:52:15 PM PDT 24
Finished Jul 19 04:52:45 PM PDT 24
Peak memory 212368 kb
Host smart-efac2337-df24-4e3f-a3c3-083a47cd3530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422822713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1422822713
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.820679990
Short name T10
Test name
Test status
Simulation time 33832906286 ps
CPU time 74.8 seconds
Started Jul 19 04:52:13 PM PDT 24
Finished Jul 19 04:53:29 PM PDT 24
Peak memory 219412 kb
Host smart-d85439bc-2836-43e0-bb4d-c773ecbaabee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820679990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.820679990
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3882842594
Short name T23
Test name
Test status
Simulation time 96744487 ps
CPU time 4.35 seconds
Started Jul 19 04:52:15 PM PDT 24
Finished Jul 19 04:52:21 PM PDT 24
Peak memory 211304 kb
Host smart-aa579734-caa1-4d02-81a3-c79b06686ff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882842594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3882842594
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3948810678
Short name T200
Test name
Test status
Simulation time 15061734574 ps
CPU time 130.08 seconds
Started Jul 19 04:52:14 PM PDT 24
Finished Jul 19 04:54:25 PM PDT 24
Peak memory 236804 kb
Host smart-d8a95fb2-75b0-4ce9-b68c-d6ce84c1abdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948810678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3948810678
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4228464431
Short name T155
Test name
Test status
Simulation time 6692393667 ps
CPU time 28.68 seconds
Started Jul 19 04:52:16 PM PDT 24
Finished Jul 19 04:52:46 PM PDT 24
Peak memory 213496 kb
Host smart-0378d59d-b4c4-41f7-9154-72564e90b0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228464431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4228464431
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3976626184
Short name T237
Test name
Test status
Simulation time 7850007134 ps
CPU time 17.25 seconds
Started Jul 19 04:52:12 PM PDT 24
Finished Jul 19 04:52:30 PM PDT 24
Peak memory 211412 kb
Host smart-6f1969ce-66b0-454c-972d-f3ad7b81d5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976626184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3976626184
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3475639427
Short name T297
Test name
Test status
Simulation time 14179337331 ps
CPU time 21.86 seconds
Started Jul 19 04:52:15 PM PDT 24
Finished Jul 19 04:52:39 PM PDT 24
Peak memory 213936 kb
Host smart-6571538f-69ad-42d0-ad88-2241c74f98c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475639427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3475639427
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3887282569
Short name T65
Test name
Test status
Simulation time 398339410 ps
CPU time 21.95 seconds
Started Jul 19 04:52:15 PM PDT 24
Finished Jul 19 04:52:39 PM PDT 24
Peak memory 215312 kb
Host smart-62504fb8-16e1-48a3-8818-c8d159089d65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887282569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3887282569
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3772276396
Short name T157
Test name
Test status
Simulation time 5828691617 ps
CPU time 13.79 seconds
Started Jul 19 04:52:21 PM PDT 24
Finished Jul 19 04:52:37 PM PDT 24
Peak memory 211340 kb
Host smart-a6c9730c-8202-4746-86e6-b38dd25693d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772276396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3772276396
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1730945475
Short name T260
Test name
Test status
Simulation time 1232319701 ps
CPU time 73.67 seconds
Started Jul 19 04:52:22 PM PDT 24
Finished Jul 19 04:53:37 PM PDT 24
Peak memory 212528 kb
Host smart-60d48e74-9910-47d7-becc-e5777699b350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730945475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1730945475
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3022810106
Short name T89
Test name
Test status
Simulation time 2660779547 ps
CPU time 24.65 seconds
Started Jul 19 04:52:24 PM PDT 24
Finished Jul 19 04:52:53 PM PDT 24
Peak memory 212120 kb
Host smart-a2e6bd2f-4706-403a-9429-0d643b1f0f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022810106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3022810106
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1006850907
Short name T122
Test name
Test status
Simulation time 2663004744 ps
CPU time 9.63 seconds
Started Jul 19 04:52:23 PM PDT 24
Finished Jul 19 04:52:35 PM PDT 24
Peak memory 211464 kb
Host smart-3a1f633b-9024-4dfb-974c-0d605c8ecb17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1006850907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1006850907
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.124623839
Short name T359
Test name
Test status
Simulation time 14258901590 ps
CPU time 31.76 seconds
Started Jul 19 04:52:21 PM PDT 24
Finished Jul 19 04:52:55 PM PDT 24
Peak memory 214584 kb
Host smart-b6b520b1-666b-48dc-b8bb-7c331d9f68a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124623839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.124623839
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1684688180
Short name T176
Test name
Test status
Simulation time 989677360 ps
CPU time 8.1 seconds
Started Jul 19 04:52:20 PM PDT 24
Finished Jul 19 04:52:29 PM PDT 24
Peak memory 211248 kb
Host smart-a59871b2-3547-404d-80b9-067bc4d6899f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684688180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1684688180
Directory /workspace/9.rom_ctrl_stress_all/latest
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