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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.67 100.00 98.28 97.30 98.37


Total test records in report: 461
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T298 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2513104552 Jul 21 06:28:32 PM PDT 24 Jul 21 06:32:22 PM PDT 24 25969102691 ps
T299 /workspace/coverage/default/6.rom_ctrl_stress_all.663167185 Jul 21 06:27:21 PM PDT 24 Jul 21 06:27:37 PM PDT 24 6228754659 ps
T25 /workspace/coverage/default/3.rom_ctrl_sec_cm.702764052 Jul 21 06:27:16 PM PDT 24 Jul 21 06:28:56 PM PDT 24 1303979529 ps
T300 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1120883822 Jul 21 06:27:11 PM PDT 24 Jul 21 06:27:21 PM PDT 24 3097692724 ps
T301 /workspace/coverage/default/16.rom_ctrl_smoke.3076338919 Jul 21 06:27:31 PM PDT 24 Jul 21 06:27:59 PM PDT 24 1994038044 ps
T302 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1498699625 Jul 21 06:28:04 PM PDT 24 Jul 21 06:28:13 PM PDT 24 303910145 ps
T303 /workspace/coverage/default/1.rom_ctrl_smoke.878100955 Jul 21 06:27:09 PM PDT 24 Jul 21 06:27:33 PM PDT 24 4073648876 ps
T304 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4137650469 Jul 21 06:27:47 PM PDT 24 Jul 21 06:29:07 PM PDT 24 4909600532 ps
T305 /workspace/coverage/default/32.rom_ctrl_smoke.3593255634 Jul 21 06:27:53 PM PDT 24 Jul 21 06:28:18 PM PDT 24 2378603094 ps
T306 /workspace/coverage/default/33.rom_ctrl_smoke.1732001094 Jul 21 06:27:52 PM PDT 24 Jul 21 06:28:16 PM PDT 24 6553915243 ps
T307 /workspace/coverage/default/23.rom_ctrl_stress_all.1031780360 Jul 21 06:27:41 PM PDT 24 Jul 21 06:27:51 PM PDT 24 531971790 ps
T308 /workspace/coverage/default/38.rom_ctrl_alert_test.1136568399 Jul 21 06:28:10 PM PDT 24 Jul 21 06:28:15 PM PDT 24 89043858 ps
T309 /workspace/coverage/default/37.rom_ctrl_stress_all.1897873239 Jul 21 06:28:05 PM PDT 24 Jul 21 06:28:19 PM PDT 24 542325168 ps
T310 /workspace/coverage/default/0.rom_ctrl_alert_test.1054888975 Jul 21 06:27:13 PM PDT 24 Jul 21 06:27:28 PM PDT 24 16839743979 ps
T55 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1493998157 Jul 21 06:28:29 PM PDT 24 Jul 21 07:01:03 PM PDT 24 50124497543 ps
T311 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3191187582 Jul 21 06:27:49 PM PDT 24 Jul 21 06:31:45 PM PDT 24 23938987353 ps
T312 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3721755510 Jul 21 06:28:19 PM PDT 24 Jul 21 06:28:36 PM PDT 24 2194705968 ps
T313 /workspace/coverage/default/37.rom_ctrl_alert_test.3235720857 Jul 21 06:28:06 PM PDT 24 Jul 21 06:28:10 PM PDT 24 89229884 ps
T314 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3358814494 Jul 21 06:27:31 PM PDT 24 Jul 21 06:33:56 PM PDT 24 163215356241 ps
T315 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.448333367 Jul 21 06:27:33 PM PDT 24 Jul 21 06:30:03 PM PDT 24 7387715728 ps
T26 /workspace/coverage/default/2.rom_ctrl_sec_cm.2695551831 Jul 21 06:27:16 PM PDT 24 Jul 21 06:28:08 PM PDT 24 166650270 ps
T316 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3384737383 Jul 21 06:27:54 PM PDT 24 Jul 21 06:28:09 PM PDT 24 432145619 ps
T317 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.790241237 Jul 21 06:27:41 PM PDT 24 Jul 21 06:28:01 PM PDT 24 2238106612 ps
T318 /workspace/coverage/default/7.rom_ctrl_stress_all.3728664681 Jul 21 06:27:22 PM PDT 24 Jul 21 06:27:46 PM PDT 24 5203853826 ps
T319 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1991885602 Jul 21 06:27:35 PM PDT 24 Jul 21 06:27:44 PM PDT 24 961782011 ps
T320 /workspace/coverage/default/39.rom_ctrl_stress_all.1695416236 Jul 21 06:28:10 PM PDT 24 Jul 21 06:28:48 PM PDT 24 9678545281 ps
T56 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2044976977 Jul 21 06:27:32 PM PDT 24 Jul 21 06:50:25 PM PDT 24 33584482636 ps
T321 /workspace/coverage/default/1.rom_ctrl_alert_test.3292555711 Jul 21 06:27:13 PM PDT 24 Jul 21 06:27:18 PM PDT 24 186713949 ps
T322 /workspace/coverage/default/8.rom_ctrl_stress_all.1766317597 Jul 21 06:27:23 PM PDT 24 Jul 21 06:28:06 PM PDT 24 48004134241 ps
T323 /workspace/coverage/default/44.rom_ctrl_stress_all.3090565622 Jul 21 06:28:16 PM PDT 24 Jul 21 06:28:45 PM PDT 24 25533476928 ps
T324 /workspace/coverage/default/0.rom_ctrl_stress_all.1291156826 Jul 21 06:27:09 PM PDT 24 Jul 21 06:27:24 PM PDT 24 233852922 ps
T325 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.847689175 Jul 21 06:27:14 PM PDT 24 Jul 21 06:30:33 PM PDT 24 114506393970 ps
T326 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.961619782 Jul 21 06:27:34 PM PDT 24 Jul 21 06:27:40 PM PDT 24 451200218 ps
T327 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1114333403 Jul 21 06:27:36 PM PDT 24 Jul 21 06:28:05 PM PDT 24 3098494006 ps
T328 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2449796031 Jul 21 06:28:16 PM PDT 24 Jul 21 06:29:26 PM PDT 24 3453066263 ps
T329 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1850813080 Jul 21 06:27:59 PM PDT 24 Jul 21 06:32:17 PM PDT 24 13093860666 ps
T330 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2997041633 Jul 21 06:27:40 PM PDT 24 Jul 21 06:27:46 PM PDT 24 383853471 ps
T331 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2887780501 Jul 21 06:28:04 PM PDT 24 Jul 21 06:28:25 PM PDT 24 1754856649 ps
T332 /workspace/coverage/default/29.rom_ctrl_alert_test.3054793098 Jul 21 06:27:50 PM PDT 24 Jul 21 06:28:01 PM PDT 24 2130019650 ps
T333 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2682173588 Jul 21 06:27:47 PM PDT 24 Jul 21 06:28:00 PM PDT 24 2224837594 ps
T334 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.855010823 Jul 21 06:27:59 PM PDT 24 Jul 21 06:28:13 PM PDT 24 1112557050 ps
T335 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1538692033 Jul 21 06:27:33 PM PDT 24 Jul 21 06:33:22 PM PDT 24 148665696272 ps
T336 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2266887183 Jul 21 06:28:19 PM PDT 24 Jul 21 06:32:33 PM PDT 24 73178983688 ps
T337 /workspace/coverage/default/9.rom_ctrl_alert_test.2499256448 Jul 21 06:27:25 PM PDT 24 Jul 21 06:27:30 PM PDT 24 332829562 ps
T338 /workspace/coverage/default/16.rom_ctrl_stress_all.2958770277 Jul 21 06:27:33 PM PDT 24 Jul 21 06:28:25 PM PDT 24 8849803406 ps
T339 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3787721050 Jul 21 06:27:43 PM PDT 24 Jul 21 06:27:55 PM PDT 24 1158228163 ps
T340 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2880850101 Jul 21 06:27:28 PM PDT 24 Jul 21 06:27:46 PM PDT 24 1100561039 ps
T57 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3671314297 Jul 21 06:27:48 PM PDT 24 Jul 21 06:38:10 PM PDT 24 31106424061 ps
T341 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.436506686 Jul 21 06:28:05 PM PDT 24 Jul 21 06:28:17 PM PDT 24 2610399218 ps
T342 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.378170444 Jul 21 06:28:26 PM PDT 24 Jul 21 06:28:32 PM PDT 24 100712475 ps
T343 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3991470723 Jul 21 06:27:46 PM PDT 24 Jul 21 06:27:58 PM PDT 24 2196083310 ps
T344 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.568376083 Jul 21 06:27:59 PM PDT 24 Jul 21 06:31:06 PM PDT 24 14773342994 ps
T345 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.317708398 Jul 21 06:28:26 PM PDT 24 Jul 21 06:31:52 PM PDT 24 23848796466 ps
T346 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.307544642 Jul 21 06:27:41 PM PDT 24 Jul 21 07:20:58 PM PDT 24 57160019561 ps
T347 /workspace/coverage/default/42.rom_ctrl_stress_all.3007550623 Jul 21 06:28:19 PM PDT 24 Jul 21 06:28:30 PM PDT 24 102636933 ps
T348 /workspace/coverage/default/38.rom_ctrl_stress_all.2612947890 Jul 21 06:28:09 PM PDT 24 Jul 21 06:29:33 PM PDT 24 9435936952 ps
T349 /workspace/coverage/default/11.rom_ctrl_stress_all.406706244 Jul 21 06:27:29 PM PDT 24 Jul 21 06:28:00 PM PDT 24 3762036939 ps
T350 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2584621717 Jul 21 06:27:23 PM PDT 24 Jul 21 06:27:30 PM PDT 24 1330548631 ps
T351 /workspace/coverage/default/20.rom_ctrl_alert_test.2051478740 Jul 21 06:27:36 PM PDT 24 Jul 21 06:27:41 PM PDT 24 89182365 ps
T352 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3079847865 Jul 21 06:28:24 PM PDT 24 Jul 21 07:15:34 PM PDT 24 803396390380 ps
T353 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1317011784 Jul 21 06:27:14 PM PDT 24 Jul 21 06:27:20 PM PDT 24 182403416 ps
T354 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.4212607263 Jul 21 06:27:42 PM PDT 24 Jul 21 06:58:18 PM PDT 24 389357289139 ps
T355 /workspace/coverage/default/22.rom_ctrl_alert_test.2623992306 Jul 21 06:27:40 PM PDT 24 Jul 21 06:27:45 PM PDT 24 591992977 ps
T356 /workspace/coverage/default/32.rom_ctrl_stress_all.3858545137 Jul 21 06:27:53 PM PDT 24 Jul 21 06:28:00 PM PDT 24 461971889 ps
T357 /workspace/coverage/default/44.rom_ctrl_smoke.1287297031 Jul 21 06:28:16 PM PDT 24 Jul 21 06:28:26 PM PDT 24 360190777 ps
T358 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4019461940 Jul 21 06:28:16 PM PDT 24 Jul 21 06:28:30 PM PDT 24 665190473 ps
T61 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3458363328 Jul 21 06:28:39 PM PDT 24 Jul 21 06:29:18 PM PDT 24 6418340277 ps
T62 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2494322387 Jul 21 06:28:50 PM PDT 24 Jul 21 06:29:07 PM PDT 24 9164218686 ps
T63 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2042779175 Jul 21 06:28:58 PM PDT 24 Jul 21 06:29:25 PM PDT 24 2227951295 ps
T359 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.963199429 Jul 21 06:28:30 PM PDT 24 Jul 21 06:28:42 PM PDT 24 5606002672 ps
T96 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2396237967 Jul 21 06:28:50 PM PDT 24 Jul 21 06:28:59 PM PDT 24 3499414024 ps
T360 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1513566384 Jul 21 06:28:56 PM PDT 24 Jul 21 06:29:17 PM PDT 24 21081912743 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2031790413 Jul 21 06:28:37 PM PDT 24 Jul 21 06:28:42 PM PDT 24 101800098 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2090878569 Jul 21 06:28:41 PM PDT 24 Jul 21 06:28:45 PM PDT 24 168451230 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4161006507 Jul 21 06:28:38 PM PDT 24 Jul 21 06:28:52 PM PDT 24 7515838628 ps
T362 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4277023428 Jul 21 06:29:00 PM PDT 24 Jul 21 06:29:13 PM PDT 24 987459062 ps
T100 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4236662518 Jul 21 06:28:37 PM PDT 24 Jul 21 06:28:53 PM PDT 24 8403917987 ps
T58 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.297205467 Jul 21 06:28:39 PM PDT 24 Jul 21 06:29:20 PM PDT 24 4023452113 ps
T363 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3358215242 Jul 21 06:28:51 PM PDT 24 Jul 21 06:29:03 PM PDT 24 750006098 ps
T364 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2158229005 Jul 21 06:29:02 PM PDT 24 Jul 21 06:29:08 PM PDT 24 101785399 ps
T70 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2211518689 Jul 21 06:28:33 PM PDT 24 Jul 21 06:29:36 PM PDT 24 30214381818 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2224028066 Jul 21 06:28:56 PM PDT 24 Jul 21 06:29:11 PM PDT 24 15307881341 ps
T72 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.575825276 Jul 21 06:28:55 PM PDT 24 Jul 21 06:30:01 PM PDT 24 32689186518 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4103201622 Jul 21 06:28:33 PM PDT 24 Jul 21 06:28:50 PM PDT 24 2098832547 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2924158321 Jul 21 06:28:36 PM PDT 24 Jul 21 06:30:15 PM PDT 24 12084968410 ps
T74 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1575719735 Jul 21 06:28:57 PM PDT 24 Jul 21 06:30:03 PM PDT 24 66937220876 ps
T75 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1329306883 Jul 21 06:28:42 PM PDT 24 Jul 21 06:28:59 PM PDT 24 4374580845 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.813615628 Jul 21 06:28:36 PM PDT 24 Jul 21 06:28:50 PM PDT 24 33668032969 ps
T367 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2826583691 Jul 21 06:29:01 PM PDT 24 Jul 21 06:29:11 PM PDT 24 230770889 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1865476778 Jul 21 06:28:31 PM PDT 24 Jul 21 06:28:43 PM PDT 24 6074863133 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3492369113 Jul 21 06:28:41 PM PDT 24 Jul 21 06:28:46 PM PDT 24 260314627 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2494352663 Jul 21 06:28:38 PM PDT 24 Jul 21 06:28:57 PM PDT 24 1800645363 ps
T59 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4247106048 Jul 21 06:28:50 PM PDT 24 Jul 21 06:29:59 PM PDT 24 1141143134 ps
T60 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2322059616 Jul 21 06:28:57 PM PDT 24 Jul 21 06:29:39 PM PDT 24 8742487908 ps
T371 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.402971047 Jul 21 06:29:02 PM PDT 24 Jul 21 06:29:15 PM PDT 24 2721243344 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3039024224 Jul 21 06:28:38 PM PDT 24 Jul 21 06:28:53 PM PDT 24 5848808576 ps
T373 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.305167335 Jul 21 06:29:07 PM PDT 24 Jul 21 06:29:22 PM PDT 24 3761120018 ps
T374 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4060384262 Jul 21 06:28:49 PM PDT 24 Jul 21 06:29:05 PM PDT 24 3804781995 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1758274599 Jul 21 06:28:51 PM PDT 24 Jul 21 06:29:47 PM PDT 24 6809532440 ps
T105 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.764647927 Jul 21 06:28:55 PM PDT 24 Jul 21 06:29:33 PM PDT 24 371454141 ps
T375 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2753268505 Jul 21 06:28:55 PM PDT 24 Jul 21 06:29:09 PM PDT 24 7498788049 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.844947932 Jul 21 06:28:42 PM PDT 24 Jul 21 06:28:54 PM PDT 24 11983964599 ps
T108 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2284301894 Jul 21 06:28:53 PM PDT 24 Jul 21 06:29:38 PM PDT 24 3307370371 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1810166554 Jul 21 06:28:48 PM PDT 24 Jul 21 06:28:53 PM PDT 24 320183418 ps
T97 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2598337983 Jul 21 06:29:08 PM PDT 24 Jul 21 06:29:20 PM PDT 24 3785314338 ps
T83 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2896209148 Jul 21 06:29:08 PM PDT 24 Jul 21 06:29:17 PM PDT 24 4897669760 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1850955095 Jul 21 06:28:59 PM PDT 24 Jul 21 06:29:16 PM PDT 24 7361438405 ps
T98 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2490437131 Jul 21 06:28:54 PM PDT 24 Jul 21 06:29:03 PM PDT 24 2758414305 ps
T379 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.21328255 Jul 21 06:28:48 PM PDT 24 Jul 21 06:29:07 PM PDT 24 1905258022 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4086508044 Jul 21 06:28:36 PM PDT 24 Jul 21 06:28:47 PM PDT 24 4255819590 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1546632496 Jul 21 06:28:38 PM PDT 24 Jul 21 06:28:50 PM PDT 24 2630225387 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1284296153 Jul 21 06:28:38 PM PDT 24 Jul 21 06:30:12 PM PDT 24 11579186640 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1514873687 Jul 21 06:28:42 PM PDT 24 Jul 21 06:28:47 PM PDT 24 85659786 ps
T85 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1552783881 Jul 21 06:28:48 PM PDT 24 Jul 21 06:30:03 PM PDT 24 8482930311 ps
T383 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2323655438 Jul 21 06:29:09 PM PDT 24 Jul 21 06:29:19 PM PDT 24 345417187 ps
T109 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.782106466 Jul 21 06:28:42 PM PDT 24 Jul 21 06:29:58 PM PDT 24 19628634885 ps
T384 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3608489530 Jul 21 06:28:44 PM PDT 24 Jul 21 06:28:55 PM PDT 24 2915528552 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1527044469 Jul 21 06:28:44 PM PDT 24 Jul 21 06:28:51 PM PDT 24 2711216038 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.286058433 Jul 21 06:28:39 PM PDT 24 Jul 21 06:28:54 PM PDT 24 1832824494 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3156524124 Jul 21 06:28:56 PM PDT 24 Jul 21 06:29:12 PM PDT 24 11424266150 ps
T388 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2304077225 Jul 21 06:28:42 PM PDT 24 Jul 21 06:28:59 PM PDT 24 41311760051 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3321540173 Jul 21 06:28:44 PM PDT 24 Jul 21 06:29:01 PM PDT 24 3504470407 ps
T86 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.867848896 Jul 21 06:28:56 PM PDT 24 Jul 21 06:29:29 PM PDT 24 830535085 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3217299900 Jul 21 06:28:48 PM PDT 24 Jul 21 06:29:01 PM PDT 24 1059493527 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.68342258 Jul 21 06:28:41 PM PDT 24 Jul 21 06:28:56 PM PDT 24 2781735688 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3848841427 Jul 21 06:28:52 PM PDT 24 Jul 21 06:29:01 PM PDT 24 512887921 ps
T393 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1685385046 Jul 21 06:28:37 PM PDT 24 Jul 21 06:28:49 PM PDT 24 6707956359 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1292100538 Jul 21 06:28:37 PM PDT 24 Jul 21 06:28:45 PM PDT 24 556905919 ps
T395 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2765256648 Jul 21 06:28:42 PM PDT 24 Jul 21 06:28:55 PM PDT 24 3435275438 ps
T111 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.521185356 Jul 21 06:28:58 PM PDT 24 Jul 21 06:30:15 PM PDT 24 12821898534 ps
T396 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4264427651 Jul 21 06:28:50 PM PDT 24 Jul 21 06:29:00 PM PDT 24 572453288 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3876411540 Jul 21 06:28:39 PM PDT 24 Jul 21 06:28:48 PM PDT 24 1865311812 ps
T398 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3953205830 Jul 21 06:29:03 PM PDT 24 Jul 21 06:29:19 PM PDT 24 7042889749 ps
T399 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2722372996 Jul 21 06:28:57 PM PDT 24 Jul 21 06:29:11 PM PDT 24 3224373928 ps
T113 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.393880146 Jul 21 06:28:52 PM PDT 24 Jul 21 06:29:34 PM PDT 24 4151485284 ps
T400 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.683505367 Jul 21 06:28:57 PM PDT 24 Jul 21 06:29:15 PM PDT 24 18570311739 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1016112385 Jul 21 06:28:39 PM PDT 24 Jul 21 06:28:56 PM PDT 24 6953517594 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2931460219 Jul 21 06:28:39 PM PDT 24 Jul 21 06:28:52 PM PDT 24 5487805009 ps
T402 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1799972133 Jul 21 06:28:43 PM PDT 24 Jul 21 06:29:24 PM PDT 24 3022797823 ps
T403 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3131503731 Jul 21 06:28:58 PM PDT 24 Jul 21 06:29:07 PM PDT 24 2093806424 ps
T110 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4114913804 Jul 21 06:28:41 PM PDT 24 Jul 21 06:29:59 PM PDT 24 1859891665 ps
T404 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2475239321 Jul 21 06:28:51 PM PDT 24 Jul 21 06:28:59 PM PDT 24 168675025 ps
T405 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1097888685 Jul 21 06:29:03 PM PDT 24 Jul 21 06:29:22 PM PDT 24 3761210859 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.531773008 Jul 21 06:28:39 PM PDT 24 Jul 21 06:28:47 PM PDT 24 95006816 ps
T88 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1113216235 Jul 21 06:28:37 PM PDT 24 Jul 21 06:28:49 PM PDT 24 1247550428 ps
T407 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3505852251 Jul 21 06:29:08 PM PDT 24 Jul 21 06:29:25 PM PDT 24 14815543323 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1579517458 Jul 21 06:29:03 PM PDT 24 Jul 21 06:29:21 PM PDT 24 33900963638 ps
T106 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1811679188 Jul 21 06:29:02 PM PDT 24 Jul 21 06:30:17 PM PDT 24 10932598415 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1652661117 Jul 21 06:28:39 PM PDT 24 Jul 21 06:28:54 PM PDT 24 8900941425 ps
T410 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3970967873 Jul 21 06:28:55 PM PDT 24 Jul 21 06:29:13 PM PDT 24 1658694612 ps
T92 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2912102352 Jul 21 06:29:02 PM PDT 24 Jul 21 06:29:17 PM PDT 24 11643493064 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2027243628 Jul 21 06:28:30 PM PDT 24 Jul 21 06:28:44 PM PDT 24 5533338411 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.986956702 Jul 21 06:28:31 PM PDT 24 Jul 21 06:29:42 PM PDT 24 317745573 ps
T412 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1884554198 Jul 21 06:28:55 PM PDT 24 Jul 21 06:29:23 PM PDT 24 10700661797 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2557232715 Jul 21 06:29:07 PM PDT 24 Jul 21 06:29:12 PM PDT 24 334376857 ps
T114 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2210122109 Jul 21 06:28:29 PM PDT 24 Jul 21 06:29:49 PM PDT 24 9581990275 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3656817313 Jul 21 06:29:08 PM PDT 24 Jul 21 06:29:44 PM PDT 24 581205771 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2063793621 Jul 21 06:28:36 PM PDT 24 Jul 21 06:28:47 PM PDT 24 6474445620 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1026735241 Jul 21 06:28:37 PM PDT 24 Jul 21 06:28:44 PM PDT 24 257589093 ps
T94 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.209816117 Jul 21 06:28:51 PM PDT 24 Jul 21 06:29:33 PM PDT 24 10217548076 ps
T417 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2944074166 Jul 21 06:28:52 PM PDT 24 Jul 21 06:29:08 PM PDT 24 7558959427 ps
T418 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2006045224 Jul 21 06:28:56 PM PDT 24 Jul 21 06:30:13 PM PDT 24 11161567081 ps
T112 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2362122435 Jul 21 06:28:42 PM PDT 24 Jul 21 06:29:29 PM PDT 24 1881114275 ps
T419 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3515300791 Jul 21 06:29:04 PM PDT 24 Jul 21 06:29:11 PM PDT 24 369974195 ps
T89 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.429567956 Jul 21 06:28:55 PM PDT 24 Jul 21 06:29:11 PM PDT 24 7554734744 ps
T420 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.950094183 Jul 21 06:28:32 PM PDT 24 Jul 21 06:28:53 PM PDT 24 4473884062 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.589182164 Jul 21 06:28:29 PM PDT 24 Jul 21 06:28:34 PM PDT 24 205111705 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2638567302 Jul 21 06:28:45 PM PDT 24 Jul 21 06:28:50 PM PDT 24 333216119 ps
T95 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2968857026 Jul 21 06:29:04 PM PDT 24 Jul 21 06:29:51 PM PDT 24 17659744472 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2176549531 Jul 21 06:28:37 PM PDT 24 Jul 21 06:28:42 PM PDT 24 883238187 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2047845797 Jul 21 06:28:43 PM PDT 24 Jul 21 06:29:01 PM PDT 24 3047699434 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3033528337 Jul 21 06:28:38 PM PDT 24 Jul 21 06:28:55 PM PDT 24 2041404911 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2155798140 Jul 21 06:28:43 PM PDT 24 Jul 21 06:28:48 PM PDT 24 153092508 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.550373553 Jul 21 06:28:48 PM PDT 24 Jul 21 06:29:02 PM PDT 24 1628226525 ps
T428 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.244568474 Jul 21 06:28:46 PM PDT 24 Jul 21 06:29:12 PM PDT 24 2145253271 ps
T90 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1562623992 Jul 21 06:29:08 PM PDT 24 Jul 21 06:30:16 PM PDT 24 15474035612 ps
T429 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.858111883 Jul 21 06:28:43 PM PDT 24 Jul 21 06:29:28 PM PDT 24 1772826322 ps
T430 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4045314923 Jul 21 06:28:43 PM PDT 24 Jul 21 06:29:11 PM PDT 24 2356901948 ps
T431 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.8499283 Jul 21 06:28:45 PM PDT 24 Jul 21 06:28:59 PM PDT 24 1447722978 ps
T432 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.461115824 Jul 21 06:28:55 PM PDT 24 Jul 21 06:29:04 PM PDT 24 872043988 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3025984361 Jul 21 06:28:32 PM PDT 24 Jul 21 06:28:48 PM PDT 24 1737455929 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2030444063 Jul 21 06:28:45 PM PDT 24 Jul 21 06:29:02 PM PDT 24 4296584334 ps
T435 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3819381595 Jul 21 06:28:51 PM PDT 24 Jul 21 06:28:57 PM PDT 24 306790206 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.520806895 Jul 21 06:28:39 PM PDT 24 Jul 21 06:29:48 PM PDT 24 640565586 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1781021508 Jul 21 06:28:57 PM PDT 24 Jul 21 06:29:07 PM PDT 24 1138326613 ps
T438 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2745134427 Jul 21 06:28:43 PM PDT 24 Jul 21 06:29:02 PM PDT 24 365840384 ps
T439 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2057013653 Jul 21 06:28:51 PM PDT 24 Jul 21 06:28:56 PM PDT 24 86371238 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2727773545 Jul 21 06:28:37 PM PDT 24 Jul 21 06:28:49 PM PDT 24 7468654566 ps
T441 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3345635257 Jul 21 06:29:08 PM PDT 24 Jul 21 06:29:20 PM PDT 24 4683638308 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2126129422 Jul 21 06:28:36 PM PDT 24 Jul 21 06:28:48 PM PDT 24 4299451942 ps
T93 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1258965134 Jul 21 06:28:44 PM PDT 24 Jul 21 06:29:03 PM PDT 24 386555840 ps
T443 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2267652770 Jul 21 06:28:31 PM PDT 24 Jul 21 06:28:41 PM PDT 24 3619123989 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.202157295 Jul 21 06:28:57 PM PDT 24 Jul 21 06:29:04 PM PDT 24 774828013 ps
T445 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3691959466 Jul 21 06:28:50 PM PDT 24 Jul 21 06:29:06 PM PDT 24 8018577517 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1082308968 Jul 21 06:28:38 PM PDT 24 Jul 21 06:28:52 PM PDT 24 7132705076 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2488981359 Jul 21 06:28:43 PM PDT 24 Jul 21 06:28:50 PM PDT 24 474287062 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1523639092 Jul 21 06:28:30 PM PDT 24 Jul 21 06:28:58 PM PDT 24 561459507 ps
T449 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3057113677 Jul 21 06:29:02 PM PDT 24 Jul 21 06:29:39 PM PDT 24 303749012 ps
T450 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3410049097 Jul 21 06:28:57 PM PDT 24 Jul 21 06:29:12 PM PDT 24 2007168423 ps
T451 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3784982407 Jul 21 06:28:56 PM PDT 24 Jul 21 06:29:16 PM PDT 24 31122577297 ps
T452 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1467046888 Jul 21 06:29:09 PM PDT 24 Jul 21 06:30:19 PM PDT 24 12242091452 ps
T453 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1243960873 Jul 21 06:28:44 PM PDT 24 Jul 21 06:28:59 PM PDT 24 1676833949 ps
T91 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3888821353 Jul 21 06:28:29 PM PDT 24 Jul 21 06:28:39 PM PDT 24 792767236 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4016500397 Jul 21 06:28:44 PM PDT 24 Jul 21 06:28:49 PM PDT 24 1035514521 ps
T455 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4224704773 Jul 21 06:28:44 PM PDT 24 Jul 21 06:28:59 PM PDT 24 1808253986 ps
T456 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.807052754 Jul 21 06:28:55 PM PDT 24 Jul 21 06:29:06 PM PDT 24 713807635 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3171982769 Jul 21 06:28:32 PM PDT 24 Jul 21 06:28:44 PM PDT 24 13897529633 ps
T458 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1311581600 Jul 21 06:28:50 PM PDT 24 Jul 21 06:29:00 PM PDT 24 3917981776 ps
T459 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.952351905 Jul 21 06:28:45 PM PDT 24 Jul 21 06:29:01 PM PDT 24 17824128355 ps
T460 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3619340775 Jul 21 06:28:58 PM PDT 24 Jul 21 06:29:09 PM PDT 24 1908479918 ps
T461 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2964289359 Jul 21 06:29:03 PM PDT 24 Jul 21 06:30:19 PM PDT 24 30579843685 ps

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.4273785027
Short name T6
Test name
Test status
Simulation time 77584014120 ps
CPU time 8598.91 seconds
Started Jul 21 06:28:23 PM PDT 24
Finished Jul 21 08:51:43 PM PDT 24
Peak memory 235880 kb
Host smart-ddf85868-32eb-4740-8854-b440bd61a8e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273785027 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.4273785027
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.81923463
Short name T14
Test name
Test status
Simulation time 20401058799 ps
CPU time 237.58 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:31:30 PM PDT 24
Peak memory 237876 kb
Host smart-31d8ec7e-f009-4e1d-ae7e-ff5cfc0220d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81923463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_co
rrupt_sig_fatal_chk.81923463
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3062693854
Short name T46
Test name
Test status
Simulation time 17524802346 ps
CPU time 270.01 seconds
Started Jul 21 06:27:14 PM PDT 24
Finished Jul 21 06:31:44 PM PDT 24
Peak memory 212896 kb
Host smart-bb8e33af-9c22-464e-b285-f932e4d277cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062693854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3062693854
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4247106048
Short name T59
Test name
Test status
Simulation time 1141143134 ps
CPU time 68.89 seconds
Started Jul 21 06:28:50 PM PDT 24
Finished Jul 21 06:29:59 PM PDT 24
Peak memory 212156 kb
Host smart-2c711598-24d8-454b-a02b-e701c99fcfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247106048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4247106048
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2784353198
Short name T16
Test name
Test status
Simulation time 9884476563 ps
CPU time 104.08 seconds
Started Jul 21 06:27:15 PM PDT 24
Finished Jul 21 06:29:00 PM PDT 24
Peak memory 238352 kb
Host smart-1f550e87-d783-40d2-8be8-3e8b2c16eec2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784353198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2784353198
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3458363328
Short name T61
Test name
Test status
Simulation time 6418340277 ps
CPU time 38.11 seconds
Started Jul 21 06:28:39 PM PDT 24
Finished Jul 21 06:29:18 PM PDT 24
Peak memory 210716 kb
Host smart-36eeba7c-56d6-4496-9a8d-7fd8ff479a4a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458363328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3458363328
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4114913804
Short name T110
Test name
Test status
Simulation time 1859891665 ps
CPU time 77.2 seconds
Started Jul 21 06:28:41 PM PDT 24
Finished Jul 21 06:29:59 PM PDT 24
Peak memory 212156 kb
Host smart-16b686bb-88d0-4d4c-a192-6a4c85e111b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114913804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4114913804
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2040980688
Short name T20
Test name
Test status
Simulation time 2118703745 ps
CPU time 10.67 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:41 PM PDT 24
Peak memory 211356 kb
Host smart-b5d75358-601e-45f0-b4ef-6642491685a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040980688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2040980688
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1491076649
Short name T10
Test name
Test status
Simulation time 6848594233 ps
CPU time 35.14 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:28:06 PM PDT 24
Peak memory 214512 kb
Host smart-9473df0d-06c7-49ca-9678-af64c63bdcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491076649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1491076649
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2720913078
Short name T131
Test name
Test status
Simulation time 10175059289 ps
CPU time 24.29 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:55 PM PDT 24
Peak memory 212244 kb
Host smart-769f586f-ab3a-4d9a-9752-2c4ad35796bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720913078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2720913078
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1559820484
Short name T197
Test name
Test status
Simulation time 663889456 ps
CPU time 9.75 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:40 PM PDT 24
Peak memory 211920 kb
Host smart-db3b455e-8ab3-4e4b-97d4-6b5998707a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559820484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1559820484
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.986956702
Short name T107
Test name
Test status
Simulation time 317745573 ps
CPU time 70.75 seconds
Started Jul 21 06:28:31 PM PDT 24
Finished Jul 21 06:29:42 PM PDT 24
Peak memory 212332 kb
Host smart-e1d703cf-6030-48cf-903d-0daf63681501
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986956702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.986956702
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.782106466
Short name T109
Test name
Test status
Simulation time 19628634885 ps
CPU time 75.21 seconds
Started Jul 21 06:28:42 PM PDT 24
Finished Jul 21 06:29:58 PM PDT 24
Peak memory 212388 kb
Host smart-67801054-ce24-4231-ae5a-0ffa012a8973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782106466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.782106466
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.575825276
Short name T72
Test name
Test status
Simulation time 32689186518 ps
CPU time 65.23 seconds
Started Jul 21 06:28:55 PM PDT 24
Finished Jul 21 06:30:01 PM PDT 24
Peak memory 210780 kb
Host smart-bd8568bb-95f6-4ab2-b0a4-29be6183091f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575825276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.575825276
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3385395949
Short name T102
Test name
Test status
Simulation time 6572453610 ps
CPU time 14.23 seconds
Started Jul 21 06:27:27 PM PDT 24
Finished Jul 21 06:27:42 PM PDT 24
Peak memory 211444 kb
Host smart-7aab422e-1839-47d3-a40e-3b1b084fe66c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3385395949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3385395949
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.806218352
Short name T36
Test name
Test status
Simulation time 27724474092 ps
CPU time 280.29 seconds
Started Jul 21 06:27:27 PM PDT 24
Finished Jul 21 06:32:08 PM PDT 24
Peak memory 228648 kb
Host smart-52783567-f2ca-4c73-ba54-94351d542fbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806218352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.806218352
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2180267771
Short name T13
Test name
Test status
Simulation time 25471438981 ps
CPU time 1937.89 seconds
Started Jul 21 06:27:30 PM PDT 24
Finished Jul 21 06:59:51 PM PDT 24
Peak memory 235904 kb
Host smart-f7a85fae-7b86-4ec9-8380-f72567fc16c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180267771 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2180267771
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3888821353
Short name T91
Test name
Test status
Simulation time 792767236 ps
CPU time 9.13 seconds
Started Jul 21 06:28:29 PM PDT 24
Finished Jul 21 06:28:39 PM PDT 24
Peak memory 210628 kb
Host smart-ddaccc0f-2544-42f2-be53-e43e49ab2a5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888821353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3888821353
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1865476778
Short name T368
Test name
Test status
Simulation time 6074863133 ps
CPU time 12.52 seconds
Started Jul 21 06:28:31 PM PDT 24
Finished Jul 21 06:28:43 PM PDT 24
Peak memory 218820 kb
Host smart-70ab0d06-f1b2-4d16-9d7f-da48dd880921
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865476778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1865476778
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2027243628
Short name T411
Test name
Test status
Simulation time 5533338411 ps
CPU time 13.68 seconds
Started Jul 21 06:28:30 PM PDT 24
Finished Jul 21 06:28:44 PM PDT 24
Peak memory 210628 kb
Host smart-62bacffe-b587-4792-beca-18d9ba54e1a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027243628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2027243628
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.589182164
Short name T421
Test name
Test status
Simulation time 205111705 ps
CPU time 5.06 seconds
Started Jul 21 06:28:29 PM PDT 24
Finished Jul 21 06:28:34 PM PDT 24
Peak memory 218776 kb
Host smart-57d572fb-d0de-45aa-882b-eaf11cad8bea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589182164 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.589182164
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3171982769
Short name T457
Test name
Test status
Simulation time 13897529633 ps
CPU time 11.33 seconds
Started Jul 21 06:28:32 PM PDT 24
Finished Jul 21 06:28:44 PM PDT 24
Peak memory 210656 kb
Host smart-b84de2e9-f85b-4497-8f76-33fce7d4c052
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171982769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3171982769
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4103201622
Short name T365
Test name
Test status
Simulation time 2098832547 ps
CPU time 16.61 seconds
Started Jul 21 06:28:33 PM PDT 24
Finished Jul 21 06:28:50 PM PDT 24
Peak memory 210412 kb
Host smart-0160e9fa-78e8-44d4-913a-327b405bdcba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103201622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4103201622
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.963199429
Short name T359
Test name
Test status
Simulation time 5606002672 ps
CPU time 12.22 seconds
Started Jul 21 06:28:30 PM PDT 24
Finished Jul 21 06:28:42 PM PDT 24
Peak memory 210544 kb
Host smart-e4ab0ce4-8734-4fe3-8648-7be458b0cb91
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963199429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
963199429
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1523639092
Short name T448
Test name
Test status
Simulation time 561459507 ps
CPU time 27.34 seconds
Started Jul 21 06:28:30 PM PDT 24
Finished Jul 21 06:28:58 PM PDT 24
Peak memory 210656 kb
Host smart-5c61edaa-ed3b-48cf-af07-3d4caaf4ba01
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523639092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1523639092
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2267652770
Short name T443
Test name
Test status
Simulation time 3619123989 ps
CPU time 9.57 seconds
Started Jul 21 06:28:31 PM PDT 24
Finished Jul 21 06:28:41 PM PDT 24
Peak memory 218816 kb
Host smart-d0302218-f9b2-4a68-a595-58332aa483a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267652770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2267652770
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.950094183
Short name T420
Test name
Test status
Simulation time 4473884062 ps
CPU time 20.71 seconds
Started Jul 21 06:28:32 PM PDT 24
Finished Jul 21 06:28:53 PM PDT 24
Peak memory 218872 kb
Host smart-57e1832a-9be3-444a-99ca-ffd49f90370a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950094183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.950094183
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2210122109
Short name T114
Test name
Test status
Simulation time 9581990275 ps
CPU time 79.24 seconds
Started Jul 21 06:28:29 PM PDT 24
Finished Jul 21 06:29:49 PM PDT 24
Peak memory 212444 kb
Host smart-259b5c88-fb49-454e-a599-6bef32ef739a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210122109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2210122109
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1546632496
Short name T381
Test name
Test status
Simulation time 2630225387 ps
CPU time 11.07 seconds
Started Jul 21 06:28:38 PM PDT 24
Finished Jul 21 06:28:50 PM PDT 24
Peak memory 218712 kb
Host smart-7168abf6-5062-4603-a599-3e30989c6465
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546632496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1546632496
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3033528337
Short name T425
Test name
Test status
Simulation time 2041404911 ps
CPU time 15.94 seconds
Started Jul 21 06:28:38 PM PDT 24
Finished Jul 21 06:28:55 PM PDT 24
Peak memory 210588 kb
Host smart-1c8878e4-52d0-446d-a1ec-64afe58c0ff5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033528337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3033528337
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.68342258
Short name T391
Test name
Test status
Simulation time 2781735688 ps
CPU time 15.19 seconds
Started Jul 21 06:28:41 PM PDT 24
Finished Jul 21 06:28:56 PM PDT 24
Peak memory 217780 kb
Host smart-4fbcf55f-99d1-49dc-a2d4-476e3e9a6935
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68342258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_res
et.68342258
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2031790413
Short name T361
Test name
Test status
Simulation time 101800098 ps
CPU time 4.85 seconds
Started Jul 21 06:28:37 PM PDT 24
Finished Jul 21 06:28:42 PM PDT 24
Peak memory 213764 kb
Host smart-858d5eb0-67dc-4bc1-8db2-1295ff3ffda9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031790413 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2031790413
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2090878569
Short name T69
Test name
Test status
Simulation time 168451230 ps
CPU time 4.09 seconds
Started Jul 21 06:28:41 PM PDT 24
Finished Jul 21 06:28:45 PM PDT 24
Peak memory 217904 kb
Host smart-c9b2a98d-c265-4b35-9ef6-686f7e45221d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090878569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2090878569
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4086508044
Short name T380
Test name
Test status
Simulation time 4255819590 ps
CPU time 10.33 seconds
Started Jul 21 06:28:36 PM PDT 24
Finished Jul 21 06:28:47 PM PDT 24
Peak memory 210468 kb
Host smart-bb040bd9-91ed-4ece-b0b3-77f606a279a7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086508044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4086508044
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2727773545
Short name T440
Test name
Test status
Simulation time 7468654566 ps
CPU time 12.24 seconds
Started Jul 21 06:28:37 PM PDT 24
Finished Jul 21 06:28:49 PM PDT 24
Peak memory 210524 kb
Host smart-3a3c85a0-d860-451a-9a65-66c83b786b7c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727773545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2727773545
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2211518689
Short name T70
Test name
Test status
Simulation time 30214381818 ps
CPU time 62.49 seconds
Started Jul 21 06:28:33 PM PDT 24
Finished Jul 21 06:29:36 PM PDT 24
Peak memory 210672 kb
Host smart-714d3440-e9a1-47cc-8e3a-c1ea960ee6fa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211518689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2211518689
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2126129422
Short name T442
Test name
Test status
Simulation time 4299451942 ps
CPU time 12.16 seconds
Started Jul 21 06:28:36 PM PDT 24
Finished Jul 21 06:28:48 PM PDT 24
Peak memory 210752 kb
Host smart-153d1d4f-19f6-44d4-9f35-0de803257796
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126129422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2126129422
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3025984361
Short name T433
Test name
Test status
Simulation time 1737455929 ps
CPU time 15.81 seconds
Started Jul 21 06:28:32 PM PDT 24
Finished Jul 21 06:28:48 PM PDT 24
Peak memory 218772 kb
Host smart-67e8648e-0e65-4f60-adea-0b25305e5107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025984361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3025984361
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3848841427
Short name T392
Test name
Test status
Simulation time 512887921 ps
CPU time 8.5 seconds
Started Jul 21 06:28:52 PM PDT 24
Finished Jul 21 06:29:01 PM PDT 24
Peak memory 214632 kb
Host smart-495149e9-6996-4bc7-8431-d68f511bb47a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848841427 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3848841427
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2057013653
Short name T439
Test name
Test status
Simulation time 86371238 ps
CPU time 4.4 seconds
Started Jul 21 06:28:51 PM PDT 24
Finished Jul 21 06:28:56 PM PDT 24
Peak memory 210532 kb
Host smart-c58db93a-8d62-4647-9766-67532aea5c78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057013653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2057013653
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1552783881
Short name T85
Test name
Test status
Simulation time 8482930311 ps
CPU time 74.1 seconds
Started Jul 21 06:28:48 PM PDT 24
Finished Jul 21 06:30:03 PM PDT 24
Peak memory 210764 kb
Host smart-ff19be7b-28da-4e56-a04b-b537703fad8d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552783881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1552783881
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2494322387
Short name T62
Test name
Test status
Simulation time 9164218686 ps
CPU time 15.77 seconds
Started Jul 21 06:28:50 PM PDT 24
Finished Jul 21 06:29:07 PM PDT 24
Peak memory 210908 kb
Host smart-ac5975f5-4fb6-4d73-ad38-a7d6b0ba35da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494322387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2494322387
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2475239321
Short name T404
Test name
Test status
Simulation time 168675025 ps
CPU time 7.6 seconds
Started Jul 21 06:28:51 PM PDT 24
Finished Jul 21 06:28:59 PM PDT 24
Peak memory 214508 kb
Host smart-1627800a-d7d7-4dba-ad17-38e2e83fd456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475239321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2475239321
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.393880146
Short name T113
Test name
Test status
Simulation time 4151485284 ps
CPU time 41.12 seconds
Started Jul 21 06:28:52 PM PDT 24
Finished Jul 21 06:29:34 PM PDT 24
Peak memory 218852 kb
Host smart-6d5e65fc-e5a6-4b1d-a027-e0527ab8e93d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393880146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.393880146
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2753268505
Short name T375
Test name
Test status
Simulation time 7498788049 ps
CPU time 13.24 seconds
Started Jul 21 06:28:55 PM PDT 24
Finished Jul 21 06:29:09 PM PDT 24
Peak memory 218976 kb
Host smart-d3b5b7c0-3cdd-4863-ad4f-829cbf498b29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753268505 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2753268505
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3819381595
Short name T435
Test name
Test status
Simulation time 306790206 ps
CPU time 5.29 seconds
Started Jul 21 06:28:51 PM PDT 24
Finished Jul 21 06:28:57 PM PDT 24
Peak memory 217488 kb
Host smart-32d239fc-3af9-41d9-9d99-608ac2fb8c99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819381595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3819381595
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.209816117
Short name T94
Test name
Test status
Simulation time 10217548076 ps
CPU time 42.42 seconds
Started Jul 21 06:28:51 PM PDT 24
Finished Jul 21 06:29:33 PM PDT 24
Peak memory 210780 kb
Host smart-53c415f8-1b5f-425e-8461-9701152b66da
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209816117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.209816117
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3619340775
Short name T460
Test name
Test status
Simulation time 1908479918 ps
CPU time 9.98 seconds
Started Jul 21 06:28:58 PM PDT 24
Finished Jul 21 06:29:09 PM PDT 24
Peak memory 218064 kb
Host smart-863643a4-7d48-4955-a223-bbaa2a131062
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619340775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3619340775
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4060384262
Short name T374
Test name
Test status
Simulation time 3804781995 ps
CPU time 14.73 seconds
Started Jul 21 06:28:49 PM PDT 24
Finished Jul 21 06:29:05 PM PDT 24
Peak memory 218908 kb
Host smart-1e8f0d6a-9fe9-47ba-b9e5-f4ca77a091c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060384262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4060384262
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3131503731
Short name T403
Test name
Test status
Simulation time 2093806424 ps
CPU time 8.51 seconds
Started Jul 21 06:28:58 PM PDT 24
Finished Jul 21 06:29:07 PM PDT 24
Peak memory 218884 kb
Host smart-bb159c03-8db0-44dc-8f98-10514436ba32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131503731 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3131503731
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.429567956
Short name T89
Test name
Test status
Simulation time 7554734744 ps
CPU time 15 seconds
Started Jul 21 06:28:55 PM PDT 24
Finished Jul 21 06:29:11 PM PDT 24
Peak memory 210716 kb
Host smart-96677bc0-44cb-4a94-ab07-ee2c2083947b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429567956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.429567956
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.807052754
Short name T456
Test name
Test status
Simulation time 713807635 ps
CPU time 10.99 seconds
Started Jul 21 06:28:55 PM PDT 24
Finished Jul 21 06:29:06 PM PDT 24
Peak memory 210664 kb
Host smart-86e0e2d8-6461-45de-ac81-e058770321af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807052754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.807052754
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3784982407
Short name T451
Test name
Test status
Simulation time 31122577297 ps
CPU time 19.15 seconds
Started Jul 21 06:28:56 PM PDT 24
Finished Jul 21 06:29:16 PM PDT 24
Peak memory 218888 kb
Host smart-b25d4a86-f97f-4dc2-b942-ca0e4c564b7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784982407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3784982407
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2322059616
Short name T60
Test name
Test status
Simulation time 8742487908 ps
CPU time 42.33 seconds
Started Jul 21 06:28:57 PM PDT 24
Finished Jul 21 06:29:39 PM PDT 24
Peak memory 212312 kb
Host smart-05f5c53c-40bf-4618-a04c-6104facc678a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322059616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2322059616
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.461115824
Short name T432
Test name
Test status
Simulation time 872043988 ps
CPU time 8.6 seconds
Started Jul 21 06:28:55 PM PDT 24
Finished Jul 21 06:29:04 PM PDT 24
Peak memory 218796 kb
Host smart-ef33eefb-59ac-47a7-9981-de6031222cd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461115824 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.461115824
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3156524124
Short name T387
Test name
Test status
Simulation time 11424266150 ps
CPU time 15.89 seconds
Started Jul 21 06:28:56 PM PDT 24
Finished Jul 21 06:29:12 PM PDT 24
Peak memory 218816 kb
Host smart-34ac3b14-44c1-4ca8-b361-d8b59f929c61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156524124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3156524124
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1884554198
Short name T412
Test name
Test status
Simulation time 10700661797 ps
CPU time 27.82 seconds
Started Jul 21 06:28:55 PM PDT 24
Finished Jul 21 06:29:23 PM PDT 24
Peak memory 210756 kb
Host smart-6f75f6a5-129d-40a4-91de-8e97fdccffbf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884554198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1884554198
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2490437131
Short name T98
Test name
Test status
Simulation time 2758414305 ps
CPU time 8.55 seconds
Started Jul 21 06:28:54 PM PDT 24
Finished Jul 21 06:29:03 PM PDT 24
Peak memory 217944 kb
Host smart-a990e6b6-0ef5-42ec-9395-41877d30705e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490437131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2490437131
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1513566384
Short name T360
Test name
Test status
Simulation time 21081912743 ps
CPU time 20.37 seconds
Started Jul 21 06:28:56 PM PDT 24
Finished Jul 21 06:29:17 PM PDT 24
Peak memory 218956 kb
Host smart-be6692fa-3882-4377-80fe-5eb1ddc3d41b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513566384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1513566384
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2006045224
Short name T418
Test name
Test status
Simulation time 11161567081 ps
CPU time 76.28 seconds
Started Jul 21 06:28:56 PM PDT 24
Finished Jul 21 06:30:13 PM PDT 24
Peak memory 212536 kb
Host smart-2c2daad6-0ce0-41bb-ae1d-3a606aae875e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006045224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2006045224
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.202157295
Short name T444
Test name
Test status
Simulation time 774828013 ps
CPU time 7.25 seconds
Started Jul 21 06:28:57 PM PDT 24
Finished Jul 21 06:29:04 PM PDT 24
Peak memory 218860 kb
Host smart-1bbb1041-7ac5-456f-9f48-218fda1cc5d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202157295 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.202157295
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.683505367
Short name T400
Test name
Test status
Simulation time 18570311739 ps
CPU time 16.55 seconds
Started Jul 21 06:28:57 PM PDT 24
Finished Jul 21 06:29:15 PM PDT 24
Peak memory 218768 kb
Host smart-60949fa0-590f-4571-8954-c004512df2aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683505367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.683505367
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2042779175
Short name T63
Test name
Test status
Simulation time 2227951295 ps
CPU time 26.66 seconds
Started Jul 21 06:28:58 PM PDT 24
Finished Jul 21 06:29:25 PM PDT 24
Peak memory 210660 kb
Host smart-eb1a1a26-8410-4c07-80e1-1e2a957ffd4a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042779175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2042779175
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1781021508
Short name T437
Test name
Test status
Simulation time 1138326613 ps
CPU time 10.4 seconds
Started Jul 21 06:28:57 PM PDT 24
Finished Jul 21 06:29:07 PM PDT 24
Peak memory 210592 kb
Host smart-693c46a4-5821-41e7-b1be-b51c0f6b3dea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781021508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1781021508
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3970967873
Short name T410
Test name
Test status
Simulation time 1658694612 ps
CPU time 17.92 seconds
Started Jul 21 06:28:55 PM PDT 24
Finished Jul 21 06:29:13 PM PDT 24
Peak memory 216536 kb
Host smart-457567a0-684e-47c2-a8e2-b771a25ac1b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970967873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3970967873
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.764647927
Short name T105
Test name
Test status
Simulation time 371454141 ps
CPU time 37.27 seconds
Started Jul 21 06:28:55 PM PDT 24
Finished Jul 21 06:29:33 PM PDT 24
Peak memory 218784 kb
Host smart-baf1d074-3fe1-4c72-9214-e55232f369d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764647927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.764647927
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1850955095
Short name T378
Test name
Test status
Simulation time 7361438405 ps
CPU time 16.6 seconds
Started Jul 21 06:28:59 PM PDT 24
Finished Jul 21 06:29:16 PM PDT 24
Peak memory 218944 kb
Host smart-8e0ba509-ae3f-4ac0-a275-0517fe7eb8ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850955095 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1850955095
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2722372996
Short name T399
Test name
Test status
Simulation time 3224373928 ps
CPU time 13.93 seconds
Started Jul 21 06:28:57 PM PDT 24
Finished Jul 21 06:29:11 PM PDT 24
Peak memory 210776 kb
Host smart-32fd9949-fd75-4e2b-8ef9-b6b28806a8b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722372996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2722372996
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.867848896
Short name T86
Test name
Test status
Simulation time 830535085 ps
CPU time 32.84 seconds
Started Jul 21 06:28:56 PM PDT 24
Finished Jul 21 06:29:29 PM PDT 24
Peak memory 217752 kb
Host smart-348dfc96-0b63-4bcb-9448-81c49d94241f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867848896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.867848896
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2224028066
Short name T71
Test name
Test status
Simulation time 15307881341 ps
CPU time 15.02 seconds
Started Jul 21 06:28:56 PM PDT 24
Finished Jul 21 06:29:11 PM PDT 24
Peak memory 210752 kb
Host smart-a156b7a8-5565-4a57-bc9d-efe508954409
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224028066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2224028066
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3410049097
Short name T450
Test name
Test status
Simulation time 2007168423 ps
CPU time 14.8 seconds
Started Jul 21 06:28:57 PM PDT 24
Finished Jul 21 06:29:12 PM PDT 24
Peak memory 218820 kb
Host smart-0ec1dd47-cc5e-431c-a6cb-42b4d8028fca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410049097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3410049097
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.521185356
Short name T111
Test name
Test status
Simulation time 12821898534 ps
CPU time 76.31 seconds
Started Jul 21 06:28:58 PM PDT 24
Finished Jul 21 06:30:15 PM PDT 24
Peak memory 218896 kb
Host smart-659164ca-e92b-4901-811d-e971c6bf870f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521185356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.521185356
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.402971047
Short name T371
Test name
Test status
Simulation time 2721243344 ps
CPU time 12.69 seconds
Started Jul 21 06:29:02 PM PDT 24
Finished Jul 21 06:29:15 PM PDT 24
Peak memory 218820 kb
Host smart-072ffd6a-d457-4de0-8910-6f6cb19796a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402971047 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.402971047
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2912102352
Short name T92
Test name
Test status
Simulation time 11643493064 ps
CPU time 14.88 seconds
Started Jul 21 06:29:02 PM PDT 24
Finished Jul 21 06:29:17 PM PDT 24
Peak memory 218724 kb
Host smart-271d8588-4161-4008-9c2d-cdb99be71927
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912102352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2912102352
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1575719735
Short name T74
Test name
Test status
Simulation time 66937220876 ps
CPU time 65.52 seconds
Started Jul 21 06:28:57 PM PDT 24
Finished Jul 21 06:30:03 PM PDT 24
Peak memory 210836 kb
Host smart-a283e890-e0e3-4b09-9c31-a9b9b2d71d4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575719735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1575719735
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3953205830
Short name T398
Test name
Test status
Simulation time 7042889749 ps
CPU time 15.72 seconds
Started Jul 21 06:29:03 PM PDT 24
Finished Jul 21 06:29:19 PM PDT 24
Peak memory 210884 kb
Host smart-7b9a3b60-22df-41ec-b990-fce405bf7ac7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953205830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3953205830
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4277023428
Short name T362
Test name
Test status
Simulation time 987459062 ps
CPU time 12.34 seconds
Started Jul 21 06:29:00 PM PDT 24
Finished Jul 21 06:29:13 PM PDT 24
Peak memory 218772 kb
Host smart-df71a8ce-d831-4cd5-a1bb-7adb9f944606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277023428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4277023428
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1811679188
Short name T106
Test name
Test status
Simulation time 10932598415 ps
CPU time 74.73 seconds
Started Jul 21 06:29:02 PM PDT 24
Finished Jul 21 06:30:17 PM PDT 24
Peak memory 212496 kb
Host smart-075d986b-6ee1-4990-af7e-4f230b9ada21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811679188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1811679188
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2158229005
Short name T364
Test name
Test status
Simulation time 101785399 ps
CPU time 5.24 seconds
Started Jul 21 06:29:02 PM PDT 24
Finished Jul 21 06:29:08 PM PDT 24
Peak memory 218820 kb
Host smart-a958299e-49e9-4b5a-a773-6bb23bf45fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158229005 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2158229005
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3515300791
Short name T419
Test name
Test status
Simulation time 369974195 ps
CPU time 6.86 seconds
Started Jul 21 06:29:04 PM PDT 24
Finished Jul 21 06:29:11 PM PDT 24
Peak memory 217528 kb
Host smart-592dcc5a-8699-4a88-aa7f-28a044e134ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515300791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3515300791
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2968857026
Short name T95
Test name
Test status
Simulation time 17659744472 ps
CPU time 46.19 seconds
Started Jul 21 06:29:04 PM PDT 24
Finished Jul 21 06:29:51 PM PDT 24
Peak memory 210752 kb
Host smart-7fa579f3-d3d3-47ad-9ba6-3014eb62583b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968857026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2968857026
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1579517458
Short name T408
Test name
Test status
Simulation time 33900963638 ps
CPU time 17.08 seconds
Started Jul 21 06:29:03 PM PDT 24
Finished Jul 21 06:29:21 PM PDT 24
Peak memory 218972 kb
Host smart-757818aa-c055-4456-8f95-994e364d8758
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579517458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1579517458
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2826583691
Short name T367
Test name
Test status
Simulation time 230770889 ps
CPU time 8.76 seconds
Started Jul 21 06:29:01 PM PDT 24
Finished Jul 21 06:29:11 PM PDT 24
Peak memory 218820 kb
Host smart-25d1200c-4836-4e9f-8ae8-2b41a47839c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826583691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2826583691
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3057113677
Short name T449
Test name
Test status
Simulation time 303749012 ps
CPU time 36.22 seconds
Started Jul 21 06:29:02 PM PDT 24
Finished Jul 21 06:29:39 PM PDT 24
Peak memory 218800 kb
Host smart-0767f46e-0cf0-4caa-864e-b759fc353a33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057113677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3057113677
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3345635257
Short name T441
Test name
Test status
Simulation time 4683638308 ps
CPU time 11.23 seconds
Started Jul 21 06:29:08 PM PDT 24
Finished Jul 21 06:29:20 PM PDT 24
Peak memory 218988 kb
Host smart-e8f3b0fe-fef0-48a2-beb7-27803f255c1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345635257 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3345635257
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.305167335
Short name T373
Test name
Test status
Simulation time 3761120018 ps
CPU time 15.05 seconds
Started Jul 21 06:29:07 PM PDT 24
Finished Jul 21 06:29:22 PM PDT 24
Peak memory 218488 kb
Host smart-d06adf75-39b4-4089-8bcc-8aacbca9437b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305167335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.305167335
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2964289359
Short name T461
Test name
Test status
Simulation time 30579843685 ps
CPU time 74.9 seconds
Started Jul 21 06:29:03 PM PDT 24
Finished Jul 21 06:30:19 PM PDT 24
Peak memory 210820 kb
Host smart-adb22713-8fd9-48fe-8a42-4303ca22461e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964289359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2964289359
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2598337983
Short name T97
Test name
Test status
Simulation time 3785314338 ps
CPU time 11.84 seconds
Started Jul 21 06:29:08 PM PDT 24
Finished Jul 21 06:29:20 PM PDT 24
Peak memory 210720 kb
Host smart-19853e15-c8e4-4d90-b7ef-7156ed382235
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598337983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2598337983
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1097888685
Short name T405
Test name
Test status
Simulation time 3761210859 ps
CPU time 18.37 seconds
Started Jul 21 06:29:03 PM PDT 24
Finished Jul 21 06:29:22 PM PDT 24
Peak memory 218828 kb
Host smart-33ee024d-d686-4b43-9ced-46e1c0af2537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097888685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1097888685
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3656817313
Short name T414
Test name
Test status
Simulation time 581205771 ps
CPU time 35.76 seconds
Started Jul 21 06:29:08 PM PDT 24
Finished Jul 21 06:29:44 PM PDT 24
Peak memory 218792 kb
Host smart-7126cde4-c985-4a34-b061-66752f7447f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656817313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3656817313
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3505852251
Short name T407
Test name
Test status
Simulation time 14815543323 ps
CPU time 16.29 seconds
Started Jul 21 06:29:08 PM PDT 24
Finished Jul 21 06:29:25 PM PDT 24
Peak memory 219004 kb
Host smart-cb93d146-b39a-4179-8b9d-7630c8b290dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505852251 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3505852251
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2896209148
Short name T83
Test name
Test status
Simulation time 4897669760 ps
CPU time 8.83 seconds
Started Jul 21 06:29:08 PM PDT 24
Finished Jul 21 06:29:17 PM PDT 24
Peak memory 210580 kb
Host smart-a795f5c2-0310-495c-a7e7-e1d6519bb3b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896209148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2896209148
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1562623992
Short name T90
Test name
Test status
Simulation time 15474035612 ps
CPU time 66.73 seconds
Started Jul 21 06:29:08 PM PDT 24
Finished Jul 21 06:30:16 PM PDT 24
Peak memory 210748 kb
Host smart-1720859b-920b-4163-85a2-3fe40a39561b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562623992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1562623992
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2557232715
Short name T413
Test name
Test status
Simulation time 334376857 ps
CPU time 4.19 seconds
Started Jul 21 06:29:07 PM PDT 24
Finished Jul 21 06:29:12 PM PDT 24
Peak memory 210596 kb
Host smart-efceabfb-68ca-4088-ac14-470ff2af78a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557232715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2557232715
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2323655438
Short name T383
Test name
Test status
Simulation time 345417187 ps
CPU time 9.52 seconds
Started Jul 21 06:29:09 PM PDT 24
Finished Jul 21 06:29:19 PM PDT 24
Peak memory 218832 kb
Host smart-601c703d-4e37-49ae-a34d-6c13ef32a944
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323655438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2323655438
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1467046888
Short name T452
Test name
Test status
Simulation time 12242091452 ps
CPU time 69.85 seconds
Started Jul 21 06:29:09 PM PDT 24
Finished Jul 21 06:30:19 PM PDT 24
Peak memory 218936 kb
Host smart-dd77ac06-f11e-400c-b36a-974ac2ebe734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467046888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1467046888
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1685385046
Short name T393
Test name
Test status
Simulation time 6707956359 ps
CPU time 10.62 seconds
Started Jul 21 06:28:37 PM PDT 24
Finished Jul 21 06:28:49 PM PDT 24
Peak memory 210564 kb
Host smart-657738d9-a3bc-4c7e-aee4-aa5917b8c8b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685385046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1685385046
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4236662518
Short name T100
Test name
Test status
Simulation time 8403917987 ps
CPU time 15.32 seconds
Started Jul 21 06:28:37 PM PDT 24
Finished Jul 21 06:28:53 PM PDT 24
Peak memory 210704 kb
Host smart-1a8c15ef-865e-47d5-aab7-636011f7e380
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236662518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4236662518
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.531773008
Short name T406
Test name
Test status
Simulation time 95006816 ps
CPU time 7.44 seconds
Started Jul 21 06:28:39 PM PDT 24
Finished Jul 21 06:28:47 PM PDT 24
Peak memory 210724 kb
Host smart-d952748e-c618-4bbe-b22a-d27d0571b4c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531773008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.531773008
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.286058433
Short name T386
Test name
Test status
Simulation time 1832824494 ps
CPU time 14.35 seconds
Started Jul 21 06:28:39 PM PDT 24
Finished Jul 21 06:28:54 PM PDT 24
Peak memory 212892 kb
Host smart-9f91fc2d-b5df-4887-8583-37aede8ceca9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286058433 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.286058433
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4161006507
Short name T99
Test name
Test status
Simulation time 7515838628 ps
CPU time 14.01 seconds
Started Jul 21 06:28:38 PM PDT 24
Finished Jul 21 06:28:52 PM PDT 24
Peak memory 210688 kb
Host smart-ecaf5ecc-8a3f-47e0-82c1-c53c51bfbad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161006507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.4161006507
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.813615628
Short name T366
Test name
Test status
Simulation time 33668032969 ps
CPU time 13.86 seconds
Started Jul 21 06:28:36 PM PDT 24
Finished Jul 21 06:28:50 PM PDT 24
Peak memory 210540 kb
Host smart-a93cf15e-3b71-4331-9bdf-6cf9eb5b8fed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813615628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.813615628
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3492369113
Short name T369
Test name
Test status
Simulation time 260314627 ps
CPU time 4.89 seconds
Started Jul 21 06:28:41 PM PDT 24
Finished Jul 21 06:28:46 PM PDT 24
Peak memory 210416 kb
Host smart-fad9685c-3447-4c49-a989-1a620a116d89
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492369113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3492369113
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1026735241
Short name T416
Test name
Test status
Simulation time 257589093 ps
CPU time 5.99 seconds
Started Jul 21 06:28:37 PM PDT 24
Finished Jul 21 06:28:44 PM PDT 24
Peak memory 210660 kb
Host smart-ef404d81-67e8-4073-a6c8-6b6c4880a339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026735241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1026735241
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2494352663
Short name T370
Test name
Test status
Simulation time 1800645363 ps
CPU time 18.41 seconds
Started Jul 21 06:28:38 PM PDT 24
Finished Jul 21 06:28:57 PM PDT 24
Peak memory 218836 kb
Host smart-ef9e3b4e-62ee-437a-9f05-2f7175f57e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494352663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2494352663
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1113216235
Short name T88
Test name
Test status
Simulation time 1247550428 ps
CPU time 11.73 seconds
Started Jul 21 06:28:37 PM PDT 24
Finished Jul 21 06:28:49 PM PDT 24
Peak memory 218508 kb
Host smart-c153926a-f453-4d8c-ac92-7f084a04890f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113216235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1113216235
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1292100538
Short name T394
Test name
Test status
Simulation time 556905919 ps
CPU time 8.05 seconds
Started Jul 21 06:28:37 PM PDT 24
Finished Jul 21 06:28:45 PM PDT 24
Peak memory 216992 kb
Host smart-37ea3e98-8d56-46ed-801b-bc714843eced
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292100538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1292100538
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3876411540
Short name T397
Test name
Test status
Simulation time 1865311812 ps
CPU time 8.25 seconds
Started Jul 21 06:28:39 PM PDT 24
Finished Jul 21 06:28:48 PM PDT 24
Peak memory 210524 kb
Host smart-2c4e3999-d55b-441b-8922-6bb220f5ad1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876411540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3876411540
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2176549531
Short name T423
Test name
Test status
Simulation time 883238187 ps
CPU time 4.43 seconds
Started Jul 21 06:28:37 PM PDT 24
Finished Jul 21 06:28:42 PM PDT 24
Peak memory 212852 kb
Host smart-059ecf54-2746-4401-9a2f-59deea796847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176549531 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2176549531
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2931460219
Short name T87
Test name
Test status
Simulation time 5487805009 ps
CPU time 12.81 seconds
Started Jul 21 06:28:39 PM PDT 24
Finished Jul 21 06:28:52 PM PDT 24
Peak memory 210644 kb
Host smart-174a8e5e-b3ee-40d8-b14e-3d8e44df576e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931460219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2931460219
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1082308968
Short name T446
Test name
Test status
Simulation time 7132705076 ps
CPU time 13.41 seconds
Started Jul 21 06:28:38 PM PDT 24
Finished Jul 21 06:28:52 PM PDT 24
Peak memory 210532 kb
Host smart-c0a68464-8de2-4ff5-bc5c-abde5bbfff4f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082308968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1082308968
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2063793621
Short name T415
Test name
Test status
Simulation time 6474445620 ps
CPU time 10 seconds
Started Jul 21 06:28:36 PM PDT 24
Finished Jul 21 06:28:47 PM PDT 24
Peak memory 210544 kb
Host smart-3321d223-3e25-4747-bffb-66659fdaf3c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063793621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2063793621
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2924158321
Short name T73
Test name
Test status
Simulation time 12084968410 ps
CPU time 97.85 seconds
Started Jul 21 06:28:36 PM PDT 24
Finished Jul 21 06:30:15 PM PDT 24
Peak memory 210716 kb
Host smart-682e3f2c-6ff2-40d9-a373-c2c5b5c9422c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924158321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2924158321
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1652661117
Short name T409
Test name
Test status
Simulation time 8900941425 ps
CPU time 14.3 seconds
Started Jul 21 06:28:39 PM PDT 24
Finished Jul 21 06:28:54 PM PDT 24
Peak memory 219036 kb
Host smart-15e455ae-2a8c-420a-8b01-80e477eaff69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652661117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1652661117
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1016112385
Short name T401
Test name
Test status
Simulation time 6953517594 ps
CPU time 17.01 seconds
Started Jul 21 06:28:39 PM PDT 24
Finished Jul 21 06:28:56 PM PDT 24
Peak memory 218912 kb
Host smart-b835f901-b925-4bdc-9e79-af4d102e57af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016112385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1016112385
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.520806895
Short name T436
Test name
Test status
Simulation time 640565586 ps
CPU time 69.43 seconds
Started Jul 21 06:28:39 PM PDT 24
Finished Jul 21 06:29:48 PM PDT 24
Peak memory 218760 kb
Host smart-da457231-4b37-4f88-8d27-281c8b28407d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520806895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.520806895
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2488981359
Short name T447
Test name
Test status
Simulation time 474287062 ps
CPU time 6.96 seconds
Started Jul 21 06:28:43 PM PDT 24
Finished Jul 21 06:28:50 PM PDT 24
Peak memory 210588 kb
Host smart-b495e318-7d33-4608-9a75-51172e88306f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488981359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2488981359
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2155798140
Short name T426
Test name
Test status
Simulation time 153092508 ps
CPU time 4.57 seconds
Started Jul 21 06:28:43 PM PDT 24
Finished Jul 21 06:28:48 PM PDT 24
Peak memory 210588 kb
Host smart-f1e28149-2c4c-4b89-8a94-ba7dd5b3fe90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155798140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2155798140
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3321540173
Short name T389
Test name
Test status
Simulation time 3504470407 ps
CPU time 15.88 seconds
Started Jul 21 06:28:44 PM PDT 24
Finished Jul 21 06:29:01 PM PDT 24
Peak memory 218436 kb
Host smart-e4736af0-92f4-43ee-a07d-c04e5e1ed67e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321540173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3321540173
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.844947932
Short name T376
Test name
Test status
Simulation time 11983964599 ps
CPU time 11.21 seconds
Started Jul 21 06:28:42 PM PDT 24
Finished Jul 21 06:28:54 PM PDT 24
Peak memory 213076 kb
Host smart-7970b98e-b922-4ba8-98de-51ee3009a801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844947932 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.844947932
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1527044469
Short name T385
Test name
Test status
Simulation time 2711216038 ps
CPU time 7.13 seconds
Started Jul 21 06:28:44 PM PDT 24
Finished Jul 21 06:28:51 PM PDT 24
Peak memory 217632 kb
Host smart-3b107530-7b8b-4582-a5db-190635187dd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527044469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1527044469
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.550373553
Short name T427
Test name
Test status
Simulation time 1628226525 ps
CPU time 13.41 seconds
Started Jul 21 06:28:48 PM PDT 24
Finished Jul 21 06:29:02 PM PDT 24
Peak memory 210412 kb
Host smart-5a55d9e8-9224-490c-af3a-faee3629be64
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550373553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.550373553
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2638567302
Short name T422
Test name
Test status
Simulation time 333216119 ps
CPU time 4.08 seconds
Started Jul 21 06:28:45 PM PDT 24
Finished Jul 21 06:28:50 PM PDT 24
Peak memory 210384 kb
Host smart-e7fec906-4292-482f-bea3-9fe933005b33
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638567302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2638567302
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1284296153
Short name T382
Test name
Test status
Simulation time 11579186640 ps
CPU time 93.56 seconds
Started Jul 21 06:28:38 PM PDT 24
Finished Jul 21 06:30:12 PM PDT 24
Peak memory 210760 kb
Host smart-a8d59511-025e-479f-874e-7ddbdd524162
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284296153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1284296153
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4016500397
Short name T454
Test name
Test status
Simulation time 1035514521 ps
CPU time 4.28 seconds
Started Jul 21 06:28:44 PM PDT 24
Finished Jul 21 06:28:49 PM PDT 24
Peak memory 210656 kb
Host smart-b56d1ac7-7b82-42df-b4e6-9c4714114ac5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016500397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4016500397
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3039024224
Short name T372
Test name
Test status
Simulation time 5848808576 ps
CPU time 14.84 seconds
Started Jul 21 06:28:38 PM PDT 24
Finished Jul 21 06:28:53 PM PDT 24
Peak memory 218920 kb
Host smart-6d919918-354f-4818-80df-f10c52f1ac58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039024224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3039024224
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.297205467
Short name T58
Test name
Test status
Simulation time 4023452113 ps
CPU time 41.3 seconds
Started Jul 21 06:28:39 PM PDT 24
Finished Jul 21 06:29:20 PM PDT 24
Peak memory 212752 kb
Host smart-fafd913a-8f82-4bf0-8bba-e58a6097a238
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297205467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.297205467
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4224704773
Short name T455
Test name
Test status
Simulation time 1808253986 ps
CPU time 14.76 seconds
Started Jul 21 06:28:44 PM PDT 24
Finished Jul 21 06:28:59 PM PDT 24
Peak memory 218784 kb
Host smart-200d5512-749e-485e-b696-4e956ca66bfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224704773 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4224704773
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1243960873
Short name T453
Test name
Test status
Simulation time 1676833949 ps
CPU time 13.88 seconds
Started Jul 21 06:28:44 PM PDT 24
Finished Jul 21 06:28:59 PM PDT 24
Peak memory 218412 kb
Host smart-6a5c6b5c-1db0-43b6-a232-94ed85f0e374
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243960873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1243960873
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1258965134
Short name T93
Test name
Test status
Simulation time 386555840 ps
CPU time 18.44 seconds
Started Jul 21 06:28:44 PM PDT 24
Finished Jul 21 06:29:03 PM PDT 24
Peak memory 210592 kb
Host smart-ec2a5ce7-4822-49b6-bee2-0bf763cb29fb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258965134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1258965134
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.8499283
Short name T431
Test name
Test status
Simulation time 1447722978 ps
CPU time 13.46 seconds
Started Jul 21 06:28:45 PM PDT 24
Finished Jul 21 06:28:59 PM PDT 24
Peak memory 210592 kb
Host smart-f63b0b1e-79ea-4bb2-be5d-5fa89ec03566
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8499283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl
_same_csr_outstanding.8499283
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3217299900
Short name T390
Test name
Test status
Simulation time 1059493527 ps
CPU time 13.07 seconds
Started Jul 21 06:28:48 PM PDT 24
Finished Jul 21 06:29:01 PM PDT 24
Peak memory 218780 kb
Host smart-40915c06-ff59-4186-8a2b-f60b80475070
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217299900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3217299900
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1799972133
Short name T402
Test name
Test status
Simulation time 3022797823 ps
CPU time 40.29 seconds
Started Jul 21 06:28:43 PM PDT 24
Finished Jul 21 06:29:24 PM PDT 24
Peak memory 210988 kb
Host smart-300af257-8c57-4698-9b0e-740459595f8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799972133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1799972133
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2304077225
Short name T388
Test name
Test status
Simulation time 41311760051 ps
CPU time 16.5 seconds
Started Jul 21 06:28:42 PM PDT 24
Finished Jul 21 06:28:59 PM PDT 24
Peak memory 219008 kb
Host smart-4217b984-31ad-40ad-b0ff-18eea63f98b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304077225 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2304077225
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1514873687
Short name T84
Test name
Test status
Simulation time 85659786 ps
CPU time 4.19 seconds
Started Jul 21 06:28:42 PM PDT 24
Finished Jul 21 06:28:47 PM PDT 24
Peak memory 210580 kb
Host smart-92bccd95-02cc-4fba-918f-179415eec2f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514873687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1514873687
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4045314923
Short name T430
Test name
Test status
Simulation time 2356901948 ps
CPU time 27.54 seconds
Started Jul 21 06:28:43 PM PDT 24
Finished Jul 21 06:29:11 PM PDT 24
Peak memory 210732 kb
Host smart-fec1870f-79b1-49c6-8f79-4f55f04d765f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045314923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.4045314923
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1329306883
Short name T75
Test name
Test status
Simulation time 4374580845 ps
CPU time 16.07 seconds
Started Jul 21 06:28:42 PM PDT 24
Finished Jul 21 06:28:59 PM PDT 24
Peak memory 218880 kb
Host smart-83adf4b9-f6da-466f-aad6-64e51f2a9584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329306883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1329306883
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.21328255
Short name T379
Test name
Test status
Simulation time 1905258022 ps
CPU time 18.95 seconds
Started Jul 21 06:28:48 PM PDT 24
Finished Jul 21 06:29:07 PM PDT 24
Peak memory 218784 kb
Host smart-ac1212af-8c94-4636-b9d5-8eb2303eaf00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21328255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.21328255
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.858111883
Short name T429
Test name
Test status
Simulation time 1772826322 ps
CPU time 44.7 seconds
Started Jul 21 06:28:43 PM PDT 24
Finished Jul 21 06:29:28 PM PDT 24
Peak memory 218820 kb
Host smart-0b681a5e-220b-48a7-8c1e-5c762ce62d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858111883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.858111883
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.952351905
Short name T459
Test name
Test status
Simulation time 17824128355 ps
CPU time 16.04 seconds
Started Jul 21 06:28:45 PM PDT 24
Finished Jul 21 06:29:01 PM PDT 24
Peak memory 218944 kb
Host smart-9ab4fe2c-899c-4369-bd60-bdfc6e215325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952351905 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.952351905
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2030444063
Short name T434
Test name
Test status
Simulation time 4296584334 ps
CPU time 16.59 seconds
Started Jul 21 06:28:45 PM PDT 24
Finished Jul 21 06:29:02 PM PDT 24
Peak memory 210636 kb
Host smart-0880ed1c-2b57-4874-9acc-464a6c91f5d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030444063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2030444063
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.244568474
Short name T428
Test name
Test status
Simulation time 2145253271 ps
CPU time 26.3 seconds
Started Jul 21 06:28:46 PM PDT 24
Finished Jul 21 06:29:12 PM PDT 24
Peak memory 211588 kb
Host smart-829473e2-8b3f-405c-8c84-c03cbd3f8e6d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244568474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.244568474
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3608489530
Short name T384
Test name
Test status
Simulation time 2915528552 ps
CPU time 10.72 seconds
Started Jul 21 06:28:44 PM PDT 24
Finished Jul 21 06:28:55 PM PDT 24
Peak memory 210676 kb
Host smart-267da120-6a0e-4b04-abb2-8b504c18a02c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608489530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3608489530
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2765256648
Short name T395
Test name
Test status
Simulation time 3435275438 ps
CPU time 11.79 seconds
Started Jul 21 06:28:42 PM PDT 24
Finished Jul 21 06:28:55 PM PDT 24
Peak memory 218928 kb
Host smart-74ff4174-5157-4373-8f3b-0db2956e6cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765256648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2765256648
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2362122435
Short name T112
Test name
Test status
Simulation time 1881114275 ps
CPU time 46.85 seconds
Started Jul 21 06:28:42 PM PDT 24
Finished Jul 21 06:29:29 PM PDT 24
Peak memory 211912 kb
Host smart-696379b9-04e5-4406-808e-8f327cca7058
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362122435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2362122435
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4264427651
Short name T396
Test name
Test status
Simulation time 572453288 ps
CPU time 8.73 seconds
Started Jul 21 06:28:50 PM PDT 24
Finished Jul 21 06:29:00 PM PDT 24
Peak memory 218752 kb
Host smart-e2c03495-dfa1-4062-82a4-8babeb770ca9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264427651 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4264427651
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2944074166
Short name T417
Test name
Test status
Simulation time 7558959427 ps
CPU time 15.97 seconds
Started Jul 21 06:28:52 PM PDT 24
Finished Jul 21 06:29:08 PM PDT 24
Peak memory 210636 kb
Host smart-439ff38b-39cb-4465-b2e4-76de9e221371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944074166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2944074166
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2745134427
Short name T438
Test name
Test status
Simulation time 365840384 ps
CPU time 18.76 seconds
Started Jul 21 06:28:43 PM PDT 24
Finished Jul 21 06:29:02 PM PDT 24
Peak memory 210640 kb
Host smart-c46a5c3c-0f86-47bb-96f2-4757dffe9ae6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745134427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2745134427
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1311581600
Short name T458
Test name
Test status
Simulation time 3917981776 ps
CPU time 10.15 seconds
Started Jul 21 06:28:50 PM PDT 24
Finished Jul 21 06:29:00 PM PDT 24
Peak memory 210600 kb
Host smart-7157c112-047b-498d-9bff-a99d18f4e1a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311581600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1311581600
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2047845797
Short name T424
Test name
Test status
Simulation time 3047699434 ps
CPU time 17.14 seconds
Started Jul 21 06:28:43 PM PDT 24
Finished Jul 21 06:29:01 PM PDT 24
Peak memory 218880 kb
Host smart-ebbc4649-61f5-4b51-8379-44f9ea51441e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047845797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2047845797
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3691959466
Short name T445
Test name
Test status
Simulation time 8018577517 ps
CPU time 15.97 seconds
Started Jul 21 06:28:50 PM PDT 24
Finished Jul 21 06:29:06 PM PDT 24
Peak memory 218964 kb
Host smart-afc826ec-8e5f-4a0a-a116-0f05a2632e3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691959466 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3691959466
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1810166554
Short name T377
Test name
Test status
Simulation time 320183418 ps
CPU time 4.16 seconds
Started Jul 21 06:28:48 PM PDT 24
Finished Jul 21 06:28:53 PM PDT 24
Peak memory 210588 kb
Host smart-e0c10a9b-58b0-4f30-a430-93d7052700fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810166554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1810166554
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1758274599
Short name T76
Test name
Test status
Simulation time 6809532440 ps
CPU time 55.26 seconds
Started Jul 21 06:28:51 PM PDT 24
Finished Jul 21 06:29:47 PM PDT 24
Peak memory 210752 kb
Host smart-6bedeae3-19b5-45a5-93a4-8d1c7d4c6dcc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758274599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1758274599
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2396237967
Short name T96
Test name
Test status
Simulation time 3499414024 ps
CPU time 8.8 seconds
Started Jul 21 06:28:50 PM PDT 24
Finished Jul 21 06:28:59 PM PDT 24
Peak memory 210708 kb
Host smart-5f1ae041-0588-43a0-a9a3-3c73856dc01d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396237967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2396237967
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3358215242
Short name T363
Test name
Test status
Simulation time 750006098 ps
CPU time 11.11 seconds
Started Jul 21 06:28:51 PM PDT 24
Finished Jul 21 06:29:03 PM PDT 24
Peak memory 215332 kb
Host smart-cddb205b-8e90-4ac8-b670-874e52d90ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358215242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3358215242
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2284301894
Short name T108
Test name
Test status
Simulation time 3307370371 ps
CPU time 45 seconds
Started Jul 21 06:28:53 PM PDT 24
Finished Jul 21 06:29:38 PM PDT 24
Peak memory 210796 kb
Host smart-0923f132-cf92-4d34-9fd0-896d46a35f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284301894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2284301894
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1054888975
Short name T310
Test name
Test status
Simulation time 16839743979 ps
CPU time 14.78 seconds
Started Jul 21 06:27:13 PM PDT 24
Finished Jul 21 06:27:28 PM PDT 24
Peak memory 211492 kb
Host smart-e1216ca4-1a30-4eb3-8b0a-8f4b658f361f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054888975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1054888975
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4278756000
Short name T286
Test name
Test status
Simulation time 1374718686 ps
CPU time 85.76 seconds
Started Jul 21 06:27:09 PM PDT 24
Finished Jul 21 06:28:35 PM PDT 24
Peak memory 236808 kb
Host smart-17d0ef13-2633-4a61-a8de-b33a2545c56d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278756000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4278756000
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2041326790
Short name T145
Test name
Test status
Simulation time 11287252844 ps
CPU time 19.1 seconds
Started Jul 21 06:27:11 PM PDT 24
Finished Jul 21 06:27:31 PM PDT 24
Peak memory 212320 kb
Host smart-80731350-1ab8-4ab3-a534-df93f4b95858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041326790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2041326790
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1120883822
Short name T300
Test name
Test status
Simulation time 3097692724 ps
CPU time 9.27 seconds
Started Jul 21 06:27:11 PM PDT 24
Finished Jul 21 06:27:21 PM PDT 24
Peak memory 211484 kb
Host smart-b780088e-73f5-4c8d-bcfe-93da5532ad0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120883822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1120883822
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1926051436
Short name T17
Test name
Test status
Simulation time 1484302648 ps
CPU time 100.6 seconds
Started Jul 21 06:27:07 PM PDT 24
Finished Jul 21 06:28:48 PM PDT 24
Peak memory 238316 kb
Host smart-42e450b0-379e-414f-9a22-a4e2455b097c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926051436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1926051436
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1371960206
Short name T296
Test name
Test status
Simulation time 6280036145 ps
CPU time 22.42 seconds
Started Jul 21 06:27:09 PM PDT 24
Finished Jul 21 06:27:32 PM PDT 24
Peak memory 214520 kb
Host smart-344c7427-cc2d-4a1d-b16b-248469457cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371960206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1371960206
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1291156826
Short name T324
Test name
Test status
Simulation time 233852922 ps
CPU time 14.66 seconds
Started Jul 21 06:27:09 PM PDT 24
Finished Jul 21 06:27:24 PM PDT 24
Peak memory 212456 kb
Host smart-d2c27a11-1a89-4ad9-a0bd-c9c63c4ca44b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291156826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1291156826
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3292555711
Short name T321
Test name
Test status
Simulation time 186713949 ps
CPU time 4.29 seconds
Started Jul 21 06:27:13 PM PDT 24
Finished Jul 21 06:27:18 PM PDT 24
Peak memory 211436 kb
Host smart-7ae74c02-2fd9-41ed-99a1-bc6013cf8d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292555711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3292555711
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.847689175
Short name T325
Test name
Test status
Simulation time 114506393970 ps
CPU time 198.68 seconds
Started Jul 21 06:27:14 PM PDT 24
Finished Jul 21 06:30:33 PM PDT 24
Peak memory 237388 kb
Host smart-51e70de5-419d-4079-9387-7069e6d1ad0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847689175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.847689175
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2878936456
Short name T233
Test name
Test status
Simulation time 3171492189 ps
CPU time 15.76 seconds
Started Jul 21 06:27:15 PM PDT 24
Finished Jul 21 06:27:31 PM PDT 24
Peak memory 212100 kb
Host smart-4e48686c-7514-4e22-bf33-851714264c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878936456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2878936456
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2744785910
Short name T235
Test name
Test status
Simulation time 4181398410 ps
CPU time 11.69 seconds
Started Jul 21 06:27:15 PM PDT 24
Finished Jul 21 06:27:27 PM PDT 24
Peak memory 211444 kb
Host smart-a402f7b9-bf70-49f4-a1c9-bd89110aa3eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744785910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2744785910
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.878100955
Short name T303
Test name
Test status
Simulation time 4073648876 ps
CPU time 23.22 seconds
Started Jul 21 06:27:09 PM PDT 24
Finished Jul 21 06:27:33 PM PDT 24
Peak memory 212536 kb
Host smart-4ea5378b-3046-42a8-8af2-1af812db9975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878100955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.878100955
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1909218041
Short name T162
Test name
Test status
Simulation time 13032540899 ps
CPU time 39.79 seconds
Started Jul 21 06:27:14 PM PDT 24
Finished Jul 21 06:27:54 PM PDT 24
Peak memory 214840 kb
Host smart-5c25a330-4124-4d2b-a9ee-f21e717035f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909218041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1909218041
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2811168506
Short name T65
Test name
Test status
Simulation time 1010159544 ps
CPU time 7.21 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:27:39 PM PDT 24
Peak memory 211344 kb
Host smart-a72d6ecb-a96a-41e6-98d1-8df46ecaa2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811168506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2811168506
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4249870881
Short name T8
Test name
Test status
Simulation time 15863667896 ps
CPU time 171.25 seconds
Started Jul 21 06:27:22 PM PDT 24
Finished Jul 21 06:30:14 PM PDT 24
Peak memory 228500 kb
Host smart-c0477283-126c-4a9b-9947-235b1e962cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249870881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4249870881
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2880850101
Short name T340
Test name
Test status
Simulation time 1100561039 ps
CPU time 16.27 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:46 PM PDT 24
Peak memory 211948 kb
Host smart-c1055a84-1b82-461d-9f19-6edbce967370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880850101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2880850101
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3224637754
Short name T152
Test name
Test status
Simulation time 3377000276 ps
CPU time 20.62 seconds
Started Jul 21 06:27:24 PM PDT 24
Finished Jul 21 06:27:46 PM PDT 24
Peak memory 213128 kb
Host smart-ffa79938-4c54-41e9-bf66-a174dbee6661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224637754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3224637754
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.770149914
Short name T121
Test name
Test status
Simulation time 9333619595 ps
CPU time 26.94 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:57 PM PDT 24
Peak memory 219568 kb
Host smart-dfe08430-0690-4d8a-b5a0-689cf29e33bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770149914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.770149914
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1357772976
Short name T64
Test name
Test status
Simulation time 4204158680 ps
CPU time 10.35 seconds
Started Jul 21 06:27:31 PM PDT 24
Finished Jul 21 06:27:44 PM PDT 24
Peak memory 211424 kb
Host smart-bd2f5ac5-a9fb-410b-b128-b0b6ef5cd987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357772976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1357772976
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4010874038
Short name T276
Test name
Test status
Simulation time 1157767123 ps
CPU time 12.09 seconds
Started Jul 21 06:27:27 PM PDT 24
Finished Jul 21 06:27:40 PM PDT 24
Peak memory 211400 kb
Host smart-4383ab68-d3bc-4705-b0a6-8b264244d37c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010874038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4010874038
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3802100287
Short name T82
Test name
Test status
Simulation time 37205878118 ps
CPU time 35.29 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:28:06 PM PDT 24
Peak memory 214140 kb
Host smart-acfa6153-128c-4402-9301-8e3c80badd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802100287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3802100287
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.406706244
Short name T349
Test name
Test status
Simulation time 3762036939 ps
CPU time 28.11 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:28:00 PM PDT 24
Peak memory 213260 kb
Host smart-73b4c5d8-8b10-41f6-86a3-d4b643cdb484
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406706244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.406706244
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.722895082
Short name T256
Test name
Test status
Simulation time 1566057551 ps
CPU time 13.53 seconds
Started Jul 21 06:27:26 PM PDT 24
Finished Jul 21 06:27:40 PM PDT 24
Peak memory 211324 kb
Host smart-6f58fa19-0b91-4629-adef-a1bf1b0a67ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722895082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.722895082
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1458497071
Short name T158
Test name
Test status
Simulation time 28972239031 ps
CPU time 158.87 seconds
Started Jul 21 06:27:27 PM PDT 24
Finished Jul 21 06:30:07 PM PDT 24
Peak memory 234960 kb
Host smart-4bad2477-adb5-4709-a34c-c9f38aefeec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458497071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1458497071
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.961619782
Short name T326
Test name
Test status
Simulation time 451200218 ps
CPU time 5.25 seconds
Started Jul 21 06:27:34 PM PDT 24
Finished Jul 21 06:27:40 PM PDT 24
Peak memory 211364 kb
Host smart-f9090e16-df33-4d9e-a990-8af11505925f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961619782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.961619782
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4268154941
Short name T122
Test name
Test status
Simulation time 7679921254 ps
CPU time 30.76 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:28:03 PM PDT 24
Peak memory 214980 kb
Host smart-670e73c1-6add-4e90-8003-92186440ea53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268154941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4268154941
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1606087096
Short name T271
Test name
Test status
Simulation time 8525523144 ps
CPU time 77.06 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:28:47 PM PDT 24
Peak memory 215464 kb
Host smart-a5a3ce9a-107e-441e-a2d0-e1989d0dd8b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606087096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1606087096
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3358814494
Short name T314
Test name
Test status
Simulation time 163215356241 ps
CPU time 383.13 seconds
Started Jul 21 06:27:31 PM PDT 24
Finished Jul 21 06:33:56 PM PDT 24
Peak memory 212644 kb
Host smart-48483bb5-8ac5-4786-a4a8-043a60fdd0b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358814494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3358814494
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2200577670
Short name T280
Test name
Test status
Simulation time 7798655037 ps
CPU time 27.12 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:58 PM PDT 24
Peak memory 212128 kb
Host smart-bc052b3f-4fe3-4478-a114-4e4f7f46622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200577670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2200577670
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2056221661
Short name T206
Test name
Test status
Simulation time 22713250438 ps
CPU time 17.31 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:48 PM PDT 24
Peak memory 211380 kb
Host smart-ceace732-18d4-4bbd-92a3-7ebcc9ba338d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056221661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2056221661
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1765991099
Short name T174
Test name
Test status
Simulation time 2422156522 ps
CPU time 22.81 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:54 PM PDT 24
Peak memory 213532 kb
Host smart-f563e030-e477-43c6-89f0-d11e3b2f3990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765991099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1765991099
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4248468040
Short name T127
Test name
Test status
Simulation time 5367611994 ps
CPU time 25.12 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:56 PM PDT 24
Peak memory 214308 kb
Host smart-02854f6a-676f-4e04-8c86-f2056412590e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248468040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4248468040
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3098711299
Short name T163
Test name
Test status
Simulation time 1664841186 ps
CPU time 12.77 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:44 PM PDT 24
Peak memory 211432 kb
Host smart-697ac986-3b24-4548-9c39-003f52f9895e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098711299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3098711299
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.696495121
Short name T172
Test name
Test status
Simulation time 35679682128 ps
CPU time 266.23 seconds
Started Jul 21 06:27:27 PM PDT 24
Finished Jul 21 06:31:54 PM PDT 24
Peak memory 228636 kb
Host smart-66529a2d-2566-448a-9497-147f7f56238b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696495121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.696495121
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.649050963
Short name T167
Test name
Test status
Simulation time 2555750488 ps
CPU time 24.9 seconds
Started Jul 21 06:27:33 PM PDT 24
Finished Jul 21 06:27:59 PM PDT 24
Peak memory 212056 kb
Host smart-d09aa08e-130c-4464-9f13-85fd01794d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649050963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.649050963
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3856428892
Short name T234
Test name
Test status
Simulation time 5739674776 ps
CPU time 14.5 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:27:46 PM PDT 24
Peak memory 211464 kb
Host smart-cf767262-894c-478e-971e-927c763537a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856428892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3856428892
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1077795219
Short name T78
Test name
Test status
Simulation time 2673980461 ps
CPU time 19.24 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:50 PM PDT 24
Peak memory 215164 kb
Host smart-041ad007-a94c-46fc-8c28-ec484bf1ddbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077795219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1077795219
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1843449992
Short name T188
Test name
Test status
Simulation time 392730826 ps
CPU time 6.61 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:27:38 PM PDT 24
Peak memory 211372 kb
Host smart-ba95b7fb-5de7-41a5-b084-8e06efb7ff5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843449992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1843449992
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2732292807
Short name T183
Test name
Test status
Simulation time 3682035025 ps
CPU time 146.77 seconds
Started Jul 21 06:27:36 PM PDT 24
Finished Jul 21 06:30:03 PM PDT 24
Peak memory 225740 kb
Host smart-fa76f886-0ade-4ea2-9e31-51c2097e097a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732292807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2732292807
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4059237591
Short name T220
Test name
Test status
Simulation time 22846937808 ps
CPU time 29.67 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:28:02 PM PDT 24
Peak memory 212804 kb
Host smart-a4721e7d-6160-49db-990a-fa9422a32648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059237591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4059237591
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.552021102
Short name T285
Test name
Test status
Simulation time 3405477847 ps
CPU time 15.48 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:27:47 PM PDT 24
Peak memory 211496 kb
Host smart-e2363bc0-9021-4e9a-bf38-f9c8923fcc7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552021102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.552021102
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.748134419
Short name T101
Test name
Test status
Simulation time 361456972 ps
CPU time 9.86 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:27:42 PM PDT 24
Peak memory 212864 kb
Host smart-e4f11a3b-faba-493e-a2bc-60534302d90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748134419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.748134419
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1210238979
Short name T80
Test name
Test status
Simulation time 2779062204 ps
CPU time 43.1 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:28:15 PM PDT 24
Peak memory 214644 kb
Host smart-99dec6fe-9467-46c1-bd29-a634c441800b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210238979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1210238979
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.716202404
Short name T21
Test name
Test status
Simulation time 2163178443 ps
CPU time 17.14 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:48 PM PDT 24
Peak memory 211412 kb
Host smart-a425fea9-71f3-4f07-a329-325602e075e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716202404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.716202404
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3195877729
Short name T33
Test name
Test status
Simulation time 15012254665 ps
CPU time 30.92 seconds
Started Jul 21 06:27:30 PM PDT 24
Finished Jul 21 06:28:04 PM PDT 24
Peak memory 212368 kb
Host smart-26240028-0af2-4a67-9021-2238b7b494ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195877729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3195877729
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3288253432
Short name T117
Test name
Test status
Simulation time 1236644625 ps
CPU time 12.18 seconds
Started Jul 21 06:27:31 PM PDT 24
Finished Jul 21 06:27:45 PM PDT 24
Peak memory 211408 kb
Host smart-6be89629-2606-42b2-9898-2af0d657f018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288253432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3288253432
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3076338919
Short name T301
Test name
Test status
Simulation time 1994038044 ps
CPU time 26.39 seconds
Started Jul 21 06:27:31 PM PDT 24
Finished Jul 21 06:27:59 PM PDT 24
Peak memory 212884 kb
Host smart-be4bffb6-b836-442d-8f90-1c60c4e39388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076338919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3076338919
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2958770277
Short name T338
Test name
Test status
Simulation time 8849803406 ps
CPU time 50.21 seconds
Started Jul 21 06:27:33 PM PDT 24
Finished Jul 21 06:28:25 PM PDT 24
Peak memory 213920 kb
Host smart-05b1e417-433e-43bd-b88a-52d688697324
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958770277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2958770277
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2097977287
Short name T204
Test name
Test status
Simulation time 2000813412 ps
CPU time 15.36 seconds
Started Jul 21 06:27:35 PM PDT 24
Finished Jul 21 06:27:51 PM PDT 24
Peak memory 211360 kb
Host smart-e72291f6-c10c-4702-a52d-8469ef9c5b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097977287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2097977287
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1538692033
Short name T335
Test name
Test status
Simulation time 148665696272 ps
CPU time 347.37 seconds
Started Jul 21 06:27:33 PM PDT 24
Finished Jul 21 06:33:22 PM PDT 24
Peak memory 212804 kb
Host smart-bfc186c7-8f06-4923-8241-491520320ad6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538692033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1538692033
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.394124887
Short name T132
Test name
Test status
Simulation time 14924301680 ps
CPU time 32.86 seconds
Started Jul 21 06:27:27 PM PDT 24
Finished Jul 21 06:28:01 PM PDT 24
Peak memory 212552 kb
Host smart-07866b3c-2e3f-4001-9a9f-059106298179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394124887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.394124887
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2175041625
Short name T205
Test name
Test status
Simulation time 5903153271 ps
CPU time 13.41 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:27:46 PM PDT 24
Peak memory 211444 kb
Host smart-dd157179-d581-4b9b-89c8-d7c9ff5466b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2175041625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2175041625
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2342934953
Short name T218
Test name
Test status
Simulation time 691989893 ps
CPU time 10.17 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:27:41 PM PDT 24
Peak memory 213528 kb
Host smart-d5f2c3fd-4cac-4ab5-a583-f2e3adbf05e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342934953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2342934953
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3023633065
Short name T238
Test name
Test status
Simulation time 16483856536 ps
CPU time 27.49 seconds
Started Jul 21 06:27:29 PM PDT 24
Finished Jul 21 06:28:00 PM PDT 24
Peak memory 215916 kb
Host smart-e8d9408f-df53-4a70-98e5-d7e5f2e99fa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023633065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3023633065
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.249900375
Short name T54
Test name
Test status
Simulation time 18978976702 ps
CPU time 2997.37 seconds
Started Jul 21 06:27:33 PM PDT 24
Finished Jul 21 07:17:32 PM PDT 24
Peak memory 235924 kb
Host smart-43bbd27b-2e13-4fd9-9ad2-4cf91f74a224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249900375 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.249900375
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.171772104
Short name T68
Test name
Test status
Simulation time 14200163608 ps
CPU time 16.12 seconds
Started Jul 21 06:27:37 PM PDT 24
Finished Jul 21 06:27:54 PM PDT 24
Peak memory 211400 kb
Host smart-1683cedd-3479-42d1-9a5a-7b9b56d154ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171772104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.171772104
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1746267235
Short name T15
Test name
Test status
Simulation time 110354696046 ps
CPU time 245.95 seconds
Started Jul 21 06:27:42 PM PDT 24
Finished Jul 21 06:31:49 PM PDT 24
Peak memory 212720 kb
Host smart-fd7216ee-e91f-435a-a8a8-f3ab0bd811d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746267235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1746267235
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.647864277
Short name T31
Test name
Test status
Simulation time 7042682430 ps
CPU time 27.19 seconds
Started Jul 21 06:27:34 PM PDT 24
Finished Jul 21 06:28:02 PM PDT 24
Peak memory 212612 kb
Host smart-a9f57380-426c-45aa-9e6e-50f3065627fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647864277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.647864277
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1991885602
Short name T319
Test name
Test status
Simulation time 961782011 ps
CPU time 8.49 seconds
Started Jul 21 06:27:35 PM PDT 24
Finished Jul 21 06:27:44 PM PDT 24
Peak memory 211384 kb
Host smart-2d625120-48fa-4813-a480-49f2783b3f8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991885602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1991885602
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1041982307
Short name T266
Test name
Test status
Simulation time 8506384871 ps
CPU time 28.55 seconds
Started Jul 21 06:27:34 PM PDT 24
Finished Jul 21 06:28:04 PM PDT 24
Peak memory 214716 kb
Host smart-060ea57a-086d-4f6e-8184-4b2e6e117b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041982307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1041982307
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2068167514
Short name T240
Test name
Test status
Simulation time 1644063525 ps
CPU time 23.37 seconds
Started Jul 21 06:27:36 PM PDT 24
Finished Jul 21 06:28:00 PM PDT 24
Peak memory 216192 kb
Host smart-59f4b6f9-8aaa-4087-a568-aa2ef76ef992
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068167514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2068167514
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3409628352
Short name T224
Test name
Test status
Simulation time 4217034846 ps
CPU time 14.53 seconds
Started Jul 21 06:27:35 PM PDT 24
Finished Jul 21 06:27:50 PM PDT 24
Peak memory 211392 kb
Host smart-8d1b1a66-51ab-454b-9293-c75d61f5613c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409628352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3409628352
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4294070795
Short name T153
Test name
Test status
Simulation time 10243596543 ps
CPU time 181.79 seconds
Started Jul 21 06:27:33 PM PDT 24
Finished Jul 21 06:30:36 PM PDT 24
Peak memory 233256 kb
Host smart-3c5e0145-36b6-4853-ad58-6ee547409441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294070795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4294070795
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4025954201
Short name T159
Test name
Test status
Simulation time 3209508176 ps
CPU time 28.1 seconds
Started Jul 21 06:27:36 PM PDT 24
Finished Jul 21 06:28:04 PM PDT 24
Peak memory 211896 kb
Host smart-dc2ba892-3035-442e-96d0-0e8e03658ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025954201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4025954201
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.594179642
Short name T9
Test name
Test status
Simulation time 4175766222 ps
CPU time 16.66 seconds
Started Jul 21 06:27:34 PM PDT 24
Finished Jul 21 06:27:52 PM PDT 24
Peak memory 211392 kb
Host smart-0d2d1ae0-40e0-4402-b5eb-33a1c816e91f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=594179642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.594179642
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.329253784
Short name T171
Test name
Test status
Simulation time 717433696 ps
CPU time 9.75 seconds
Started Jul 21 06:27:36 PM PDT 24
Finished Jul 21 06:27:46 PM PDT 24
Peak memory 213680 kb
Host smart-a27a87be-7025-4d1b-960e-dcd22ef84c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329253784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.329253784
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2237682462
Short name T297
Test name
Test status
Simulation time 5764022167 ps
CPU time 29.11 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:28:12 PM PDT 24
Peak memory 214188 kb
Host smart-87303480-2579-4e7a-a579-b0d6534a3207
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237682462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2237682462
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2044976977
Short name T56
Test name
Test status
Simulation time 33584482636 ps
CPU time 1370.61 seconds
Started Jul 21 06:27:32 PM PDT 24
Finished Jul 21 06:50:25 PM PDT 24
Peak memory 235836 kb
Host smart-8f98ab39-1cd7-4868-bcdc-12c4cb3c1ede
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044976977 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2044976977
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2546245659
Short name T139
Test name
Test status
Simulation time 4915566657 ps
CPU time 11.57 seconds
Started Jul 21 06:27:16 PM PDT 24
Finished Jul 21 06:27:28 PM PDT 24
Peak memory 211440 kb
Host smart-f39b2254-057c-4ba3-89cd-0811bf32138d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546245659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2546245659
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2699545577
Short name T51
Test name
Test status
Simulation time 69037684439 ps
CPU time 169.85 seconds
Started Jul 21 06:27:15 PM PDT 24
Finished Jul 21 06:30:06 PM PDT 24
Peak memory 236784 kb
Host smart-9dce0374-8561-4c06-b204-b7250bc6899e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699545577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2699545577
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3287488204
Short name T141
Test name
Test status
Simulation time 9153524611 ps
CPU time 23.46 seconds
Started Jul 21 06:27:14 PM PDT 24
Finished Jul 21 06:27:39 PM PDT 24
Peak memory 212476 kb
Host smart-8b0c278c-b1ec-4f06-8871-63764272aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287488204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3287488204
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.96477850
Short name T282
Test name
Test status
Simulation time 1345748229 ps
CPU time 7.22 seconds
Started Jul 21 06:27:15 PM PDT 24
Finished Jul 21 06:27:23 PM PDT 24
Peak memory 211344 kb
Host smart-40790986-e367-41b3-8827-3c38797f5d08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96477850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.96477850
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2695551831
Short name T26
Test name
Test status
Simulation time 166650270 ps
CPU time 51.89 seconds
Started Jul 21 06:27:16 PM PDT 24
Finished Jul 21 06:28:08 PM PDT 24
Peak memory 235804 kb
Host smart-8e9209d3-b6a7-4501-a530-39917742f884
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695551831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2695551831
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.494223229
Short name T260
Test name
Test status
Simulation time 1650643619 ps
CPU time 10.66 seconds
Started Jul 21 06:27:14 PM PDT 24
Finished Jul 21 06:27:26 PM PDT 24
Peak memory 213980 kb
Host smart-23c1cca9-ea94-4192-801c-8851c2da1ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494223229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.494223229
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2642428798
Short name T180
Test name
Test status
Simulation time 800429254 ps
CPU time 15.69 seconds
Started Jul 21 06:27:14 PM PDT 24
Finished Jul 21 06:27:31 PM PDT 24
Peak memory 212640 kb
Host smart-687a3c4b-3c03-4f1f-afae-d5d7eaee9351
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642428798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2642428798
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2051478740
Short name T351
Test name
Test status
Simulation time 89182365 ps
CPU time 4.34 seconds
Started Jul 21 06:27:36 PM PDT 24
Finished Jul 21 06:27:41 PM PDT 24
Peak memory 211308 kb
Host smart-fa3f0239-4fa9-4927-a0ca-40caf75cafc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051478740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2051478740
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2679978167
Short name T226
Test name
Test status
Simulation time 41158524030 ps
CPU time 406.24 seconds
Started Jul 21 06:27:37 PM PDT 24
Finished Jul 21 06:34:24 PM PDT 24
Peak memory 238096 kb
Host smart-18921864-4e96-462d-be07-23dd17adba74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679978167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2679978167
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2786590737
Short name T273
Test name
Test status
Simulation time 6774074333 ps
CPU time 27.83 seconds
Started Jul 21 06:27:35 PM PDT 24
Finished Jul 21 06:28:04 PM PDT 24
Peak memory 212524 kb
Host smart-3aaa9ace-2b1d-4349-92df-bc64265c2da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786590737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2786590737
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3864242377
Short name T225
Test name
Test status
Simulation time 2061740353 ps
CPU time 16.29 seconds
Started Jul 21 06:27:33 PM PDT 24
Finished Jul 21 06:27:50 PM PDT 24
Peak memory 211376 kb
Host smart-7d88ff85-010e-426b-abe6-33d6841c1d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864242377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3864242377
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1603217303
Short name T184
Test name
Test status
Simulation time 1246712702 ps
CPU time 18.03 seconds
Started Jul 21 06:27:35 PM PDT 24
Finished Jul 21 06:27:54 PM PDT 24
Peak memory 213364 kb
Host smart-ac264f77-4908-48af-b102-54a310eb5ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603217303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1603217303
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2388089121
Short name T203
Test name
Test status
Simulation time 811357117 ps
CPU time 34.08 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:28:17 PM PDT 24
Peak memory 215256 kb
Host smart-727c9cec-b91b-4bc5-bd18-e38723b575ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388089121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2388089121
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1913068103
Short name T12
Test name
Test status
Simulation time 23620901853 ps
CPU time 4863.45 seconds
Started Jul 21 06:27:34 PM PDT 24
Finished Jul 21 07:48:39 PM PDT 24
Peak memory 235816 kb
Host smart-35f744a5-70a0-4869-b3a5-2abe35adba80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913068103 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1913068103
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.685627624
Short name T287
Test name
Test status
Simulation time 85508437 ps
CPU time 4.31 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:27:47 PM PDT 24
Peak memory 211376 kb
Host smart-30817670-53b0-4b3e-90bd-67a3ae091a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685627624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.685627624
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.448333367
Short name T315
Test name
Test status
Simulation time 7387715728 ps
CPU time 148.77 seconds
Started Jul 21 06:27:33 PM PDT 24
Finished Jul 21 06:30:03 PM PDT 24
Peak memory 212692 kb
Host smart-50f89807-ed65-4060-97c9-efb87b4cbc19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448333367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.448333367
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1114333403
Short name T327
Test name
Test status
Simulation time 3098494006 ps
CPU time 27.54 seconds
Started Jul 21 06:27:36 PM PDT 24
Finished Jul 21 06:28:05 PM PDT 24
Peak memory 211444 kb
Host smart-28673150-79db-4277-8d25-13dea1023667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114333403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1114333403
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3787721050
Short name T339
Test name
Test status
Simulation time 1158228163 ps
CPU time 11.81 seconds
Started Jul 21 06:27:43 PM PDT 24
Finished Jul 21 06:27:55 PM PDT 24
Peak memory 211420 kb
Host smart-c75db787-b48b-449c-ade8-b659d5124646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787721050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3787721050
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1225924533
Short name T79
Test name
Test status
Simulation time 3384760592 ps
CPU time 32.5 seconds
Started Jul 21 06:27:36 PM PDT 24
Finished Jul 21 06:28:09 PM PDT 24
Peak memory 213408 kb
Host smart-9ac4a6cf-addb-4a1c-b087-10981b1177e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225924533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1225924533
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1660451765
Short name T7
Test name
Test status
Simulation time 68740796944 ps
CPU time 68.94 seconds
Started Jul 21 06:27:37 PM PDT 24
Finished Jul 21 06:28:46 PM PDT 24
Peak memory 217092 kb
Host smart-34cfcea6-0ccf-4eb8-9dcc-de2fbfc1e014
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660451765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1660451765
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2623992306
Short name T355
Test name
Test status
Simulation time 591992977 ps
CPU time 4.23 seconds
Started Jul 21 06:27:40 PM PDT 24
Finished Jul 21 06:27:45 PM PDT 24
Peak memory 211392 kb
Host smart-4b8fc905-d4c0-4b88-91ec-46f3a0e27ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623992306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2623992306
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1539290623
Short name T37
Test name
Test status
Simulation time 36791155547 ps
CPU time 366.03 seconds
Started Jul 21 06:27:40 PM PDT 24
Finished Jul 21 06:33:47 PM PDT 24
Peak memory 228700 kb
Host smart-3838d096-2566-430d-9237-7492912b9766
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539290623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1539290623
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3081932046
Short name T268
Test name
Test status
Simulation time 8823258114 ps
CPU time 24.5 seconds
Started Jul 21 06:27:42 PM PDT 24
Finished Jul 21 06:28:08 PM PDT 24
Peak memory 212316 kb
Host smart-3414ae97-6f55-4ff5-a8f0-e07ef0900458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081932046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3081932046
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2277444415
Short name T245
Test name
Test status
Simulation time 752904614 ps
CPU time 9.57 seconds
Started Jul 21 06:27:36 PM PDT 24
Finished Jul 21 06:27:46 PM PDT 24
Peak memory 211384 kb
Host smart-6cda9612-3de3-4605-b1bc-ee78c5904fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2277444415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2277444415
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2405671332
Short name T81
Test name
Test status
Simulation time 8178778087 ps
CPU time 45.86 seconds
Started Jul 21 06:27:33 PM PDT 24
Finished Jul 21 06:28:20 PM PDT 24
Peak memory 214452 kb
Host smart-5e81e23f-1dd6-4961-9e74-633303f06a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405671332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2405671332
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3033818707
Short name T151
Test name
Test status
Simulation time 3918617016 ps
CPU time 31.79 seconds
Started Jul 21 06:27:34 PM PDT 24
Finished Jul 21 06:28:07 PM PDT 24
Peak memory 216944 kb
Host smart-6daa1c03-d14f-4fb9-bd18-f13a3f6ae5b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033818707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3033818707
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.307544642
Short name T346
Test name
Test status
Simulation time 57160019561 ps
CPU time 3194.74 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 07:20:58 PM PDT 24
Peak memory 235852 kb
Host smart-0d90be06-2d20-4def-8a0f-26b511888c99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307544642 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.307544642
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.917953579
Short name T190
Test name
Test status
Simulation time 2688985638 ps
CPU time 8.17 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:27:50 PM PDT 24
Peak memory 211428 kb
Host smart-bce12884-e860-4e3d-9963-3fa46cbc9db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917953579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.917953579
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3114834635
Short name T264
Test name
Test status
Simulation time 1152479869 ps
CPU time 65.9 seconds
Started Jul 21 06:27:40 PM PDT 24
Finished Jul 21 06:28:47 PM PDT 24
Peak memory 237724 kb
Host smart-819931d0-c5bc-439a-b271-64be3a678600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114834635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3114834635
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2465033371
Short name T295
Test name
Test status
Simulation time 1526454026 ps
CPU time 16.07 seconds
Started Jul 21 06:27:43 PM PDT 24
Finished Jul 21 06:28:00 PM PDT 24
Peak memory 212260 kb
Host smart-605f196e-d378-404d-b7aa-adb5cbe2fb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465033371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2465033371
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3466762754
Short name T168
Test name
Test status
Simulation time 181929794 ps
CPU time 6.6 seconds
Started Jul 21 06:27:40 PM PDT 24
Finished Jul 21 06:27:47 PM PDT 24
Peak memory 211344 kb
Host smart-f5b7d146-fc09-4305-8bc4-862eb3ab4191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466762754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3466762754
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4114006109
Short name T236
Test name
Test status
Simulation time 5863421050 ps
CPU time 34.8 seconds
Started Jul 21 06:27:42 PM PDT 24
Finished Jul 21 06:28:18 PM PDT 24
Peak memory 214112 kb
Host smart-1283bf57-6223-4d0e-a299-ab245943d05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114006109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4114006109
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1031780360
Short name T307
Test name
Test status
Simulation time 531971790 ps
CPU time 8.68 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:27:51 PM PDT 24
Peak memory 211192 kb
Host smart-cc959bd4-adf5-4697-9151-231a6433ba14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031780360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1031780360
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2401673651
Short name T177
Test name
Test status
Simulation time 1305246131 ps
CPU time 8.53 seconds
Started Jul 21 06:27:43 PM PDT 24
Finished Jul 21 06:27:52 PM PDT 24
Peak memory 211384 kb
Host smart-036ba58f-791d-4e69-a0d0-f1fea6e4b436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401673651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2401673651
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.823967093
Short name T255
Test name
Test status
Simulation time 129152177648 ps
CPU time 306.03 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:32:48 PM PDT 24
Peak memory 237892 kb
Host smart-127558e9-c163-465b-9f8b-a9f133de6ed9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823967093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.823967093
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3691827967
Short name T44
Test name
Test status
Simulation time 1109422528 ps
CPU time 9.43 seconds
Started Jul 21 06:27:43 PM PDT 24
Finished Jul 21 06:27:53 PM PDT 24
Peak memory 211932 kb
Host smart-d7f6cfd6-1505-4888-a7ff-0803b97c27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691827967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3691827967
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.790241237
Short name T317
Test name
Test status
Simulation time 2238106612 ps
CPU time 17.79 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:28:01 PM PDT 24
Peak memory 211460 kb
Host smart-0a76be76-f23d-4756-bf79-d84064a3a98c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=790241237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.790241237
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3101309430
Short name T165
Test name
Test status
Simulation time 3313630369 ps
CPU time 28.17 seconds
Started Jul 21 06:27:44 PM PDT 24
Finished Jul 21 06:28:12 PM PDT 24
Peak memory 213380 kb
Host smart-57ec4b0e-55fd-4783-98b4-65db502beaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101309430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3101309430
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1205322589
Short name T1
Test name
Test status
Simulation time 8914781536 ps
CPU time 99.11 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:29:21 PM PDT 24
Peak memory 218004 kb
Host smart-3027002f-e61e-4c61-9484-f9fa17775381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205322589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1205322589
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1977946728
Short name T11
Test name
Test status
Simulation time 22482473478 ps
CPU time 878.23 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:42:21 PM PDT 24
Peak memory 233584 kb
Host smart-4e8111f6-99a3-4194-aab4-36d94045b394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977946728 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1977946728
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.396093604
Short name T277
Test name
Test status
Simulation time 7160063733 ps
CPU time 13.61 seconds
Started Jul 21 06:27:40 PM PDT 24
Finished Jul 21 06:27:55 PM PDT 24
Peak memory 211428 kb
Host smart-4b2cbc33-d045-4166-8bc2-cf0ac9251f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396093604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.396093604
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.545409572
Short name T41
Test name
Test status
Simulation time 86032186049 ps
CPU time 246.88 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:31:48 PM PDT 24
Peak memory 240092 kb
Host smart-7141715d-ae37-4fa1-8386-9e787cbcc72c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545409572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.545409572
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3982239438
Short name T161
Test name
Test status
Simulation time 10832191418 ps
CPU time 35.76 seconds
Started Jul 21 06:27:42 PM PDT 24
Finished Jul 21 06:28:19 PM PDT 24
Peak memory 212200 kb
Host smart-60673668-d3f6-4b3a-b904-1023c370ef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982239438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3982239438
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2997041633
Short name T330
Test name
Test status
Simulation time 383853471 ps
CPU time 5.54 seconds
Started Jul 21 06:27:40 PM PDT 24
Finished Jul 21 06:27:46 PM PDT 24
Peak memory 211400 kb
Host smart-1200b51d-26f9-411d-899d-824c59612eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2997041633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2997041633
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2846988231
Short name T294
Test name
Test status
Simulation time 357672243 ps
CPU time 9.92 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:27:52 PM PDT 24
Peak memory 213868 kb
Host smart-717a7f30-388a-41a9-8aeb-7b7e03ab3eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846988231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2846988231
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3346003563
Short name T252
Test name
Test status
Simulation time 406397320 ps
CPU time 21.2 seconds
Started Jul 21 06:27:40 PM PDT 24
Finished Jul 21 06:28:02 PM PDT 24
Peak memory 215256 kb
Host smart-8d3d57cb-c5ae-4406-84c5-fa3cf39c6c80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346003563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3346003563
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.4212607263
Short name T354
Test name
Test status
Simulation time 389357289139 ps
CPU time 1834.39 seconds
Started Jul 21 06:27:42 PM PDT 24
Finished Jul 21 06:58:18 PM PDT 24
Peak memory 235920 kb
Host smart-10465ddd-4f6a-4540-b017-1d9cf84eb83d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212607263 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.4212607263
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2962205165
Short name T241
Test name
Test status
Simulation time 1822225656 ps
CPU time 15.29 seconds
Started Jul 21 06:27:48 PM PDT 24
Finished Jul 21 06:28:04 PM PDT 24
Peak memory 211340 kb
Host smart-f03fd160-1cd9-4c1b-8f2c-63317ac3b170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962205165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2962205165
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.456470952
Short name T48
Test name
Test status
Simulation time 8563931868 ps
CPU time 136.29 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:29:59 PM PDT 24
Peak memory 238164 kb
Host smart-e06b1289-bc60-4e7a-af4a-d1a8a5bedf86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456470952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.456470952
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1051201674
Short name T123
Test name
Test status
Simulation time 16796940476 ps
CPU time 35.45 seconds
Started Jul 21 06:27:46 PM PDT 24
Finished Jul 21 06:28:22 PM PDT 24
Peak memory 212280 kb
Host smart-d725d281-3ea0-4612-88ae-048290aaefbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051201674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1051201674
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1976774704
Short name T270
Test name
Test status
Simulation time 5443829416 ps
CPU time 12.12 seconds
Started Jul 21 06:27:42 PM PDT 24
Finished Jul 21 06:27:55 PM PDT 24
Peak memory 211508 kb
Host smart-dcd8670c-9e81-4f4c-97a0-c3590a64a79e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976774704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1976774704
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1002387854
Short name T247
Test name
Test status
Simulation time 1272448616 ps
CPU time 9.91 seconds
Started Jul 21 06:27:42 PM PDT 24
Finished Jul 21 06:27:53 PM PDT 24
Peak memory 213712 kb
Host smart-b55901d5-de27-4b5c-9f40-4a55ceda4f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002387854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1002387854
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2843407088
Short name T290
Test name
Test status
Simulation time 4065977752 ps
CPU time 39.37 seconds
Started Jul 21 06:27:41 PM PDT 24
Finished Jul 21 06:28:21 PM PDT 24
Peak memory 213776 kb
Host smart-9a6a7f37-67d3-451c-85ca-7ce28664fd8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843407088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2843407088
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2053778785
Short name T249
Test name
Test status
Simulation time 7843316128 ps
CPU time 13.91 seconds
Started Jul 21 06:27:51 PM PDT 24
Finished Jul 21 06:28:05 PM PDT 24
Peak memory 211336 kb
Host smart-7a907ddc-9599-475c-9e60-e997c6c96483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053778785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2053778785
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2789842767
Short name T50
Test name
Test status
Simulation time 106638792383 ps
CPU time 140.49 seconds
Started Jul 21 06:27:47 PM PDT 24
Finished Jul 21 06:30:09 PM PDT 24
Peak memory 212656 kb
Host smart-125af98a-830c-47fa-abbd-5a6ff9781655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789842767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2789842767
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3184737531
Short name T207
Test name
Test status
Simulation time 291667727 ps
CPU time 11 seconds
Started Jul 21 06:27:47 PM PDT 24
Finished Jul 21 06:27:59 PM PDT 24
Peak memory 212072 kb
Host smart-e4cdce7f-9537-4cab-9893-84ee1de60189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184737531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3184737531
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2682173588
Short name T333
Test name
Test status
Simulation time 2224837594 ps
CPU time 12.7 seconds
Started Jul 21 06:27:47 PM PDT 24
Finished Jul 21 06:28:00 PM PDT 24
Peak memory 211492 kb
Host smart-9224fb23-2270-4048-b042-ac78dd285a77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682173588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2682173588
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2898255864
Short name T258
Test name
Test status
Simulation time 3822117950 ps
CPU time 16.66 seconds
Started Jul 21 06:27:46 PM PDT 24
Finished Jul 21 06:28:03 PM PDT 24
Peak memory 214048 kb
Host smart-726ccd30-4759-4a93-b6e2-898fb7c6c907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898255864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2898255864
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2058239980
Short name T216
Test name
Test status
Simulation time 892966402 ps
CPU time 12.86 seconds
Started Jul 21 06:27:48 PM PDT 24
Finished Jul 21 06:28:02 PM PDT 24
Peak memory 212168 kb
Host smart-f8ac06af-1aa8-49d4-a9a6-43d22e8c0e5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058239980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2058239980
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3914386425
Short name T52
Test name
Test status
Simulation time 184436830608 ps
CPU time 1760.69 seconds
Started Jul 21 06:27:49 PM PDT 24
Finished Jul 21 06:57:11 PM PDT 24
Peak memory 235948 kb
Host smart-dfe3e430-09f0-46f8-95b9-e2db8356b41f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914386425 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3914386425
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2978300425
Short name T176
Test name
Test status
Simulation time 2136679366 ps
CPU time 16.85 seconds
Started Jul 21 06:27:48 PM PDT 24
Finished Jul 21 06:28:06 PM PDT 24
Peak memory 211368 kb
Host smart-2a79d7c9-8659-4117-a53a-3bb5127120ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978300425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2978300425
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3191187582
Short name T311
Test name
Test status
Simulation time 23938987353 ps
CPU time 234.98 seconds
Started Jul 21 06:27:49 PM PDT 24
Finished Jul 21 06:31:45 PM PDT 24
Peak memory 224636 kb
Host smart-112686c8-fdab-4863-bfc7-4f1b363f11d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191187582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3191187582
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2533425991
Short name T283
Test name
Test status
Simulation time 4775541917 ps
CPU time 16.65 seconds
Started Jul 21 06:27:47 PM PDT 24
Finished Jul 21 06:28:05 PM PDT 24
Peak memory 212928 kb
Host smart-188f5d12-ec46-4f86-a5f3-0a03f0bf6e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533425991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2533425991
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2948232298
Short name T146
Test name
Test status
Simulation time 3713082228 ps
CPU time 11.95 seconds
Started Jul 21 06:27:47 PM PDT 24
Finished Jul 21 06:28:00 PM PDT 24
Peak memory 211456 kb
Host smart-4972f832-631a-4a21-858f-2e7b44e72d4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948232298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2948232298
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.625746616
Short name T291
Test name
Test status
Simulation time 751624914 ps
CPU time 10.16 seconds
Started Jul 21 06:27:49 PM PDT 24
Finished Jul 21 06:28:00 PM PDT 24
Peak memory 213888 kb
Host smart-696c1592-bd12-44a3-b7bd-51112ef603f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625746616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.625746616
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2444302323
Short name T202
Test name
Test status
Simulation time 7959243843 ps
CPU time 25.63 seconds
Started Jul 21 06:27:49 PM PDT 24
Finished Jul 21 06:28:16 PM PDT 24
Peak memory 219356 kb
Host smart-ed9fd350-e531-42bd-b63d-82a99a1fe9ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444302323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2444302323
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3054793098
Short name T332
Test name
Test status
Simulation time 2130019650 ps
CPU time 10.15 seconds
Started Jul 21 06:27:50 PM PDT 24
Finished Jul 21 06:28:01 PM PDT 24
Peak memory 211292 kb
Host smart-41977bd1-acbb-48cf-8536-b0cf2fffbc8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054793098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3054793098
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4137650469
Short name T304
Test name
Test status
Simulation time 4909600532 ps
CPU time 79.52 seconds
Started Jul 21 06:27:47 PM PDT 24
Finished Jul 21 06:29:07 PM PDT 24
Peak memory 237212 kb
Host smart-cca66ec6-4f4b-410b-89c6-3e49b1d1e22f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137650469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4137650469
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3649002308
Short name T196
Test name
Test status
Simulation time 7347704610 ps
CPU time 30.55 seconds
Started Jul 21 06:27:47 PM PDT 24
Finished Jul 21 06:28:18 PM PDT 24
Peak memory 212732 kb
Host smart-90a38bbd-094f-43ca-955c-3dc8acf6798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649002308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3649002308
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4246199742
Short name T149
Test name
Test status
Simulation time 2313360720 ps
CPU time 11.12 seconds
Started Jul 21 06:27:49 PM PDT 24
Finished Jul 21 06:28:01 PM PDT 24
Peak memory 211352 kb
Host smart-ca7698c3-51ac-4734-b250-5834e04ea696
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246199742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4246199742
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3771660254
Short name T77
Test name
Test status
Simulation time 189055064 ps
CPU time 10.06 seconds
Started Jul 21 06:27:46 PM PDT 24
Finished Jul 21 06:27:57 PM PDT 24
Peak memory 213680 kb
Host smart-65126f16-bcfe-4d53-b477-df8e47bbfa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771660254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3771660254
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1002752997
Short name T248
Test name
Test status
Simulation time 1768340002 ps
CPU time 44.18 seconds
Started Jul 21 06:27:50 PM PDT 24
Finished Jul 21 06:28:35 PM PDT 24
Peak memory 216140 kb
Host smart-c921aafa-f06d-43f0-b813-2c7f4ad6512b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002752997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1002752997
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3671314297
Short name T57
Test name
Test status
Simulation time 31106424061 ps
CPU time 620.63 seconds
Started Jul 21 06:27:48 PM PDT 24
Finished Jul 21 06:38:10 PM PDT 24
Peak memory 228056 kb
Host smart-4a441a3b-0120-4d5f-a580-d79b926643e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671314297 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3671314297
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3378275065
Short name T263
Test name
Test status
Simulation time 998555876 ps
CPU time 10.48 seconds
Started Jul 21 06:27:16 PM PDT 24
Finished Jul 21 06:27:27 PM PDT 24
Peak memory 211372 kb
Host smart-57a904f7-565a-4551-8432-7f19f2b86ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378275065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3378275065
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3206823362
Short name T130
Test name
Test status
Simulation time 17184260979 ps
CPU time 33.95 seconds
Started Jul 21 06:27:16 PM PDT 24
Finished Jul 21 06:27:51 PM PDT 24
Peak memory 211628 kb
Host smart-b6fbb5d9-9416-4675-adda-e8526db08bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206823362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3206823362
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2138641564
Short name T229
Test name
Test status
Simulation time 542381076 ps
CPU time 8.88 seconds
Started Jul 21 06:27:14 PM PDT 24
Finished Jul 21 06:27:24 PM PDT 24
Peak memory 211408 kb
Host smart-856d8978-b0aa-4e02-8bec-d0ee438eb931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138641564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2138641564
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.702764052
Short name T25
Test name
Test status
Simulation time 1303979529 ps
CPU time 99.55 seconds
Started Jul 21 06:27:16 PM PDT 24
Finished Jul 21 06:28:56 PM PDT 24
Peak memory 236924 kb
Host smart-0cc19ce1-499e-4293-8cfe-4100566dfdae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702764052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.702764052
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3205497608
Short name T212
Test name
Test status
Simulation time 182143865 ps
CPU time 9.86 seconds
Started Jul 21 06:27:15 PM PDT 24
Finished Jul 21 06:27:26 PM PDT 24
Peak memory 213544 kb
Host smart-d113133a-7eee-4a1f-ada1-59f51fce4a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205497608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3205497608
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1500617999
Short name T191
Test name
Test status
Simulation time 43725651232 ps
CPU time 34.27 seconds
Started Jul 21 06:27:16 PM PDT 24
Finished Jul 21 06:27:51 PM PDT 24
Peak memory 217044 kb
Host smart-42d63f8b-0f52-44b5-a2ce-407be5c12bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500617999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1500617999
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3741647514
Short name T208
Test name
Test status
Simulation time 333092394 ps
CPU time 4.34 seconds
Started Jul 21 06:27:52 PM PDT 24
Finished Jul 21 06:27:58 PM PDT 24
Peak memory 211352 kb
Host smart-0de6b8bb-2734-4801-b7d3-bd9acf6c9686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741647514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3741647514
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2637957071
Short name T201
Test name
Test status
Simulation time 47073723436 ps
CPU time 311.91 seconds
Started Jul 21 06:27:54 PM PDT 24
Finished Jul 21 06:33:08 PM PDT 24
Peak memory 213704 kb
Host smart-7ab36106-2c96-4311-ab9a-a8a464852eb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637957071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2637957071
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3384737383
Short name T316
Test name
Test status
Simulation time 432145619 ps
CPU time 12.74 seconds
Started Jul 21 06:27:54 PM PDT 24
Finished Jul 21 06:28:09 PM PDT 24
Peak memory 211892 kb
Host smart-cafc37fc-f9db-4aaf-beb3-c71e0816972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384737383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3384737383
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3991470723
Short name T343
Test name
Test status
Simulation time 2196083310 ps
CPU time 10.3 seconds
Started Jul 21 06:27:46 PM PDT 24
Finished Jul 21 06:27:58 PM PDT 24
Peak memory 211520 kb
Host smart-c7060665-5601-4c76-8bad-7011e71b89b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3991470723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3991470723
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2261729386
Short name T154
Test name
Test status
Simulation time 3796689526 ps
CPU time 36.36 seconds
Started Jul 21 06:27:48 PM PDT 24
Finished Jul 21 06:28:25 PM PDT 24
Peak memory 213524 kb
Host smart-f78d012b-fe26-4662-9909-5f37b36857a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261729386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2261729386
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2478245630
Short name T272
Test name
Test status
Simulation time 160632428 ps
CPU time 10.04 seconds
Started Jul 21 06:27:49 PM PDT 24
Finished Jul 21 06:28:00 PM PDT 24
Peak memory 211988 kb
Host smart-df7b01b3-a91b-48eb-8929-f49550efff72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478245630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2478245630
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2000586408
Short name T217
Test name
Test status
Simulation time 171197247 ps
CPU time 4.34 seconds
Started Jul 21 06:27:53 PM PDT 24
Finished Jul 21 06:27:59 PM PDT 24
Peak memory 211336 kb
Host smart-10854cbe-be55-46e3-a6eb-d85579178188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000586408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2000586408
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.749826771
Short name T35
Test name
Test status
Simulation time 34052738545 ps
CPU time 322.76 seconds
Started Jul 21 06:27:52 PM PDT 24
Finished Jul 21 06:33:17 PM PDT 24
Peak memory 228680 kb
Host smart-75bb1522-2e65-4877-88ba-8db0614f2890
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749826771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.749826771
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2695645656
Short name T230
Test name
Test status
Simulation time 3209396469 ps
CPU time 22.93 seconds
Started Jul 21 06:27:53 PM PDT 24
Finished Jul 21 06:28:18 PM PDT 24
Peak memory 211460 kb
Host smart-ac211fa0-5c99-4e94-8727-430014b15bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695645656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2695645656
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2670177555
Short name T274
Test name
Test status
Simulation time 7589154246 ps
CPU time 15.73 seconds
Started Jul 21 06:27:54 PM PDT 24
Finished Jul 21 06:28:11 PM PDT 24
Peak memory 211492 kb
Host smart-a13231a5-060c-48c1-a95f-fa7fecd9baa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2670177555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2670177555
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3342204420
Short name T104
Test name
Test status
Simulation time 14793029237 ps
CPU time 26.43 seconds
Started Jul 21 06:27:52 PM PDT 24
Finished Jul 21 06:28:19 PM PDT 24
Peak memory 214528 kb
Host smart-501a09a7-d276-41f2-9ce5-b2d5242dcc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342204420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3342204420
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2886848365
Short name T257
Test name
Test status
Simulation time 24579142556 ps
CPU time 12.64 seconds
Started Jul 21 06:27:53 PM PDT 24
Finished Jul 21 06:28:08 PM PDT 24
Peak memory 211396 kb
Host smart-0add0103-dd1c-4316-8448-5d7b15d89de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886848365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2886848365
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2077475533
Short name T223
Test name
Test status
Simulation time 14477726633 ps
CPU time 122.78 seconds
Started Jul 21 06:27:53 PM PDT 24
Finished Jul 21 06:29:57 PM PDT 24
Peak memory 234864 kb
Host smart-27aaa896-61fb-44fc-9f5d-0e8cec7ca4bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077475533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2077475533
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4192723140
Short name T134
Test name
Test status
Simulation time 7841625377 ps
CPU time 32.44 seconds
Started Jul 21 06:27:51 PM PDT 24
Finished Jul 21 06:28:24 PM PDT 24
Peak memory 212728 kb
Host smart-ca146b37-df9d-47d6-a24c-26506f8cafec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192723140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4192723140
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2627012083
Short name T136
Test name
Test status
Simulation time 4105218846 ps
CPU time 16.33 seconds
Started Jul 21 06:27:53 PM PDT 24
Finished Jul 21 06:28:12 PM PDT 24
Peak memory 211440 kb
Host smart-76a43c80-af1c-4de7-b1b4-95eeecf111e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627012083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2627012083
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3593255634
Short name T305
Test name
Test status
Simulation time 2378603094 ps
CPU time 23.52 seconds
Started Jul 21 06:27:53 PM PDT 24
Finished Jul 21 06:28:18 PM PDT 24
Peak memory 213452 kb
Host smart-970d02df-9056-4564-a9e6-bcf0d0e4a7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593255634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3593255634
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3858545137
Short name T356
Test name
Test status
Simulation time 461971889 ps
CPU time 5.92 seconds
Started Jul 21 06:27:53 PM PDT 24
Finished Jul 21 06:28:00 PM PDT 24
Peak memory 211440 kb
Host smart-911ece8a-30ef-4c6a-a1d7-96d509a14fb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858545137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3858545137
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4140825929
Short name T30
Test name
Test status
Simulation time 4482861445 ps
CPU time 16.65 seconds
Started Jul 21 06:27:59 PM PDT 24
Finished Jul 21 06:28:16 PM PDT 24
Peak memory 211460 kb
Host smart-f22726f7-1ea0-479a-ad65-8aa2f6f9e80b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140825929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4140825929
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.910832600
Short name T186
Test name
Test status
Simulation time 6432368164 ps
CPU time 105.3 seconds
Started Jul 21 06:27:53 PM PDT 24
Finished Jul 21 06:29:40 PM PDT 24
Peak memory 235008 kb
Host smart-31ae23ee-a5ed-4ef9-89d3-0b5c6ed82c72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910832600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.910832600
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3997574167
Short name T43
Test name
Test status
Simulation time 693457268 ps
CPU time 9.69 seconds
Started Jul 21 06:27:52 PM PDT 24
Finished Jul 21 06:28:02 PM PDT 24
Peak memory 211872 kb
Host smart-175dddab-571d-4bef-b937-f90ae79b8167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997574167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3997574167
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1580978104
Short name T219
Test name
Test status
Simulation time 7775253044 ps
CPU time 15.81 seconds
Started Jul 21 06:27:53 PM PDT 24
Finished Jul 21 06:28:10 PM PDT 24
Peak memory 211416 kb
Host smart-43375efb-cbcc-4969-89c9-9e6d24f37153
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580978104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1580978104
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1732001094
Short name T306
Test name
Test status
Simulation time 6553915243 ps
CPU time 21.75 seconds
Started Jul 21 06:27:52 PM PDT 24
Finished Jul 21 06:28:16 PM PDT 24
Peak memory 213620 kb
Host smart-02266d6e-809d-4fd9-8f25-0f24181b522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732001094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1732001094
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1545178700
Short name T279
Test name
Test status
Simulation time 28376305202 ps
CPU time 71.22 seconds
Started Jul 21 06:27:54 PM PDT 24
Finished Jul 21 06:29:07 PM PDT 24
Peak memory 219428 kb
Host smart-88437db3-ad22-4ef9-9d4f-d9da6b8f99d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545178700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1545178700
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.820648001
Short name T284
Test name
Test status
Simulation time 743631605 ps
CPU time 8.68 seconds
Started Jul 21 06:28:01 PM PDT 24
Finished Jul 21 06:28:10 PM PDT 24
Peak memory 211372 kb
Host smart-04aaa91b-6a75-4c19-9bc8-3f14fbbc6ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820648001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.820648001
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.568376083
Short name T344
Test name
Test status
Simulation time 14773342994 ps
CPU time 186.07 seconds
Started Jul 21 06:27:59 PM PDT 24
Finished Jul 21 06:31:06 PM PDT 24
Peak memory 212700 kb
Host smart-4221c119-9a33-434f-8c62-3b687aa92303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568376083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.568376083
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1346169479
Short name T22
Test name
Test status
Simulation time 5169387321 ps
CPU time 27.74 seconds
Started Jul 21 06:27:58 PM PDT 24
Finished Jul 21 06:28:26 PM PDT 24
Peak memory 212128 kb
Host smart-1dc98e6a-73bd-4052-b037-d72c15e167e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346169479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1346169479
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.690080889
Short name T179
Test name
Test status
Simulation time 6219221349 ps
CPU time 13.95 seconds
Started Jul 21 06:27:59 PM PDT 24
Finished Jul 21 06:28:14 PM PDT 24
Peak memory 211424 kb
Host smart-15594886-4b15-4a0d-94ea-6d299af0ea06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690080889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.690080889
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3543826733
Short name T288
Test name
Test status
Simulation time 275722695 ps
CPU time 10.84 seconds
Started Jul 21 06:27:59 PM PDT 24
Finished Jul 21 06:28:11 PM PDT 24
Peak memory 213708 kb
Host smart-619a4ae3-5864-4f3a-8f0f-13855a94c8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543826733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3543826733
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.786313559
Short name T138
Test name
Test status
Simulation time 1380478293 ps
CPU time 14.6 seconds
Started Jul 21 06:28:00 PM PDT 24
Finished Jul 21 06:28:15 PM PDT 24
Peak memory 211268 kb
Host smart-85a85ea4-b70c-4df6-8f41-a5bdde9aae9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786313559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.786313559
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2387739586
Short name T166
Test name
Test status
Simulation time 1305994567 ps
CPU time 12.23 seconds
Started Jul 21 06:28:08 PM PDT 24
Finished Jul 21 06:28:20 PM PDT 24
Peak memory 211376 kb
Host smart-3a222033-5294-42b7-a7b1-9dc63382df36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387739586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2387739586
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1850813080
Short name T329
Test name
Test status
Simulation time 13093860666 ps
CPU time 257.13 seconds
Started Jul 21 06:27:59 PM PDT 24
Finished Jul 21 06:32:17 PM PDT 24
Peak memory 235036 kb
Host smart-e5332c8a-c96d-4a70-bac8-838557039824
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850813080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1850813080
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.855010823
Short name T334
Test name
Test status
Simulation time 1112557050 ps
CPU time 13.38 seconds
Started Jul 21 06:27:59 PM PDT 24
Finished Jul 21 06:28:13 PM PDT 24
Peak memory 213444 kb
Host smart-d811c694-38fd-41e4-9f78-48e21f83d076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855010823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.855010823
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1006383413
Short name T103
Test name
Test status
Simulation time 1692888060 ps
CPU time 14.67 seconds
Started Jul 21 06:28:00 PM PDT 24
Finished Jul 21 06:28:15 PM PDT 24
Peak memory 211564 kb
Host smart-2d9078e4-d76d-4310-8ea2-be0385b86d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1006383413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1006383413
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1263249543
Short name T259
Test name
Test status
Simulation time 4047307656 ps
CPU time 24.69 seconds
Started Jul 21 06:27:59 PM PDT 24
Finished Jul 21 06:28:25 PM PDT 24
Peak memory 215092 kb
Host smart-ae601435-c37b-4378-a3ff-d6b1cb00f5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263249543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1263249543
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.349984358
Short name T231
Test name
Test status
Simulation time 523744117 ps
CPU time 14.16 seconds
Started Jul 21 06:27:59 PM PDT 24
Finished Jul 21 06:28:14 PM PDT 24
Peak memory 213936 kb
Host smart-d10d0098-9829-4b23-8ae4-37df40a02521
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349984358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.349984358
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3514168390
Short name T164
Test name
Test status
Simulation time 899686574 ps
CPU time 9.52 seconds
Started Jul 21 06:28:06 PM PDT 24
Finished Jul 21 06:28:15 PM PDT 24
Peak memory 211404 kb
Host smart-cab2ee68-4a5b-4f6e-b120-7f2de5b88b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514168390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3514168390
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.66182859
Short name T228
Test name
Test status
Simulation time 4450284579 ps
CPU time 120.11 seconds
Started Jul 21 06:28:04 PM PDT 24
Finished Jul 21 06:30:05 PM PDT 24
Peak memory 237896 kb
Host smart-6f43e0b3-c2c7-49d0-bcf2-4005f49271be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66182859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_co
rrupt_sig_fatal_chk.66182859
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2887780501
Short name T331
Test name
Test status
Simulation time 1754856649 ps
CPU time 20.1 seconds
Started Jul 21 06:28:04 PM PDT 24
Finished Jul 21 06:28:25 PM PDT 24
Peak memory 211900 kb
Host smart-73cce553-7351-4a8c-8b79-9de2a6401100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887780501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2887780501
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1802518751
Short name T160
Test name
Test status
Simulation time 95086458 ps
CPU time 5.32 seconds
Started Jul 21 06:28:04 PM PDT 24
Finished Jul 21 06:28:10 PM PDT 24
Peak memory 211424 kb
Host smart-a592168d-3b07-437f-b3fc-263586cb5216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1802518751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1802518751
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.753371949
Short name T215
Test name
Test status
Simulation time 8610361124 ps
CPU time 26.88 seconds
Started Jul 21 06:28:04 PM PDT 24
Finished Jul 21 06:28:31 PM PDT 24
Peak memory 213408 kb
Host smart-5a93d9b7-4e87-45d4-8a7a-fe024fd381b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753371949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.753371949
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.137477553
Short name T232
Test name
Test status
Simulation time 395409958 ps
CPU time 6 seconds
Started Jul 21 06:28:05 PM PDT 24
Finished Jul 21 06:28:12 PM PDT 24
Peak memory 211444 kb
Host smart-70722db4-90f5-47ad-ab4e-983b8349383e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137477553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.137477553
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3235720857
Short name T313
Test name
Test status
Simulation time 89229884 ps
CPU time 4.37 seconds
Started Jul 21 06:28:06 PM PDT 24
Finished Jul 21 06:28:10 PM PDT 24
Peak memory 211384 kb
Host smart-ab061a9c-2e29-4eab-8a1b-a9729c7f2acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235720857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3235720857
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3868136842
Short name T275
Test name
Test status
Simulation time 28648315968 ps
CPU time 297.74 seconds
Started Jul 21 06:28:06 PM PDT 24
Finished Jul 21 06:33:04 PM PDT 24
Peak memory 225068 kb
Host smart-008fdde4-5fe7-48fd-9744-0314afcc9aaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868136842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3868136842
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1498699625
Short name T302
Test name
Test status
Simulation time 303910145 ps
CPU time 9.15 seconds
Started Jul 21 06:28:04 PM PDT 24
Finished Jul 21 06:28:13 PM PDT 24
Peak memory 212288 kb
Host smart-8c7fbbcd-fde5-46b8-b91a-fd1d35e65af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498699625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1498699625
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.436506686
Short name T341
Test name
Test status
Simulation time 2610399218 ps
CPU time 11.85 seconds
Started Jul 21 06:28:05 PM PDT 24
Finished Jul 21 06:28:17 PM PDT 24
Peak memory 211464 kb
Host smart-dd068f54-243a-40d2-bee3-7a8850f1dd4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436506686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.436506686
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2661117003
Short name T128
Test name
Test status
Simulation time 7218889812 ps
CPU time 28.27 seconds
Started Jul 21 06:28:05 PM PDT 24
Finished Jul 21 06:28:34 PM PDT 24
Peak memory 214536 kb
Host smart-988c6697-e4f3-43e1-9c0d-e77f1b635c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661117003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2661117003
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1897873239
Short name T309
Test name
Test status
Simulation time 542325168 ps
CPU time 13.15 seconds
Started Jul 21 06:28:05 PM PDT 24
Finished Jul 21 06:28:19 PM PDT 24
Peak memory 214496 kb
Host smart-d395de5e-6372-404d-881f-8abb584e6522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897873239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1897873239
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1136568399
Short name T308
Test name
Test status
Simulation time 89043858 ps
CPU time 4.7 seconds
Started Jul 21 06:28:10 PM PDT 24
Finished Jul 21 06:28:15 PM PDT 24
Peak memory 211344 kb
Host smart-6ec1e72d-7065-487b-ac28-f028cc257a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136568399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1136568399
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1144304795
Short name T38
Test name
Test status
Simulation time 96684662859 ps
CPU time 247.34 seconds
Started Jul 21 06:28:09 PM PDT 24
Finished Jul 21 06:32:17 PM PDT 24
Peak memory 228612 kb
Host smart-d0a6b1dd-c144-4c43-a311-042e2a79bd01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144304795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1144304795
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3719724701
Short name T45
Test name
Test status
Simulation time 664236745 ps
CPU time 9.63 seconds
Started Jul 21 06:28:05 PM PDT 24
Finished Jul 21 06:28:15 PM PDT 24
Peak memory 212052 kb
Host smart-1f8653c3-e121-4a16-872b-ffc4c7dcb130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719724701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3719724701
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3197071125
Short name T157
Test name
Test status
Simulation time 597205434 ps
CPU time 8.89 seconds
Started Jul 21 06:28:06 PM PDT 24
Finished Jul 21 06:28:15 PM PDT 24
Peak memory 211380 kb
Host smart-a1e30ec7-e7bb-4f22-86d6-1c1bd0cba6ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3197071125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3197071125
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.249558437
Short name T137
Test name
Test status
Simulation time 1623943410 ps
CPU time 19.45 seconds
Started Jul 21 06:28:05 PM PDT 24
Finished Jul 21 06:28:25 PM PDT 24
Peak memory 213864 kb
Host smart-99d83eb2-4a8d-4b74-a957-e2ba595e9769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249558437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.249558437
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2612947890
Short name T348
Test name
Test status
Simulation time 9435936952 ps
CPU time 83.44 seconds
Started Jul 21 06:28:09 PM PDT 24
Finished Jul 21 06:29:33 PM PDT 24
Peak memory 216284 kb
Host smart-921a5254-490e-4512-a904-16cf3623b790
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612947890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2612947890
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.306517733
Short name T175
Test name
Test status
Simulation time 20426650276 ps
CPU time 16.98 seconds
Started Jul 21 06:28:10 PM PDT 24
Finished Jul 21 06:28:27 PM PDT 24
Peak memory 211420 kb
Host smart-ebb9a8ec-16aa-4165-bee2-f6cef9551cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306517733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.306517733
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2789672623
Short name T40
Test name
Test status
Simulation time 18361060576 ps
CPU time 153.44 seconds
Started Jul 21 06:28:10 PM PDT 24
Finished Jul 21 06:30:44 PM PDT 24
Peak memory 237868 kb
Host smart-0e9dc879-a198-4247-8621-4005a55cb70c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789672623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2789672623
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.196950225
Short name T254
Test name
Test status
Simulation time 4106624084 ps
CPU time 32.91 seconds
Started Jul 21 06:28:11 PM PDT 24
Finished Jul 21 06:28:44 PM PDT 24
Peak memory 212100 kb
Host smart-8703a04f-b920-4f40-aac1-02e03031f6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196950225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.196950225
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3480367544
Short name T142
Test name
Test status
Simulation time 96377594 ps
CPU time 5.73 seconds
Started Jul 21 06:28:11 PM PDT 24
Finished Jul 21 06:28:17 PM PDT 24
Peak memory 211340 kb
Host smart-bb2ea122-75d6-40bf-bc88-b96aaf0caf8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480367544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3480367544
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1280252471
Short name T289
Test name
Test status
Simulation time 8612440776 ps
CPU time 23.42 seconds
Started Jul 21 06:28:12 PM PDT 24
Finished Jul 21 06:28:36 PM PDT 24
Peak memory 214204 kb
Host smart-018cb473-572b-4301-a7e3-900011915698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280252471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1280252471
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1695416236
Short name T320
Test name
Test status
Simulation time 9678545281 ps
CPU time 37.4 seconds
Started Jul 21 06:28:10 PM PDT 24
Finished Jul 21 06:28:48 PM PDT 24
Peak memory 215760 kb
Host smart-9a221b5e-125a-4fdd-84d9-5c11f9f49068
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695416236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1695416236
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3699935975
Short name T181
Test name
Test status
Simulation time 2298948876 ps
CPU time 7.91 seconds
Started Jul 21 06:27:22 PM PDT 24
Finished Jul 21 06:27:30 PM PDT 24
Peak memory 211396 kb
Host smart-434a540b-8ab3-4344-8c31-0abf10e39c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699935975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3699935975
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.112168784
Short name T116
Test name
Test status
Simulation time 19564655492 ps
CPU time 87.77 seconds
Started Jul 21 06:27:15 PM PDT 24
Finished Jul 21 06:28:43 PM PDT 24
Peak memory 234812 kb
Host smart-4a9cc524-7f43-4efa-b6fc-1ddde40a9a8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112168784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.112168784
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1834295614
Short name T170
Test name
Test status
Simulation time 6942665481 ps
CPU time 21.54 seconds
Started Jul 21 06:27:24 PM PDT 24
Finished Jul 21 06:27:47 PM PDT 24
Peak memory 212512 kb
Host smart-508b1343-5050-4c91-9b81-6f401e67ea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834295614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1834295614
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1317011784
Short name T353
Test name
Test status
Simulation time 182403416 ps
CPU time 5.3 seconds
Started Jul 21 06:27:14 PM PDT 24
Finished Jul 21 06:27:20 PM PDT 24
Peak memory 211488 kb
Host smart-496dc6b2-a197-47d5-b113-94f0cf431d4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317011784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1317011784
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3827309265
Short name T18
Test name
Test status
Simulation time 930805419 ps
CPU time 102.28 seconds
Started Jul 21 06:27:23 PM PDT 24
Finished Jul 21 06:29:06 PM PDT 24
Peak memory 238096 kb
Host smart-f0f3bd70-7869-4d36-8e9b-709de711d113
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827309265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3827309265
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1992669958
Short name T269
Test name
Test status
Simulation time 4469046241 ps
CPU time 40.88 seconds
Started Jul 21 06:27:14 PM PDT 24
Finished Jul 21 06:27:56 PM PDT 24
Peak memory 213892 kb
Host smart-73422a92-2241-43f2-9354-c83600ef8f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992669958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1992669958
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2990099472
Short name T3
Test name
Test status
Simulation time 3392055432 ps
CPU time 27.52 seconds
Started Jul 21 06:27:15 PM PDT 24
Finished Jul 21 06:27:43 PM PDT 24
Peak memory 214820 kb
Host smart-a18a82f6-b6b2-48b2-8469-3a49456e8980
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990099472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2990099472
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3881958421
Short name T53
Test name
Test status
Simulation time 138929483030 ps
CPU time 10702.4 seconds
Started Jul 21 06:27:22 PM PDT 24
Finished Jul 21 09:25:47 PM PDT 24
Peak memory 235852 kb
Host smart-0f01146a-c2e9-4209-a903-3ea1a62a6809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881958421 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3881958421
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2618707687
Short name T211
Test name
Test status
Simulation time 171347814 ps
CPU time 4.3 seconds
Started Jul 21 06:28:18 PM PDT 24
Finished Jul 21 06:28:23 PM PDT 24
Peak memory 211376 kb
Host smart-b976bd9b-90b6-4775-839a-7a2d1591e89d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618707687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2618707687
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2186518364
Short name T251
Test name
Test status
Simulation time 3558552887 ps
CPU time 102.98 seconds
Started Jul 21 06:28:12 PM PDT 24
Finished Jul 21 06:29:55 PM PDT 24
Peak memory 225044 kb
Host smart-50f09052-d2dc-43f9-ab28-5c9490ed1fcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186518364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2186518364
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4281407062
Short name T262
Test name
Test status
Simulation time 1472215997 ps
CPU time 18.4 seconds
Started Jul 21 06:28:25 PM PDT 24
Finished Jul 21 06:28:44 PM PDT 24
Peak memory 212776 kb
Host smart-870d48b6-4fce-4e83-ae6c-5c27171d1ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281407062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4281407062
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3453027514
Short name T135
Test name
Test status
Simulation time 8783617167 ps
CPU time 18.04 seconds
Started Jul 21 06:28:10 PM PDT 24
Finished Jul 21 06:28:29 PM PDT 24
Peak memory 211492 kb
Host smart-3fa3da14-3cb8-4dec-ad79-5c4654e5665f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453027514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3453027514
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2414730879
Short name T150
Test name
Test status
Simulation time 9120106881 ps
CPU time 20.46 seconds
Started Jul 21 06:28:11 PM PDT 24
Finished Jul 21 06:28:32 PM PDT 24
Peak memory 214216 kb
Host smart-ea2fabfb-e586-4326-bd48-db3b70de565f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414730879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2414730879
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3330157732
Short name T2
Test name
Test status
Simulation time 9868894615 ps
CPU time 87.76 seconds
Started Jul 21 06:28:11 PM PDT 24
Finished Jul 21 06:29:39 PM PDT 24
Peak memory 214844 kb
Host smart-76bfbe6d-2b71-455b-ab36-c7a902c927fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330157732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3330157732
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4290461275
Short name T67
Test name
Test status
Simulation time 4446586117 ps
CPU time 10.63 seconds
Started Jul 21 06:28:16 PM PDT 24
Finished Jul 21 06:28:27 PM PDT 24
Peak memory 211412 kb
Host smart-b7fb34a0-c2d6-4032-aca6-eb7c091a16ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290461275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4290461275
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1882664226
Short name T47
Test name
Test status
Simulation time 130198212372 ps
CPU time 239.82 seconds
Started Jul 21 06:28:16 PM PDT 24
Finished Jul 21 06:32:16 PM PDT 24
Peak memory 238956 kb
Host smart-cb818c3a-e4a1-4719-a4ea-153f1769ba4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882664226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1882664226
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3377500358
Short name T192
Test name
Test status
Simulation time 4601417280 ps
CPU time 16.71 seconds
Started Jul 21 06:28:19 PM PDT 24
Finished Jul 21 06:28:36 PM PDT 24
Peak memory 212336 kb
Host smart-20393f04-8049-4374-a258-a6e1ee39a999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377500358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3377500358
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3721755510
Short name T312
Test name
Test status
Simulation time 2194705968 ps
CPU time 17.47 seconds
Started Jul 21 06:28:19 PM PDT 24
Finished Jul 21 06:28:36 PM PDT 24
Peak memory 211444 kb
Host smart-ba9c73c7-9c3f-495a-93ec-6ed58239c3e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721755510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3721755510
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1423364058
Short name T243
Test name
Test status
Simulation time 6018474555 ps
CPU time 27.03 seconds
Started Jul 21 06:28:17 PM PDT 24
Finished Jul 21 06:28:44 PM PDT 24
Peak memory 214140 kb
Host smart-4f72bb33-1cf1-45bc-a6af-6389262219a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423364058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1423364058
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.64808896
Short name T32
Test name
Test status
Simulation time 1369465935 ps
CPU time 14.05 seconds
Started Jul 21 06:28:19 PM PDT 24
Finished Jul 21 06:28:34 PM PDT 24
Peak memory 211972 kb
Host smart-f91207de-b0ba-49cb-9df7-3952f4cbf046
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64808896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.rom_ctrl_stress_all.64808896
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.64060956
Short name T28
Test name
Test status
Simulation time 5924577527 ps
CPU time 12.45 seconds
Started Jul 21 06:28:16 PM PDT 24
Finished Jul 21 06:28:29 PM PDT 24
Peak memory 211372 kb
Host smart-346feb7e-4145-491c-a5ac-bbfefffa807e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64060956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.64060956
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2266887183
Short name T336
Test name
Test status
Simulation time 73178983688 ps
CPU time 253.72 seconds
Started Jul 21 06:28:19 PM PDT 24
Finished Jul 21 06:32:33 PM PDT 24
Peak memory 233988 kb
Host smart-ab5f5762-4a16-4750-86ad-17329c94b192
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266887183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2266887183
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3195377670
Short name T193
Test name
Test status
Simulation time 1703160042 ps
CPU time 13.68 seconds
Started Jul 21 06:28:19 PM PDT 24
Finished Jul 21 06:28:33 PM PDT 24
Peak memory 211848 kb
Host smart-e9b7f68a-8804-4142-85af-c63597d84abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195377670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3195377670
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3192510624
Short name T129
Test name
Test status
Simulation time 6188663717 ps
CPU time 13.63 seconds
Started Jul 21 06:28:16 PM PDT 24
Finished Jul 21 06:28:30 PM PDT 24
Peak memory 211480 kb
Host smart-fc198c5b-510b-4fc2-ad66-ea158da0bc15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3192510624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3192510624
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2553340783
Short name T200
Test name
Test status
Simulation time 2065237623 ps
CPU time 26.42 seconds
Started Jul 21 06:28:18 PM PDT 24
Finished Jul 21 06:28:45 PM PDT 24
Peak memory 213096 kb
Host smart-44f49390-120f-4702-a09a-5b619a1d1c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553340783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2553340783
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3007550623
Short name T347
Test name
Test status
Simulation time 102636933 ps
CPU time 10.4 seconds
Started Jul 21 06:28:19 PM PDT 24
Finished Jul 21 06:28:30 PM PDT 24
Peak memory 211356 kb
Host smart-2a940ecb-2753-4cac-805b-1ab987569f1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007550623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3007550623
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3543410791
Short name T173
Test name
Test status
Simulation time 1073647599 ps
CPU time 10.32 seconds
Started Jul 21 06:28:16 PM PDT 24
Finished Jul 21 06:28:27 PM PDT 24
Peak memory 211344 kb
Host smart-10fe57ba-f8c5-4296-a1f1-585c0d671506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543410791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3543410791
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2449796031
Short name T328
Test name
Test status
Simulation time 3453066263 ps
CPU time 69.31 seconds
Started Jul 21 06:28:16 PM PDT 24
Finished Jul 21 06:29:26 PM PDT 24
Peak memory 236836 kb
Host smart-1fca7f2e-0ed5-4ccf-8e65-bf0c3281f986
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449796031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2449796031
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4019461940
Short name T358
Test name
Test status
Simulation time 665190473 ps
CPU time 14.16 seconds
Started Jul 21 06:28:16 PM PDT 24
Finished Jul 21 06:28:30 PM PDT 24
Peak memory 211904 kb
Host smart-f17c7cf8-eb31-4a4d-a83b-f2b8718300fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019461940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4019461940
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4118534837
Short name T293
Test name
Test status
Simulation time 1803662841 ps
CPU time 15.86 seconds
Started Jul 21 06:28:16 PM PDT 24
Finished Jul 21 06:28:32 PM PDT 24
Peak memory 211384 kb
Host smart-b05ceb63-8e36-4534-84f1-72c02500b541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118534837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4118534837
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.601494237
Short name T126
Test name
Test status
Simulation time 14702871203 ps
CPU time 31.41 seconds
Started Jul 21 06:28:17 PM PDT 24
Finished Jul 21 06:28:49 PM PDT 24
Peak memory 213772 kb
Host smart-e23eba6a-8dc1-48f3-89ef-37af592e00e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601494237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.601494237
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1352367583
Short name T124
Test name
Test status
Simulation time 2495926233 ps
CPU time 30 seconds
Started Jul 21 06:28:19 PM PDT 24
Finished Jul 21 06:28:50 PM PDT 24
Peak memory 215200 kb
Host smart-e26fe581-a920-4501-a25b-67d439b9f4a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352367583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1352367583
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1761503627
Short name T194
Test name
Test status
Simulation time 1542030097 ps
CPU time 6.83 seconds
Started Jul 21 06:28:25 PM PDT 24
Finished Jul 21 06:28:32 PM PDT 24
Peak memory 211372 kb
Host smart-885dd85b-e9ff-4736-aca9-899c8a440b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761503627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1761503627
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1116226448
Short name T189
Test name
Test status
Simulation time 84612513840 ps
CPU time 270.82 seconds
Started Jul 21 06:28:18 PM PDT 24
Finished Jul 21 06:32:49 PM PDT 24
Peak memory 237384 kb
Host smart-8041740d-e1e3-4711-9b16-53eb8044bda1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116226448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1116226448
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.994339572
Short name T199
Test name
Test status
Simulation time 328885056 ps
CPU time 9.39 seconds
Started Jul 21 06:28:25 PM PDT 24
Finished Jul 21 06:28:34 PM PDT 24
Peak memory 212568 kb
Host smart-09df632f-515a-4443-9c89-3afa626474e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994339572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.994339572
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2384040378
Short name T4
Test name
Test status
Simulation time 2134203071 ps
CPU time 18.53 seconds
Started Jul 21 06:28:17 PM PDT 24
Finished Jul 21 06:28:36 PM PDT 24
Peak memory 211416 kb
Host smart-286339f2-c156-468e-9468-e57fd84d2c87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384040378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2384040378
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1287297031
Short name T357
Test name
Test status
Simulation time 360190777 ps
CPU time 10.06 seconds
Started Jul 21 06:28:16 PM PDT 24
Finished Jul 21 06:28:26 PM PDT 24
Peak memory 213524 kb
Host smart-f0c3a6cf-ad3e-4d3f-b699-07af435e9949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287297031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1287297031
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3090565622
Short name T323
Test name
Test status
Simulation time 25533476928 ps
CPU time 28.18 seconds
Started Jul 21 06:28:16 PM PDT 24
Finished Jul 21 06:28:45 PM PDT 24
Peak memory 214196 kb
Host smart-76e034b3-57df-4004-b8b5-11b25d2aef80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090565622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3090565622
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.803870864
Short name T222
Test name
Test status
Simulation time 297722522 ps
CPU time 6.29 seconds
Started Jul 21 06:28:24 PM PDT 24
Finished Jul 21 06:28:31 PM PDT 24
Peak memory 211364 kb
Host smart-9f16c8cd-d5c5-4a78-840f-8117f12b6e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803870864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.803870864
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1223376771
Short name T39
Test name
Test status
Simulation time 49526856920 ps
CPU time 497.91 seconds
Started Jul 21 06:28:25 PM PDT 24
Finished Jul 21 06:36:43 PM PDT 24
Peak memory 237432 kb
Host smart-82f60478-0e64-4c0c-bb15-aed1404ca1a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223376771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1223376771
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3090694141
Short name T195
Test name
Test status
Simulation time 3260799627 ps
CPU time 25.21 seconds
Started Jul 21 06:28:26 PM PDT 24
Finished Jul 21 06:28:52 PM PDT 24
Peak memory 211880 kb
Host smart-b3a33fb7-d544-4728-b30a-1fa633b05e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090694141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3090694141
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.378170444
Short name T342
Test name
Test status
Simulation time 100712475 ps
CPU time 5.6 seconds
Started Jul 21 06:28:26 PM PDT 24
Finished Jul 21 06:28:32 PM PDT 24
Peak memory 211384 kb
Host smart-b60569b1-574b-4536-9ca8-6ea9b36a2d0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378170444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.378170444
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3316651252
Short name T155
Test name
Test status
Simulation time 34737887083 ps
CPU time 41.34 seconds
Started Jul 21 06:28:24 PM PDT 24
Finished Jul 21 06:29:06 PM PDT 24
Peak memory 214192 kb
Host smart-df53814d-fa8a-49d1-82bc-9cd0cbb11fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316651252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3316651252
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2364829507
Short name T267
Test name
Test status
Simulation time 4121890632 ps
CPU time 43.08 seconds
Started Jul 21 06:28:25 PM PDT 24
Finished Jul 21 06:29:08 PM PDT 24
Peak memory 213868 kb
Host smart-3f191a96-fba8-4a11-a02c-4f34409dbae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364829507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2364829507
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3979291618
Short name T66
Test name
Test status
Simulation time 4124103820 ps
CPU time 10.41 seconds
Started Jul 21 06:28:24 PM PDT 24
Finished Jul 21 06:28:35 PM PDT 24
Peak memory 211408 kb
Host smart-59651ff4-5b48-40fd-aedb-5d09ef594cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979291618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3979291618
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.317708398
Short name T345
Test name
Test status
Simulation time 23848796466 ps
CPU time 204.73 seconds
Started Jul 21 06:28:26 PM PDT 24
Finished Jul 21 06:31:52 PM PDT 24
Peak memory 225224 kb
Host smart-e2c61116-0c51-4e8e-9d2d-2e6bf5a30070
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317708398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.317708398
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.631862814
Short name T198
Test name
Test status
Simulation time 584508725 ps
CPU time 11.63 seconds
Started Jul 21 06:28:24 PM PDT 24
Finished Jul 21 06:28:36 PM PDT 24
Peak memory 212016 kb
Host smart-14e12a15-1941-471f-b473-27140b99548b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631862814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.631862814
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3107471530
Short name T119
Test name
Test status
Simulation time 1382364318 ps
CPU time 13.21 seconds
Started Jul 21 06:28:23 PM PDT 24
Finished Jul 21 06:28:37 PM PDT 24
Peak memory 211444 kb
Host smart-439a156c-df63-404e-bc03-757a29f1d30f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107471530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3107471530
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3826671991
Short name T246
Test name
Test status
Simulation time 1410250949 ps
CPU time 16.32 seconds
Started Jul 21 06:28:26 PM PDT 24
Finished Jul 21 06:28:42 PM PDT 24
Peak memory 211404 kb
Host smart-c2a04c0b-4322-4357-b84f-32675a0cd9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826671991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3826671991
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3363401196
Short name T178
Test name
Test status
Simulation time 394492521 ps
CPU time 22.32 seconds
Started Jul 21 06:28:23 PM PDT 24
Finished Jul 21 06:28:46 PM PDT 24
Peak memory 215580 kb
Host smart-b7b6c3e9-5e65-4336-9f3d-d910cfe74066
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363401196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3363401196
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1772088087
Short name T253
Test name
Test status
Simulation time 87371577 ps
CPU time 4.3 seconds
Started Jul 21 06:28:23 PM PDT 24
Finished Jul 21 06:28:28 PM PDT 24
Peak memory 211356 kb
Host smart-ec1f8921-60d2-446a-98ab-f4f399c85310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772088087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1772088087
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4179923297
Short name T169
Test name
Test status
Simulation time 1602177152 ps
CPU time 102.97 seconds
Started Jul 21 06:28:23 PM PDT 24
Finished Jul 21 06:30:07 PM PDT 24
Peak memory 236792 kb
Host smart-4cfcc6e1-4d37-4e1b-b4ad-b14c90dc134b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179923297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4179923297
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.530613440
Short name T34
Test name
Test status
Simulation time 9529786583 ps
CPU time 23.28 seconds
Started Jul 21 06:28:26 PM PDT 24
Finished Jul 21 06:28:49 PM PDT 24
Peak memory 212424 kb
Host smart-fbfd8eca-5358-4af9-85da-edc1a0e53a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530613440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.530613440
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.55227072
Short name T187
Test name
Test status
Simulation time 1917195406 ps
CPU time 16.96 seconds
Started Jul 21 06:28:24 PM PDT 24
Finished Jul 21 06:28:41 PM PDT 24
Peak memory 211380 kb
Host smart-e9134a15-ddf1-44d0-ba77-d05c9ebc1c9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55227072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.55227072
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2056362902
Short name T42
Test name
Test status
Simulation time 1999284541 ps
CPU time 16.66 seconds
Started Jul 21 06:28:23 PM PDT 24
Finished Jul 21 06:28:40 PM PDT 24
Peak memory 213568 kb
Host smart-3abf1586-52b9-4475-89a8-ba3716084cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056362902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2056362902
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.628897304
Short name T182
Test name
Test status
Simulation time 17856634068 ps
CPU time 40.78 seconds
Started Jul 21 06:28:25 PM PDT 24
Finished Jul 21 06:29:06 PM PDT 24
Peak memory 214464 kb
Host smart-174232c5-7959-41cb-b7fe-f9a5b5aa1dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628897304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.628897304
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3079847865
Short name T352
Test name
Test status
Simulation time 803396390380 ps
CPU time 2829.38 seconds
Started Jul 21 06:28:24 PM PDT 24
Finished Jul 21 07:15:34 PM PDT 24
Peak memory 244096 kb
Host smart-4d2a1553-e4dc-4c91-a447-d663b67fe7c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079847865 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3079847865
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.649029062
Short name T143
Test name
Test status
Simulation time 1644084864 ps
CPU time 14.43 seconds
Started Jul 21 06:28:31 PM PDT 24
Finished Jul 21 06:28:46 PM PDT 24
Peak memory 211432 kb
Host smart-f8d80582-7a9f-4312-a7cd-2f4de7e7051f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649029062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.649029062
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2674720543
Short name T148
Test name
Test status
Simulation time 122272040960 ps
CPU time 304.5 seconds
Started Jul 21 06:28:29 PM PDT 24
Finished Jul 21 06:33:34 PM PDT 24
Peak memory 230600 kb
Host smart-5e6b0811-5858-4414-8127-85843c903e81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674720543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2674720543
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1507686261
Short name T156
Test name
Test status
Simulation time 4125824742 ps
CPU time 11.39 seconds
Started Jul 21 06:28:29 PM PDT 24
Finished Jul 21 06:28:41 PM PDT 24
Peak memory 211444 kb
Host smart-c5beb577-13b0-499e-9467-79c1c86283b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507686261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1507686261
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.655918949
Short name T120
Test name
Test status
Simulation time 27537005756 ps
CPU time 34.43 seconds
Started Jul 21 06:28:24 PM PDT 24
Finished Jul 21 06:28:59 PM PDT 24
Peak memory 214420 kb
Host smart-3d65e469-ffbc-430f-b035-68bb430b231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655918949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.655918949
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.167911473
Short name T227
Test name
Test status
Simulation time 500583941 ps
CPU time 8.53 seconds
Started Jul 21 06:28:25 PM PDT 24
Finished Jul 21 06:28:34 PM PDT 24
Peak memory 212068 kb
Host smart-06012ec2-beea-434d-818a-667455e3ea29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167911473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.167911473
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2499348817
Short name T237
Test name
Test status
Simulation time 1959136490 ps
CPU time 15.78 seconds
Started Jul 21 06:28:30 PM PDT 24
Finished Jul 21 06:28:46 PM PDT 24
Peak memory 211380 kb
Host smart-55ba521e-e4f0-4d11-9c58-50e5bc2a8356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499348817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2499348817
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2513104552
Short name T298
Test name
Test status
Simulation time 25969102691 ps
CPU time 229.42 seconds
Started Jul 21 06:28:32 PM PDT 24
Finished Jul 21 06:32:22 PM PDT 24
Peak memory 237908 kb
Host smart-798208f8-fb56-47bb-b454-017e4e01e25c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513104552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2513104552
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1464993026
Short name T281
Test name
Test status
Simulation time 1011603451 ps
CPU time 12.53 seconds
Started Jul 21 06:28:29 PM PDT 24
Finished Jul 21 06:28:42 PM PDT 24
Peak memory 211988 kb
Host smart-b6a0574f-daea-4e60-8272-e5df5a850307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464993026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1464993026
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2176607117
Short name T133
Test name
Test status
Simulation time 1434976956 ps
CPU time 9.83 seconds
Started Jul 21 06:28:29 PM PDT 24
Finished Jul 21 06:28:39 PM PDT 24
Peak memory 211388 kb
Host smart-45e0a2df-7022-4b42-8e6d-7616b624f2a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176607117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2176607117
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.574661419
Short name T29
Test name
Test status
Simulation time 1410358871 ps
CPU time 21 seconds
Started Jul 21 06:28:29 PM PDT 24
Finished Jul 21 06:28:51 PM PDT 24
Peak memory 213028 kb
Host smart-d4d22786-8241-4405-b895-fb10c1953ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574661419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.574661419
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2092077227
Short name T213
Test name
Test status
Simulation time 11713941757 ps
CPU time 105.52 seconds
Started Jul 21 06:28:30 PM PDT 24
Finished Jul 21 06:30:16 PM PDT 24
Peak memory 219328 kb
Host smart-ebaa6b68-5870-45d1-a7b6-2a92fc5f76f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092077227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2092077227
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1493998157
Short name T55
Test name
Test status
Simulation time 50124497543 ps
CPU time 1953.47 seconds
Started Jul 21 06:28:29 PM PDT 24
Finished Jul 21 07:01:03 PM PDT 24
Peak memory 234196 kb
Host smart-05af75ec-a7e6-43cd-afeb-e8d2724d249a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493998157 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1493998157
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2240362613
Short name T140
Test name
Test status
Simulation time 1646720928 ps
CPU time 13.77 seconds
Started Jul 21 06:27:22 PM PDT 24
Finished Jul 21 06:27:37 PM PDT 24
Peak memory 211340 kb
Host smart-a802289a-8a78-4612-8ae4-714deb230c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240362613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2240362613
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2441358308
Short name T115
Test name
Test status
Simulation time 31066588776 ps
CPU time 275.76 seconds
Started Jul 21 06:27:23 PM PDT 24
Finished Jul 21 06:32:01 PM PDT 24
Peak memory 234904 kb
Host smart-161bb680-c9a4-4016-95fd-bec221dac7a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441358308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2441358308
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2290240023
Short name T24
Test name
Test status
Simulation time 15844503323 ps
CPU time 34.13 seconds
Started Jul 21 06:27:24 PM PDT 24
Finished Jul 21 06:27:59 PM PDT 24
Peak memory 212296 kb
Host smart-cf9e31d6-aa86-4e57-a373-d07a5dbbdac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290240023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2290240023
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4229538944
Short name T118
Test name
Test status
Simulation time 671395005 ps
CPU time 7.71 seconds
Started Jul 21 06:27:21 PM PDT 24
Finished Jul 21 06:27:29 PM PDT 24
Peak memory 211388 kb
Host smart-31bd8377-be21-4f45-97c1-ddf0a034df72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229538944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4229538944
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3914235125
Short name T147
Test name
Test status
Simulation time 5159462589 ps
CPU time 17.61 seconds
Started Jul 21 06:27:24 PM PDT 24
Finished Jul 21 06:27:43 PM PDT 24
Peak memory 213480 kb
Host smart-8d9c9045-3988-48ff-99fa-4e9cde9604a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914235125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3914235125
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.453094703
Short name T5
Test name
Test status
Simulation time 9308108592 ps
CPU time 17.12 seconds
Started Jul 21 06:27:24 PM PDT 24
Finished Jul 21 06:27:42 PM PDT 24
Peak memory 212776 kb
Host smart-c6fdf4a8-8172-4500-8116-e8c07be40364
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453094703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.453094703
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2379704175
Short name T239
Test name
Test status
Simulation time 4117636489 ps
CPU time 6.96 seconds
Started Jul 21 06:27:25 PM PDT 24
Finished Jul 21 06:27:33 PM PDT 24
Peak memory 211464 kb
Host smart-2f63ab9f-279c-4b80-8d35-6b5cae97848f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379704175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2379704175
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.516625737
Short name T49
Test name
Test status
Simulation time 1435090989 ps
CPU time 102.88 seconds
Started Jul 21 06:27:24 PM PDT 24
Finished Jul 21 06:29:08 PM PDT 24
Peak memory 228588 kb
Host smart-b073660a-c6b4-4f88-9f44-d02eaf05056f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516625737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.516625737
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.947508703
Short name T265
Test name
Test status
Simulation time 347551693 ps
CPU time 9.29 seconds
Started Jul 21 06:27:23 PM PDT 24
Finished Jul 21 06:27:34 PM PDT 24
Peak memory 212220 kb
Host smart-fad1c512-730a-4a65-b005-ca4b87657fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947508703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.947508703
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1588510261
Short name T210
Test name
Test status
Simulation time 5659741953 ps
CPU time 13.17 seconds
Started Jul 21 06:27:21 PM PDT 24
Finished Jul 21 06:27:35 PM PDT 24
Peak memory 211412 kb
Host smart-eb217619-c206-49e6-bd1b-9eb2dd7dbb5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588510261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1588510261
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3417591035
Short name T221
Test name
Test status
Simulation time 16414310989 ps
CPU time 40.2 seconds
Started Jul 21 06:27:22 PM PDT 24
Finished Jul 21 06:28:03 PM PDT 24
Peak memory 214264 kb
Host smart-5dea1765-ab6d-4b8c-8ddf-135bd9f990c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417591035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3417591035
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.663167185
Short name T299
Test name
Test status
Simulation time 6228754659 ps
CPU time 15.83 seconds
Started Jul 21 06:27:21 PM PDT 24
Finished Jul 21 06:27:37 PM PDT 24
Peak memory 211344 kb
Host smart-2fa1631d-1dc1-4d41-8cbf-1cb0a860d7de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663167185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.663167185
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3601576322
Short name T19
Test name
Test status
Simulation time 1251617511 ps
CPU time 6.2 seconds
Started Jul 21 06:27:22 PM PDT 24
Finished Jul 21 06:27:29 PM PDT 24
Peak memory 211400 kb
Host smart-8dd5fce3-158f-4085-91bf-29d0bfdaa767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601576322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3601576322
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2926323986
Short name T250
Test name
Test status
Simulation time 1040652317 ps
CPU time 85.81 seconds
Started Jul 21 06:27:25 PM PDT 24
Finished Jul 21 06:28:52 PM PDT 24
Peak memory 228052 kb
Host smart-f78f0d4d-0806-44ef-97c0-8713a5cc85ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926323986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2926323986
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2789343809
Short name T144
Test name
Test status
Simulation time 58779287636 ps
CPU time 32.72 seconds
Started Jul 21 06:27:23 PM PDT 24
Finished Jul 21 06:27:57 PM PDT 24
Peak memory 211656 kb
Host smart-18985816-f410-4b08-9eaa-f705819e49b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789343809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2789343809
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2584621717
Short name T350
Test name
Test status
Simulation time 1330548631 ps
CPU time 5.82 seconds
Started Jul 21 06:27:23 PM PDT 24
Finished Jul 21 06:27:30 PM PDT 24
Peak memory 211452 kb
Host smart-2b7fec47-3ddf-4673-99df-c5281f652e49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584621717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2584621717
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4070512778
Short name T242
Test name
Test status
Simulation time 529291216 ps
CPU time 9.96 seconds
Started Jul 21 06:27:25 PM PDT 24
Finished Jul 21 06:27:36 PM PDT 24
Peak memory 214036 kb
Host smart-8971d02e-e811-42ed-83b9-6f9065271213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070512778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4070512778
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3728664681
Short name T318
Test name
Test status
Simulation time 5203853826 ps
CPU time 23.28 seconds
Started Jul 21 06:27:22 PM PDT 24
Finished Jul 21 06:27:46 PM PDT 24
Peak memory 216620 kb
Host smart-054f6289-af15-4576-a2ac-289028f919ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728664681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3728664681
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1399817150
Short name T209
Test name
Test status
Simulation time 4474696201 ps
CPU time 15.72 seconds
Started Jul 21 06:27:23 PM PDT 24
Finished Jul 21 06:27:40 PM PDT 24
Peak memory 211380 kb
Host smart-364b449a-d468-407c-a416-606c34a3098b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399817150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1399817150
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1702976488
Short name T261
Test name
Test status
Simulation time 120284279239 ps
CPU time 236.21 seconds
Started Jul 21 06:27:28 PM PDT 24
Finished Jul 21 06:31:27 PM PDT 24
Peak memory 212824 kb
Host smart-4161b97f-89a2-4e9c-9a89-d2e6327151af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702976488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1702976488
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.672328730
Short name T23
Test name
Test status
Simulation time 2017580974 ps
CPU time 21.32 seconds
Started Jul 21 06:27:24 PM PDT 24
Finished Jul 21 06:27:46 PM PDT 24
Peak memory 212256 kb
Host smart-7d332771-979d-49a0-bd54-ff8f8509e1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672328730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.672328730
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3008832882
Short name T185
Test name
Test status
Simulation time 1570577161 ps
CPU time 7.98 seconds
Started Jul 21 06:27:24 PM PDT 24
Finished Jul 21 06:27:33 PM PDT 24
Peak memory 211388 kb
Host smart-35d21937-bc2b-4677-906d-13ba39542fa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008832882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3008832882
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3192250717
Short name T125
Test name
Test status
Simulation time 770779860 ps
CPU time 13.51 seconds
Started Jul 21 06:27:23 PM PDT 24
Finished Jul 21 06:27:38 PM PDT 24
Peak memory 213360 kb
Host smart-dec5f8aa-cd9d-4beb-8729-3c4135657291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192250717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3192250717
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1766317597
Short name T322
Test name
Test status
Simulation time 48004134241 ps
CPU time 42.15 seconds
Started Jul 21 06:27:23 PM PDT 24
Finished Jul 21 06:28:06 PM PDT 24
Peak memory 216688 kb
Host smart-9831dbd0-7a40-41f1-8267-ce17e4cd97fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766317597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1766317597
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2499256448
Short name T337
Test name
Test status
Simulation time 332829562 ps
CPU time 4.12 seconds
Started Jul 21 06:27:25 PM PDT 24
Finished Jul 21 06:27:30 PM PDT 24
Peak memory 211296 kb
Host smart-be52d925-2912-427d-8da4-ea560566abfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499256448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2499256448
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2719322793
Short name T244
Test name
Test status
Simulation time 83605042412 ps
CPU time 314.32 seconds
Started Jul 21 06:27:22 PM PDT 24
Finished Jul 21 06:32:38 PM PDT 24
Peak memory 237856 kb
Host smart-552f8bfe-cac8-4643-8906-1952efbbce2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719322793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2719322793
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2162023660
Short name T278
Test name
Test status
Simulation time 13891907410 ps
CPU time 30.71 seconds
Started Jul 21 06:27:22 PM PDT 24
Finished Jul 21 06:27:53 PM PDT 24
Peak memory 212180 kb
Host smart-8d98816f-951d-4caf-b7e1-fdb18d07fadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162023660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2162023660
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1198472694
Short name T292
Test name
Test status
Simulation time 6715819633 ps
CPU time 14.82 seconds
Started Jul 21 06:27:23 PM PDT 24
Finished Jul 21 06:27:39 PM PDT 24
Peak memory 211448 kb
Host smart-92feceb8-5e7b-4ba2-bcb2-a6f1d7ccd497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198472694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1198472694
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2901456543
Short name T27
Test name
Test status
Simulation time 873607565 ps
CPU time 13.66 seconds
Started Jul 21 06:27:27 PM PDT 24
Finished Jul 21 06:27:42 PM PDT 24
Peak memory 213304 kb
Host smart-201842cd-696b-4e88-917a-522e308158c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901456543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2901456543
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.800004448
Short name T214
Test name
Test status
Simulation time 23196061287 ps
CPU time 49.41 seconds
Started Jul 21 06:27:24 PM PDT 24
Finished Jul 21 06:28:15 PM PDT 24
Peak memory 214308 kb
Host smart-db1a2e73-b23c-465a-8d84-fc7028611261
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800004448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.800004448
Directory /workspace/9.rom_ctrl_stress_all/latest
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