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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.18 96.89 91.99 97.67 100.00 98.28 97.30 98.14


Total test records in report: 467
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T298 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1588489341 Jul 22 06:22:23 PM PDT 24 Jul 22 06:26:01 PM PDT 24 49904162472 ps
T299 /workspace/coverage/default/24.rom_ctrl_alert_test.3287640429 Jul 22 06:22:13 PM PDT 24 Jul 22 06:22:27 PM PDT 24 16960088960 ps
T300 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1270677946 Jul 22 06:22:19 PM PDT 24 Jul 22 06:57:36 PM PDT 24 56122510982 ps
T301 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1713069797 Jul 22 06:21:59 PM PDT 24 Jul 22 06:22:09 PM PDT 24 1607605256 ps
T302 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.545740046 Jul 22 06:22:10 PM PDT 24 Jul 22 06:24:53 PM PDT 24 34359166258 ps
T303 /workspace/coverage/default/46.rom_ctrl_stress_all.2546605856 Jul 22 06:22:38 PM PDT 24 Jul 22 06:24:23 PM PDT 24 48217121581 ps
T304 /workspace/coverage/default/1.rom_ctrl_smoke.277010020 Jul 22 06:22:02 PM PDT 24 Jul 22 06:22:13 PM PDT 24 732788174 ps
T305 /workspace/coverage/default/17.rom_ctrl_alert_test.1418539305 Jul 22 06:22:15 PM PDT 24 Jul 22 06:22:22 PM PDT 24 175190112 ps
T306 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3656664411 Jul 22 06:22:11 PM PDT 24 Jul 22 06:28:55 PM PDT 24 189040091275 ps
T307 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2209267465 Jul 22 06:22:42 PM PDT 24 Jul 22 06:22:56 PM PDT 24 1277714817 ps
T308 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2609213304 Jul 22 06:22:42 PM PDT 24 Jul 22 06:29:48 PM PDT 24 98868817289 ps
T309 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4061155710 Jul 22 06:22:23 PM PDT 24 Jul 22 06:27:26 PM PDT 24 140812923772 ps
T22 /workspace/coverage/default/2.rom_ctrl_sec_cm.219733502 Jul 22 06:21:58 PM PDT 24 Jul 22 06:23:01 PM PDT 24 8938603728 ps
T310 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4282468606 Jul 22 06:22:33 PM PDT 24 Jul 22 06:25:01 PM PDT 24 12644037349 ps
T311 /workspace/coverage/default/38.rom_ctrl_stress_all.2312758918 Jul 22 06:22:23 PM PDT 24 Jul 22 06:22:40 PM PDT 24 9219725867 ps
T312 /workspace/coverage/default/17.rom_ctrl_smoke.1870020433 Jul 22 06:22:07 PM PDT 24 Jul 22 06:22:29 PM PDT 24 3581221272 ps
T313 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4077502675 Jul 22 06:22:42 PM PDT 24 Jul 22 06:22:57 PM PDT 24 748702572 ps
T314 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3946137312 Jul 22 06:23:31 PM PDT 24 Jul 22 06:27:13 PM PDT 24 159956029584 ps
T315 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3337969854 Jul 22 06:22:11 PM PDT 24 Jul 22 06:22:43 PM PDT 24 3825538604 ps
T316 /workspace/coverage/default/23.rom_ctrl_alert_test.2406398426 Jul 22 06:22:17 PM PDT 24 Jul 22 06:22:26 PM PDT 24 2418610278 ps
T317 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.777473434 Jul 22 06:22:28 PM PDT 24 Jul 22 06:22:40 PM PDT 24 1649380727 ps
T318 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1106600388 Jul 22 06:22:00 PM PDT 24 Jul 22 06:22:18 PM PDT 24 1464557304 ps
T319 /workspace/coverage/default/40.rom_ctrl_stress_all.2137915926 Jul 22 06:22:57 PM PDT 24 Jul 22 06:23:09 PM PDT 24 222942139 ps
T320 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.507592880 Jul 22 06:22:21 PM PDT 24 Jul 22 06:24:38 PM PDT 24 135693970970 ps
T321 /workspace/coverage/default/27.rom_ctrl_stress_all.2250609401 Jul 22 06:22:13 PM PDT 24 Jul 22 06:22:28 PM PDT 24 1073883418 ps
T322 /workspace/coverage/default/36.rom_ctrl_alert_test.2930568943 Jul 22 06:22:24 PM PDT 24 Jul 22 06:22:40 PM PDT 24 2545024485 ps
T323 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2523052237 Jul 22 06:22:24 PM PDT 24 Jul 22 06:22:47 PM PDT 24 1951857040 ps
T324 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4224496649 Jul 22 06:22:12 PM PDT 24 Jul 22 06:22:21 PM PDT 24 451693554 ps
T325 /workspace/coverage/default/43.rom_ctrl_stress_all.2585311419 Jul 22 06:22:40 PM PDT 24 Jul 22 06:22:55 PM PDT 24 6105846900 ps
T326 /workspace/coverage/default/1.rom_ctrl_alert_test.398735631 Jul 22 06:21:56 PM PDT 24 Jul 22 06:22:01 PM PDT 24 334527216 ps
T327 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3552638774 Jul 22 06:22:23 PM PDT 24 Jul 22 06:22:49 PM PDT 24 16370708986 ps
T328 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.209217451 Jul 22 06:22:08 PM PDT 24 Jul 22 06:22:28 PM PDT 24 1710760584 ps
T329 /workspace/coverage/default/44.rom_ctrl_smoke.3744057511 Jul 22 06:22:42 PM PDT 24 Jul 22 06:23:05 PM PDT 24 1998545327 ps
T330 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2366379523 Jul 22 06:22:36 PM PDT 24 Jul 22 06:22:50 PM PDT 24 519249071 ps
T331 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2105495764 Jul 22 06:22:04 PM PDT 24 Jul 22 06:22:28 PM PDT 24 2462630321 ps
T332 /workspace/coverage/default/25.rom_ctrl_alert_test.2473788606 Jul 22 06:22:23 PM PDT 24 Jul 22 06:22:31 PM PDT 24 1810465322 ps
T333 /workspace/coverage/default/37.rom_ctrl_stress_all.3962073964 Jul 22 06:22:33 PM PDT 24 Jul 22 06:24:36 PM PDT 24 15937700948 ps
T334 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.114874349 Jul 22 06:22:15 PM PDT 24 Jul 22 06:22:26 PM PDT 24 175918591 ps
T335 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2235436740 Jul 22 06:22:12 PM PDT 24 Jul 22 06:50:33 PM PDT 24 42512109442 ps
T336 /workspace/coverage/default/42.rom_ctrl_smoke.1381351766 Jul 22 06:22:36 PM PDT 24 Jul 22 06:23:03 PM PDT 24 5861757523 ps
T337 /workspace/coverage/default/29.rom_ctrl_alert_test.1940501588 Jul 22 06:22:22 PM PDT 24 Jul 22 06:22:29 PM PDT 24 570624478 ps
T338 /workspace/coverage/default/2.rom_ctrl_smoke.674770960 Jul 22 06:21:55 PM PDT 24 Jul 22 06:22:06 PM PDT 24 645882777 ps
T339 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2193895045 Jul 22 06:22:35 PM PDT 24 Jul 22 06:22:44 PM PDT 24 667663782 ps
T340 /workspace/coverage/default/22.rom_ctrl_smoke.2281044154 Jul 22 06:22:13 PM PDT 24 Jul 22 06:22:24 PM PDT 24 788818286 ps
T341 /workspace/coverage/default/34.rom_ctrl_alert_test.1747748985 Jul 22 06:22:22 PM PDT 24 Jul 22 06:22:39 PM PDT 24 1930921638 ps
T342 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1819932876 Jul 22 06:24:39 PM PDT 24 Jul 22 06:24:49 PM PDT 24 1262081256 ps
T343 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2654308768 Jul 22 06:22:13 PM PDT 24 Jul 22 06:22:29 PM PDT 24 17968610381 ps
T344 /workspace/coverage/default/0.rom_ctrl_alert_test.2651965166 Jul 22 06:22:02 PM PDT 24 Jul 22 06:22:13 PM PDT 24 2239904861 ps
T345 /workspace/coverage/default/28.rom_ctrl_alert_test.2091064061 Jul 22 06:22:17 PM PDT 24 Jul 22 06:22:36 PM PDT 24 4350298438 ps
T346 /workspace/coverage/default/36.rom_ctrl_stress_all.234247414 Jul 22 06:22:24 PM PDT 24 Jul 22 06:22:43 PM PDT 24 549433485 ps
T347 /workspace/coverage/default/41.rom_ctrl_smoke.587880326 Jul 22 06:24:39 PM PDT 24 Jul 22 06:24:50 PM PDT 24 2549141716 ps
T348 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1357756446 Jul 22 06:22:07 PM PDT 24 Jul 22 06:22:17 PM PDT 24 175500225 ps
T349 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3247425687 Jul 22 06:22:42 PM PDT 24 Jul 22 06:24:17 PM PDT 24 13008114820 ps
T350 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.715270106 Jul 22 06:22:13 PM PDT 24 Jul 22 06:24:28 PM PDT 24 4480840926 ps
T351 /workspace/coverage/default/31.rom_ctrl_alert_test.2317435095 Jul 22 06:22:17 PM PDT 24 Jul 22 06:22:27 PM PDT 24 2725702385 ps
T352 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1059931142 Jul 22 06:22:37 PM PDT 24 Jul 22 06:22:52 PM PDT 24 661130165 ps
T353 /workspace/coverage/default/1.rom_ctrl_stress_all.4191148246 Jul 22 06:22:09 PM PDT 24 Jul 22 06:22:23 PM PDT 24 489493789 ps
T354 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3022215088 Jul 22 06:22:24 PM PDT 24 Jul 22 06:22:59 PM PDT 24 13128836420 ps
T355 /workspace/coverage/default/13.rom_ctrl_stress_all.3844131153 Jul 22 06:22:11 PM PDT 24 Jul 22 06:22:22 PM PDT 24 575143191 ps
T356 /workspace/coverage/default/43.rom_ctrl_smoke.4150298384 Jul 22 06:22:58 PM PDT 24 Jul 22 06:23:26 PM PDT 24 3032246907 ps
T357 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2809041041 Jul 22 06:22:14 PM PDT 24 Jul 22 06:26:09 PM PDT 24 68844204351 ps
T358 /workspace/coverage/default/14.rom_ctrl_alert_test.1318477801 Jul 22 06:22:11 PM PDT 24 Jul 22 06:22:17 PM PDT 24 437512032 ps
T359 /workspace/coverage/default/29.rom_ctrl_stress_all.389078706 Jul 22 06:22:18 PM PDT 24 Jul 22 06:23:01 PM PDT 24 12550411994 ps
T360 /workspace/coverage/default/45.rom_ctrl_smoke.3151519469 Jul 22 06:24:00 PM PDT 24 Jul 22 06:24:10 PM PDT 24 188141369 ps
T361 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1503068726 Jul 22 06:22:38 PM PDT 24 Jul 22 06:25:41 PM PDT 24 25097021158 ps
T362 /workspace/coverage/default/8.rom_ctrl_smoke.149930140 Jul 22 06:22:12 PM PDT 24 Jul 22 06:22:23 PM PDT 24 185902282 ps
T363 /workspace/coverage/default/23.rom_ctrl_smoke.1750439412 Jul 22 06:22:18 PM PDT 24 Jul 22 06:22:47 PM PDT 24 11011135759 ps
T364 /workspace/coverage/default/30.rom_ctrl_smoke.1607267340 Jul 22 06:22:22 PM PDT 24 Jul 22 06:22:50 PM PDT 24 36034112148 ps
T365 /workspace/coverage/default/12.rom_ctrl_alert_test.365099587 Jul 22 06:22:10 PM PDT 24 Jul 22 06:22:27 PM PDT 24 7876151426 ps
T366 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1986505783 Jul 22 06:22:36 PM PDT 24 Jul 22 06:25:57 PM PDT 24 17412517599 ps
T367 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.58439142 Jul 22 06:22:12 PM PDT 24 Jul 22 06:28:55 PM PDT 24 200715968127 ps
T368 /workspace/coverage/default/20.rom_ctrl_stress_all.2361282961 Jul 22 06:22:15 PM PDT 24 Jul 22 06:22:53 PM PDT 24 6249372991 ps
T56 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2732383734 Jul 22 06:50:06 PM PDT 24 Jul 22 06:50:35 PM PDT 24 574468139 ps
T369 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1781083241 Jul 22 06:49:59 PM PDT 24 Jul 22 06:50:19 PM PDT 24 8468234087 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3892620280 Jul 22 06:51:09 PM PDT 24 Jul 22 06:52:07 PM PDT 24 670211955 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3089557373 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:30 PM PDT 24 8412868411 ps
T57 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3138486761 Jul 22 06:50:03 PM PDT 24 Jul 22 06:50:19 PM PDT 24 1799764113 ps
T372 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3575357176 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:32 PM PDT 24 6747242190 ps
T58 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1506704001 Jul 22 06:50:19 PM PDT 24 Jul 22 06:51:49 PM PDT 24 9627874348 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.159514744 Jul 22 06:49:59 PM PDT 24 Jul 22 06:50:17 PM PDT 24 2114193075 ps
T63 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2494878769 Jul 22 06:50:04 PM PDT 24 Jul 22 06:50:11 PM PDT 24 87951941 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.607340321 Jul 22 06:50:01 PM PDT 24 Jul 22 06:50:15 PM PDT 24 8615800443 ps
T374 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2760664401 Jul 22 06:50:03 PM PDT 24 Jul 22 06:50:17 PM PDT 24 5707954702 ps
T64 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2137975316 Jul 22 06:50:57 PM PDT 24 Jul 22 06:51:47 PM PDT 24 1156442132 ps
T53 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4110661086 Jul 22 06:51:17 PM PDT 24 Jul 22 06:52:52 PM PDT 24 2166706436 ps
T375 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1292882165 Jul 22 06:50:03 PM PDT 24 Jul 22 06:50:15 PM PDT 24 3240968322 ps
T65 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1807280342 Jul 22 06:50:00 PM PDT 24 Jul 22 06:50:17 PM PDT 24 6299765861 ps
T94 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.950649017 Jul 22 06:50:05 PM PDT 24 Jul 22 06:51:03 PM PDT 24 26798722752 ps
T376 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2072553661 Jul 22 06:50:03 PM PDT 24 Jul 22 06:50:21 PM PDT 24 6135017915 ps
T377 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1146507920 Jul 22 06:50:06 PM PDT 24 Jul 22 06:50:23 PM PDT 24 6269298981 ps
T54 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1628686021 Jul 22 06:50:15 PM PDT 24 Jul 22 06:51:34 PM PDT 24 5460718784 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.93504174 Jul 22 06:50:23 PM PDT 24 Jul 22 06:50:46 PM PDT 24 1173850884 ps
T379 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3768383512 Jul 22 06:50:13 PM PDT 24 Jul 22 06:50:27 PM PDT 24 1162406778 ps
T66 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2171446045 Jul 22 06:50:11 PM PDT 24 Jul 22 06:50:24 PM PDT 24 1275575989 ps
T67 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4072336518 Jul 22 06:50:56 PM PDT 24 Jul 22 06:51:47 PM PDT 24 1175606880 ps
T380 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.299102330 Jul 22 06:50:20 PM PDT 24 Jul 22 06:50:36 PM PDT 24 382857568 ps
T68 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3218685711 Jul 22 06:49:58 PM PDT 24 Jul 22 06:50:35 PM PDT 24 2967290665 ps
T69 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2975892909 Jul 22 06:50:06 PM PDT 24 Jul 22 06:50:19 PM PDT 24 1196888365 ps
T70 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2244724386 Jul 22 06:50:00 PM PDT 24 Jul 22 06:50:17 PM PDT 24 7350855471 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3187603986 Jul 22 06:49:56 PM PDT 24 Jul 22 06:50:02 PM PDT 24 109102390 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3512094099 Jul 22 06:50:00 PM PDT 24 Jul 22 06:50:19 PM PDT 24 13292327149 ps
T55 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3595571412 Jul 22 06:49:48 PM PDT 24 Jul 22 06:51:03 PM PDT 24 1494592831 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3469331250 Jul 22 06:51:19 PM PDT 24 Jul 22 06:52:19 PM PDT 24 1149870243 ps
T71 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.560964619 Jul 22 06:50:05 PM PDT 24 Jul 22 06:50:54 PM PDT 24 5161187790 ps
T383 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1248991393 Jul 22 06:50:11 PM PDT 24 Jul 22 06:50:25 PM PDT 24 2765068329 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1402608839 Jul 22 06:49:55 PM PDT 24 Jul 22 06:50:03 PM PDT 24 769739236 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.760406637 Jul 22 06:49:50 PM PDT 24 Jul 22 06:49:59 PM PDT 24 2228004708 ps
T77 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3620730800 Jul 22 06:50:03 PM PDT 24 Jul 22 06:50:20 PM PDT 24 7096668001 ps
T385 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2820688897 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:18 PM PDT 24 171908847 ps
T386 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.353231820 Jul 22 06:50:13 PM PDT 24 Jul 22 06:50:24 PM PDT 24 148967995 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.936718953 Jul 22 06:49:50 PM PDT 24 Jul 22 06:49:56 PM PDT 24 193958493 ps
T78 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4181015476 Jul 22 06:50:13 PM PDT 24 Jul 22 06:50:48 PM PDT 24 22147444151 ps
T388 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2486590387 Jul 22 06:50:30 PM PDT 24 Jul 22 06:50:55 PM PDT 24 4822488293 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3399813070 Jul 22 06:49:55 PM PDT 24 Jul 22 06:50:01 PM PDT 24 85851349 ps
T102 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4237325662 Jul 22 06:50:14 PM PDT 24 Jul 22 06:51:36 PM PDT 24 8372444354 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1791069576 Jul 22 06:50:00 PM PDT 24 Jul 22 06:50:16 PM PDT 24 1529731321 ps
T79 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.735132963 Jul 22 06:49:51 PM PDT 24 Jul 22 06:50:04 PM PDT 24 3014627172 ps
T391 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3545471908 Jul 22 06:50:07 PM PDT 24 Jul 22 06:50:26 PM PDT 24 8911986792 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4194646930 Jul 22 06:49:55 PM PDT 24 Jul 22 06:50:15 PM PDT 24 2054519803 ps
T106 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.127086325 Jul 22 06:49:48 PM PDT 24 Jul 22 06:50:31 PM PDT 24 1874516890 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2839364097 Jul 22 06:49:55 PM PDT 24 Jul 22 06:50:04 PM PDT 24 130216498 ps
T394 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4270365715 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:19 PM PDT 24 347382703 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2628875517 Jul 22 06:50:02 PM PDT 24 Jul 22 06:50:22 PM PDT 24 2572142379 ps
T396 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2826542702 Jul 22 06:50:19 PM PDT 24 Jul 22 06:50:45 PM PDT 24 13422112175 ps
T103 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1871387801 Jul 22 06:50:13 PM PDT 24 Jul 22 06:51:28 PM PDT 24 971356169 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.660580989 Jul 22 06:50:00 PM PDT 24 Jul 22 06:50:18 PM PDT 24 6217992129 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.795118835 Jul 22 06:49:54 PM PDT 24 Jul 22 06:50:10 PM PDT 24 7467091153 ps
T398 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3854977610 Jul 22 06:51:10 PM PDT 24 Jul 22 06:52:07 PM PDT 24 5221213924 ps
T399 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2715402699 Jul 22 06:50:14 PM PDT 24 Jul 22 06:50:30 PM PDT 24 1187177949 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3101472575 Jul 22 06:49:50 PM PDT 24 Jul 22 06:50:07 PM PDT 24 4026445660 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.950265786 Jul 22 06:49:53 PM PDT 24 Jul 22 06:51:20 PM PDT 24 16197090234 ps
T87 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2249684639 Jul 22 06:50:14 PM PDT 24 Jul 22 06:50:29 PM PDT 24 5461159500 ps
T401 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3928712536 Jul 22 06:49:53 PM PDT 24 Jul 22 06:50:00 PM PDT 24 88143117 ps
T107 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4243247018 Jul 22 06:49:52 PM PDT 24 Jul 22 06:50:37 PM PDT 24 1526672519 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3809733220 Jul 22 06:49:50 PM PDT 24 Jul 22 06:50:06 PM PDT 24 3367270116 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.769439896 Jul 22 06:51:10 PM PDT 24 Jul 22 06:52:31 PM PDT 24 38500534771 ps
T112 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.415495429 Jul 22 06:50:00 PM PDT 24 Jul 22 06:51:19 PM PDT 24 3397764176 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2748056353 Jul 22 06:49:55 PM PDT 24 Jul 22 06:50:08 PM PDT 24 993689830 ps
T90 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3987760836 Jul 22 06:50:04 PM PDT 24 Jul 22 06:51:03 PM PDT 24 16344085779 ps
T405 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2831330743 Jul 22 06:50:03 PM PDT 24 Jul 22 06:50:09 PM PDT 24 433667374 ps
T82 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2471681065 Jul 22 06:49:58 PM PDT 24 Jul 22 06:50:13 PM PDT 24 3405502862 ps
T406 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1184650436 Jul 22 06:50:02 PM PDT 24 Jul 22 06:50:08 PM PDT 24 523679009 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.186666975 Jul 22 06:51:17 PM PDT 24 Jul 22 06:52:25 PM PDT 24 2124073467 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1724822402 Jul 22 06:50:00 PM PDT 24 Jul 22 06:50:08 PM PDT 24 88585805 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3894724512 Jul 22 06:49:51 PM PDT 24 Jul 22 06:50:00 PM PDT 24 3751705315 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3776281118 Jul 22 06:50:06 PM PDT 24 Jul 22 06:50:22 PM PDT 24 3477487111 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2485827728 Jul 22 06:49:54 PM PDT 24 Jul 22 06:49:59 PM PDT 24 175331412 ps
T412 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2399248523 Jul 22 06:50:05 PM PDT 24 Jul 22 06:50:11 PM PDT 24 171412194 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4089489933 Jul 22 06:49:53 PM PDT 24 Jul 22 06:50:02 PM PDT 24 640265470 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1122324870 Jul 22 06:49:58 PM PDT 24 Jul 22 06:50:03 PM PDT 24 87233289 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3935399283 Jul 22 06:50:13 PM PDT 24 Jul 22 06:50:32 PM PDT 24 2191101360 ps
T415 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4154567971 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:33 PM PDT 24 2045266881 ps
T104 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1303163616 Jul 22 06:50:03 PM PDT 24 Jul 22 06:50:44 PM PDT 24 3040598522 ps
T416 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1397854581 Jul 22 06:50:00 PM PDT 24 Jul 22 06:50:17 PM PDT 24 2574267508 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4155468141 Jul 22 06:49:53 PM PDT 24 Jul 22 06:50:05 PM PDT 24 1225530914 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1054730422 Jul 22 06:49:56 PM PDT 24 Jul 22 06:50:05 PM PDT 24 178458765 ps
T419 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4224868143 Jul 22 06:50:07 PM PDT 24 Jul 22 06:50:23 PM PDT 24 3620938548 ps
T420 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4287393954 Jul 22 06:50:03 PM PDT 24 Jul 22 06:50:22 PM PDT 24 1423697861 ps
T421 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1046549478 Jul 22 06:50:17 PM PDT 24 Jul 22 06:50:34 PM PDT 24 1028698458 ps
T108 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.500767460 Jul 22 06:50:00 PM PDT 24 Jul 22 06:51:17 PM PDT 24 8668553619 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.468529878 Jul 22 06:49:50 PM PDT 24 Jul 22 06:50:00 PM PDT 24 931670138 ps
T105 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3797722713 Jul 22 06:50:20 PM PDT 24 Jul 22 06:51:09 PM PDT 24 1178390650 ps
T423 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2219850296 Jul 22 06:50:20 PM PDT 24 Jul 22 06:50:46 PM PDT 24 2777861337 ps
T424 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3813519048 Jul 22 06:50:17 PM PDT 24 Jul 22 06:50:37 PM PDT 24 1600707628 ps
T425 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3162454770 Jul 22 06:50:14 PM PDT 24 Jul 22 06:50:32 PM PDT 24 7003621294 ps
T426 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2755228748 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:24 PM PDT 24 994709932 ps
T427 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.266901720 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:24 PM PDT 24 579972344 ps
T428 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4208342766 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:26 PM PDT 24 22866278245 ps
T429 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1534932019 Jul 22 06:50:00 PM PDT 24 Jul 22 06:51:37 PM PDT 24 48243209561 ps
T88 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3120416965 Jul 22 06:49:58 PM PDT 24 Jul 22 06:51:15 PM PDT 24 8325624339 ps
T430 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.669200143 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:58 PM PDT 24 4761438303 ps
T431 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2628432819 Jul 22 06:50:02 PM PDT 24 Jul 22 06:50:11 PM PDT 24 634688360 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2020768619 Jul 22 06:49:53 PM PDT 24 Jul 22 06:50:38 PM PDT 24 6869507909 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3772530709 Jul 22 06:49:54 PM PDT 24 Jul 22 06:50:10 PM PDT 24 1941424047 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2048174113 Jul 22 06:50:02 PM PDT 24 Jul 22 06:50:49 PM PDT 24 2007568597 ps
T111 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2216657054 Jul 22 06:50:03 PM PDT 24 Jul 22 06:50:43 PM PDT 24 1774101785 ps
T434 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1127874961 Jul 22 06:50:15 PM PDT 24 Jul 22 06:50:38 PM PDT 24 1588750411 ps
T435 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3556568976 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:35 PM PDT 24 5484394570 ps
T113 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3036666867 Jul 22 06:50:16 PM PDT 24 Jul 22 06:51:08 PM PDT 24 1865064881 ps
T436 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1405791998 Jul 22 06:50:03 PM PDT 24 Jul 22 06:50:09 PM PDT 24 333006964 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1429137529 Jul 22 06:49:52 PM PDT 24 Jul 22 06:50:07 PM PDT 24 1751381524 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3551882756 Jul 22 06:49:58 PM PDT 24 Jul 22 06:51:24 PM PDT 24 10782883128 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3885521320 Jul 22 06:49:55 PM PDT 24 Jul 22 06:50:11 PM PDT 24 6971554672 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1857350234 Jul 22 06:50:13 PM PDT 24 Jul 22 06:50:31 PM PDT 24 3279402547 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.297497081 Jul 22 06:49:51 PM PDT 24 Jul 22 06:50:06 PM PDT 24 1529586860 ps
T441 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.193233894 Jul 22 06:49:51 PM PDT 24 Jul 22 06:50:11 PM PDT 24 2246564577 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.243403455 Jul 22 06:49:51 PM PDT 24 Jul 22 06:49:56 PM PDT 24 346391983 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.676142781 Jul 22 06:49:54 PM PDT 24 Jul 22 06:49:59 PM PDT 24 90018753 ps
T114 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4084822191 Jul 22 06:50:01 PM PDT 24 Jul 22 06:51:21 PM PDT 24 13915820197 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.409890908 Jul 22 06:50:20 PM PDT 24 Jul 22 06:50:36 PM PDT 24 1211799645 ps
T85 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3882785967 Jul 22 06:50:16 PM PDT 24 Jul 22 06:51:15 PM PDT 24 11723714568 ps
T445 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2050134593 Jul 22 06:50:27 PM PDT 24 Jul 22 06:50:52 PM PDT 24 1276318770 ps
T446 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1685335142 Jul 22 06:50:02 PM PDT 24 Jul 22 06:50:17 PM PDT 24 2269368407 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1473966168 Jul 22 06:49:52 PM PDT 24 Jul 22 06:50:08 PM PDT 24 2292511777 ps
T448 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3703707820 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:40 PM PDT 24 1581265491 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.659474095 Jul 22 06:49:49 PM PDT 24 Jul 22 06:50:00 PM PDT 24 1602837351 ps
T450 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3016584589 Jul 22 06:50:11 PM PDT 24 Jul 22 06:51:28 PM PDT 24 8006439406 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2859045134 Jul 22 06:50:29 PM PDT 24 Jul 22 06:50:55 PM PDT 24 4920073658 ps
T452 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3856726675 Jul 22 06:50:14 PM PDT 24 Jul 22 06:50:28 PM PDT 24 9589168805 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3442594414 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:25 PM PDT 24 2067670798 ps
T454 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1215898992 Jul 22 06:50:01 PM PDT 24 Jul 22 06:50:47 PM PDT 24 1501455822 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2503905792 Jul 22 06:49:54 PM PDT 24 Jul 22 06:50:14 PM PDT 24 9472755123 ps
T456 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.53234407 Jul 22 06:49:56 PM PDT 24 Jul 22 06:50:11 PM PDT 24 1751703950 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2831950133 Jul 22 06:49:50 PM PDT 24 Jul 22 06:50:04 PM PDT 24 2908091837 ps
T110 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.913528531 Jul 22 06:50:10 PM PDT 24 Jul 22 06:51:24 PM PDT 24 969825133 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.625770086 Jul 22 06:49:50 PM PDT 24 Jul 22 06:50:05 PM PDT 24 3297702808 ps
T459 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.258635269 Jul 22 06:50:19 PM PDT 24 Jul 22 06:50:37 PM PDT 24 2428301457 ps
T89 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4248479681 Jul 22 06:50:13 PM PDT 24 Jul 22 06:51:25 PM PDT 24 7421010207 ps
T460 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3163340280 Jul 22 06:50:00 PM PDT 24 Jul 22 06:50:14 PM PDT 24 1132427691 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.75980383 Jul 22 06:49:58 PM PDT 24 Jul 22 06:50:04 PM PDT 24 90009377 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2460094560 Jul 22 06:49:51 PM PDT 24 Jul 22 06:50:20 PM PDT 24 1733507214 ps
T462 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2733302836 Jul 22 06:50:00 PM PDT 24 Jul 22 06:50:39 PM PDT 24 12272456183 ps
T463 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2851408613 Jul 22 06:50:05 PM PDT 24 Jul 22 06:50:16 PM PDT 24 3564840217 ps
T464 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.967320980 Jul 22 06:50:16 PM PDT 24 Jul 22 06:50:58 PM PDT 24 391678329 ps
T465 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.266866117 Jul 22 06:50:02 PM PDT 24 Jul 22 06:51:36 PM PDT 24 52303209143 ps
T466 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2219783732 Jul 22 06:50:12 PM PDT 24 Jul 22 06:50:19 PM PDT 24 85760753 ps
T467 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.749919770 Jul 22 06:49:59 PM PDT 24 Jul 22 06:50:15 PM PDT 24 7176275115 ps

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1430783114
Short name T7
Test name
Test status
Simulation time 71013671758 ps
CPU time 2600.2 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 07:05:37 PM PDT 24
Peak memory 238648 kb
Host smart-f1d34791-557a-4d30-93e0-6b72a3d02aa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430783114 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1430783114
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.441876598
Short name T13
Test name
Test status
Simulation time 69137664810 ps
CPU time 313.78 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:27:38 PM PDT 24
Peak memory 212676 kb
Host smart-b7165b6f-6517-4bfb-8ef9-5aa87065e610
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441876598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.441876598
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1628686021
Short name T54
Test name
Test status
Simulation time 5460718784 ps
CPU time 74.83 seconds
Started Jul 22 06:50:15 PM PDT 24
Finished Jul 22 06:51:34 PM PDT 24
Peak memory 211556 kb
Host smart-ed16ca3c-8cd4-4e83-97a9-2f7e7c783d19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628686021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1628686021
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.286762678
Short name T3
Test name
Test status
Simulation time 176326271418 ps
CPU time 420.18 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:29:16 PM PDT 24
Peak memory 233812 kb
Host smart-db71e41a-1334-4f75-a1b5-8408538250c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286762678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.286762678
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4271911225
Short name T6
Test name
Test status
Simulation time 20526622786 ps
CPU time 127.81 seconds
Started Jul 22 06:22:30 PM PDT 24
Finished Jul 22 06:24:38 PM PDT 24
Peak memory 219212 kb
Host smart-1549dca3-594f-4b00-8f84-901b41ca3a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271911225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4271911225
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3900780033
Short name T14
Test name
Test status
Simulation time 1479058358 ps
CPU time 59.77 seconds
Started Jul 22 06:22:27 PM PDT 24
Finished Jul 22 06:23:29 PM PDT 24
Peak memory 236812 kb
Host smart-11446b5f-ebc7-467a-a5b8-b712014f7280
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900780033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3900780033
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1506704001
Short name T58
Test name
Test status
Simulation time 9627874348 ps
CPU time 81.19 seconds
Started Jul 22 06:50:19 PM PDT 24
Finished Jul 22 06:51:49 PM PDT 24
Peak memory 211700 kb
Host smart-d8774020-926e-46bb-8141-fe60ad38fe8d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506704001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1506704001
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.913528531
Short name T110
Test name
Test status
Simulation time 969825133 ps
CPU time 72.34 seconds
Started Jul 22 06:50:10 PM PDT 24
Finished Jul 22 06:51:24 PM PDT 24
Peak memory 212104 kb
Host smart-2d8055cb-636a-4522-b798-57df4fc72906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913528531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.913528531
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2276808924
Short name T131
Test name
Test status
Simulation time 1935737985 ps
CPU time 15.96 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 211368 kb
Host smart-558f09e4-a89f-41a1-9b60-8735c8582e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276808924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2276808924
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.31162326
Short name T41
Test name
Test status
Simulation time 1861619304 ps
CPU time 13.36 seconds
Started Jul 22 06:22:46 PM PDT 24
Finished Jul 22 06:23:00 PM PDT 24
Peak memory 212012 kb
Host smart-ef523926-6b44-4b5a-980e-6b6cdfd24731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31162326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.31162326
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3551882756
Short name T84
Test name
Test status
Simulation time 10782883128 ps
CPU time 84.93 seconds
Started Jul 22 06:49:58 PM PDT 24
Finished Jul 22 06:51:24 PM PDT 24
Peak memory 210824 kb
Host smart-cf572e55-c056-48d9-833d-8666fcdc1d48
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551882756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3551882756
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1571204387
Short name T40
Test name
Test status
Simulation time 665568978 ps
CPU time 9.36 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:25 PM PDT 24
Peak memory 211900 kb
Host smart-8fe95d9e-09d5-4096-9a3d-f8a56b1c33aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571204387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1571204387
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.543190744
Short name T46
Test name
Test status
Simulation time 338854608429 ps
CPU time 1557.07 seconds
Started Jul 22 06:24:39 PM PDT 24
Finished Jul 22 06:50:37 PM PDT 24
Peak memory 235596 kb
Host smart-f6b91bf4-8cf1-43f3-a8eb-180b1132ebe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543190744 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.543190744
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4243247018
Short name T107
Test name
Test status
Simulation time 1526672519 ps
CPU time 43.25 seconds
Started Jul 22 06:49:52 PM PDT 24
Finished Jul 22 06:50:37 PM PDT 24
Peak memory 218320 kb
Host smart-bb3245b0-2b03-45af-9818-ea58e3148ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243247018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4243247018
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4237325662
Short name T102
Test name
Test status
Simulation time 8372444354 ps
CPU time 77.5 seconds
Started Jul 22 06:50:14 PM PDT 24
Finished Jul 22 06:51:36 PM PDT 24
Peak memory 212444 kb
Host smart-e707ab1f-1574-4c04-af71-b9b0b012e480
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237325662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.4237325662
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.500767460
Short name T108
Test name
Test status
Simulation time 8668553619 ps
CPU time 75.73 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:51:17 PM PDT 24
Peak memory 218816 kb
Host smart-e56c60ef-d753-44e0-8c2d-d1be9baac4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500767460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.500767460
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.560964619
Short name T71
Test name
Test status
Simulation time 5161187790 ps
CPU time 47.51 seconds
Started Jul 22 06:50:05 PM PDT 24
Finished Jul 22 06:50:54 PM PDT 24
Peak memory 210784 kb
Host smart-f371155b-f797-49ea-a2f6-ab6605a5e8fb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560964619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.560964619
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.697515339
Short name T12
Test name
Test status
Simulation time 52175005264 ps
CPU time 6949.64 seconds
Started Jul 22 06:23:05 PM PDT 24
Finished Jul 22 08:18:56 PM PDT 24
Peak memory 235516 kb
Host smart-876137c7-1437-45fc-a3b4-b09e4adbfc50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697515339 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.697515339
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.795118835
Short name T80
Test name
Test status
Simulation time 7467091153 ps
CPU time 15.05 seconds
Started Jul 22 06:49:54 PM PDT 24
Finished Jul 22 06:50:10 PM PDT 24
Peak memory 218616 kb
Host smart-8e682c57-d9fc-4fd7-b113-d6548e6bf922
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795118835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.795118835
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3772530709
Short name T433
Test name
Test status
Simulation time 1941424047 ps
CPU time 15.19 seconds
Started Jul 22 06:49:54 PM PDT 24
Finished Jul 22 06:50:10 PM PDT 24
Peak memory 218220 kb
Host smart-299e3918-64f4-4631-a46c-39cb0ea8909b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772530709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3772530709
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3809733220
Short name T402
Test name
Test status
Simulation time 3367270116 ps
CPU time 14.82 seconds
Started Jul 22 06:49:50 PM PDT 24
Finished Jul 22 06:50:06 PM PDT 24
Peak memory 210536 kb
Host smart-2035c711-5a6c-44cc-81ad-6eacaf1409ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809733220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3809733220
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3187603986
Short name T381
Test name
Test status
Simulation time 109102390 ps
CPU time 5.25 seconds
Started Jul 22 06:49:56 PM PDT 24
Finished Jul 22 06:50:02 PM PDT 24
Peak memory 218820 kb
Host smart-9aa398db-811d-476a-ae35-e3d43eca5d92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187603986 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3187603986
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.735132963
Short name T79
Test name
Test status
Simulation time 3014627172 ps
CPU time 12.52 seconds
Started Jul 22 06:49:51 PM PDT 24
Finished Jul 22 06:50:04 PM PDT 24
Peak memory 218696 kb
Host smart-2262e44a-1107-4dff-a228-4b7d251bb28d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735132963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.735132963
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2831950133
Short name T457
Test name
Test status
Simulation time 2908091837 ps
CPU time 12.83 seconds
Started Jul 22 06:49:50 PM PDT 24
Finished Jul 22 06:50:04 PM PDT 24
Peak memory 210448 kb
Host smart-83196c1d-9995-4fbe-bfc4-bd225829d4b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831950133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2831950133
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3089557373
Short name T371
Test name
Test status
Simulation time 8412868411 ps
CPU time 16.11 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:30 PM PDT 24
Peak memory 210500 kb
Host smart-0cd26e1e-4787-4a11-9fcd-1db017cb6230
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089557373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3089557373
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2485827728
Short name T411
Test name
Test status
Simulation time 175331412 ps
CPU time 4.37 seconds
Started Jul 22 06:49:54 PM PDT 24
Finished Jul 22 06:49:59 PM PDT 24
Peak memory 218060 kb
Host smart-b8746581-8fc3-42b2-8c0b-46094cc40fb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485827728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2485827728
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2839364097
Short name T393
Test name
Test status
Simulation time 130216498 ps
CPU time 7.32 seconds
Started Jul 22 06:49:55 PM PDT 24
Finished Jul 22 06:50:04 PM PDT 24
Peak memory 218776 kb
Host smart-ca47bf50-ade9-4b19-ac6a-c1c98e4bb783
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839364097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2839364097
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1429137529
Short name T437
Test name
Test status
Simulation time 1751381524 ps
CPU time 13.44 seconds
Started Jul 22 06:49:52 PM PDT 24
Finished Jul 22 06:50:07 PM PDT 24
Peak memory 217656 kb
Host smart-f13f24dc-be07-4708-91b7-85fec7e37973
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429137529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1429137529
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4155468141
Short name T417
Test name
Test status
Simulation time 1225530914 ps
CPU time 11.44 seconds
Started Jul 22 06:49:53 PM PDT 24
Finished Jul 22 06:50:05 PM PDT 24
Peak memory 218680 kb
Host smart-d9333704-5a7f-4252-9fb0-3ebacffbf6df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155468141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4155468141
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.659474095
Short name T449
Test name
Test status
Simulation time 1602837351 ps
CPU time 10.62 seconds
Started Jul 22 06:49:49 PM PDT 24
Finished Jul 22 06:50:00 PM PDT 24
Peak memory 217320 kb
Host smart-67835177-f6ac-430e-bcb8-ab6e4e092158
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659474095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.659474095
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.625770086
Short name T458
Test name
Test status
Simulation time 3297702808 ps
CPU time 13.51 seconds
Started Jul 22 06:49:50 PM PDT 24
Finished Jul 22 06:50:05 PM PDT 24
Peak memory 218948 kb
Host smart-7048a826-1970-4ee2-8762-7bdd2db9d393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625770086 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.625770086
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1473966168
Short name T447
Test name
Test status
Simulation time 2292511777 ps
CPU time 14.52 seconds
Started Jul 22 06:49:52 PM PDT 24
Finished Jul 22 06:50:08 PM PDT 24
Peak memory 210596 kb
Host smart-9b0e1f41-60f0-4e61-97e4-bb04ccbef727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473966168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1473966168
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.243403455
Short name T442
Test name
Test status
Simulation time 346391983 ps
CPU time 4.3 seconds
Started Jul 22 06:49:51 PM PDT 24
Finished Jul 22 06:49:56 PM PDT 24
Peak memory 210340 kb
Host smart-d7c9c73e-ff0d-4485-a38e-648b45a7b2af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243403455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.243403455
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.760406637
Short name T384
Test name
Test status
Simulation time 2228004708 ps
CPU time 7.67 seconds
Started Jul 22 06:49:50 PM PDT 24
Finished Jul 22 06:49:59 PM PDT 24
Peak memory 210472 kb
Host smart-aa8a8386-9761-4b9e-80c8-d6efdae2f110
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760406637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
760406637
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.193233894
Short name T441
Test name
Test status
Simulation time 2246564577 ps
CPU time 18.79 seconds
Started Jul 22 06:49:51 PM PDT 24
Finished Jul 22 06:50:11 PM PDT 24
Peak memory 210664 kb
Host smart-e5f2ba3a-5ba4-44a7-a869-6aa452526800
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193233894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.193233894
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2748056353
Short name T404
Test name
Test status
Simulation time 993689830 ps
CPU time 11.92 seconds
Started Jul 22 06:49:55 PM PDT 24
Finished Jul 22 06:50:08 PM PDT 24
Peak memory 210608 kb
Host smart-0bd4575a-b77f-4e55-be1b-dbf11b6ac43e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748056353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2748056353
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4194646930
Short name T392
Test name
Test status
Simulation time 2054519803 ps
CPU time 18.63 seconds
Started Jul 22 06:49:55 PM PDT 24
Finished Jul 22 06:50:15 PM PDT 24
Peak memory 218772 kb
Host smart-5b47831e-47fa-4fcb-ad04-48cc3e825346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194646930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4194646930
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.127086325
Short name T106
Test name
Test status
Simulation time 1874516890 ps
CPU time 42.14 seconds
Started Jul 22 06:49:48 PM PDT 24
Finished Jul 22 06:50:31 PM PDT 24
Peak memory 211908 kb
Host smart-db8a5001-0bf8-4f01-833d-b55c5713b245
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127086325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.127086325
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2831330743
Short name T405
Test name
Test status
Simulation time 433667374 ps
CPU time 4.46 seconds
Started Jul 22 06:50:03 PM PDT 24
Finished Jul 22 06:50:09 PM PDT 24
Peak memory 218652 kb
Host smart-8744e78b-81ce-4e6b-aa2c-6b3cdbe1a9cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831330743 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2831330743
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.749919770
Short name T467
Test name
Test status
Simulation time 7176275115 ps
CPU time 15.33 seconds
Started Jul 22 06:49:59 PM PDT 24
Finished Jul 22 06:50:15 PM PDT 24
Peak memory 210676 kb
Host smart-d378e313-8e4d-48ed-af33-60ec880d46ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749919770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.749919770
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3163340280
Short name T460
Test name
Test status
Simulation time 1132427691 ps
CPU time 12.7 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:50:14 PM PDT 24
Peak memory 210644 kb
Host smart-b6610481-4c3f-4fe1-84b1-1ff9ad85cd49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163340280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3163340280
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2628875517
Short name T395
Test name
Test status
Simulation time 2572142379 ps
CPU time 17.98 seconds
Started Jul 22 06:50:02 PM PDT 24
Finished Jul 22 06:50:22 PM PDT 24
Peak memory 219056 kb
Host smart-a015266d-9941-4189-ae78-694bd2f6654f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628875517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2628875517
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3797722713
Short name T105
Test name
Test status
Simulation time 1178390650 ps
CPU time 38.79 seconds
Started Jul 22 06:50:20 PM PDT 24
Finished Jul 22 06:51:09 PM PDT 24
Peak memory 218768 kb
Host smart-7bf036e0-0924-4e86-ace0-8da0e7cf4391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797722713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3797722713
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3545471908
Short name T391
Test name
Test status
Simulation time 8911986792 ps
CPU time 17.5 seconds
Started Jul 22 06:50:07 PM PDT 24
Finished Jul 22 06:50:26 PM PDT 24
Peak memory 218912 kb
Host smart-a02457c6-ff68-4d94-a20b-183fcd745732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545471908 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3545471908
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3854977610
Short name T398
Test name
Test status
Simulation time 5221213924 ps
CPU time 9.16 seconds
Started Jul 22 06:51:10 PM PDT 24
Finished Jul 22 06:52:07 PM PDT 24
Peak memory 210628 kb
Host smart-26d48d7b-7fc5-4d5c-a172-9df2b98a6d50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854977610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3854977610
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3987760836
Short name T90
Test name
Test status
Simulation time 16344085779 ps
CPU time 56.54 seconds
Started Jul 22 06:50:04 PM PDT 24
Finished Jul 22 06:51:03 PM PDT 24
Peak memory 211760 kb
Host smart-c3157e12-02a5-43d5-a08e-daa6d689d109
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987760836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3987760836
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1685335142
Short name T446
Test name
Test status
Simulation time 2269368407 ps
CPU time 13.19 seconds
Started Jul 22 06:50:02 PM PDT 24
Finished Jul 22 06:50:17 PM PDT 24
Peak memory 219020 kb
Host smart-9dc281e8-9bd1-4f8a-9e1d-6eb654ca2bd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685335142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1685335142
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3892620280
Short name T370
Test name
Test status
Simulation time 670211955 ps
CPU time 10.05 seconds
Started Jul 22 06:51:09 PM PDT 24
Finished Jul 22 06:52:07 PM PDT 24
Peak memory 218824 kb
Host smart-d9cc6aaf-88a4-4afa-974c-38c5c61e9dae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892620280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3892620280
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1303163616
Short name T104
Test name
Test status
Simulation time 3040598522 ps
CPU time 39.49 seconds
Started Jul 22 06:50:03 PM PDT 24
Finished Jul 22 06:50:44 PM PDT 24
Peak memory 218820 kb
Host smart-798fb092-eea7-42a0-9da3-925f08fdd2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303163616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1303163616
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1184650436
Short name T406
Test name
Test status
Simulation time 523679009 ps
CPU time 4.72 seconds
Started Jul 22 06:50:02 PM PDT 24
Finished Jul 22 06:50:08 PM PDT 24
Peak memory 218780 kb
Host smart-98c4753d-25bf-46e8-aac6-7df4ccfacad5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184650436 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1184650436
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3620730800
Short name T77
Test name
Test status
Simulation time 7096668001 ps
CPU time 14.44 seconds
Started Jul 22 06:50:03 PM PDT 24
Finished Jul 22 06:50:20 PM PDT 24
Peak memory 218708 kb
Host smart-9a8f6108-e8f2-468b-8d23-791979228194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620730800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3620730800
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2732383734
Short name T56
Test name
Test status
Simulation time 574468139 ps
CPU time 27.02 seconds
Started Jul 22 06:50:06 PM PDT 24
Finished Jul 22 06:50:35 PM PDT 24
Peak memory 210604 kb
Host smart-20bb0005-563b-4a07-b128-31b64eff6a00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732383734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2732383734
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1807280342
Short name T65
Test name
Test status
Simulation time 6299765861 ps
CPU time 15.8 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:50:17 PM PDT 24
Peak memory 218892 kb
Host smart-66f75de8-15ee-47d6-adb3-7e41e995e81f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807280342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1807280342
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2760664401
Short name T374
Test name
Test status
Simulation time 5707954702 ps
CPU time 11.69 seconds
Started Jul 22 06:50:03 PM PDT 24
Finished Jul 22 06:50:17 PM PDT 24
Peak memory 218852 kb
Host smart-dda5ff4a-e49c-476e-b137-59352c9b2f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760664401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2760664401
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2048174113
Short name T109
Test name
Test status
Simulation time 2007568597 ps
CPU time 45.97 seconds
Started Jul 22 06:50:02 PM PDT 24
Finished Jul 22 06:50:49 PM PDT 24
Peak memory 218744 kb
Host smart-31ea5f07-8981-4db1-94c7-218160ca582d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048174113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2048174113
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1046549478
Short name T421
Test name
Test status
Simulation time 1028698458 ps
CPU time 10.64 seconds
Started Jul 22 06:50:17 PM PDT 24
Finished Jul 22 06:50:34 PM PDT 24
Peak memory 218884 kb
Host smart-c941f542-453e-4f97-90c7-c56a5cc8c245
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046549478 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1046549478
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2219783732
Short name T466
Test name
Test status
Simulation time 85760753 ps
CPU time 4.32 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:19 PM PDT 24
Peak memory 210512 kb
Host smart-3531ca5c-875f-4058-a4eb-201ae15a6bd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219783732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2219783732
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.950649017
Short name T94
Test name
Test status
Simulation time 26798722752 ps
CPU time 55.66 seconds
Started Jul 22 06:50:05 PM PDT 24
Finished Jul 22 06:51:03 PM PDT 24
Peak memory 210764 kb
Host smart-6206aaf7-cdb8-47a2-8632-ad7c99e97b5a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950649017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.950649017
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4270365715
Short name T394
Test name
Test status
Simulation time 347382703 ps
CPU time 4.26 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:19 PM PDT 24
Peak memory 218164 kb
Host smart-03d2270f-e349-4939-83e2-94d76a76cf75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270365715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4270365715
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2219850296
Short name T423
Test name
Test status
Simulation time 2777861337 ps
CPU time 14.61 seconds
Started Jul 22 06:50:20 PM PDT 24
Finished Jul 22 06:50:46 PM PDT 24
Peak memory 218760 kb
Host smart-5c99d31d-a95f-452d-86f7-89ac70d55d51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219850296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2219850296
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3768383512
Short name T379
Test name
Test status
Simulation time 1162406778 ps
CPU time 11.34 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:50:27 PM PDT 24
Peak memory 218800 kb
Host smart-63abc136-7655-422f-ba8f-c9f87121a0cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768383512 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3768383512
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2820688897
Short name T385
Test name
Test status
Simulation time 171908847 ps
CPU time 4.38 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:18 PM PDT 24
Peak memory 210480 kb
Host smart-49b8a657-97e7-4c66-a2be-45dd6e17a276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820688897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2820688897
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.669200143
Short name T430
Test name
Test status
Simulation time 4761438303 ps
CPU time 44.6 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:58 PM PDT 24
Peak memory 210776 kb
Host smart-4e4d2d51-1c4b-44a0-9020-5e2df782f6c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669200143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.669200143
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2715402699
Short name T399
Test name
Test status
Simulation time 1187177949 ps
CPU time 11.23 seconds
Started Jul 22 06:50:14 PM PDT 24
Finished Jul 22 06:50:30 PM PDT 24
Peak memory 210704 kb
Host smart-0a89ca74-a735-4768-a2c9-aa3adf1a48bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715402699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2715402699
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.266901720
Short name T427
Test name
Test status
Simulation time 579972344 ps
CPU time 10.11 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:24 PM PDT 24
Peak memory 218800 kb
Host smart-c4086c94-3cc2-4a7b-b058-7d04f36b75c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266901720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.266901720
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4208342766
Short name T428
Test name
Test status
Simulation time 22866278245 ps
CPU time 12.64 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:26 PM PDT 24
Peak memory 218928 kb
Host smart-0f8cc797-3865-4855-b6cf-76bc682c24cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208342766 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4208342766
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2249684639
Short name T87
Test name
Test status
Simulation time 5461159500 ps
CPU time 11.78 seconds
Started Jul 22 06:50:14 PM PDT 24
Finished Jul 22 06:50:29 PM PDT 24
Peak memory 218780 kb
Host smart-ac734d80-83e4-4f18-bcc8-fd602f04f39c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249684639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2249684639
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4072336518
Short name T67
Test name
Test status
Simulation time 1175606880 ps
CPU time 10.76 seconds
Started Jul 22 06:50:56 PM PDT 24
Finished Jul 22 06:51:47 PM PDT 24
Peak memory 218168 kb
Host smart-0cfa15c2-d57d-4d94-a0c7-12f49b57aa29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072336518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4072336518
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1127874961
Short name T434
Test name
Test status
Simulation time 1588750411 ps
CPU time 18.05 seconds
Started Jul 22 06:50:15 PM PDT 24
Finished Jul 22 06:50:38 PM PDT 24
Peak memory 218784 kb
Host smart-c0a4c895-a1e3-4c74-a3c8-7a0f9d2c62fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127874961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1127874961
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3016584589
Short name T450
Test name
Test status
Simulation time 8006439406 ps
CPU time 76.5 seconds
Started Jul 22 06:50:11 PM PDT 24
Finished Jul 22 06:51:28 PM PDT 24
Peak memory 218864 kb
Host smart-a98a29dd-0e07-4b25-9789-049a771f54ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016584589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3016584589
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3856726675
Short name T452
Test name
Test status
Simulation time 9589168805 ps
CPU time 9.51 seconds
Started Jul 22 06:50:14 PM PDT 24
Finished Jul 22 06:50:28 PM PDT 24
Peak memory 218940 kb
Host smart-c6f25841-5434-4724-9853-946a142a572b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856726675 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3856726675
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2171446045
Short name T66
Test name
Test status
Simulation time 1275575989 ps
CPU time 11.88 seconds
Started Jul 22 06:50:11 PM PDT 24
Finished Jul 22 06:50:24 PM PDT 24
Peak memory 218600 kb
Host smart-c678c021-b7eb-4c9d-93ea-251a29fe235e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171446045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2171446045
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3703707820
Short name T448
Test name
Test status
Simulation time 1581265491 ps
CPU time 18.6 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:40 PM PDT 24
Peak memory 210568 kb
Host smart-f9c14f0f-b2c7-46cc-85a6-965e8ef82167
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703707820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3703707820
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3162454770
Short name T425
Test name
Test status
Simulation time 7003621294 ps
CPU time 14.49 seconds
Started Jul 22 06:50:14 PM PDT 24
Finished Jul 22 06:50:32 PM PDT 24
Peak memory 210748 kb
Host smart-29fa6c74-78c3-42e0-b39b-ebcccc5f8e4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162454770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3162454770
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3556568976
Short name T435
Test name
Test status
Simulation time 5484394570 ps
CPU time 14.55 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:35 PM PDT 24
Peak memory 218908 kb
Host smart-f290f2d6-a5bf-48a0-a6c5-e91094ef100b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556568976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3556568976
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1871387801
Short name T103
Test name
Test status
Simulation time 971356169 ps
CPU time 71.63 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:51:28 PM PDT 24
Peak memory 218780 kb
Host smart-275c2b5d-b8b8-4ec4-9813-ebc2b3db85fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871387801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1871387801
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.353231820
Short name T386
Test name
Test status
Simulation time 148967995 ps
CPU time 7.07 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:50:24 PM PDT 24
Peak memory 218892 kb
Host smart-bfc2e2c2-0e7e-4f75-91cb-58e34e75f96a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353231820 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.353231820
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2137975316
Short name T64
Test name
Test status
Simulation time 1156442132 ps
CPU time 10.11 seconds
Started Jul 22 06:50:57 PM PDT 24
Finished Jul 22 06:51:47 PM PDT 24
Peak memory 210516 kb
Host smart-5283fb06-a8e1-48e2-b5f3-6a7f20787ff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137975316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2137975316
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4248479681
Short name T89
Test name
Test status
Simulation time 7421010207 ps
CPU time 68.58 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:51:25 PM PDT 24
Peak memory 211724 kb
Host smart-ddf522ca-db7b-478f-b30c-1b8a5074c762
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248479681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4248479681
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2050134593
Short name T445
Test name
Test status
Simulation time 1276318770 ps
CPU time 11.22 seconds
Started Jul 22 06:50:27 PM PDT 24
Finished Jul 22 06:50:52 PM PDT 24
Peak memory 217440 kb
Host smart-573cadb1-7bf3-484b-8239-677db1fc8d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050134593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2050134593
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3575357176
Short name T372
Test name
Test status
Simulation time 6747242190 ps
CPU time 17.98 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:32 PM PDT 24
Peak memory 218932 kb
Host smart-df1b93c5-e5c7-4423-af91-a577f9b7b6a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575357176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3575357176
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3036666867
Short name T113
Test name
Test status
Simulation time 1865064881 ps
CPU time 46.27 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:51:08 PM PDT 24
Peak memory 211820 kb
Host smart-12e51094-698d-4827-99e0-4f26a3c3b873
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036666867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3036666867
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1248991393
Short name T383
Test name
Test status
Simulation time 2765068329 ps
CPU time 13.01 seconds
Started Jul 22 06:50:11 PM PDT 24
Finished Jul 22 06:50:25 PM PDT 24
Peak memory 218844 kb
Host smart-bb679ca8-1b3a-467f-8510-81045e622fe8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248991393 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1248991393
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3935399283
Short name T414
Test name
Test status
Simulation time 2191101360 ps
CPU time 17.04 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:50:32 PM PDT 24
Peak memory 210564 kb
Host smart-0c3bc3b4-f624-4108-9aa8-713497880c1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935399283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3935399283
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3882785967
Short name T85
Test name
Test status
Simulation time 11723714568 ps
CPU time 53.26 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:51:15 PM PDT 24
Peak memory 210748 kb
Host smart-0888964d-0050-49e8-b6df-6524f131039c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882785967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3882785967
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3813519048
Short name T424
Test name
Test status
Simulation time 1600707628 ps
CPU time 13.94 seconds
Started Jul 22 06:50:17 PM PDT 24
Finished Jul 22 06:50:37 PM PDT 24
Peak memory 218780 kb
Host smart-1ce1ed23-aed4-4569-847e-85893b7ad2cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813519048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3813519048
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4154567971
Short name T415
Test name
Test status
Simulation time 2045266881 ps
CPU time 11.95 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:33 PM PDT 24
Peak memory 218844 kb
Host smart-bab194cc-80d0-4b85-bce8-9b791efa6337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154567971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4154567971
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2826542702
Short name T396
Test name
Test status
Simulation time 13422112175 ps
CPU time 17.55 seconds
Started Jul 22 06:50:19 PM PDT 24
Finished Jul 22 06:50:45 PM PDT 24
Peak memory 218876 kb
Host smart-e538350c-8227-4eb0-abba-bc683f0e31b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826542702 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2826542702
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2486590387
Short name T388
Test name
Test status
Simulation time 4822488293 ps
CPU time 10.76 seconds
Started Jul 22 06:50:30 PM PDT 24
Finished Jul 22 06:50:55 PM PDT 24
Peak memory 210620 kb
Host smart-ba4d9659-4e40-436c-8581-b03b1598fd88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486590387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2486590387
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4181015476
Short name T78
Test name
Test status
Simulation time 22147444151 ps
CPU time 31.03 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:50:48 PM PDT 24
Peak memory 210724 kb
Host smart-0e68fd81-6347-420f-b0b9-805b3a39bd09
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181015476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4181015476
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2859045134
Short name T451
Test name
Test status
Simulation time 4920073658 ps
CPU time 11.56 seconds
Started Jul 22 06:50:29 PM PDT 24
Finished Jul 22 06:50:55 PM PDT 24
Peak memory 218896 kb
Host smart-aedb7d1e-e6d9-4058-8fe3-6c028fb76c38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859045134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2859045134
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1857350234
Short name T439
Test name
Test status
Simulation time 3279402547 ps
CPU time 13.56 seconds
Started Jul 22 06:50:13 PM PDT 24
Finished Jul 22 06:50:31 PM PDT 24
Peak memory 218924 kb
Host smart-01f9514e-91c0-4f2e-b21e-6bc71f8a0f10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857350234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1857350234
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.967320980
Short name T464
Test name
Test status
Simulation time 391678329 ps
CPU time 36.84 seconds
Started Jul 22 06:50:16 PM PDT 24
Finished Jul 22 06:50:58 PM PDT 24
Peak memory 218812 kb
Host smart-ca8e8cc3-d8d5-4d61-a38b-07b758c00063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967320980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.967320980
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2755228748
Short name T426
Test name
Test status
Simulation time 994709932 ps
CPU time 10.24 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:24 PM PDT 24
Peak memory 218648 kb
Host smart-d5707659-e881-42ca-8410-22549751d4b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755228748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2755228748
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4089489933
Short name T413
Test name
Test status
Simulation time 640265470 ps
CPU time 8.49 seconds
Started Jul 22 06:49:53 PM PDT 24
Finished Jul 22 06:50:02 PM PDT 24
Peak memory 217136 kb
Host smart-6c537abd-9b32-418e-b626-f53278d8442d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089489933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4089489933
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3894724512
Short name T409
Test name
Test status
Simulation time 3751705315 ps
CPU time 8.65 seconds
Started Jul 22 06:49:51 PM PDT 24
Finished Jul 22 06:50:00 PM PDT 24
Peak memory 217520 kb
Host smart-f96b4344-ea33-4a80-ab18-2c0dbfd276c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894724512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3894724512
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.936718953
Short name T387
Test name
Test status
Simulation time 193958493 ps
CPU time 4.9 seconds
Started Jul 22 06:49:50 PM PDT 24
Finished Jul 22 06:49:56 PM PDT 24
Peak memory 214684 kb
Host smart-42517da5-391f-4f2f-874a-fd034095c38a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936718953 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.936718953
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.297497081
Short name T440
Test name
Test status
Simulation time 1529586860 ps
CPU time 13.85 seconds
Started Jul 22 06:49:51 PM PDT 24
Finished Jul 22 06:50:06 PM PDT 24
Peak memory 218544 kb
Host smart-37d89cfa-5dfc-45b6-9b7f-25e033fc917f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297497081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.297497081
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3885521320
Short name T438
Test name
Test status
Simulation time 6971554672 ps
CPU time 14.19 seconds
Started Jul 22 06:49:55 PM PDT 24
Finished Jul 22 06:50:11 PM PDT 24
Peak memory 210508 kb
Host smart-de160b9f-80b2-449d-b666-0c8cf4f3b018
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885521320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3885521320
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3101472575
Short name T400
Test name
Test status
Simulation time 4026445660 ps
CPU time 16.17 seconds
Started Jul 22 06:49:50 PM PDT 24
Finished Jul 22 06:50:07 PM PDT 24
Peak memory 210492 kb
Host smart-62d5ebb4-c8fc-48fe-8d30-4eb5cf2e518a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101472575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3101472575
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2460094560
Short name T86
Test name
Test status
Simulation time 1733507214 ps
CPU time 28.16 seconds
Started Jul 22 06:49:51 PM PDT 24
Finished Jul 22 06:50:20 PM PDT 24
Peak memory 210636 kb
Host smart-8cc3f1de-a1fb-4c61-a840-6f2348885e3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460094560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2460094560
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1402608839
Short name T93
Test name
Test status
Simulation time 769739236 ps
CPU time 6.88 seconds
Started Jul 22 06:49:55 PM PDT 24
Finished Jul 22 06:50:03 PM PDT 24
Peak memory 210616 kb
Host smart-bc52fe31-a2be-4a0d-9577-00807c22ecdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402608839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1402608839
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3928712536
Short name T401
Test name
Test status
Simulation time 88143117 ps
CPU time 6.35 seconds
Started Jul 22 06:49:53 PM PDT 24
Finished Jul 22 06:50:00 PM PDT 24
Peak memory 218788 kb
Host smart-aba05f63-959b-4edb-9813-8de40a49ab30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928712536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3928712536
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2020768619
Short name T432
Test name
Test status
Simulation time 6869507909 ps
CPU time 44.43 seconds
Started Jul 22 06:49:53 PM PDT 24
Finished Jul 22 06:50:38 PM PDT 24
Peak memory 218872 kb
Host smart-a9e96443-7687-4a7c-83d3-2e93cd9e6aca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020768619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2020768619
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2471681065
Short name T82
Test name
Test status
Simulation time 3405502862 ps
CPU time 13.75 seconds
Started Jul 22 06:49:58 PM PDT 24
Finished Jul 22 06:50:13 PM PDT 24
Peak memory 210580 kb
Host smart-245164f6-c5aa-44d2-8f7a-c2515db670bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471681065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2471681065
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.53234407
Short name T456
Test name
Test status
Simulation time 1751703950 ps
CPU time 14.33 seconds
Started Jul 22 06:49:56 PM PDT 24
Finished Jul 22 06:50:11 PM PDT 24
Peak memory 210552 kb
Host smart-cf767cdf-6ced-4250-b7d5-2f6071fadc91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53234407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_ba
sh.53234407
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1054730422
Short name T418
Test name
Test status
Simulation time 178458765 ps
CPU time 7.78 seconds
Started Jul 22 06:49:56 PM PDT 24
Finished Jul 22 06:50:05 PM PDT 24
Peak memory 210556 kb
Host smart-313b20a9-7a76-433b-9cdf-49477bd332c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054730422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1054730422
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3442594414
Short name T453
Test name
Test status
Simulation time 2067670798 ps
CPU time 10.49 seconds
Started Jul 22 06:50:12 PM PDT 24
Finished Jul 22 06:50:25 PM PDT 24
Peak memory 212540 kb
Host smart-8acdb284-501a-471e-a16c-48dc25f1cda2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442594414 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3442594414
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1122324870
Short name T83
Test name
Test status
Simulation time 87233289 ps
CPU time 4.27 seconds
Started Jul 22 06:49:58 PM PDT 24
Finished Jul 22 06:50:03 PM PDT 24
Peak memory 210496 kb
Host smart-ae83398f-9038-48e9-9d11-d5b1fedaf1ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122324870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1122324870
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3399813070
Short name T389
Test name
Test status
Simulation time 85851349 ps
CPU time 4.08 seconds
Started Jul 22 06:49:55 PM PDT 24
Finished Jul 22 06:50:01 PM PDT 24
Peak memory 210372 kb
Host smart-c4b16692-2f0a-4cfe-abde-c2ead627b1ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399813070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3399813070
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.676142781
Short name T443
Test name
Test status
Simulation time 90018753 ps
CPU time 4.29 seconds
Started Jul 22 06:49:54 PM PDT 24
Finished Jul 22 06:49:59 PM PDT 24
Peak memory 210392 kb
Host smart-73316e01-62ed-46ed-8f3d-0b7270f81261
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676142781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
676142781
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.950265786
Short name T81
Test name
Test status
Simulation time 16197090234 ps
CPU time 86.88 seconds
Started Jul 22 06:49:53 PM PDT 24
Finished Jul 22 06:51:20 PM PDT 24
Peak memory 210572 kb
Host smart-e3ea16c5-9d11-44bd-8b67-37c0aa4576de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950265786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.950265786
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3469331250
Short name T92
Test name
Test status
Simulation time 1149870243 ps
CPU time 10.47 seconds
Started Jul 22 06:51:19 PM PDT 24
Finished Jul 22 06:52:19 PM PDT 24
Peak memory 218788 kb
Host smart-11e02d5a-46ff-42af-bd04-e2e93e029f07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469331250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3469331250
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.186666975
Short name T407
Test name
Test status
Simulation time 2124073467 ps
CPU time 19.1 seconds
Started Jul 22 06:51:17 PM PDT 24
Finished Jul 22 06:52:25 PM PDT 24
Peak memory 218804 kb
Host smart-f92c66ad-e9bf-4208-bcb1-fa91122ed550
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186666975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.186666975
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3595571412
Short name T55
Test name
Test status
Simulation time 1494592831 ps
CPU time 74.49 seconds
Started Jul 22 06:49:48 PM PDT 24
Finished Jul 22 06:51:03 PM PDT 24
Peak memory 218752 kb
Host smart-68d39087-f195-4dcc-aba9-90e0b3bf5d07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595571412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3595571412
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2975892909
Short name T69
Test name
Test status
Simulation time 1196888365 ps
CPU time 11.42 seconds
Started Jul 22 06:50:06 PM PDT 24
Finished Jul 22 06:50:19 PM PDT 24
Peak memory 210504 kb
Host smart-6e87dedb-4c78-4cef-824b-f3f19f38fa5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975892909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2975892909
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3512094099
Short name T382
Test name
Test status
Simulation time 13292327149 ps
CPU time 17.93 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:50:19 PM PDT 24
Peak memory 210660 kb
Host smart-4badd3e4-5621-4822-a9ac-48eeeb5a729b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512094099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3512094099
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1724822402
Short name T408
Test name
Test status
Simulation time 88585805 ps
CPU time 5.87 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:50:08 PM PDT 24
Peak memory 210580 kb
Host smart-204209bb-9211-45ef-b794-e92b7c6da81a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724822402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1724822402
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.93504174
Short name T378
Test name
Test status
Simulation time 1173850884 ps
CPU time 11.45 seconds
Started Jul 22 06:50:23 PM PDT 24
Finished Jul 22 06:50:46 PM PDT 24
Peak memory 218784 kb
Host smart-cf6b56b3-a624-47b4-9495-b8b04e9e4fd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93504174 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.93504174
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.409890908
Short name T444
Test name
Test status
Simulation time 1211799645 ps
CPU time 6.11 seconds
Started Jul 22 06:50:20 PM PDT 24
Finished Jul 22 06:50:36 PM PDT 24
Peak memory 210500 kb
Host smart-53e0cadd-8100-4c1a-8504-3efef0406e1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409890908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.409890908
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.75980383
Short name T461
Test name
Test status
Simulation time 90009377 ps
CPU time 4.35 seconds
Started Jul 22 06:49:58 PM PDT 24
Finished Jul 22 06:50:04 PM PDT 24
Peak memory 210412 kb
Host smart-617b71d1-6c95-4369-a0db-25a18dba352b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75980383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_
mem_partial_access.75980383
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.468529878
Short name T422
Test name
Test status
Simulation time 931670138 ps
CPU time 9.43 seconds
Started Jul 22 06:49:50 PM PDT 24
Finished Jul 22 06:50:00 PM PDT 24
Peak memory 210392 kb
Host smart-aca0af3d-c735-43a8-9a8d-3929c2c1179f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468529878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
468529878
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3120416965
Short name T88
Test name
Test status
Simulation time 8325624339 ps
CPU time 76.12 seconds
Started Jul 22 06:49:58 PM PDT 24
Finished Jul 22 06:51:15 PM PDT 24
Peak memory 210752 kb
Host smart-a8bd7cb6-128d-45d5-b0bb-9b41f107cb18
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120416965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3120416965
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1791069576
Short name T390
Test name
Test status
Simulation time 1529731321 ps
CPU time 14.9 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:50:16 PM PDT 24
Peak memory 218652 kb
Host smart-36f11de8-794f-4011-afe5-32fd842aaa14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791069576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1791069576
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2503905792
Short name T455
Test name
Test status
Simulation time 9472755123 ps
CPU time 19.43 seconds
Started Jul 22 06:49:54 PM PDT 24
Finished Jul 22 06:50:14 PM PDT 24
Peak memory 218656 kb
Host smart-33462fb3-4574-4943-b5c1-ceff4621a69a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503905792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2503905792
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4110661086
Short name T53
Test name
Test status
Simulation time 2166706436 ps
CPU time 46.13 seconds
Started Jul 22 06:51:17 PM PDT 24
Finished Jul 22 06:52:52 PM PDT 24
Peak memory 211644 kb
Host smart-684a3ac9-4a19-46d0-a2e2-2d7d8a9f99a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110661086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4110661086
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1292882165
Short name T375
Test name
Test status
Simulation time 3240968322 ps
CPU time 9.62 seconds
Started Jul 22 06:50:03 PM PDT 24
Finished Jul 22 06:50:15 PM PDT 24
Peak memory 218888 kb
Host smart-7b22eeb7-c0fe-497d-a068-e6aa814d21d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292882165 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1292882165
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3138486761
Short name T57
Test name
Test status
Simulation time 1799764113 ps
CPU time 13.95 seconds
Started Jul 22 06:50:03 PM PDT 24
Finished Jul 22 06:50:19 PM PDT 24
Peak memory 210424 kb
Host smart-6f2858a1-7c4d-45ac-b899-6a7765bbb9ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138486761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3138486761
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3218685711
Short name T68
Test name
Test status
Simulation time 2967290665 ps
CPU time 35.97 seconds
Started Jul 22 06:49:58 PM PDT 24
Finished Jul 22 06:50:35 PM PDT 24
Peak memory 210672 kb
Host smart-298b3308-b317-4255-aaba-ee4691c37940
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218685711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3218685711
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1397854581
Short name T416
Test name
Test status
Simulation time 2574267508 ps
CPU time 14.94 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:50:17 PM PDT 24
Peak memory 218828 kb
Host smart-1da4cf11-501a-45c0-a789-3d971ff17ea8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397854581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1397854581
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.660580989
Short name T397
Test name
Test status
Simulation time 6217992129 ps
CPU time 15.95 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:50:18 PM PDT 24
Peak memory 218924 kb
Host smart-7d16b0b0-0ff1-4ecf-87ef-8fde7eeb5ea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660580989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.660580989
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2216657054
Short name T111
Test name
Test status
Simulation time 1774101785 ps
CPU time 38.76 seconds
Started Jul 22 06:50:03 PM PDT 24
Finished Jul 22 06:50:43 PM PDT 24
Peak memory 210868 kb
Host smart-60201c28-86a7-44fb-8884-74758cddac46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216657054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2216657054
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.607340321
Short name T373
Test name
Test status
Simulation time 8615800443 ps
CPU time 11.73 seconds
Started Jul 22 06:50:01 PM PDT 24
Finished Jul 22 06:50:15 PM PDT 24
Peak memory 218984 kb
Host smart-a1e6adaf-a936-454e-a5a3-e205ed51e798
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607340321 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.607340321
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2399248523
Short name T412
Test name
Test status
Simulation time 171412194 ps
CPU time 4.2 seconds
Started Jul 22 06:50:05 PM PDT 24
Finished Jul 22 06:50:11 PM PDT 24
Peak memory 217388 kb
Host smart-a324be43-0295-43d8-93b2-1c095b60b3cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399248523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2399248523
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.266866117
Short name T465
Test name
Test status
Simulation time 52303209143 ps
CPU time 91.99 seconds
Started Jul 22 06:50:02 PM PDT 24
Finished Jul 22 06:51:36 PM PDT 24
Peak memory 210752 kb
Host smart-5858684f-85aa-4d63-a560-c4c06bff0537
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266866117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.266866117
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2851408613
Short name T463
Test name
Test status
Simulation time 3564840217 ps
CPU time 9.46 seconds
Started Jul 22 06:50:05 PM PDT 24
Finished Jul 22 06:50:16 PM PDT 24
Peak memory 218828 kb
Host smart-85085083-97c2-4f99-8c90-14831d843f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851408613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2851408613
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1781083241
Short name T369
Test name
Test status
Simulation time 8468234087 ps
CPU time 18.92 seconds
Started Jul 22 06:49:59 PM PDT 24
Finished Jul 22 06:50:19 PM PDT 24
Peak memory 218904 kb
Host smart-49bfec72-12f9-4d38-8a62-baf2bf7ecac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781083241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1781083241
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.415495429
Short name T112
Test name
Test status
Simulation time 3397764176 ps
CPU time 77.07 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:51:19 PM PDT 24
Peak memory 212044 kb
Host smart-c1971005-cc8e-4a2f-b1bd-124eb7650029
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415495429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.415495429
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4224868143
Short name T419
Test name
Test status
Simulation time 3620938548 ps
CPU time 14.72 seconds
Started Jul 22 06:50:07 PM PDT 24
Finished Jul 22 06:50:23 PM PDT 24
Peak memory 218888 kb
Host smart-a01e2315-b3e8-441b-82fd-17c6e10942ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224868143 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4224868143
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3776281118
Short name T410
Test name
Test status
Simulation time 3477487111 ps
CPU time 14.29 seconds
Started Jul 22 06:50:06 PM PDT 24
Finished Jul 22 06:50:22 PM PDT 24
Peak memory 218384 kb
Host smart-80c57724-2a04-436e-af13-e74fb5bd5d6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776281118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3776281118
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.769439896
Short name T403
Test name
Test status
Simulation time 38500534771 ps
CPU time 33.55 seconds
Started Jul 22 06:51:10 PM PDT 24
Finished Jul 22 06:52:31 PM PDT 24
Peak memory 210724 kb
Host smart-05f015fc-9d93-489d-8d48-28313b569109
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769439896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.769439896
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2244724386
Short name T70
Test name
Test status
Simulation time 7350855471 ps
CPU time 14.91 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:50:17 PM PDT 24
Peak memory 218540 kb
Host smart-6d9ec30e-1733-447a-9111-b71c629180ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244724386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2244724386
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4287393954
Short name T420
Test name
Test status
Simulation time 1423697861 ps
CPU time 16.48 seconds
Started Jul 22 06:50:03 PM PDT 24
Finished Jul 22 06:50:22 PM PDT 24
Peak memory 218832 kb
Host smart-3f60d6ec-2792-41a4-af5b-b510769af2b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287393954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4287393954
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1215898992
Short name T454
Test name
Test status
Simulation time 1501455822 ps
CPU time 44.41 seconds
Started Jul 22 06:50:01 PM PDT 24
Finished Jul 22 06:50:47 PM PDT 24
Peak memory 210872 kb
Host smart-dc2aa200-ddd0-4c6b-88a3-a07e21761aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215898992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1215898992
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.258635269
Short name T459
Test name
Test status
Simulation time 2428301457 ps
CPU time 8.27 seconds
Started Jul 22 06:50:19 PM PDT 24
Finished Jul 22 06:50:37 PM PDT 24
Peak memory 218904 kb
Host smart-901803d9-9cf1-499a-8327-bddc05ff1213
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258635269 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.258635269
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2494878769
Short name T63
Test name
Test status
Simulation time 87951941 ps
CPU time 4.23 seconds
Started Jul 22 06:50:04 PM PDT 24
Finished Jul 22 06:50:11 PM PDT 24
Peak memory 210572 kb
Host smart-30bad093-bae2-4813-ba9a-a913ff1b9644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494878769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2494878769
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2733302836
Short name T462
Test name
Test status
Simulation time 12272456183 ps
CPU time 36.83 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:50:39 PM PDT 24
Peak memory 210780 kb
Host smart-eee2ae14-d034-4063-abb7-a14800e9fd3c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733302836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2733302836
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2628432819
Short name T431
Test name
Test status
Simulation time 634688360 ps
CPU time 8.17 seconds
Started Jul 22 06:50:02 PM PDT 24
Finished Jul 22 06:50:11 PM PDT 24
Peak memory 217832 kb
Host smart-9e5ffec1-dd35-4f34-a9a6-3d5867178308
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628432819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2628432819
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1146507920
Short name T377
Test name
Test status
Simulation time 6269298981 ps
CPU time 14.98 seconds
Started Jul 22 06:50:06 PM PDT 24
Finished Jul 22 06:50:23 PM PDT 24
Peak memory 218892 kb
Host smart-ba43154d-7465-4181-8894-1e5abcb8824f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146507920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1146507920
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.299102330
Short name T380
Test name
Test status
Simulation time 382857568 ps
CPU time 4.89 seconds
Started Jul 22 06:50:20 PM PDT 24
Finished Jul 22 06:50:36 PM PDT 24
Peak memory 218836 kb
Host smart-27f89a78-019e-4104-a03e-d1a490f1a676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299102330 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.299102330
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1405791998
Short name T436
Test name
Test status
Simulation time 333006964 ps
CPU time 4.24 seconds
Started Jul 22 06:50:03 PM PDT 24
Finished Jul 22 06:50:09 PM PDT 24
Peak memory 217308 kb
Host smart-f357673a-3543-4f50-8285-b68d7c86afd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405791998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1405791998
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1534932019
Short name T429
Test name
Test status
Simulation time 48243209561 ps
CPU time 94.75 seconds
Started Jul 22 06:50:00 PM PDT 24
Finished Jul 22 06:51:37 PM PDT 24
Peak memory 210768 kb
Host smart-be311f83-9314-4877-a378-2aba7d815c26
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534932019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1534932019
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.159514744
Short name T91
Test name
Test status
Simulation time 2114193075 ps
CPU time 16.99 seconds
Started Jul 22 06:49:59 PM PDT 24
Finished Jul 22 06:50:17 PM PDT 24
Peak memory 210596 kb
Host smart-dbdcd49d-ac68-4076-8219-b504e360cf47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159514744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.159514744
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2072553661
Short name T376
Test name
Test status
Simulation time 6135017915 ps
CPU time 15.36 seconds
Started Jul 22 06:50:03 PM PDT 24
Finished Jul 22 06:50:21 PM PDT 24
Peak memory 218992 kb
Host smart-099b601f-60cf-461d-8a74-9a3a76e34223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072553661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2072553661
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4084822191
Short name T114
Test name
Test status
Simulation time 13915820197 ps
CPU time 78.46 seconds
Started Jul 22 06:50:01 PM PDT 24
Finished Jul 22 06:51:21 PM PDT 24
Peak memory 218868 kb
Host smart-62cedc8e-5999-490f-8d4a-0e1922090f42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084822191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4084822191
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2651965166
Short name T344
Test name
Test status
Simulation time 2239904861 ps
CPU time 10.55 seconds
Started Jul 22 06:22:02 PM PDT 24
Finished Jul 22 06:22:13 PM PDT 24
Peak memory 211416 kb
Host smart-5003cbd7-eae5-459b-81f6-e9e1fd1270c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651965166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2651965166
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2799325354
Short name T285
Test name
Test status
Simulation time 3270155778 ps
CPU time 104.69 seconds
Started Jul 22 06:21:55 PM PDT 24
Finished Jul 22 06:23:40 PM PDT 24
Peak memory 234924 kb
Host smart-04096f74-998d-4344-8892-5807f6e21214
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799325354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2799325354
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3624616658
Short name T225
Test name
Test status
Simulation time 1118751759 ps
CPU time 16.48 seconds
Started Jul 22 06:22:02 PM PDT 24
Finished Jul 22 06:22:19 PM PDT 24
Peak memory 212316 kb
Host smart-704c9dd0-2d84-4994-8e8d-c19f209a3354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624616658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3624616658
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4057949434
Short name T255
Test name
Test status
Simulation time 427524673 ps
CPU time 7.19 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:22:18 PM PDT 24
Peak memory 211388 kb
Host smart-aed51d4d-9ed8-42f3-be70-e66108fabb7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4057949434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4057949434
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3424921895
Short name T15
Test name
Test status
Simulation time 2183471048 ps
CPU time 63.53 seconds
Started Jul 22 06:21:58 PM PDT 24
Finished Jul 22 06:23:02 PM PDT 24
Peak memory 236716 kb
Host smart-3afeb03e-94da-4dc4-9779-e4874a8b9432
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424921895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3424921895
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2159197029
Short name T272
Test name
Test status
Simulation time 775634736 ps
CPU time 14.77 seconds
Started Jul 22 06:22:02 PM PDT 24
Finished Jul 22 06:22:18 PM PDT 24
Peak memory 212096 kb
Host smart-d92dd7fc-33fa-47a6-bc64-fa3f8c1ac9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159197029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2159197029
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3263877808
Short name T193
Test name
Test status
Simulation time 4565699791 ps
CPU time 29.41 seconds
Started Jul 22 06:21:59 PM PDT 24
Finished Jul 22 06:22:29 PM PDT 24
Peak memory 217248 kb
Host smart-55e2ddf6-0988-4f92-b4f1-06a862fe5dc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263877808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3263877808
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1270677946
Short name T300
Test name
Test status
Simulation time 56122510982 ps
CPU time 2116.76 seconds
Started Jul 22 06:22:19 PM PDT 24
Finished Jul 22 06:57:36 PM PDT 24
Peak memory 237176 kb
Host smart-04b57fe7-6754-43f2-ace7-a34e06574b88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270677946 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1270677946
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.398735631
Short name T326
Test name
Test status
Simulation time 334527216 ps
CPU time 4.34 seconds
Started Jul 22 06:21:56 PM PDT 24
Finished Jul 22 06:22:01 PM PDT 24
Peak memory 211348 kb
Host smart-f59e489e-b965-4b6c-bb4d-bf2a300ea7e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398735631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.398735631
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.545740046
Short name T302
Test name
Test status
Simulation time 34359166258 ps
CPU time 161.27 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:24:53 PM PDT 24
Peak memory 225704 kb
Host smart-39cd7cc4-8d81-4087-a786-fbb6824b78bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545740046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.545740046
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.633683914
Short name T154
Test name
Test status
Simulation time 601957977 ps
CPU time 13.33 seconds
Started Jul 22 06:21:58 PM PDT 24
Finished Jul 22 06:22:12 PM PDT 24
Peak memory 212036 kb
Host smart-86c52c03-2d57-42e5-848f-69e6aca4025c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633683914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.633683914
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3851304605
Short name T233
Test name
Test status
Simulation time 6649057787 ps
CPU time 14.29 seconds
Started Jul 22 06:21:55 PM PDT 24
Finished Jul 22 06:22:10 PM PDT 24
Peak memory 211360 kb
Host smart-972f966f-3bf4-4605-ab30-20860a3fde06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851304605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3851304605
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1850857207
Short name T16
Test name
Test status
Simulation time 2832063093 ps
CPU time 105.63 seconds
Started Jul 22 06:21:57 PM PDT 24
Finished Jul 22 06:23:43 PM PDT 24
Peak memory 237136 kb
Host smart-c76b395f-8153-4ca3-beb6-fb429da1d308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850857207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1850857207
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.277010020
Short name T304
Test name
Test status
Simulation time 732788174 ps
CPU time 10.24 seconds
Started Jul 22 06:22:02 PM PDT 24
Finished Jul 22 06:22:13 PM PDT 24
Peak memory 213312 kb
Host smart-148182fe-8aa2-408b-8288-dcfaf19e730c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277010020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.277010020
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4191148246
Short name T353
Test name
Test status
Simulation time 489493789 ps
CPU time 13.26 seconds
Started Jul 22 06:22:09 PM PDT 24
Finished Jul 22 06:22:23 PM PDT 24
Peak memory 213520 kb
Host smart-2861918a-b04a-4f07-8635-1e5e3ec42dac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191148246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4191148246
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1513275243
Short name T278
Test name
Test status
Simulation time 168428920 ps
CPU time 4.25 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:22:19 PM PDT 24
Peak memory 211352 kb
Host smart-d4f4d87f-eae8-471b-8940-18a7e549fcbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513275243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1513275243
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3632387990
Short name T36
Test name
Test status
Simulation time 94995911055 ps
CPU time 258.13 seconds
Started Jul 22 06:22:04 PM PDT 24
Finished Jul 22 06:26:23 PM PDT 24
Peak memory 237876 kb
Host smart-632a3ced-f2b3-409a-a124-b5b61baece07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632387990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3632387990
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1104255691
Short name T119
Test name
Test status
Simulation time 3545305539 ps
CPU time 22.07 seconds
Started Jul 22 06:22:08 PM PDT 24
Finished Jul 22 06:22:30 PM PDT 24
Peak memory 211972 kb
Host smart-aad8d5d2-9e35-494c-a6ce-83ec21abec62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104255691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1104255691
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1850242143
Short name T242
Test name
Test status
Simulation time 1503835749 ps
CPU time 12.05 seconds
Started Jul 22 06:22:08 PM PDT 24
Finished Jul 22 06:22:21 PM PDT 24
Peak memory 211404 kb
Host smart-8b4bcb1d-d04c-4a59-a466-479f71c51101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850242143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1850242143
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1463993694
Short name T218
Test name
Test status
Simulation time 12341592595 ps
CPU time 31.68 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:22:42 PM PDT 24
Peak memory 213856 kb
Host smart-e160ac6a-7b12-4163-8a1e-f45573d9e48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463993694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1463993694
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2334627162
Short name T97
Test name
Test status
Simulation time 3396758774 ps
CPU time 46.33 seconds
Started Jul 22 06:22:04 PM PDT 24
Finished Jul 22 06:22:51 PM PDT 24
Peak memory 216132 kb
Host smart-875fe053-9e2b-4ca4-9a35-b76b18b08981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334627162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2334627162
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1881778698
Short name T184
Test name
Test status
Simulation time 298196351 ps
CPU time 4.39 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:22:15 PM PDT 24
Peak memory 211396 kb
Host smart-0acef481-77de-48ee-9899-63c596370981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881778698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1881778698
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.785709836
Short name T261
Test name
Test status
Simulation time 11414360911 ps
CPU time 116.32 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:24:08 PM PDT 24
Peak memory 236848 kb
Host smart-22f2c0d6-2e83-413c-9cbe-f47b0c3e22f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785709836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.785709836
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3870359789
Short name T10
Test name
Test status
Simulation time 1375372649 ps
CPU time 11.7 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:22:23 PM PDT 24
Peak memory 211988 kb
Host smart-426a245a-bf05-4a3a-936b-b8ef000ba9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870359789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3870359789
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.18135385
Short name T239
Test name
Test status
Simulation time 2463267857 ps
CPU time 8.96 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:25 PM PDT 24
Peak memory 211416 kb
Host smart-09e07bf0-6492-464d-b015-c5a327c1442d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18135385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.18135385
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3680665997
Short name T75
Test name
Test status
Simulation time 721636028 ps
CPU time 10.07 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 213092 kb
Host smart-0ea0b68a-63b1-4e5b-b9fc-4d94def18037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680665997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3680665997
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4282784437
Short name T252
Test name
Test status
Simulation time 13945119354 ps
CPU time 42.42 seconds
Started Jul 22 06:22:05 PM PDT 24
Finished Jul 22 06:22:48 PM PDT 24
Peak memory 214576 kb
Host smart-b5ea25f7-b486-481f-a913-593412e98a99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282784437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4282784437
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.365099587
Short name T365
Test name
Test status
Simulation time 7876151426 ps
CPU time 15.08 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:22:27 PM PDT 24
Peak memory 211412 kb
Host smart-00e34ff6-89d2-4e4f-88b2-7ded918d6b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365099587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.365099587
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2467823563
Short name T5
Test name
Test status
Simulation time 4781845618 ps
CPU time 141.43 seconds
Started Jul 22 06:22:06 PM PDT 24
Finished Jul 22 06:24:27 PM PDT 24
Peak memory 234072 kb
Host smart-7558d829-b4b3-4271-b93a-3109d351b3b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467823563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2467823563
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3933639591
Short name T28
Test name
Test status
Simulation time 263845525 ps
CPU time 10.85 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:22:22 PM PDT 24
Peak memory 211900 kb
Host smart-d9f66951-7030-48b4-aaf0-83e2746e61ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933639591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3933639591
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2831305220
Short name T130
Test name
Test status
Simulation time 570469287 ps
CPU time 8.73 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:22:21 PM PDT 24
Peak memory 211412 kb
Host smart-e2350569-95f8-4f19-9c8e-e52817a01ca8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831305220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2831305220
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1996784397
Short name T164
Test name
Test status
Simulation time 378039055 ps
CPU time 9.82 seconds
Started Jul 22 06:22:04 PM PDT 24
Finished Jul 22 06:22:14 PM PDT 24
Peak memory 213544 kb
Host smart-eb6fe25a-370c-4ff5-a48e-da7979e95b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996784397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1996784397
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.667872137
Short name T288
Test name
Test status
Simulation time 15383359606 ps
CPU time 45.88 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:23:00 PM PDT 24
Peak memory 216188 kb
Host smart-4f7999ab-772e-4e51-b6c5-f1abf0e5cabb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667872137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.667872137
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3062397712
Short name T205
Test name
Test status
Simulation time 172946454095 ps
CPU time 468.18 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:30:02 PM PDT 24
Peak memory 235076 kb
Host smart-47e16ac5-3900-48ac-93b5-8421849acc07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062397712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3062397712
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2202708112
Short name T194
Test name
Test status
Simulation time 3031578174 ps
CPU time 13.4 seconds
Started Jul 22 06:22:09 PM PDT 24
Finished Jul 22 06:22:23 PM PDT 24
Peak memory 212076 kb
Host smart-9a40a10f-99af-4635-b4bd-c8fd34b98434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202708112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2202708112
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4143457967
Short name T101
Test name
Test status
Simulation time 417408174 ps
CPU time 8.08 seconds
Started Jul 22 06:22:07 PM PDT 24
Finished Jul 22 06:22:16 PM PDT 24
Peak memory 211352 kb
Host smart-d470a517-2b2c-45ab-8356-7ca52538f82b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143457967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4143457967
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2154024398
Short name T124
Test name
Test status
Simulation time 17878813512 ps
CPU time 34.64 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:48 PM PDT 24
Peak memory 214024 kb
Host smart-8afb67e0-c4df-40a3-be1e-fb32b8a29e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154024398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2154024398
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3844131153
Short name T355
Test name
Test status
Simulation time 575143191 ps
CPU time 9.93 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:22:22 PM PDT 24
Peak memory 211288 kb
Host smart-fd172b49-5a03-4375-980e-24404b5004f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844131153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3844131153
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1318477801
Short name T358
Test name
Test status
Simulation time 437512032 ps
CPU time 4.38 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:22:17 PM PDT 24
Peak memory 211304 kb
Host smart-518a6ee7-262d-43ca-aa87-5110b5996464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318477801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1318477801
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.58439142
Short name T367
Test name
Test status
Simulation time 200715968127 ps
CPU time 401.57 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:28:55 PM PDT 24
Peak memory 234888 kb
Host smart-155de85b-1cd4-46d3-871f-a7cfb8094e11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58439142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_co
rrupt_sig_fatal_chk.58439142
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.209217451
Short name T328
Test name
Test status
Simulation time 1710760584 ps
CPU time 19.41 seconds
Started Jul 22 06:22:08 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 212152 kb
Host smart-9da00069-cc8b-48da-a828-57a09b3987aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209217451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.209217451
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2779308298
Short name T147
Test name
Test status
Simulation time 443602810 ps
CPU time 8.55 seconds
Started Jul 22 06:22:06 PM PDT 24
Finished Jul 22 06:22:15 PM PDT 24
Peak memory 211600 kb
Host smart-e54e648e-bd68-4684-8892-ef74f23b9fea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779308298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2779308298
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3537462573
Short name T229
Test name
Test status
Simulation time 11167340958 ps
CPU time 37.39 seconds
Started Jul 22 06:22:09 PM PDT 24
Finished Jul 22 06:22:46 PM PDT 24
Peak memory 212736 kb
Host smart-e7abda13-01c6-47ca-86bc-31292954fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537462573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3537462573
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1278331145
Short name T230
Test name
Test status
Simulation time 2951723972 ps
CPU time 16.12 seconds
Started Jul 22 06:22:07 PM PDT 24
Finished Jul 22 06:22:24 PM PDT 24
Peak memory 213356 kb
Host smart-9e7688c0-215f-4bed-8ab4-7fb719c17915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278331145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1278331145
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.288294012
Short name T177
Test name
Test status
Simulation time 862335432 ps
CPU time 9.25 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:22:21 PM PDT 24
Peak memory 211316 kb
Host smart-9f031e63-5bd5-4c91-8d28-e2c2b3084727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288294012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.288294012
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3656664411
Short name T306
Test name
Test status
Simulation time 189040091275 ps
CPU time 403.2 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:28:55 PM PDT 24
Peak memory 234916 kb
Host smart-6c73ff35-736b-49f0-b8e5-120c1f2d6095
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656664411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3656664411
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.674044379
Short name T129
Test name
Test status
Simulation time 40663769039 ps
CPU time 32.11 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:22:44 PM PDT 24
Peak memory 212220 kb
Host smart-80b72483-86a4-468f-80cf-8ccf7bbfd83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674044379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.674044379
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2099776640
Short name T215
Test name
Test status
Simulation time 1961529317 ps
CPU time 16.89 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:30 PM PDT 24
Peak memory 211416 kb
Host smart-ce5dbe9e-e175-4e97-93ed-fed8a70200cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099776640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2099776640
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2245316732
Short name T72
Test name
Test status
Simulation time 16970487445 ps
CPU time 39.83 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:22:52 PM PDT 24
Peak memory 213808 kb
Host smart-1ecb1de0-fba9-4dcc-a366-cf3021c210ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245316732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2245316732
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2306834754
Short name T206
Test name
Test status
Simulation time 28624399447 ps
CPU time 72.87 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:23:26 PM PDT 24
Peak memory 217116 kb
Host smart-5a60c518-7011-452d-81b8-0f9a1951a097
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306834754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2306834754
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1295239387
Short name T296
Test name
Test status
Simulation time 6390556949 ps
CPU time 14.86 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 211416 kb
Host smart-6b7b09a9-cd5c-46a3-a53d-de7c1c5f9bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295239387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1295239387
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2419513917
Short name T283
Test name
Test status
Simulation time 131142097788 ps
CPU time 271.53 seconds
Started Jul 22 06:22:09 PM PDT 24
Finished Jul 22 06:26:41 PM PDT 24
Peak memory 236516 kb
Host smart-e4768917-ca88-45cc-ac78-f016cc584062
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419513917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2419513917
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2614918376
Short name T1
Test name
Test status
Simulation time 378640760 ps
CPU time 9.2 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:23 PM PDT 24
Peak memory 211848 kb
Host smart-5060bd86-125f-4a0a-a96d-fd47003fa4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614918376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2614918376
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3215991666
Short name T162
Test name
Test status
Simulation time 1022282835 ps
CPU time 11.08 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:25 PM PDT 24
Peak memory 211400 kb
Host smart-ea2e93bc-a323-48b7-88f2-80e063906241
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215991666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3215991666
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1337513407
Short name T277
Test name
Test status
Simulation time 214898629 ps
CPU time 10.11 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:22:25 PM PDT 24
Peak memory 213544 kb
Host smart-ce43811d-2727-4a3f-9ce6-8a68021954a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337513407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1337513407
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1536972695
Short name T52
Test name
Test status
Simulation time 21784708985 ps
CPU time 63.5 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:23:19 PM PDT 24
Peak memory 219388 kb
Host smart-761ec1e8-58ca-4abd-93b5-bba6671a74b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536972695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1536972695
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2235436740
Short name T335
Test name
Test status
Simulation time 42512109442 ps
CPU time 1698.5 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:50:33 PM PDT 24
Peak memory 234908 kb
Host smart-3f59ca88-2320-491c-80d1-b6748d9862fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235436740 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2235436740
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1418539305
Short name T305
Test name
Test status
Simulation time 175190112 ps
CPU time 4.21 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:22 PM PDT 24
Peak memory 211328 kb
Host smart-f6b59d79-69db-46e6-a8c2-a54a24e119e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418539305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1418539305
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1536951980
Short name T34
Test name
Test status
Simulation time 54385281969 ps
CPU time 173.49 seconds
Started Jul 22 06:22:06 PM PDT 24
Finished Jul 22 06:25:00 PM PDT 24
Peak memory 212664 kb
Host smart-4459db9e-8df2-41d9-8ace-56756421fe48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536951980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1536951980
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.114874349
Short name T334
Test name
Test status
Simulation time 175918591 ps
CPU time 9.4 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:26 PM PDT 24
Peak memory 211936 kb
Host smart-554ac008-6914-49b8-85da-8a8e8cf584dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114874349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.114874349
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4085786072
Short name T167
Test name
Test status
Simulation time 1084631246 ps
CPU time 11.26 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:25 PM PDT 24
Peak memory 211368 kb
Host smart-e57abaee-e310-4b42-a0b2-59a40dc79f45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085786072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4085786072
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1870020433
Short name T312
Test name
Test status
Simulation time 3581221272 ps
CPU time 21.52 seconds
Started Jul 22 06:22:07 PM PDT 24
Finished Jul 22 06:22:29 PM PDT 24
Peak memory 213752 kb
Host smart-d9286258-57f3-46cc-b371-3231311e0743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870020433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1870020433
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1751582177
Short name T178
Test name
Test status
Simulation time 659352250 ps
CPU time 19.55 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:33 PM PDT 24
Peak memory 212644 kb
Host smart-6f82667e-c210-4044-acc3-cc86e9ae1f96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751582177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1751582177
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2201545330
Short name T200
Test name
Test status
Simulation time 1353239936 ps
CPU time 7.61 seconds
Started Jul 22 06:22:16 PM PDT 24
Finished Jul 22 06:22:26 PM PDT 24
Peak memory 211328 kb
Host smart-2ed5ce15-7b2b-4d2e-a8c2-d58e7feb9dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201545330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2201545330
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.757259201
Short name T195
Test name
Test status
Simulation time 25276232096 ps
CPU time 228.55 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:26:01 PM PDT 24
Peak memory 236860 kb
Host smart-eb70b32f-6d5e-4bf4-9750-62adb16ea081
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757259201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.757259201
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1926809364
Short name T20
Test name
Test status
Simulation time 14943937157 ps
CPU time 28.6 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:45 PM PDT 24
Peak memory 212240 kb
Host smart-839e8f90-2bbe-4da0-a7bd-cd7e4b7f8ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926809364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1926809364
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2716989800
Short name T212
Test name
Test status
Simulation time 8279119532 ps
CPU time 16.93 seconds
Started Jul 22 06:22:07 PM PDT 24
Finished Jul 22 06:22:25 PM PDT 24
Peak memory 211436 kb
Host smart-7024e7e7-9e64-4dcf-96c9-aae6b053fd14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716989800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2716989800
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.814515222
Short name T98
Test name
Test status
Simulation time 65559823609 ps
CPU time 32.35 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:48 PM PDT 24
Peak memory 213832 kb
Host smart-61710eb6-a24c-4021-822e-3214b57d8700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814515222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.814515222
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.357056334
Short name T284
Test name
Test status
Simulation time 14485018609 ps
CPU time 33.88 seconds
Started Jul 22 06:22:43 PM PDT 24
Finished Jul 22 06:23:18 PM PDT 24
Peak memory 216148 kb
Host smart-cce48991-d06c-4627-a04f-55f3ae1dd0f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357056334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.357056334
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4158856082
Short name T237
Test name
Test status
Simulation time 2500643908 ps
CPU time 11.15 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 211424 kb
Host smart-60c21a9c-2859-4a12-906d-0d0928bbec13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158856082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4158856082
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1702469362
Short name T275
Test name
Test status
Simulation time 8189700586 ps
CPU time 147.11 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:24:45 PM PDT 24
Peak memory 237552 kb
Host smart-4195c60c-b5b3-480e-bd9b-0120b4efc8c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702469362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1702469362
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2770419601
Short name T250
Test name
Test status
Simulation time 28929655644 ps
CPU time 24.77 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:43 PM PDT 24
Peak memory 212308 kb
Host smart-eeeb8303-9f93-4037-bc8e-9e19f27c0af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770419601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2770419601
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1294503718
Short name T216
Test name
Test status
Simulation time 96347410 ps
CPU time 5.49 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:22 PM PDT 24
Peak memory 211368 kb
Host smart-410e1865-36b3-4e10-ba57-ee4eb2641681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294503718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1294503718
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3013550795
Short name T160
Test name
Test status
Simulation time 6903759801 ps
CPU time 12.43 seconds
Started Jul 22 06:22:07 PM PDT 24
Finished Jul 22 06:22:20 PM PDT 24
Peak memory 214528 kb
Host smart-ee21dbc1-b9ad-487b-b2d0-4f20048bec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013550795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3013550795
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.689829724
Short name T240
Test name
Test status
Simulation time 8648242762 ps
CPU time 18.66 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:36 PM PDT 24
Peak memory 211308 kb
Host smart-4660f325-39bf-4f84-9ab3-f821d8b25056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689829724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.689829724
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3431646049
Short name T146
Test name
Test status
Simulation time 1439665692 ps
CPU time 7.81 seconds
Started Jul 22 06:21:55 PM PDT 24
Finished Jul 22 06:22:03 PM PDT 24
Peak memory 211368 kb
Host smart-625c5d9b-a664-4e95-9486-e863f9456b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431646049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3431646049
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3080174400
Short name T169
Test name
Test status
Simulation time 111621411404 ps
CPU time 283.17 seconds
Started Jul 22 06:22:09 PM PDT 24
Finished Jul 22 06:26:53 PM PDT 24
Peak memory 233244 kb
Host smart-d95d4006-fc93-4616-b91e-a99a2ebb48dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080174400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3080174400
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1106600388
Short name T318
Test name
Test status
Simulation time 1464557304 ps
CPU time 18.02 seconds
Started Jul 22 06:22:00 PM PDT 24
Finished Jul 22 06:22:18 PM PDT 24
Peak memory 212380 kb
Host smart-2b7bb566-75f0-4118-9c4f-8c7691ad04b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106600388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1106600388
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1713069797
Short name T301
Test name
Test status
Simulation time 1607605256 ps
CPU time 9.9 seconds
Started Jul 22 06:21:59 PM PDT 24
Finished Jul 22 06:22:09 PM PDT 24
Peak memory 211396 kb
Host smart-34e68d38-68ab-4776-a8b1-af5e48f5c391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713069797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1713069797
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.219733502
Short name T22
Test name
Test status
Simulation time 8938603728 ps
CPU time 61.64 seconds
Started Jul 22 06:21:58 PM PDT 24
Finished Jul 22 06:23:01 PM PDT 24
Peak memory 235972 kb
Host smart-7101bd64-a58f-4ffc-a727-35de38c9a770
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219733502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.219733502
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.674770960
Short name T338
Test name
Test status
Simulation time 645882777 ps
CPU time 10.4 seconds
Started Jul 22 06:21:55 PM PDT 24
Finished Jul 22 06:22:06 PM PDT 24
Peak memory 213344 kb
Host smart-ceff6990-6e8e-48f2-93bb-9bfc950720f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674770960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.674770960
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2416648096
Short name T188
Test name
Test status
Simulation time 9082047142 ps
CPU time 38.42 seconds
Started Jul 22 06:21:58 PM PDT 24
Finished Jul 22 06:22:37 PM PDT 24
Peak memory 217172 kb
Host smart-c0892d61-fca9-4852-b321-9e98008063a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416648096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2416648096
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.23088104
Short name T143
Test name
Test status
Simulation time 89012411 ps
CPU time 4.17 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 210988 kb
Host smart-e3e452f0-3a46-4703-b63e-e5482042ca3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23088104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.23088104
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3527011663
Short name T191
Test name
Test status
Simulation time 198756266969 ps
CPU time 245.62 seconds
Started Jul 22 06:22:16 PM PDT 24
Finished Jul 22 06:26:24 PM PDT 24
Peak memory 233800 kb
Host smart-eb1dd2f3-57e7-4d8b-8f5d-607c75088c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527011663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3527011663
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2161382584
Short name T289
Test name
Test status
Simulation time 1843602912 ps
CPU time 11.8 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:29 PM PDT 24
Peak memory 212072 kb
Host smart-46c1fc6d-ab3f-41ba-9131-504366701631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161382584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2161382584
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.645264539
Short name T149
Test name
Test status
Simulation time 1525825225 ps
CPU time 14.53 seconds
Started Jul 22 06:22:45 PM PDT 24
Finished Jul 22 06:23:00 PM PDT 24
Peak memory 211408 kb
Host smart-52e13df8-adf5-4244-b83f-1363b5eba0ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645264539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.645264539
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3950907881
Short name T214
Test name
Test status
Simulation time 26010858089 ps
CPU time 28.55 seconds
Started Jul 22 06:22:16 PM PDT 24
Finished Jul 22 06:22:47 PM PDT 24
Peak memory 214640 kb
Host smart-e0b18bbf-273d-45ba-bcd7-7adbea536c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950907881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3950907881
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2361282961
Short name T368
Test name
Test status
Simulation time 6249372991 ps
CPU time 35.11 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:53 PM PDT 24
Peak memory 215556 kb
Host smart-19153866-9d86-49cc-a850-a16319e597a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361282961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2361282961
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1443505264
Short name T291
Test name
Test status
Simulation time 1082071184 ps
CPU time 6 seconds
Started Jul 22 06:22:18 PM PDT 24
Finished Jul 22 06:22:25 PM PDT 24
Peak memory 211328 kb
Host smart-e00dae82-1b87-4730-9626-c2480f6797b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443505264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1443505264
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.682213799
Short name T260
Test name
Test status
Simulation time 3423838625 ps
CPU time 95.9 seconds
Started Jul 22 06:22:43 PM PDT 24
Finished Jul 22 06:24:20 PM PDT 24
Peak memory 212348 kb
Host smart-da658437-00cd-4ce4-b990-d3535922571d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682213799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.682213799
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.939561669
Short name T133
Test name
Test status
Simulation time 664015845 ps
CPU time 9.51 seconds
Started Jul 22 06:22:17 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 211940 kb
Host smart-de1a6c0f-acfe-4c65-bde1-5c7b6b5ba976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939561669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.939561669
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1550046687
Short name T120
Test name
Test status
Simulation time 99466835 ps
CPU time 5.9 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:22:21 PM PDT 24
Peak memory 211408 kb
Host smart-354df4bf-a39c-475c-a6c2-9ba63c0b2069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550046687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1550046687
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3102985417
Short name T132
Test name
Test status
Simulation time 3586965115 ps
CPU time 10.08 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:26 PM PDT 24
Peak memory 213752 kb
Host smart-cdc3c2c5-1393-475c-8558-c0733bb21984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102985417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3102985417
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.651070915
Short name T173
Test name
Test status
Simulation time 898409372 ps
CPU time 15.78 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:22:30 PM PDT 24
Peak memory 213948 kb
Host smart-43759b79-98a4-4601-b483-9c02ba56f3d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651070915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.651070915
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2399545772
Short name T257
Test name
Test status
Simulation time 52769112002 ps
CPU time 2239.08 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:59:35 PM PDT 24
Peak memory 244052 kb
Host smart-625d62cf-20b5-43f7-9353-35a9b7fbe8c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399545772 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2399545772
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.761808517
Short name T187
Test name
Test status
Simulation time 1770433179 ps
CPU time 14.74 seconds
Started Jul 22 06:22:18 PM PDT 24
Finished Jul 22 06:22:34 PM PDT 24
Peak memory 211348 kb
Host smart-71c1e9bd-2000-4e01-93b4-b2be17127004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761808517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.761808517
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3588504727
Short name T290
Test name
Test status
Simulation time 25165635092 ps
CPU time 268.82 seconds
Started Jul 22 06:23:28 PM PDT 24
Finished Jul 22 06:27:58 PM PDT 24
Peak memory 236860 kb
Host smart-e12738e1-fb65-4c77-b2ca-79d9732223d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588504727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3588504727
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4248529765
Short name T39
Test name
Test status
Simulation time 168436009 ps
CPU time 9.3 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:33 PM PDT 24
Peak memory 212012 kb
Host smart-b653e027-4e87-4516-8bb4-14e5004a5193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248529765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4248529765
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.971497065
Short name T161
Test name
Test status
Simulation time 2886516344 ps
CPU time 11.62 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:27 PM PDT 24
Peak memory 211432 kb
Host smart-21e6d72b-b698-493d-b82d-1a88ae74c23d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971497065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.971497065
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2281044154
Short name T340
Test name
Test status
Simulation time 788818286 ps
CPU time 9.92 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:22:24 PM PDT 24
Peak memory 213860 kb
Host smart-afb64d44-28ba-4823-8a1e-1de0280fac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281044154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2281044154
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1435022309
Short name T151
Test name
Test status
Simulation time 1225526105 ps
CPU time 20.08 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:37 PM PDT 24
Peak memory 212456 kb
Host smart-713b4776-d349-4e8b-ac92-37a80c3b794c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435022309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1435022309
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1706073037
Short name T45
Test name
Test status
Simulation time 368482211197 ps
CPU time 3635.86 seconds
Started Jul 22 06:22:23 PM PDT 24
Finished Jul 22 07:23:01 PM PDT 24
Peak memory 252264 kb
Host smart-d22a5abb-1d8c-4dbf-b61c-ee95da60decc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706073037 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1706073037
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2406398426
Short name T316
Test name
Test status
Simulation time 2418610278 ps
CPU time 7.59 seconds
Started Jul 22 06:22:17 PM PDT 24
Finished Jul 22 06:22:26 PM PDT 24
Peak memory 211392 kb
Host smart-13db797b-6f9b-4694-b818-3cb0d4001cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406398426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2406398426
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1986031075
Short name T43
Test name
Test status
Simulation time 1283114037 ps
CPU time 89.51 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:23:44 PM PDT 24
Peak memory 228480 kb
Host smart-599f51d1-f9d0-4add-9f76-cb510fef6036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986031075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1986031075
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3825759839
Short name T208
Test name
Test status
Simulation time 6228315901 ps
CPU time 27.15 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:44 PM PDT 24
Peak memory 212524 kb
Host smart-e506a436-5778-4030-9bfc-65ec688eb2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825759839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3825759839
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1819932876
Short name T342
Test name
Test status
Simulation time 1262081256 ps
CPU time 9.35 seconds
Started Jul 22 06:24:39 PM PDT 24
Finished Jul 22 06:24:49 PM PDT 24
Peak memory 211308 kb
Host smart-2ed8636b-6085-4754-a7e2-e0fb60705684
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819932876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1819932876
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1750439412
Short name T363
Test name
Test status
Simulation time 11011135759 ps
CPU time 27.96 seconds
Started Jul 22 06:22:18 PM PDT 24
Finished Jul 22 06:22:47 PM PDT 24
Peak memory 214636 kb
Host smart-106b81ee-a953-4494-9bac-39af3a1b5565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750439412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1750439412
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3013893812
Short name T24
Test name
Test status
Simulation time 26174919188 ps
CPU time 67.99 seconds
Started Jul 22 06:22:16 PM PDT 24
Finished Jul 22 06:23:26 PM PDT 24
Peak memory 217924 kb
Host smart-d312d06d-0ee6-4bba-b477-7ba2bc088b7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013893812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3013893812
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3287640429
Short name T299
Test name
Test status
Simulation time 16960088960 ps
CPU time 12.59 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:22:27 PM PDT 24
Peak memory 211428 kb
Host smart-a9d53d90-44c0-4457-a9bf-9658e6ab7394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287640429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3287640429
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.799094823
Short name T23
Test name
Test status
Simulation time 3568515611 ps
CPU time 29.66 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:45 PM PDT 24
Peak memory 211964 kb
Host smart-85bac6ed-3a69-479b-b055-f029c26cb755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799094823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.799094823
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2906998124
Short name T121
Test name
Test status
Simulation time 13889085388 ps
CPU time 15.37 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:22:30 PM PDT 24
Peak memory 211464 kb
Host smart-f8814b55-71fe-481d-a55c-f824e3811c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906998124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2906998124
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4095720496
Short name T197
Test name
Test status
Simulation time 192381538 ps
CPU time 10.53 seconds
Started Jul 22 06:22:17 PM PDT 24
Finished Jul 22 06:22:29 PM PDT 24
Peak memory 214096 kb
Host smart-3850600f-eeef-4ef2-a411-62e9840219e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095720496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4095720496
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3849024018
Short name T76
Test name
Test status
Simulation time 3922861859 ps
CPU time 31.64 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:48 PM PDT 24
Peak memory 216804 kb
Host smart-521d6bc3-28bb-4d0b-8fbd-c247755976dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849024018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3849024018
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2473788606
Short name T332
Test name
Test status
Simulation time 1810465322 ps
CPU time 7.32 seconds
Started Jul 22 06:22:23 PM PDT 24
Finished Jul 22 06:22:31 PM PDT 24
Peak memory 211316 kb
Host smart-9342a15e-2d9d-42af-8b68-8b08261c936d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473788606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2473788606
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3837955542
Short name T228
Test name
Test status
Simulation time 79410369340 ps
CPU time 258.11 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:26:36 PM PDT 24
Peak memory 212844 kb
Host smart-966313c8-db95-46aa-91dc-6ed288a684d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837955542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3837955542
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1576711777
Short name T179
Test name
Test status
Simulation time 172138597 ps
CPU time 9.36 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:25 PM PDT 24
Peak memory 211904 kb
Host smart-d24e2000-cb03-4c71-9c86-5585d9e5bfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576711777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1576711777
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.343869660
Short name T128
Test name
Test status
Simulation time 397311547 ps
CPU time 5.54 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:23 PM PDT 24
Peak memory 211300 kb
Host smart-2d7280c7-c086-4d99-81ff-867664ff41ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343869660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.343869660
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1184207753
Short name T220
Test name
Test status
Simulation time 31730633151 ps
CPU time 21.75 seconds
Started Jul 22 06:22:17 PM PDT 24
Finished Jul 22 06:22:41 PM PDT 24
Peak memory 213928 kb
Host smart-ebdce171-2555-4776-8659-164fe8d89edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184207753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1184207753
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2066977756
Short name T198
Test name
Test status
Simulation time 44938600453 ps
CPU time 65.9 seconds
Started Jul 22 06:22:16 PM PDT 24
Finished Jul 22 06:23:24 PM PDT 24
Peak memory 217612 kb
Host smart-fec5ae5d-3264-4a59-95f6-523e4aede3df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066977756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2066977756
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2680289264
Short name T47
Test name
Test status
Simulation time 20878470070 ps
CPU time 6794.01 seconds
Started Jul 22 06:22:28 PM PDT 24
Finished Jul 22 08:15:44 PM PDT 24
Peak memory 235856 kb
Host smart-aa7ebd3f-ec46-4572-bc6e-507c7632f5dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680289264 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2680289264
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.94121297
Short name T254
Test name
Test status
Simulation time 346409393 ps
CPU time 4.27 seconds
Started Jul 22 06:22:28 PM PDT 24
Finished Jul 22 06:22:34 PM PDT 24
Peak memory 211344 kb
Host smart-1615a2a8-11c3-45aa-8d0d-299f085aecdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94121297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.94121297
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4210003624
Short name T35
Test name
Test status
Simulation time 14656236791 ps
CPU time 232.32 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:26:09 PM PDT 24
Peak memory 234920 kb
Host smart-4e949af6-ae46-4844-aec8-d8f5035ef4a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210003624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4210003624
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3552638774
Short name T327
Test name
Test status
Simulation time 16370708986 ps
CPU time 23.87 seconds
Started Jul 22 06:22:23 PM PDT 24
Finished Jul 22 06:22:49 PM PDT 24
Peak memory 212028 kb
Host smart-08aee66e-d042-4eaa-8620-86fb6c3121e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552638774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3552638774
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2339370427
Short name T172
Test name
Test status
Simulation time 952725638 ps
CPU time 10.62 seconds
Started Jul 22 06:22:16 PM PDT 24
Finished Jul 22 06:22:29 PM PDT 24
Peak memory 211400 kb
Host smart-b6ee5d5b-0f9e-47c9-a6a4-8598333d8691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2339370427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2339370427
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3009677119
Short name T8
Test name
Test status
Simulation time 2403411612 ps
CPU time 25.96 seconds
Started Jul 22 06:22:16 PM PDT 24
Finished Jul 22 06:22:44 PM PDT 24
Peak memory 213544 kb
Host smart-cca3d864-f74b-42e8-9ce5-2bad9ff70f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009677119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3009677119
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1182052096
Short name T210
Test name
Test status
Simulation time 5799049915 ps
CPU time 18.48 seconds
Started Jul 22 06:22:16 PM PDT 24
Finished Jul 22 06:22:37 PM PDT 24
Peak memory 213656 kb
Host smart-1cd812a3-20ee-4288-8e2c-217239f97b02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182052096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1182052096
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3917715317
Short name T61
Test name
Test status
Simulation time 1783969135 ps
CPU time 14.85 seconds
Started Jul 22 06:22:23 PM PDT 24
Finished Jul 22 06:22:40 PM PDT 24
Peak memory 210912 kb
Host smart-b5b9b733-82d6-4bfd-b7e4-2168a5fb2691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917715317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3917715317
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4061155710
Short name T309
Test name
Test status
Simulation time 140812923772 ps
CPU time 300.99 seconds
Started Jul 22 06:22:23 PM PDT 24
Finished Jul 22 06:27:26 PM PDT 24
Peak memory 212624 kb
Host smart-700c7e8f-e73c-458f-aab5-6d0cfe00cffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061155710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4061155710
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2784856844
Short name T258
Test name
Test status
Simulation time 23387307358 ps
CPU time 20.69 seconds
Started Jul 22 06:22:23 PM PDT 24
Finished Jul 22 06:22:45 PM PDT 24
Peak memory 212236 kb
Host smart-75f5f286-2dfa-4b1f-8b96-d137ccbeeeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784856844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2784856844
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.777473434
Short name T317
Test name
Test status
Simulation time 1649380727 ps
CPU time 10.01 seconds
Started Jul 22 06:22:28 PM PDT 24
Finished Jul 22 06:22:40 PM PDT 24
Peak memory 211388 kb
Host smart-76df5dea-ae4c-4d2f-86a5-8cbedb146e30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777473434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.777473434
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1268440441
Short name T4
Test name
Test status
Simulation time 189034663 ps
CPU time 10.31 seconds
Started Jul 22 06:22:18 PM PDT 24
Finished Jul 22 06:22:29 PM PDT 24
Peak memory 212424 kb
Host smart-fd375a94-91b9-46f8-a30f-0ccf947dc022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268440441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1268440441
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2250609401
Short name T321
Test name
Test status
Simulation time 1073883418 ps
CPU time 13.11 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 211424 kb
Host smart-10441089-35ee-4d97-a740-fd62dbdc3cb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250609401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2250609401
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2091064061
Short name T345
Test name
Test status
Simulation time 4350298438 ps
CPU time 17.13 seconds
Started Jul 22 06:22:17 PM PDT 24
Finished Jul 22 06:22:36 PM PDT 24
Peak memory 211428 kb
Host smart-a72537ed-57c6-456f-ab49-7b0e1f104e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091064061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2091064061
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1588489341
Short name T298
Test name
Test status
Simulation time 49904162472 ps
CPU time 217.23 seconds
Started Jul 22 06:22:23 PM PDT 24
Finished Jul 22 06:26:01 PM PDT 24
Peak memory 212696 kb
Host smart-62a317d9-4df1-4332-84c4-39456a7d76fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588489341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1588489341
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.725813258
Short name T189
Test name
Test status
Simulation time 4327930719 ps
CPU time 32.98 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:22:49 PM PDT 24
Peak memory 212404 kb
Host smart-17f20ce0-e962-4aed-aee0-4cbd2ac70474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725813258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.725813258
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3005758281
Short name T168
Test name
Test status
Simulation time 10593466796 ps
CPU time 15.09 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:33 PM PDT 24
Peak memory 211360 kb
Host smart-621092ec-6251-44da-bede-f85ddf1eff3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3005758281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3005758281
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.698524007
Short name T235
Test name
Test status
Simulation time 8221964225 ps
CPU time 22.63 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:22:38 PM PDT 24
Peak memory 213428 kb
Host smart-9881f7ea-986e-4d49-bcb3-493410a3d7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698524007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.698524007
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3545242022
Short name T26
Test name
Test status
Simulation time 1715925345 ps
CPU time 28.86 seconds
Started Jul 22 06:22:17 PM PDT 24
Finished Jul 22 06:22:48 PM PDT 24
Peak memory 215432 kb
Host smart-187c38bb-8385-4c7f-b54b-f4570bdb0b13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545242022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3545242022
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1940501588
Short name T337
Test name
Test status
Simulation time 570624478 ps
CPU time 6.25 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:29 PM PDT 24
Peak memory 211336 kb
Host smart-43015ea9-1ac6-4486-89e8-2db4cd8166a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940501588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1940501588
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3361670135
Short name T33
Test name
Test status
Simulation time 6281892137 ps
CPU time 147.91 seconds
Started Jul 22 06:22:27 PM PDT 24
Finished Jul 22 06:24:57 PM PDT 24
Peak memory 236464 kb
Host smart-9c475b4c-e5e1-42f4-afb8-13a62784d350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361670135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3361670135
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2536194981
Short name T202
Test name
Test status
Simulation time 8378016719 ps
CPU time 32.34 seconds
Started Jul 22 06:22:26 PM PDT 24
Finished Jul 22 06:23:00 PM PDT 24
Peak memory 212360 kb
Host smart-a8400e7b-fd32-4fc3-9ee7-a4e19ea458b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536194981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2536194981
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1240332041
Short name T232
Test name
Test status
Simulation time 1651519113 ps
CPU time 15.03 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:38 PM PDT 24
Peak memory 211088 kb
Host smart-08dbfe8b-3440-4b6f-9a21-448a6be7bc8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240332041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1240332041
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3529847802
Short name T222
Test name
Test status
Simulation time 748484221 ps
CPU time 10.01 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:32 PM PDT 24
Peak memory 214164 kb
Host smart-a020379c-5903-419f-b79f-81cf2ea9c644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529847802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3529847802
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.389078706
Short name T359
Test name
Test status
Simulation time 12550411994 ps
CPU time 41.9 seconds
Started Jul 22 06:22:18 PM PDT 24
Finished Jul 22 06:23:01 PM PDT 24
Peak memory 216540 kb
Host smart-26c9fca9-f1d0-45ab-afb1-a5482cdf0316
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389078706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.389078706
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1243256767
Short name T287
Test name
Test status
Simulation time 3384989515 ps
CPU time 14.82 seconds
Started Jul 22 06:22:01 PM PDT 24
Finished Jul 22 06:22:16 PM PDT 24
Peak memory 211432 kb
Host smart-a7e196d3-46c3-4d87-8aeb-bc28688d5a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243256767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1243256767
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1071821637
Short name T37
Test name
Test status
Simulation time 16450567372 ps
CPU time 183.33 seconds
Started Jul 22 06:22:01 PM PDT 24
Finished Jul 22 06:25:05 PM PDT 24
Peak memory 237856 kb
Host smart-58d6943e-8e14-4fd1-ade9-e1b8df45aa52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071821637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1071821637
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.721055276
Short name T186
Test name
Test status
Simulation time 2206497268 ps
CPU time 22.51 seconds
Started Jul 22 06:22:29 PM PDT 24
Finished Jul 22 06:22:52 PM PDT 24
Peak memory 211436 kb
Host smart-45503fa7-aa15-4995-83dc-c9e7de351d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721055276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.721055276
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4165218185
Short name T116
Test name
Test status
Simulation time 1028858662 ps
CPU time 11.15 seconds
Started Jul 22 06:22:04 PM PDT 24
Finished Jul 22 06:22:15 PM PDT 24
Peak memory 211376 kb
Host smart-683adec8-8518-4fe8-adb2-5f04b7b3a0ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165218185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4165218185
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4159540568
Short name T203
Test name
Test status
Simulation time 28865855733 ps
CPU time 30.88 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:58 PM PDT 24
Peak memory 214340 kb
Host smart-a4d2510f-7e44-4d6e-ac39-d5662fe153ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159540568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4159540568
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1439726406
Short name T150
Test name
Test status
Simulation time 2358920220 ps
CPU time 40.99 seconds
Started Jul 22 06:22:25 PM PDT 24
Finished Jul 22 06:23:08 PM PDT 24
Peak memory 219380 kb
Host smart-c2483911-3c4c-4219-9af0-90c9fd1a54f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439726406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1439726406
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2689039645
Short name T213
Test name
Test status
Simulation time 1779828357 ps
CPU time 13.88 seconds
Started Jul 22 06:22:25 PM PDT 24
Finished Jul 22 06:22:42 PM PDT 24
Peak memory 211324 kb
Host smart-fd279bbd-a5a9-48d2-b8cf-bfa48f628b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689039645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2689039645
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1388846590
Short name T265
Test name
Test status
Simulation time 25113623956 ps
CPU time 244.97 seconds
Started Jul 22 06:24:39 PM PDT 24
Finished Jul 22 06:28:45 PM PDT 24
Peak memory 237660 kb
Host smart-57537354-aac8-48b5-a575-a001c0b7dbb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388846590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1388846590
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.387324962
Short name T137
Test name
Test status
Simulation time 4089351903 ps
CPU time 21.71 seconds
Started Jul 22 06:22:21 PM PDT 24
Finished Jul 22 06:22:44 PM PDT 24
Peak memory 211444 kb
Host smart-ca107925-f662-44c7-9541-6371ebd72528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387324962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.387324962
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1737570888
Short name T207
Test name
Test status
Simulation time 4576524986 ps
CPU time 14.3 seconds
Started Jul 22 06:24:39 PM PDT 24
Finished Jul 22 06:24:54 PM PDT 24
Peak memory 211196 kb
Host smart-7ed2d61b-cff5-4e74-9b06-fd128514d7d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737570888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1737570888
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1607267340
Short name T364
Test name
Test status
Simulation time 36034112148 ps
CPU time 25.91 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:50 PM PDT 24
Peak memory 212800 kb
Host smart-d5dec7c3-7f58-4994-a563-b97f2b92210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607267340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1607267340
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1681326931
Short name T117
Test name
Test status
Simulation time 425130486 ps
CPU time 22.34 seconds
Started Jul 22 06:22:27 PM PDT 24
Finished Jul 22 06:22:51 PM PDT 24
Peak memory 215256 kb
Host smart-44faceb9-cd0e-4271-950f-e861179bc5eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681326931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1681326931
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2317435095
Short name T351
Test name
Test status
Simulation time 2725702385 ps
CPU time 8.15 seconds
Started Jul 22 06:22:17 PM PDT 24
Finished Jul 22 06:22:27 PM PDT 24
Peak memory 211384 kb
Host smart-209367a4-bd5d-4b5c-b1ac-480d1a15095f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317435095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2317435095
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1937161371
Short name T211
Test name
Test status
Simulation time 42476178880 ps
CPU time 128.66 seconds
Started Jul 22 06:22:26 PM PDT 24
Finished Jul 22 06:24:37 PM PDT 24
Peak memory 236772 kb
Host smart-cc5235c6-5f64-4e94-8e4d-f475de4bbaeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937161371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1937161371
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3653950832
Short name T192
Test name
Test status
Simulation time 779275819 ps
CPU time 14.67 seconds
Started Jul 22 06:23:05 PM PDT 24
Finished Jul 22 06:23:20 PM PDT 24
Peak memory 211628 kb
Host smart-1d72bb0b-28a8-484a-b9e9-012bd74c679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653950832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3653950832
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.427749615
Short name T25
Test name
Test status
Simulation time 3841485356 ps
CPU time 15.51 seconds
Started Jul 22 06:22:25 PM PDT 24
Finished Jul 22 06:22:43 PM PDT 24
Peak memory 211428 kb
Host smart-079d01f8-7aa5-4970-80e1-1bf12797dec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=427749615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.427749615
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1755736063
Short name T269
Test name
Test status
Simulation time 526665821 ps
CPU time 13.17 seconds
Started Jul 22 06:22:17 PM PDT 24
Finished Jul 22 06:22:32 PM PDT 24
Peak memory 211932 kb
Host smart-77b23427-eda9-455c-8e21-c24a4769bc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755736063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1755736063
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.130265451
Short name T181
Test name
Test status
Simulation time 4031351562 ps
CPU time 25.98 seconds
Started Jul 22 06:22:28 PM PDT 24
Finished Jul 22 06:22:56 PM PDT 24
Peak memory 213268 kb
Host smart-d9ebb1be-bda5-41c8-8af2-7b3993bce65f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130265451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.130265451
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.11130048
Short name T241
Test name
Test status
Simulation time 14740350095 ps
CPU time 14.59 seconds
Started Jul 22 06:22:27 PM PDT 24
Finished Jul 22 06:22:44 PM PDT 24
Peak memory 211364 kb
Host smart-28c679e4-adda-4d92-8b7f-e8f555da6dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11130048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.11130048
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.600431033
Short name T249
Test name
Test status
Simulation time 14823496311 ps
CPU time 183.03 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:25:20 PM PDT 24
Peak memory 236828 kb
Host smart-68ab56d3-2ebe-4c85-8319-4925540d27fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600431033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.600431033
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3188700744
Short name T152
Test name
Test status
Simulation time 3718704000 ps
CPU time 29.49 seconds
Started Jul 22 06:23:31 PM PDT 24
Finished Jul 22 06:24:01 PM PDT 24
Peak memory 211884 kb
Host smart-7400d2c9-b117-41a5-ab7a-246f3fbd2032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188700744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3188700744
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1573662116
Short name T221
Test name
Test status
Simulation time 982381208 ps
CPU time 8.15 seconds
Started Jul 22 06:22:16 PM PDT 24
Finished Jul 22 06:22:26 PM PDT 24
Peak memory 211556 kb
Host smart-e78f1336-aec3-4ba0-b1d4-acf8957d2029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573662116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1573662116
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1605310072
Short name T144
Test name
Test status
Simulation time 1811588452 ps
CPU time 23.73 seconds
Started Jul 22 06:22:15 PM PDT 24
Finished Jul 22 06:22:42 PM PDT 24
Peak memory 213704 kb
Host smart-4ced6ec7-bff1-4bb0-9ca4-98c59b5fd240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605310072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1605310072
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.15314493
Short name T190
Test name
Test status
Simulation time 734668223 ps
CPU time 9.13 seconds
Started Jul 22 06:22:26 PM PDT 24
Finished Jul 22 06:22:38 PM PDT 24
Peak memory 211408 kb
Host smart-e429f703-3029-4349-b2ac-32f1151aefd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15314493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 32.rom_ctrl_stress_all.15314493
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1735068653
Short name T59
Test name
Test status
Simulation time 1562333351 ps
CPU time 8.87 seconds
Started Jul 22 06:22:35 PM PDT 24
Finished Jul 22 06:22:44 PM PDT 24
Peak memory 211292 kb
Host smart-86cff5ac-884d-48a7-a986-f64b2337c60d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735068653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1735068653
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3706184966
Short name T217
Test name
Test status
Simulation time 24858941454 ps
CPU time 236.3 seconds
Started Jul 22 06:22:23 PM PDT 24
Finished Jul 22 06:26:21 PM PDT 24
Peak memory 237828 kb
Host smart-3ea09d7d-edda-4329-9c4f-c1bed4b286c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706184966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3706184966
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1667934475
Short name T268
Test name
Test status
Simulation time 3178189028 ps
CPU time 27.17 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:53 PM PDT 24
Peak memory 212100 kb
Host smart-f62245f6-36cb-4b09-9b36-aa145edaf317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667934475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1667934475
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1610913735
Short name T170
Test name
Test status
Simulation time 185414811 ps
CPU time 5.63 seconds
Started Jul 22 06:22:25 PM PDT 24
Finished Jul 22 06:22:33 PM PDT 24
Peak memory 211412 kb
Host smart-91106576-2c41-428d-8067-f84e99f6243c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610913735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1610913735
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3738909709
Short name T156
Test name
Test status
Simulation time 8296889191 ps
CPU time 18.85 seconds
Started Jul 22 06:22:27 PM PDT 24
Finished Jul 22 06:22:48 PM PDT 24
Peak memory 213460 kb
Host smart-3b736037-d743-47ec-8966-13618bbe8cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738909709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3738909709
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3132546067
Short name T234
Test name
Test status
Simulation time 10320598204 ps
CPU time 91.56 seconds
Started Jul 22 06:24:13 PM PDT 24
Finished Jul 22 06:25:45 PM PDT 24
Peak memory 219424 kb
Host smart-eae94372-668d-4879-b12f-f6e38fcc1e91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132546067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3132546067
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1747748985
Short name T341
Test name
Test status
Simulation time 1930921638 ps
CPU time 15.63 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:39 PM PDT 24
Peak memory 211352 kb
Host smart-ccd11673-7c18-4d5b-a420-8c3cb51892a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747748985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1747748985
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3753967795
Short name T115
Test name
Test status
Simulation time 16584628294 ps
CPU time 152.06 seconds
Started Jul 22 06:22:26 PM PDT 24
Finished Jul 22 06:25:01 PM PDT 24
Peak memory 233752 kb
Host smart-310802ee-4e1c-483f-a223-e3fe5c41ac74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753967795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3753967795
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.201871878
Short name T264
Test name
Test status
Simulation time 5084456122 ps
CPU time 25.52 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:51 PM PDT 24
Peak memory 212188 kb
Host smart-5d5d5877-7679-484f-b0f7-d3c4093795cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201871878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.201871878
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4215015040
Short name T135
Test name
Test status
Simulation time 6202463541 ps
CPU time 14.78 seconds
Started Jul 22 06:22:34 PM PDT 24
Finished Jul 22 06:22:49 PM PDT 24
Peak memory 211396 kb
Host smart-050b3009-cf78-406c-b647-3178a1e8774d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215015040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4215015040
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4152205145
Short name T2
Test name
Test status
Simulation time 3150151666 ps
CPU time 30.4 seconds
Started Jul 22 06:22:25 PM PDT 24
Finished Jul 22 06:22:58 PM PDT 24
Peak memory 213572 kb
Host smart-decd7dd7-4e75-45cf-8775-66e8b0bfd8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152205145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4152205145
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2514776887
Short name T256
Test name
Test status
Simulation time 946499515 ps
CPU time 10.69 seconds
Started Jul 22 06:22:21 PM PDT 24
Finished Jul 22 06:22:33 PM PDT 24
Peak memory 211416 kb
Host smart-39daef2d-6341-4a71-b204-b3ebc60ecb1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514776887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2514776887
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1701674295
Short name T274
Test name
Test status
Simulation time 1184477608 ps
CPU time 10.43 seconds
Started Jul 22 06:22:26 PM PDT 24
Finished Jul 22 06:22:39 PM PDT 24
Peak memory 211324 kb
Host smart-85f726c1-646b-4472-a4f9-699ee9c8f8f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701674295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1701674295
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2018554897
Short name T32
Test name
Test status
Simulation time 107217622291 ps
CPU time 340.81 seconds
Started Jul 22 06:22:27 PM PDT 24
Finished Jul 22 06:28:10 PM PDT 24
Peak memory 236940 kb
Host smart-e029c9e7-49ca-464e-8d26-1ec352f364bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018554897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2018554897
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3840226379
Short name T262
Test name
Test status
Simulation time 7462002428 ps
CPU time 30.93 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 212536 kb
Host smart-58224037-703f-443d-822e-cacb281ff433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840226379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3840226379
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.674663466
Short name T267
Test name
Test status
Simulation time 383033641 ps
CPU time 5.76 seconds
Started Jul 22 06:22:27 PM PDT 24
Finished Jul 22 06:22:35 PM PDT 24
Peak memory 211412 kb
Host smart-178ba005-bcc9-45b7-8c4f-efec8d54667c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674663466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.674663466
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2595903257
Short name T293
Test name
Test status
Simulation time 3139452990 ps
CPU time 28 seconds
Started Jul 22 06:22:27 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 213484 kb
Host smart-056bacb0-8918-48eb-b012-c86ed817407b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595903257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2595903257
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2284339409
Short name T159
Test name
Test status
Simulation time 52644708073 ps
CPU time 69.55 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:23:36 PM PDT 24
Peak memory 217924 kb
Host smart-3b711fe0-c802-4494-813a-caa05bfc1069
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284339409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2284339409
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2930568943
Short name T322
Test name
Test status
Simulation time 2545024485 ps
CPU time 14 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:40 PM PDT 24
Peak memory 211424 kb
Host smart-016e3ffc-891f-428a-b610-95204db3bcde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930568943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2930568943
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.999808137
Short name T294
Test name
Test status
Simulation time 11997119865 ps
CPU time 138.71 seconds
Started Jul 22 06:22:20 PM PDT 24
Finished Jul 22 06:24:39 PM PDT 24
Peak memory 228632 kb
Host smart-84b2adc5-e600-4018-b45e-e6dbdf0524d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999808137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.999808137
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2523052237
Short name T323
Test name
Test status
Simulation time 1951857040 ps
CPU time 21.06 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:47 PM PDT 24
Peak memory 211940 kb
Host smart-1c3f3b7a-f359-4734-8541-b8417ebbe5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523052237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2523052237
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1088418232
Short name T138
Test name
Test status
Simulation time 2071498108 ps
CPU time 8.66 seconds
Started Jul 22 06:22:25 PM PDT 24
Finished Jul 22 06:22:36 PM PDT 24
Peak memory 211400 kb
Host smart-11ce4f55-4869-4eeb-8af0-141cfb57732f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088418232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1088418232
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1421101712
Short name T273
Test name
Test status
Simulation time 2738200946 ps
CPU time 25.23 seconds
Started Jul 22 06:23:28 PM PDT 24
Finished Jul 22 06:23:54 PM PDT 24
Peak memory 213508 kb
Host smart-3b77e56a-f44f-429e-babe-03e65ccd0771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421101712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1421101712
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.234247414
Short name T346
Test name
Test status
Simulation time 549433485 ps
CPU time 17.6 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:43 PM PDT 24
Peak memory 212504 kb
Host smart-418b0a7d-fe33-4fa2-9a28-073b3bf45e73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234247414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.234247414
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.680498887
Short name T62
Test name
Test status
Simulation time 175193415 ps
CPU time 4.24 seconds
Started Jul 22 06:22:27 PM PDT 24
Finished Jul 22 06:22:33 PM PDT 24
Peak memory 211332 kb
Host smart-bc438970-51b0-4bb3-b1dc-ef0e372883b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680498887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.680498887
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3946137312
Short name T314
Test name
Test status
Simulation time 159956029584 ps
CPU time 221.63 seconds
Started Jul 22 06:23:31 PM PDT 24
Finished Jul 22 06:27:13 PM PDT 24
Peak memory 225724 kb
Host smart-5803655e-4080-457d-9e66-180a7f9290f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946137312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3946137312
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.57378519
Short name T238
Test name
Test status
Simulation time 342894780 ps
CPU time 11.72 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:37 PM PDT 24
Peak memory 212040 kb
Host smart-749516f0-0a0f-4069-be92-72c59afd8a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57378519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.57378519
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3494914728
Short name T209
Test name
Test status
Simulation time 1601515808 ps
CPU time 14.4 seconds
Started Jul 22 06:22:25 PM PDT 24
Finished Jul 22 06:22:42 PM PDT 24
Peak memory 211384 kb
Host smart-67014815-c229-4023-a022-977abf33a609
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494914728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3494914728
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1845088373
Short name T145
Test name
Test status
Simulation time 280415178 ps
CPU time 11.44 seconds
Started Jul 22 06:22:57 PM PDT 24
Finished Jul 22 06:23:10 PM PDT 24
Peak memory 213428 kb
Host smart-dac7176e-8cf9-4ff7-a405-4775e11b88f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845088373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1845088373
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3962073964
Short name T333
Test name
Test status
Simulation time 15937700948 ps
CPU time 122.22 seconds
Started Jul 22 06:22:33 PM PDT 24
Finished Jul 22 06:24:36 PM PDT 24
Peak memory 219352 kb
Host smart-0f694a84-27be-49c4-bb76-c2868551ae5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962073964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3962073964
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2803324583
Short name T49
Test name
Test status
Simulation time 193076845886 ps
CPU time 7583.04 seconds
Started Jul 22 06:22:28 PM PDT 24
Finished Jul 22 08:28:53 PM PDT 24
Peak memory 235860 kb
Host smart-65b740fe-ff58-46ba-a9f9-cec2daf7f344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803324583 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2803324583
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3690785434
Short name T219
Test name
Test status
Simulation time 3176781272 ps
CPU time 8.78 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:31 PM PDT 24
Peak memory 211392 kb
Host smart-5c25b20c-d255-4627-87d9-cbca9c8643e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690785434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3690785434
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2212045510
Short name T42
Test name
Test status
Simulation time 51430058390 ps
CPU time 461.52 seconds
Started Jul 22 06:22:26 PM PDT 24
Finished Jul 22 06:30:10 PM PDT 24
Peak memory 237808 kb
Host smart-b59a2ce0-8793-41fd-a75c-737d6e24270d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212045510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2212045510
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3022215088
Short name T354
Test name
Test status
Simulation time 13128836420 ps
CPU time 33.46 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 212240 kb
Host smart-729eb8ed-ddd1-4070-bd8e-f85c0101164e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022215088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3022215088
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2193895045
Short name T339
Test name
Test status
Simulation time 667663782 ps
CPU time 9.22 seconds
Started Jul 22 06:22:35 PM PDT 24
Finished Jul 22 06:22:44 PM PDT 24
Peak memory 211336 kb
Host smart-dbf96d61-74c7-4332-bd99-0556d00b9aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193895045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2193895045
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.145100407
Short name T253
Test name
Test status
Simulation time 3166811801 ps
CPU time 29.64 seconds
Started Jul 22 06:22:33 PM PDT 24
Finished Jul 22 06:23:03 PM PDT 24
Peak memory 213248 kb
Host smart-137ad221-ba7e-4e12-bd45-2097b30be289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145100407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.145100407
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2312758918
Short name T311
Test name
Test status
Simulation time 9219725867 ps
CPU time 16.22 seconds
Started Jul 22 06:22:23 PM PDT 24
Finished Jul 22 06:22:40 PM PDT 24
Peak memory 211384 kb
Host smart-fe7d0ccc-7e9a-4507-b9ed-d33884539943
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312758918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2312758918
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4143826297
Short name T243
Test name
Test status
Simulation time 695396849 ps
CPU time 8.26 seconds
Started Jul 22 06:23:28 PM PDT 24
Finished Jul 22 06:23:37 PM PDT 24
Peak memory 211368 kb
Host smart-9469ba19-9f62-4c5a-9cfd-ec40911f0a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143826297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4143826297
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4282468606
Short name T310
Test name
Test status
Simulation time 12644037349 ps
CPU time 148.05 seconds
Started Jul 22 06:22:33 PM PDT 24
Finished Jul 22 06:25:01 PM PDT 24
Peak memory 228516 kb
Host smart-80eb343d-0218-40f3-95ee-df5968934940
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282468606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4282468606
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.398113714
Short name T166
Test name
Test status
Simulation time 1197185877 ps
CPU time 13.09 seconds
Started Jul 22 06:22:25 PM PDT 24
Finished Jul 22 06:22:41 PM PDT 24
Peak memory 212540 kb
Host smart-5340bdd8-03e2-4a02-b814-1904eb787c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398113714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.398113714
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3596083842
Short name T224
Test name
Test status
Simulation time 1825846739 ps
CPU time 14.68 seconds
Started Jul 22 06:22:35 PM PDT 24
Finished Jul 22 06:22:50 PM PDT 24
Peak memory 211336 kb
Host smart-21dd044a-3d12-47f0-be90-4cef1f3d7fc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596083842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3596083842
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.910009174
Short name T141
Test name
Test status
Simulation time 2094125255 ps
CPU time 14.06 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:40 PM PDT 24
Peak memory 212052 kb
Host smart-217eda02-de0d-4717-8700-ff36037d46b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910009174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.910009174
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1828979286
Short name T270
Test name
Test status
Simulation time 26282594926 ps
CPU time 40.32 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:23:06 PM PDT 24
Peak memory 217324 kb
Host smart-fda53c09-e11f-4faa-a082-c18b21129289
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828979286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1828979286
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.700648590
Short name T182
Test name
Test status
Simulation time 2071784680 ps
CPU time 16.02 seconds
Started Jul 22 06:21:56 PM PDT 24
Finished Jul 22 06:22:13 PM PDT 24
Peak memory 211480 kb
Host smart-965c043a-e32f-4287-a769-ad78ebc404db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700648590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.700648590
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.507592880
Short name T320
Test name
Test status
Simulation time 135693970970 ps
CPU time 136.48 seconds
Started Jul 22 06:22:21 PM PDT 24
Finished Jul 22 06:24:38 PM PDT 24
Peak memory 236756 kb
Host smart-40ef7a66-4ad7-48f5-8ff4-690e605343dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507592880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.507592880
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.36386898
Short name T118
Test name
Test status
Simulation time 6251827240 ps
CPU time 21.08 seconds
Started Jul 22 06:21:58 PM PDT 24
Finished Jul 22 06:22:20 PM PDT 24
Peak memory 212580 kb
Host smart-0ecc1c62-f486-4253-89c9-3db1d8848356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36386898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.36386898
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3653409003
Short name T125
Test name
Test status
Simulation time 2282336083 ps
CPU time 8.92 seconds
Started Jul 22 06:21:57 PM PDT 24
Finished Jul 22 06:22:06 PM PDT 24
Peak memory 211452 kb
Host smart-10f5f42c-dabb-4fa3-a31d-6dfc2960bc8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3653409003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3653409003
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1699413827
Short name T21
Test name
Test status
Simulation time 1111306577 ps
CPU time 106.94 seconds
Started Jul 22 06:22:02 PM PDT 24
Finished Jul 22 06:23:49 PM PDT 24
Peak memory 236812 kb
Host smart-f8131a15-7198-441d-8871-564ebd325513
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699413827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1699413827
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2800634869
Short name T281
Test name
Test status
Simulation time 2573158537 ps
CPU time 16.82 seconds
Started Jul 22 06:21:58 PM PDT 24
Finished Jul 22 06:22:16 PM PDT 24
Peak memory 213404 kb
Host smart-ff5fd203-7e66-4b14-a22f-780d2a962d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800634869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2800634869
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3661383624
Short name T127
Test name
Test status
Simulation time 1534124801 ps
CPU time 14.29 seconds
Started Jul 22 06:22:01 PM PDT 24
Finished Jul 22 06:22:15 PM PDT 24
Peak memory 211264 kb
Host smart-380f67d1-2603-4793-afe4-1761b985703e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661383624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3661383624
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.4248211260
Short name T11
Test name
Test status
Simulation time 197056524929 ps
CPU time 1927.75 seconds
Started Jul 22 06:22:02 PM PDT 24
Finished Jul 22 06:54:11 PM PDT 24
Peak memory 236292 kb
Host smart-c128c7c0-69d7-470a-8438-3b1cd073a378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248211260 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.4248211260
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3807977791
Short name T60
Test name
Test status
Simulation time 800125500 ps
CPU time 9.3 seconds
Started Jul 22 06:22:35 PM PDT 24
Finished Jul 22 06:22:45 PM PDT 24
Peak memory 211348 kb
Host smart-f99c6a5f-5967-4b42-a688-1c5ffcbaf89c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807977791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3807977791
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.271909724
Short name T223
Test name
Test status
Simulation time 63666564477 ps
CPU time 126.69 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:24:32 PM PDT 24
Peak memory 238960 kb
Host smart-82a0dd61-260e-4671-a552-83b03c12af78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271909724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.271909724
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3602561814
Short name T276
Test name
Test status
Simulation time 2134098371 ps
CPU time 22.37 seconds
Started Jul 22 06:22:34 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 211896 kb
Host smart-5fdf23fa-b3ff-4438-8c69-f3b0e808430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602561814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3602561814
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1504241645
Short name T183
Test name
Test status
Simulation time 1391225497 ps
CPU time 13.4 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:39 PM PDT 24
Peak memory 211240 kb
Host smart-ce5ab83e-658e-431a-b2a0-f583e3989e64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504241645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1504241645
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1014242434
Short name T74
Test name
Test status
Simulation time 1057771855 ps
CPU time 10.23 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:36 PM PDT 24
Peak memory 213936 kb
Host smart-11b0417e-a648-436b-bb6b-d49b0d352ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014242434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1014242434
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2137915926
Short name T319
Test name
Test status
Simulation time 222942139 ps
CPU time 11.06 seconds
Started Jul 22 06:22:57 PM PDT 24
Finished Jul 22 06:23:09 PM PDT 24
Peak memory 214928 kb
Host smart-7c2d6617-8c2d-41e7-8392-3bc4c5eb4677
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137915926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2137915926
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4192457528
Short name T18
Test name
Test status
Simulation time 9058708897 ps
CPU time 14.17 seconds
Started Jul 22 06:22:40 PM PDT 24
Finished Jul 22 06:22:55 PM PDT 24
Peak memory 211428 kb
Host smart-38d2d420-afec-43a1-8a01-74202732bec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192457528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4192457528
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1986505783
Short name T366
Test name
Test status
Simulation time 17412517599 ps
CPU time 200.42 seconds
Started Jul 22 06:22:36 PM PDT 24
Finished Jul 22 06:25:57 PM PDT 24
Peak memory 234900 kb
Host smart-b8de65d3-ef0a-4994-9662-60bb81f516a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986505783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1986505783
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3372770942
Short name T126
Test name
Test status
Simulation time 1109925730 ps
CPU time 16.51 seconds
Started Jul 22 06:24:39 PM PDT 24
Finished Jul 22 06:24:56 PM PDT 24
Peak memory 211876 kb
Host smart-e3eb2538-5e46-4632-94a6-da827a2cfcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372770942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3372770942
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1098044718
Short name T251
Test name
Test status
Simulation time 2526575753 ps
CPU time 9.24 seconds
Started Jul 22 06:22:30 PM PDT 24
Finished Jul 22 06:22:39 PM PDT 24
Peak memory 211620 kb
Host smart-7b6847f2-f6c0-417b-9522-bbf8072ec6e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098044718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1098044718
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.587880326
Short name T347
Test name
Test status
Simulation time 2549141716 ps
CPU time 10 seconds
Started Jul 22 06:24:39 PM PDT 24
Finished Jul 22 06:24:50 PM PDT 24
Peak memory 213376 kb
Host smart-c2562449-c0a1-4d43-9d6f-9fbdf34d4a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587880326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.587880326
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2952279987
Short name T247
Test name
Test status
Simulation time 56951623867 ps
CPU time 120.38 seconds
Started Jul 22 06:23:31 PM PDT 24
Finished Jul 22 06:25:32 PM PDT 24
Peak memory 219424 kb
Host smart-a33114bd-f558-4181-8425-0e14ae693091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952279987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2952279987
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2809353253
Short name T279
Test name
Test status
Simulation time 269300163964 ps
CPU time 5311.55 seconds
Started Jul 22 06:22:37 PM PDT 24
Finished Jul 22 07:51:10 PM PDT 24
Peak memory 252956 kb
Host smart-c9362036-4bea-4a68-b12a-021dffafcec9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809353253 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2809353253
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2397476285
Short name T292
Test name
Test status
Simulation time 89107045 ps
CPU time 4.19 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:22:47 PM PDT 24
Peak memory 211368 kb
Host smart-88acba0a-1bb4-4499-a041-3f0af68c7575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397476285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2397476285
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2837869521
Short name T29
Test name
Test status
Simulation time 84537058823 ps
CPU time 388.78 seconds
Started Jul 22 06:22:40 PM PDT 24
Finished Jul 22 06:29:10 PM PDT 24
Peak memory 212676 kb
Host smart-0e981fdb-57d2-40d2-8f0c-e86451602fab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837869521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2837869521
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1059931142
Short name T352
Test name
Test status
Simulation time 661130165 ps
CPU time 14.17 seconds
Started Jul 22 06:22:37 PM PDT 24
Finished Jul 22 06:22:52 PM PDT 24
Peak memory 212056 kb
Host smart-c7eb1ea1-f28a-468c-a43c-54a82517590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059931142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1059931142
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2209267465
Short name T307
Test name
Test status
Simulation time 1277714817 ps
CPU time 13.02 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:22:56 PM PDT 24
Peak memory 211400 kb
Host smart-2b2b9c4d-b006-4a06-8e72-79e608058c9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209267465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2209267465
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1381351766
Short name T336
Test name
Test status
Simulation time 5861757523 ps
CPU time 25.89 seconds
Started Jul 22 06:22:36 PM PDT 24
Finished Jul 22 06:23:03 PM PDT 24
Peak memory 213764 kb
Host smart-184699a2-af4c-456f-81f1-e83962ffe05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381351766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1381351766
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3625761939
Short name T282
Test name
Test status
Simulation time 162175573 ps
CPU time 4.33 seconds
Started Jul 22 06:22:37 PM PDT 24
Finished Jul 22 06:22:42 PM PDT 24
Peak memory 211360 kb
Host smart-2a8f83cc-0223-4295-8602-a1f9a0923025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625761939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3625761939
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2152621694
Short name T171
Test name
Test status
Simulation time 239372713689 ps
CPU time 579.87 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:32:23 PM PDT 24
Peak memory 237864 kb
Host smart-fe540e45-f4c8-440f-932a-6036c89d8ac9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152621694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2152621694
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2092521484
Short name T185
Test name
Test status
Simulation time 31798600257 ps
CPU time 27.88 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:23:11 PM PDT 24
Peak memory 212628 kb
Host smart-b45aace1-566d-45f7-9cf3-635b1c38366a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092521484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2092521484
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1717054513
Short name T201
Test name
Test status
Simulation time 859732632 ps
CPU time 9.38 seconds
Started Jul 22 06:23:57 PM PDT 24
Finished Jul 22 06:24:07 PM PDT 24
Peak memory 211360 kb
Host smart-471128a6-56b1-41f0-af04-ec78ca29b5e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1717054513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1717054513
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4150298384
Short name T356
Test name
Test status
Simulation time 3032246907 ps
CPU time 26.33 seconds
Started Jul 22 06:22:58 PM PDT 24
Finished Jul 22 06:23:26 PM PDT 24
Peak memory 213432 kb
Host smart-6bf4caba-0402-4f89-8951-7bd69c56e72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150298384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4150298384
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2585311419
Short name T325
Test name
Test status
Simulation time 6105846900 ps
CPU time 13.79 seconds
Started Jul 22 06:22:40 PM PDT 24
Finished Jul 22 06:22:55 PM PDT 24
Peak memory 211352 kb
Host smart-a1a3ec6e-075e-4971-86e0-b5eba402f9f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585311419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2585311419
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2768472842
Short name T196
Test name
Test status
Simulation time 2299540295 ps
CPU time 11.24 seconds
Started Jul 22 06:23:57 PM PDT 24
Finished Jul 22 06:24:09 PM PDT 24
Peak memory 211388 kb
Host smart-e35ab426-dae2-44f0-a3d9-8810b1e5ce32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768472842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2768472842
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1008957563
Short name T44
Test name
Test status
Simulation time 22408889985 ps
CPU time 167.05 seconds
Started Jul 22 06:22:37 PM PDT 24
Finished Jul 22 06:25:25 PM PDT 24
Peak memory 237880 kb
Host smart-ed948965-e60f-43ba-9f8a-ba8ed34f827c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008957563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1008957563
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3016131228
Short name T286
Test name
Test status
Simulation time 4264879234 ps
CPU time 32.71 seconds
Started Jul 22 06:23:56 PM PDT 24
Finished Jul 22 06:24:30 PM PDT 24
Peak memory 211944 kb
Host smart-ea319d94-2caf-49ca-925b-67a0c64b88a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016131228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3016131228
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4090242550
Short name T226
Test name
Test status
Simulation time 1932818685 ps
CPU time 16.21 seconds
Started Jul 22 06:23:57 PM PDT 24
Finished Jul 22 06:24:14 PM PDT 24
Peak memory 211360 kb
Host smart-e0679d99-c0d9-4a7a-a903-459bc9d95565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090242550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4090242550
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3744057511
Short name T329
Test name
Test status
Simulation time 1998545327 ps
CPU time 22.45 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:23:05 PM PDT 24
Peak memory 213016 kb
Host smart-d489038a-77d8-4934-96af-58f87901bf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744057511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3744057511
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1039717810
Short name T9
Test name
Test status
Simulation time 10577294324 ps
CPU time 34.88 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:23:17 PM PDT 24
Peak memory 214800 kb
Host smart-4b719258-0197-4adb-8fad-fa7c5d8f5f54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039717810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1039717810
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1308209878
Short name T48
Test name
Test status
Simulation time 73765306685 ps
CPU time 1400.48 seconds
Started Jul 22 06:22:37 PM PDT 24
Finished Jul 22 06:45:59 PM PDT 24
Peak memory 232432 kb
Host smart-9ead5fb6-010e-4c99-a5d1-867421580b71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308209878 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1308209878
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.183285620
Short name T30
Test name
Test status
Simulation time 6817994976 ps
CPU time 15.3 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 211424 kb
Host smart-a5fe8060-79c6-4cbb-8374-c237274a1e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183285620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.183285620
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3247425687
Short name T349
Test name
Test status
Simulation time 13008114820 ps
CPU time 94.01 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:24:17 PM PDT 24
Peak memory 212644 kb
Host smart-3cc3df4b-d482-466f-8350-e418eda16f9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247425687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3247425687
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4077502675
Short name T313
Test name
Test status
Simulation time 748702572 ps
CPU time 14.25 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 211904 kb
Host smart-529c6b80-0f6b-43c1-ba53-f853bb4cb52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077502675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4077502675
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3479033761
Short name T139
Test name
Test status
Simulation time 8039887914 ps
CPU time 16.92 seconds
Started Jul 22 06:22:39 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 211408 kb
Host smart-92aaddbb-b911-4851-8761-1d46b8e16d52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3479033761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3479033761
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3151519469
Short name T360
Test name
Test status
Simulation time 188141369 ps
CPU time 9.82 seconds
Started Jul 22 06:24:00 PM PDT 24
Finished Jul 22 06:24:10 PM PDT 24
Peak memory 213560 kb
Host smart-f4531e40-4b80-45cd-89da-888801a2faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151519469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3151519469
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3080682041
Short name T134
Test name
Test status
Simulation time 33751237491 ps
CPU time 33.87 seconds
Started Jul 22 06:22:37 PM PDT 24
Finished Jul 22 06:23:12 PM PDT 24
Peak memory 215324 kb
Host smart-1e190245-2d74-4359-b9ce-be7aae21bfb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080682041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3080682041
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.603966555
Short name T17
Test name
Test status
Simulation time 7222537103 ps
CPU time 14.81 seconds
Started Jul 22 06:22:39 PM PDT 24
Finished Jul 22 06:22:56 PM PDT 24
Peak memory 211380 kb
Host smart-b02a7e67-aeb9-4684-9d12-2d760513f149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603966555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.603966555
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2609213304
Short name T308
Test name
Test status
Simulation time 98868817289 ps
CPU time 425.3 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:29:48 PM PDT 24
Peak memory 233976 kb
Host smart-75bfcd65-0413-49ad-b60c-89522eb61ea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609213304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2609213304
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1286708779
Short name T236
Test name
Test status
Simulation time 2320309233 ps
CPU time 14.03 seconds
Started Jul 22 06:24:36 PM PDT 24
Finished Jul 22 06:24:51 PM PDT 24
Peak memory 216424 kb
Host smart-bf0705d5-b201-446b-afe3-2594aa6ee2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286708779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1286708779
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3944738951
Short name T123
Test name
Test status
Simulation time 7733851118 ps
CPU time 16.73 seconds
Started Jul 22 06:22:39 PM PDT 24
Finished Jul 22 06:22:58 PM PDT 24
Peak memory 211500 kb
Host smart-ab2f6549-47a9-4837-aacf-ecd8e60e9f63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944738951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3944738951
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3008882845
Short name T245
Test name
Test status
Simulation time 14830236874 ps
CPU time 36.28 seconds
Started Jul 22 06:22:42 PM PDT 24
Finished Jul 22 06:23:19 PM PDT 24
Peak memory 213948 kb
Host smart-3314542c-36d7-4016-8b38-9369c5ce3e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008882845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3008882845
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2546605856
Short name T303
Test name
Test status
Simulation time 48217121581 ps
CPU time 103.69 seconds
Started Jul 22 06:22:38 PM PDT 24
Finished Jul 22 06:24:23 PM PDT 24
Peak memory 217124 kb
Host smart-149bc850-e0fa-4105-8bc7-a4bc1aa04ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546605856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2546605856
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3440627781
Short name T163
Test name
Test status
Simulation time 87514120 ps
CPU time 4.32 seconds
Started Jul 22 06:22:38 PM PDT 24
Finished Jul 22 06:22:44 PM PDT 24
Peak memory 211404 kb
Host smart-3dfb56b5-356c-43c4-9984-e6e4a6bf37e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440627781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3440627781
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2409515864
Short name T248
Test name
Test status
Simulation time 21308387023 ps
CPU time 219.07 seconds
Started Jul 22 06:22:37 PM PDT 24
Finished Jul 22 06:26:17 PM PDT 24
Peak memory 228188 kb
Host smart-6d5a7f06-ff8b-4701-b8d4-30be7e04f554
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409515864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2409515864
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2366379523
Short name T330
Test name
Test status
Simulation time 519249071 ps
CPU time 12.89 seconds
Started Jul 22 06:22:36 PM PDT 24
Finished Jul 22 06:22:50 PM PDT 24
Peak memory 211900 kb
Host smart-5452bdd2-9155-4bcf-b7ee-6bedd00a3f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366379523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2366379523
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3890812957
Short name T297
Test name
Test status
Simulation time 3779468131 ps
CPU time 15.61 seconds
Started Jul 22 06:22:38 PM PDT 24
Finished Jul 22 06:22:55 PM PDT 24
Peak memory 211432 kb
Host smart-72d0d3a0-49fb-4755-b149-31efa8cda232
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890812957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3890812957
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2306637101
Short name T122
Test name
Test status
Simulation time 188294183 ps
CPU time 9.92 seconds
Started Jul 22 06:22:38 PM PDT 24
Finished Jul 22 06:22:50 PM PDT 24
Peak memory 213840 kb
Host smart-3c21927d-509b-4617-b739-5d8d0d8ec658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306637101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2306637101
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1345711621
Short name T73
Test name
Test status
Simulation time 7716592926 ps
CPU time 81.4 seconds
Started Jul 22 06:22:39 PM PDT 24
Finished Jul 22 06:24:02 PM PDT 24
Peak memory 215020 kb
Host smart-d97bc346-f7fc-4c48-b41e-0eaee1a10bf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345711621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1345711621
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3406148157
Short name T259
Test name
Test status
Simulation time 85880946 ps
CPU time 4.32 seconds
Started Jul 22 06:22:46 PM PDT 24
Finished Jul 22 06:22:51 PM PDT 24
Peak memory 211368 kb
Host smart-f484b318-9972-40c5-be82-c67e28413775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406148157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3406148157
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1503068726
Short name T361
Test name
Test status
Simulation time 25097021158 ps
CPU time 180.98 seconds
Started Jul 22 06:22:38 PM PDT 24
Finished Jul 22 06:25:41 PM PDT 24
Peak memory 233900 kb
Host smart-e531fe02-19d9-4cf1-a8a7-cbae2eb1f964
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503068726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1503068726
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.278902023
Short name T199
Test name
Test status
Simulation time 2860567031 ps
CPU time 18.85 seconds
Started Jul 22 06:22:39 PM PDT 24
Finished Jul 22 06:23:00 PM PDT 24
Peak memory 211904 kb
Host smart-25169661-703a-4bea-8221-b70c9336df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278902023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.278902023
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1202754291
Short name T158
Test name
Test status
Simulation time 95242549 ps
CPU time 5.29 seconds
Started Jul 22 06:22:40 PM PDT 24
Finished Jul 22 06:22:46 PM PDT 24
Peak memory 211364 kb
Host smart-bbe9fd20-7d5f-4a65-8058-30e86cbfd830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202754291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1202754291
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2626925238
Short name T165
Test name
Test status
Simulation time 2406663954 ps
CPU time 22.96 seconds
Started Jul 22 06:22:36 PM PDT 24
Finished Jul 22 06:23:00 PM PDT 24
Peak memory 213792 kb
Host smart-e2f5ff5f-3c98-4452-ae20-28f20b75fb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626925238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2626925238
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3187312110
Short name T136
Test name
Test status
Simulation time 3123903337 ps
CPU time 53.93 seconds
Started Jul 22 06:22:40 PM PDT 24
Finished Jul 22 06:23:35 PM PDT 24
Peak memory 217392 kb
Host smart-41219ba9-066d-4747-9955-4095dd9e23ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187312110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3187312110
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2179637789
Short name T50
Test name
Test status
Simulation time 16325681386 ps
CPU time 828.71 seconds
Started Jul 22 06:22:46 PM PDT 24
Finished Jul 22 06:36:36 PM PDT 24
Peak memory 227688 kb
Host smart-8891a498-6556-46ce-b082-6484f63bceb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179637789 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2179637789
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.739850440
Short name T155
Test name
Test status
Simulation time 1497458526 ps
CPU time 12.54 seconds
Started Jul 22 06:24:36 PM PDT 24
Finished Jul 22 06:24:49 PM PDT 24
Peak memory 211356 kb
Host smart-34f869b5-bb81-4e95-b4f9-5fc41ef456f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739850440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.739850440
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2153372475
Short name T153
Test name
Test status
Simulation time 148477195927 ps
CPU time 111.86 seconds
Started Jul 22 06:22:47 PM PDT 24
Finished Jul 22 06:24:39 PM PDT 24
Peak memory 234844 kb
Host smart-8c0cdbd0-214d-4874-80d5-1957b9383ce5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153372475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2153372475
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1978879077
Short name T175
Test name
Test status
Simulation time 98807649 ps
CPU time 5.71 seconds
Started Jul 22 06:23:57 PM PDT 24
Finished Jul 22 06:24:03 PM PDT 24
Peak memory 211360 kb
Host smart-ae1b62a1-ec55-41d2-afe3-954459354db9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978879077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1978879077
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.397814596
Short name T227
Test name
Test status
Simulation time 10201217345 ps
CPU time 25.43 seconds
Started Jul 22 06:22:49 PM PDT 24
Finished Jul 22 06:23:15 PM PDT 24
Peak memory 214444 kb
Host smart-3a84ef4a-104e-4686-a013-0bfe833772e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397814596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.397814596
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3628002734
Short name T176
Test name
Test status
Simulation time 1170026059 ps
CPU time 9.83 seconds
Started Jul 22 06:22:48 PM PDT 24
Finished Jul 22 06:22:58 PM PDT 24
Peak memory 211236 kb
Host smart-23c3219b-226e-4e6f-9853-4de510d93b97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628002734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3628002734
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1392845801
Short name T271
Test name
Test status
Simulation time 272926839294 ps
CPU time 2760.07 seconds
Started Jul 22 06:22:46 PM PDT 24
Finished Jul 22 07:08:46 PM PDT 24
Peak memory 240796 kb
Host smart-13607c25-4316-4a5f-ac84-acdba31af299
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392845801 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1392845801
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1547076986
Short name T142
Test name
Test status
Simulation time 2138134831 ps
CPU time 15.9 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:29 PM PDT 24
Peak memory 211356 kb
Host smart-9578a294-25a1-4dbc-881b-f75b7104d5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547076986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1547076986
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2809041041
Short name T357
Test name
Test status
Simulation time 68844204351 ps
CPU time 233.23 seconds
Started Jul 22 06:22:14 PM PDT 24
Finished Jul 22 06:26:09 PM PDT 24
Peak memory 233160 kb
Host smart-554de11a-0463-4587-9182-c75ffac302fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809041041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2809041041
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3337969854
Short name T315
Test name
Test status
Simulation time 3825538604 ps
CPU time 31.56 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:22:43 PM PDT 24
Peak memory 212108 kb
Host smart-a32fac14-f6c6-464a-af71-de67acdf95f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337969854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3337969854
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2654308768
Short name T343
Test name
Test status
Simulation time 17968610381 ps
CPU time 14.25 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:22:29 PM PDT 24
Peak memory 211464 kb
Host smart-2dbf94a9-3510-4487-b34f-e1d3012b7bec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654308768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2654308768
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1658788956
Short name T246
Test name
Test status
Simulation time 2980158120 ps
CPU time 30.6 seconds
Started Jul 22 06:22:02 PM PDT 24
Finished Jul 22 06:22:33 PM PDT 24
Peak memory 213112 kb
Host smart-53e370af-d326-4cb3-9dc9-c766702d8022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658788956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1658788956
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4065897811
Short name T95
Test name
Test status
Simulation time 4305969875 ps
CPU time 35.91 seconds
Started Jul 22 06:22:01 PM PDT 24
Finished Jul 22 06:22:38 PM PDT 24
Peak memory 214508 kb
Host smart-1758f876-85e6-4e4f-9ad5-ac150f2c99de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065897811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4065897811
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3229480130
Short name T51
Test name
Test status
Simulation time 40879022576 ps
CPU time 1951.22 seconds
Started Jul 22 06:22:02 PM PDT 24
Finished Jul 22 06:54:34 PM PDT 24
Peak memory 235860 kb
Host smart-2b9677c7-0bbd-4154-a9c7-c6dc13f08254
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229480130 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3229480130
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3532243801
Short name T174
Test name
Test status
Simulation time 1215689624 ps
CPU time 6.42 seconds
Started Jul 22 06:22:07 PM PDT 24
Finished Jul 22 06:22:14 PM PDT 24
Peak memory 211348 kb
Host smart-2d8e338d-9939-4b50-af19-147a59b82fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532243801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3532243801
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2105495764
Short name T331
Test name
Test status
Simulation time 2462630321 ps
CPU time 23.35 seconds
Started Jul 22 06:22:04 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 212096 kb
Host smart-21d49772-8a3c-41a7-8407-d0be223842d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105495764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2105495764
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.320008768
Short name T180
Test name
Test status
Simulation time 2828837635 ps
CPU time 13.83 seconds
Started Jul 22 06:22:17 PM PDT 24
Finished Jul 22 06:22:33 PM PDT 24
Peak memory 211464 kb
Host smart-9f31546b-4921-445f-b37d-1d2c5818bd2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=320008768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.320008768
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2646229551
Short name T263
Test name
Test status
Simulation time 8816273831 ps
CPU time 27.12 seconds
Started Jul 22 06:22:17 PM PDT 24
Finished Jul 22 06:22:46 PM PDT 24
Peak memory 213980 kb
Host smart-0a35c623-98cd-4704-8c1c-5792f735ac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646229551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2646229551
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2072242636
Short name T148
Test name
Test status
Simulation time 2786329418 ps
CPU time 30.96 seconds
Started Jul 22 06:22:05 PM PDT 24
Finished Jul 22 06:22:36 PM PDT 24
Peak memory 216476 kb
Host smart-9936f510-9e65-4054-b60e-3ab35aef6aae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072242636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2072242636
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1860780212
Short name T280
Test name
Test status
Simulation time 155625121312 ps
CPU time 907.63 seconds
Started Jul 22 06:22:09 PM PDT 24
Finished Jul 22 06:37:17 PM PDT 24
Peak memory 235772 kb
Host smart-39b03611-a8c9-4c50-8b89-e446eaceaf33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860780212 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1860780212
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3498413656
Short name T27
Test name
Test status
Simulation time 175652734 ps
CPU time 5.56 seconds
Started Jul 22 06:22:06 PM PDT 24
Finished Jul 22 06:22:12 PM PDT 24
Peak memory 211356 kb
Host smart-6571e14f-7aed-42f8-887e-707e98f7709b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498413656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3498413656
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1872468253
Short name T38
Test name
Test status
Simulation time 85958087162 ps
CPU time 205.6 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:25:40 PM PDT 24
Peak memory 212676 kb
Host smart-261c5d3d-02e3-4591-a3e6-1928fafa3c24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872468253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1872468253
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1357756446
Short name T348
Test name
Test status
Simulation time 175500225 ps
CPU time 9.6 seconds
Started Jul 22 06:22:07 PM PDT 24
Finished Jul 22 06:22:17 PM PDT 24
Peak memory 211948 kb
Host smart-d4176c1a-6062-45f9-8615-eb646ad7a4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357756446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1357756446
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3792289778
Short name T244
Test name
Test status
Simulation time 674632461 ps
CPU time 9.52 seconds
Started Jul 22 06:22:06 PM PDT 24
Finished Jul 22 06:22:16 PM PDT 24
Peak memory 211600 kb
Host smart-43543061-e447-44a4-b36c-192164f4b079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792289778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3792289778
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2274027156
Short name T100
Test name
Test status
Simulation time 15764242126 ps
CPU time 31.33 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:22:44 PM PDT 24
Peak memory 213956 kb
Host smart-15a97377-debb-46d7-a412-ccc17269ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274027156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2274027156
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1020977283
Short name T99
Test name
Test status
Simulation time 3112390808 ps
CPU time 30.95 seconds
Started Jul 22 06:22:11 PM PDT 24
Finished Jul 22 06:22:43 PM PDT 24
Peak memory 215300 kb
Host smart-76756df4-fc23-47d8-ba40-9ee3f7794032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020977283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1020977283
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.411210901
Short name T204
Test name
Test status
Simulation time 40919763821 ps
CPU time 2033.08 seconds
Started Jul 22 06:22:43 PM PDT 24
Finished Jul 22 06:56:37 PM PDT 24
Peak memory 235548 kb
Host smart-f4aa5f5b-445d-4207-93b3-5af859410e9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411210901 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.411210901
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2317827454
Short name T157
Test name
Test status
Simulation time 3767818399 ps
CPU time 9.63 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:22:20 PM PDT 24
Peak memory 211392 kb
Host smart-30f61806-0a9c-45a0-91e3-a0e6054c12f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317827454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2317827454
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2956369363
Short name T266
Test name
Test status
Simulation time 57771788666 ps
CPU time 253.39 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:26:25 PM PDT 24
Peak memory 233768 kb
Host smart-3cd4eb86-3e49-4413-84f9-9a34c547e61c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956369363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2956369363
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3898775313
Short name T96
Test name
Test status
Simulation time 8098903699 ps
CPU time 16.27 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:22:27 PM PDT 24
Peak memory 211460 kb
Host smart-8429d880-96eb-4f2d-8c50-b378b74cc9bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898775313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3898775313
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.149930140
Short name T362
Test name
Test status
Simulation time 185902282 ps
CPU time 9.98 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:23 PM PDT 24
Peak memory 213248 kb
Host smart-f092108e-fc79-41dc-bcb4-9e667a6d0f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149930140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.149930140
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.808176376
Short name T31
Test name
Test status
Simulation time 2759588541 ps
CPU time 26.16 seconds
Started Jul 22 06:22:10 PM PDT 24
Finished Jul 22 06:22:36 PM PDT 24
Peak memory 214876 kb
Host smart-add19241-d1ae-438f-a877-bc7e3c58a629
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808176376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.808176376
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.359290215
Short name T19
Test name
Test status
Simulation time 1504120039 ps
CPU time 5.54 seconds
Started Jul 22 06:22:07 PM PDT 24
Finished Jul 22 06:22:13 PM PDT 24
Peak memory 211308 kb
Host smart-7b37285d-f31e-4a86-844e-090c39e4ac49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359290215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.359290215
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.715270106
Short name T350
Test name
Test status
Simulation time 4480840926 ps
CPU time 134.09 seconds
Started Jul 22 06:22:13 PM PDT 24
Finished Jul 22 06:24:28 PM PDT 24
Peak memory 225320 kb
Host smart-15715066-81ca-4e97-93cb-96f43641fcfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715270106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.715270106
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3111301415
Short name T231
Test name
Test status
Simulation time 5300411802 ps
CPU time 18.28 seconds
Started Jul 22 06:22:08 PM PDT 24
Finished Jul 22 06:22:27 PM PDT 24
Peak memory 212272 kb
Host smart-772d7745-70f3-4b5c-bb72-3b888d39a45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111301415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3111301415
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4224496649
Short name T324
Test name
Test status
Simulation time 451693554 ps
CPU time 7.02 seconds
Started Jul 22 06:22:12 PM PDT 24
Finished Jul 22 06:22:21 PM PDT 24
Peak memory 211336 kb
Host smart-e173f144-3663-4b12-9633-bfc3a747616a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4224496649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4224496649
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.688241500
Short name T295
Test name
Test status
Simulation time 851345840 ps
CPU time 9.77 seconds
Started Jul 22 06:23:08 PM PDT 24
Finished Jul 22 06:23:18 PM PDT 24
Peak memory 213672 kb
Host smart-9d36f220-8345-4a17-a183-5b995c8b31cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688241500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.688241500
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2221184818
Short name T140
Test name
Test status
Simulation time 5767773490 ps
CPU time 34.06 seconds
Started Jul 22 06:22:08 PM PDT 24
Finished Jul 22 06:22:43 PM PDT 24
Peak memory 213820 kb
Host smart-2d772733-c4f8-4cce-b627-3bcb20a6b561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221184818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2221184818
Directory /workspace/9.rom_ctrl_stress_all/latest
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