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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.34 96.89 91.99 97.67 100.00 98.28 97.45 99.07


Total test records in report: 467
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T311 /workspace/coverage/default/44.rom_ctrl_alert_test.270246825 Jul 23 06:24:26 PM PDT 24 Jul 23 06:24:43 PM PDT 24 3759521452 ps
T312 /workspace/coverage/default/12.rom_ctrl_alert_test.4040223704 Jul 23 06:23:09 PM PDT 24 Jul 23 06:23:27 PM PDT 24 100323312 ps
T313 /workspace/coverage/default/45.rom_ctrl_smoke.549807014 Jul 23 06:24:26 PM PDT 24 Jul 23 06:24:54 PM PDT 24 10579076738 ps
T314 /workspace/coverage/default/28.rom_ctrl_smoke.1815644948 Jul 23 06:23:50 PM PDT 24 Jul 23 06:24:28 PM PDT 24 3784543164 ps
T315 /workspace/coverage/default/3.rom_ctrl_stress_all.3670639287 Jul 23 06:22:39 PM PDT 24 Jul 23 06:23:55 PM PDT 24 21517888681 ps
T316 /workspace/coverage/default/47.rom_ctrl_alert_test.823356355 Jul 23 06:24:35 PM PDT 24 Jul 23 06:24:47 PM PDT 24 4623535090 ps
T317 /workspace/coverage/default/22.rom_ctrl_alert_test.1244677332 Jul 23 06:23:42 PM PDT 24 Jul 23 06:23:53 PM PDT 24 923434917 ps
T318 /workspace/coverage/default/30.rom_ctrl_smoke.2861992333 Jul 23 06:23:55 PM PDT 24 Jul 23 06:24:07 PM PDT 24 2163009882 ps
T319 /workspace/coverage/default/24.rom_ctrl_smoke.3188583344 Jul 23 06:23:43 PM PDT 24 Jul 23 06:24:07 PM PDT 24 940422210 ps
T320 /workspace/coverage/default/18.rom_ctrl_alert_test.809006547 Jul 23 06:23:27 PM PDT 24 Jul 23 06:23:48 PM PDT 24 1065666727 ps
T321 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3879504387 Jul 23 06:23:42 PM PDT 24 Jul 23 06:58:32 PM PDT 24 60719733693 ps
T322 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2994813802 Jul 23 06:22:40 PM PDT 24 Jul 23 06:23:23 PM PDT 24 2985773701 ps
T323 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3004770890 Jul 23 06:23:16 PM PDT 24 Jul 23 06:23:36 PM PDT 24 2368563249 ps
T324 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2778381087 Jul 23 06:23:59 PM PDT 24 Jul 23 06:27:49 PM PDT 24 23077512177 ps
T325 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3571623050 Jul 23 06:23:07 PM PDT 24 Jul 23 06:23:54 PM PDT 24 4054333411 ps
T326 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3995370123 Jul 23 06:24:32 PM PDT 24 Jul 23 06:34:11 PM PDT 24 722638668695 ps
T327 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1434475935 Jul 23 06:23:22 PM PDT 24 Jul 23 06:23:49 PM PDT 24 5186547939 ps
T328 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1736402610 Jul 23 06:23:41 PM PDT 24 Jul 23 06:24:02 PM PDT 24 2516095219 ps
T329 /workspace/coverage/default/10.rom_ctrl_stress_all.3202923706 Jul 23 06:23:03 PM PDT 24 Jul 23 06:23:58 PM PDT 24 20541666359 ps
T330 /workspace/coverage/default/12.rom_ctrl_stress_all.2304386897 Jul 23 06:23:02 PM PDT 24 Jul 23 06:24:42 PM PDT 24 9340286139 ps
T331 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3763684002 Jul 23 06:23:54 PM PDT 24 Jul 23 06:27:18 PM PDT 24 268778874447 ps
T332 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2309088942 Jul 23 06:22:59 PM PDT 24 Jul 23 06:23:47 PM PDT 24 13132175258 ps
T333 /workspace/coverage/default/9.rom_ctrl_alert_test.3664500419 Jul 23 06:22:56 PM PDT 24 Jul 23 06:23:30 PM PDT 24 7651447476 ps
T334 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2277660968 Jul 23 06:22:49 PM PDT 24 Jul 23 06:23:21 PM PDT 24 1526066537 ps
T335 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3815447863 Jul 23 06:23:05 PM PDT 24 Jul 23 06:25:30 PM PDT 24 5072730886 ps
T336 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1408238360 Jul 23 06:23:05 PM PDT 24 Jul 23 06:23:35 PM PDT 24 4220879676 ps
T337 /workspace/coverage/default/44.rom_ctrl_smoke.2417503735 Jul 23 06:24:26 PM PDT 24 Jul 23 06:24:39 PM PDT 24 761059619 ps
T338 /workspace/coverage/default/29.rom_ctrl_smoke.1574877590 Jul 23 06:23:50 PM PDT 24 Jul 23 06:24:34 PM PDT 24 16090494900 ps
T339 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.835676810 Jul 23 06:24:16 PM PDT 24 Jul 23 06:31:30 PM PDT 24 173666596663 ps
T340 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2078601155 Jul 23 06:22:36 PM PDT 24 Jul 23 06:23:28 PM PDT 24 4100774998 ps
T341 /workspace/coverage/default/29.rom_ctrl_alert_test.768034279 Jul 23 06:23:55 PM PDT 24 Jul 23 06:24:06 PM PDT 24 1854956708 ps
T118 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1843242956 Jul 23 06:23:58 PM PDT 24 Jul 23 06:48:48 PM PDT 24 150992861558 ps
T342 /workspace/coverage/default/19.rom_ctrl_smoke.626750780 Jul 23 06:23:28 PM PDT 24 Jul 23 06:24:10 PM PDT 24 2979994284 ps
T343 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2110377696 Jul 23 06:24:00 PM PDT 24 Jul 23 06:24:27 PM PDT 24 11311408221 ps
T344 /workspace/coverage/default/48.rom_ctrl_smoke.2409857147 Jul 23 06:24:33 PM PDT 24 Jul 23 06:24:54 PM PDT 24 2064962334 ps
T345 /workspace/coverage/default/0.rom_ctrl_alert_test.2890937673 Jul 23 06:22:33 PM PDT 24 Jul 23 06:22:52 PM PDT 24 87172747 ps
T346 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3789594894 Jul 23 06:23:54 PM PDT 24 Jul 23 06:24:06 PM PDT 24 1392809938 ps
T347 /workspace/coverage/default/3.rom_ctrl_alert_test.1719449537 Jul 23 06:22:49 PM PDT 24 Jul 23 06:23:23 PM PDT 24 6654923151 ps
T348 /workspace/coverage/default/37.rom_ctrl_stress_all.2314000358 Jul 23 06:24:06 PM PDT 24 Jul 23 06:24:50 PM PDT 24 2987901873 ps
T349 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3970051988 Jul 23 06:24:07 PM PDT 24 Jul 23 06:24:35 PM PDT 24 2962286944 ps
T350 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3151272137 Jul 23 06:23:02 PM PDT 24 Jul 23 06:30:19 PM PDT 24 52219780482 ps
T351 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.807890674 Jul 23 06:24:25 PM PDT 24 Jul 23 06:27:50 PM PDT 24 5252887721 ps
T352 /workspace/coverage/default/19.rom_ctrl_stress_all.3892797237 Jul 23 06:23:26 PM PDT 24 Jul 23 06:23:56 PM PDT 24 1548378618 ps
T353 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1790181826 Jul 23 06:22:32 PM PDT 24 Jul 23 06:23:00 PM PDT 24 3914447896 ps
T354 /workspace/coverage/default/25.rom_ctrl_alert_test.2102082107 Jul 23 06:23:40 PM PDT 24 Jul 23 06:23:52 PM PDT 24 261636524 ps
T355 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2957535260 Jul 23 06:23:48 PM PDT 24 Jul 23 06:25:13 PM PDT 24 2627150297 ps
T356 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1611903865 Jul 23 06:24:05 PM PDT 24 Jul 23 06:24:22 PM PDT 24 6585226239 ps
T357 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3706499299 Jul 23 06:23:07 PM PDT 24 Jul 23 06:26:49 PM PDT 24 86857204801 ps
T358 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1231074044 Jul 23 06:24:08 PM PDT 24 Jul 23 06:24:42 PM PDT 24 8128136911 ps
T359 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3996749066 Jul 23 06:23:44 PM PDT 24 Jul 23 06:23:56 PM PDT 24 103637983 ps
T360 /workspace/coverage/default/38.rom_ctrl_alert_test.361467431 Jul 23 06:24:15 PM PDT 24 Jul 23 06:24:22 PM PDT 24 488956187 ps
T361 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1522896335 Jul 23 06:24:07 PM PDT 24 Jul 23 06:24:20 PM PDT 24 809101764 ps
T362 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3091913112 Jul 23 06:23:42 PM PDT 24 Jul 23 06:23:56 PM PDT 24 183118430 ps
T363 /workspace/coverage/default/39.rom_ctrl_smoke.4251322120 Jul 23 06:24:18 PM PDT 24 Jul 23 06:24:59 PM PDT 24 4441867326 ps
T364 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2857524663 Jul 23 06:24:27 PM PDT 24 Jul 23 06:24:42 PM PDT 24 1338659532 ps
T365 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.58649901 Jul 23 06:22:51 PM PDT 24 Jul 23 06:23:25 PM PDT 24 7841084549 ps
T366 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.151516886 Jul 23 06:24:29 PM PDT 24 Jul 23 07:43:08 PM PDT 24 514424595291 ps
T367 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.191943849 Jul 23 06:24:19 PM PDT 24 Jul 23 06:24:36 PM PDT 24 5915941098 ps
T368 /workspace/coverage/default/33.rom_ctrl_stress_all.1402461403 Jul 23 06:23:59 PM PDT 24 Jul 23 06:24:54 PM PDT 24 22645708388 ps
T98 /workspace/coverage/default/23.rom_ctrl_stress_all.788933761 Jul 23 06:23:42 PM PDT 24 Jul 23 06:24:19 PM PDT 24 4594435594 ps
T99 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.715994820 Jul 23 06:23:07 PM PDT 24 Jul 23 08:42:40 PM PDT 24 153779329820 ps
T100 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3880917537 Jul 23 06:24:12 PM PDT 24 Jul 23 06:24:23 PM PDT 24 693193433 ps
T28 /workspace/coverage/default/2.rom_ctrl_sec_cm.367960004 Jul 23 06:22:49 PM PDT 24 Jul 23 06:24:06 PM PDT 24 11990442245 ps
T101 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2746248747 Jul 23 06:24:33 PM PDT 24 Jul 23 06:25:00 PM PDT 24 16311075340 ps
T102 /workspace/coverage/default/2.rom_ctrl_smoke.2007263766 Jul 23 06:22:41 PM PDT 24 Jul 23 06:23:27 PM PDT 24 14997379397 ps
T103 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3637449646 Jul 23 06:23:48 PM PDT 24 Jul 23 06:24:08 PM PDT 24 1510465801 ps
T104 /workspace/coverage/default/38.rom_ctrl_smoke.398837108 Jul 23 06:24:18 PM PDT 24 Jul 23 06:24:45 PM PDT 24 3606146914 ps
T105 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3034111297 Jul 23 06:24:37 PM PDT 24 Jul 23 06:43:22 PM PDT 24 109491219930 ps
T106 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3642893681 Jul 23 06:22:45 PM PDT 24 Jul 23 06:23:12 PM PDT 24 896796490 ps
T369 /workspace/coverage/default/17.rom_ctrl_stress_all.348168799 Jul 23 06:23:27 PM PDT 24 Jul 23 06:24:31 PM PDT 24 26837862924 ps
T370 /workspace/coverage/default/34.rom_ctrl_alert_test.2308198178 Jul 23 06:24:07 PM PDT 24 Jul 23 06:24:25 PM PDT 24 2007148111 ps
T371 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3006936795 Jul 23 06:22:33 PM PDT 24 Jul 23 06:23:52 PM PDT 24 2061837038 ps
T71 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3424146067 Jul 23 06:24:59 PM PDT 24 Jul 23 06:25:12 PM PDT 24 1547307761 ps
T72 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2360525611 Jul 23 06:25:05 PM PDT 24 Jul 23 06:25:19 PM PDT 24 1020766393 ps
T73 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2245662649 Jul 23 06:25:08 PM PDT 24 Jul 23 06:26:53 PM PDT 24 27165562508 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1496106457 Jul 23 06:25:14 PM PDT 24 Jul 23 06:25:32 PM PDT 24 3570391025 ps
T108 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.141651112 Jul 23 06:24:52 PM PDT 24 Jul 23 06:25:05 PM PDT 24 598818772 ps
T78 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1255115841 Jul 23 06:25:06 PM PDT 24 Jul 23 06:26:49 PM PDT 24 69875061187 ps
T372 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3404736099 Jul 23 06:24:51 PM PDT 24 Jul 23 06:25:07 PM PDT 24 4262795596 ps
T373 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4186454054 Jul 23 06:25:12 PM PDT 24 Jul 23 06:25:28 PM PDT 24 6170696747 ps
T374 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1224146615 Jul 23 06:25:05 PM PDT 24 Jul 23 06:25:13 PM PDT 24 103798368 ps
T375 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1806526874 Jul 23 06:24:51 PM PDT 24 Jul 23 06:25:10 PM PDT 24 5842087254 ps
T79 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4277807161 Jul 23 06:24:44 PM PDT 24 Jul 23 06:24:55 PM PDT 24 590523900 ps
T376 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3370364285 Jul 23 06:24:51 PM PDT 24 Jul 23 06:25:12 PM PDT 24 3744552926 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2320962319 Jul 23 06:25:20 PM PDT 24 Jul 23 06:25:40 PM PDT 24 1965986609 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.655895341 Jul 23 06:24:43 PM PDT 24 Jul 23 06:24:49 PM PDT 24 86694185 ps
T379 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.123816160 Jul 23 06:24:38 PM PDT 24 Jul 23 06:24:49 PM PDT 24 4240237430 ps
T109 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.175625298 Jul 23 06:25:20 PM PDT 24 Jul 23 06:25:34 PM PDT 24 1380488016 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1396667021 Jul 23 06:25:06 PM PDT 24 Jul 23 06:25:19 PM PDT 24 905800999 ps
T114 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3820484843 Jul 23 06:24:43 PM PDT 24 Jul 23 06:24:50 PM PDT 24 347022733 ps
T80 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.994337730 Jul 23 06:25:06 PM PDT 24 Jul 23 06:25:28 PM PDT 24 369970467 ps
T115 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3526781767 Jul 23 06:25:14 PM PDT 24 Jul 23 06:25:21 PM PDT 24 93626303 ps
T81 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.860533035 Jul 23 06:25:07 PM PDT 24 Jul 23 06:25:25 PM PDT 24 1687945617 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2235061615 Jul 23 06:24:44 PM PDT 24 Jul 23 06:25:00 PM PDT 24 6491190428 ps
T82 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3544852458 Jul 23 06:25:04 PM PDT 24 Jul 23 06:25:23 PM PDT 24 4275057729 ps
T110 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3660778508 Jul 23 06:25:07 PM PDT 24 Jul 23 06:25:26 PM PDT 24 2082348842 ps
T382 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2060525849 Jul 23 06:25:13 PM PDT 24 Jul 23 06:25:24 PM PDT 24 105669472 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3252352317 Jul 23 06:24:58 PM PDT 24 Jul 23 06:25:47 PM PDT 24 4704331551 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.824229184 Jul 23 06:24:38 PM PDT 24 Jul 23 06:24:53 PM PDT 24 31906209671 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2076488398 Jul 23 06:24:44 PM PDT 24 Jul 23 06:25:05 PM PDT 24 7767081993 ps
T117 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2866598851 Jul 23 06:24:51 PM PDT 24 Jul 23 06:25:37 PM PDT 24 4196908259 ps
T111 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2314892839 Jul 23 06:25:06 PM PDT 24 Jul 23 06:25:19 PM PDT 24 820781913 ps
T84 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1586556867 Jul 23 06:25:04 PM PDT 24 Jul 23 06:25:20 PM PDT 24 1636467153 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3632955188 Jul 23 06:24:39 PM PDT 24 Jul 23 06:25:29 PM PDT 24 5120127829 ps
T112 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.976708250 Jul 23 06:24:42 PM PDT 24 Jul 23 06:24:59 PM PDT 24 7278005493 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2624997580 Jul 23 06:24:38 PM PDT 24 Jul 23 06:24:54 PM PDT 24 1747378133 ps
T385 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3206313695 Jul 23 06:25:05 PM PDT 24 Jul 23 06:25:24 PM PDT 24 1816611704 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.268128009 Jul 23 06:24:39 PM PDT 24 Jul 23 06:24:52 PM PDT 24 1235517262 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1415086537 Jul 23 06:24:45 PM PDT 24 Jul 23 06:24:53 PM PDT 24 351233290 ps
T86 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4187509997 Jul 23 06:25:20 PM PDT 24 Jul 23 06:25:32 PM PDT 24 828259825 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2282021360 Jul 23 06:24:45 PM PDT 24 Jul 23 06:24:56 PM PDT 24 2033268307 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.688904808 Jul 23 06:24:40 PM PDT 24 Jul 23 06:24:55 PM PDT 24 742774407 ps
T68 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1658762832 Jul 23 06:25:06 PM PDT 24 Jul 23 06:25:49 PM PDT 24 650050584 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.127319053 Jul 23 06:24:47 PM PDT 24 Jul 23 06:25:00 PM PDT 24 1158505205 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2132017319 Jul 23 06:24:45 PM PDT 24 Jul 23 06:25:56 PM PDT 24 867124471 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3932260704 Jul 23 06:24:40 PM PDT 24 Jul 23 06:24:51 PM PDT 24 1976623607 ps
T87 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1422691007 Jul 23 06:25:21 PM PDT 24 Jul 23 06:26:31 PM PDT 24 21938741353 ps
T88 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.167069995 Jul 23 06:24:59 PM PDT 24 Jul 23 06:25:30 PM PDT 24 2223071652 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1834177102 Jul 23 06:25:21 PM PDT 24 Jul 23 06:25:40 PM PDT 24 16947087503 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1648785204 Jul 23 06:24:40 PM PDT 24 Jul 23 06:24:50 PM PDT 24 1568174053 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2843782773 Jul 23 06:25:06 PM PDT 24 Jul 23 06:25:26 PM PDT 24 1484639817 ps
T394 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1462469656 Jul 23 06:24:58 PM PDT 24 Jul 23 06:25:11 PM PDT 24 628615678 ps
T119 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.476600429 Jul 23 06:25:13 PM PDT 24 Jul 23 06:25:57 PM PDT 24 2934755850 ps
T395 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2903990993 Jul 23 06:24:59 PM PDT 24 Jul 23 06:25:19 PM PDT 24 1194800040 ps
T123 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1461558442 Jul 23 06:25:04 PM PDT 24 Jul 23 06:25:47 PM PDT 24 836540159 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1861587561 Jul 23 06:24:51 PM PDT 24 Jul 23 06:24:57 PM PDT 24 357329898 ps
T125 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.519860728 Jul 23 06:25:01 PM PDT 24 Jul 23 06:26:11 PM PDT 24 1433480105 ps
T89 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.491277576 Jul 23 06:24:50 PM PDT 24 Jul 23 06:25:03 PM PDT 24 3040920356 ps
T397 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1138664639 Jul 23 06:24:58 PM PDT 24 Jul 23 06:25:14 PM PDT 24 4621247815 ps
T120 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4260084032 Jul 23 06:25:13 PM PDT 24 Jul 23 06:26:04 PM PDT 24 9712712249 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2572797287 Jul 23 06:24:43 PM PDT 24 Jul 23 06:25:01 PM PDT 24 1917498193 ps
T399 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3260674356 Jul 23 06:24:58 PM PDT 24 Jul 23 06:25:30 PM PDT 24 2242541699 ps
T400 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3650053845 Jul 23 06:24:59 PM PDT 24 Jul 23 06:25:12 PM PDT 24 4531695970 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1202943499 Jul 23 06:24:52 PM PDT 24 Jul 23 06:25:13 PM PDT 24 725266564 ps
T402 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.503346357 Jul 23 06:25:05 PM PDT 24 Jul 23 06:25:21 PM PDT 24 5547428975 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.164282583 Jul 23 06:24:57 PM PDT 24 Jul 23 06:25:15 PM PDT 24 25271637453 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.573313628 Jul 23 06:24:38 PM PDT 24 Jul 23 06:24:47 PM PDT 24 621382824 ps
T90 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.378107862 Jul 23 06:25:15 PM PDT 24 Jul 23 06:25:24 PM PDT 24 1810655705 ps
T405 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2806040094 Jul 23 06:25:13 PM PDT 24 Jul 23 06:25:24 PM PDT 24 668763111 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2147789901 Jul 23 06:24:42 PM PDT 24 Jul 23 06:24:54 PM PDT 24 3754317074 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3083345135 Jul 23 06:24:44 PM PDT 24 Jul 23 06:25:07 PM PDT 24 8267057094 ps
T91 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3427940042 Jul 23 06:25:13 PM PDT 24 Jul 23 06:25:43 PM PDT 24 551383316 ps
T408 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.228806345 Jul 23 06:24:49 PM PDT 24 Jul 23 06:25:10 PM PDT 24 7195394604 ps
T409 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1043535016 Jul 23 06:24:41 PM PDT 24 Jul 23 06:24:56 PM PDT 24 1456123726 ps
T121 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1992369395 Jul 23 06:24:50 PM PDT 24 Jul 23 06:26:01 PM PDT 24 796524947 ps
T410 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2203990902 Jul 23 06:24:58 PM PDT 24 Jul 23 06:25:22 PM PDT 24 7545404928 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2312873953 Jul 23 06:24:43 PM PDT 24 Jul 23 06:24:58 PM PDT 24 12275376576 ps
T412 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1444358728 Jul 23 06:25:05 PM PDT 24 Jul 23 06:26:12 PM PDT 24 94902794380 ps
T413 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.829262930 Jul 23 06:24:59 PM PDT 24 Jul 23 06:25:20 PM PDT 24 8665849217 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.456344968 Jul 23 06:24:37 PM PDT 24 Jul 23 06:24:45 PM PDT 24 2654531474 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1724583481 Jul 23 06:24:44 PM PDT 24 Jul 23 06:24:58 PM PDT 24 4293951928 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3734137105 Jul 23 06:24:43 PM PDT 24 Jul 23 06:24:52 PM PDT 24 306611356 ps
T417 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3364726317 Jul 23 06:24:52 PM PDT 24 Jul 23 06:25:06 PM PDT 24 901660109 ps
T418 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3584632503 Jul 23 06:24:40 PM PDT 24 Jul 23 06:25:37 PM PDT 24 27952287881 ps
T419 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3046877169 Jul 23 06:24:45 PM PDT 24 Jul 23 06:26:09 PM PDT 24 9647928461 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1942424676 Jul 23 06:24:40 PM PDT 24 Jul 23 06:24:49 PM PDT 24 434515577 ps
T95 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3567753518 Jul 23 06:25:14 PM PDT 24 Jul 23 06:25:31 PM PDT 24 1719588871 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2423856214 Jul 23 06:24:44 PM PDT 24 Jul 23 06:24:52 PM PDT 24 346308168 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2555759365 Jul 23 06:24:45 PM PDT 24 Jul 23 06:24:59 PM PDT 24 1228748390 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3225874058 Jul 23 06:24:38 PM PDT 24 Jul 23 06:24:53 PM PDT 24 6719445248 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2960655906 Jul 23 06:24:40 PM PDT 24 Jul 23 06:24:59 PM PDT 24 3816728077 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2343877321 Jul 23 06:24:57 PM PDT 24 Jul 23 06:25:10 PM PDT 24 1068182122 ps
T425 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2683268911 Jul 23 06:25:07 PM PDT 24 Jul 23 06:25:18 PM PDT 24 1076260394 ps
T426 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3942143317 Jul 23 06:24:47 PM PDT 24 Jul 23 06:24:56 PM PDT 24 472508759 ps
T124 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3418140118 Jul 23 06:24:50 PM PDT 24 Jul 23 06:26:10 PM PDT 24 2332421745 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3216823734 Jul 23 06:24:47 PM PDT 24 Jul 23 06:25:04 PM PDT 24 7829478599 ps
T428 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1568491511 Jul 23 06:24:42 PM PDT 24 Jul 23 06:24:57 PM PDT 24 6082284901 ps
T429 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.487882684 Jul 23 06:24:57 PM PDT 24 Jul 23 06:25:05 PM PDT 24 3034421743 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.821982919 Jul 23 06:24:45 PM PDT 24 Jul 23 06:25:01 PM PDT 24 3738751562 ps
T127 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.331272884 Jul 23 06:25:12 PM PDT 24 Jul 23 06:26:01 PM PDT 24 5576607431 ps
T128 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4190325274 Jul 23 06:24:50 PM PDT 24 Jul 23 06:25:33 PM PDT 24 2289971409 ps
T130 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3548221859 Jul 23 06:24:47 PM PDT 24 Jul 23 06:25:35 PM PDT 24 12625777974 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3026080778 Jul 23 06:24:44 PM PDT 24 Jul 23 06:25:37 PM PDT 24 3503270895 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2200179815 Jul 23 06:24:44 PM PDT 24 Jul 23 06:24:56 PM PDT 24 261951928 ps
T431 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2053640980 Jul 23 06:25:13 PM PDT 24 Jul 23 06:25:27 PM PDT 24 1530978431 ps
T432 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4210757809 Jul 23 06:25:13 PM PDT 24 Jul 23 06:25:23 PM PDT 24 335046577 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.454000771 Jul 23 06:24:57 PM PDT 24 Jul 23 06:25:14 PM PDT 24 1117981015 ps
T129 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3104588187 Jul 23 06:25:22 PM PDT 24 Jul 23 06:26:44 PM PDT 24 7853288945 ps
T434 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1787355256 Jul 23 06:24:59 PM PDT 24 Jul 23 06:25:13 PM PDT 24 3113646187 ps
T97 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.728269938 Jul 23 06:24:57 PM PDT 24 Jul 23 06:26:37 PM PDT 24 24775555006 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4204658288 Jul 23 06:24:42 PM PDT 24 Jul 23 06:25:00 PM PDT 24 8271144291 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.772275970 Jul 23 06:24:43 PM PDT 24 Jul 23 06:25:55 PM PDT 24 8702757158 ps
T437 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3454935652 Jul 23 06:24:58 PM PDT 24 Jul 23 06:25:12 PM PDT 24 2122545633 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1774997690 Jul 23 06:24:46 PM PDT 24 Jul 23 06:24:58 PM PDT 24 2870608534 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2056754650 Jul 23 06:24:42 PM PDT 24 Jul 23 06:24:54 PM PDT 24 4279636854 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.73154496 Jul 23 06:24:39 PM PDT 24 Jul 23 06:24:47 PM PDT 24 542633992 ps
T441 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3342986929 Jul 23 06:25:13 PM PDT 24 Jul 23 06:26:22 PM PDT 24 58308680705 ps
T442 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.283892687 Jul 23 06:25:20 PM PDT 24 Jul 23 06:25:37 PM PDT 24 9313403742 ps
T443 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2790419206 Jul 23 06:25:19 PM PDT 24 Jul 23 06:25:36 PM PDT 24 1919333920 ps
T444 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1181191408 Jul 23 06:24:38 PM PDT 24 Jul 23 06:25:17 PM PDT 24 158135675 ps
T131 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3102185162 Jul 23 06:25:04 PM PDT 24 Jul 23 06:25:44 PM PDT 24 724111766 ps
T126 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4293097537 Jul 23 06:24:37 PM PDT 24 Jul 23 06:25:47 PM PDT 24 220796471 ps
T445 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2427397176 Jul 23 06:24:58 PM PDT 24 Jul 23 06:25:42 PM PDT 24 415366238 ps
T446 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2797170355 Jul 23 06:24:52 PM PDT 24 Jul 23 06:25:32 PM PDT 24 1977356513 ps
T447 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2338060211 Jul 23 06:24:57 PM PDT 24 Jul 23 06:25:12 PM PDT 24 8002789797 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1942178818 Jul 23 06:24:37 PM PDT 24 Jul 23 06:24:43 PM PDT 24 89170430 ps
T449 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3366764420 Jul 23 06:24:51 PM PDT 24 Jul 23 06:25:09 PM PDT 24 1975176575 ps
T450 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.511021317 Jul 23 06:24:51 PM PDT 24 Jul 23 06:25:08 PM PDT 24 1527780083 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2742192546 Jul 23 06:24:45 PM PDT 24 Jul 23 06:24:57 PM PDT 24 299946486 ps
T452 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.883574901 Jul 23 06:25:16 PM PDT 24 Jul 23 06:25:38 PM PDT 24 1974430940 ps
T453 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.568766235 Jul 23 06:24:58 PM PDT 24 Jul 23 06:25:07 PM PDT 24 87172696 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4203684221 Jul 23 06:24:40 PM PDT 24 Jul 23 06:25:01 PM PDT 24 1976325013 ps
T455 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2118699540 Jul 23 06:24:58 PM PDT 24 Jul 23 06:25:13 PM PDT 24 3509080278 ps
T456 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4090917706 Jul 23 06:24:37 PM PDT 24 Jul 23 06:24:46 PM PDT 24 119576024 ps
T457 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.437551978 Jul 23 06:25:05 PM PDT 24 Jul 23 06:25:25 PM PDT 24 2747806894 ps
T458 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3519135298 Jul 23 06:24:52 PM PDT 24 Jul 23 06:25:14 PM PDT 24 607358414 ps
T459 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1367793036 Jul 23 06:24:52 PM PDT 24 Jul 23 06:25:03 PM PDT 24 5144815568 ps
T460 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3118826478 Jul 23 06:24:40 PM PDT 24 Jul 23 06:24:55 PM PDT 24 5184622516 ps
T461 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3361638660 Jul 23 06:24:44 PM PDT 24 Jul 23 06:24:58 PM PDT 24 18428873951 ps
T122 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1978356760 Jul 23 06:24:38 PM PDT 24 Jul 23 06:25:22 PM PDT 24 1305921907 ps
T462 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2321720151 Jul 23 06:25:07 PM PDT 24 Jul 23 06:25:24 PM PDT 24 2063877939 ps
T463 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2374813724 Jul 23 06:24:50 PM PDT 24 Jul 23 06:25:05 PM PDT 24 14306592179 ps
T464 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.285658324 Jul 23 06:24:58 PM PDT 24 Jul 23 06:25:39 PM PDT 24 1348153076 ps
T465 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.33956117 Jul 23 06:24:59 PM PDT 24 Jul 23 06:26:12 PM PDT 24 1348949440 ps
T466 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.307038267 Jul 23 06:24:39 PM PDT 24 Jul 23 06:25:41 PM PDT 24 30781242410 ps
T467 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2815115044 Jul 23 06:24:50 PM PDT 24 Jul 23 06:24:56 PM PDT 24 178555537 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1186345161 Jul 23 06:24:59 PM PDT 24 Jul 23 06:25:18 PM PDT 24 1691772322 ps

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2403549129
Short name T6
Test name
Test status
Simulation time 1051310690 ps
CPU time 26.6 seconds
Started Jul 23 06:23:07 PM PDT 24
Finished Jul 23 06:23:48 PM PDT 24
Peak memory 216320 kb
Host smart-8840d665-429d-4aaa-9f89-d4a87c62a5b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403549129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2403549129
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3454402015
Short name T16
Test name
Test status
Simulation time 105370494597 ps
CPU time 2038.6 seconds
Started Jul 23 06:23:03 PM PDT 24
Finished Jul 23 06:57:17 PM PDT 24
Peak memory 244084 kb
Host smart-631b35f3-5fca-455d-a19c-2207b69aca20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454402015 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3454402015
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.92036325
Short name T22
Test name
Test status
Simulation time 8030008705 ps
CPU time 118.01 seconds
Started Jul 23 06:24:02 PM PDT 24
Finished Jul 23 06:26:01 PM PDT 24
Peak memory 234968 kb
Host smart-c99c9c84-0960-4375-92a2-1caa35f938d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92036325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_co
rrupt_sig_fatal_chk.92036325
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2438082669
Short name T38
Test name
Test status
Simulation time 58995215870 ps
CPU time 305.79 seconds
Started Jul 23 06:24:12 PM PDT 24
Finished Jul 23 06:29:20 PM PDT 24
Peak memory 236344 kb
Host smart-3ee3d8a2-d449-4630-8047-01fe6c1745aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438082669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2438082669
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.715753707
Short name T53
Test name
Test status
Simulation time 22884328516 ps
CPU time 16.2 seconds
Started Jul 23 06:23:48 PM PDT 24
Finished Jul 23 06:24:09 PM PDT 24
Peak memory 211444 kb
Host smart-16d982fc-99a8-43e8-8d68-fb22401f0fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715753707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.715753707
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2132017319
Short name T69
Test name
Test status
Simulation time 867124471 ps
CPU time 67.97 seconds
Started Jul 23 06:24:45 PM PDT 24
Finished Jul 23 06:25:56 PM PDT 24
Peak memory 218768 kb
Host smart-60035ce9-860b-49de-a019-0929438a0b90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132017319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2132017319
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4125303790
Short name T14
Test name
Test status
Simulation time 613411818 ps
CPU time 13.82 seconds
Started Jul 23 06:23:02 PM PDT 24
Finished Jul 23 06:23:32 PM PDT 24
Peak memory 211388 kb
Host smart-1a50211b-d20c-4e28-9e4f-4b34fa1d2bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125303790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4125303790
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2499216027
Short name T24
Test name
Test status
Simulation time 4390143603 ps
CPU time 107.36 seconds
Started Jul 23 06:22:40 PM PDT 24
Finished Jul 23 06:24:45 PM PDT 24
Peak memory 237012 kb
Host smart-3fb264dc-f237-4606-9b1c-e60659950d99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499216027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2499216027
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3104588187
Short name T129
Test name
Test status
Simulation time 7853288945 ps
CPU time 77.1 seconds
Started Jul 23 06:25:22 PM PDT 24
Finished Jul 23 06:26:44 PM PDT 24
Peak memory 218924 kb
Host smart-20178a97-6b8b-43d4-91e9-e96e83b637c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104588187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3104588187
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1255115841
Short name T78
Test name
Test status
Simulation time 69875061187 ps
CPU time 100.02 seconds
Started Jul 23 06:25:06 PM PDT 24
Finished Jul 23 06:26:49 PM PDT 24
Peak memory 210752 kb
Host smart-f698d8f8-6a51-40a4-82d0-778fbd4dd71a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255115841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1255115841
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.788933761
Short name T98
Test name
Test status
Simulation time 4594435594 ps
CPU time 29.87 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:24:19 PM PDT 24
Peak memory 213520 kb
Host smart-20f22b7c-867f-430a-b9ca-45d8a28261c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788933761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.788933761
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1786732911
Short name T11
Test name
Test status
Simulation time 6739956299 ps
CPU time 29.74 seconds
Started Jul 23 06:24:15 PM PDT 24
Finished Jul 23 06:24:47 PM PDT 24
Peak memory 212360 kb
Host smart-fc42257d-bfcc-424d-af65-3772dc3cb199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786732911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1786732911
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.593229323
Short name T51
Test name
Test status
Simulation time 174131478 ps
CPU time 9.44 seconds
Started Jul 23 06:24:32 PM PDT 24
Finished Jul 23 06:24:43 PM PDT 24
Peak memory 212072 kb
Host smart-b979d7ed-2ff7-43e6-a3d3-27ff64d1e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593229323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.593229323
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4059368334
Short name T55
Test name
Test status
Simulation time 159053101089 ps
CPU time 3856.06 seconds
Started Jul 23 06:24:04 PM PDT 24
Finished Jul 23 07:28:21 PM PDT 24
Peak memory 250704 kb
Host smart-7a2679d5-d76c-4597-a2fe-f66f495c8a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059368334 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.4059368334
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.821982919
Short name T93
Test name
Test status
Simulation time 3738751562 ps
CPU time 13.06 seconds
Started Jul 23 06:24:45 PM PDT 24
Finished Jul 23 06:25:01 PM PDT 24
Peak memory 210572 kb
Host smart-81592a09-b31d-42d5-8d7d-df2dcd4d3264
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821982919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.821982919
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1978356760
Short name T122
Test name
Test status
Simulation time 1305921907 ps
CPU time 42.4 seconds
Started Jul 23 06:24:38 PM PDT 24
Finished Jul 23 06:25:22 PM PDT 24
Peak memory 218800 kb
Host smart-12c9ea2c-6e49-4c45-9fb9-b3a666fb8570
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978356760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1978356760
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4293097537
Short name T126
Test name
Test status
Simulation time 220796471 ps
CPU time 68.96 seconds
Started Jul 23 06:24:37 PM PDT 24
Finished Jul 23 06:25:47 PM PDT 24
Peak memory 218768 kb
Host smart-207ea051-2def-4dae-8ca5-67a162efd8a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293097537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4293097537
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4260084032
Short name T120
Test name
Test status
Simulation time 9712712249 ps
CPU time 47.96 seconds
Started Jul 23 06:25:13 PM PDT 24
Finished Jul 23 06:26:04 PM PDT 24
Peak memory 212244 kb
Host smart-2b26c1fc-04e3-4082-85ab-47606c43cbfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260084032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4260084032
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.976708250
Short name T112
Test name
Test status
Simulation time 7278005493 ps
CPU time 14.44 seconds
Started Jul 23 06:24:42 PM PDT 24
Finished Jul 23 06:24:59 PM PDT 24
Peak memory 218884 kb
Host smart-6df47d8c-1d47-4fa9-be68-b69475c509f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976708250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.976708250
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1769727292
Short name T18
Test name
Test status
Simulation time 28257568813 ps
CPU time 1080.97 seconds
Started Jul 23 06:22:34 PM PDT 24
Finished Jul 23 06:40:49 PM PDT 24
Peak memory 230664 kb
Host smart-c4e182b3-3069-4349-b87b-8c4bb461178c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769727292 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1769727292
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3787292329
Short name T19
Test name
Test status
Simulation time 137288797933 ps
CPU time 1769.79 seconds
Started Jul 23 06:24:33 PM PDT 24
Finished Jul 23 06:54:04 PM PDT 24
Peak memory 231156 kb
Host smart-82a5209b-eb60-4db9-a9d3-992ac6430b8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787292329 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3787292329
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.210611756
Short name T1
Test name
Test status
Simulation time 1606493083 ps
CPU time 13.67 seconds
Started Jul 23 06:23:59 PM PDT 24
Finished Jul 23 06:24:14 PM PDT 24
Peak memory 211376 kb
Host smart-83759f78-af0b-4dfa-b3af-061ab1545357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210611756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.210611756
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1568491511
Short name T428
Test name
Test status
Simulation time 6082284901 ps
CPU time 12.88 seconds
Started Jul 23 06:24:42 PM PDT 24
Finished Jul 23 06:24:57 PM PDT 24
Peak memory 210592 kb
Host smart-59b1b992-d16d-4ed3-8cfc-59e911823843
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568491511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1568491511
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.456344968
Short name T414
Test name
Test status
Simulation time 2654531474 ps
CPU time 6.92 seconds
Started Jul 23 06:24:37 PM PDT 24
Finished Jul 23 06:24:45 PM PDT 24
Peak memory 210640 kb
Host smart-bb6f4049-2887-47fb-9efc-e11bd5f18ede
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456344968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.456344968
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.573313628
Short name T404
Test name
Test status
Simulation time 621382824 ps
CPU time 7.26 seconds
Started Jul 23 06:24:38 PM PDT 24
Finished Jul 23 06:24:47 PM PDT 24
Peak memory 210540 kb
Host smart-7f4d8ea9-d868-4230-81c2-84a2393ce793
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573313628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.573313628
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.73154496
Short name T440
Test name
Test status
Simulation time 542633992 ps
CPU time 7.32 seconds
Started Jul 23 06:24:39 PM PDT 24
Finished Jul 23 06:24:47 PM PDT 24
Peak memory 218888 kb
Host smart-9d7d12f3-d46b-4712-95df-4bba2b333fb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73154496 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.73154496
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2624997580
Short name T384
Test name
Test status
Simulation time 1747378133 ps
CPU time 14.7 seconds
Started Jul 23 06:24:38 PM PDT 24
Finished Jul 23 06:24:54 PM PDT 24
Peak memory 210556 kb
Host smart-3094c2a5-b97b-46d0-b602-00467be4b95f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624997580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2624997580
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.824229184
Short name T383
Test name
Test status
Simulation time 31906209671 ps
CPU time 13.4 seconds
Started Jul 23 06:24:38 PM PDT 24
Finished Jul 23 06:24:53 PM PDT 24
Peak memory 210544 kb
Host smart-0f36cde2-40a5-4409-a789-20d373d260eb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824229184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.824229184
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.268128009
Short name T386
Test name
Test status
Simulation time 1235517262 ps
CPU time 10.89 seconds
Started Jul 23 06:24:39 PM PDT 24
Finished Jul 23 06:24:52 PM PDT 24
Peak memory 210428 kb
Host smart-f5310efd-56da-4eba-9238-11aef79c1331
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268128009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
268128009
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3632955188
Short name T85
Test name
Test status
Simulation time 5120127829 ps
CPU time 48.41 seconds
Started Jul 23 06:24:39 PM PDT 24
Finished Jul 23 06:25:29 PM PDT 24
Peak memory 210740 kb
Host smart-b864e905-d763-4b6d-91bb-ac1bccfb5fbf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632955188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3632955188
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2056754650
Short name T439
Test name
Test status
Simulation time 4279636854 ps
CPU time 9.94 seconds
Started Jul 23 06:24:42 PM PDT 24
Finished Jul 23 06:24:54 PM PDT 24
Peak memory 218720 kb
Host smart-06d735c0-e8b2-4246-99d1-bb0672fdbbaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056754650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2056754650
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.688904808
Short name T389
Test name
Test status
Simulation time 742774407 ps
CPU time 13.01 seconds
Started Jul 23 06:24:40 PM PDT 24
Finished Jul 23 06:24:55 PM PDT 24
Peak memory 218800 kb
Host smart-544a668e-cfa6-4c18-b2c1-b8d19a680ef1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688904808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.688904808
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.123816160
Short name T379
Test name
Test status
Simulation time 4240237430 ps
CPU time 9.71 seconds
Started Jul 23 06:24:38 PM PDT 24
Finished Jul 23 06:24:49 PM PDT 24
Peak memory 218376 kb
Host smart-1605dbda-c972-4a41-a40f-aa54595ea0d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123816160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.123816160
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3118826478
Short name T460
Test name
Test status
Simulation time 5184622516 ps
CPU time 13.53 seconds
Started Jul 23 06:24:40 PM PDT 24
Finished Jul 23 06:24:55 PM PDT 24
Peak memory 218728 kb
Host smart-523e278b-dafa-4995-bdfb-ec2b59341fbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118826478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3118826478
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2960655906
Short name T423
Test name
Test status
Simulation time 3816728077 ps
CPU time 16.79 seconds
Started Jul 23 06:24:40 PM PDT 24
Finished Jul 23 06:24:59 PM PDT 24
Peak memory 210532 kb
Host smart-5371c6d8-8e2a-43a5-a1e2-332322b71124
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960655906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2960655906
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4204658288
Short name T435
Test name
Test status
Simulation time 8271144291 ps
CPU time 15.48 seconds
Started Jul 23 06:24:42 PM PDT 24
Finished Jul 23 06:25:00 PM PDT 24
Peak memory 218972 kb
Host smart-2f0bf757-f67a-4efc-9aa4-9af3c3862456
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204658288 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4204658288
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1043535016
Short name T409
Test name
Test status
Simulation time 1456123726 ps
CPU time 12.1 seconds
Started Jul 23 06:24:41 PM PDT 24
Finished Jul 23 06:24:56 PM PDT 24
Peak memory 210508 kb
Host smart-52cda87d-aff4-424f-8a2b-649406c07e28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043535016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1043535016
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1648785204
Short name T392
Test name
Test status
Simulation time 1568174053 ps
CPU time 8.12 seconds
Started Jul 23 06:24:40 PM PDT 24
Finished Jul 23 06:24:50 PM PDT 24
Peak memory 210432 kb
Host smart-77b57651-2f5b-42a2-9d36-fe84ca8a009b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648785204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1648785204
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1942178818
Short name T448
Test name
Test status
Simulation time 89170430 ps
CPU time 4.09 seconds
Started Jul 23 06:24:37 PM PDT 24
Finished Jul 23 06:24:43 PM PDT 24
Peak memory 210424 kb
Host smart-5e8ba124-c820-4ef3-b81f-3b976cc0da3b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942178818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1942178818
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3584632503
Short name T418
Test name
Test status
Simulation time 27952287881 ps
CPU time 55.23 seconds
Started Jul 23 06:24:40 PM PDT 24
Finished Jul 23 06:25:37 PM PDT 24
Peak memory 210684 kb
Host smart-a58057b1-b9f6-4700-915c-988e2de3afbd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584632503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3584632503
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4090917706
Short name T456
Test name
Test status
Simulation time 119576024 ps
CPU time 7.27 seconds
Started Jul 23 06:24:37 PM PDT 24
Finished Jul 23 06:24:46 PM PDT 24
Peak memory 215400 kb
Host smart-1535a757-2248-4a4e-a47f-11ee80de56eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090917706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4090917706
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.829262930
Short name T413
Test name
Test status
Simulation time 8665849217 ps
CPU time 16.52 seconds
Started Jul 23 06:24:59 PM PDT 24
Finished Jul 23 06:25:20 PM PDT 24
Peak memory 218892 kb
Host smart-bf7bcce1-4180-40f1-9231-c1e02c06d856
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829262930 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.829262930
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3424146067
Short name T71
Test name
Test status
Simulation time 1547307761 ps
CPU time 9.19 seconds
Started Jul 23 06:24:59 PM PDT 24
Finished Jul 23 06:25:12 PM PDT 24
Peak memory 210576 kb
Host smart-cda827be-e9e4-4f5d-a620-7bd24d3c156c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424146067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3424146067
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3260674356
Short name T399
Test name
Test status
Simulation time 2242541699 ps
CPU time 28.48 seconds
Started Jul 23 06:24:58 PM PDT 24
Finished Jul 23 06:25:30 PM PDT 24
Peak memory 210684 kb
Host smart-ffe6c96c-8ac6-4ada-a836-79df8d66121b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260674356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3260674356
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1138664639
Short name T397
Test name
Test status
Simulation time 4621247815 ps
CPU time 12.18 seconds
Started Jul 23 06:24:58 PM PDT 24
Finished Jul 23 06:25:14 PM PDT 24
Peak memory 210964 kb
Host smart-9c3a496a-d7b8-42bb-ae90-ea4d980ee8a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138664639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1138664639
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.454000771
Short name T433
Test name
Test status
Simulation time 1117981015 ps
CPU time 13.55 seconds
Started Jul 23 06:24:57 PM PDT 24
Finished Jul 23 06:25:14 PM PDT 24
Peak memory 218860 kb
Host smart-1e65d069-5f4a-4c07-a6e0-09a93531e24d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454000771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.454000771
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2427397176
Short name T445
Test name
Test status
Simulation time 415366238 ps
CPU time 38.94 seconds
Started Jul 23 06:24:58 PM PDT 24
Finished Jul 23 06:25:42 PM PDT 24
Peak memory 218748 kb
Host smart-aafd3e76-5e19-4ae8-ab39-b46394ed7e36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427397176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2427397176
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3650053845
Short name T400
Test name
Test status
Simulation time 4531695970 ps
CPU time 9.44 seconds
Started Jul 23 06:24:59 PM PDT 24
Finished Jul 23 06:25:12 PM PDT 24
Peak memory 212392 kb
Host smart-f2a62607-d4d4-4c9a-b874-e7826a56b35b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650053845 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3650053845
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2338060211
Short name T447
Test name
Test status
Simulation time 8002789797 ps
CPU time 12.03 seconds
Started Jul 23 06:24:57 PM PDT 24
Finished Jul 23 06:25:12 PM PDT 24
Peak memory 210660 kb
Host smart-41ebc72b-f2a5-4fd9-8607-5e4267ffa4fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338060211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2338060211
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.167069995
Short name T88
Test name
Test status
Simulation time 2223071652 ps
CPU time 26.95 seconds
Started Jul 23 06:24:59 PM PDT 24
Finished Jul 23 06:25:30 PM PDT 24
Peak memory 210664 kb
Host smart-29b0e496-3e93-46f0-bc40-1e8be538583b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167069995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.167069995
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.568766235
Short name T453
Test name
Test status
Simulation time 87172696 ps
CPU time 4.4 seconds
Started Jul 23 06:24:58 PM PDT 24
Finished Jul 23 06:25:07 PM PDT 24
Peak memory 210612 kb
Host smart-45deebfe-3ff7-4ddc-bd7d-c951355723ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568766235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.568766235
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2903990993
Short name T395
Test name
Test status
Simulation time 1194800040 ps
CPU time 15.39 seconds
Started Jul 23 06:24:59 PM PDT 24
Finished Jul 23 06:25:19 PM PDT 24
Peak memory 218716 kb
Host smart-1b88f3f1-8aa1-403e-9556-f9589ed17410
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903990993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2903990993
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3252352317
Short name T67
Test name
Test status
Simulation time 4704331551 ps
CPU time 45.77 seconds
Started Jul 23 06:24:58 PM PDT 24
Finished Jul 23 06:25:47 PM PDT 24
Peak memory 212332 kb
Host smart-d77957c6-dc68-471e-a12b-a504c6b30bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252352317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3252352317
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3206313695
Short name T385
Test name
Test status
Simulation time 1816611704 ps
CPU time 14.6 seconds
Started Jul 23 06:25:05 PM PDT 24
Finished Jul 23 06:25:24 PM PDT 24
Peak memory 218636 kb
Host smart-998f1507-2aee-4b72-99e4-9e52ed53f093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206313695 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3206313695
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2118699540
Short name T455
Test name
Test status
Simulation time 3509080278 ps
CPU time 10.01 seconds
Started Jul 23 06:24:58 PM PDT 24
Finished Jul 23 06:25:13 PM PDT 24
Peak memory 210608 kb
Host smart-80489593-ac0e-4619-b903-9011de3c3067
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118699540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2118699540
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.728269938
Short name T97
Test name
Test status
Simulation time 24775555006 ps
CPU time 96.1 seconds
Started Jul 23 06:24:57 PM PDT 24
Finished Jul 23 06:26:37 PM PDT 24
Peak memory 211788 kb
Host smart-0d676ed4-e399-44c1-a62e-6d2c0fd4d37c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728269938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.728269938
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3544852458
Short name T82
Test name
Test status
Simulation time 4275057729 ps
CPU time 16.15 seconds
Started Jul 23 06:25:04 PM PDT 24
Finished Jul 23 06:25:23 PM PDT 24
Peak memory 210708 kb
Host smart-242da9f2-c15c-4bcb-920d-a0b7cdd905d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544852458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3544852458
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2203990902
Short name T410
Test name
Test status
Simulation time 7545404928 ps
CPU time 19.52 seconds
Started Jul 23 06:24:58 PM PDT 24
Finished Jul 23 06:25:22 PM PDT 24
Peak memory 218912 kb
Host smart-a902ea3c-a1a2-4bf3-a5d7-976cbdbc7e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203990902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2203990902
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.519860728
Short name T125
Test name
Test status
Simulation time 1433480105 ps
CPU time 67.45 seconds
Started Jul 23 06:25:01 PM PDT 24
Finished Jul 23 06:26:11 PM PDT 24
Peak memory 218768 kb
Host smart-ece90012-62e8-41a6-935a-4ac8bc378b50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519860728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.519860728
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1224146615
Short name T374
Test name
Test status
Simulation time 103798368 ps
CPU time 5.03 seconds
Started Jul 23 06:25:05 PM PDT 24
Finished Jul 23 06:25:13 PM PDT 24
Peak memory 218812 kb
Host smart-b2c55822-277e-4c69-ae9c-39a913121562
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224146615 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1224146615
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.860533035
Short name T81
Test name
Test status
Simulation time 1687945617 ps
CPU time 14.26 seconds
Started Jul 23 06:25:07 PM PDT 24
Finished Jul 23 06:25:25 PM PDT 24
Peak memory 218704 kb
Host smart-bad8d96a-4dd4-4a57-adf7-97016b7729e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860533035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.860533035
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2245662649
Short name T73
Test name
Test status
Simulation time 27165562508 ps
CPU time 101.58 seconds
Started Jul 23 06:25:08 PM PDT 24
Finished Jul 23 06:26:53 PM PDT 24
Peak memory 210748 kb
Host smart-0fad0ffa-f48f-422e-8178-dc121e65ac97
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245662649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2245662649
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3660778508
Short name T110
Test name
Test status
Simulation time 2082348842 ps
CPU time 15.32 seconds
Started Jul 23 06:25:07 PM PDT 24
Finished Jul 23 06:25:26 PM PDT 24
Peak memory 210632 kb
Host smart-fbddd395-8428-46f9-8aed-8911b468ab48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660778508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3660778508
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2843782773
Short name T393
Test name
Test status
Simulation time 1484639817 ps
CPU time 17.2 seconds
Started Jul 23 06:25:06 PM PDT 24
Finished Jul 23 06:25:26 PM PDT 24
Peak memory 218828 kb
Host smart-7af02e92-5725-4b2a-bddb-de5946e087b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843782773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2843782773
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1461558442
Short name T123
Test name
Test status
Simulation time 836540159 ps
CPU time 39.93 seconds
Started Jul 23 06:25:04 PM PDT 24
Finished Jul 23 06:25:47 PM PDT 24
Peak memory 211924 kb
Host smart-367dc629-95d5-4e11-a1b0-7c5801261f90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461558442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1461558442
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1396667021
Short name T380
Test name
Test status
Simulation time 905800999 ps
CPU time 9.76 seconds
Started Jul 23 06:25:06 PM PDT 24
Finished Jul 23 06:25:19 PM PDT 24
Peak memory 218888 kb
Host smart-b3ac2e92-e5f2-4e22-a39a-1fd4751747a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396667021 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1396667021
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.503346357
Short name T402
Test name
Test status
Simulation time 5547428975 ps
CPU time 12.71 seconds
Started Jul 23 06:25:05 PM PDT 24
Finished Jul 23 06:25:21 PM PDT 24
Peak memory 218812 kb
Host smart-f82a5e73-24cd-404a-994a-54ffbb74b0e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503346357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.503346357
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1444358728
Short name T412
Test name
Test status
Simulation time 94902794380 ps
CPU time 63.14 seconds
Started Jul 23 06:25:05 PM PDT 24
Finished Jul 23 06:26:12 PM PDT 24
Peak memory 210644 kb
Host smart-4e765c7e-9a21-4318-8b50-13f6cca20177
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444358728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1444358728
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2314892839
Short name T111
Test name
Test status
Simulation time 820781913 ps
CPU time 9.57 seconds
Started Jul 23 06:25:06 PM PDT 24
Finished Jul 23 06:25:19 PM PDT 24
Peak memory 210604 kb
Host smart-70bfc59d-2d73-4f63-9d84-2c731f46b296
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314892839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2314892839
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.437551978
Short name T457
Test name
Test status
Simulation time 2747806894 ps
CPU time 16.74 seconds
Started Jul 23 06:25:05 PM PDT 24
Finished Jul 23 06:25:25 PM PDT 24
Peak memory 218872 kb
Host smart-bb492ffa-5075-4e0e-bb16-f965616bc2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437551978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.437551978
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1658762832
Short name T68
Test name
Test status
Simulation time 650050584 ps
CPU time 39.08 seconds
Started Jul 23 06:25:06 PM PDT 24
Finished Jul 23 06:25:49 PM PDT 24
Peak memory 218760 kb
Host smart-dcd796e7-f1b9-4232-bfc4-af13e9d223e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658762832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1658762832
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2360525611
Short name T72
Test name
Test status
Simulation time 1020766393 ps
CPU time 10.53 seconds
Started Jul 23 06:25:05 PM PDT 24
Finished Jul 23 06:25:19 PM PDT 24
Peak memory 218816 kb
Host smart-8f2779f0-2809-42b3-af91-705737e273f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360525611 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2360525611
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2683268911
Short name T425
Test name
Test status
Simulation time 1076260394 ps
CPU time 7.78 seconds
Started Jul 23 06:25:07 PM PDT 24
Finished Jul 23 06:25:18 PM PDT 24
Peak memory 210480 kb
Host smart-f79aa45c-4563-4758-bd12-d06457803253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683268911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2683268911
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.994337730
Short name T80
Test name
Test status
Simulation time 369970467 ps
CPU time 18.74 seconds
Started Jul 23 06:25:06 PM PDT 24
Finished Jul 23 06:25:28 PM PDT 24
Peak memory 210656 kb
Host smart-f87cfc6b-1c0a-4cb8-a43c-a2aca49a1d29
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994337730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.994337730
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1586556867
Short name T84
Test name
Test status
Simulation time 1636467153 ps
CPU time 13.64 seconds
Started Jul 23 06:25:04 PM PDT 24
Finished Jul 23 06:25:20 PM PDT 24
Peak memory 210564 kb
Host smart-08c0c20c-e046-4047-af84-74bf03c04890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586556867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1586556867
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2321720151
Short name T462
Test name
Test status
Simulation time 2063877939 ps
CPU time 12.88 seconds
Started Jul 23 06:25:07 PM PDT 24
Finished Jul 23 06:25:24 PM PDT 24
Peak memory 218776 kb
Host smart-3d9dc16b-aa5f-439f-8394-5e23cf56e5fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321720151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2321720151
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3102185162
Short name T131
Test name
Test status
Simulation time 724111766 ps
CPU time 35.98 seconds
Started Jul 23 06:25:04 PM PDT 24
Finished Jul 23 06:25:44 PM PDT 24
Peak memory 212036 kb
Host smart-57b40179-2be6-4c7d-9a9f-00d0c93cead2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102185162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3102185162
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4186454054
Short name T373
Test name
Test status
Simulation time 6170696747 ps
CPU time 13.69 seconds
Started Jul 23 06:25:12 PM PDT 24
Finished Jul 23 06:25:28 PM PDT 24
Peak memory 214372 kb
Host smart-9c6def13-5933-4769-8ee8-c2c0e0405ba7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186454054 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4186454054
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3526781767
Short name T115
Test name
Test status
Simulation time 93626303 ps
CPU time 4.26 seconds
Started Jul 23 06:25:14 PM PDT 24
Finished Jul 23 06:25:21 PM PDT 24
Peak memory 210576 kb
Host smart-1b7e1487-d76f-49b3-b441-24822aa2521c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526781767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3526781767
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1496106457
Short name T107
Test name
Test status
Simulation time 3570391025 ps
CPU time 15.13 seconds
Started Jul 23 06:25:14 PM PDT 24
Finished Jul 23 06:25:32 PM PDT 24
Peak memory 218148 kb
Host smart-d8baa39d-c6b0-4f5f-a552-fcfefed85897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496106457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1496106457
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.883574901
Short name T452
Test name
Test status
Simulation time 1974430940 ps
CPU time 20.14 seconds
Started Jul 23 06:25:16 PM PDT 24
Finished Jul 23 06:25:38 PM PDT 24
Peak memory 218808 kb
Host smart-1dc3e508-6253-4784-bcf4-133bfcfd28e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883574901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.883574901
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.476600429
Short name T119
Test name
Test status
Simulation time 2934755850 ps
CPU time 41.89 seconds
Started Jul 23 06:25:13 PM PDT 24
Finished Jul 23 06:25:57 PM PDT 24
Peak memory 218808 kb
Host smart-d1fbe6a1-80ef-4f88-9067-37fcec5fabb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476600429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.476600429
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2806040094
Short name T405
Test name
Test status
Simulation time 668763111 ps
CPU time 8.27 seconds
Started Jul 23 06:25:13 PM PDT 24
Finished Jul 23 06:25:24 PM PDT 24
Peak memory 218772 kb
Host smart-9cf5fa61-d8f5-4f82-862a-d5349b23cdc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806040094 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2806040094
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.378107862
Short name T90
Test name
Test status
Simulation time 1810655705 ps
CPU time 7.09 seconds
Started Jul 23 06:25:15 PM PDT 24
Finished Jul 23 06:25:24 PM PDT 24
Peak memory 210552 kb
Host smart-bf3b601e-0ebc-4550-b95c-ad85302bbd78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378107862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.378107862
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3427940042
Short name T91
Test name
Test status
Simulation time 551383316 ps
CPU time 27.75 seconds
Started Jul 23 06:25:13 PM PDT 24
Finished Jul 23 06:25:43 PM PDT 24
Peak memory 210564 kb
Host smart-1b5ca06c-42cd-4278-9f31-c1ee38fd7ae7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427940042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3427940042
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4210757809
Short name T432
Test name
Test status
Simulation time 335046577 ps
CPU time 6.57 seconds
Started Jul 23 06:25:13 PM PDT 24
Finished Jul 23 06:25:23 PM PDT 24
Peak memory 217840 kb
Host smart-41d550c3-ddc1-468b-b8e4-9d0498236ba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210757809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4210757809
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2060525849
Short name T382
Test name
Test status
Simulation time 105669472 ps
CPU time 8.23 seconds
Started Jul 23 06:25:13 PM PDT 24
Finished Jul 23 06:25:24 PM PDT 24
Peak memory 218820 kb
Host smart-ea85a003-8bb3-4e43-852b-06fead7c1d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060525849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2060525849
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2790419206
Short name T443
Test name
Test status
Simulation time 1919333920 ps
CPU time 15.74 seconds
Started Jul 23 06:25:19 PM PDT 24
Finished Jul 23 06:25:36 PM PDT 24
Peak memory 218824 kb
Host smart-80b21b2b-aa53-49ed-8d60-30c9bc071f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790419206 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2790419206
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3567753518
Short name T95
Test name
Test status
Simulation time 1719588871 ps
CPU time 14.83 seconds
Started Jul 23 06:25:14 PM PDT 24
Finished Jul 23 06:25:31 PM PDT 24
Peak memory 218712 kb
Host smart-89e389c1-65fd-4b29-bc0f-46d157eb9556
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567753518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3567753518
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3342986929
Short name T441
Test name
Test status
Simulation time 58308680705 ps
CPU time 67.4 seconds
Started Jul 23 06:25:13 PM PDT 24
Finished Jul 23 06:26:22 PM PDT 24
Peak memory 210748 kb
Host smart-5bc7d10d-0b85-481f-a065-9211b1f1ff70
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342986929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3342986929
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.175625298
Short name T109
Test name
Test status
Simulation time 1380488016 ps
CPU time 11.57 seconds
Started Jul 23 06:25:20 PM PDT 24
Finished Jul 23 06:25:34 PM PDT 24
Peak memory 210644 kb
Host smart-dbdb7d5d-b3fc-4820-8147-cb06ccd7de9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175625298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.175625298
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2053640980
Short name T431
Test name
Test status
Simulation time 1530978431 ps
CPU time 11.26 seconds
Started Jul 23 06:25:13 PM PDT 24
Finished Jul 23 06:25:27 PM PDT 24
Peak memory 218828 kb
Host smart-9cfda46f-df90-45a0-9b0f-f11fc909ddd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053640980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2053640980
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.331272884
Short name T127
Test name
Test status
Simulation time 5576607431 ps
CPU time 46.97 seconds
Started Jul 23 06:25:12 PM PDT 24
Finished Jul 23 06:26:01 PM PDT 24
Peak memory 211916 kb
Host smart-bd598290-3ab7-46bf-926e-d90dfd46c004
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331272884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.331272884
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2320962319
Short name T377
Test name
Test status
Simulation time 1965986609 ps
CPU time 15.26 seconds
Started Jul 23 06:25:20 PM PDT 24
Finished Jul 23 06:25:40 PM PDT 24
Peak memory 218852 kb
Host smart-075f9271-06c4-4b28-8d0c-f38e855edf8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320962319 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2320962319
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4187509997
Short name T86
Test name
Test status
Simulation time 828259825 ps
CPU time 9.41 seconds
Started Jul 23 06:25:20 PM PDT 24
Finished Jul 23 06:25:32 PM PDT 24
Peak memory 210512 kb
Host smart-79c40a4d-43be-4424-87ab-9c91790520ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187509997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4187509997
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1422691007
Short name T87
Test name
Test status
Simulation time 21938741353 ps
CPU time 63.79 seconds
Started Jul 23 06:25:21 PM PDT 24
Finished Jul 23 06:26:31 PM PDT 24
Peak memory 210728 kb
Host smart-31cbd728-82d3-477c-a720-dac091751d2b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422691007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1422691007
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1834177102
Short name T113
Test name
Test status
Simulation time 16947087503 ps
CPU time 13.9 seconds
Started Jul 23 06:25:21 PM PDT 24
Finished Jul 23 06:25:40 PM PDT 24
Peak memory 218896 kb
Host smart-543afaee-ed86-4d57-be4e-5487b086818a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834177102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1834177102
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.283892687
Short name T442
Test name
Test status
Simulation time 9313403742 ps
CPU time 12.69 seconds
Started Jul 23 06:25:20 PM PDT 24
Finished Jul 23 06:25:37 PM PDT 24
Peak memory 218908 kb
Host smart-4cb8048c-1911-449d-b0e6-b14f038af69f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283892687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.283892687
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3820484843
Short name T114
Test name
Test status
Simulation time 347022733 ps
CPU time 4.84 seconds
Started Jul 23 06:24:43 PM PDT 24
Finished Jul 23 06:24:50 PM PDT 24
Peak memory 210576 kb
Host smart-71533eeb-e333-4878-a8bd-3dca1c14bdb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820484843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3820484843
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1942424676
Short name T92
Test name
Test status
Simulation time 434515577 ps
CPU time 7.26 seconds
Started Jul 23 06:24:40 PM PDT 24
Finished Jul 23 06:24:49 PM PDT 24
Peak memory 210512 kb
Host smart-5aa48614-ffa0-4008-9188-a532b88c33e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942424676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1942424676
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1724583481
Short name T415
Test name
Test status
Simulation time 4293951928 ps
CPU time 10.53 seconds
Started Jul 23 06:24:44 PM PDT 24
Finished Jul 23 06:24:58 PM PDT 24
Peak memory 212872 kb
Host smart-1db9c907-779e-4a98-a72b-cb1730bd02c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724583481 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1724583481
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3225874058
Short name T422
Test name
Test status
Simulation time 6719445248 ps
CPU time 14.1 seconds
Started Jul 23 06:24:38 PM PDT 24
Finished Jul 23 06:24:53 PM PDT 24
Peak memory 210732 kb
Host smart-c2c3464e-c82b-45da-9664-0a952a62750d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225874058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3225874058
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2147789901
Short name T406
Test name
Test status
Simulation time 3754317074 ps
CPU time 9.68 seconds
Started Jul 23 06:24:42 PM PDT 24
Finished Jul 23 06:24:54 PM PDT 24
Peak memory 210484 kb
Host smart-b684b1e0-9bae-4a45-bf10-392d4b2e2f2f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147789901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2147789901
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3932260704
Short name T391
Test name
Test status
Simulation time 1976623607 ps
CPU time 10.05 seconds
Started Jul 23 06:24:40 PM PDT 24
Finished Jul 23 06:24:51 PM PDT 24
Peak memory 210376 kb
Host smart-8d3d7fb5-7c83-4204-840d-cba0b6e356fa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932260704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3932260704
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.307038267
Short name T466
Test name
Test status
Simulation time 30781242410 ps
CPU time 61.28 seconds
Started Jul 23 06:24:39 PM PDT 24
Finished Jul 23 06:25:41 PM PDT 24
Peak memory 210676 kb
Host smart-4cf6d469-77e9-41c8-afa0-bd6cfc43f99d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307038267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.307038267
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3734137105
Short name T416
Test name
Test status
Simulation time 306611356 ps
CPU time 6.41 seconds
Started Jul 23 06:24:43 PM PDT 24
Finished Jul 23 06:24:52 PM PDT 24
Peak memory 210644 kb
Host smart-c8feedf3-2019-471c-9577-fc99992c7228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734137105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3734137105
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4203684221
Short name T454
Test name
Test status
Simulation time 1976325013 ps
CPU time 19.18 seconds
Started Jul 23 06:24:40 PM PDT 24
Finished Jul 23 06:25:01 PM PDT 24
Peak memory 218732 kb
Host smart-cf2e049d-ed7c-45eb-bca9-082e55d0ba9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203684221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4203684221
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1181191408
Short name T444
Test name
Test status
Simulation time 158135675 ps
CPU time 37.27 seconds
Started Jul 23 06:24:38 PM PDT 24
Finished Jul 23 06:25:17 PM PDT 24
Peak memory 211060 kb
Host smart-c260890f-b962-49ca-98ab-bfbc1276c5b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181191408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1181191408
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3942143317
Short name T426
Test name
Test status
Simulation time 472508759 ps
CPU time 6.92 seconds
Started Jul 23 06:24:47 PM PDT 24
Finished Jul 23 06:24:56 PM PDT 24
Peak memory 217572 kb
Host smart-ca19093a-5e3c-4f69-a1aa-77a3f629a296
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942143317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3942143317
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1415086537
Short name T387
Test name
Test status
Simulation time 351233290 ps
CPU time 5.76 seconds
Started Jul 23 06:24:45 PM PDT 24
Finished Jul 23 06:24:53 PM PDT 24
Peak memory 217120 kb
Host smart-492996ff-e91c-48ac-b70c-cf0e6319353a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415086537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1415086537
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2076488398
Short name T83
Test name
Test status
Simulation time 7767081993 ps
CPU time 18.01 seconds
Started Jul 23 06:24:44 PM PDT 24
Finished Jul 23 06:25:05 PM PDT 24
Peak memory 218672 kb
Host smart-186474c3-51d5-47ce-bb31-f495c30974b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076488398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2076488398
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2235061615
Short name T381
Test name
Test status
Simulation time 6491190428 ps
CPU time 13.3 seconds
Started Jul 23 06:24:44 PM PDT 24
Finished Jul 23 06:25:00 PM PDT 24
Peak memory 218948 kb
Host smart-b51a4275-e4bc-4e36-a6ed-9429066aea90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235061615 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2235061615
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3361638660
Short name T461
Test name
Test status
Simulation time 18428873951 ps
CPU time 11.27 seconds
Started Jul 23 06:24:44 PM PDT 24
Finished Jul 23 06:24:58 PM PDT 24
Peak memory 217888 kb
Host smart-5af64433-ff43-4050-9da1-1dccf5c040dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361638660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3361638660
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2312873953
Short name T411
Test name
Test status
Simulation time 12275376576 ps
CPU time 12.19 seconds
Started Jul 23 06:24:43 PM PDT 24
Finished Jul 23 06:24:58 PM PDT 24
Peak memory 210548 kb
Host smart-ea80345a-9876-4053-8229-2af89f1d66cf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312873953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2312873953
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.655895341
Short name T378
Test name
Test status
Simulation time 86694185 ps
CPU time 4.19 seconds
Started Jul 23 06:24:43 PM PDT 24
Finished Jul 23 06:24:49 PM PDT 24
Peak memory 210400 kb
Host smart-8cfba58e-3014-45b0-bc10-1bc131d98b5b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655895341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
655895341
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.772275970
Short name T436
Test name
Test status
Simulation time 8702757158 ps
CPU time 68.56 seconds
Started Jul 23 06:24:43 PM PDT 24
Finished Jul 23 06:25:55 PM PDT 24
Peak memory 210752 kb
Host smart-827096a9-f85d-4c74-b755-a9eab673fa93
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772275970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.772275970
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2423856214
Short name T420
Test name
Test status
Simulation time 346308168 ps
CPU time 4.18 seconds
Started Jul 23 06:24:44 PM PDT 24
Finished Jul 23 06:24:52 PM PDT 24
Peak memory 218140 kb
Host smart-fb809378-f9f4-4dae-bb52-705b39a276c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423856214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2423856214
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3083345135
Short name T407
Test name
Test status
Simulation time 8267057094 ps
CPU time 19.52 seconds
Started Jul 23 06:24:44 PM PDT 24
Finished Jul 23 06:25:07 PM PDT 24
Peak memory 218904 kb
Host smart-9ec3acf0-7b5d-49f6-9200-d456fdf541da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083345135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3083345135
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2572797287
Short name T398
Test name
Test status
Simulation time 1917498193 ps
CPU time 14.71 seconds
Started Jul 23 06:24:43 PM PDT 24
Finished Jul 23 06:25:01 PM PDT 24
Peak memory 210492 kb
Host smart-36dd565b-5523-454f-ba17-34acd6cfc1e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572797287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2572797287
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.127319053
Short name T390
Test name
Test status
Simulation time 1158505205 ps
CPU time 10.45 seconds
Started Jul 23 06:24:47 PM PDT 24
Finished Jul 23 06:25:00 PM PDT 24
Peak memory 217420 kb
Host smart-fc615384-1a65-4294-b129-a6d9c68e7fb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127319053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.127319053
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2742192546
Short name T451
Test name
Test status
Simulation time 299946486 ps
CPU time 9.31 seconds
Started Jul 23 06:24:45 PM PDT 24
Finished Jul 23 06:24:57 PM PDT 24
Peak memory 218424 kb
Host smart-d6a4215d-e48a-4e30-b0e0-7e368e644907
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742192546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2742192546
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2282021360
Short name T388
Test name
Test status
Simulation time 2033268307 ps
CPU time 8.05 seconds
Started Jul 23 06:24:45 PM PDT 24
Finished Jul 23 06:24:56 PM PDT 24
Peak memory 218788 kb
Host smart-2f2023ad-14cb-4a79-91f4-d463f614b0e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282021360 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2282021360
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4277807161
Short name T79
Test name
Test status
Simulation time 590523900 ps
CPU time 7.91 seconds
Started Jul 23 06:24:44 PM PDT 24
Finished Jul 23 06:24:55 PM PDT 24
Peak memory 210576 kb
Host smart-57b34da1-4f1e-4e72-8c94-2c5d9a09893e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277807161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4277807161
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1774997690
Short name T438
Test name
Test status
Simulation time 2870608534 ps
CPU time 9.45 seconds
Started Jul 23 06:24:46 PM PDT 24
Finished Jul 23 06:24:58 PM PDT 24
Peak memory 210484 kb
Host smart-697eda53-e15a-482e-b669-196db9714120
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774997690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1774997690
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2555759365
Short name T421
Test name
Test status
Simulation time 1228748390 ps
CPU time 10.98 seconds
Started Jul 23 06:24:45 PM PDT 24
Finished Jul 23 06:24:59 PM PDT 24
Peak memory 210424 kb
Host smart-a74e207d-5c8a-4208-bf5b-288e84fbefa8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555759365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2555759365
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3026080778
Short name T96
Test name
Test status
Simulation time 3503270895 ps
CPU time 49.97 seconds
Started Jul 23 06:24:44 PM PDT 24
Finished Jul 23 06:25:37 PM PDT 24
Peak memory 210780 kb
Host smart-eb4ecd57-69a8-44e8-909a-f5404a107784
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026080778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3026080778
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3216823734
Short name T427
Test name
Test status
Simulation time 7829478599 ps
CPU time 15.07 seconds
Started Jul 23 06:24:47 PM PDT 24
Finished Jul 23 06:25:04 PM PDT 24
Peak memory 210748 kb
Host smart-e435027b-ac1c-4c08-8d9d-2f9e9de2f9eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216823734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3216823734
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2200179815
Short name T430
Test name
Test status
Simulation time 261951928 ps
CPU time 9.21 seconds
Started Jul 23 06:24:44 PM PDT 24
Finished Jul 23 06:24:56 PM PDT 24
Peak memory 218828 kb
Host smart-adb72125-cbfd-4f28-b667-50000526a231
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200179815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2200179815
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3548221859
Short name T130
Test name
Test status
Simulation time 12625777974 ps
CPU time 45.61 seconds
Started Jul 23 06:24:47 PM PDT 24
Finished Jul 23 06:25:35 PM PDT 24
Peak memory 212408 kb
Host smart-429afc28-9428-4f6e-8486-9b2efdcf3362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548221859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3548221859
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2374813724
Short name T463
Test name
Test status
Simulation time 14306592179 ps
CPU time 14.14 seconds
Started Jul 23 06:24:50 PM PDT 24
Finished Jul 23 06:25:05 PM PDT 24
Peak memory 213920 kb
Host smart-62b9bcbb-3a36-403f-9406-e9f30c7add96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374813724 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2374813724
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.491277576
Short name T89
Test name
Test status
Simulation time 3040920356 ps
CPU time 12.41 seconds
Started Jul 23 06:24:50 PM PDT 24
Finished Jul 23 06:25:03 PM PDT 24
Peak memory 218780 kb
Host smart-1e794a5c-c313-4f20-b577-3d8013dbf371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491277576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.491277576
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3046877169
Short name T419
Test name
Test status
Simulation time 9647928461 ps
CPU time 81.19 seconds
Started Jul 23 06:24:45 PM PDT 24
Finished Jul 23 06:26:09 PM PDT 24
Peak memory 211748 kb
Host smart-69b1a928-02d1-48bb-9013-30a453bdcff5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046877169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3046877169
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2815115044
Short name T467
Test name
Test status
Simulation time 178555537 ps
CPU time 4.25 seconds
Started Jul 23 06:24:50 PM PDT 24
Finished Jul 23 06:24:56 PM PDT 24
Peak memory 210652 kb
Host smart-3e6c8132-eaae-429f-809c-4c4cf02e446a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815115044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2815115044
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3370364285
Short name T376
Test name
Test status
Simulation time 3744552926 ps
CPU time 18.34 seconds
Started Jul 23 06:24:51 PM PDT 24
Finished Jul 23 06:25:12 PM PDT 24
Peak memory 218860 kb
Host smart-bb783fe0-04b4-459b-bbf0-0665aad2f7d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370364285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3370364285
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4190325274
Short name T128
Test name
Test status
Simulation time 2289971409 ps
CPU time 42.19 seconds
Started Jul 23 06:24:50 PM PDT 24
Finished Jul 23 06:25:33 PM PDT 24
Peak memory 212096 kb
Host smart-232a0829-d541-4ac9-ae22-25798125aaba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190325274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4190325274
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1861587561
Short name T396
Test name
Test status
Simulation time 357329898 ps
CPU time 4.48 seconds
Started Jul 23 06:24:51 PM PDT 24
Finished Jul 23 06:24:57 PM PDT 24
Peak memory 218792 kb
Host smart-346d1355-5332-49f4-8a76-900d1c4dd8b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861587561 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1861587561
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3366764420
Short name T449
Test name
Test status
Simulation time 1975176575 ps
CPU time 15.04 seconds
Started Jul 23 06:24:51 PM PDT 24
Finished Jul 23 06:25:09 PM PDT 24
Peak memory 218320 kb
Host smart-c6911890-1d02-460b-921a-7633ace9fb58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366764420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3366764420
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1202943499
Short name T401
Test name
Test status
Simulation time 725266564 ps
CPU time 19 seconds
Started Jul 23 06:24:52 PM PDT 24
Finished Jul 23 06:25:13 PM PDT 24
Peak memory 210644 kb
Host smart-72b740f4-7076-4288-8a48-3cbe8297c8b3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202943499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1202943499
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3364726317
Short name T417
Test name
Test status
Simulation time 901660109 ps
CPU time 11.33 seconds
Started Jul 23 06:24:52 PM PDT 24
Finished Jul 23 06:25:06 PM PDT 24
Peak memory 210632 kb
Host smart-69edf899-118e-4f4e-a202-1a7df50ae44a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364726317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3364726317
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1806526874
Short name T375
Test name
Test status
Simulation time 5842087254 ps
CPU time 17.01 seconds
Started Jul 23 06:24:51 PM PDT 24
Finished Jul 23 06:25:10 PM PDT 24
Peak memory 215848 kb
Host smart-e4347d0a-ac68-46ce-9389-ca09e5b788ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806526874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1806526874
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3418140118
Short name T124
Test name
Test status
Simulation time 2332421745 ps
CPU time 78.26 seconds
Started Jul 23 06:24:50 PM PDT 24
Finished Jul 23 06:26:10 PM PDT 24
Peak memory 218804 kb
Host smart-d0b96e01-dbb7-45c0-a6e0-9fac3ed7311e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418140118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3418140118
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3404736099
Short name T372
Test name
Test status
Simulation time 4262795596 ps
CPU time 12.73 seconds
Started Jul 23 06:24:51 PM PDT 24
Finished Jul 23 06:25:07 PM PDT 24
Peak memory 218856 kb
Host smart-2629de6f-f336-4e2c-ae1c-466458e52058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404736099 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3404736099
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1367793036
Short name T459
Test name
Test status
Simulation time 5144815568 ps
CPU time 8.16 seconds
Started Jul 23 06:24:52 PM PDT 24
Finished Jul 23 06:25:03 PM PDT 24
Peak memory 218780 kb
Host smart-443270ca-dbbe-4075-bf0f-d67dacaa1085
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367793036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1367793036
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3519135298
Short name T458
Test name
Test status
Simulation time 607358414 ps
CPU time 18.74 seconds
Started Jul 23 06:24:52 PM PDT 24
Finished Jul 23 06:25:14 PM PDT 24
Peak memory 210600 kb
Host smart-50e7a9ad-aa6e-4c2d-a263-0a5277449f96
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519135298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3519135298
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.141651112
Short name T108
Test name
Test status
Simulation time 598818772 ps
CPU time 9.67 seconds
Started Jul 23 06:24:52 PM PDT 24
Finished Jul 23 06:25:05 PM PDT 24
Peak memory 210736 kb
Host smart-0bfb738a-7d84-48cf-9fc4-02026b0210de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141651112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.141651112
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.228806345
Short name T408
Test name
Test status
Simulation time 7195394604 ps
CPU time 19.71 seconds
Started Jul 23 06:24:49 PM PDT 24
Finished Jul 23 06:25:10 PM PDT 24
Peak memory 215000 kb
Host smart-5294de4a-291a-45ec-9cb1-12b54df7fd79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228806345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.228806345
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1992369395
Short name T121
Test name
Test status
Simulation time 796524947 ps
CPU time 69.79 seconds
Started Jul 23 06:24:50 PM PDT 24
Finished Jul 23 06:26:01 PM PDT 24
Peak memory 213176 kb
Host smart-84b50b53-519c-4334-9028-e9fa31e6a273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992369395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1992369395
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1787355256
Short name T434
Test name
Test status
Simulation time 3113646187 ps
CPU time 9.51 seconds
Started Jul 23 06:24:59 PM PDT 24
Finished Jul 23 06:25:13 PM PDT 24
Peak memory 218920 kb
Host smart-57cc6acf-063b-4f5a-8278-3d0be85c2ec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787355256 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1787355256
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1186345161
Short name T94
Test name
Test status
Simulation time 1691772322 ps
CPU time 14.4 seconds
Started Jul 23 06:24:59 PM PDT 24
Finished Jul 23 06:25:18 PM PDT 24
Peak memory 218692 kb
Host smart-1ff83351-d685-4a83-8bbf-1ea075390a75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186345161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1186345161
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2866598851
Short name T117
Test name
Test status
Simulation time 4196908259 ps
CPU time 42.8 seconds
Started Jul 23 06:24:51 PM PDT 24
Finished Jul 23 06:25:37 PM PDT 24
Peak memory 210780 kb
Host smart-46b5a2b7-1a7d-4da9-990f-9e9945354e2d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866598851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2866598851
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2343877321
Short name T424
Test name
Test status
Simulation time 1068182122 ps
CPU time 10.38 seconds
Started Jul 23 06:24:57 PM PDT 24
Finished Jul 23 06:25:10 PM PDT 24
Peak memory 210560 kb
Host smart-ec9f58c2-557f-40e7-a206-e58c53cf33a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343877321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2343877321
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.511021317
Short name T450
Test name
Test status
Simulation time 1527780083 ps
CPU time 15.32 seconds
Started Jul 23 06:24:51 PM PDT 24
Finished Jul 23 06:25:08 PM PDT 24
Peak memory 218768 kb
Host smart-ec14aa81-4c00-4a5b-89f1-f35bd2947835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511021317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.511021317
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2797170355
Short name T446
Test name
Test status
Simulation time 1977356513 ps
CPU time 37.85 seconds
Started Jul 23 06:24:52 PM PDT 24
Finished Jul 23 06:25:32 PM PDT 24
Peak memory 218748 kb
Host smart-35c547d0-6924-46bc-9757-a43d320f97bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797170355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2797170355
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.487882684
Short name T429
Test name
Test status
Simulation time 3034421743 ps
CPU time 6.16 seconds
Started Jul 23 06:24:57 PM PDT 24
Finished Jul 23 06:25:05 PM PDT 24
Peak memory 218880 kb
Host smart-02b3bbf2-afe8-4ad5-b632-2029a2959a8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487882684 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.487882684
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3454935652
Short name T437
Test name
Test status
Simulation time 2122545633 ps
CPU time 10.49 seconds
Started Jul 23 06:24:58 PM PDT 24
Finished Jul 23 06:25:12 PM PDT 24
Peak memory 210512 kb
Host smart-8f97b025-9f7b-4bf4-8733-a9bc5e1efb6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454935652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3454935652
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.285658324
Short name T464
Test name
Test status
Simulation time 1348153076 ps
CPU time 36.3 seconds
Started Jul 23 06:24:58 PM PDT 24
Finished Jul 23 06:25:39 PM PDT 24
Peak memory 210588 kb
Host smart-d8abbfa9-711e-4b07-9835-8485378d8826
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285658324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.285658324
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1462469656
Short name T394
Test name
Test status
Simulation time 628615678 ps
CPU time 9.9 seconds
Started Jul 23 06:24:58 PM PDT 24
Finished Jul 23 06:25:11 PM PDT 24
Peak memory 218784 kb
Host smart-5c1d9298-655e-433d-ba51-ef770bfd1145
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462469656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1462469656
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.164282583
Short name T403
Test name
Test status
Simulation time 25271637453 ps
CPU time 15.67 seconds
Started Jul 23 06:24:57 PM PDT 24
Finished Jul 23 06:25:15 PM PDT 24
Peak memory 218820 kb
Host smart-d0c6d936-d617-43a1-baa5-d0d50d28efb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164282583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.164282583
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.33956117
Short name T465
Test name
Test status
Simulation time 1348949440 ps
CPU time 68.34 seconds
Started Jul 23 06:24:59 PM PDT 24
Finished Jul 23 06:26:12 PM PDT 24
Peak memory 212104 kb
Host smart-b34732fc-55fc-47f4-a031-0fb751f48942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33956117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg
_err.33956117
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2890937673
Short name T345
Test name
Test status
Simulation time 87172747 ps
CPU time 4.37 seconds
Started Jul 23 06:22:33 PM PDT 24
Finished Jul 23 06:22:52 PM PDT 24
Peak memory 211380 kb
Host smart-ee165a5c-3bf3-4f1a-b93f-04db28b01bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890937673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2890937673
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3006936795
Short name T371
Test name
Test status
Simulation time 2061837038 ps
CPU time 64.93 seconds
Started Jul 23 06:22:33 PM PDT 24
Finished Jul 23 06:23:52 PM PDT 24
Peak memory 212624 kb
Host smart-99385957-64ae-469a-a053-2aba2793f4b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006936795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3006936795
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2078601155
Short name T340
Test name
Test status
Simulation time 4100774998 ps
CPU time 35.66 seconds
Started Jul 23 06:22:36 PM PDT 24
Finished Jul 23 06:23:28 PM PDT 24
Peak memory 212028 kb
Host smart-470918d8-de30-4bab-a763-c7b3aa86a7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078601155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2078601155
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1790181826
Short name T353
Test name
Test status
Simulation time 3914447896 ps
CPU time 14.41 seconds
Started Jul 23 06:22:32 PM PDT 24
Finished Jul 23 06:23:00 PM PDT 24
Peak memory 211472 kb
Host smart-fd9d8b36-590e-454b-8dfa-57d871b762aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790181826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1790181826
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1971285363
Short name T27
Test name
Test status
Simulation time 1931440543 ps
CPU time 111.17 seconds
Started Jul 23 06:22:32 PM PDT 24
Finished Jul 23 06:24:37 PM PDT 24
Peak memory 236736 kb
Host smart-47dc37c0-eadc-4b46-af64-01bdb374aad6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971285363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1971285363
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.379295362
Short name T155
Test name
Test status
Simulation time 3163466027 ps
CPU time 14.81 seconds
Started Jul 23 06:22:33 PM PDT 24
Finished Jul 23 06:23:02 PM PDT 24
Peak memory 212172 kb
Host smart-3a04b6fa-3cd1-460d-b23a-c2e4e08a6e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379295362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.379295362
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2470896148
Short name T135
Test name
Test status
Simulation time 27961477106 ps
CPU time 78.09 seconds
Started Jul 23 06:22:32 PM PDT 24
Finished Jul 23 06:24:04 PM PDT 24
Peak memory 216200 kb
Host smart-bb32d1b2-91b4-468d-a7fe-d3f6b2de49ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470896148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2470896148
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4081201784
Short name T152
Test name
Test status
Simulation time 348081416 ps
CPU time 4.27 seconds
Started Jul 23 06:22:49 PM PDT 24
Finished Jul 23 06:23:12 PM PDT 24
Peak memory 211324 kb
Host smart-966192d9-da75-41e4-b232-2458f2ad1cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081201784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4081201784
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1633799442
Short name T301
Test name
Test status
Simulation time 25736927515 ps
CPU time 271.45 seconds
Started Jul 23 06:22:40 PM PDT 24
Finished Jul 23 06:27:29 PM PDT 24
Peak memory 234088 kb
Host smart-831d8625-c7b8-4c56-aa53-cb3c562442ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633799442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1633799442
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2994813802
Short name T322
Test name
Test status
Simulation time 2985773701 ps
CPU time 25.16 seconds
Started Jul 23 06:22:40 PM PDT 24
Finished Jul 23 06:23:23 PM PDT 24
Peak memory 211948 kb
Host smart-1a33623a-04bc-478e-ab31-3da73d306a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994813802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2994813802
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3902890496
Short name T288
Test name
Test status
Simulation time 4425582369 ps
CPU time 16.9 seconds
Started Jul 23 06:22:48 PM PDT 24
Finished Jul 23 06:23:25 PM PDT 24
Peak memory 211448 kb
Host smart-df774f0e-103e-435f-b35f-3c06ad6544aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902890496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3902890496
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4110068968
Short name T262
Test name
Test status
Simulation time 367288599 ps
CPU time 10 seconds
Started Jul 23 06:22:36 PM PDT 24
Finished Jul 23 06:23:03 PM PDT 24
Peak memory 213172 kb
Host smart-a15a5a2f-8b2f-4a51-bc3e-3432d821346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110068968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4110068968
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2699802676
Short name T287
Test name
Test status
Simulation time 801548714 ps
CPU time 8.3 seconds
Started Jul 23 06:22:34 PM PDT 24
Finished Jul 23 06:22:57 PM PDT 24
Peak memory 211280 kb
Host smart-a8a6f8ec-c665-4eb1-95c2-970fb1cb7615
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699802676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2699802676
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3861382737
Short name T294
Test name
Test status
Simulation time 40220747262 ps
CPU time 378.54 seconds
Started Jul 23 06:22:47 PM PDT 24
Finished Jul 23 06:29:24 PM PDT 24
Peak memory 226468 kb
Host smart-6db7370a-0075-4063-bdbd-8c87fd038004
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861382737 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3861382737
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2255459206
Short name T172
Test name
Test status
Simulation time 3573964131 ps
CPU time 14.69 seconds
Started Jul 23 06:23:02 PM PDT 24
Finished Jul 23 06:23:33 PM PDT 24
Peak memory 211436 kb
Host smart-f22a4e66-9235-46b9-b300-74933032dc5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255459206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2255459206
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3151272137
Short name T350
Test name
Test status
Simulation time 52219780482 ps
CPU time 421.06 seconds
Started Jul 23 06:23:02 PM PDT 24
Finished Jul 23 06:30:19 PM PDT 24
Peak memory 234920 kb
Host smart-072d2f79-87a7-46b0-ae09-2556e8699ed6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151272137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3151272137
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2348169263
Short name T223
Test name
Test status
Simulation time 168466977 ps
CPU time 9.35 seconds
Started Jul 23 06:23:05 PM PDT 24
Finished Jul 23 06:23:29 PM PDT 24
Peak memory 211988 kb
Host smart-0e821892-3d32-469b-9a1a-7d65748fb83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348169263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2348169263
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4294067245
Short name T268
Test name
Test status
Simulation time 98751171 ps
CPU time 5.51 seconds
Started Jul 23 06:23:05 PM PDT 24
Finished Jul 23 06:23:25 PM PDT 24
Peak memory 211432 kb
Host smart-37f2a130-f130-4f20-b31c-1e236ee53197
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294067245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4294067245
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1939812918
Short name T33
Test name
Test status
Simulation time 4182474329 ps
CPU time 41.76 seconds
Started Jul 23 06:23:03 PM PDT 24
Finished Jul 23 06:24:01 PM PDT 24
Peak memory 212276 kb
Host smart-b9388aaa-23e8-4eaf-be7e-cb893d40c4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939812918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1939812918
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3202923706
Short name T329
Test name
Test status
Simulation time 20541666359 ps
CPU time 39.7 seconds
Started Jul 23 06:23:03 PM PDT 24
Finished Jul 23 06:23:58 PM PDT 24
Peak memory 215228 kb
Host smart-d5460d4c-d9dc-4661-ac1c-97afb95a6d61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202923706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3202923706
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2361312453
Short name T157
Test name
Test status
Simulation time 4797302668 ps
CPU time 11.38 seconds
Started Jul 23 06:23:02 PM PDT 24
Finished Jul 23 06:23:30 PM PDT 24
Peak memory 211428 kb
Host smart-ef9111ed-3d64-453b-8933-c3c85dd8ec0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361312453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2361312453
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3815447863
Short name T335
Test name
Test status
Simulation time 5072730886 ps
CPU time 130.47 seconds
Started Jul 23 06:23:05 PM PDT 24
Finished Jul 23 06:25:30 PM PDT 24
Peak memory 212680 kb
Host smart-ac9e17aa-c208-4b18-a126-ed5f51f5c753
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815447863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3815447863
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.771104641
Short name T240
Test name
Test status
Simulation time 698527296 ps
CPU time 9.55 seconds
Started Jul 23 06:23:02 PM PDT 24
Finished Jul 23 06:23:28 PM PDT 24
Peak memory 211380 kb
Host smart-7ca86c5e-7b17-47b5-a25c-c7a1239db58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771104641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.771104641
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1408238360
Short name T336
Test name
Test status
Simulation time 4220879676 ps
CPU time 15.69 seconds
Started Jul 23 06:23:05 PM PDT 24
Finished Jul 23 06:23:35 PM PDT 24
Peak memory 211488 kb
Host smart-8922351c-c75f-4d75-889c-d1f12c945db6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408238360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1408238360
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.277469561
Short name T179
Test name
Test status
Simulation time 3429871537 ps
CPU time 32.44 seconds
Started Jul 23 06:23:03 PM PDT 24
Finished Jul 23 06:23:51 PM PDT 24
Peak memory 213312 kb
Host smart-806a4c19-7f60-4446-8429-4ce85ff9847b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277469561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.277469561
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.740795221
Short name T137
Test name
Test status
Simulation time 1098285992 ps
CPU time 17.53 seconds
Started Jul 23 06:23:03 PM PDT 24
Finished Jul 23 06:23:36 PM PDT 24
Peak memory 214008 kb
Host smart-beff267d-f76e-4fc0-9658-ee2fb05c2ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740795221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.740795221
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4040223704
Short name T312
Test name
Test status
Simulation time 100323312 ps
CPU time 4.25 seconds
Started Jul 23 06:23:09 PM PDT 24
Finished Jul 23 06:23:27 PM PDT 24
Peak memory 211384 kb
Host smart-f52fd1ff-b4a3-42fa-9339-5b5dfc5f7704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040223704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4040223704
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3706499299
Short name T357
Test name
Test status
Simulation time 86857204801 ps
CPU time 206.88 seconds
Started Jul 23 06:23:07 PM PDT 24
Finished Jul 23 06:26:49 PM PDT 24
Peak memory 238916 kb
Host smart-f31052d4-5e03-4518-8a21-bebfd879e943
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706499299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3706499299
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.923685811
Short name T15
Test name
Test status
Simulation time 3018426083 ps
CPU time 26.62 seconds
Started Jul 23 06:23:10 PM PDT 24
Finished Jul 23 06:23:50 PM PDT 24
Peak memory 212136 kb
Host smart-fcb1c84e-69d8-45e2-a74e-d9269d6df2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923685811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.923685811
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2423409349
Short name T166
Test name
Test status
Simulation time 633477620 ps
CPU time 9.35 seconds
Started Jul 23 06:23:02 PM PDT 24
Finished Jul 23 06:23:28 PM PDT 24
Peak memory 211412 kb
Host smart-7a9854ec-4dc1-4abf-ba5e-c918391b7266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423409349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2423409349
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2304386897
Short name T330
Test name
Test status
Simulation time 9340286139 ps
CPU time 83.51 seconds
Started Jul 23 06:23:02 PM PDT 24
Finished Jul 23 06:24:42 PM PDT 24
Peak memory 217188 kb
Host smart-bc58414a-24b8-458d-8676-ee1b9729ac1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304386897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2304386897
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.715994820
Short name T99
Test name
Test status
Simulation time 153779329820 ps
CPU time 8357.35 seconds
Started Jul 23 06:23:07 PM PDT 24
Finished Jul 23 08:42:40 PM PDT 24
Peak memory 235904 kb
Host smart-dded9e35-64fe-41b5-80a7-1f660fbf58e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715994820 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.715994820
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3621162338
Short name T9
Test name
Test status
Simulation time 5131007937 ps
CPU time 9.7 seconds
Started Jul 23 06:23:07 PM PDT 24
Finished Jul 23 06:23:32 PM PDT 24
Peak memory 211388 kb
Host smart-b49a7f9a-9390-4adc-aade-596bdeeed709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621162338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3621162338
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.448071970
Short name T277
Test name
Test status
Simulation time 34967224770 ps
CPU time 141.85 seconds
Started Jul 23 06:23:09 PM PDT 24
Finished Jul 23 06:25:45 PM PDT 24
Peak memory 233032 kb
Host smart-602065b3-3615-4673-9666-dd6619a43c4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448071970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.448071970
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3571623050
Short name T325
Test name
Test status
Simulation time 4054333411 ps
CPU time 31.22 seconds
Started Jul 23 06:23:07 PM PDT 24
Finished Jul 23 06:23:54 PM PDT 24
Peak memory 212608 kb
Host smart-4340f03f-7e07-40ba-9316-742dccf17976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571623050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3571623050
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.504759160
Short name T35
Test name
Test status
Simulation time 652802444 ps
CPU time 9.2 seconds
Started Jul 23 06:23:11 PM PDT 24
Finished Jul 23 06:23:32 PM PDT 24
Peak memory 211436 kb
Host smart-dcdba9a2-cdfc-4281-b2e3-4c9cae212eab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504759160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.504759160
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.941963223
Short name T269
Test name
Test status
Simulation time 593208555 ps
CPU time 13.82 seconds
Started Jul 23 06:23:07 PM PDT 24
Finished Jul 23 06:23:36 PM PDT 24
Peak memory 213416 kb
Host smart-82327425-26b9-4056-99df-a6f236fdd18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941963223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.941963223
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.601345588
Short name T59
Test name
Test status
Simulation time 95384729497 ps
CPU time 868.48 seconds
Started Jul 23 06:23:08 PM PDT 24
Finished Jul 23 06:37:51 PM PDT 24
Peak memory 235860 kb
Host smart-47eb3000-5561-4875-ae58-d8f4e4356644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601345588 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.601345588
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.325305145
Short name T75
Test name
Test status
Simulation time 2052760171 ps
CPU time 5.43 seconds
Started Jul 23 06:23:14 PM PDT 24
Finished Jul 23 06:23:31 PM PDT 24
Peak memory 211348 kb
Host smart-19de3e8a-20cd-4211-9ee6-341ee5935713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325305145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.325305145
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2879308062
Short name T39
Test name
Test status
Simulation time 27444627525 ps
CPU time 197.64 seconds
Started Jul 23 06:23:14 PM PDT 24
Finished Jul 23 06:26:44 PM PDT 24
Peak memory 237932 kb
Host smart-10f1d054-a180-42c3-8bb1-01894b538179
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879308062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2879308062
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3004770890
Short name T323
Test name
Test status
Simulation time 2368563249 ps
CPU time 9.41 seconds
Started Jul 23 06:23:16 PM PDT 24
Finished Jul 23 06:23:36 PM PDT 24
Peak memory 212108 kb
Host smart-9a82c787-7938-463f-a477-06dccd653784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004770890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3004770890
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4053678827
Short name T66
Test name
Test status
Simulation time 8233358610 ps
CPU time 16.39 seconds
Started Jul 23 06:23:13 PM PDT 24
Finished Jul 23 06:23:41 PM PDT 24
Peak memory 211448 kb
Host smart-00d0cc96-241c-4c2f-955f-a4d883b53415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053678827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4053678827
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2692977788
Short name T186
Test name
Test status
Simulation time 8016328510 ps
CPU time 25.44 seconds
Started Jul 23 06:23:10 PM PDT 24
Finished Jul 23 06:23:48 PM PDT 24
Peak memory 214756 kb
Host smart-dffb9fbe-a8a0-411c-8d61-a21cd7a91845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692977788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2692977788
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3548226451
Short name T273
Test name
Test status
Simulation time 8572917788 ps
CPU time 64.59 seconds
Started Jul 23 06:23:08 PM PDT 24
Finished Jul 23 06:24:27 PM PDT 24
Peak memory 218008 kb
Host smart-7730e873-e6e5-4326-9262-df0f066ee66e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548226451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3548226451
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1127504057
Short name T296
Test name
Test status
Simulation time 1281111733 ps
CPU time 11.97 seconds
Started Jul 23 06:23:16 PM PDT 24
Finished Jul 23 06:23:39 PM PDT 24
Peak memory 211376 kb
Host smart-cbaa4525-043e-435d-9327-57827ee5bf06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127504057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1127504057
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.450128191
Short name T243
Test name
Test status
Simulation time 2203002443 ps
CPU time 56.05 seconds
Started Jul 23 06:23:15 PM PDT 24
Finished Jul 23 06:24:22 PM PDT 24
Peak memory 211660 kb
Host smart-c9e9984a-bbce-4ce5-9fe0-72b4e236d0aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450128191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.450128191
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1028598297
Short name T191
Test name
Test status
Simulation time 7134161924 ps
CPU time 19.68 seconds
Started Jul 23 06:23:14 PM PDT 24
Finished Jul 23 06:23:45 PM PDT 24
Peak memory 213340 kb
Host smart-034ede0e-ba01-4548-9fbc-60862f54eb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028598297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1028598297
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4076343328
Short name T49
Test name
Test status
Simulation time 3276650856 ps
CPU time 14.04 seconds
Started Jul 23 06:23:16 PM PDT 24
Finished Jul 23 06:23:42 PM PDT 24
Peak memory 211444 kb
Host smart-9467e2b4-a936-4317-b384-052819c1047b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4076343328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4076343328
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1333160929
Short name T178
Test name
Test status
Simulation time 3973348036 ps
CPU time 16.45 seconds
Started Jul 23 06:23:14 PM PDT 24
Finished Jul 23 06:23:42 PM PDT 24
Peak memory 213700 kb
Host smart-257c2d01-5b5a-4636-a9f4-c3fa7c8c93f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333160929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1333160929
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.551739300
Short name T116
Test name
Test status
Simulation time 8429337046 ps
CPU time 24.96 seconds
Started Jul 23 06:23:15 PM PDT 24
Finished Jul 23 06:23:51 PM PDT 24
Peak memory 213572 kb
Host smart-05755558-b3e0-40aa-9461-9b7835f6ab23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551739300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.551739300
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1524010374
Short name T174
Test name
Test status
Simulation time 2203687555 ps
CPU time 17.09 seconds
Started Jul 23 06:23:22 PM PDT 24
Finished Jul 23 06:23:48 PM PDT 24
Peak memory 211424 kb
Host smart-bcb69038-601d-48c7-98e5-40302c0248fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524010374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1524010374
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.622423013
Short name T226
Test name
Test status
Simulation time 31607312723 ps
CPU time 325.09 seconds
Started Jul 23 06:23:21 PM PDT 24
Finished Jul 23 06:28:56 PM PDT 24
Peak memory 237916 kb
Host smart-f6744936-44a4-4c6b-8aea-d44bb71bfd72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622423013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.622423013
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1434475935
Short name T327
Test name
Test status
Simulation time 5186547939 ps
CPU time 17.85 seconds
Started Jul 23 06:23:22 PM PDT 24
Finished Jul 23 06:23:49 PM PDT 24
Peak memory 212300 kb
Host smart-5641061f-5ec7-41c8-980b-6560bc6db323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434475935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1434475935
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2747317266
Short name T281
Test name
Test status
Simulation time 6480580550 ps
CPU time 14.98 seconds
Started Jul 23 06:23:25 PM PDT 24
Finished Jul 23 06:23:49 PM PDT 24
Peak memory 211468 kb
Host smart-62acc7ee-00cd-4ea7-a53a-e5530b4f4135
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747317266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2747317266
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2062839675
Short name T184
Test name
Test status
Simulation time 16068924488 ps
CPU time 33.1 seconds
Started Jul 23 06:23:14 PM PDT 24
Finished Jul 23 06:23:59 PM PDT 24
Peak memory 214228 kb
Host smart-fec648ea-a0b8-4ea8-89f5-ad9244af5792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062839675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2062839675
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.536284222
Short name T133
Test name
Test status
Simulation time 4065433530 ps
CPU time 12.98 seconds
Started Jul 23 06:23:15 PM PDT 24
Finished Jul 23 06:23:40 PM PDT 24
Peak memory 212000 kb
Host smart-3181ddbd-4e4e-451d-8c1e-a480bfe73731
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536284222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.536284222
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.771665942
Short name T239
Test name
Test status
Simulation time 497817846 ps
CPU time 6.17 seconds
Started Jul 23 06:23:20 PM PDT 24
Finished Jul 23 06:23:36 PM PDT 24
Peak memory 211332 kb
Host smart-5cdbb2da-1dc6-499c-9a4b-8c4738c65835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771665942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.771665942
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.847249521
Short name T43
Test name
Test status
Simulation time 12031953513 ps
CPU time 112.32 seconds
Started Jul 23 06:23:26 PM PDT 24
Finished Jul 23 06:25:27 PM PDT 24
Peak memory 236784 kb
Host smart-ad99d207-639a-4a0f-966e-e189b9f39281
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847249521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.847249521
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3434730227
Short name T291
Test name
Test status
Simulation time 3893205608 ps
CPU time 31.96 seconds
Started Jul 23 06:23:25 PM PDT 24
Finished Jul 23 06:24:06 PM PDT 24
Peak memory 212036 kb
Host smart-071c7262-edbc-471a-b76c-53c8eaee427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434730227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3434730227
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1243559511
Short name T222
Test name
Test status
Simulation time 99346212 ps
CPU time 5.66 seconds
Started Jul 23 06:23:21 PM PDT 24
Finished Jul 23 06:23:36 PM PDT 24
Peak memory 211384 kb
Host smart-22d4593a-a1fe-4531-bb8d-6a7b0a86d6dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243559511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1243559511
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1072767060
Short name T259
Test name
Test status
Simulation time 203183236 ps
CPU time 9.96 seconds
Started Jul 23 06:23:22 PM PDT 24
Finished Jul 23 06:23:41 PM PDT 24
Peak memory 211904 kb
Host smart-3196934e-dfd2-4f40-9f00-a66527e843be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072767060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1072767060
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.348168799
Short name T369
Test name
Test status
Simulation time 26837862924 ps
CPU time 54.92 seconds
Started Jul 23 06:23:27 PM PDT 24
Finished Jul 23 06:24:31 PM PDT 24
Peak memory 217108 kb
Host smart-7769dfa1-1507-47d3-9450-ee52e73d5e4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348168799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.348168799
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.809006547
Short name T320
Test name
Test status
Simulation time 1065666727 ps
CPU time 11.1 seconds
Started Jul 23 06:23:27 PM PDT 24
Finished Jul 23 06:23:48 PM PDT 24
Peak memory 211320 kb
Host smart-bc5af400-ac72-4cb9-a46a-a28ffd80893e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809006547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.809006547
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.964323847
Short name T197
Test name
Test status
Simulation time 2808343269 ps
CPU time 85.27 seconds
Started Jul 23 06:23:21 PM PDT 24
Finished Jul 23 06:24:56 PM PDT 24
Peak memory 237892 kb
Host smart-fb39345f-6c5f-4682-a8bb-1efddc0a1c3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964323847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.964323847
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1696218908
Short name T264
Test name
Test status
Simulation time 3138858151 ps
CPU time 26.29 seconds
Started Jul 23 06:23:25 PM PDT 24
Finished Jul 23 06:24:00 PM PDT 24
Peak memory 212076 kb
Host smart-64bef43e-d87f-4e09-a6f9-782d1fec7421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696218908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1696218908
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.222945721
Short name T52
Test name
Test status
Simulation time 519508108 ps
CPU time 8.6 seconds
Started Jul 23 06:23:21 PM PDT 24
Finished Jul 23 06:23:40 PM PDT 24
Peak memory 211420 kb
Host smart-ec64d2c6-78dd-4496-941c-19ae9f4f68ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222945721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.222945721
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.288043669
Short name T250
Test name
Test status
Simulation time 189911308 ps
CPU time 10.36 seconds
Started Jul 23 06:23:27 PM PDT 24
Finished Jul 23 06:23:46 PM PDT 24
Peak memory 213892 kb
Host smart-9b93fc86-1d2b-4020-9d23-1e22f740038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288043669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.288043669
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4200267826
Short name T293
Test name
Test status
Simulation time 1162821607 ps
CPU time 13.36 seconds
Started Jul 23 06:23:23 PM PDT 24
Finished Jul 23 06:23:45 PM PDT 24
Peak memory 213700 kb
Host smart-8465e06b-fd5c-4f37-9edb-614969b3ce7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200267826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4200267826
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3283210258
Short name T215
Test name
Test status
Simulation time 4598682545 ps
CPU time 10.84 seconds
Started Jul 23 06:23:28 PM PDT 24
Finished Jul 23 06:23:48 PM PDT 24
Peak memory 211432 kb
Host smart-045d24a0-1c3b-4620-bfe6-fb9f53cf7ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283210258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3283210258
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3226462040
Short name T45
Test name
Test status
Simulation time 5807072042 ps
CPU time 89.72 seconds
Started Jul 23 06:23:26 PM PDT 24
Finished Jul 23 06:25:04 PM PDT 24
Peak memory 212652 kb
Host smart-23d03a47-7645-4866-9018-80d7afc1c1a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226462040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3226462040
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2949449279
Short name T159
Test name
Test status
Simulation time 4311811206 ps
CPU time 29.78 seconds
Started Jul 23 06:23:28 PM PDT 24
Finished Jul 23 06:24:07 PM PDT 24
Peak memory 212288 kb
Host smart-e7b265d5-2ae7-4793-906e-641865221215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949449279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2949449279
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1330703626
Short name T208
Test name
Test status
Simulation time 313417370 ps
CPU time 7.37 seconds
Started Jul 23 06:23:26 PM PDT 24
Finished Jul 23 06:23:42 PM PDT 24
Peak memory 211432 kb
Host smart-6ea4b3ca-4ca9-40f5-aa13-7e4b1a338843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330703626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1330703626
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.626750780
Short name T342
Test name
Test status
Simulation time 2979994284 ps
CPU time 33.23 seconds
Started Jul 23 06:23:28 PM PDT 24
Finished Jul 23 06:24:10 PM PDT 24
Peak memory 213744 kb
Host smart-3c38a041-acf0-4e68-9c6a-ee70ea5ce83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626750780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.626750780
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3892797237
Short name T352
Test name
Test status
Simulation time 1548378618 ps
CPU time 21.87 seconds
Started Jul 23 06:23:26 PM PDT 24
Finished Jul 23 06:23:56 PM PDT 24
Peak memory 216600 kb
Host smart-f600e45c-59b5-4d7f-8e91-504484f4d734
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892797237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3892797237
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1455048855
Short name T26
Test name
Test status
Simulation time 519640817 ps
CPU time 5.05 seconds
Started Jul 23 06:22:41 PM PDT 24
Finished Jul 23 06:23:04 PM PDT 24
Peak memory 211384 kb
Host smart-f1cbcf90-c47f-4bc9-b936-6ec55d78ebe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455048855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1455048855
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1814681641
Short name T245
Test name
Test status
Simulation time 100969012371 ps
CPU time 214.08 seconds
Started Jul 23 06:22:43 PM PDT 24
Finished Jul 23 06:26:37 PM PDT 24
Peak memory 237868 kb
Host smart-9e48691b-c816-4e8e-af45-bb9f323d6d00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814681641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1814681641
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.80912671
Short name T189
Test name
Test status
Simulation time 13580553615 ps
CPU time 26.88 seconds
Started Jul 23 06:22:39 PM PDT 24
Finished Jul 23 06:23:24 PM PDT 24
Peak memory 213708 kb
Host smart-c36d4364-733b-4ac3-b2c8-ac6e0e256288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80912671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.80912671
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3128275224
Short name T139
Test name
Test status
Simulation time 345467577 ps
CPU time 5.64 seconds
Started Jul 23 06:22:39 PM PDT 24
Finished Jul 23 06:23:02 PM PDT 24
Peak memory 211412 kb
Host smart-fe8f3850-35d9-44ad-90d2-ae5651f43f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128275224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3128275224
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.367960004
Short name T28
Test name
Test status
Simulation time 11990442245 ps
CPU time 58.3 seconds
Started Jul 23 06:22:49 PM PDT 24
Finished Jul 23 06:24:06 PM PDT 24
Peak memory 238008 kb
Host smart-fb8af45f-dc63-4f30-b31b-ec0835baf3d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367960004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.367960004
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2007263766
Short name T102
Test name
Test status
Simulation time 14997379397 ps
CPU time 28.34 seconds
Started Jul 23 06:22:41 PM PDT 24
Finished Jul 23 06:23:27 PM PDT 24
Peak memory 214576 kb
Host smart-7073f1b6-4c37-4ed2-9fc2-e893558b8348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007263766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2007263766
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1446801027
Short name T228
Test name
Test status
Simulation time 4812222765 ps
CPU time 50.84 seconds
Started Jul 23 06:22:40 PM PDT 24
Finished Jul 23 06:23:49 PM PDT 24
Peak memory 216156 kb
Host smart-f9e76d7b-96fb-42a9-9086-11e9dc672b76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446801027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1446801027
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1773695931
Short name T169
Test name
Test status
Simulation time 3174533425 ps
CPU time 14.8 seconds
Started Jul 23 06:23:34 PM PDT 24
Finished Jul 23 06:23:58 PM PDT 24
Peak memory 211328 kb
Host smart-e92c297a-da93-4ac9-9afe-99ff939df235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773695931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1773695931
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1802530354
Short name T289
Test name
Test status
Simulation time 6372459025 ps
CPU time 104.39 seconds
Started Jul 23 06:23:26 PM PDT 24
Finished Jul 23 06:25:19 PM PDT 24
Peak memory 236832 kb
Host smart-d8eeb37a-d70f-4fdb-afb8-3570892196ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802530354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1802530354
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3802875100
Short name T309
Test name
Test status
Simulation time 1972718545 ps
CPU time 13.1 seconds
Started Jul 23 06:23:27 PM PDT 24
Finished Jul 23 06:23:49 PM PDT 24
Peak memory 212040 kb
Host smart-97374532-93ea-4239-875a-a4dd9fa36ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802875100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3802875100
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1046552292
Short name T61
Test name
Test status
Simulation time 653718908 ps
CPU time 9.51 seconds
Started Jul 23 06:23:28 PM PDT 24
Finished Jul 23 06:23:47 PM PDT 24
Peak memory 211332 kb
Host smart-d1892584-9138-44ef-8809-2b0307fd7878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046552292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1046552292
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.216221855
Short name T266
Test name
Test status
Simulation time 561001383 ps
CPU time 10.61 seconds
Started Jul 23 06:23:29 PM PDT 24
Finished Jul 23 06:23:49 PM PDT 24
Peak memory 213824 kb
Host smart-9d2b9b6b-9c8f-49b3-9366-ffc6961c3eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216221855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.216221855
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4135227077
Short name T290
Test name
Test status
Simulation time 3169489760 ps
CPU time 40.87 seconds
Started Jul 23 06:23:25 PM PDT 24
Finished Jul 23 06:24:15 PM PDT 24
Peak memory 213568 kb
Host smart-cbe40be0-14aa-4837-97ec-f1607d12aea2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135227077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4135227077
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3644098919
Short name T74
Test name
Test status
Simulation time 592423299 ps
CPU time 4.33 seconds
Started Jul 23 06:23:35 PM PDT 24
Finished Jul 23 06:23:49 PM PDT 24
Peak memory 211320 kb
Host smart-b24efde7-102b-4441-89bd-73fd55518630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644098919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3644098919
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2295386155
Short name T279
Test name
Test status
Simulation time 181052387850 ps
CPU time 293.14 seconds
Started Jul 23 06:23:34 PM PDT 24
Finished Jul 23 06:28:36 PM PDT 24
Peak memory 237492 kb
Host smart-264ac495-c178-41af-b5d0-e6bee8bb2e63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295386155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2295386155
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4243989963
Short name T164
Test name
Test status
Simulation time 3788482961 ps
CPU time 31.44 seconds
Started Jul 23 06:23:33 PM PDT 24
Finished Jul 23 06:24:14 PM PDT 24
Peak memory 212484 kb
Host smart-32fef334-172e-41cc-8fa7-957b878415f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243989963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4243989963
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2231535505
Short name T205
Test name
Test status
Simulation time 1937086400 ps
CPU time 15.8 seconds
Started Jul 23 06:23:33 PM PDT 24
Finished Jul 23 06:23:58 PM PDT 24
Peak memory 211428 kb
Host smart-617ed795-8bf1-4bf9-9034-35edaccc52bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2231535505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2231535505
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2175108922
Short name T209
Test name
Test status
Simulation time 6441560787 ps
CPU time 29.31 seconds
Started Jul 23 06:23:35 PM PDT 24
Finished Jul 23 06:24:13 PM PDT 24
Peak memory 214368 kb
Host smart-94877fbf-dddb-40e9-aaf8-04187b0c634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175108922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2175108922
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2259313574
Short name T235
Test name
Test status
Simulation time 743971542 ps
CPU time 21.04 seconds
Started Jul 23 06:23:34 PM PDT 24
Finished Jul 23 06:24:04 PM PDT 24
Peak memory 216108 kb
Host smart-b5165e10-3805-4412-aeaf-83e9458c6e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259313574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2259313574
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1244677332
Short name T317
Test name
Test status
Simulation time 923434917 ps
CPU time 4.3 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:23:53 PM PDT 24
Peak memory 211364 kb
Host smart-b5d503fb-9309-4ce4-b32b-413d41fb48a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244677332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1244677332
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2863764947
Short name T148
Test name
Test status
Simulation time 9681413389 ps
CPU time 120.69 seconds
Started Jul 23 06:23:35 PM PDT 24
Finished Jul 23 06:25:46 PM PDT 24
Peak memory 233244 kb
Host smart-4a55226c-b474-4149-b530-07138b9697a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863764947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2863764947
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1453478163
Short name T207
Test name
Test status
Simulation time 8709802804 ps
CPU time 35.87 seconds
Started Jul 23 06:23:36 PM PDT 24
Finished Jul 23 06:24:21 PM PDT 24
Peak memory 212236 kb
Host smart-2494c868-e7a0-4bb1-9416-8c1651fd820f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453478163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1453478163
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.644167837
Short name T286
Test name
Test status
Simulation time 6130166155 ps
CPU time 13.59 seconds
Started Jul 23 06:23:36 PM PDT 24
Finished Jul 23 06:23:59 PM PDT 24
Peak memory 211440 kb
Host smart-d832a52f-5580-429a-bce3-f3ace0bb81d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=644167837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.644167837
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1228537155
Short name T47
Test name
Test status
Simulation time 188232062 ps
CPU time 10.1 seconds
Started Jul 23 06:23:33 PM PDT 24
Finished Jul 23 06:23:53 PM PDT 24
Peak memory 213408 kb
Host smart-d7ab0794-38d9-4702-8977-7755bba700e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228537155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1228537155
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.144244902
Short name T146
Test name
Test status
Simulation time 1665214039 ps
CPU time 23.28 seconds
Started Jul 23 06:23:35 PM PDT 24
Finished Jul 23 06:24:08 PM PDT 24
Peak memory 215488 kb
Host smart-06e19579-9c5d-4855-ab67-9c19d63abc7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144244902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.144244902
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.4021890087
Short name T236
Test name
Test status
Simulation time 5575437415 ps
CPU time 12.63 seconds
Started Jul 23 06:23:43 PM PDT 24
Finished Jul 23 06:24:02 PM PDT 24
Peak memory 211416 kb
Host smart-5781bc0d-4f3d-4c26-b630-bd2d92376b18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021890087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4021890087
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.249920666
Short name T41
Test name
Test status
Simulation time 31511858595 ps
CPU time 124.23 seconds
Started Jul 23 06:23:41 PM PDT 24
Finished Jul 23 06:25:52 PM PDT 24
Peak memory 237888 kb
Host smart-0187a56b-3e87-40f8-993e-2e2d802f155f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249920666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.249920666
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1916431913
Short name T195
Test name
Test status
Simulation time 554673144 ps
CPU time 9.47 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:23:58 PM PDT 24
Peak memory 212068 kb
Host smart-a9a5bb32-6fa6-47f6-9a1c-b0bdd704e2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916431913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1916431913
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3091913112
Short name T362
Test name
Test status
Simulation time 183118430 ps
CPU time 7.05 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:23:56 PM PDT 24
Peak memory 211364 kb
Host smart-e2745a7a-1b36-4f76-a0ca-555373fc01f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091913112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3091913112
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.405451883
Short name T190
Test name
Test status
Simulation time 4141487792 ps
CPU time 17.55 seconds
Started Jul 23 06:23:41 PM PDT 24
Finished Jul 23 06:24:06 PM PDT 24
Peak memory 212628 kb
Host smart-7c0367ff-07c1-4387-8893-0ce328f21292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405451883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.405451883
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3404314629
Short name T310
Test name
Test status
Simulation time 5818201361 ps
CPU time 13.3 seconds
Started Jul 23 06:23:43 PM PDT 24
Finished Jul 23 06:24:03 PM PDT 24
Peak memory 211436 kb
Host smart-0957d7a6-6282-440a-89e4-09017c761337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404314629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3404314629
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2729002491
Short name T177
Test name
Test status
Simulation time 3478332084 ps
CPU time 53.74 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:24:43 PM PDT 24
Peak memory 212636 kb
Host smart-c028d526-ce29-4fc3-a812-1c5d0c58b038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729002491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2729002491
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1298679107
Short name T29
Test name
Test status
Simulation time 2289630564 ps
CPU time 17.79 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:24:07 PM PDT 24
Peak memory 212088 kb
Host smart-239acdc8-a7bd-4d49-9bc9-a2f0be7cc471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298679107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1298679107
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1772899739
Short name T149
Test name
Test status
Simulation time 482700788 ps
CPU time 7.09 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:23:56 PM PDT 24
Peak memory 211400 kb
Host smart-e4983b1c-4cea-45ef-b33c-12e2ffac8849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772899739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1772899739
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3188583344
Short name T319
Test name
Test status
Simulation time 940422210 ps
CPU time 17.15 seconds
Started Jul 23 06:23:43 PM PDT 24
Finished Jul 23 06:24:07 PM PDT 24
Peak memory 212864 kb
Host smart-f314e3a3-133a-4179-81f6-bb2a601f1e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188583344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3188583344
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3103808073
Short name T136
Test name
Test status
Simulation time 9121960947 ps
CPU time 25.46 seconds
Started Jul 23 06:23:41 PM PDT 24
Finished Jul 23 06:24:13 PM PDT 24
Peak memory 214868 kb
Host smart-a1d69f81-7e97-489d-95a1-26021ecc8c31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103808073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3103808073
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3879504387
Short name T321
Test name
Test status
Simulation time 60719733693 ps
CPU time 2082.64 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:58:32 PM PDT 24
Peak memory 240776 kb
Host smart-ed8f6976-781f-4ab7-ba35-48770557f7e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879504387 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3879504387
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2102082107
Short name T354
Test name
Test status
Simulation time 261636524 ps
CPU time 4.2 seconds
Started Jul 23 06:23:40 PM PDT 24
Finished Jul 23 06:23:52 PM PDT 24
Peak memory 211380 kb
Host smart-e88d07d9-9d2e-4874-ace3-2c48d022b647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102082107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2102082107
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.491256150
Short name T204
Test name
Test status
Simulation time 97761293038 ps
CPU time 335.34 seconds
Started Jul 23 06:23:41 PM PDT 24
Finished Jul 23 06:29:24 PM PDT 24
Peak memory 237896 kb
Host smart-03a9b0ff-b68c-426d-a511-2a2ecdf176e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491256150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.491256150
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1136473356
Short name T145
Test name
Test status
Simulation time 1694327244 ps
CPU time 20.28 seconds
Started Jul 23 06:23:41 PM PDT 24
Finished Jul 23 06:24:09 PM PDT 24
Peak memory 211936 kb
Host smart-7f56533c-14c4-4e69-ae3e-6bdb402a5210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136473356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1136473356
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2619743575
Short name T175
Test name
Test status
Simulation time 1504710173 ps
CPU time 12.43 seconds
Started Jul 23 06:23:41 PM PDT 24
Finished Jul 23 06:24:01 PM PDT 24
Peak memory 211412 kb
Host smart-b0b115b4-988e-4636-826f-1d709e3afa3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2619743575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2619743575
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1094567428
Short name T282
Test name
Test status
Simulation time 4280634576 ps
CPU time 13.29 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:24:02 PM PDT 24
Peak memory 213428 kb
Host smart-05381949-7e30-425f-9076-84085c1142fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094567428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1094567428
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.234270005
Short name T307
Test name
Test status
Simulation time 611770267 ps
CPU time 10.44 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:23:59 PM PDT 24
Peak memory 211276 kb
Host smart-2912e2ef-ad45-40f7-b684-9dae8fe62e6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234270005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.234270005
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3714508026
Short name T181
Test name
Test status
Simulation time 175155453 ps
CPU time 4.3 seconds
Started Jul 23 06:23:48 PM PDT 24
Finished Jul 23 06:23:57 PM PDT 24
Peak memory 211376 kb
Host smart-3d27ecf9-30e8-45ba-8af3-074d0dbfe797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714508026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3714508026
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3761724445
Short name T298
Test name
Test status
Simulation time 9567305323 ps
CPU time 149.35 seconds
Started Jul 23 06:23:42 PM PDT 24
Finished Jul 23 06:26:19 PM PDT 24
Peak memory 236832 kb
Host smart-48f6676e-f239-414d-9d16-d89593103846
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761724445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3761724445
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1736402610
Short name T328
Test name
Test status
Simulation time 2516095219 ps
CPU time 13.89 seconds
Started Jul 23 06:23:41 PM PDT 24
Finished Jul 23 06:24:02 PM PDT 24
Peak memory 211964 kb
Host smart-1e74c755-32c6-440d-aae2-e3ac9d1610ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736402610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1736402610
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3996749066
Short name T359
Test name
Test status
Simulation time 103637983 ps
CPU time 5.92 seconds
Started Jul 23 06:23:44 PM PDT 24
Finished Jul 23 06:23:56 PM PDT 24
Peak memory 211408 kb
Host smart-0d028c73-c927-45ef-a331-8b5a7c614542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3996749066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3996749066
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.389381232
Short name T260
Test name
Test status
Simulation time 2629302285 ps
CPU time 24.43 seconds
Started Jul 23 06:23:41 PM PDT 24
Finished Jul 23 06:24:13 PM PDT 24
Peak memory 212256 kb
Host smart-80a025f7-2109-4d0c-bcee-00cc5079f1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389381232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.389381232
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2708971708
Short name T247
Test name
Test status
Simulation time 2502611412 ps
CPU time 32.22 seconds
Started Jul 23 06:23:43 PM PDT 24
Finished Jul 23 06:24:22 PM PDT 24
Peak memory 213676 kb
Host smart-f400d8f2-0447-4780-8349-56124d5647d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708971708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2708971708
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2957535260
Short name T355
Test name
Test status
Simulation time 2627150297 ps
CPU time 80.8 seconds
Started Jul 23 06:23:48 PM PDT 24
Finished Jul 23 06:25:13 PM PDT 24
Peak memory 236828 kb
Host smart-5ada43a3-1711-48b7-b5ff-f04777237b84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957535260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2957535260
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3637449646
Short name T103
Test name
Test status
Simulation time 1510465801 ps
CPU time 15.19 seconds
Started Jul 23 06:23:48 PM PDT 24
Finished Jul 23 06:24:08 PM PDT 24
Peak memory 211948 kb
Host smart-a9cb4091-54f8-4d4e-b52d-c298fcb7acc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637449646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3637449646
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3556962556
Short name T143
Test name
Test status
Simulation time 138490896 ps
CPU time 5.77 seconds
Started Jul 23 06:23:48 PM PDT 24
Finished Jul 23 06:23:58 PM PDT 24
Peak memory 211408 kb
Host smart-61c06dfb-d880-4463-b092-cead7c245fe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556962556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3556962556
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.7373034
Short name T154
Test name
Test status
Simulation time 3048153810 ps
CPU time 26.91 seconds
Started Jul 23 06:23:50 PM PDT 24
Finished Jul 23 06:24:20 PM PDT 24
Peak memory 213564 kb
Host smart-f5bf2641-d39c-403b-8f17-b57bd0c7cf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7373034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.7373034
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1077079329
Short name T8
Test name
Test status
Simulation time 34272136921 ps
CPU time 72.91 seconds
Started Jul 23 06:23:48 PM PDT 24
Finished Jul 23 06:25:05 PM PDT 24
Peak memory 216008 kb
Host smart-df2d3047-1f18-45bc-94c0-688305220415
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077079329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1077079329
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3770601717
Short name T224
Test name
Test status
Simulation time 85693437 ps
CPU time 4.19 seconds
Started Jul 23 06:23:48 PM PDT 24
Finished Jul 23 06:23:57 PM PDT 24
Peak memory 211368 kb
Host smart-1e7b9f70-8513-478c-950b-c88638f215b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770601717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3770601717
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.323349046
Short name T40
Test name
Test status
Simulation time 7196740088 ps
CPU time 111.98 seconds
Started Jul 23 06:23:47 PM PDT 24
Finished Jul 23 06:25:44 PM PDT 24
Peak memory 228656 kb
Host smart-a4d5c661-aec9-4722-bc8f-1fc0aef341af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323349046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.323349046
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3017868791
Short name T263
Test name
Test status
Simulation time 171879983 ps
CPU time 9.77 seconds
Started Jul 23 06:23:48 PM PDT 24
Finished Jul 23 06:24:02 PM PDT 24
Peak memory 211948 kb
Host smart-327a3529-72df-4d06-bf14-a508b676511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017868791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3017868791
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2324446120
Short name T255
Test name
Test status
Simulation time 7763154443 ps
CPU time 16.78 seconds
Started Jul 23 06:23:48 PM PDT 24
Finished Jul 23 06:24:09 PM PDT 24
Peak memory 211484 kb
Host smart-5faf1553-f697-4a9b-86cd-aeeed0769644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2324446120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2324446120
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1815644948
Short name T314
Test name
Test status
Simulation time 3784543164 ps
CPU time 35.02 seconds
Started Jul 23 06:23:50 PM PDT 24
Finished Jul 23 06:24:28 PM PDT 24
Peak memory 213468 kb
Host smart-6ba0d97a-ee4a-47b5-9db2-eb4aa3f703dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815644948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1815644948
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3901775351
Short name T275
Test name
Test status
Simulation time 32913839051 ps
CPU time 86.68 seconds
Started Jul 23 06:23:48 PM PDT 24
Finished Jul 23 06:25:19 PM PDT 24
Peak memory 217640 kb
Host smart-bcbe18cb-b916-4522-a98d-6cc7ec9aa518
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901775351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3901775351
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.768034279
Short name T341
Test name
Test status
Simulation time 1854956708 ps
CPU time 9.27 seconds
Started Jul 23 06:23:55 PM PDT 24
Finished Jul 23 06:24:06 PM PDT 24
Peak memory 211324 kb
Host smart-c72ee113-3008-48a8-91b0-189987a2b800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768034279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.768034279
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1347790928
Short name T267
Test name
Test status
Simulation time 86003896322 ps
CPU time 272.51 seconds
Started Jul 23 06:23:53 PM PDT 24
Finished Jul 23 06:28:27 PM PDT 24
Peak memory 239944 kb
Host smart-17038421-708c-43f6-a82e-8f9c3b84f338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347790928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1347790928
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3016710651
Short name T144
Test name
Test status
Simulation time 175805560 ps
CPU time 9.53 seconds
Started Jul 23 06:23:52 PM PDT 24
Finished Jul 23 06:24:04 PM PDT 24
Peak memory 211944 kb
Host smart-ba88b109-d172-44e7-bb90-d39a8e5a31bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016710651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3016710651
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3471836936
Short name T132
Test name
Test status
Simulation time 950951117 ps
CPU time 11.13 seconds
Started Jul 23 06:23:53 PM PDT 24
Finished Jul 23 06:24:06 PM PDT 24
Peak memory 211384 kb
Host smart-3804ae70-7ac7-493a-ac3a-99d3e9efe233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471836936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3471836936
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1574877590
Short name T338
Test name
Test status
Simulation time 16090494900 ps
CPU time 40.73 seconds
Started Jul 23 06:23:50 PM PDT 24
Finished Jul 23 06:24:34 PM PDT 24
Peak memory 214172 kb
Host smart-a680d0ff-d8c4-43d5-9183-fe99f7fd12b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574877590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1574877590
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2650540516
Short name T295
Test name
Test status
Simulation time 1194454487 ps
CPU time 22.08 seconds
Started Jul 23 06:23:56 PM PDT 24
Finished Jul 23 06:24:19 PM PDT 24
Peak memory 214164 kb
Host smart-13c0a9cc-cbb5-4f3f-aa4a-cebc22277a9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650540516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2650540516
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1719449537
Short name T347
Test name
Test status
Simulation time 6654923151 ps
CPU time 13.91 seconds
Started Jul 23 06:22:49 PM PDT 24
Finished Jul 23 06:23:23 PM PDT 24
Peak memory 211380 kb
Host smart-755ce050-e114-46ec-8304-ed3acdb1bc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719449537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1719449537
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1068739086
Short name T234
Test name
Test status
Simulation time 39768580293 ps
CPU time 367.83 seconds
Started Jul 23 06:22:38 PM PDT 24
Finished Jul 23 06:29:04 PM PDT 24
Peak memory 226960 kb
Host smart-94010a07-6b69-4c89-ae4f-edbceaea8c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068739086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1068739086
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.996206623
Short name T140
Test name
Test status
Simulation time 11104329973 ps
CPU time 27.97 seconds
Started Jul 23 06:22:40 PM PDT 24
Finished Jul 23 06:23:25 PM PDT 24
Peak memory 212272 kb
Host smart-1295bc7a-a34d-4d8e-a17e-d71df478f381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996206623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.996206623
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2277660968
Short name T334
Test name
Test status
Simulation time 1526066537 ps
CPU time 13.27 seconds
Started Jul 23 06:22:49 PM PDT 24
Finished Jul 23 06:23:21 PM PDT 24
Peak memory 211340 kb
Host smart-bbe737cf-53bf-4758-8735-8da24d5e7814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2277660968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2277660968
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3213478660
Short name T25
Test name
Test status
Simulation time 599002329 ps
CPU time 51.2 seconds
Started Jul 23 06:22:48 PM PDT 24
Finished Jul 23 06:23:59 PM PDT 24
Peak memory 237772 kb
Host smart-f5c1e2a4-3b63-4259-8ddf-6cfbdbc958e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213478660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3213478660
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3267191551
Short name T170
Test name
Test status
Simulation time 531233950 ps
CPU time 9.89 seconds
Started Jul 23 06:22:42 PM PDT 24
Finished Jul 23 06:23:10 PM PDT 24
Peak memory 213852 kb
Host smart-998709b2-0ea5-4f30-a531-1b2413938059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267191551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3267191551
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3670639287
Short name T315
Test name
Test status
Simulation time 21517888681 ps
CPU time 58.24 seconds
Started Jul 23 06:22:39 PM PDT 24
Finished Jul 23 06:23:55 PM PDT 24
Peak memory 218132 kb
Host smart-96f1f6f6-42fc-4658-ad59-507ff2b3d927
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670639287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3670639287
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1912634415
Short name T76
Test name
Test status
Simulation time 6734973742 ps
CPU time 14.46 seconds
Started Jul 23 06:23:55 PM PDT 24
Finished Jul 23 06:24:11 PM PDT 24
Peak memory 211412 kb
Host smart-746d2334-6232-4c83-8e4e-2c9c276ff1a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912634415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1912634415
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2778381087
Short name T324
Test name
Test status
Simulation time 23077512177 ps
CPU time 228.23 seconds
Started Jul 23 06:23:59 PM PDT 24
Finished Jul 23 06:27:49 PM PDT 24
Peak memory 228672 kb
Host smart-bdc92c5f-8cc9-42cc-ae1b-908006edf214
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778381087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2778381087
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2373603137
Short name T216
Test name
Test status
Simulation time 4295775983 ps
CPU time 33.95 seconds
Started Jul 23 06:23:54 PM PDT 24
Finished Jul 23 06:24:30 PM PDT 24
Peak memory 212092 kb
Host smart-6523dd6e-8f33-442d-b88b-1cd4ad0daa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373603137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2373603137
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1851579020
Short name T304
Test name
Test status
Simulation time 191693554 ps
CPU time 5.32 seconds
Started Jul 23 06:23:59 PM PDT 24
Finished Jul 23 06:24:06 PM PDT 24
Peak memory 211360 kb
Host smart-71e10a95-923b-49b9-b336-c7843b8f577b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851579020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1851579020
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2861992333
Short name T318
Test name
Test status
Simulation time 2163009882 ps
CPU time 10.76 seconds
Started Jul 23 06:23:55 PM PDT 24
Finished Jul 23 06:24:07 PM PDT 24
Peak memory 213904 kb
Host smart-b7098bf4-202c-43c7-98dc-057b7b5b42b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861992333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2861992333
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4244812209
Short name T161
Test name
Test status
Simulation time 2286577595 ps
CPU time 20.85 seconds
Started Jul 23 06:23:55 PM PDT 24
Finished Jul 23 06:24:17 PM PDT 24
Peak memory 211876 kb
Host smart-6423e97a-85fe-499f-aee5-8523493fc78b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244812209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4244812209
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2798636175
Short name T77
Test name
Test status
Simulation time 86373646 ps
CPU time 4.36 seconds
Started Jul 23 06:24:00 PM PDT 24
Finished Jul 23 06:24:06 PM PDT 24
Peak memory 211368 kb
Host smart-8ece9adb-01ef-4e48-a83f-fdb48961c521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798636175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2798636175
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3763684002
Short name T331
Test name
Test status
Simulation time 268778874447 ps
CPU time 202.05 seconds
Started Jul 23 06:23:54 PM PDT 24
Finished Jul 23 06:27:18 PM PDT 24
Peak memory 212708 kb
Host smart-11819918-bd51-4633-88c7-e20531ac5ff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763684002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3763684002
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2110377696
Short name T343
Test name
Test status
Simulation time 11311408221 ps
CPU time 25.47 seconds
Started Jul 23 06:24:00 PM PDT 24
Finished Jul 23 06:24:27 PM PDT 24
Peak memory 211488 kb
Host smart-ede68e14-b6b0-40c5-a1a6-92d305d4110b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110377696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2110377696
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3789594894
Short name T346
Test name
Test status
Simulation time 1392809938 ps
CPU time 10.8 seconds
Started Jul 23 06:23:54 PM PDT 24
Finished Jul 23 06:24:06 PM PDT 24
Peak memory 211428 kb
Host smart-902ad4c4-971e-4b75-a97c-74c69862ff94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3789594894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3789594894
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1730394360
Short name T285
Test name
Test status
Simulation time 3191690485 ps
CPU time 27.88 seconds
Started Jul 23 06:24:00 PM PDT 24
Finished Jul 23 06:24:29 PM PDT 24
Peak memory 212668 kb
Host smart-2bad93f6-2249-426f-abe8-d32f42af72b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730394360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1730394360
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3169750896
Short name T138
Test name
Test status
Simulation time 7150969605 ps
CPU time 15.78 seconds
Started Jul 23 06:23:55 PM PDT 24
Finished Jul 23 06:24:12 PM PDT 24
Peak memory 211316 kb
Host smart-3551b191-9311-477f-94af-87a86464e867
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169750896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3169750896
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3672700397
Short name T261
Test name
Test status
Simulation time 3259278991 ps
CPU time 9.14 seconds
Started Jul 23 06:24:00 PM PDT 24
Finished Jul 23 06:24:11 PM PDT 24
Peak memory 211432 kb
Host smart-54d7c10d-1057-4a3f-97aa-bc2440780c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672700397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3672700397
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2261309934
Short name T185
Test name
Test status
Simulation time 48337668294 ps
CPU time 211.79 seconds
Started Jul 23 06:24:02 PM PDT 24
Finished Jul 23 06:27:35 PM PDT 24
Peak memory 237732 kb
Host smart-0bfa27cc-1da6-4b33-80f0-8f87d410d7f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261309934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2261309934
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4042462455
Short name T252
Test name
Test status
Simulation time 347599668 ps
CPU time 9.51 seconds
Started Jul 23 06:23:57 PM PDT 24
Finished Jul 23 06:24:08 PM PDT 24
Peak memory 211888 kb
Host smart-ae07ed02-873b-4eea-bb16-d8cf59c5df7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042462455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4042462455
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.410679489
Short name T272
Test name
Test status
Simulation time 6071323706 ps
CPU time 12.67 seconds
Started Jul 23 06:24:00 PM PDT 24
Finished Jul 23 06:24:14 PM PDT 24
Peak memory 211488 kb
Host smart-6ce69f1c-72bd-48ec-b379-f9285d280d11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410679489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.410679489
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2660961219
Short name T163
Test name
Test status
Simulation time 15732873315 ps
CPU time 32.26 seconds
Started Jul 23 06:24:00 PM PDT 24
Finished Jul 23 06:24:34 PM PDT 24
Peak memory 213960 kb
Host smart-6482bb9d-863d-4f78-89fe-03f7a76958ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660961219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2660961219
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2377873623
Short name T64
Test name
Test status
Simulation time 4109863371 ps
CPU time 19.95 seconds
Started Jul 23 06:23:59 PM PDT 24
Finished Jul 23 06:24:20 PM PDT 24
Peak memory 212164 kb
Host smart-4c0f4cb3-78e6-4eff-87ef-282feef76e20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377873623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2377873623
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1843242956
Short name T118
Test name
Test status
Simulation time 150992861558 ps
CPU time 1488.9 seconds
Started Jul 23 06:23:58 PM PDT 24
Finished Jul 23 06:48:48 PM PDT 24
Peak memory 233420 kb
Host smart-f74bda19-4a32-4e10-98e8-ce1db94e7102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843242956 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1843242956
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1049689376
Short name T227
Test name
Test status
Simulation time 168823179 ps
CPU time 9.5 seconds
Started Jul 23 06:24:01 PM PDT 24
Finished Jul 23 06:24:12 PM PDT 24
Peak memory 211884 kb
Host smart-b6322ba7-2ae5-4c83-8380-9526d7876fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049689376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1049689376
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.156779520
Short name T153
Test name
Test status
Simulation time 839883512 ps
CPU time 8.65 seconds
Started Jul 23 06:24:03 PM PDT 24
Finished Jul 23 06:24:12 PM PDT 24
Peak memory 211360 kb
Host smart-1b9478fa-f0dc-4f52-8b15-c5a3abd3ff56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=156779520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.156779520
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1780428185
Short name T36
Test name
Test status
Simulation time 511394061 ps
CPU time 14.11 seconds
Started Jul 23 06:23:59 PM PDT 24
Finished Jul 23 06:24:14 PM PDT 24
Peak memory 213100 kb
Host smart-b9effe1e-fc35-4b0c-9e04-30092cfc39ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780428185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1780428185
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1402461403
Short name T368
Test name
Test status
Simulation time 22645708388 ps
CPU time 54.03 seconds
Started Jul 23 06:23:59 PM PDT 24
Finished Jul 23 06:24:54 PM PDT 24
Peak memory 213984 kb
Host smart-ed315e9f-c6f3-47f1-80e1-9e7a14025f85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402461403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1402461403
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2308198178
Short name T370
Test name
Test status
Simulation time 2007148111 ps
CPU time 16.09 seconds
Started Jul 23 06:24:07 PM PDT 24
Finished Jul 23 06:24:25 PM PDT 24
Peak memory 211384 kb
Host smart-7b7b1b6b-fce3-4ebb-b447-42dfde819fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308198178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2308198178
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1718019731
Short name T278
Test name
Test status
Simulation time 4215792663 ps
CPU time 77.78 seconds
Started Jul 23 06:24:06 PM PDT 24
Finished Jul 23 06:25:26 PM PDT 24
Peak memory 228624 kb
Host smart-db54e05b-1352-4538-831b-ba09bed28eff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718019731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1718019731
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3970051988
Short name T349
Test name
Test status
Simulation time 2962286944 ps
CPU time 26.11 seconds
Started Jul 23 06:24:07 PM PDT 24
Finished Jul 23 06:24:35 PM PDT 24
Peak memory 212200 kb
Host smart-525a914a-22cc-4098-b4c8-7ce3e788d7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970051988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3970051988
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2597023987
Short name T156
Test name
Test status
Simulation time 1405369293 ps
CPU time 13.71 seconds
Started Jul 23 06:24:05 PM PDT 24
Finished Jul 23 06:24:20 PM PDT 24
Peak memory 211428 kb
Host smart-714284a3-2dc5-4ff9-9cf3-d1616b6ac0c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597023987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2597023987
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.951162908
Short name T220
Test name
Test status
Simulation time 3015858438 ps
CPU time 15.03 seconds
Started Jul 23 06:23:58 PM PDT 24
Finished Jul 23 06:24:15 PM PDT 24
Peak memory 212444 kb
Host smart-dc753f78-fc4d-4595-88e0-5efd37cea294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951162908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.951162908
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.13146777
Short name T280
Test name
Test status
Simulation time 6419188177 ps
CPU time 71.53 seconds
Started Jul 23 06:23:59 PM PDT 24
Finished Jul 23 06:25:13 PM PDT 24
Peak memory 217152 kb
Host smart-2ed0fe28-0133-49a3-b051-5436fdeb85d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13146777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.rom_ctrl_stress_all.13146777
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2004206345
Short name T206
Test name
Test status
Simulation time 6276896439 ps
CPU time 13.2 seconds
Started Jul 23 06:24:05 PM PDT 24
Finished Jul 23 06:24:21 PM PDT 24
Peak memory 211416 kb
Host smart-efc48a3f-9c03-4782-9f98-1b9ca9973eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004206345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2004206345
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.529619095
Short name T242
Test name
Test status
Simulation time 10301245028 ps
CPU time 130.65 seconds
Started Jul 23 06:24:07 PM PDT 24
Finished Jul 23 06:26:20 PM PDT 24
Peak memory 234944 kb
Host smart-92a7a03f-3b67-4d5e-afa8-9ac1411353a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529619095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.529619095
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.325756147
Short name T141
Test name
Test status
Simulation time 675286051 ps
CPU time 11.84 seconds
Started Jul 23 06:24:06 PM PDT 24
Finished Jul 23 06:24:21 PM PDT 24
Peak memory 211936 kb
Host smart-8ed164bf-f97b-4095-a87e-5934f492a3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325756147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.325756147
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1522896335
Short name T361
Test name
Test status
Simulation time 809101764 ps
CPU time 10.73 seconds
Started Jul 23 06:24:07 PM PDT 24
Finished Jul 23 06:24:20 PM PDT 24
Peak memory 211428 kb
Host smart-682c15cd-44ce-4ddd-b135-c71136c99c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522896335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1522896335
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3844492640
Short name T142
Test name
Test status
Simulation time 4018915752 ps
CPU time 25.95 seconds
Started Jul 23 06:24:05 PM PDT 24
Finished Jul 23 06:24:33 PM PDT 24
Peak memory 213476 kb
Host smart-83b03b2d-0667-45e5-88ec-db0efe70979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844492640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3844492640
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2811825816
Short name T230
Test name
Test status
Simulation time 831219239 ps
CPU time 24.05 seconds
Started Jul 23 06:24:06 PM PDT 24
Finished Jul 23 06:24:32 PM PDT 24
Peak memory 215624 kb
Host smart-e8563249-ec6f-41ff-a651-351ee88a4183
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811825816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2811825816
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4285444731
Short name T165
Test name
Test status
Simulation time 3022342290 ps
CPU time 13.51 seconds
Started Jul 23 06:24:06 PM PDT 24
Finished Jul 23 06:24:22 PM PDT 24
Peak memory 211444 kb
Host smart-fa6cb556-24e3-4c7e-ab64-78db57f2fc1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285444731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4285444731
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3942272684
Short name T42
Test name
Test status
Simulation time 12511243835 ps
CPU time 187.35 seconds
Started Jul 23 06:24:07 PM PDT 24
Finished Jul 23 06:27:16 PM PDT 24
Peak memory 238000 kb
Host smart-74c58190-7d0c-4e7b-94a2-62c64807f2d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942272684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3942272684
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1231074044
Short name T358
Test name
Test status
Simulation time 8128136911 ps
CPU time 32.55 seconds
Started Jul 23 06:24:08 PM PDT 24
Finished Jul 23 06:24:42 PM PDT 24
Peak memory 212332 kb
Host smart-53de2701-dcc2-4f95-8d7e-19454bf680e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231074044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1231074044
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1611903865
Short name T356
Test name
Test status
Simulation time 6585226239 ps
CPU time 14.74 seconds
Started Jul 23 06:24:05 PM PDT 24
Finished Jul 23 06:24:22 PM PDT 24
Peak memory 211440 kb
Host smart-3d03ec13-4f17-4504-af94-f95eb6638aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611903865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1611903865
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2299967139
Short name T134
Test name
Test status
Simulation time 758084322 ps
CPU time 10.28 seconds
Started Jul 23 06:24:05 PM PDT 24
Finished Jul 23 06:24:18 PM PDT 24
Peak memory 213424 kb
Host smart-4e250535-c32a-4c6f-b23b-19c65671a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299967139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2299967139
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2879846378
Short name T218
Test name
Test status
Simulation time 3275487001 ps
CPU time 28.11 seconds
Started Jul 23 06:24:06 PM PDT 24
Finished Jul 23 06:24:37 PM PDT 24
Peak memory 213912 kb
Host smart-7886fb51-289e-4d29-b5cc-c6783b001ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879846378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2879846378
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2132565934
Short name T62
Test name
Test status
Simulation time 429488709 ps
CPU time 5.78 seconds
Started Jul 23 06:24:13 PM PDT 24
Finished Jul 23 06:24:20 PM PDT 24
Peak memory 211320 kb
Host smart-3e5272c5-3b3e-43bd-9e7e-6bc6c63b0847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132565934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2132565934
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4247036301
Short name T201
Test name
Test status
Simulation time 108326050780 ps
CPU time 379.92 seconds
Started Jul 23 06:24:07 PM PDT 24
Finished Jul 23 06:30:29 PM PDT 24
Peak memory 228652 kb
Host smart-03578323-7f2b-4812-ac69-493f0b74c52a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247036301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4247036301
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3880917537
Short name T100
Test name
Test status
Simulation time 693193433 ps
CPU time 9.48 seconds
Started Jul 23 06:24:12 PM PDT 24
Finished Jul 23 06:24:23 PM PDT 24
Peak memory 211988 kb
Host smart-12016957-c9e6-4b66-abac-06193785a0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880917537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3880917537
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1572493733
Short name T150
Test name
Test status
Simulation time 878587888 ps
CPU time 11.14 seconds
Started Jul 23 06:24:07 PM PDT 24
Finished Jul 23 06:24:20 PM PDT 24
Peak memory 211428 kb
Host smart-299b45cb-e303-40f5-b103-a4337a6834c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572493733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1572493733
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1902092144
Short name T221
Test name
Test status
Simulation time 195646852 ps
CPU time 10.17 seconds
Started Jul 23 06:24:08 PM PDT 24
Finished Jul 23 06:24:20 PM PDT 24
Peak memory 213452 kb
Host smart-d8f66a58-418c-47fa-a056-adf357f455b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902092144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1902092144
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2314000358
Short name T348
Test name
Test status
Simulation time 2987901873 ps
CPU time 41.42 seconds
Started Jul 23 06:24:06 PM PDT 24
Finished Jul 23 06:24:50 PM PDT 24
Peak memory 216164 kb
Host smart-d5aba2b8-8748-46d3-a1d2-6cac94feda96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314000358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2314000358
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.361467431
Short name T360
Test name
Test status
Simulation time 488956187 ps
CPU time 4.39 seconds
Started Jul 23 06:24:15 PM PDT 24
Finished Jul 23 06:24:22 PM PDT 24
Peak memory 211384 kb
Host smart-2688bfb2-de77-44a6-8efa-80a3bdc34280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361467431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.361467431
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3492206462
Short name T194
Test name
Test status
Simulation time 422317230 ps
CPU time 12.67 seconds
Started Jul 23 06:24:12 PM PDT 24
Finished Jul 23 06:24:26 PM PDT 24
Peak memory 211864 kb
Host smart-d43bc83d-85df-4b71-b32a-221d2f523c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492206462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3492206462
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.776395112
Short name T198
Test name
Test status
Simulation time 671528790 ps
CPU time 9.83 seconds
Started Jul 23 06:24:10 PM PDT 24
Finished Jul 23 06:24:21 PM PDT 24
Peak memory 211360 kb
Host smart-0dd9bf35-1d20-41f8-9936-3bfbbbee0991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776395112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.776395112
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.398837108
Short name T104
Test name
Test status
Simulation time 3606146914 ps
CPU time 22.64 seconds
Started Jul 23 06:24:18 PM PDT 24
Finished Jul 23 06:24:45 PM PDT 24
Peak memory 213244 kb
Host smart-5325c7c1-3ce7-4a3f-a996-7a3e326505f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398837108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.398837108
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1955764914
Short name T31
Test name
Test status
Simulation time 1962432220 ps
CPU time 14.04 seconds
Started Jul 23 06:24:12 PM PDT 24
Finished Jul 23 06:24:27 PM PDT 24
Peak memory 211520 kb
Host smart-eb3dca00-7fb5-429d-b3bd-dcf1e1fe99b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955764914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1955764914
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3786033525
Short name T56
Test name
Test status
Simulation time 139515233862 ps
CPU time 955.63 seconds
Started Jul 23 06:24:12 PM PDT 24
Finished Jul 23 06:40:10 PM PDT 24
Peak memory 235860 kb
Host smart-e4fc613b-e24a-47c5-8553-643ca3294759
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786033525 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3786033525
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3529595940
Short name T297
Test name
Test status
Simulation time 1939466336 ps
CPU time 16.26 seconds
Started Jul 23 06:24:15 PM PDT 24
Finished Jul 23 06:24:35 PM PDT 24
Peak memory 211404 kb
Host smart-cec285f5-7fb0-4582-8187-19b7db724b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529595940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3529595940
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.337138092
Short name T192
Test name
Test status
Simulation time 7525506501 ps
CPU time 129.75 seconds
Started Jul 23 06:24:15 PM PDT 24
Finished Jul 23 06:26:28 PM PDT 24
Peak memory 239256 kb
Host smart-28cbf9ff-1834-4036-ac8e-182eb0fa31de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337138092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.337138092
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3275832595
Short name T302
Test name
Test status
Simulation time 3952223965 ps
CPU time 16.52 seconds
Started Jul 23 06:24:14 PM PDT 24
Finished Jul 23 06:24:33 PM PDT 24
Peak memory 211888 kb
Host smart-5d7ef2db-e942-4469-bf2d-aae31888238a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275832595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3275832595
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.718211646
Short name T271
Test name
Test status
Simulation time 100975892 ps
CPU time 5.67 seconds
Started Jul 23 06:24:13 PM PDT 24
Finished Jul 23 06:24:20 PM PDT 24
Peak memory 211320 kb
Host smart-89567c4b-2a8a-4549-9498-749f9965f97b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=718211646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.718211646
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4251322120
Short name T363
Test name
Test status
Simulation time 4441867326 ps
CPU time 37.46 seconds
Started Jul 23 06:24:18 PM PDT 24
Finished Jul 23 06:24:59 PM PDT 24
Peak memory 213572 kb
Host smart-eed6dec3-149d-4d2f-9560-db1a176d9e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251322120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4251322120
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1108514521
Short name T210
Test name
Test status
Simulation time 25404923692 ps
CPU time 46.7 seconds
Started Jul 23 06:24:18 PM PDT 24
Finished Jul 23 06:25:09 PM PDT 24
Peak memory 213060 kb
Host smart-86cf3f1c-7248-4312-87dc-5e0572634404
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108514521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1108514521
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3297716961
Short name T200
Test name
Test status
Simulation time 616426553 ps
CPU time 5.33 seconds
Started Jul 23 06:22:45 PM PDT 24
Finished Jul 23 06:23:09 PM PDT 24
Peak memory 211384 kb
Host smart-8d1052a0-dce0-479f-ad43-e4f72d8bf347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297716961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3297716961
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3240406593
Short name T306
Test name
Test status
Simulation time 23703923108 ps
CPU time 258.54 seconds
Started Jul 23 06:22:45 PM PDT 24
Finished Jul 23 06:27:23 PM PDT 24
Peak memory 237060 kb
Host smart-68677bab-d589-4373-95b3-33c4d223466a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240406593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3240406593
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1609713885
Short name T180
Test name
Test status
Simulation time 4224356736 ps
CPU time 33.48 seconds
Started Jul 23 06:22:45 PM PDT 24
Finished Jul 23 06:23:38 PM PDT 24
Peak memory 211928 kb
Host smart-56964b69-6d76-4a40-ad30-f4aa615ccc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609713885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1609713885
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3642893681
Short name T106
Test name
Test status
Simulation time 896796490 ps
CPU time 7.85 seconds
Started Jul 23 06:22:45 PM PDT 24
Finished Jul 23 06:23:12 PM PDT 24
Peak memory 211408 kb
Host smart-faeb1c36-9a44-41d0-8354-3bd8f180044d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3642893681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3642893681
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.48016721
Short name T23
Test name
Test status
Simulation time 903287013 ps
CPU time 52.56 seconds
Started Jul 23 06:22:47 PM PDT 24
Finished Jul 23 06:23:58 PM PDT 24
Peak memory 235788 kb
Host smart-2cc996f5-2a9d-462a-89ba-ddbb304ad88a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48016721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.48016721
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2130886470
Short name T65
Test name
Test status
Simulation time 34135669885 ps
CPU time 31.05 seconds
Started Jul 23 06:22:46 PM PDT 24
Finished Jul 23 06:23:36 PM PDT 24
Peak memory 214288 kb
Host smart-851a28e8-48de-4400-b2c5-ccc784cd0c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130886470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2130886470
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1712814330
Short name T37
Test name
Test status
Simulation time 1786878679 ps
CPU time 23.35 seconds
Started Jul 23 06:22:45 PM PDT 24
Finished Jul 23 06:23:27 PM PDT 24
Peak memory 214076 kb
Host smart-faa797af-86ac-40c7-b673-983b968dff82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712814330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1712814330
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1742249693
Short name T57
Test name
Test status
Simulation time 35729396143 ps
CPU time 918.9 seconds
Started Jul 23 06:22:46 PM PDT 24
Finished Jul 23 06:38:24 PM PDT 24
Peak memory 224268 kb
Host smart-7ef49e99-1240-4f5f-80f8-a936b087b713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742249693 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1742249693
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2129805475
Short name T187
Test name
Test status
Simulation time 7749609170 ps
CPU time 16.09 seconds
Started Jul 23 06:24:18 PM PDT 24
Finished Jul 23 06:24:38 PM PDT 24
Peak memory 211424 kb
Host smart-4cd341bd-844c-4a1c-a94b-00140416869d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129805475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2129805475
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.835676810
Short name T339
Test name
Test status
Simulation time 173666596663 ps
CPU time 429.79 seconds
Started Jul 23 06:24:16 PM PDT 24
Finished Jul 23 06:31:30 PM PDT 24
Peak memory 237936 kb
Host smart-21fc3a4c-49af-4b1e-ac28-f429efdacaa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835676810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.835676810
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3156712894
Short name T34
Test name
Test status
Simulation time 6858562478 ps
CPU time 15.43 seconds
Started Jul 23 06:24:11 PM PDT 24
Finished Jul 23 06:24:28 PM PDT 24
Peak memory 211452 kb
Host smart-d83a3cf5-9394-4edb-8a29-8b66457d61d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156712894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3156712894
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3455206239
Short name T196
Test name
Test status
Simulation time 9926414519 ps
CPU time 23.98 seconds
Started Jul 23 06:24:14 PM PDT 24
Finished Jul 23 06:24:40 PM PDT 24
Peak memory 214116 kb
Host smart-13411ba6-fe6a-4174-bcf5-886125ccadbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455206239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3455206239
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2474970684
Short name T212
Test name
Test status
Simulation time 67295110208 ps
CPU time 36 seconds
Started Jul 23 06:24:12 PM PDT 24
Finished Jul 23 06:24:50 PM PDT 24
Peak memory 216392 kb
Host smart-9a520b31-f846-4a18-94e3-ae051d626d18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474970684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2474970684
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1718965462
Short name T17
Test name
Test status
Simulation time 295997078323 ps
CPU time 2708.06 seconds
Started Jul 23 06:24:18 PM PDT 24
Finished Jul 23 07:09:31 PM PDT 24
Peak memory 238872 kb
Host smart-401e29ce-c403-4b51-9ff0-c6387eafb4bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718965462 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1718965462
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4219520262
Short name T256
Test name
Test status
Simulation time 865441607 ps
CPU time 5.93 seconds
Started Jul 23 06:24:18 PM PDT 24
Finished Jul 23 06:24:28 PM PDT 24
Peak memory 211344 kb
Host smart-94aa81a5-f915-4c37-b4f4-45e920379f47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219520262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4219520262
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2440587802
Short name T13
Test name
Test status
Simulation time 1256725470 ps
CPU time 71.93 seconds
Started Jul 23 06:24:19 PM PDT 24
Finished Jul 23 06:25:35 PM PDT 24
Peak memory 233240 kb
Host smart-117e4933-ba55-4aef-a70f-e7c5457887ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440587802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2440587802
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2581907941
Short name T4
Test name
Test status
Simulation time 2729038408 ps
CPU time 25.96 seconds
Started Jul 23 06:24:19 PM PDT 24
Finished Jul 23 06:24:49 PM PDT 24
Peak memory 211892 kb
Host smart-3807de10-87ff-42db-81d9-cee5e7ae3281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581907941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2581907941
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1561344877
Short name T274
Test name
Test status
Simulation time 2629414839 ps
CPU time 13.4 seconds
Started Jul 23 06:24:19 PM PDT 24
Finished Jul 23 06:24:36 PM PDT 24
Peak memory 211516 kb
Host smart-4609af69-fb96-4f3f-99ff-f2a12147e66c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1561344877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1561344877
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2429868366
Short name T10
Test name
Test status
Simulation time 346767295 ps
CPU time 12.27 seconds
Started Jul 23 06:24:17 PM PDT 24
Finished Jul 23 06:24:34 PM PDT 24
Peak memory 213316 kb
Host smart-1107009c-fafa-4c63-b690-095a563e9330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429868366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2429868366
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2460667166
Short name T276
Test name
Test status
Simulation time 2461526640 ps
CPU time 24.57 seconds
Started Jul 23 06:24:20 PM PDT 24
Finished Jul 23 06:24:48 PM PDT 24
Peak memory 214704 kb
Host smart-722c8f09-5788-425f-8cf6-a60b75624a92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460667166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2460667166
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1141036598
Short name T229
Test name
Test status
Simulation time 592020435 ps
CPU time 8.39 seconds
Started Jul 23 06:24:27 PM PDT 24
Finished Jul 23 06:24:37 PM PDT 24
Peak memory 211400 kb
Host smart-85ea79b5-bc23-4bb3-a39b-368b130f738b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141036598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1141036598
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2252175148
Short name T44
Test name
Test status
Simulation time 1121589611 ps
CPU time 64.75 seconds
Started Jul 23 06:24:17 PM PDT 24
Finished Jul 23 06:25:26 PM PDT 24
Peak memory 228600 kb
Host smart-45b7570b-6d89-4d53-9a44-b234f80b0948
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252175148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2252175148
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3388754079
Short name T50
Test name
Test status
Simulation time 665150514 ps
CPU time 9.58 seconds
Started Jul 23 06:24:18 PM PDT 24
Finished Jul 23 06:24:32 PM PDT 24
Peak memory 211964 kb
Host smart-723687c8-27a1-4e7d-91ea-3ea5022a6700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388754079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3388754079
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.191943849
Short name T367
Test name
Test status
Simulation time 5915941098 ps
CPU time 13.09 seconds
Started Jul 23 06:24:19 PM PDT 24
Finished Jul 23 06:24:36 PM PDT 24
Peak memory 211496 kb
Host smart-113a9423-16ed-47d3-a925-2fb4371fcbd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=191943849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.191943849
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1280411587
Short name T162
Test name
Test status
Simulation time 2315869222 ps
CPU time 28.3 seconds
Started Jul 23 06:24:17 PM PDT 24
Finished Jul 23 06:24:50 PM PDT 24
Peak memory 213792 kb
Host smart-a3501e16-f4cb-4b76-8397-36ec4b50a5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280411587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1280411587
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2098888414
Short name T70
Test name
Test status
Simulation time 6470096596 ps
CPU time 48.66 seconds
Started Jul 23 06:24:21 PM PDT 24
Finished Jul 23 06:25:12 PM PDT 24
Peak memory 217036 kb
Host smart-55beb915-bbc5-4b17-a46b-7a709b88896f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098888414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2098888414
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.151516886
Short name T366
Test name
Test status
Simulation time 514424595291 ps
CPU time 4717.53 seconds
Started Jul 23 06:24:29 PM PDT 24
Finished Jul 23 07:43:08 PM PDT 24
Peak memory 250200 kb
Host smart-a174418d-9b07-488e-8726-d14979613314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151516886 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.151516886
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1827278844
Short name T246
Test name
Test status
Simulation time 12562902401 ps
CPU time 13.23 seconds
Started Jul 23 06:24:28 PM PDT 24
Finished Jul 23 06:24:43 PM PDT 24
Peak memory 211436 kb
Host smart-c450924c-b8a6-4f57-93a2-51e2fafb8150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827278844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1827278844
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.630732801
Short name T213
Test name
Test status
Simulation time 50771411578 ps
CPU time 250.74 seconds
Started Jul 23 06:24:27 PM PDT 24
Finished Jul 23 06:28:40 PM PDT 24
Peak memory 234952 kb
Host smart-4bf9b0cc-c34c-48c1-aa0f-aaef199b10ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630732801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.630732801
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2780064329
Short name T176
Test name
Test status
Simulation time 16431697283 ps
CPU time 33.6 seconds
Started Jul 23 06:24:28 PM PDT 24
Finished Jul 23 06:25:03 PM PDT 24
Peak memory 212228 kb
Host smart-94f4e523-32d7-4d08-8470-ccc6ae7cf7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780064329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2780064329
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2857524663
Short name T364
Test name
Test status
Simulation time 1338659532 ps
CPU time 13 seconds
Started Jul 23 06:24:27 PM PDT 24
Finished Jul 23 06:24:42 PM PDT 24
Peak memory 211412 kb
Host smart-32a4057a-feab-447d-9281-3845a2e1878a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857524663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2857524663
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2019815202
Short name T3
Test name
Test status
Simulation time 9940374666 ps
CPU time 26.79 seconds
Started Jul 23 06:24:26 PM PDT 24
Finished Jul 23 06:24:55 PM PDT 24
Peak memory 214132 kb
Host smart-ade854d3-0e90-46dc-9580-884cf74a9cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019815202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2019815202
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1797000083
Short name T168
Test name
Test status
Simulation time 6886203521 ps
CPU time 62.5 seconds
Started Jul 23 06:24:28 PM PDT 24
Finished Jul 23 06:25:32 PM PDT 24
Peak memory 217624 kb
Host smart-c804f4a5-a235-4223-b4ce-741d644b6110
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797000083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1797000083
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.807890674
Short name T351
Test name
Test status
Simulation time 5252887721 ps
CPU time 203.32 seconds
Started Jul 23 06:24:25 PM PDT 24
Finished Jul 23 06:27:50 PM PDT 24
Peak memory 223140 kb
Host smart-85e66f65-2395-4dc4-b0dc-4cd0e2a2adb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807890674 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.807890674
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.270246825
Short name T311
Test name
Test status
Simulation time 3759521452 ps
CPU time 15.29 seconds
Started Jul 23 06:24:26 PM PDT 24
Finished Jul 23 06:24:43 PM PDT 24
Peak memory 211432 kb
Host smart-74bc3b89-db4e-4244-9e25-ac77b99fc4e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270246825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.270246825
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1557086753
Short name T233
Test name
Test status
Simulation time 7671947071 ps
CPU time 112.94 seconds
Started Jul 23 06:24:27 PM PDT 24
Finished Jul 23 06:26:22 PM PDT 24
Peak memory 213680 kb
Host smart-1f9e8d47-b458-4b5e-8d38-c72434d95570
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557086753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1557086753
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1532402105
Short name T171
Test name
Test status
Simulation time 3948977927 ps
CPU time 31.02 seconds
Started Jul 23 06:24:25 PM PDT 24
Finished Jul 23 06:24:57 PM PDT 24
Peak memory 211968 kb
Host smart-eb89c8f7-0f8a-4a5e-8463-c2d816b6d85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532402105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1532402105
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3017065799
Short name T188
Test name
Test status
Simulation time 1685044838 ps
CPU time 14.87 seconds
Started Jul 23 06:24:27 PM PDT 24
Finished Jul 23 06:24:44 PM PDT 24
Peak memory 211412 kb
Host smart-1b168a5d-e84e-46a9-9d73-569a2360dea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017065799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3017065799
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2417503735
Short name T337
Test name
Test status
Simulation time 761059619 ps
CPU time 10.12 seconds
Started Jul 23 06:24:26 PM PDT 24
Finished Jul 23 06:24:39 PM PDT 24
Peak memory 213704 kb
Host smart-aa233b0a-32c6-4ed6-bcb3-23972f065ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417503735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2417503735
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.992157672
Short name T248
Test name
Test status
Simulation time 11281811879 ps
CPU time 29.17 seconds
Started Jul 23 06:24:27 PM PDT 24
Finished Jul 23 06:24:58 PM PDT 24
Peak memory 213704 kb
Host smart-aa3ddb88-7e7d-4c8a-ad50-5a8d84e73d6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992157672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.992157672
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3102228650
Short name T60
Test name
Test status
Simulation time 168846454217 ps
CPU time 3317.28 seconds
Started Jul 23 06:24:30 PM PDT 24
Finished Jul 23 07:19:48 PM PDT 24
Peak memory 252248 kb
Host smart-da037c99-3f1e-4072-a129-96881cf34fb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102228650 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3102228650
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1107332806
Short name T299
Test name
Test status
Simulation time 1950473058 ps
CPU time 10.47 seconds
Started Jul 23 06:24:26 PM PDT 24
Finished Jul 23 06:24:38 PM PDT 24
Peak memory 211396 kb
Host smart-69bd129e-e014-4bc0-9a18-c87eadb19f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107332806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1107332806
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2881204888
Short name T225
Test name
Test status
Simulation time 34563723178 ps
CPU time 172.2 seconds
Started Jul 23 06:24:33 PM PDT 24
Finished Jul 23 06:27:27 PM PDT 24
Peak memory 225100 kb
Host smart-4d852c3f-4ab6-40f5-9dba-7697a400a33e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881204888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2881204888
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3875322281
Short name T219
Test name
Test status
Simulation time 4156480631 ps
CPU time 21.1 seconds
Started Jul 23 06:24:31 PM PDT 24
Finished Jul 23 06:24:53 PM PDT 24
Peak memory 212264 kb
Host smart-5644e76e-bfc2-4ba1-9b1d-e769841219a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875322281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3875322281
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1927895158
Short name T21
Test name
Test status
Simulation time 964651613 ps
CPU time 10.89 seconds
Started Jul 23 06:24:27 PM PDT 24
Finished Jul 23 06:24:40 PM PDT 24
Peak memory 211312 kb
Host smart-d6146b65-809d-4d36-8175-71bde909fd22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927895158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1927895158
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.549807014
Short name T313
Test name
Test status
Simulation time 10579076738 ps
CPU time 26.8 seconds
Started Jul 23 06:24:26 PM PDT 24
Finished Jul 23 06:24:54 PM PDT 24
Peak memory 213780 kb
Host smart-75d2d70c-4a74-470c-8426-73460d5ed35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549807014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.549807014
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2144844716
Short name T182
Test name
Test status
Simulation time 3507635821 ps
CPU time 59.79 seconds
Started Jul 23 06:24:26 PM PDT 24
Finished Jul 23 06:25:29 PM PDT 24
Peak memory 217828 kb
Host smart-52e49a4c-2d92-43c2-9184-29bbad2bada1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144844716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2144844716
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1102280870
Short name T270
Test name
Test status
Simulation time 516323061 ps
CPU time 5.09 seconds
Started Jul 23 06:24:35 PM PDT 24
Finished Jul 23 06:24:41 PM PDT 24
Peak memory 211364 kb
Host smart-814c3dca-bf35-4bc9-ab4e-926e855df4e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102280870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1102280870
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1737941304
Short name T238
Test name
Test status
Simulation time 29558409580 ps
CPU time 294.85 seconds
Started Jul 23 06:24:34 PM PDT 24
Finished Jul 23 06:29:31 PM PDT 24
Peak memory 236872 kb
Host smart-3d528377-e127-4fba-b545-ad4cbfda7341
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737941304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1737941304
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2746248747
Short name T101
Test name
Test status
Simulation time 16311075340 ps
CPU time 24.9 seconds
Started Jul 23 06:24:33 PM PDT 24
Finished Jul 23 06:25:00 PM PDT 24
Peak memory 212276 kb
Host smart-f896286f-d593-4ec4-b473-aa4b2dfa1ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746248747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2746248747
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3310112962
Short name T214
Test name
Test status
Simulation time 3968069638 ps
CPU time 10.84 seconds
Started Jul 23 06:24:26 PM PDT 24
Finished Jul 23 06:24:38 PM PDT 24
Peak memory 211472 kb
Host smart-9bab3a1b-5c46-4450-ad9c-5572a95db1ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310112962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3310112962
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3936333090
Short name T305
Test name
Test status
Simulation time 3010230508 ps
CPU time 32.44 seconds
Started Jul 23 06:24:26 PM PDT 24
Finished Jul 23 06:25:01 PM PDT 24
Peak memory 213356 kb
Host smart-9b19597f-a18f-4cdd-8e13-2c3de6a44f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936333090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3936333090
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1240557396
Short name T5
Test name
Test status
Simulation time 970556211 ps
CPU time 16.06 seconds
Started Jul 23 06:24:26 PM PDT 24
Finished Jul 23 06:24:45 PM PDT 24
Peak memory 213976 kb
Host smart-19d3d164-e9eb-4818-a574-a6faf432e0aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240557396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1240557396
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1073846215
Short name T58
Test name
Test status
Simulation time 256368452694 ps
CPU time 2695.81 seconds
Started Jul 23 06:24:33 PM PDT 24
Finished Jul 23 07:09:31 PM PDT 24
Peak memory 245180 kb
Host smart-5d186ac9-1a2d-4cb0-9bd4-9fb1a007f9b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073846215 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1073846215
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.823356355
Short name T316
Test name
Test status
Simulation time 4623535090 ps
CPU time 11.02 seconds
Started Jul 23 06:24:35 PM PDT 24
Finished Jul 23 06:24:47 PM PDT 24
Peak memory 211444 kb
Host smart-a37683da-eecd-4ea2-b252-46d2c0e83772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823356355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.823356355
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3995370123
Short name T326
Test name
Test status
Simulation time 722638668695 ps
CPU time 577.8 seconds
Started Jul 23 06:24:32 PM PDT 24
Finished Jul 23 06:34:11 PM PDT 24
Peak memory 237116 kb
Host smart-ea532db4-0ca6-499f-834a-ed280244fe16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995370123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3995370123
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.178371627
Short name T20
Test name
Test status
Simulation time 7394799297 ps
CPU time 15.81 seconds
Started Jul 23 06:24:34 PM PDT 24
Finished Jul 23 06:24:52 PM PDT 24
Peak memory 211484 kb
Host smart-59548042-9097-4be1-994b-f79e63d76ede
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=178371627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.178371627
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4085668683
Short name T232
Test name
Test status
Simulation time 1864586677 ps
CPU time 18.68 seconds
Started Jul 23 06:24:34 PM PDT 24
Finished Jul 23 06:24:55 PM PDT 24
Peak memory 212444 kb
Host smart-40db01f4-c594-49d3-a655-70fe151cdf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085668683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4085668683
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2280550378
Short name T48
Test name
Test status
Simulation time 3361875239 ps
CPU time 33.56 seconds
Started Jul 23 06:24:31 PM PDT 24
Finished Jul 23 06:25:06 PM PDT 24
Peak memory 212724 kb
Host smart-b458d302-24e8-4777-83d0-635d24aefa50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280550378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2280550378
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3015481710
Short name T292
Test name
Test status
Simulation time 85853293 ps
CPU time 4.36 seconds
Started Jul 23 06:24:32 PM PDT 24
Finished Jul 23 06:24:38 PM PDT 24
Peak memory 211376 kb
Host smart-c9283ce5-98af-4c18-8491-cb3c7490a863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015481710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3015481710
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.953079128
Short name T217
Test name
Test status
Simulation time 75334044463 ps
CPU time 350 seconds
Started Jul 23 06:24:33 PM PDT 24
Finished Jul 23 06:30:25 PM PDT 24
Peak memory 237904 kb
Host smart-32c82107-27f1-4ab0-8205-34455b12e663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953079128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.953079128
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1917060306
Short name T202
Test name
Test status
Simulation time 692017724 ps
CPU time 14.51 seconds
Started Jul 23 06:24:32 PM PDT 24
Finished Jul 23 06:24:48 PM PDT 24
Peak memory 211864 kb
Host smart-70a53239-6178-4731-a525-90329fa78f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917060306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1917060306
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2545929295
Short name T231
Test name
Test status
Simulation time 528192818 ps
CPU time 8.56 seconds
Started Jul 23 06:24:34 PM PDT 24
Finished Jul 23 06:24:44 PM PDT 24
Peak memory 211424 kb
Host smart-b9968172-97ee-45da-8c1d-35e251191db0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545929295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2545929295
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2409857147
Short name T344
Test name
Test status
Simulation time 2064962334 ps
CPU time 19.24 seconds
Started Jul 23 06:24:33 PM PDT 24
Finished Jul 23 06:24:54 PM PDT 24
Peak memory 213240 kb
Host smart-a9fb15f7-d916-4a98-8975-bdaf2a54d514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409857147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2409857147
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1788502232
Short name T284
Test name
Test status
Simulation time 489785816 ps
CPU time 26.16 seconds
Started Jul 23 06:24:34 PM PDT 24
Finished Jul 23 06:25:02 PM PDT 24
Peak memory 215556 kb
Host smart-fc727bd7-db44-4f19-91ae-06856b41c32f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788502232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1788502232
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.982793603
Short name T303
Test name
Test status
Simulation time 10429286519 ps
CPU time 11.67 seconds
Started Jul 23 06:24:38 PM PDT 24
Finished Jul 23 06:24:51 PM PDT 24
Peak memory 211392 kb
Host smart-4ab6cdb0-4132-4d47-b30c-52b48669dbc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982793603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.982793603
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3326640242
Short name T251
Test name
Test status
Simulation time 1683079841 ps
CPU time 101.46 seconds
Started Jul 23 06:24:34 PM PDT 24
Finished Jul 23 06:26:17 PM PDT 24
Peak memory 212624 kb
Host smart-c4d02e11-e025-437e-aae8-53be75561b08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326640242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3326640242
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1599214997
Short name T32
Test name
Test status
Simulation time 692103920 ps
CPU time 9.41 seconds
Started Jul 23 06:24:35 PM PDT 24
Finished Jul 23 06:24:46 PM PDT 24
Peak memory 212128 kb
Host smart-1e46e185-e48d-4d99-a362-fac6d3b0bd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599214997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1599214997
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2285089118
Short name T63
Test name
Test status
Simulation time 270882444 ps
CPU time 7.15 seconds
Started Jul 23 06:24:33 PM PDT 24
Finished Jul 23 06:24:41 PM PDT 24
Peak memory 211412 kb
Host smart-89eca65e-455b-4409-9055-37063b1f779f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285089118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2285089118
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3946612118
Short name T244
Test name
Test status
Simulation time 17166836192 ps
CPU time 29.91 seconds
Started Jul 23 06:24:34 PM PDT 24
Finished Jul 23 06:25:06 PM PDT 24
Peak memory 213960 kb
Host smart-f64de7cf-5900-4c00-9007-c08e9f8499d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946612118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3946612118
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1269248716
Short name T7
Test name
Test status
Simulation time 17295901408 ps
CPU time 49.34 seconds
Started Jul 23 06:24:32 PM PDT 24
Finished Jul 23 06:25:23 PM PDT 24
Peak memory 216592 kb
Host smart-89a00a96-7b71-4d53-81e0-10db9222ac96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269248716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1269248716
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3034111297
Short name T105
Test name
Test status
Simulation time 109491219930 ps
CPU time 1123.82 seconds
Started Jul 23 06:24:37 PM PDT 24
Finished Jul 23 06:43:22 PM PDT 24
Peak memory 230024 kb
Host smart-68f9d41b-0cdf-4b55-bf49-234a4a3c5d19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034111297 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3034111297
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.137844490
Short name T308
Test name
Test status
Simulation time 172590048 ps
CPU time 5.59 seconds
Started Jul 23 06:22:51 PM PDT 24
Finished Jul 23 06:23:17 PM PDT 24
Peak memory 211384 kb
Host smart-292db836-d5a5-4470-9c05-3de3d0d48c86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137844490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.137844490
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.235661149
Short name T54
Test name
Test status
Simulation time 153681546506 ps
CPU time 388.14 seconds
Started Jul 23 06:22:46 PM PDT 24
Finished Jul 23 06:29:34 PM PDT 24
Peak memory 236620 kb
Host smart-8c01ac4b-f6e1-4ebe-9962-d3748fb51ca3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235661149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.235661149
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3435358748
Short name T253
Test name
Test status
Simulation time 2471129067 ps
CPU time 17.5 seconds
Started Jul 23 06:22:45 PM PDT 24
Finished Jul 23 06:23:22 PM PDT 24
Peak memory 211976 kb
Host smart-7c0331ad-37c6-48e0-a517-21e6365f8777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435358748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3435358748
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.579647082
Short name T30
Test name
Test status
Simulation time 97018085 ps
CPU time 5.46 seconds
Started Jul 23 06:22:49 PM PDT 24
Finished Jul 23 06:23:14 PM PDT 24
Peak memory 211380 kb
Host smart-aec5a602-2c6c-43c5-b535-b659352bb476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579647082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.579647082
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3573881436
Short name T173
Test name
Test status
Simulation time 2981065915 ps
CPU time 26.65 seconds
Started Jul 23 06:22:46 PM PDT 24
Finished Jul 23 06:23:32 PM PDT 24
Peak memory 213392 kb
Host smart-cef989c3-e355-4c4b-9816-749d69fb7e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573881436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3573881436
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2693318325
Short name T203
Test name
Test status
Simulation time 6065768364 ps
CPU time 37.41 seconds
Started Jul 23 06:22:46 PM PDT 24
Finished Jul 23 06:23:43 PM PDT 24
Peak memory 213812 kb
Host smart-965cb40a-5619-4523-9618-1271fea4dd97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693318325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2693318325
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3892307662
Short name T46
Test name
Test status
Simulation time 126774581 ps
CPU time 5.12 seconds
Started Jul 23 06:22:53 PM PDT 24
Finished Jul 23 06:23:18 PM PDT 24
Peak memory 211264 kb
Host smart-964400b5-6a41-4732-b653-a5eccba62da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892307662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3892307662
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2716938383
Short name T12
Test name
Test status
Simulation time 5295230900 ps
CPU time 114.91 seconds
Started Jul 23 06:22:51 PM PDT 24
Finished Jul 23 06:25:06 PM PDT 24
Peak memory 213716 kb
Host smart-50e2f9cd-a143-4683-bf44-8331828049bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716938383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2716938383
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3996803008
Short name T183
Test name
Test status
Simulation time 30780432380 ps
CPU time 25.31 seconds
Started Jul 23 06:22:54 PM PDT 24
Finished Jul 23 06:23:39 PM PDT 24
Peak memory 212036 kb
Host smart-08a4b6c0-4dcc-473a-bb68-7363dd930897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996803008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3996803008
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.371193504
Short name T2
Test name
Test status
Simulation time 2184242116 ps
CPU time 11.41 seconds
Started Jul 23 06:22:51 PM PDT 24
Finished Jul 23 06:23:23 PM PDT 24
Peak memory 211488 kb
Host smart-d286bceb-f032-4eee-b4a6-6d3df7871e37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371193504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.371193504
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.192420114
Short name T158
Test name
Test status
Simulation time 3051270373 ps
CPU time 26.89 seconds
Started Jul 23 06:22:53 PM PDT 24
Finished Jul 23 06:23:40 PM PDT 24
Peak memory 213292 kb
Host smart-08b8291c-e505-476f-9721-71c9da88ea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192420114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.192420114
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1055802725
Short name T257
Test name
Test status
Simulation time 15391281428 ps
CPU time 40.01 seconds
Started Jul 23 06:22:51 PM PDT 24
Finished Jul 23 06:23:51 PM PDT 24
Peak memory 217224 kb
Host smart-57feb0d9-0c2e-4017-8bba-5c651726eed2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055802725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1055802725
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2589008683
Short name T199
Test name
Test status
Simulation time 2052789707 ps
CPU time 9.26 seconds
Started Jul 23 06:22:54 PM PDT 24
Finished Jul 23 06:23:22 PM PDT 24
Peak memory 211200 kb
Host smart-e4aff6e8-c396-4df9-a6d1-a08b8d6b5695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589008683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2589008683
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2150875188
Short name T265
Test name
Test status
Simulation time 72162638059 ps
CPU time 349.31 seconds
Started Jul 23 06:22:52 PM PDT 24
Finished Jul 23 06:29:02 PM PDT 24
Peak memory 233800 kb
Host smart-384d2c30-1591-4b25-8091-58fb2464a5d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150875188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2150875188
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3177068019
Short name T167
Test name
Test status
Simulation time 11686803452 ps
CPU time 15.65 seconds
Started Jul 23 06:22:51 PM PDT 24
Finished Jul 23 06:23:27 PM PDT 24
Peak memory 212316 kb
Host smart-18fa863f-30fa-4aa8-88b6-be0a13b324f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177068019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3177068019
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.58649901
Short name T365
Test name
Test status
Simulation time 7841084549 ps
CPU time 13.51 seconds
Started Jul 23 06:22:51 PM PDT 24
Finished Jul 23 06:23:25 PM PDT 24
Peak memory 211472 kb
Host smart-015714f4-18f8-4f94-b2fc-477abb2fd5df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58649901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.58649901
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3841522503
Short name T211
Test name
Test status
Simulation time 9634832242 ps
CPU time 23.98 seconds
Started Jul 23 06:22:53 PM PDT 24
Finished Jul 23 06:23:36 PM PDT 24
Peak memory 214092 kb
Host smart-f23d4550-0769-4ff0-8167-c0fd9f2b8f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841522503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3841522503
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4044144086
Short name T160
Test name
Test status
Simulation time 15107435250 ps
CPU time 45.82 seconds
Started Jul 23 06:22:50 PM PDT 24
Finished Jul 23 06:23:56 PM PDT 24
Peak memory 215512 kb
Host smart-2eececb8-bdde-4bcb-8b0c-442e86379f19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044144086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4044144086
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4237468990
Short name T237
Test name
Test status
Simulation time 171885698 ps
CPU time 4.15 seconds
Started Jul 23 06:22:58 PM PDT 24
Finished Jul 23 06:23:20 PM PDT 24
Peak memory 211384 kb
Host smart-10a751d6-20a1-4e11-880a-7b94d868ed1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237468990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4237468990
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1421281036
Short name T193
Test name
Test status
Simulation time 152517157685 ps
CPU time 346.14 seconds
Started Jul 23 06:22:59 PM PDT 24
Finished Jul 23 06:29:02 PM PDT 24
Peak memory 234324 kb
Host smart-65fadae1-8e99-498f-b3d6-9611e5ac0897
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421281036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1421281036
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1169996038
Short name T241
Test name
Test status
Simulation time 176407550 ps
CPU time 9.6 seconds
Started Jul 23 06:22:57 PM PDT 24
Finished Jul 23 06:23:25 PM PDT 24
Peak memory 211820 kb
Host smart-f1d2d8f6-bf94-4140-b594-ddfbb89a969b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169996038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1169996038
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2608586410
Short name T283
Test name
Test status
Simulation time 1179362319 ps
CPU time 9.35 seconds
Started Jul 23 06:22:57 PM PDT 24
Finished Jul 23 06:23:24 PM PDT 24
Peak memory 211336 kb
Host smart-f81bf01c-a755-4aef-a674-a144edef9fe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608586410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2608586410
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3369591130
Short name T249
Test name
Test status
Simulation time 744503585 ps
CPU time 10.22 seconds
Started Jul 23 06:22:50 PM PDT 24
Finished Jul 23 06:23:21 PM PDT 24
Peak memory 213412 kb
Host smart-504c248e-02f9-4885-b9c9-b781e5e037b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369591130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3369591130
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3592821336
Short name T147
Test name
Test status
Simulation time 1709356564 ps
CPU time 13.42 seconds
Started Jul 23 06:22:52 PM PDT 24
Finished Jul 23 06:23:25 PM PDT 24
Peak memory 211284 kb
Host smart-c6605923-466a-4d05-85bf-45996f8a04ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592821336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3592821336
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3664500419
Short name T333
Test name
Test status
Simulation time 7651447476 ps
CPU time 15.92 seconds
Started Jul 23 06:22:56 PM PDT 24
Finished Jul 23 06:23:30 PM PDT 24
Peak memory 211400 kb
Host smart-866d390c-bdf1-464c-b6c9-34f7a016df28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664500419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3664500419
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1738696787
Short name T254
Test name
Test status
Simulation time 5120051226 ps
CPU time 128.52 seconds
Started Jul 23 06:22:57 PM PDT 24
Finished Jul 23 06:25:23 PM PDT 24
Peak memory 212692 kb
Host smart-bdd0b1e7-9284-4391-86cf-fae3b8c16f1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738696787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1738696787
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2309088942
Short name T332
Test name
Test status
Simulation time 13132175258 ps
CPU time 30.7 seconds
Started Jul 23 06:22:59 PM PDT 24
Finished Jul 23 06:23:47 PM PDT 24
Peak memory 212292 kb
Host smart-521aaf13-cc99-49e9-882d-4b72313d7033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309088942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2309088942
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.129187616
Short name T258
Test name
Test status
Simulation time 629960394 ps
CPU time 9.52 seconds
Started Jul 23 06:22:57 PM PDT 24
Finished Jul 23 06:23:25 PM PDT 24
Peak memory 211432 kb
Host smart-c6509b7f-d2da-4a9b-aed0-8e42f00a1cb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129187616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.129187616
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1536725956
Short name T300
Test name
Test status
Simulation time 5031470754 ps
CPU time 18.38 seconds
Started Jul 23 06:22:57 PM PDT 24
Finished Jul 23 06:23:34 PM PDT 24
Peak memory 214156 kb
Host smart-be66ac4a-e0cb-4f0f-b0fb-a1d1b7d7c051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536725956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1536725956
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2259088093
Short name T151
Test name
Test status
Simulation time 14409266996 ps
CPU time 125.51 seconds
Started Jul 23 06:22:58 PM PDT 24
Finished Jul 23 06:25:21 PM PDT 24
Peak memory 219440 kb
Host smart-677bea7a-b5c1-4f56-a8e3-cd3a6d2e01ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259088093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2259088093
Directory /workspace/9.rom_ctrl_stress_all/latest
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