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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.35 96.89 92.42 97.67 100.00 98.62 97.45 98.37


Total test records in report: 467
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T301 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.587933225 Jul 24 05:18:21 PM PDT 24 Jul 24 05:18:34 PM PDT 24 6550726640 ps
T302 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3858712696 Jul 24 05:18:34 PM PDT 24 Jul 24 05:20:11 PM PDT 24 6270520636 ps
T303 /workspace/coverage/default/3.rom_ctrl_smoke.147472997 Jul 24 05:17:58 PM PDT 24 Jul 24 05:18:08 PM PDT 24 362288061 ps
T304 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1676770575 Jul 24 05:18:22 PM PDT 24 Jul 24 05:18:35 PM PDT 24 510562705 ps
T43 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.203925689 Jul 24 05:18:41 PM PDT 24 Jul 24 05:23:04 PM PDT 24 109882532131 ps
T305 /workspace/coverage/default/45.rom_ctrl_stress_all.2897477794 Jul 24 05:18:52 PM PDT 24 Jul 24 05:19:17 PM PDT 24 2288032560 ps
T306 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1671337981 Jul 24 05:18:32 PM PDT 24 Jul 24 05:18:38 PM PDT 24 186434796 ps
T307 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3518769873 Jul 24 05:18:10 PM PDT 24 Jul 24 05:24:21 PM PDT 24 152099151483 ps
T308 /workspace/coverage/default/10.rom_ctrl_smoke.1681644738 Jul 24 05:18:12 PM PDT 24 Jul 24 05:18:52 PM PDT 24 4053983155 ps
T309 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1971391545 Jul 24 05:18:37 PM PDT 24 Jul 24 05:21:40 PM PDT 24 79583104769 ps
T41 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3930118472 Jul 24 05:18:36 PM PDT 24 Jul 24 06:00:47 PM PDT 24 20331268360 ps
T310 /workspace/coverage/default/5.rom_ctrl_alert_test.172626009 Jul 24 05:18:12 PM PDT 24 Jul 24 05:18:28 PM PDT 24 12670896680 ps
T44 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2998207703 Jul 24 05:18:51 PM PDT 24 Jul 24 05:22:01 PM PDT 24 38428614622 ps
T311 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.597151605 Jul 24 05:18:41 PM PDT 24 Jul 24 05:18:57 PM PDT 24 13831423489 ps
T312 /workspace/coverage/default/30.rom_ctrl_stress_all.2495389935 Jul 24 05:18:21 PM PDT 24 Jul 24 05:18:52 PM PDT 24 2514595486 ps
T313 /workspace/coverage/default/23.rom_ctrl_stress_all.1752810404 Jul 24 05:18:22 PM PDT 24 Jul 24 05:19:44 PM PDT 24 7249605670 ps
T314 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4173373534 Jul 24 05:18:11 PM PDT 24 Jul 24 05:40:12 PM PDT 24 122055333763 ps
T315 /workspace/coverage/default/26.rom_ctrl_alert_test.2352270756 Jul 24 05:18:31 PM PDT 24 Jul 24 05:18:35 PM PDT 24 320143295 ps
T316 /workspace/coverage/default/41.rom_ctrl_smoke.1899173439 Jul 24 05:18:32 PM PDT 24 Jul 24 05:18:42 PM PDT 24 760923575 ps
T317 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.869618 Jul 24 05:18:22 PM PDT 24 Jul 24 05:22:04 PM PDT 24 18804427364 ps
T318 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3106261048 Jul 24 05:18:22 PM PDT 24 Jul 24 05:18:34 PM PDT 24 1008589403 ps
T319 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2848986138 Jul 24 05:18:54 PM PDT 24 Jul 24 05:22:15 PM PDT 24 19641447699 ps
T320 /workspace/coverage/default/24.rom_ctrl_stress_all.2167170410 Jul 24 05:18:17 PM PDT 24 Jul 24 05:18:53 PM PDT 24 16895118988 ps
T321 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.336039558 Jul 24 05:18:18 PM PDT 24 Jul 24 05:19:57 PM PDT 24 6114769732 ps
T322 /workspace/coverage/default/46.rom_ctrl_alert_test.1266480758 Jul 24 05:18:46 PM PDT 24 Jul 24 05:18:52 PM PDT 24 1372807303 ps
T323 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3669601075 Jul 24 05:18:26 PM PDT 24 Jul 24 05:18:31 PM PDT 24 379626903 ps
T324 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1501471092 Jul 24 05:18:18 PM PDT 24 Jul 24 05:19:24 PM PDT 24 2432492593 ps
T325 /workspace/coverage/default/18.rom_ctrl_smoke.1882336427 Jul 24 05:18:21 PM PDT 24 Jul 24 05:18:44 PM PDT 24 1835043744 ps
T326 /workspace/coverage/default/0.rom_ctrl_alert_test.474006149 Jul 24 05:17:51 PM PDT 24 Jul 24 05:18:02 PM PDT 24 1245996175 ps
T327 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1892329308 Jul 24 05:18:38 PM PDT 24 Jul 24 05:18:43 PM PDT 24 187185824 ps
T328 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1492008504 Jul 24 05:18:18 PM PDT 24 Jul 24 05:18:27 PM PDT 24 175240828 ps
T329 /workspace/coverage/default/32.rom_ctrl_alert_test.4139584455 Jul 24 05:18:36 PM PDT 24 Jul 24 05:18:41 PM PDT 24 171479174 ps
T330 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.116500721 Jul 24 05:18:28 PM PDT 24 Jul 24 05:18:46 PM PDT 24 2161416289 ps
T331 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3165644156 Jul 24 05:18:03 PM PDT 24 Jul 24 05:18:18 PM PDT 24 1786872732 ps
T332 /workspace/coverage/default/2.rom_ctrl_stress_all.3434399861 Jul 24 05:18:01 PM PDT 24 Jul 24 05:19:10 PM PDT 24 148113681109 ps
T333 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3730628524 Jul 24 05:18:12 PM PDT 24 Jul 24 05:18:35 PM PDT 24 2429439251 ps
T334 /workspace/coverage/default/35.rom_ctrl_stress_all.3160554790 Jul 24 05:18:32 PM PDT 24 Jul 24 05:18:47 PM PDT 24 287337578 ps
T335 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1206355723 Jul 24 05:18:46 PM PDT 24 Jul 24 06:52:04 PM PDT 24 35849198467 ps
T336 /workspace/coverage/default/22.rom_ctrl_stress_all.2078133749 Jul 24 05:18:21 PM PDT 24 Jul 24 05:18:52 PM PDT 24 3262595200 ps
T337 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1883484346 Jul 24 05:18:36 PM PDT 24 Jul 24 05:56:26 PM PDT 24 55517154268 ps
T338 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3826317078 Jul 24 05:18:49 PM PDT 24 Jul 24 05:20:51 PM PDT 24 18980152158 ps
T339 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4082532938 Jul 24 05:18:21 PM PDT 24 Jul 24 05:18:31 PM PDT 24 174964868 ps
T340 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.493632927 Jul 24 05:18:06 PM PDT 24 Jul 24 05:20:32 PM PDT 24 3947328022 ps
T341 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3897117884 Jul 24 05:18:33 PM PDT 24 Jul 24 05:38:32 PM PDT 24 62192525054 ps
T342 /workspace/coverage/default/13.rom_ctrl_stress_all.803401096 Jul 24 05:18:27 PM PDT 24 Jul 24 05:19:07 PM PDT 24 31848553268 ps
T343 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1709169809 Jul 24 05:18:23 PM PDT 24 Jul 24 05:26:15 PM PDT 24 194925471768 ps
T344 /workspace/coverage/default/44.rom_ctrl_stress_all.910416956 Jul 24 05:18:44 PM PDT 24 Jul 24 05:19:25 PM PDT 24 4923548938 ps
T345 /workspace/coverage/default/8.rom_ctrl_stress_all.3299514987 Jul 24 05:18:04 PM PDT 24 Jul 24 05:18:22 PM PDT 24 1793832656 ps
T346 /workspace/coverage/default/34.rom_ctrl_alert_test.2009036613 Jul 24 05:18:24 PM PDT 24 Jul 24 05:18:37 PM PDT 24 2961218235 ps
T347 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1551427291 Jul 24 05:18:40 PM PDT 24 Jul 24 05:22:57 PM PDT 24 51249468279 ps
T348 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1443131915 Jul 24 05:18:13 PM PDT 24 Jul 24 05:18:19 PM PDT 24 99476542 ps
T349 /workspace/coverage/default/36.rom_ctrl_stress_all.3914605163 Jul 24 05:18:27 PM PDT 24 Jul 24 05:19:02 PM PDT 24 1966684598 ps
T350 /workspace/coverage/default/9.rom_ctrl_alert_test.3572664630 Jul 24 05:18:08 PM PDT 24 Jul 24 05:18:22 PM PDT 24 1616941822 ps
T351 /workspace/coverage/default/41.rom_ctrl_stress_all.4199234612 Jul 24 05:18:40 PM PDT 24 Jul 24 05:19:47 PM PDT 24 7085533836 ps
T352 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.4152795601 Jul 24 05:18:29 PM PDT 24 Jul 24 07:09:31 PM PDT 24 76063904932 ps
T353 /workspace/coverage/default/9.rom_ctrl_smoke.2071178176 Jul 24 05:18:08 PM PDT 24 Jul 24 05:18:27 PM PDT 24 1377724945 ps
T354 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1807892387 Jul 24 05:18:46 PM PDT 24 Jul 24 05:58:58 PM PDT 24 64353593087 ps
T355 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4142475179 Jul 24 05:18:37 PM PDT 24 Jul 24 05:19:09 PM PDT 24 32718738207 ps
T356 /workspace/coverage/default/45.rom_ctrl_alert_test.3238643876 Jul 24 05:18:40 PM PDT 24 Jul 24 05:18:45 PM PDT 24 172487722 ps
T357 /workspace/coverage/default/2.rom_ctrl_alert_test.3550309000 Jul 24 05:18:11 PM PDT 24 Jul 24 05:18:22 PM PDT 24 2464392615 ps
T358 /workspace/coverage/default/37.rom_ctrl_stress_all.4189657709 Jul 24 05:18:30 PM PDT 24 Jul 24 05:19:04 PM PDT 24 2499256144 ps
T359 /workspace/coverage/default/31.rom_ctrl_stress_all.582062147 Jul 24 05:18:37 PM PDT 24 Jul 24 05:18:59 PM PDT 24 7338494563 ps
T360 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.317336800 Jul 24 05:18:15 PM PDT 24 Jul 24 05:18:21 PM PDT 24 761738708 ps
T361 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.938794235 Jul 24 05:18:38 PM PDT 24 Jul 24 05:18:52 PM PDT 24 7556613303 ps
T362 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.423969623 Jul 24 05:18:50 PM PDT 24 Jul 24 05:19:19 PM PDT 24 3300307273 ps
T363 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2088354925 Jul 24 05:18:16 PM PDT 24 Jul 24 05:19:30 PM PDT 24 1161909103 ps
T364 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1729885535 Jul 24 05:18:05 PM PDT 24 Jul 24 05:24:51 PM PDT 24 158123048203 ps
T365 /workspace/coverage/default/43.rom_ctrl_stress_all.4171342109 Jul 24 05:18:35 PM PDT 24 Jul 24 05:19:19 PM PDT 24 3727819329 ps
T366 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4147169162 Jul 24 05:18:21 PM PDT 24 Jul 24 05:20:13 PM PDT 24 2059259062 ps
T367 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1580008381 Jul 24 05:18:33 PM PDT 24 Jul 24 05:18:46 PM PDT 24 2518005474 ps
T368 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.697142598 Jul 24 05:18:29 PM PDT 24 Jul 24 05:18:39 PM PDT 24 2139719539 ps
T369 /workspace/coverage/default/27.rom_ctrl_smoke.1692192313 Jul 24 05:18:44 PM PDT 24 Jul 24 05:19:08 PM PDT 24 5579652852 ps
T57 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.376121675 Jul 24 05:53:17 PM PDT 24 Jul 24 05:53:22 PM PDT 24 752025894 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.720154284 Jul 24 05:53:06 PM PDT 24 Jul 24 05:53:24 PM PDT 24 2129279410 ps
T58 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1621196897 Jul 24 05:53:09 PM PDT 24 Jul 24 05:53:13 PM PDT 24 85885128 ps
T59 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.201411020 Jul 24 05:53:10 PM PDT 24 Jul 24 05:53:21 PM PDT 24 7529298784 ps
T104 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3058295808 Jul 24 05:53:07 PM PDT 24 Jul 24 05:54:34 PM PDT 24 11290164936 ps
T105 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3959250419 Jul 24 05:53:14 PM PDT 24 Jul 24 05:53:40 PM PDT 24 1920304961 ps
T371 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.263154439 Jul 24 05:53:12 PM PDT 24 Jul 24 05:53:28 PM PDT 24 2050101421 ps
T54 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3645308755 Jul 24 05:53:16 PM PDT 24 Jul 24 05:54:32 PM PDT 24 6352790089 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1656232864 Jul 24 05:53:01 PM PDT 24 Jul 24 05:53:12 PM PDT 24 3982401892 ps
T63 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2007940782 Jul 24 05:53:11 PM PDT 24 Jul 24 05:54:05 PM PDT 24 11474641684 ps
T64 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1490745618 Jul 24 05:53:02 PM PDT 24 Jul 24 05:54:07 PM PDT 24 6482014012 ps
T65 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2095198778 Jul 24 05:52:55 PM PDT 24 Jul 24 05:54:39 PM PDT 24 57315678801 ps
T106 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2296983016 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:19 PM PDT 24 1209311610 ps
T373 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3280645085 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:15 PM PDT 24 359234883 ps
T66 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1674095228 Jul 24 05:53:08 PM PDT 24 Jul 24 05:54:13 PM PDT 24 50308667904 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1415565285 Jul 24 05:53:05 PM PDT 24 Jul 24 05:53:12 PM PDT 24 1111707773 ps
T55 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2433644068 Jul 24 05:53:17 PM PDT 24 Jul 24 05:53:58 PM PDT 24 2864872361 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4133569853 Jul 24 05:53:06 PM PDT 24 Jul 24 05:53:16 PM PDT 24 11383370083 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.550617997 Jul 24 05:53:07 PM PDT 24 Jul 24 05:53:12 PM PDT 24 174688404 ps
T99 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3826691029 Jul 24 05:53:11 PM PDT 24 Jul 24 05:53:23 PM PDT 24 1340593456 ps
T100 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2853491034 Jul 24 05:53:07 PM PDT 24 Jul 24 05:53:14 PM PDT 24 89142609 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3642676288 Jul 24 05:53:00 PM PDT 24 Jul 24 05:53:16 PM PDT 24 1846687843 ps
T56 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3002117280 Jul 24 05:53:06 PM PDT 24 Jul 24 05:54:19 PM PDT 24 3876424467 ps
T114 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.26048185 Jul 24 05:53:16 PM PDT 24 Jul 24 05:53:53 PM PDT 24 310597381 ps
T110 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1007323400 Jul 24 05:53:09 PM PDT 24 Jul 24 05:54:22 PM PDT 24 1759764605 ps
T378 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1099295891 Jul 24 05:53:07 PM PDT 24 Jul 24 05:53:23 PM PDT 24 9247514284 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2906910521 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:14 PM PDT 24 328629160 ps
T379 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2645386572 Jul 24 05:53:26 PM PDT 24 Jul 24 05:53:42 PM PDT 24 1514636295 ps
T112 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1976494952 Jul 24 05:52:59 PM PDT 24 Jul 24 05:54:07 PM PDT 24 1160421036 ps
T380 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.725487585 Jul 24 05:53:05 PM PDT 24 Jul 24 05:53:15 PM PDT 24 204459175 ps
T68 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2918476974 Jul 24 05:53:06 PM PDT 24 Jul 24 05:53:18 PM PDT 24 2544238705 ps
T101 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.888034965 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:17 PM PDT 24 450854469 ps
T381 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.931315100 Jul 24 05:53:09 PM PDT 24 Jul 24 05:53:13 PM PDT 24 175636429 ps
T102 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2514188968 Jul 24 05:53:16 PM PDT 24 Jul 24 05:53:28 PM PDT 24 5427221159 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3190635381 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:21 PM PDT 24 5725141247 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.821464418 Jul 24 05:53:02 PM PDT 24 Jul 24 05:53:16 PM PDT 24 5993723572 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1359866680 Jul 24 05:53:04 PM PDT 24 Jul 24 05:53:09 PM PDT 24 87209688 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3294465448 Jul 24 05:53:05 PM PDT 24 Jul 24 05:53:13 PM PDT 24 861153062 ps
T76 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2770150905 Jul 24 05:53:12 PM PDT 24 Jul 24 05:53:16 PM PDT 24 347256374 ps
T385 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2787376048 Jul 24 05:53:10 PM PDT 24 Jul 24 05:53:16 PM PDT 24 362309968 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3576274671 Jul 24 05:53:01 PM PDT 24 Jul 24 05:53:15 PM PDT 24 5762147030 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.852128354 Jul 24 05:53:02 PM PDT 24 Jul 24 05:53:17 PM PDT 24 1745832939 ps
T103 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2486723777 Jul 24 05:53:00 PM PDT 24 Jul 24 05:53:05 PM PDT 24 89131187 ps
T388 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.525566868 Jul 24 05:53:14 PM PDT 24 Jul 24 05:53:24 PM PDT 24 1668125808 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.509137375 Jul 24 05:53:00 PM PDT 24 Jul 24 05:53:19 PM PDT 24 2419795552 ps
T390 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1332072589 Jul 24 05:53:15 PM PDT 24 Jul 24 05:54:10 PM PDT 24 6413171124 ps
T391 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2996048919 Jul 24 05:53:19 PM PDT 24 Jul 24 05:53:33 PM PDT 24 1930558581 ps
T77 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2221106312 Jul 24 05:53:02 PM PDT 24 Jul 24 05:53:08 PM PDT 24 329894663 ps
T111 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3783475589 Jul 24 05:53:10 PM PDT 24 Jul 24 05:54:30 PM PDT 24 2193138661 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1047098705 Jul 24 05:53:03 PM PDT 24 Jul 24 05:53:15 PM PDT 24 7187284794 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1912799556 Jul 24 05:53:11 PM PDT 24 Jul 24 05:53:19 PM PDT 24 2029893141 ps
T394 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1155527566 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:21 PM PDT 24 6036436436 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1155335427 Jul 24 05:53:07 PM PDT 24 Jul 24 05:53:22 PM PDT 24 8891398698 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1652553055 Jul 24 05:53:03 PM PDT 24 Jul 24 05:53:57 PM PDT 24 21068298428 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3748783835 Jul 24 05:53:00 PM PDT 24 Jul 24 05:53:20 PM PDT 24 7971081791 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1956267079 Jul 24 05:53:04 PM PDT 24 Jul 24 05:53:17 PM PDT 24 1435853925 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2964180345 Jul 24 05:53:07 PM PDT 24 Jul 24 05:53:17 PM PDT 24 653891758 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.701966527 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:16 PM PDT 24 492456688 ps
T400 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4065746338 Jul 24 05:53:07 PM PDT 24 Jul 24 05:53:17 PM PDT 24 3290753512 ps
T79 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2161558920 Jul 24 05:53:03 PM PDT 24 Jul 24 05:53:19 PM PDT 24 4011341664 ps
T80 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2118597745 Jul 24 05:53:16 PM PDT 24 Jul 24 05:53:25 PM PDT 24 8621845330 ps
T113 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2180189013 Jul 24 05:53:11 PM PDT 24 Jul 24 05:54:22 PM PDT 24 325607507 ps
T401 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3848930269 Jul 24 05:53:17 PM PDT 24 Jul 24 05:53:22 PM PDT 24 171182066 ps
T402 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3032577249 Jul 24 05:53:10 PM PDT 24 Jul 24 05:53:22 PM PDT 24 2451109706 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3083255218 Jul 24 05:53:07 PM PDT 24 Jul 24 05:53:11 PM PDT 24 396980205 ps
T115 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2142972249 Jul 24 05:53:03 PM PDT 24 Jul 24 05:54:17 PM PDT 24 19267373211 ps
T404 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3399604160 Jul 24 05:53:17 PM PDT 24 Jul 24 05:53:21 PM PDT 24 346794015 ps
T116 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2107289627 Jul 24 05:53:10 PM PDT 24 Jul 24 05:54:24 PM PDT 24 2246693786 ps
T405 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2364895134 Jul 24 05:53:19 PM PDT 24 Jul 24 05:53:24 PM PDT 24 428435813 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1118844235 Jul 24 05:53:04 PM PDT 24 Jul 24 05:53:09 PM PDT 24 89083490 ps
T406 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1264164827 Jul 24 05:53:12 PM PDT 24 Jul 24 05:53:19 PM PDT 24 2184095254 ps
T109 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1759002154 Jul 24 05:53:11 PM PDT 24 Jul 24 05:54:03 PM PDT 24 5781681479 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1668494927 Jul 24 05:53:06 PM PDT 24 Jul 24 05:53:54 PM PDT 24 14525989248 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4219727641 Jul 24 05:53:10 PM PDT 24 Jul 24 05:53:23 PM PDT 24 1491643520 ps
T409 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2137255124 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:14 PM PDT 24 151194491 ps
T410 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1809529598 Jul 24 05:53:13 PM PDT 24 Jul 24 05:53:19 PM PDT 24 255651358 ps
T120 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2834521827 Jul 24 05:53:09 PM PDT 24 Jul 24 05:53:52 PM PDT 24 1238386850 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1999236227 Jul 24 05:53:00 PM PDT 24 Jul 24 05:53:12 PM PDT 24 1431945728 ps
T85 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2002770240 Jul 24 05:53:11 PM PDT 24 Jul 24 05:54:50 PM PDT 24 44067521821 ps
T412 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3364690597 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:22 PM PDT 24 6460703092 ps
T119 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1779609250 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:52 PM PDT 24 1703448929 ps
T117 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.290756442 Jul 24 05:53:07 PM PDT 24 Jul 24 05:54:26 PM PDT 24 2165267864 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.694683995 Jul 24 05:53:18 PM PDT 24 Jul 24 05:53:26 PM PDT 24 261791845 ps
T414 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2134272346 Jul 24 05:53:17 PM PDT 24 Jul 24 05:53:31 PM PDT 24 1829594081 ps
T415 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3391893829 Jul 24 05:53:07 PM PDT 24 Jul 24 05:53:21 PM PDT 24 2692238871 ps
T416 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3032726392 Jul 24 05:53:19 PM PDT 24 Jul 24 05:54:06 PM PDT 24 2277749738 ps
T417 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1959312783 Jul 24 05:53:12 PM PDT 24 Jul 24 05:53:28 PM PDT 24 1102484362 ps
T418 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.592685958 Jul 24 05:53:05 PM PDT 24 Jul 24 05:53:22 PM PDT 24 41770210436 ps
T419 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3931346966 Jul 24 05:53:15 PM PDT 24 Jul 24 05:53:30 PM PDT 24 3664732106 ps
T86 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3623178951 Jul 24 05:53:07 PM PDT 24 Jul 24 05:54:46 PM PDT 24 25478832039 ps
T82 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4131604296 Jul 24 05:53:05 PM PDT 24 Jul 24 05:53:56 PM PDT 24 7926481573 ps
T420 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.654777938 Jul 24 05:53:13 PM PDT 24 Jul 24 05:53:20 PM PDT 24 360886362 ps
T421 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.36944840 Jul 24 05:53:12 PM PDT 24 Jul 24 05:53:17 PM PDT 24 333386123 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3572577199 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:20 PM PDT 24 2866724872 ps
T88 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2008065566 Jul 24 05:53:20 PM PDT 24 Jul 24 05:54:13 PM PDT 24 6098317054 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.370962833 Jul 24 05:53:02 PM PDT 24 Jul 24 05:53:15 PM PDT 24 5545362765 ps
T424 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1198618823 Jul 24 05:53:19 PM PDT 24 Jul 24 05:53:26 PM PDT 24 418418719 ps
T425 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1656963889 Jul 24 05:53:16 PM PDT 24 Jul 24 05:53:55 PM PDT 24 1978656974 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2549373186 Jul 24 05:53:14 PM PDT 24 Jul 24 05:53:20 PM PDT 24 96199782 ps
T83 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.167704474 Jul 24 05:53:11 PM PDT 24 Jul 24 05:53:16 PM PDT 24 347757677 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2284576582 Jul 24 05:53:01 PM PDT 24 Jul 24 05:53:09 PM PDT 24 2047838663 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2364225424 Jul 24 05:53:04 PM PDT 24 Jul 24 05:53:19 PM PDT 24 3183230677 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4004175558 Jul 24 05:53:18 PM PDT 24 Jul 24 05:53:31 PM PDT 24 1387543581 ps
T430 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3782219159 Jul 24 05:53:14 PM PDT 24 Jul 24 05:53:28 PM PDT 24 3069904373 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1406756212 Jul 24 05:53:06 PM PDT 24 Jul 24 05:53:21 PM PDT 24 5483761462 ps
T432 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.876777438 Jul 24 05:53:11 PM PDT 24 Jul 24 05:53:51 PM PDT 24 3391031208 ps
T433 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.67757660 Jul 24 05:53:11 PM PDT 24 Jul 24 05:53:23 PM PDT 24 1084830570 ps
T434 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1629157670 Jul 24 05:53:12 PM PDT 24 Jul 24 05:53:21 PM PDT 24 482370978 ps
T435 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2406014579 Jul 24 05:53:10 PM PDT 24 Jul 24 05:54:00 PM PDT 24 11035360423 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.333944425 Jul 24 05:53:04 PM PDT 24 Jul 24 05:53:50 PM PDT 24 2217648678 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2718250085 Jul 24 05:53:09 PM PDT 24 Jul 24 05:53:22 PM PDT 24 1375166885 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.25105610 Jul 24 05:53:00 PM PDT 24 Jul 24 05:53:06 PM PDT 24 985215744 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2000645465 Jul 24 05:53:01 PM PDT 24 Jul 24 05:53:10 PM PDT 24 4353471582 ps
T440 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2311885731 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:23 PM PDT 24 2307618555 ps
T441 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4146368896 Jul 24 05:53:00 PM PDT 24 Jul 24 05:53:15 PM PDT 24 1693242931 ps
T442 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3359275341 Jul 24 05:53:06 PM PDT 24 Jul 24 05:53:14 PM PDT 24 14030576118 ps
T87 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3360977265 Jul 24 05:53:19 PM PDT 24 Jul 24 05:53:23 PM PDT 24 88343511 ps
T443 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1522453378 Jul 24 05:53:01 PM PDT 24 Jul 24 05:53:08 PM PDT 24 561171324 ps
T444 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3624503846 Jul 24 05:53:07 PM PDT 24 Jul 24 05:53:22 PM PDT 24 1435934024 ps
T445 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3878420569 Jul 24 05:53:09 PM PDT 24 Jul 24 05:54:43 PM PDT 24 12416716928 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3770722541 Jul 24 05:53:04 PM PDT 24 Jul 24 05:53:08 PM PDT 24 86238872 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3292888814 Jul 24 05:53:07 PM PDT 24 Jul 24 05:53:18 PM PDT 24 4325405570 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3148728523 Jul 24 05:53:03 PM PDT 24 Jul 24 05:53:18 PM PDT 24 19279599412 ps
T449 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3844941939 Jul 24 05:53:14 PM PDT 24 Jul 24 05:53:29 PM PDT 24 1476311703 ps
T450 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2440518040 Jul 24 05:53:09 PM PDT 24 Jul 24 05:53:27 PM PDT 24 3101115749 ps
T451 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1469574182 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:22 PM PDT 24 2468119106 ps
T452 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1053090226 Jul 24 05:53:12 PM PDT 24 Jul 24 05:53:24 PM PDT 24 2860344214 ps
T453 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2443343041 Jul 24 05:53:10 PM PDT 24 Jul 24 05:53:32 PM PDT 24 531741586 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1944703486 Jul 24 05:53:06 PM PDT 24 Jul 24 05:53:15 PM PDT 24 3086626853 ps
T455 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4046070911 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:13 PM PDT 24 175622238 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2866893137 Jul 24 05:53:03 PM PDT 24 Jul 24 05:53:23 PM PDT 24 15849878886 ps
T89 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2250449271 Jul 24 05:53:18 PM PDT 24 Jul 24 05:54:46 PM PDT 24 41602550687 ps
T457 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3457721493 Jul 24 05:53:05 PM PDT 24 Jul 24 05:53:17 PM PDT 24 5464359472 ps
T458 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1972898794 Jul 24 05:53:10 PM PDT 24 Jul 24 05:53:15 PM PDT 24 722099810 ps
T459 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1068506047 Jul 24 05:53:10 PM PDT 24 Jul 24 05:53:54 PM PDT 24 2356764215 ps
T460 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3368183868 Jul 24 05:53:11 PM PDT 24 Jul 24 05:53:59 PM PDT 24 8158075444 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2497763380 Jul 24 05:52:59 PM PDT 24 Jul 24 05:53:49 PM PDT 24 10956128911 ps
T462 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.18825819 Jul 24 05:53:11 PM PDT 24 Jul 24 05:53:22 PM PDT 24 2944121965 ps
T463 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2402203855 Jul 24 05:53:10 PM PDT 24 Jul 24 05:53:17 PM PDT 24 519870661 ps
T464 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1745713061 Jul 24 05:53:06 PM PDT 24 Jul 24 05:53:51 PM PDT 24 5521454256 ps
T465 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2784175140 Jul 24 05:53:14 PM PDT 24 Jul 24 05:53:28 PM PDT 24 1612811295 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.376111317 Jul 24 05:53:03 PM PDT 24 Jul 24 05:53:15 PM PDT 24 6036440862 ps
T118 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3311204418 Jul 24 05:53:01 PM PDT 24 Jul 24 05:54:19 PM PDT 24 2114421904 ps
T466 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.682512747 Jul 24 05:53:08 PM PDT 24 Jul 24 05:53:24 PM PDT 24 4970250330 ps
T467 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3105893955 Jul 24 05:53:03 PM PDT 24 Jul 24 05:53:07 PM PDT 24 147524544 ps

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1763138669
Short name T4
Test name
Test status
Simulation time 33689578467 ps
CPU time 310.51 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:23:48 PM PDT 24
Peak memory 237884 kb
Host smart-552442c6-7191-4195-b433-0822454f62a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763138669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1763138669
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.779774315
Short name T14
Test name
Test status
Simulation time 16265781380 ps
CPU time 2522.64 seconds
Started Jul 24 05:18:36 PM PDT 24
Finished Jul 24 06:00:39 PM PDT 24
Peak memory 234692 kb
Host smart-f84f507c-649d-4ac5-8e9a-78f2d85b478e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779774315 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.779774315
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1826486638
Short name T30
Test name
Test status
Simulation time 39567598545 ps
CPU time 377.83 seconds
Started Jul 24 05:18:09 PM PDT 24
Finished Jul 24 05:24:27 PM PDT 24
Peak memory 235156 kb
Host smart-3ff9d5b8-3a3f-4816-89f3-11be58216f74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826486638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1826486638
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2981938817
Short name T40
Test name
Test status
Simulation time 9143169836 ps
CPU time 156.92 seconds
Started Jul 24 05:18:19 PM PDT 24
Finished Jul 24 05:20:56 PM PDT 24
Peak memory 236840 kb
Host smart-97af4aff-6b9e-42ac-bef5-916871eb8a89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981938817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2981938817
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3645308755
Short name T54
Test name
Test status
Simulation time 6352790089 ps
CPU time 75.79 seconds
Started Jul 24 05:53:16 PM PDT 24
Finished Jul 24 05:54:32 PM PDT 24
Peak memory 218912 kb
Host smart-92c15244-7d98-4c0f-b748-0b0ba5f1e68c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645308755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3645308755
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1189217715
Short name T11
Test name
Test status
Simulation time 83726642101 ps
CPU time 1580.44 seconds
Started Jul 24 05:18:39 PM PDT 24
Finished Jul 24 05:45:00 PM PDT 24
Peak memory 235456 kb
Host smart-99ece613-79cd-4014-8516-cebded4282df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189217715 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1189217715
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3889277751
Short name T20
Test name
Test status
Simulation time 1286721318 ps
CPU time 97.73 seconds
Started Jul 24 05:18:13 PM PDT 24
Finished Jul 24 05:19:51 PM PDT 24
Peak memory 238092 kb
Host smart-a3588f96-76cf-4cea-bf67-df24b916a738
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889277751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3889277751
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1674095228
Short name T66
Test name
Test status
Simulation time 50308667904 ps
CPU time 63.91 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:54:13 PM PDT 24
Peak memory 210784 kb
Host smart-5e3647df-e0a5-4c22-9f03-a76f78586f42
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674095228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1674095228
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3930118472
Short name T41
Test name
Test status
Simulation time 20331268360 ps
CPU time 2530.26 seconds
Started Jul 24 05:18:36 PM PDT 24
Finished Jul 24 06:00:47 PM PDT 24
Peak memory 228320 kb
Host smart-fdcca9e0-bee2-467d-85e3-7c909681201e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930118472 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3930118472
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.814241219
Short name T1
Test name
Test status
Simulation time 6448326176 ps
CPU time 13.92 seconds
Started Jul 24 05:18:39 PM PDT 24
Finished Jul 24 05:18:53 PM PDT 24
Peak memory 211280 kb
Host smart-5daa02af-65f6-4e64-9ff2-752eecaa2920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814241219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.814241219
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.333944425
Short name T436
Test name
Test status
Simulation time 2217648678 ps
CPU time 46.49 seconds
Started Jul 24 05:53:04 PM PDT 24
Finished Jul 24 05:53:50 PM PDT 24
Peak memory 210684 kb
Host smart-60df3702-5b64-4215-af8c-ef2568b1a6fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333944425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.333944425
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3153360847
Short name T33
Test name
Test status
Simulation time 8718975843 ps
CPU time 32.31 seconds
Started Jul 24 05:17:58 PM PDT 24
Finished Jul 24 05:18:31 PM PDT 24
Peak memory 212268 kb
Host smart-3965899b-82fe-47f9-bc78-79c0128938f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153360847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3153360847
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3986544389
Short name T42
Test name
Test status
Simulation time 334857173 ps
CPU time 9.43 seconds
Started Jul 24 05:18:05 PM PDT 24
Finished Jul 24 05:18:15 PM PDT 24
Peak memory 211876 kb
Host smart-31f4b6c3-7a5e-43f4-ade2-fe1d06af918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986544389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3986544389
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2107289627
Short name T116
Test name
Test status
Simulation time 2246693786 ps
CPU time 73.23 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:54:24 PM PDT 24
Peak memory 218836 kb
Host smart-76271cd0-198e-446b-8d28-9800c0cd0597
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107289627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2107289627
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3783475589
Short name T111
Test name
Test status
Simulation time 2193138661 ps
CPU time 79.27 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:54:30 PM PDT 24
Peak memory 212256 kb
Host smart-4fd6fabf-6d1c-428b-b226-2eaf49734671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783475589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3783475589
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.332970286
Short name T70
Test name
Test status
Simulation time 4021474155 ps
CPU time 14.25 seconds
Started Jul 24 05:18:38 PM PDT 24
Finished Jul 24 05:18:52 PM PDT 24
Peak memory 211360 kb
Host smart-3e30f9b2-08cb-40f8-b4ae-e2014acd661a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332970286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.332970286
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2095198778
Short name T65
Test name
Test status
Simulation time 57315678801 ps
CPU time 103.95 seconds
Started Jul 24 05:52:55 PM PDT 24
Finished Jul 24 05:54:39 PM PDT 24
Peak memory 218956 kb
Host smart-7cf435a4-6387-4036-b235-4362a1ea74a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095198778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2095198778
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3311204418
Short name T118
Test name
Test status
Simulation time 2114421904 ps
CPU time 77.24 seconds
Started Jul 24 05:53:01 PM PDT 24
Finished Jul 24 05:54:19 PM PDT 24
Peak memory 218744 kb
Host smart-cd76f7a6-d98a-46f1-a953-1853f97e94e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311204418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3311204418
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2834521827
Short name T120
Test name
Test status
Simulation time 1238386850 ps
CPU time 42.35 seconds
Started Jul 24 05:53:09 PM PDT 24
Finished Jul 24 05:53:52 PM PDT 24
Peak memory 218780 kb
Host smart-fbaa971d-63d8-416e-bbba-75c7fd6cb2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834521827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2834521827
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2918476974
Short name T68
Test name
Test status
Simulation time 2544238705 ps
CPU time 11.6 seconds
Started Jul 24 05:53:06 PM PDT 24
Finished Jul 24 05:53:18 PM PDT 24
Peak memory 210688 kb
Host smart-41569513-777b-4e40-9625-8c3497fdf09d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918476974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2918476974
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3790963491
Short name T90
Test name
Test status
Simulation time 7701824518 ps
CPU time 16.55 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:18:49 PM PDT 24
Peak memory 211408 kb
Host smart-3f413a1c-fbf5-46bb-9042-052f079f881b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790963491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3790963491
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2136629812
Short name T169
Test name
Test status
Simulation time 8973261029 ps
CPU time 59.33 seconds
Started Jul 24 05:18:15 PM PDT 24
Finished Jul 24 05:19:15 PM PDT 24
Peak memory 216964 kb
Host smart-be20189c-8d93-4116-ad0f-927e82e401ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136629812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2136629812
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2284576582
Short name T427
Test name
Test status
Simulation time 2047838663 ps
CPU time 7.14 seconds
Started Jul 24 05:53:01 PM PDT 24
Finished Jul 24 05:53:09 PM PDT 24
Peak memory 210544 kb
Host smart-32cce6a2-1958-46ad-aece-dd5f1345ae50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284576582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2284576582
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3105893955
Short name T467
Test name
Test status
Simulation time 147524544 ps
CPU time 4.32 seconds
Started Jul 24 05:53:03 PM PDT 24
Finished Jul 24 05:53:07 PM PDT 24
Peak memory 210620 kb
Host smart-5441708c-e195-4125-b3c6-7d6e68ee0c1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105893955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3105893955
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1406756212
Short name T431
Test name
Test status
Simulation time 5483761462 ps
CPU time 14.84 seconds
Started Jul 24 05:53:06 PM PDT 24
Finished Jul 24 05:53:21 PM PDT 24
Peak memory 210620 kb
Host smart-eb601faf-c979-4187-b26e-a93ff93c4aa8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406756212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1406756212
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1944703486
Short name T454
Test name
Test status
Simulation time 3086626853 ps
CPU time 8.86 seconds
Started Jul 24 05:53:06 PM PDT 24
Finished Jul 24 05:53:15 PM PDT 24
Peak memory 218836 kb
Host smart-1c503082-e717-4506-a159-de75297b0cc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944703486 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1944703486
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2221106312
Short name T77
Test name
Test status
Simulation time 329894663 ps
CPU time 6.5 seconds
Started Jul 24 05:53:02 PM PDT 24
Finished Jul 24 05:53:08 PM PDT 24
Peak memory 210460 kb
Host smart-fabf8684-3e38-445f-8ad0-909d01ecc337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221106312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2221106312
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1656232864
Short name T372
Test name
Test status
Simulation time 3982401892 ps
CPU time 11.12 seconds
Started Jul 24 05:53:01 PM PDT 24
Finished Jul 24 05:53:12 PM PDT 24
Peak memory 210480 kb
Host smart-26166f33-e7c1-4a14-b764-20766fc28ab4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656232864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1656232864
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1522453378
Short name T443
Test name
Test status
Simulation time 561171324 ps
CPU time 7.49 seconds
Started Jul 24 05:53:01 PM PDT 24
Finished Jul 24 05:53:08 PM PDT 24
Peak memory 210384 kb
Host smart-e000f1b4-6625-496c-937f-7f3ae0a9eaaf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522453378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1522453378
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2866893137
Short name T456
Test name
Test status
Simulation time 15849878886 ps
CPU time 19.78 seconds
Started Jul 24 05:53:03 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 218948 kb
Host smart-b3dc4626-bd93-44dc-b973-6d0b49c483f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866893137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2866893137
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1359866680
Short name T383
Test name
Test status
Simulation time 87209688 ps
CPU time 4.26 seconds
Started Jul 24 05:53:04 PM PDT 24
Finished Jul 24 05:53:09 PM PDT 24
Peak memory 210452 kb
Host smart-1694d347-a9e7-479e-a551-93614f031ac5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359866680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1359866680
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3642676288
Short name T377
Test name
Test status
Simulation time 1846687843 ps
CPU time 15.84 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:16 PM PDT 24
Peak memory 210540 kb
Host smart-18f02c19-dbf5-4676-af32-dffcd7e59552
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642676288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3642676288
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.821464418
Short name T69
Test name
Test status
Simulation time 5993723572 ps
CPU time 14.36 seconds
Started Jul 24 05:53:02 PM PDT 24
Finished Jul 24 05:53:16 PM PDT 24
Peak memory 210588 kb
Host smart-98fdffac-5722-4c92-840a-ad06a42d1b24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821464418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.821464418
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4146368896
Short name T441
Test name
Test status
Simulation time 1693242931 ps
CPU time 14.88 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:15 PM PDT 24
Peak memory 218800 kb
Host smart-cdfe3010-b40a-41ca-be3c-3b2d051ad186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146368896 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4146368896
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1118844235
Short name T81
Test name
Test status
Simulation time 89083490 ps
CPU time 4.41 seconds
Started Jul 24 05:53:04 PM PDT 24
Finished Jul 24 05:53:09 PM PDT 24
Peak memory 210560 kb
Host smart-5e6789ac-90c4-438c-914f-1f3d8513356d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118844235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1118844235
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1047098705
Short name T392
Test name
Test status
Simulation time 7187284794 ps
CPU time 11.59 seconds
Started Jul 24 05:53:03 PM PDT 24
Finished Jul 24 05:53:15 PM PDT 24
Peak memory 210520 kb
Host smart-42bf8e7c-76d6-4bff-80c1-2cafac1a3e47
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047098705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1047098705
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1999236227
Short name T411
Test name
Test status
Simulation time 1431945728 ps
CPU time 12.57 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:12 PM PDT 24
Peak memory 210384 kb
Host smart-55d2417d-855d-449c-ac33-99f83a9934c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999236227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1999236227
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1652553055
Short name T78
Test name
Test status
Simulation time 21068298428 ps
CPU time 54.52 seconds
Started Jul 24 05:53:03 PM PDT 24
Finished Jul 24 05:53:57 PM PDT 24
Peak memory 210600 kb
Host smart-0f1e8f58-b3ad-4ace-92ad-1022b0631e6f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652553055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1652553055
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2000645465
Short name T439
Test name
Test status
Simulation time 4353471582 ps
CPU time 8.81 seconds
Started Jul 24 05:53:01 PM PDT 24
Finished Jul 24 05:53:10 PM PDT 24
Peak memory 218136 kb
Host smart-d66e11b5-827d-4c8e-928b-1c744fbf0abe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000645465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2000645465
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3748783835
Short name T396
Test name
Test status
Simulation time 7971081791 ps
CPU time 19.46 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:20 PM PDT 24
Peak memory 218944 kb
Host smart-a67120c3-9e71-4ae4-8f44-eb6b0e22ab60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748783835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3748783835
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2787376048
Short name T385
Test name
Test status
Simulation time 362309968 ps
CPU time 6.23 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:53:16 PM PDT 24
Peak memory 218804 kb
Host smart-4697b58a-c96d-452a-8c97-a931ebaacba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787376048 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2787376048
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.201411020
Short name T59
Test name
Test status
Simulation time 7529298784 ps
CPU time 10.01 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:53:21 PM PDT 24
Peak memory 218772 kb
Host smart-a2fdaa57-4b97-428d-84cc-7c05bbf78767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201411020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.201411020
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3878420569
Short name T445
Test name
Test status
Simulation time 12416716928 ps
CPU time 93.36 seconds
Started Jul 24 05:53:09 PM PDT 24
Finished Jul 24 05:54:43 PM PDT 24
Peak memory 210836 kb
Host smart-d7817877-e198-4a9d-adb7-5b589e2bca41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878420569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3878420569
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3359275341
Short name T442
Test name
Test status
Simulation time 14030576118 ps
CPU time 8.53 seconds
Started Jul 24 05:53:06 PM PDT 24
Finished Jul 24 05:53:14 PM PDT 24
Peak memory 218484 kb
Host smart-68e9cc63-0571-4f98-9041-4d20d256d297
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359275341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3359275341
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3624503846
Short name T444
Test name
Test status
Simulation time 1435934024 ps
CPU time 14.92 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 218796 kb
Host smart-2d5ffe29-21cf-4834-8b57-dcb2952860db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624503846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3624503846
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1155527566
Short name T394
Test name
Test status
Simulation time 6036436436 ps
CPU time 13.09 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:21 PM PDT 24
Peak memory 218992 kb
Host smart-9921007f-65f7-46ff-b7a4-a9135a91a468
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155527566 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1155527566
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2770150905
Short name T76
Test name
Test status
Simulation time 347256374 ps
CPU time 4.1 seconds
Started Jul 24 05:53:12 PM PDT 24
Finished Jul 24 05:53:16 PM PDT 24
Peak memory 210560 kb
Host smart-1d34f297-d789-4ac9-8fa6-82c1fa29e540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770150905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2770150905
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3058295808
Short name T104
Test name
Test status
Simulation time 11290164936 ps
CPU time 86.76 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:54:34 PM PDT 24
Peak memory 210720 kb
Host smart-73e8b3f7-861b-47bb-8e47-e5a4034e9e8a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058295808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3058295808
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2906910521
Short name T67
Test name
Test status
Simulation time 328629160 ps
CPU time 6.43 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:14 PM PDT 24
Peak memory 217868 kb
Host smart-13379a45-bfa7-4b7a-9249-f316fcb54ec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906910521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2906910521
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.682512747
Short name T466
Test name
Test status
Simulation time 4970250330 ps
CPU time 15.69 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:24 PM PDT 24
Peak memory 218952 kb
Host smart-13ae67a0-9a0c-4384-8569-7face465b7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682512747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.682512747
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1007323400
Short name T110
Test name
Test status
Simulation time 1759764605 ps
CPU time 72.81 seconds
Started Jul 24 05:53:09 PM PDT 24
Finished Jul 24 05:54:22 PM PDT 24
Peak memory 218724 kb
Host smart-a5eb9dc5-70c8-4882-99bd-e48fa75f9b46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007323400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1007323400
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.654777938
Short name T420
Test name
Test status
Simulation time 360886362 ps
CPU time 6.98 seconds
Started Jul 24 05:53:13 PM PDT 24
Finished Jul 24 05:53:20 PM PDT 24
Peak memory 218864 kb
Host smart-d0cb147f-c9dd-43ff-bb9d-74e42394b26b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654777938 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.654777938
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1972898794
Short name T458
Test name
Test status
Simulation time 722099810 ps
CPU time 5.44 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:53:15 PM PDT 24
Peak memory 210448 kb
Host smart-902bb8f0-1496-4d5b-a379-b95660cc0391
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972898794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1972898794
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3623178951
Short name T86
Test name
Test status
Simulation time 25478832039 ps
CPU time 99.33 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:54:46 PM PDT 24
Peak memory 210756 kb
Host smart-2fa95549-8edc-4db5-a43d-d6e09d6c5fb5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623178951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3623178951
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3844941939
Short name T449
Test name
Test status
Simulation time 1476311703 ps
CPU time 14.33 seconds
Started Jul 24 05:53:14 PM PDT 24
Finished Jul 24 05:53:29 PM PDT 24
Peak memory 218768 kb
Host smart-bf0d33cf-672c-4c8a-a76c-a1625abb2dc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844941939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3844941939
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2311885731
Short name T440
Test name
Test status
Simulation time 2307618555 ps
CPU time 15.01 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 218916 kb
Host smart-0d50ccc9-f218-496e-98f5-32c23a112721
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311885731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2311885731
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2180189013
Short name T113
Test name
Test status
Simulation time 325607507 ps
CPU time 70.86 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:54:22 PM PDT 24
Peak memory 212280 kb
Host smart-32d5b442-872c-487f-b67d-86c905a2bdb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180189013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2180189013
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1912799556
Short name T393
Test name
Test status
Simulation time 2029893141 ps
CPU time 7.91 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:53:19 PM PDT 24
Peak memory 218864 kb
Host smart-19211f4a-52a1-4c75-8c6e-c700e8373661
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912799556 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1912799556
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3782219159
Short name T430
Test name
Test status
Simulation time 3069904373 ps
CPU time 13.17 seconds
Started Jul 24 05:53:14 PM PDT 24
Finished Jul 24 05:53:28 PM PDT 24
Peak memory 218740 kb
Host smart-61b1aa18-84e5-46a6-bde3-91a9b85ef671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782219159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3782219159
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1759002154
Short name T109
Test name
Test status
Simulation time 5781681479 ps
CPU time 51.9 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:54:03 PM PDT 24
Peak memory 210736 kb
Host smart-a1298199-9bc7-4869-8344-4c60d105a954
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759002154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1759002154
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.18825819
Short name T462
Test name
Test status
Simulation time 2944121965 ps
CPU time 10.6 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 218856 kb
Host smart-c278108a-6e95-4f3d-a277-dab0cdd319f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18825819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ct
rl_same_csr_outstanding.18825819
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3931346966
Short name T419
Test name
Test status
Simulation time 3664732106 ps
CPU time 14.47 seconds
Started Jul 24 05:53:15 PM PDT 24
Finished Jul 24 05:53:30 PM PDT 24
Peak memory 218884 kb
Host smart-74fba5af-1df5-4593-b975-8ef9c299bb56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931346966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3931346966
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.26048185
Short name T114
Test name
Test status
Simulation time 310597381 ps
CPU time 36.92 seconds
Started Jul 24 05:53:16 PM PDT 24
Finished Jul 24 05:53:53 PM PDT 24
Peak memory 218760 kb
Host smart-56c714a5-2743-4bb5-abe3-a070c48d8771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26048185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_int
g_err.26048185
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.263154439
Short name T371
Test name
Test status
Simulation time 2050101421 ps
CPU time 15.75 seconds
Started Jul 24 05:53:12 PM PDT 24
Finished Jul 24 05:53:28 PM PDT 24
Peak memory 218776 kb
Host smart-06a09dda-f13d-4607-8610-0164a37d3a94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263154439 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.263154439
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1809529598
Short name T410
Test name
Test status
Simulation time 255651358 ps
CPU time 5.81 seconds
Started Jul 24 05:53:13 PM PDT 24
Finished Jul 24 05:53:19 PM PDT 24
Peak memory 210552 kb
Host smart-8943f225-e3d9-4743-bde0-a331f71a4893
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809529598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1809529598
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2002770240
Short name T85
Test name
Test status
Simulation time 44067521821 ps
CPU time 93.52 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:54:50 PM PDT 24
Peak memory 210752 kb
Host smart-dd964cad-e245-4d6a-a438-af8d7ee04b67
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002770240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2002770240
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2549373186
Short name T426
Test name
Test status
Simulation time 96199782 ps
CPU time 5.81 seconds
Started Jul 24 05:53:14 PM PDT 24
Finished Jul 24 05:53:20 PM PDT 24
Peak memory 218732 kb
Host smart-4bff755c-7ca4-4d65-85e7-c7aa66d29ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549373186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2549373186
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1053090226
Short name T452
Test name
Test status
Simulation time 2860344214 ps
CPU time 11.53 seconds
Started Jul 24 05:53:12 PM PDT 24
Finished Jul 24 05:53:24 PM PDT 24
Peak memory 218876 kb
Host smart-518a16be-19c0-4aa4-a47b-456765a7ecf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053090226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1053090226
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1264164827
Short name T406
Test name
Test status
Simulation time 2184095254 ps
CPU time 6.87 seconds
Started Jul 24 05:53:12 PM PDT 24
Finished Jul 24 05:53:19 PM PDT 24
Peak memory 218924 kb
Host smart-8c507311-b1d5-4e2d-a520-a19ebeda213c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264164827 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1264164827
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.36944840
Short name T421
Test name
Test status
Simulation time 333386123 ps
CPU time 4.2 seconds
Started Jul 24 05:53:12 PM PDT 24
Finished Jul 24 05:53:17 PM PDT 24
Peak memory 217928 kb
Host smart-c150ff88-f3c3-4a7d-820e-a9bd149d2928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36944840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.36944840
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1332072589
Short name T390
Test name
Test status
Simulation time 6413171124 ps
CPU time 54.82 seconds
Started Jul 24 05:53:15 PM PDT 24
Finished Jul 24 05:54:10 PM PDT 24
Peak memory 210824 kb
Host smart-3ad597a3-f00d-44b2-b05c-fb82d9627dc1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332072589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1332072589
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2784175140
Short name T465
Test name
Test status
Simulation time 1612811295 ps
CPU time 13.03 seconds
Started Jul 24 05:53:14 PM PDT 24
Finished Jul 24 05:53:28 PM PDT 24
Peak memory 218768 kb
Host smart-fbcac2b6-de70-45d5-8559-c4303d40f317
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784175140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2784175140
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.67757660
Short name T433
Test name
Test status
Simulation time 1084830570 ps
CPU time 11.94 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 218800 kb
Host smart-c93b2d7f-4f76-42fb-ab39-cdf8ec09b53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67757660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.67757660
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.876777438
Short name T432
Test name
Test status
Simulation time 3391031208 ps
CPU time 40.08 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 218848 kb
Host smart-202a23b4-12ae-4d1b-be9d-60171be72799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876777438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.876777438
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.525566868
Short name T388
Test name
Test status
Simulation time 1668125808 ps
CPU time 10.24 seconds
Started Jul 24 05:53:14 PM PDT 24
Finished Jul 24 05:53:24 PM PDT 24
Peak memory 218856 kb
Host smart-e3115245-d448-4832-a7d6-19f4bf368508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525566868 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.525566868
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2118597745
Short name T80
Test name
Test status
Simulation time 8621845330 ps
CPU time 9.62 seconds
Started Jul 24 05:53:16 PM PDT 24
Finished Jul 24 05:53:25 PM PDT 24
Peak memory 210632 kb
Host smart-5f0a4a17-c947-4b0e-b8f3-e5e80f6b643f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118597745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2118597745
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3959250419
Short name T105
Test name
Test status
Simulation time 1920304961 ps
CPU time 26.48 seconds
Started Jul 24 05:53:14 PM PDT 24
Finished Jul 24 05:53:40 PM PDT 24
Peak memory 210636 kb
Host smart-6a1b5488-e47f-42af-9db9-bdbcf71b3377
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959250419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3959250419
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2514188968
Short name T102
Test name
Test status
Simulation time 5427221159 ps
CPU time 12.05 seconds
Started Jul 24 05:53:16 PM PDT 24
Finished Jul 24 05:53:28 PM PDT 24
Peak memory 218872 kb
Host smart-450854ce-c389-43ff-8f56-0e8e587a578e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514188968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2514188968
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1629157670
Short name T434
Test name
Test status
Simulation time 482370978 ps
CPU time 8.63 seconds
Started Jul 24 05:53:12 PM PDT 24
Finished Jul 24 05:53:21 PM PDT 24
Peak memory 218780 kb
Host smart-ff7ad0a4-0021-40eb-b075-53e2bb4a47ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629157670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1629157670
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3368183868
Short name T460
Test name
Test status
Simulation time 8158075444 ps
CPU time 47.26 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:53:59 PM PDT 24
Peak memory 212252 kb
Host smart-511c826c-974f-4e74-b41b-9c067f073527
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368183868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3368183868
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1198618823
Short name T424
Test name
Test status
Simulation time 418418719 ps
CPU time 6.61 seconds
Started Jul 24 05:53:19 PM PDT 24
Finished Jul 24 05:53:26 PM PDT 24
Peak memory 218852 kb
Host smart-94f592cb-2c01-45ed-9d6b-6225ac576eb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198618823 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1198618823
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3848930269
Short name T401
Test name
Test status
Simulation time 171182066 ps
CPU time 4.4 seconds
Started Jul 24 05:53:17 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 210460 kb
Host smart-8e37d4b4-8e41-4784-a0bc-4f32fc554f71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848930269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3848930269
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2406014579
Short name T435
Test name
Test status
Simulation time 11035360423 ps
CPU time 49.45 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:54:00 PM PDT 24
Peak memory 210592 kb
Host smart-34f1cff2-521b-46e7-9c7c-e9ef93579ff6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406014579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2406014579
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2134272346
Short name T414
Test name
Test status
Simulation time 1829594081 ps
CPU time 14.51 seconds
Started Jul 24 05:53:17 PM PDT 24
Finished Jul 24 05:53:31 PM PDT 24
Peak memory 210580 kb
Host smart-fa75be1e-0d4a-4c2c-9747-a42850f4a7eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134272346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2134272346
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1959312783
Short name T417
Test name
Test status
Simulation time 1102484362 ps
CPU time 15.84 seconds
Started Jul 24 05:53:12 PM PDT 24
Finished Jul 24 05:53:28 PM PDT 24
Peak memory 218820 kb
Host smart-3e230514-1fb0-492f-9115-31c47ecd3462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959312783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1959312783
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1656963889
Short name T425
Test name
Test status
Simulation time 1978656974 ps
CPU time 39.1 seconds
Started Jul 24 05:53:16 PM PDT 24
Finished Jul 24 05:53:55 PM PDT 24
Peak memory 218844 kb
Host smart-07bc14b3-8a31-47a5-a4ce-c77586246a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656963889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1656963889
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2364895134
Short name T405
Test name
Test status
Simulation time 428435813 ps
CPU time 5.28 seconds
Started Jul 24 05:53:19 PM PDT 24
Finished Jul 24 05:53:24 PM PDT 24
Peak memory 218864 kb
Host smart-4d637008-f8a1-4508-a79d-89746205b79b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364895134 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2364895134
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3360977265
Short name T87
Test name
Test status
Simulation time 88343511 ps
CPU time 4.26 seconds
Started Jul 24 05:53:19 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 210516 kb
Host smart-b5ea9371-1734-4bd0-99bf-1712748d9d47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360977265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3360977265
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2008065566
Short name T88
Test name
Test status
Simulation time 6098317054 ps
CPU time 53.08 seconds
Started Jul 24 05:53:20 PM PDT 24
Finished Jul 24 05:54:13 PM PDT 24
Peak memory 210776 kb
Host smart-03803e06-298f-49dd-bde5-aa23861fa495
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008065566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2008065566
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2996048919
Short name T391
Test name
Test status
Simulation time 1930558581 ps
CPU time 14.62 seconds
Started Jul 24 05:53:19 PM PDT 24
Finished Jul 24 05:53:33 PM PDT 24
Peak memory 210608 kb
Host smart-757ea0bc-c606-45b6-acb1-99855c8626e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996048919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2996048919
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2645386572
Short name T379
Test name
Test status
Simulation time 1514636295 ps
CPU time 15.58 seconds
Started Jul 24 05:53:26 PM PDT 24
Finished Jul 24 05:53:42 PM PDT 24
Peak memory 218792 kb
Host smart-49e5b43f-c44c-4d77-bb5e-2aacc50f97c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645386572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2645386572
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2433644068
Short name T55
Test name
Test status
Simulation time 2864872361 ps
CPU time 40.7 seconds
Started Jul 24 05:53:17 PM PDT 24
Finished Jul 24 05:53:58 PM PDT 24
Peak memory 211988 kb
Host smart-52761211-1f08-413e-9fa9-f88f57c5196e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433644068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2433644068
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4004175558
Short name T429
Test name
Test status
Simulation time 1387543581 ps
CPU time 12.63 seconds
Started Jul 24 05:53:18 PM PDT 24
Finished Jul 24 05:53:31 PM PDT 24
Peak memory 218836 kb
Host smart-6e0f21f0-7644-412f-925d-71921c63a5f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004175558 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.4004175558
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.376121675
Short name T57
Test name
Test status
Simulation time 752025894 ps
CPU time 4.26 seconds
Started Jul 24 05:53:17 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 210496 kb
Host smart-179e7a56-da85-4fd0-a645-0831b607af8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376121675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.376121675
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2250449271
Short name T89
Test name
Test status
Simulation time 41602550687 ps
CPU time 88.18 seconds
Started Jul 24 05:53:18 PM PDT 24
Finished Jul 24 05:54:46 PM PDT 24
Peak memory 210788 kb
Host smart-9e829fdc-6862-484a-b354-e256b36d07d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250449271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2250449271
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3399604160
Short name T404
Test name
Test status
Simulation time 346794015 ps
CPU time 4.26 seconds
Started Jul 24 05:53:17 PM PDT 24
Finished Jul 24 05:53:21 PM PDT 24
Peak memory 218220 kb
Host smart-eeb6fa1c-d83b-4aeb-9501-5fea39f4b630
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399604160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3399604160
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.694683995
Short name T413
Test name
Test status
Simulation time 261791845 ps
CPU time 7.72 seconds
Started Jul 24 05:53:18 PM PDT 24
Finished Jul 24 05:53:26 PM PDT 24
Peak memory 218808 kb
Host smart-d6ff4b9e-1539-423c-8db3-3ea12707d68d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694683995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.694683995
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3032726392
Short name T416
Test name
Test status
Simulation time 2277749738 ps
CPU time 46.95 seconds
Started Jul 24 05:53:19 PM PDT 24
Finished Jul 24 05:54:06 PM PDT 24
Peak memory 212072 kb
Host smart-a365a188-79af-4fc2-8591-3cda8ee734e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032726392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3032726392
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1956267079
Short name T397
Test name
Test status
Simulation time 1435853925 ps
CPU time 12.4 seconds
Started Jul 24 05:53:04 PM PDT 24
Finished Jul 24 05:53:17 PM PDT 24
Peak memory 210560 kb
Host smart-893d5b88-b2a4-4138-8d2c-a4928eeae60a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956267079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1956267079
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.852128354
Short name T387
Test name
Test status
Simulation time 1745832939 ps
CPU time 14.07 seconds
Started Jul 24 05:53:02 PM PDT 24
Finished Jul 24 05:53:17 PM PDT 24
Peak memory 210536 kb
Host smart-84d08ca3-d645-43f0-81d6-8ed48ced6dfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852128354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.852128354
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.509137375
Short name T389
Test name
Test status
Simulation time 2419795552 ps
CPU time 18.69 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:19 PM PDT 24
Peak memory 218644 kb
Host smart-592f8a26-a463-41c5-8b42-755af35646bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509137375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.509137375
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1415565285
Short name T374
Test name
Test status
Simulation time 1111707773 ps
CPU time 6.83 seconds
Started Jul 24 05:53:05 PM PDT 24
Finished Jul 24 05:53:12 PM PDT 24
Peak memory 218876 kb
Host smart-a13afbb1-4dd9-4483-8222-33324e4ada04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415565285 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1415565285
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3148728523
Short name T448
Test name
Test status
Simulation time 19279599412 ps
CPU time 15.43 seconds
Started Jul 24 05:53:03 PM PDT 24
Finished Jul 24 05:53:18 PM PDT 24
Peak memory 210596 kb
Host smart-eb96e387-c8ee-42f4-a1e9-23d3503ad544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148728523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3148728523
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3292888814
Short name T447
Test name
Test status
Simulation time 4325405570 ps
CPU time 10.57 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:53:18 PM PDT 24
Peak memory 210540 kb
Host smart-19026627-7645-46e3-aa99-a28dbe0299da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292888814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3292888814
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.25105610
Short name T438
Test name
Test status
Simulation time 985215744 ps
CPU time 5.78 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:06 PM PDT 24
Peak memory 210404 kb
Host smart-d363e69b-9af3-4bb5-994d-d4876cb91c24
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25105610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.25105610
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1490745618
Short name T64
Test name
Test status
Simulation time 6482014012 ps
CPU time 64.31 seconds
Started Jul 24 05:53:02 PM PDT 24
Finished Jul 24 05:54:07 PM PDT 24
Peak memory 210772 kb
Host smart-7eda609d-da9b-4d09-91ee-8f2959c9abb3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490745618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1490745618
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3770722541
Short name T446
Test name
Test status
Simulation time 86238872 ps
CPU time 4.58 seconds
Started Jul 24 05:53:04 PM PDT 24
Finished Jul 24 05:53:08 PM PDT 24
Peak memory 210572 kb
Host smart-08750f81-2917-4275-bc04-0c66960488b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770722541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3770722541
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1155335427
Short name T395
Test name
Test status
Simulation time 8891398698 ps
CPU time 15.47 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 218956 kb
Host smart-fe211cbf-db88-433a-8bf8-f6b1b55fc897
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155335427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1155335427
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2142972249
Short name T115
Test name
Test status
Simulation time 19267373211 ps
CPU time 73.93 seconds
Started Jul 24 05:53:03 PM PDT 24
Finished Jul 24 05:54:17 PM PDT 24
Peak memory 218940 kb
Host smart-07c67f7e-bb4a-48ff-a291-dd51f38089bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142972249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2142972249
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2161558920
Short name T79
Test name
Test status
Simulation time 4011341664 ps
CPU time 15.27 seconds
Started Jul 24 05:53:03 PM PDT 24
Finished Jul 24 05:53:19 PM PDT 24
Peak memory 210568 kb
Host smart-0179e69c-f2e2-4d81-8d66-fa2ecc8661d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161558920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2161558920
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3576274671
Short name T386
Test name
Test status
Simulation time 5762147030 ps
CPU time 13.08 seconds
Started Jul 24 05:53:01 PM PDT 24
Finished Jul 24 05:53:15 PM PDT 24
Peak memory 217616 kb
Host smart-e6e08335-c16d-4443-9054-776cae0a98b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576274671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3576274671
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.376111317
Short name T84
Test name
Test status
Simulation time 6036440862 ps
CPU time 11.45 seconds
Started Jul 24 05:53:03 PM PDT 24
Finished Jul 24 05:53:15 PM PDT 24
Peak memory 210688 kb
Host smart-6cc313a8-f5b2-46b1-850d-0b025ac8bdb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376111317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.376111317
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4133569853
Short name T375
Test name
Test status
Simulation time 11383370083 ps
CPU time 10.02 seconds
Started Jul 24 05:53:06 PM PDT 24
Finished Jul 24 05:53:16 PM PDT 24
Peak memory 218928 kb
Host smart-22270369-3ae9-4e41-9478-90d1e6d578bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133569853 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4133569853
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3083255218
Short name T403
Test name
Test status
Simulation time 396980205 ps
CPU time 4.18 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:53:11 PM PDT 24
Peak memory 217956 kb
Host smart-c353ac80-ff8b-4cea-905e-d2cb460a9ab4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083255218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3083255218
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.370962833
Short name T423
Test name
Test status
Simulation time 5545362765 ps
CPU time 13.34 seconds
Started Jul 24 05:53:02 PM PDT 24
Finished Jul 24 05:53:15 PM PDT 24
Peak memory 210480 kb
Host smart-0ee6f9e2-5716-4326-b381-69543c775f76
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370962833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.370962833
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3457721493
Short name T457
Test name
Test status
Simulation time 5464359472 ps
CPU time 12.19 seconds
Started Jul 24 05:53:05 PM PDT 24
Finished Jul 24 05:53:17 PM PDT 24
Peak memory 210508 kb
Host smart-3c04e13c-39cd-48de-be9e-6c8b264ccb0f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457721493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3457721493
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1668494927
Short name T407
Test name
Test status
Simulation time 14525989248 ps
CPU time 47.53 seconds
Started Jul 24 05:53:06 PM PDT 24
Finished Jul 24 05:53:54 PM PDT 24
Peak memory 210856 kb
Host smart-4c038560-b6df-44b6-8a56-c82395373e36
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668494927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1668494927
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2486723777
Short name T103
Test name
Test status
Simulation time 89131187 ps
CPU time 4.38 seconds
Started Jul 24 05:53:00 PM PDT 24
Finished Jul 24 05:53:05 PM PDT 24
Peak memory 210508 kb
Host smart-4fe5e6f1-9549-46db-9301-0f831eec6647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486723777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2486723777
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3294465448
Short name T384
Test name
Test status
Simulation time 861153062 ps
CPU time 8.01 seconds
Started Jul 24 05:53:05 PM PDT 24
Finished Jul 24 05:53:13 PM PDT 24
Peak memory 215280 kb
Host smart-785d7c67-1cec-48c3-afcd-ad3ca22f7e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294465448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3294465448
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1976494952
Short name T112
Test name
Test status
Simulation time 1160421036 ps
CPU time 67.53 seconds
Started Jul 24 05:52:59 PM PDT 24
Finished Jul 24 05:54:07 PM PDT 24
Peak memory 212312 kb
Host smart-b7f4e147-e367-4e11-a175-39e3d5a276ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976494952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1976494952
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.167704474
Short name T83
Test name
Test status
Simulation time 347757677 ps
CPU time 4.25 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:53:16 PM PDT 24
Peak memory 210544 kb
Host smart-1bcfb8b0-63ce-45b4-9315-e9e7f9ed878a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167704474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.167704474
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.701966527
Short name T399
Test name
Test status
Simulation time 492456688 ps
CPU time 7.91 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:16 PM PDT 24
Peak memory 210564 kb
Host smart-e191bd52-5dea-4a7f-ab78-3db0741624e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701966527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.701966527
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2964180345
Short name T398
Test name
Test status
Simulation time 653891758 ps
CPU time 9.95 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:53:17 PM PDT 24
Peak memory 217628 kb
Host smart-5508f0ec-19da-406f-9e48-3719b5172416
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964180345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2964180345
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2718250085
Short name T437
Test name
Test status
Simulation time 1375166885 ps
CPU time 12.59 seconds
Started Jul 24 05:53:09 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 216444 kb
Host smart-7c6c5bf7-4f13-45d8-831c-4b71681752ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718250085 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2718250085
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3190635381
Short name T382
Test name
Test status
Simulation time 5725141247 ps
CPU time 12.79 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:21 PM PDT 24
Peak memory 210704 kb
Host smart-b4984fdd-80b9-44ec-8fc4-ad90f54eca76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190635381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3190635381
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4219727641
Short name T408
Test name
Test status
Simulation time 1491643520 ps
CPU time 12.7 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 210408 kb
Host smart-5a83ac32-4e0f-48f3-9b0d-4fadf5eca6f2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219727641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4219727641
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.720154284
Short name T370
Test name
Test status
Simulation time 2129279410 ps
CPU time 17.27 seconds
Started Jul 24 05:53:06 PM PDT 24
Finished Jul 24 05:53:24 PM PDT 24
Peak memory 210380 kb
Host smart-e7aeb4bc-297f-4415-9c17-cfdb54348465
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720154284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
720154284
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2497763380
Short name T461
Test name
Test status
Simulation time 10956128911 ps
CPU time 49.71 seconds
Started Jul 24 05:52:59 PM PDT 24
Finished Jul 24 05:53:49 PM PDT 24
Peak memory 210748 kb
Host smart-84e36fa4-f707-4faf-8660-44683e61065b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497763380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2497763380
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3826691029
Short name T99
Test name
Test status
Simulation time 1340593456 ps
CPU time 11.89 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 210668 kb
Host smart-ac9002be-7424-4abb-a708-b57bbcb77d53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826691029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3826691029
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2364225424
Short name T428
Test name
Test status
Simulation time 3183230677 ps
CPU time 15.51 seconds
Started Jul 24 05:53:04 PM PDT 24
Finished Jul 24 05:53:19 PM PDT 24
Peak memory 218868 kb
Host smart-4129519a-b295-4bf8-8646-55b0f8dbe9a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364225424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2364225424
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.290756442
Short name T117
Test name
Test status
Simulation time 2165267864 ps
CPU time 78.23 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:54:26 PM PDT 24
Peak memory 212212 kb
Host smart-60761aa3-371a-4677-8487-3b26986a333a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290756442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.290756442
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3032577249
Short name T402
Test name
Test status
Simulation time 2451109706 ps
CPU time 11.76 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 218896 kb
Host smart-d09422e3-bdd0-4a3d-8c26-22ba53bc1d20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032577249 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3032577249
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.931315100
Short name T381
Test name
Test status
Simulation time 175636429 ps
CPU time 4.23 seconds
Started Jul 24 05:53:09 PM PDT 24
Finished Jul 24 05:53:13 PM PDT 24
Peak memory 217612 kb
Host smart-740024de-cb90-4564-88ce-34bba9f99c85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931315100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.931315100
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2853491034
Short name T100
Test name
Test status
Simulation time 89142609 ps
CPU time 6.13 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:53:14 PM PDT 24
Peak memory 210668 kb
Host smart-5281f5e1-675d-4fe6-b30c-18b2320044d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853491034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2853491034
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3391893829
Short name T415
Test name
Test status
Simulation time 2692238871 ps
CPU time 13.98 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:53:21 PM PDT 24
Peak memory 218840 kb
Host smart-fc6ddf25-9475-4a9e-8279-74a0e918681b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391893829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3391893829
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1745713061
Short name T464
Test name
Test status
Simulation time 5521454256 ps
CPU time 45.24 seconds
Started Jul 24 05:53:06 PM PDT 24
Finished Jul 24 05:53:51 PM PDT 24
Peak memory 218876 kb
Host smart-7e9f5bf6-1194-4a2a-86ef-47f7d9280b8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745713061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1745713061
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2402203855
Short name T463
Test name
Test status
Simulation time 519870661 ps
CPU time 6.3 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:53:17 PM PDT 24
Peak memory 218740 kb
Host smart-29ab3fc0-829d-41ac-8cbd-80ca2b63a28f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402203855 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2402203855
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.592685958
Short name T418
Test name
Test status
Simulation time 41770210436 ps
CPU time 16.61 seconds
Started Jul 24 05:53:05 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 210704 kb
Host smart-ff7737f6-ea3b-4be8-9349-503ce836830c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592685958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.592685958
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2007940782
Short name T63
Test name
Test status
Simulation time 11474641684 ps
CPU time 53.13 seconds
Started Jul 24 05:53:11 PM PDT 24
Finished Jul 24 05:54:05 PM PDT 24
Peak memory 210820 kb
Host smart-127cf198-5263-4114-9ffe-9219eec02651
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007940782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2007940782
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1621196897
Short name T58
Test name
Test status
Simulation time 85885128 ps
CPU time 4.28 seconds
Started Jul 24 05:53:09 PM PDT 24
Finished Jul 24 05:53:13 PM PDT 24
Peak memory 210628 kb
Host smart-25fb476e-791f-445a-b414-92b16e03d5fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621196897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1621196897
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2440518040
Short name T450
Test name
Test status
Simulation time 3101115749 ps
CPU time 18.07 seconds
Started Jul 24 05:53:09 PM PDT 24
Finished Jul 24 05:53:27 PM PDT 24
Peak memory 218924 kb
Host smart-cc7c2219-f292-47b6-b518-a28f9e4b2e52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440518040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2440518040
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4065746338
Short name T400
Test name
Test status
Simulation time 3290753512 ps
CPU time 9.66 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:53:17 PM PDT 24
Peak memory 218860 kb
Host smart-5fd8c895-1ed8-4cc9-8a66-fc4d9ce05b86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065746338 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4065746338
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.550617997
Short name T376
Test name
Test status
Simulation time 174688404 ps
CPU time 4.18 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:53:12 PM PDT 24
Peak memory 210544 kb
Host smart-89428850-7283-4cef-ab52-a6c9d07b68bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550617997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.550617997
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4131604296
Short name T82
Test name
Test status
Simulation time 7926481573 ps
CPU time 50.56 seconds
Started Jul 24 05:53:05 PM PDT 24
Finished Jul 24 05:53:56 PM PDT 24
Peak memory 210624 kb
Host smart-fbb26528-cd19-45e7-9477-b9200ad00f0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131604296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.4131604296
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.888034965
Short name T101
Test name
Test status
Simulation time 450854469 ps
CPU time 8.7 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:17 PM PDT 24
Peak memory 210636 kb
Host smart-22b5bbfc-b144-4f3a-b782-b07153293a61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888034965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.888034965
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1469574182
Short name T451
Test name
Test status
Simulation time 2468119106 ps
CPU time 13.74 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 218956 kb
Host smart-b0915e21-45f7-4399-b0d8-e90cfe859894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469574182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1469574182
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1779609250
Short name T119
Test name
Test status
Simulation time 1703448929 ps
CPU time 44.41 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:52 PM PDT 24
Peak memory 211976 kb
Host smart-cb96520e-0d5e-4a6a-b2ad-3b4e9e2b305e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779609250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1779609250
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1099295891
Short name T378
Test name
Test status
Simulation time 9247514284 ps
CPU time 16.08 seconds
Started Jul 24 05:53:07 PM PDT 24
Finished Jul 24 05:53:23 PM PDT 24
Peak memory 218912 kb
Host smart-563833a2-9d3b-4920-a764-9a0751412598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099295891 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1099295891
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3364690597
Short name T412
Test name
Test status
Simulation time 6460703092 ps
CPU time 13.59 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:22 PM PDT 24
Peak memory 218792 kb
Host smart-2ff65424-96d7-41bd-ae7a-2c69e8b74845
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364690597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3364690597
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1068506047
Short name T459
Test name
Test status
Simulation time 2356764215 ps
CPU time 43.58 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:53:54 PM PDT 24
Peak memory 210760 kb
Host smart-db1046cd-ef67-4941-a140-cd0d8299e6c2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068506047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1068506047
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4046070911
Short name T455
Test name
Test status
Simulation time 175622238 ps
CPU time 4.35 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:13 PM PDT 24
Peak memory 218104 kb
Host smart-9d7562f4-7afe-4869-a4fc-82b22326315b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046070911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4046070911
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.725487585
Short name T380
Test name
Test status
Simulation time 204459175 ps
CPU time 9.16 seconds
Started Jul 24 05:53:05 PM PDT 24
Finished Jul 24 05:53:15 PM PDT 24
Peak memory 218832 kb
Host smart-b91b913f-ebce-42a8-ad57-59ac722ed7ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725487585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.725487585
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3002117280
Short name T56
Test name
Test status
Simulation time 3876424467 ps
CPU time 72.21 seconds
Started Jul 24 05:53:06 PM PDT 24
Finished Jul 24 05:54:19 PM PDT 24
Peak memory 211056 kb
Host smart-a94ce819-e236-427e-9650-6a7bbaa49d69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002117280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3002117280
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2137255124
Short name T409
Test name
Test status
Simulation time 151194491 ps
CPU time 5.71 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:14 PM PDT 24
Peak memory 218836 kb
Host smart-923f2f5a-0b16-4dbb-9c6c-545d0f2fe1b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137255124 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2137255124
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2296983016
Short name T106
Test name
Test status
Simulation time 1209311610 ps
CPU time 11.03 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:19 PM PDT 24
Peak memory 210484 kb
Host smart-7bccea80-f5bc-45ad-b885-a609984ab727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296983016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2296983016
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2443343041
Short name T453
Test name
Test status
Simulation time 531741586 ps
CPU time 22 seconds
Started Jul 24 05:53:10 PM PDT 24
Finished Jul 24 05:53:32 PM PDT 24
Peak memory 210652 kb
Host smart-58b4bc42-9f7e-4f56-b789-c9d80c5417c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443343041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2443343041
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3572577199
Short name T422
Test name
Test status
Simulation time 2866724872 ps
CPU time 12.06 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:20 PM PDT 24
Peak memory 218776 kb
Host smart-971de36c-5d2c-48a0-8bcd-1902b2aa43e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572577199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3572577199
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3280645085
Short name T373
Test name
Test status
Simulation time 359234883 ps
CPU time 7.05 seconds
Started Jul 24 05:53:08 PM PDT 24
Finished Jul 24 05:53:15 PM PDT 24
Peak memory 218824 kb
Host smart-61af171f-5b39-4d2e-857c-1375b63e7a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280645085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3280645085
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.474006149
Short name T326
Test name
Test status
Simulation time 1245996175 ps
CPU time 10 seconds
Started Jul 24 05:17:51 PM PDT 24
Finished Jul 24 05:18:02 PM PDT 24
Peak memory 211308 kb
Host smart-b97c034f-3bca-4c5b-80a6-9046302af333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474006149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.474006149
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4087914871
Short name T175
Test name
Test status
Simulation time 53449192355 ps
CPU time 247.15 seconds
Started Jul 24 05:18:15 PM PDT 24
Finished Jul 24 05:22:22 PM PDT 24
Peak memory 237780 kb
Host smart-e069299c-a2e7-498a-9603-92eb7472baea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087914871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4087914871
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1785462999
Short name T199
Test name
Test status
Simulation time 1543449722 ps
CPU time 14.19 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:22 PM PDT 24
Peak memory 211396 kb
Host smart-5d7a435f-795a-4bf8-b530-e3e287eec649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785462999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1785462999
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.253416520
Short name T26
Test name
Test status
Simulation time 6648013678 ps
CPU time 102.44 seconds
Started Jul 24 05:17:59 PM PDT 24
Finished Jul 24 05:19:42 PM PDT 24
Peak memory 236280 kb
Host smart-a3e3d3f7-abc6-4f67-9637-dbc31fe73b98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253416520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.253416520
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.585567480
Short name T267
Test name
Test status
Simulation time 3963475429 ps
CPU time 20.5 seconds
Started Jul 24 05:18:05 PM PDT 24
Finished Jul 24 05:18:26 PM PDT 24
Peak memory 213532 kb
Host smart-cc96ea5d-b74d-4e22-95f8-deee9a13c75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585567480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.585567480
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4199831806
Short name T145
Test name
Test status
Simulation time 813363073 ps
CPU time 18.83 seconds
Started Jul 24 05:18:05 PM PDT 24
Finished Jul 24 05:18:24 PM PDT 24
Peak memory 213240 kb
Host smart-0f8c0a62-9560-411f-846d-fca6e4dc36a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199831806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4199831806
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2489602324
Short name T52
Test name
Test status
Simulation time 133213723905 ps
CPU time 1411.89 seconds
Started Jul 24 05:18:06 PM PDT 24
Finished Jul 24 05:41:39 PM PDT 24
Peak memory 235780 kb
Host smart-9d8b8e3f-157b-4045-b06e-78d8cac25f1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489602324 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2489602324
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1407891319
Short name T194
Test name
Test status
Simulation time 88873307 ps
CPU time 4.42 seconds
Started Jul 24 05:18:07 PM PDT 24
Finished Jul 24 05:18:12 PM PDT 24
Peak memory 211312 kb
Host smart-45753960-045e-47b0-b9f8-c8cf50e2acf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407891319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1407891319
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1729885535
Short name T364
Test name
Test status
Simulation time 158123048203 ps
CPU time 405.13 seconds
Started Jul 24 05:18:05 PM PDT 24
Finished Jul 24 05:24:51 PM PDT 24
Peak memory 228656 kb
Host smart-8a9dc78e-d4fd-42af-a0e1-0a77899645b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729885535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1729885535
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4130739723
Short name T285
Test name
Test status
Simulation time 345920195 ps
CPU time 8.34 seconds
Started Jul 24 05:18:09 PM PDT 24
Finished Jul 24 05:18:18 PM PDT 24
Peak memory 211276 kb
Host smart-50a8555f-5c91-4eb1-a869-f6b086a87cb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130739723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4130739723
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1597656755
Short name T21
Test name
Test status
Simulation time 1870205395 ps
CPU time 107.44 seconds
Started Jul 24 05:18:07 PM PDT 24
Finished Jul 24 05:19:55 PM PDT 24
Peak memory 237964 kb
Host smart-93840a7a-402e-45f8-a24a-72ddf3e256e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597656755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1597656755
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.159048921
Short name T249
Test name
Test status
Simulation time 17400359123 ps
CPU time 28.38 seconds
Started Jul 24 05:18:20 PM PDT 24
Finished Jul 24 05:18:49 PM PDT 24
Peak memory 213916 kb
Host smart-8442eee5-4e97-4153-a9aa-821511ef6d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159048921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.159048921
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2484435843
Short name T147
Test name
Test status
Simulation time 4757140516 ps
CPU time 50.01 seconds
Started Jul 24 05:18:25 PM PDT 24
Finished Jul 24 05:19:15 PM PDT 24
Peak memory 213520 kb
Host smart-a96880eb-13bc-4d21-a701-6734d9496de9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484435843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2484435843
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4201514744
Short name T251
Test name
Test status
Simulation time 347908983 ps
CPU time 4.36 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:13 PM PDT 24
Peak memory 211316 kb
Host smart-59002d0e-4372-4661-9255-a0e6ee0c8e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201514744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4201514744
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.869618
Short name T317
Test name
Test status
Simulation time 18804427364 ps
CPU time 221.57 seconds
Started Jul 24 05:18:22 PM PDT 24
Finished Jul 24 05:22:04 PM PDT 24
Peak memory 233792 kb
Host smart-7e54db6d-07ba-47c8-92dd-1bbc877cbf10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_si
g_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corr
upt_sig_fatal_chk.869618
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2561734630
Short name T216
Test name
Test status
Simulation time 3766658764 ps
CPU time 15.28 seconds
Started Jul 24 05:18:11 PM PDT 24
Finished Jul 24 05:18:27 PM PDT 24
Peak memory 211932 kb
Host smart-159c7615-1791-4b8e-ba41-32c9f823acd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561734630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2561734630
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.665863492
Short name T179
Test name
Test status
Simulation time 104719362 ps
CPU time 5.51 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:14 PM PDT 24
Peak memory 211356 kb
Host smart-61eab915-5e3c-4778-8ee3-7c70874bc248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=665863492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.665863492
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1681644738
Short name T308
Test name
Test status
Simulation time 4053983155 ps
CPU time 39.69 seconds
Started Jul 24 05:18:12 PM PDT 24
Finished Jul 24 05:18:52 PM PDT 24
Peak memory 213264 kb
Host smart-67878af7-f21d-400f-98aa-f4dfc94455f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681644738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1681644738
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3343658279
Short name T72
Test name
Test status
Simulation time 36121337847 ps
CPU time 86.61 seconds
Started Jul 24 05:18:17 PM PDT 24
Finished Jul 24 05:19:43 PM PDT 24
Peak memory 216476 kb
Host smart-33150956-26be-491e-adbe-fc1d44a8eb95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343658279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3343658279
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3961494604
Short name T46
Test name
Test status
Simulation time 64973191077 ps
CPU time 2062.18 seconds
Started Jul 24 05:18:13 PM PDT 24
Finished Jul 24 05:52:36 PM PDT 24
Peak memory 235792 kb
Host smart-19598feb-0542-4a75-b926-587fc03f2882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961494604 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3961494604
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3992229925
Short name T274
Test name
Test status
Simulation time 1449303972 ps
CPU time 6.51 seconds
Started Jul 24 05:18:28 PM PDT 24
Finished Jul 24 05:18:40 PM PDT 24
Peak memory 211256 kb
Host smart-3b42a560-7d69-4894-a7c4-af292510bf0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992229925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3992229925
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3518769873
Short name T307
Test name
Test status
Simulation time 152099151483 ps
CPU time 370.92 seconds
Started Jul 24 05:18:10 PM PDT 24
Finished Jul 24 05:24:21 PM PDT 24
Peak memory 236924 kb
Host smart-175bee23-adce-43a5-87e4-a8b53f04f9a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518769873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3518769873
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1891746750
Short name T286
Test name
Test status
Simulation time 14083971904 ps
CPU time 30.46 seconds
Started Jul 24 05:18:16 PM PDT 24
Finished Jul 24 05:18:46 PM PDT 24
Peak memory 212304 kb
Host smart-b0bdcb77-7c57-4bab-b703-219a1ba9ba37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891746750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1891746750
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.116500721
Short name T330
Test name
Test status
Simulation time 2161416289 ps
CPU time 17.47 seconds
Started Jul 24 05:18:28 PM PDT 24
Finished Jul 24 05:18:46 PM PDT 24
Peak memory 211360 kb
Host smart-6166826f-1a36-46f5-94fc-0917c4400665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116500721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.116500721
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1854458952
Short name T107
Test name
Test status
Simulation time 3344014554 ps
CPU time 29.07 seconds
Started Jul 24 05:18:15 PM PDT 24
Finished Jul 24 05:18:44 PM PDT 24
Peak memory 213068 kb
Host smart-c4136152-08c1-4c24-91ec-73d18bcc9380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854458952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1854458952
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1069716007
Short name T173
Test name
Test status
Simulation time 40274645279 ps
CPU time 68.33 seconds
Started Jul 24 05:18:20 PM PDT 24
Finished Jul 24 05:19:33 PM PDT 24
Peak memory 219376 kb
Host smart-c822ed62-66c2-4b4f-84f9-6229c4855ca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069716007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1069716007
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2954240535
Short name T166
Test name
Test status
Simulation time 346523400 ps
CPU time 4.19 seconds
Started Jul 24 05:18:14 PM PDT 24
Finished Jul 24 05:18:24 PM PDT 24
Peak memory 211252 kb
Host smart-3c4ca8d7-531b-402b-8649-7362ac756a7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954240535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2954240535
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2846418653
Short name T202
Test name
Test status
Simulation time 10145662611 ps
CPU time 24.37 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:33 PM PDT 24
Peak memory 212416 kb
Host smart-803a856b-bdf3-4e9b-b633-c218fa548022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846418653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2846418653
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.529539790
Short name T150
Test name
Test status
Simulation time 6872986605 ps
CPU time 8.87 seconds
Started Jul 24 05:18:17 PM PDT 24
Finished Jul 24 05:18:26 PM PDT 24
Peak memory 211428 kb
Host smart-812bff8d-b2d8-4135-9d9f-56c3898e6205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529539790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.529539790
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2243292501
Short name T276
Test name
Test status
Simulation time 764194995 ps
CPU time 9.61 seconds
Started Jul 24 05:18:12 PM PDT 24
Finished Jul 24 05:18:22 PM PDT 24
Peak memory 213740 kb
Host smart-4eaab7fc-8db2-406a-8a43-50f6523d0e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243292501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2243292501
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.606236607
Short name T291
Test name
Test status
Simulation time 1102949264 ps
CPU time 17.42 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 05:18:35 PM PDT 24
Peak memory 214984 kb
Host smart-955f00b9-ff02-42a7-9713-90d333492919
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606236607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.606236607
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1068532821
Short name T93
Test name
Test status
Simulation time 2027006793 ps
CPU time 16.39 seconds
Started Jul 24 05:18:21 PM PDT 24
Finished Jul 24 05:18:43 PM PDT 24
Peak memory 211336 kb
Host smart-262f3992-939f-472f-8565-49eda41c9ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068532821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1068532821
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2642826058
Short name T184
Test name
Test status
Simulation time 19249215456 ps
CPU time 120 seconds
Started Jul 24 05:18:13 PM PDT 24
Finished Jul 24 05:20:13 PM PDT 24
Peak memory 237856 kb
Host smart-71972a61-51f5-4ef8-aef7-e27a47549200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642826058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2642826058
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2829986555
Short name T264
Test name
Test status
Simulation time 4686659907 ps
CPU time 22.89 seconds
Started Jul 24 05:18:36 PM PDT 24
Finished Jul 24 05:18:59 PM PDT 24
Peak memory 212192 kb
Host smart-4c248a27-ac46-46dd-a88f-07eb5f84fb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829986555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2829986555
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3615775467
Short name T185
Test name
Test status
Simulation time 3913023538 ps
CPU time 11.05 seconds
Started Jul 24 05:18:21 PM PDT 24
Finished Jul 24 05:18:33 PM PDT 24
Peak memory 211440 kb
Host smart-4547949d-280a-48a0-b8e3-a624a286dfbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615775467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3615775467
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1066943573
Short name T7
Test name
Test status
Simulation time 717487309 ps
CPU time 15.23 seconds
Started Jul 24 05:18:19 PM PDT 24
Finished Jul 24 05:18:35 PM PDT 24
Peak memory 212728 kb
Host smart-29f51461-5f01-4361-a9d7-18a2550337bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066943573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1066943573
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.803401096
Short name T342
Test name
Test status
Simulation time 31848553268 ps
CPU time 40.18 seconds
Started Jul 24 05:18:27 PM PDT 24
Finished Jul 24 05:19:07 PM PDT 24
Peak memory 214572 kb
Host smart-996ef9c4-9f4c-4556-b21b-50c973e68a91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803401096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.803401096
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3964358698
Short name T265
Test name
Test status
Simulation time 165226399 ps
CPU time 4.13 seconds
Started Jul 24 05:18:16 PM PDT 24
Finished Jul 24 05:18:21 PM PDT 24
Peak memory 211320 kb
Host smart-a1e6de6b-3ca3-4286-a89b-3b6beb5a2417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964358698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3964358698
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1439399846
Short name T236
Test name
Test status
Simulation time 1807327762 ps
CPU time 15.43 seconds
Started Jul 24 05:18:23 PM PDT 24
Finished Jul 24 05:18:38 PM PDT 24
Peak memory 212024 kb
Host smart-77fdd493-f724-4242-b9ff-d689bf9ceefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439399846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1439399846
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.778197085
Short name T146
Test name
Test status
Simulation time 7463449113 ps
CPU time 16.28 seconds
Started Jul 24 05:18:14 PM PDT 24
Finished Jul 24 05:18:30 PM PDT 24
Peak memory 211488 kb
Host smart-7e993aa9-b454-4806-8d5a-5eaec4b5cae5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=778197085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.778197085
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2321663834
Short name T130
Test name
Test status
Simulation time 20632737049 ps
CPU time 27.08 seconds
Started Jul 24 05:18:17 PM PDT 24
Finished Jul 24 05:18:45 PM PDT 24
Peak memory 214056 kb
Host smart-ab4c06f7-92c0-4a37-b2f6-a070996676a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321663834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2321663834
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2049151592
Short name T61
Test name
Test status
Simulation time 2176390547 ps
CPU time 9.96 seconds
Started Jul 24 05:18:26 PM PDT 24
Finished Jul 24 05:18:36 PM PDT 24
Peak memory 211380 kb
Host smart-b8550131-cee5-4a6c-989b-b684b78c3c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049151592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2049151592
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1045436121
Short name T149
Test name
Test status
Simulation time 2067573322 ps
CPU time 131.81 seconds
Started Jul 24 05:18:17 PM PDT 24
Finished Jul 24 05:20:29 PM PDT 24
Peak memory 237048 kb
Host smart-dafc3264-e07c-49af-9c97-8278d2189413
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045436121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1045436121
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2441163017
Short name T211
Test name
Test status
Simulation time 2964065460 ps
CPU time 20.05 seconds
Started Jul 24 05:18:27 PM PDT 24
Finished Jul 24 05:18:47 PM PDT 24
Peak memory 211952 kb
Host smart-13085d13-2d01-41db-b397-30a66274d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441163017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2441163017
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2170320777
Short name T298
Test name
Test status
Simulation time 6635270404 ps
CPU time 17.19 seconds
Started Jul 24 05:18:20 PM PDT 24
Finished Jul 24 05:18:37 PM PDT 24
Peak memory 211476 kb
Host smart-c517b5da-a35c-49a2-9a5d-85aa158b3848
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170320777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2170320777
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4148676702
Short name T230
Test name
Test status
Simulation time 3381052459 ps
CPU time 28 seconds
Started Jul 24 05:18:19 PM PDT 24
Finished Jul 24 05:18:47 PM PDT 24
Peak memory 213056 kb
Host smart-9485e1a9-779c-49f7-ab88-34a2c9af8891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148676702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4148676702
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3033757267
Short name T34
Test name
Test status
Simulation time 1275889795 ps
CPU time 22.69 seconds
Started Jul 24 05:18:25 PM PDT 24
Finished Jul 24 05:18:48 PM PDT 24
Peak memory 215372 kb
Host smart-08fc7bf3-c693-461e-8392-a3c059eacf36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033757267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3033757267
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3679956706
Short name T62
Test name
Test status
Simulation time 85657476 ps
CPU time 4.13 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 05:18:27 PM PDT 24
Peak memory 211300 kb
Host smart-3a049982-2e6d-419d-b95a-8c7c172a97d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679956706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3679956706
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1501471092
Short name T324
Test name
Test status
Simulation time 2432492593 ps
CPU time 65.96 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 05:19:24 PM PDT 24
Peak memory 236748 kb
Host smart-f5b7eef8-fe64-4021-aacd-4448e322dbe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501471092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1501471092
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.151050741
Short name T187
Test name
Test status
Simulation time 16149335149 ps
CPU time 31.63 seconds
Started Jul 24 05:18:17 PM PDT 24
Finished Jul 24 05:18:49 PM PDT 24
Peak memory 212324 kb
Host smart-1fab2b30-3dd6-4744-80e5-8e28488897dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151050741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.151050741
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2444293756
Short name T165
Test name
Test status
Simulation time 6012026281 ps
CPU time 14.06 seconds
Started Jul 24 05:18:26 PM PDT 24
Finished Jul 24 05:18:41 PM PDT 24
Peak memory 211376 kb
Host smart-addf5a39-c761-4fb1-add4-ca7b11b1fe36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444293756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2444293756
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4071866306
Short name T71
Test name
Test status
Simulation time 7618290522 ps
CPU time 36.42 seconds
Started Jul 24 05:18:24 PM PDT 24
Finished Jul 24 05:19:01 PM PDT 24
Peak memory 214348 kb
Host smart-2bff5649-daa0-4394-9d97-a55002c16a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071866306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4071866306
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4047140875
Short name T254
Test name
Test status
Simulation time 44559086331 ps
CPU time 87.33 seconds
Started Jul 24 05:18:24 PM PDT 24
Finished Jul 24 05:19:52 PM PDT 24
Peak memory 217852 kb
Host smart-4af7db20-c0c9-4e1f-a6bd-e4a3d8f4784b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047140875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4047140875
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3093564291
Short name T167
Test name
Test status
Simulation time 85524592 ps
CPU time 4.31 seconds
Started Jul 24 05:18:11 PM PDT 24
Finished Jul 24 05:18:15 PM PDT 24
Peak memory 211372 kb
Host smart-65bf570e-f2fc-49b4-8840-4c2bdd5629a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093564291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3093564291
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1709169809
Short name T343
Test name
Test status
Simulation time 194925471768 ps
CPU time 471.45 seconds
Started Jul 24 05:18:23 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 212924 kb
Host smart-c3c87184-b158-41f2-9aba-1477c7239cb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709169809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1709169809
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4115098772
Short name T32
Test name
Test status
Simulation time 172043191 ps
CPU time 9.47 seconds
Started Jul 24 05:18:24 PM PDT 24
Finished Jul 24 05:18:33 PM PDT 24
Peak memory 211984 kb
Host smart-34bcea6b-294f-40f8-9d29-50b61058acbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115098772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4115098772
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3730597810
Short name T197
Test name
Test status
Simulation time 3865344267 ps
CPU time 8.16 seconds
Started Jul 24 05:18:14 PM PDT 24
Finished Jul 24 05:18:23 PM PDT 24
Peak memory 211476 kb
Host smart-e443af78-c7b3-4fa3-aafc-e7e3d15a9404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730597810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3730597810
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3466356435
Short name T263
Test name
Test status
Simulation time 2046053254 ps
CPU time 14.72 seconds
Started Jul 24 05:18:20 PM PDT 24
Finished Jul 24 05:18:35 PM PDT 24
Peak memory 213676 kb
Host smart-66db3d1b-9af8-4964-9b63-96b548aa343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466356435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3466356435
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2220729809
Short name T177
Test name
Test status
Simulation time 5963463386 ps
CPU time 27.74 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 05:18:46 PM PDT 24
Peak memory 214512 kb
Host smart-70e2a48e-f3a5-4da6-901d-040e3f91e3be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220729809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2220729809
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.4152795601
Short name T352
Test name
Test status
Simulation time 76063904932 ps
CPU time 6661.63 seconds
Started Jul 24 05:18:29 PM PDT 24
Finished Jul 24 07:09:31 PM PDT 24
Peak memory 235920 kb
Host smart-e17cf298-07a2-4709-968c-74576eab69dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152795601 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.4152795601
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3814940618
Short name T275
Test name
Test status
Simulation time 303595540 ps
CPU time 6.18 seconds
Started Jul 24 05:18:28 PM PDT 24
Finished Jul 24 05:18:34 PM PDT 24
Peak memory 211340 kb
Host smart-55684e73-1e68-4707-9ab5-7d658cc74949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814940618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3814940618
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1538116018
Short name T152
Test name
Test status
Simulation time 53913854649 ps
CPU time 168.36 seconds
Started Jul 24 05:18:14 PM PDT 24
Finished Jul 24 05:21:02 PM PDT 24
Peak memory 233892 kb
Host smart-ced0a753-2d32-4d83-94da-395fcd59f547
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538116018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1538116018
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4082532938
Short name T339
Test name
Test status
Simulation time 174964868 ps
CPU time 9.73 seconds
Started Jul 24 05:18:21 PM PDT 24
Finished Jul 24 05:18:31 PM PDT 24
Peak memory 211880 kb
Host smart-1030ee2d-a836-4461-86b5-710c77d2c8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082532938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4082532938
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.697142598
Short name T368
Test name
Test status
Simulation time 2139719539 ps
CPU time 8.99 seconds
Started Jul 24 05:18:29 PM PDT 24
Finished Jul 24 05:18:39 PM PDT 24
Peak memory 211384 kb
Host smart-da082b49-7e01-4dbb-9b6e-049e09a228d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697142598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.697142598
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1882336427
Short name T325
Test name
Test status
Simulation time 1835043744 ps
CPU time 22.96 seconds
Started Jul 24 05:18:21 PM PDT 24
Finished Jul 24 05:18:44 PM PDT 24
Peak memory 213680 kb
Host smart-2520257e-2351-460a-babb-cb78f5bac72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882336427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1882336427
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2275748104
Short name T289
Test name
Test status
Simulation time 46081557459 ps
CPU time 86.79 seconds
Started Jul 24 05:18:17 PM PDT 24
Finished Jul 24 05:19:44 PM PDT 24
Peak memory 217208 kb
Host smart-b6e58091-87ea-4211-af72-177836ea7b58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275748104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2275748104
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3003328797
Short name T23
Test name
Test status
Simulation time 141339538075 ps
CPU time 8190.64 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 07:34:50 PM PDT 24
Peak memory 235828 kb
Host smart-7e21f1a8-2dd3-4993-a3e1-f891dc0d9a54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003328797 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3003328797
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2293245751
Short name T268
Test name
Test status
Simulation time 8188113441 ps
CPU time 13.73 seconds
Started Jul 24 05:18:24 PM PDT 24
Finished Jul 24 05:18:43 PM PDT 24
Peak memory 211332 kb
Host smart-c10f21bf-7faf-4048-ac71-20ad5dbe8aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293245751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2293245751
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2088354925
Short name T363
Test name
Test status
Simulation time 1161909103 ps
CPU time 73.69 seconds
Started Jul 24 05:18:16 PM PDT 24
Finished Jul 24 05:19:30 PM PDT 24
Peak memory 236732 kb
Host smart-7c3b555c-181e-491d-90a1-f537617f020a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088354925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2088354925
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.291382736
Short name T209
Test name
Test status
Simulation time 4228629832 ps
CPU time 16.72 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 05:18:35 PM PDT 24
Peak memory 212024 kb
Host smart-61a06af8-8b68-4c6f-9ae5-56ee278182c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291382736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.291382736
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1015785419
Short name T125
Test name
Test status
Simulation time 2089511967 ps
CPU time 16.24 seconds
Started Jul 24 05:18:13 PM PDT 24
Finished Jul 24 05:18:30 PM PDT 24
Peak memory 211392 kb
Host smart-6aca49af-80c8-47d6-91e4-f7a165fe40d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015785419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1015785419
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.376301177
Short name T278
Test name
Test status
Simulation time 2795058968 ps
CPU time 22.43 seconds
Started Jul 24 05:18:20 PM PDT 24
Finished Jul 24 05:18:43 PM PDT 24
Peak memory 212984 kb
Host smart-23a8dccb-ad9b-4566-a794-259913cecc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376301177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.376301177
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.168455842
Short name T223
Test name
Test status
Simulation time 2624254760 ps
CPU time 35.36 seconds
Started Jul 24 05:18:14 PM PDT 24
Finished Jul 24 05:18:50 PM PDT 24
Peak memory 216508 kb
Host smart-1b79b0a6-d150-497a-b5bf-9472e09959cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168455842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.168455842
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3550309000
Short name T357
Test name
Test status
Simulation time 2464392615 ps
CPU time 11.49 seconds
Started Jul 24 05:18:11 PM PDT 24
Finished Jul 24 05:18:22 PM PDT 24
Peak memory 211388 kb
Host smart-f836a791-9c5a-417e-9b6f-dcb396afabf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550309000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3550309000
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.375523632
Short name T38
Test name
Test status
Simulation time 1516727212 ps
CPU time 108.78 seconds
Started Jul 24 05:18:00 PM PDT 24
Finished Jul 24 05:19:49 PM PDT 24
Peak memory 236748 kb
Host smart-9758af32-a586-492d-b70d-945602307fcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375523632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.375523632
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3533844690
Short name T126
Test name
Test status
Simulation time 3110934165 ps
CPU time 19.21 seconds
Started Jul 24 05:18:12 PM PDT 24
Finished Jul 24 05:18:32 PM PDT 24
Peak memory 211884 kb
Host smart-436b497f-d1b8-4ef4-bc56-33b7854c4916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533844690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3533844690
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1443131915
Short name T348
Test name
Test status
Simulation time 99476542 ps
CPU time 5.6 seconds
Started Jul 24 05:18:13 PM PDT 24
Finished Jul 24 05:18:19 PM PDT 24
Peak memory 211412 kb
Host smart-40373bb4-268b-423f-9841-11eab12d93eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443131915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1443131915
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2820445263
Short name T25
Test name
Test status
Simulation time 1587064703 ps
CPU time 104.79 seconds
Started Jul 24 05:17:54 PM PDT 24
Finished Jul 24 05:19:39 PM PDT 24
Peak memory 236772 kb
Host smart-d3e6827a-ecb9-43ad-8156-e44d5684333d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820445263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2820445263
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2352567689
Short name T282
Test name
Test status
Simulation time 8224818946 ps
CPU time 39.93 seconds
Started Jul 24 05:18:07 PM PDT 24
Finished Jul 24 05:18:47 PM PDT 24
Peak memory 213860 kb
Host smart-b035bde1-f61a-441f-b516-0d8bcf950da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352567689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2352567689
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3434399861
Short name T332
Test name
Test status
Simulation time 148113681109 ps
CPU time 69.5 seconds
Started Jul 24 05:18:01 PM PDT 24
Finished Jul 24 05:19:10 PM PDT 24
Peak memory 217236 kb
Host smart-d87cb2c2-e6cc-4951-80d6-de5493d116ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434399861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3434399861
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1699486551
Short name T293
Test name
Test status
Simulation time 2048698353 ps
CPU time 11.14 seconds
Started Jul 24 05:18:25 PM PDT 24
Finished Jul 24 05:18:36 PM PDT 24
Peak memory 211340 kb
Host smart-24e9ccbb-65c1-4f56-b750-1cb720e99fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699486551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1699486551
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4147169162
Short name T366
Test name
Test status
Simulation time 2059259062 ps
CPU time 111.87 seconds
Started Jul 24 05:18:21 PM PDT 24
Finished Jul 24 05:20:13 PM PDT 24
Peak memory 236668 kb
Host smart-1aa74b84-cfd3-48da-bbbc-63fdfcdf8e7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147169162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4147169162
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.499750061
Short name T192
Test name
Test status
Simulation time 21824773660 ps
CPU time 24.61 seconds
Started Jul 24 05:18:28 PM PDT 24
Finished Jul 24 05:18:53 PM PDT 24
Peak memory 211400 kb
Host smart-55a048ff-fe13-4a73-9daf-9c59720eb3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499750061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.499750061
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3669601075
Short name T323
Test name
Test status
Simulation time 379626903 ps
CPU time 5.34 seconds
Started Jul 24 05:18:26 PM PDT 24
Finished Jul 24 05:18:31 PM PDT 24
Peak memory 211384 kb
Host smart-12531c8e-ddcd-4643-bbb7-51d2b799e9bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3669601075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3669601075
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.810039623
Short name T193
Test name
Test status
Simulation time 184797124 ps
CPU time 10.44 seconds
Started Jul 24 05:18:23 PM PDT 24
Finished Jul 24 05:18:34 PM PDT 24
Peak memory 213404 kb
Host smart-defba6db-6e92-45e6-8e47-146f136af385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810039623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.810039623
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1915443403
Short name T95
Test name
Test status
Simulation time 549785186 ps
CPU time 10.42 seconds
Started Jul 24 05:18:22 PM PDT 24
Finished Jul 24 05:18:33 PM PDT 24
Peak memory 211152 kb
Host smart-f3c98fca-24fa-4bc9-a259-a1d0c1ba3650
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915443403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1915443403
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1604437522
Short name T49
Test name
Test status
Simulation time 31148638433 ps
CPU time 3722.18 seconds
Started Jul 24 05:18:25 PM PDT 24
Finished Jul 24 06:20:28 PM PDT 24
Peak memory 229528 kb
Host smart-c71986e4-95b1-45cb-9988-0422f2c28ab5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604437522 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1604437522
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3712057829
Short name T203
Test name
Test status
Simulation time 4081152127 ps
CPU time 11.6 seconds
Started Jul 24 05:18:19 PM PDT 24
Finished Jul 24 05:18:30 PM PDT 24
Peak memory 211368 kb
Host smart-8376e4b1-9297-4e82-8ee6-48faa8280f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712057829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3712057829
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1550069475
Short name T36
Test name
Test status
Simulation time 31125427801 ps
CPU time 93.52 seconds
Started Jul 24 05:18:21 PM PDT 24
Finished Jul 24 05:19:55 PM PDT 24
Peak memory 237792 kb
Host smart-869b0f62-10dd-4e79-8525-21e494c4c6f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550069475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1550069475
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1676770575
Short name T304
Test name
Test status
Simulation time 510562705 ps
CPU time 12.42 seconds
Started Jul 24 05:18:22 PM PDT 24
Finished Jul 24 05:18:35 PM PDT 24
Peak memory 213004 kb
Host smart-5355c975-90ce-4873-a2ba-fa35539a879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676770575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1676770575
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3848440459
Short name T250
Test name
Test status
Simulation time 790123887 ps
CPU time 9.89 seconds
Started Jul 24 05:18:20 PM PDT 24
Finished Jul 24 05:18:30 PM PDT 24
Peak memory 211412 kb
Host smart-186a50bc-94c5-4351-bde8-177870701b18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3848440459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3848440459
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3695529999
Short name T12
Test name
Test status
Simulation time 1087013859 ps
CPU time 14.01 seconds
Started Jul 24 05:18:29 PM PDT 24
Finished Jul 24 05:18:44 PM PDT 24
Peak memory 213760 kb
Host smart-438ddc08-2801-4893-9f66-1f79cf4ffcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695529999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3695529999
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2110471171
Short name T131
Test name
Test status
Simulation time 304407664 ps
CPU time 14.6 seconds
Started Jul 24 05:18:25 PM PDT 24
Finished Jul 24 05:18:40 PM PDT 24
Peak memory 214708 kb
Host smart-9a12ea06-c4da-4083-8f63-d6708d3f737b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110471171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2110471171
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4173373534
Short name T314
Test name
Test status
Simulation time 122055333763 ps
CPU time 1320.29 seconds
Started Jul 24 05:18:11 PM PDT 24
Finished Jul 24 05:40:12 PM PDT 24
Peak memory 235872 kb
Host smart-353530d1-9b63-411f-919f-9b476d30a74a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173373534 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.4173373534
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3858712696
Short name T302
Test name
Test status
Simulation time 6270520636 ps
CPU time 96.46 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 05:20:11 PM PDT 24
Peak memory 237076 kb
Host smart-44a431a5-51f2-4913-ae16-ac9a4932b770
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858712696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3858712696
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2692262808
Short name T29
Test name
Test status
Simulation time 35317221793 ps
CPU time 29.75 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:19:13 PM PDT 24
Peak memory 212840 kb
Host smart-9db59a03-65c8-4f95-982d-74f6af4bc6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692262808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2692262808
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2081560933
Short name T15
Test name
Test status
Simulation time 1083375356 ps
CPU time 12.25 seconds
Started Jul 24 05:18:15 PM PDT 24
Finished Jul 24 05:18:27 PM PDT 24
Peak memory 211396 kb
Host smart-bf81651e-53b0-434b-ab46-c49068d84f6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081560933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2081560933
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.355037179
Short name T239
Test name
Test status
Simulation time 9543463829 ps
CPU time 16.99 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:18:54 PM PDT 24
Peak memory 213992 kb
Host smart-38c3ab74-719c-4cf5-a823-2d9144327825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355037179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.355037179
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2078133749
Short name T336
Test name
Test status
Simulation time 3262595200 ps
CPU time 31.57 seconds
Started Jul 24 05:18:21 PM PDT 24
Finished Jul 24 05:18:52 PM PDT 24
Peak memory 214932 kb
Host smart-e848403f-4f53-4f9d-b43f-6243960aed9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078133749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2078133749
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1934506935
Short name T224
Test name
Test status
Simulation time 2271822446 ps
CPU time 10.49 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 05:18:45 PM PDT 24
Peak memory 211384 kb
Host smart-8ec765aa-c0af-449d-970e-6232af7f9e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934506935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1934506935
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1489075443
Short name T128
Test name
Test status
Simulation time 115303897814 ps
CPU time 238.38 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 05:22:17 PM PDT 24
Peak memory 212656 kb
Host smart-4ac6b5dc-eef7-487a-88ce-f12f1a96a0a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489075443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1489075443
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.480149512
Short name T139
Test name
Test status
Simulation time 2623787139 ps
CPU time 13.98 seconds
Started Jul 24 05:18:40 PM PDT 24
Finished Jul 24 05:18:54 PM PDT 24
Peak memory 212016 kb
Host smart-855adb19-3d44-486a-86bc-32ad987e9def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480149512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.480149512
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.251325052
Short name T27
Test name
Test status
Simulation time 611741462 ps
CPU time 8.68 seconds
Started Jul 24 05:18:36 PM PDT 24
Finished Jul 24 05:18:45 PM PDT 24
Peak memory 211392 kb
Host smart-f44e6f7f-1103-4a38-b4a6-c182a057cdc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251325052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.251325052
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1361316740
Short name T255
Test name
Test status
Simulation time 648536156 ps
CPU time 9.93 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:18:47 PM PDT 24
Peak memory 213464 kb
Host smart-cfca9014-fb01-44d5-928e-8a00d86438b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361316740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1361316740
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1752810404
Short name T313
Test name
Test status
Simulation time 7249605670 ps
CPU time 82 seconds
Started Jul 24 05:18:22 PM PDT 24
Finished Jul 24 05:19:44 PM PDT 24
Peak memory 219400 kb
Host smart-66e1f14b-87ff-47b1-8c1c-6f8dac7a7947
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752810404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1752810404
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3814779464
Short name T127
Test name
Test status
Simulation time 8346211501 ps
CPU time 15.42 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 05:18:50 PM PDT 24
Peak memory 211412 kb
Host smart-796802f4-a672-4401-923e-d57b7bdfbb5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814779464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3814779464
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3703029853
Short name T121
Test name
Test status
Simulation time 30400014369 ps
CPU time 278.63 seconds
Started Jul 24 05:18:50 PM PDT 24
Finished Jul 24 05:23:29 PM PDT 24
Peak memory 228596 kb
Host smart-709bd645-39d1-42b8-a577-5690c4eaa5a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703029853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3703029853
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4057403891
Short name T164
Test name
Test status
Simulation time 13387255153 ps
CPU time 16.6 seconds
Started Jul 24 05:18:21 PM PDT 24
Finished Jul 24 05:18:38 PM PDT 24
Peak memory 212544 kb
Host smart-c38bf0b0-4472-4686-a077-2de03dc454c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057403891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4057403891
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.697609525
Short name T237
Test name
Test status
Simulation time 1006750491 ps
CPU time 11.11 seconds
Started Jul 24 05:18:20 PM PDT 24
Finished Jul 24 05:18:32 PM PDT 24
Peak memory 211416 kb
Host smart-c21d66b5-0c5b-4afe-8f41-8fddd8aa2f23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697609525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.697609525
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1777074740
Short name T74
Test name
Test status
Simulation time 6172026761 ps
CPU time 32.3 seconds
Started Jul 24 05:18:44 PM PDT 24
Finished Jul 24 05:19:16 PM PDT 24
Peak memory 214712 kb
Host smart-15a5d509-e1d7-477c-bae5-2cc74c4c40c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777074740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1777074740
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2167170410
Short name T320
Test name
Test status
Simulation time 16895118988 ps
CPU time 35.49 seconds
Started Jul 24 05:18:17 PM PDT 24
Finished Jul 24 05:18:53 PM PDT 24
Peak memory 214812 kb
Host smart-730b2734-ae82-4246-ba0c-9a55d9becc4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167170410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2167170410
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.965893951
Short name T247
Test name
Test status
Simulation time 1320186803 ps
CPU time 9.14 seconds
Started Jul 24 05:18:50 PM PDT 24
Finished Jul 24 05:19:00 PM PDT 24
Peak memory 211232 kb
Host smart-a62314cf-4986-4ebd-a64e-837694576161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965893951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.965893951
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1367775652
Short name T160
Test name
Test status
Simulation time 154622932669 ps
CPU time 323.06 seconds
Started Jul 24 05:18:27 PM PDT 24
Finished Jul 24 05:23:50 PM PDT 24
Peak memory 234220 kb
Host smart-15c5b9e6-ec11-4d4b-a527-b0b1da0789f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367775652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1367775652
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3242371698
Short name T189
Test name
Test status
Simulation time 6350562451 ps
CPU time 27.95 seconds
Started Jul 24 05:18:30 PM PDT 24
Finished Jul 24 05:18:58 PM PDT 24
Peak memory 211488 kb
Host smart-10564907-b171-460e-8ab2-c08bc01e81ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242371698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3242371698
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1671337981
Short name T306
Test name
Test status
Simulation time 186434796 ps
CPU time 5.95 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:18:38 PM PDT 24
Peak memory 211472 kb
Host smart-9265d38b-303a-406a-ae16-96d7c6bb4469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671337981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1671337981
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4474675
Short name T182
Test name
Test status
Simulation time 9266440667 ps
CPU time 23.06 seconds
Started Jul 24 05:18:46 PM PDT 24
Finished Jul 24 05:19:09 PM PDT 24
Peak memory 213924 kb
Host smart-dbfd123e-f81d-4ed9-81b6-a008544b248c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4474675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4474675
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2352270756
Short name T315
Test name
Test status
Simulation time 320143295 ps
CPU time 4.16 seconds
Started Jul 24 05:18:31 PM PDT 24
Finished Jul 24 05:18:35 PM PDT 24
Peak memory 211328 kb
Host smart-123cc52b-8bda-4cfd-8a09-05baf15fdcf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352270756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2352270756
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1189030414
Short name T108
Test name
Test status
Simulation time 58312047132 ps
CPU time 154.19 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:21:11 PM PDT 24
Peak memory 237540 kb
Host smart-1bd627e5-7f0b-40fc-8136-fba25bec5dcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189030414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1189030414
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3747896007
Short name T144
Test name
Test status
Simulation time 6065217494 ps
CPU time 19.84 seconds
Started Jul 24 05:18:23 PM PDT 24
Finished Jul 24 05:18:43 PM PDT 24
Peak memory 212584 kb
Host smart-c621dd8c-1557-4cf1-827e-f8c4fdc3484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747896007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3747896007
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3466234592
Short name T215
Test name
Test status
Simulation time 4682532736 ps
CPU time 12.44 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 05:18:47 PM PDT 24
Peak memory 211468 kb
Host smart-8c40bba8-e977-4476-a212-19f66ad5004f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466234592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3466234592
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.557613805
Short name T96
Test name
Test status
Simulation time 1637884598 ps
CPU time 20.21 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:18:54 PM PDT 24
Peak memory 212860 kb
Host smart-4ffcd4df-366a-4f66-a1cc-22f349ec04c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557613805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.557613805
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1332903722
Short name T280
Test name
Test status
Simulation time 8064272367 ps
CPU time 20.84 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:18:54 PM PDT 24
Peak memory 211292 kb
Host smart-70d12ee9-f2f5-44b0-8efa-94b1d13e480f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332903722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1332903722
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.51457594
Short name T47
Test name
Test status
Simulation time 37287091764 ps
CPU time 1444.84 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:42:42 PM PDT 24
Peak memory 235808 kb
Host smart-e390167d-963b-4cf8-8edd-11014cb534e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51457594 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.51457594
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.848203894
Short name T171
Test name
Test status
Simulation time 175281407 ps
CPU time 4.27 seconds
Started Jul 24 05:18:38 PM PDT 24
Finished Jul 24 05:18:43 PM PDT 24
Peak memory 211548 kb
Host smart-d551f596-fff1-440c-a800-e57c2d6f1526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848203894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.848203894
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1838234625
Short name T92
Test name
Test status
Simulation time 41332806882 ps
CPU time 140.29 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:21:04 PM PDT 24
Peak memory 228492 kb
Host smart-52acc9ab-a78b-4ff7-97db-c562b0a8f605
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838234625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1838234625
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3940530497
Short name T3
Test name
Test status
Simulation time 1104564092 ps
CPU time 9.4 seconds
Started Jul 24 05:18:35 PM PDT 24
Finished Jul 24 05:18:44 PM PDT 24
Peak memory 212048 kb
Host smart-98cdfd32-24c4-4ff7-b506-64947e234c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940530497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3940530497
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.587933225
Short name T301
Test name
Test status
Simulation time 6550726640 ps
CPU time 13.29 seconds
Started Jul 24 05:18:21 PM PDT 24
Finished Jul 24 05:18:34 PM PDT 24
Peak memory 211476 kb
Host smart-eb136cc5-9ee5-4f25-96ef-7c8cf8680c50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587933225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.587933225
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1692192313
Short name T369
Test name
Test status
Simulation time 5579652852 ps
CPU time 24.56 seconds
Started Jul 24 05:18:44 PM PDT 24
Finished Jul 24 05:19:08 PM PDT 24
Peak memory 213576 kb
Host smart-a11bc82c-a0c2-4585-a85b-2cd9f69ffc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692192313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1692192313
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1180580061
Short name T8
Test name
Test status
Simulation time 647935736 ps
CPU time 15.78 seconds
Started Jul 24 05:18:38 PM PDT 24
Finished Jul 24 05:18:54 PM PDT 24
Peak memory 214220 kb
Host smart-a7f497df-9ee1-47f0-8bd8-180e75f19003
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180580061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1180580061
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1807892387
Short name T354
Test name
Test status
Simulation time 64353593087 ps
CPU time 2410.79 seconds
Started Jul 24 05:18:46 PM PDT 24
Finished Jul 24 05:58:58 PM PDT 24
Peak memory 237280 kb
Host smart-bd8fb257-dbc7-4bf1-91e4-ef95b5f28f18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807892387 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1807892387
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2777884325
Short name T129
Test name
Test status
Simulation time 8482355114 ps
CPU time 15.07 seconds
Started Jul 24 05:18:28 PM PDT 24
Finished Jul 24 05:18:43 PM PDT 24
Peak memory 211388 kb
Host smart-8e1b39c3-e604-499e-8294-c373f202f71b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777884325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2777884325
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1407657982
Short name T181
Test name
Test status
Simulation time 3198553936 ps
CPU time 157.44 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 05:21:12 PM PDT 24
Peak memory 237908 kb
Host smart-2071dcfc-067d-4600-935b-ba94b4360b79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407657982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1407657982
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1492008504
Short name T328
Test name
Test status
Simulation time 175240828 ps
CPU time 9.24 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 05:18:27 PM PDT 24
Peak memory 212000 kb
Host smart-452193c7-9644-4be2-a80e-b0999008fe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492008504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1492008504
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2200331470
Short name T151
Test name
Test status
Simulation time 96607661 ps
CPU time 5.86 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 05:18:40 PM PDT 24
Peak memory 211468 kb
Host smart-ff479c3e-e041-4a5b-a2bb-ee2af60707d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200331470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2200331470
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1202848575
Short name T73
Test name
Test status
Simulation time 1541910516 ps
CPU time 23.5 seconds
Started Jul 24 05:18:31 PM PDT 24
Finished Jul 24 05:18:55 PM PDT 24
Peak memory 213456 kb
Host smart-40e128dc-3880-4708-a50a-c572d218d6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202848575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1202848575
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.947739740
Short name T137
Test name
Test status
Simulation time 79079805733 ps
CPU time 83.07 seconds
Started Jul 24 05:18:20 PM PDT 24
Finished Jul 24 05:19:43 PM PDT 24
Peak memory 217760 kb
Host smart-f485c04e-8554-458d-87c7-3770fb10d71b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947739740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.947739740
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.14650470
Short name T295
Test name
Test status
Simulation time 372580720 ps
CPU time 6.88 seconds
Started Jul 24 05:18:55 PM PDT 24
Finished Jul 24 05:19:02 PM PDT 24
Peak memory 211344 kb
Host smart-f1288eec-ff4d-4fb0-be39-2b402c272d4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14650470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.14650470
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2513127638
Short name T37
Test name
Test status
Simulation time 28375810499 ps
CPU time 323.1 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:24:07 PM PDT 24
Peak memory 238848 kb
Host smart-890d4a7a-64a7-4e83-88ad-8ec8bba6a186
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513127638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2513127638
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2566423496
Short name T208
Test name
Test status
Simulation time 11188924402 ps
CPU time 25.99 seconds
Started Jul 24 05:18:46 PM PDT 24
Finished Jul 24 05:19:12 PM PDT 24
Peak memory 212280 kb
Host smart-a38d0f0f-6465-4857-81f8-2a7f607558ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566423496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2566423496
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1533305732
Short name T35
Test name
Test status
Simulation time 98786648 ps
CPU time 5.48 seconds
Started Jul 24 05:18:27 PM PDT 24
Finished Jul 24 05:18:32 PM PDT 24
Peak memory 211372 kb
Host smart-c4c21f44-221d-4dc6-891d-d7ec74c15777
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1533305732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1533305732
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2297132583
Short name T133
Test name
Test status
Simulation time 2866358206 ps
CPU time 25.38 seconds
Started Jul 24 05:18:29 PM PDT 24
Finished Jul 24 05:18:55 PM PDT 24
Peak memory 213632 kb
Host smart-4f05e6bc-f085-4111-899e-e783c4e18de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297132583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2297132583
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2117818755
Short name T75
Test name
Test status
Simulation time 1191586614 ps
CPU time 14.51 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:18:47 PM PDT 24
Peak memory 211416 kb
Host smart-0b24f041-7478-42bd-b1ba-1e04aad2fe96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117818755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2117818755
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2526266582
Short name T94
Test name
Test status
Simulation time 5909232418 ps
CPU time 12.77 seconds
Started Jul 24 05:18:12 PM PDT 24
Finished Jul 24 05:18:25 PM PDT 24
Peak memory 211332 kb
Host smart-fd940a6f-6513-41a4-8759-b9dae5b293e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526266582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2526266582
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3685359849
Short name T245
Test name
Test status
Simulation time 24336408313 ps
CPU time 91.03 seconds
Started Jul 24 05:18:10 PM PDT 24
Finished Jul 24 05:19:41 PM PDT 24
Peak memory 224596 kb
Host smart-4972f801-6629-40c4-a9b0-4310c2cb2613
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685359849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3685359849
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.389851374
Short name T159
Test name
Test status
Simulation time 722603033 ps
CPU time 9.63 seconds
Started Jul 24 05:18:01 PM PDT 24
Finished Jul 24 05:18:10 PM PDT 24
Peak memory 212220 kb
Host smart-896115e4-a0b6-43e5-89eb-1b2774cc134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389851374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.389851374
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3165644156
Short name T331
Test name
Test status
Simulation time 1786872732 ps
CPU time 15.35 seconds
Started Jul 24 05:18:03 PM PDT 24
Finished Jul 24 05:18:18 PM PDT 24
Peak memory 211324 kb
Host smart-089b3aa1-539f-4f94-85c0-d4e508833c55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165644156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3165644156
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1544169208
Short name T22
Test name
Test status
Simulation time 1276284176 ps
CPU time 106.33 seconds
Started Jul 24 05:18:06 PM PDT 24
Finished Jul 24 05:19:53 PM PDT 24
Peak memory 239380 kb
Host smart-5c6e451b-609f-4caa-8644-b34d395092f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544169208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1544169208
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.147472997
Short name T303
Test name
Test status
Simulation time 362288061 ps
CPU time 10.05 seconds
Started Jul 24 05:17:58 PM PDT 24
Finished Jul 24 05:18:08 PM PDT 24
Peak memory 213608 kb
Host smart-39250751-a4c0-4313-b530-655775620c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147472997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.147472997
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1149592817
Short name T235
Test name
Test status
Simulation time 288084635 ps
CPU time 15.88 seconds
Started Jul 24 05:17:56 PM PDT 24
Finished Jul 24 05:18:12 PM PDT 24
Peak memory 215144 kb
Host smart-6d16abfa-55f9-48bb-bb8d-d48d2cfcaec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149592817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1149592817
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2894363829
Short name T10
Test name
Test status
Simulation time 4863481370 ps
CPU time 11.67 seconds
Started Jul 24 05:18:39 PM PDT 24
Finished Jul 24 05:18:51 PM PDT 24
Peak memory 211332 kb
Host smart-be723e03-10ad-4c2c-ad64-1ff52282ed21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894363829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2894363829
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1971391545
Short name T309
Test name
Test status
Simulation time 79583104769 ps
CPU time 182.87 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:21:40 PM PDT 24
Peak memory 236808 kb
Host smart-8d9ca8b3-758b-499a-92a4-c630da144fc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971391545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1971391545
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1226874259
Short name T134
Test name
Test status
Simulation time 214911580 ps
CPU time 9.37 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:18:47 PM PDT 24
Peak memory 211836 kb
Host smart-5092406e-f75b-4476-9917-bcd096d32c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226874259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1226874259
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4021343054
Short name T252
Test name
Test status
Simulation time 1212351867 ps
CPU time 12.52 seconds
Started Jul 24 05:18:47 PM PDT 24
Finished Jul 24 05:19:00 PM PDT 24
Peak memory 211312 kb
Host smart-8ce3eef0-4682-48d2-a64f-70e98839ef5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021343054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4021343054
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3233438182
Short name T243
Test name
Test status
Simulation time 2068501705 ps
CPU time 21.27 seconds
Started Jul 24 05:18:25 PM PDT 24
Finished Jul 24 05:18:46 PM PDT 24
Peak memory 213356 kb
Host smart-00034810-fe44-48ea-8bb3-2bac62fcfb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233438182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3233438182
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2495389935
Short name T312
Test name
Test status
Simulation time 2514595486 ps
CPU time 31.47 seconds
Started Jul 24 05:18:21 PM PDT 24
Finished Jul 24 05:18:52 PM PDT 24
Peak memory 216344 kb
Host smart-aef20930-37d2-4d2e-a8fa-2841b8c7d73a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495389935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2495389935
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3791758445
Short name T163
Test name
Test status
Simulation time 108937321 ps
CPU time 3.94 seconds
Started Jul 24 05:18:52 PM PDT 24
Finished Jul 24 05:18:56 PM PDT 24
Peak memory 211196 kb
Host smart-2cbc0b8a-dd05-4ef2-a5aa-67649cbfe515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791758445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3791758445
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1868648915
Short name T168
Test name
Test status
Simulation time 4617631424 ps
CPU time 113.71 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:20:31 PM PDT 24
Peak memory 237896 kb
Host smart-4597f579-e62f-4dd8-bc99-a17d184c3625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868648915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1868648915
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1415415680
Short name T140
Test name
Test status
Simulation time 24611907413 ps
CPU time 26.26 seconds
Started Jul 24 05:18:30 PM PDT 24
Finished Jul 24 05:18:57 PM PDT 24
Peak memory 212596 kb
Host smart-dfaaec70-61ad-4f96-884c-3bccee5eebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415415680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1415415680
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.35862567
Short name T157
Test name
Test status
Simulation time 3399784589 ps
CPU time 15.05 seconds
Started Jul 24 05:18:39 PM PDT 24
Finished Jul 24 05:18:54 PM PDT 24
Peak memory 211052 kb
Host smart-aa43e8f3-ea7f-4c3b-a2f2-b1d11f2818ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35862567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.35862567
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1520623628
Short name T281
Test name
Test status
Simulation time 5438471142 ps
CPU time 28.22 seconds
Started Jul 24 05:18:47 PM PDT 24
Finished Jul 24 05:19:15 PM PDT 24
Peak memory 214092 kb
Host smart-85b5d922-9a65-486b-8d85-ff9b8a389a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520623628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1520623628
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.582062147
Short name T359
Test name
Test status
Simulation time 7338494563 ps
CPU time 22.02 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:18:59 PM PDT 24
Peak memory 215104 kb
Host smart-a223505d-dc85-49a7-bdd0-f61c3dd23ca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582062147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.582062147
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4139584455
Short name T329
Test name
Test status
Simulation time 171479174 ps
CPU time 4.35 seconds
Started Jul 24 05:18:36 PM PDT 24
Finished Jul 24 05:18:41 PM PDT 24
Peak memory 211304 kb
Host smart-9fa46fbd-61e4-40c4-871d-d82b1f3cf006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139584455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4139584455
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3752644648
Short name T183
Test name
Test status
Simulation time 244106960806 ps
CPU time 144.01 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:21:07 PM PDT 24
Peak memory 240588 kb
Host smart-967cd1cf-f604-40c8-be80-42d0cc74816c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752644648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3752644648
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2397865681
Short name T2
Test name
Test status
Simulation time 31775658024 ps
CPU time 34.79 seconds
Started Jul 24 05:18:38 PM PDT 24
Finished Jul 24 05:19:13 PM PDT 24
Peak memory 212188 kb
Host smart-3323ccdf-ef65-4479-9083-bc871df3169c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397865681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2397865681
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1170703
Short name T228
Test name
Test status
Simulation time 1573166882 ps
CPU time 7.88 seconds
Started Jul 24 05:18:40 PM PDT 24
Finished Jul 24 05:18:48 PM PDT 24
Peak memory 211396 kb
Host smart-aa06ea49-9552-4aa5-ad77-c1c3212214e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1170703
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.669124979
Short name T16
Test name
Test status
Simulation time 1503386791 ps
CPU time 15.74 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:18:50 PM PDT 24
Peak memory 212076 kb
Host smart-952d2a36-d096-4b06-a194-002b98c9faf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669124979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.669124979
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3465053924
Short name T174
Test name
Test status
Simulation time 5674003715 ps
CPU time 17.34 seconds
Started Jul 24 05:18:29 PM PDT 24
Finished Jul 24 05:18:46 PM PDT 24
Peak memory 212776 kb
Host smart-ff9b8c5b-b613-4b7c-bd13-9e6b9bd3280b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465053924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3465053924
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1106391580
Short name T206
Test name
Test status
Simulation time 363327398 ps
CPU time 4.3 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:18:48 PM PDT 24
Peak memory 211212 kb
Host smart-f1895275-9da7-4a34-89df-da5addbfe73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106391580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1106391580
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4184698207
Short name T186
Test name
Test status
Simulation time 106576872451 ps
CPU time 287.92 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:23:31 PM PDT 24
Peak memory 224612 kb
Host smart-0d641e72-18c6-43f6-b9ff-a2602dc42059
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184698207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4184698207
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4216472291
Short name T161
Test name
Test status
Simulation time 32821453704 ps
CPU time 33.95 seconds
Started Jul 24 05:18:36 PM PDT 24
Finished Jul 24 05:19:10 PM PDT 24
Peak memory 212060 kb
Host smart-8743e220-3e58-4916-9e21-0cb68a9c157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216472291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4216472291
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.604251903
Short name T270
Test name
Test status
Simulation time 16054217563 ps
CPU time 15.06 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:18:47 PM PDT 24
Peak memory 211412 kb
Host smart-ddae54f2-5428-41a8-bf7b-71f09b76c476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604251903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.604251903
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1436954398
Short name T217
Test name
Test status
Simulation time 3791597589 ps
CPU time 21.77 seconds
Started Jul 24 05:18:39 PM PDT 24
Finished Jul 24 05:19:02 PM PDT 24
Peak memory 212944 kb
Host smart-521e2bfb-3f95-4fad-8980-8bfa605cfa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436954398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1436954398
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4043305188
Short name T207
Test name
Test status
Simulation time 2803015877 ps
CPU time 16.92 seconds
Started Jul 24 05:18:52 PM PDT 24
Finished Jul 24 05:19:09 PM PDT 24
Peak memory 211172 kb
Host smart-b8df58fd-d9c4-469c-bbfc-f87885e52038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043305188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4043305188
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3897117884
Short name T341
Test name
Test status
Simulation time 62192525054 ps
CPU time 1198.47 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:38:32 PM PDT 24
Peak memory 235344 kb
Host smart-2342cd46-b0ed-45df-9b07-fd0401a667d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897117884 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3897117884
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2009036613
Short name T346
Test name
Test status
Simulation time 2961218235 ps
CPU time 12.78 seconds
Started Jul 24 05:18:24 PM PDT 24
Finished Jul 24 05:18:37 PM PDT 24
Peak memory 211320 kb
Host smart-a722a204-4145-4eb7-86b9-7cca4b949fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009036613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2009036613
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3826317078
Short name T338
Test name
Test status
Simulation time 18980152158 ps
CPU time 121.22 seconds
Started Jul 24 05:18:49 PM PDT 24
Finished Jul 24 05:20:51 PM PDT 24
Peak memory 237880 kb
Host smart-ba9a089a-d87b-4835-ab63-7918def23b5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826317078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3826317078
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3952594643
Short name T299
Test name
Test status
Simulation time 3589041016 ps
CPU time 30.17 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:19:03 PM PDT 24
Peak memory 211976 kb
Host smart-6a69e321-b1d9-4b7d-96e7-e457a70c44f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952594643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3952594643
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2507588081
Short name T138
Test name
Test status
Simulation time 7427040533 ps
CPU time 13.88 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:18:46 PM PDT 24
Peak memory 211452 kb
Host smart-8ae94725-029b-46f5-8da7-8ab9cb7e0374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507588081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2507588081
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.735612074
Short name T225
Test name
Test status
Simulation time 187448339 ps
CPU time 10.07 seconds
Started Jul 24 05:18:38 PM PDT 24
Finished Jul 24 05:18:48 PM PDT 24
Peak memory 213068 kb
Host smart-21bce476-5457-45ce-a22d-13b992aca92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735612074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.735612074
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4101616469
Short name T154
Test name
Test status
Simulation time 2827815896 ps
CPU time 43.62 seconds
Started Jul 24 05:18:38 PM PDT 24
Finished Jul 24 05:19:22 PM PDT 24
Peak memory 215972 kb
Host smart-114b080c-6b83-4f42-ae05-7cf38e5df5ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101616469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4101616469
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1134028876
Short name T172
Test name
Test status
Simulation time 3914340176 ps
CPU time 15.29 seconds
Started Jul 24 05:18:29 PM PDT 24
Finished Jul 24 05:18:45 PM PDT 24
Peak memory 211396 kb
Host smart-936915da-af2e-47af-a8a1-08fc75bade53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134028876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1134028876
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1759668301
Short name T240
Test name
Test status
Simulation time 65645162610 ps
CPU time 651.75 seconds
Started Jul 24 05:18:46 PM PDT 24
Finished Jul 24 05:29:38 PM PDT 24
Peak memory 228636 kb
Host smart-fc238957-5503-40a6-8290-3b735f7750c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759668301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1759668301
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1292510766
Short name T257
Test name
Test status
Simulation time 1287367554 ps
CPU time 17.31 seconds
Started Jul 24 05:18:39 PM PDT 24
Finished Jul 24 05:18:57 PM PDT 24
Peak memory 211372 kb
Host smart-90574b83-7f7b-48be-a0ed-d07095fb626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292510766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1292510766
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1580008381
Short name T367
Test name
Test status
Simulation time 2518005474 ps
CPU time 12.13 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:18:46 PM PDT 24
Peak memory 211496 kb
Host smart-1df911e1-b731-49d8-a143-e1853bcc502c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580008381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1580008381
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4095191176
Short name T17
Test name
Test status
Simulation time 190323153 ps
CPU time 10.31 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:18:48 PM PDT 24
Peak memory 212344 kb
Host smart-aec977c5-a99a-4553-b7eb-5bd16f9020c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095191176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4095191176
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3160554790
Short name T334
Test name
Test status
Simulation time 287337578 ps
CPU time 14.85 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:18:47 PM PDT 24
Peak memory 215024 kb
Host smart-e7c2add4-3479-4251-929e-67c2ddfe55e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160554790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3160554790
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2024362102
Short name T246
Test name
Test status
Simulation time 1689364030 ps
CPU time 13.73 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:18:57 PM PDT 24
Peak memory 211312 kb
Host smart-6e6f3b25-cd74-434a-9318-5ac7dbeed602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024362102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2024362102
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2185347024
Short name T269
Test name
Test status
Simulation time 61613380345 ps
CPU time 154.43 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 05:21:08 PM PDT 24
Peak memory 212608 kb
Host smart-cc93046b-a48a-4842-9914-36d467e12aa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185347024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2185347024
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2179098001
Short name T290
Test name
Test status
Simulation time 507344050 ps
CPU time 13.24 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:18:45 PM PDT 24
Peak memory 211892 kb
Host smart-efd8d119-a48f-420b-8f59-3e820157b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179098001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2179098001
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1364960526
Short name T6
Test name
Test status
Simulation time 5966217061 ps
CPU time 13.75 seconds
Started Jul 24 05:18:24 PM PDT 24
Finished Jul 24 05:18:38 PM PDT 24
Peak memory 211456 kb
Host smart-ff3557b7-f4ea-4fca-b88c-90025da7f56d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364960526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1364960526
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.931299907
Short name T195
Test name
Test status
Simulation time 3297132333 ps
CPU time 21.13 seconds
Started Jul 24 05:18:41 PM PDT 24
Finished Jul 24 05:19:03 PM PDT 24
Peak memory 213604 kb
Host smart-6c06e30c-9828-436a-a4b4-5bc8b932a472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931299907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.931299907
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3914605163
Short name T349
Test name
Test status
Simulation time 1966684598 ps
CPU time 34.34 seconds
Started Jul 24 05:18:27 PM PDT 24
Finished Jul 24 05:19:02 PM PDT 24
Peak memory 216064 kb
Host smart-e5c1f69b-a0ee-42c8-9358-9b4046fda505
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914605163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3914605163
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4176370546
Short name T253
Test name
Test status
Simulation time 1126673668 ps
CPU time 11.12 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:18:49 PM PDT 24
Peak memory 211180 kb
Host smart-c0971ca7-b4d7-41c3-bb7a-436cb330cfbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176370546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4176370546
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2587682154
Short name T201
Test name
Test status
Simulation time 40693914444 ps
CPU time 359.12 seconds
Started Jul 24 05:18:45 PM PDT 24
Finished Jul 24 05:24:44 PM PDT 24
Peak memory 213244 kb
Host smart-0a1d2adf-d022-4575-908d-a44c1c5eae0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587682154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2587682154
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2393615064
Short name T222
Test name
Test status
Simulation time 1284259527 ps
CPU time 17.04 seconds
Started Jul 24 05:18:35 PM PDT 24
Finished Jul 24 05:18:52 PM PDT 24
Peak memory 212028 kb
Host smart-9215d42e-7c94-47e2-a584-db7311d93ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393615064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2393615064
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2744537303
Short name T190
Test name
Test status
Simulation time 2472786533 ps
CPU time 12.77 seconds
Started Jul 24 05:18:38 PM PDT 24
Finished Jul 24 05:18:51 PM PDT 24
Peak memory 211408 kb
Host smart-d7e7c110-fda7-45c7-b759-089c6f52b2a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744537303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2744537303
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.465804176
Short name T248
Test name
Test status
Simulation time 2847694416 ps
CPU time 27.75 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:19:05 PM PDT 24
Peak memory 213452 kb
Host smart-bd8fce50-8aaf-46e6-990c-6780058432a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465804176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.465804176
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4189657709
Short name T358
Test name
Test status
Simulation time 2499256144 ps
CPU time 34.13 seconds
Started Jul 24 05:18:30 PM PDT 24
Finished Jul 24 05:19:04 PM PDT 24
Peak memory 216748 kb
Host smart-6a81d5ab-70c5-41c5-b4ca-ec02722f72ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189657709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4189657709
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2122613593
Short name T51
Test name
Test status
Simulation time 116036928994 ps
CPU time 1907.31 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:50:31 PM PDT 24
Peak memory 235844 kb
Host smart-c02890c1-a683-4ecd-95b9-539acbe39f13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122613593 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2122613593
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1463775138
Short name T180
Test name
Test status
Simulation time 308226464 ps
CPU time 4.16 seconds
Started Jul 24 05:18:40 PM PDT 24
Finished Jul 24 05:18:44 PM PDT 24
Peak memory 211316 kb
Host smart-9a43b5fb-586c-4fab-9a80-32269444177e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463775138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1463775138
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.970839663
Short name T39
Test name
Test status
Simulation time 76979172878 ps
CPU time 119.97 seconds
Started Jul 24 05:18:23 PM PDT 24
Finished Jul 24 05:20:23 PM PDT 24
Peak memory 238828 kb
Host smart-c5af0e3a-7269-42c5-93af-b769096c402c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970839663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.970839663
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.337726339
Short name T45
Test name
Test status
Simulation time 2621001844 ps
CPU time 26.07 seconds
Started Jul 24 05:18:56 PM PDT 24
Finished Jul 24 05:19:22 PM PDT 24
Peak memory 211904 kb
Host smart-dfaa3a3c-9276-4b7b-8b34-27f6d7871188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337726339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.337726339
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3800332198
Short name T204
Test name
Test status
Simulation time 6175985211 ps
CPU time 13.65 seconds
Started Jul 24 05:18:41 PM PDT 24
Finished Jul 24 05:18:55 PM PDT 24
Peak memory 211420 kb
Host smart-aac69bb5-8ebe-4ce4-943d-aad7faa285b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800332198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3800332198
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3684157016
Short name T231
Test name
Test status
Simulation time 527640430 ps
CPU time 13.66 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:18:46 PM PDT 24
Peak memory 212444 kb
Host smart-37ea8dd4-fe85-4958-9c6c-2aef3ebb1035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684157016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3684157016
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1085680974
Short name T284
Test name
Test status
Simulation time 4688233768 ps
CPU time 51.8 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:19:24 PM PDT 24
Peak memory 215824 kb
Host smart-11e01eb7-a48a-469d-868d-bea734a4b603
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085680974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1085680974
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.475960697
Short name T48
Test name
Test status
Simulation time 77380909949 ps
CPU time 4483.46 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 06:33:18 PM PDT 24
Peak memory 235772 kb
Host smart-176395f7-b1e0-4e9d-a978-b101e1434373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475960697 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.475960697
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.879069572
Short name T28
Test name
Test status
Simulation time 167798011 ps
CPU time 4.26 seconds
Started Jul 24 05:18:51 PM PDT 24
Finished Jul 24 05:18:55 PM PDT 24
Peak memory 211272 kb
Host smart-29e480a2-e7e4-44d2-872f-288d382dc867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879069572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.879069572
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2821616239
Short name T212
Test name
Test status
Simulation time 26380936780 ps
CPU time 228.85 seconds
Started Jul 24 05:18:45 PM PDT 24
Finished Jul 24 05:22:35 PM PDT 24
Peak memory 213380 kb
Host smart-3feb79a7-9b92-4b95-be6d-0c1109851cfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821616239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2821616239
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4142475179
Short name T355
Test name
Test status
Simulation time 32718738207 ps
CPU time 32.57 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:19:09 PM PDT 24
Peak memory 212260 kb
Host smart-ffa2d804-bf0b-4717-996a-0b9c45bdf4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142475179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4142475179
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.949580179
Short name T277
Test name
Test status
Simulation time 7859437871 ps
CPU time 36.85 seconds
Started Jul 24 05:18:35 PM PDT 24
Finished Jul 24 05:19:12 PM PDT 24
Peak memory 213920 kb
Host smart-ab03ddf1-247f-47f3-87c7-8005554d40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949580179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.949580179
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.673931817
Short name T227
Test name
Test status
Simulation time 7071612460 ps
CPU time 21.38 seconds
Started Jul 24 05:18:36 PM PDT 24
Finished Jul 24 05:18:58 PM PDT 24
Peak memory 212404 kb
Host smart-6806d33c-3566-4837-b514-35db2a859def
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673931817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.673931817
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.373556719
Short name T162
Test name
Test status
Simulation time 6205840719 ps
CPU time 12.92 seconds
Started Jul 24 05:18:17 PM PDT 24
Finished Jul 24 05:18:30 PM PDT 24
Peak memory 211292 kb
Host smart-c18ce746-6aa7-4c97-b13f-203da9c95516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373556719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.373556719
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.493632927
Short name T340
Test name
Test status
Simulation time 3947328022 ps
CPU time 146.31 seconds
Started Jul 24 05:18:06 PM PDT 24
Finished Jul 24 05:20:32 PM PDT 24
Peak memory 212320 kb
Host smart-220f1310-73ec-4770-9021-d29da5374374
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493632927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.493632927
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4219247441
Short name T135
Test name
Test status
Simulation time 341039501 ps
CPU time 9.64 seconds
Started Jul 24 05:18:03 PM PDT 24
Finished Jul 24 05:18:13 PM PDT 24
Peak memory 212040 kb
Host smart-907c22ad-76f3-42a4-8699-e2112720e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219247441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4219247441
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3341762748
Short name T98
Test name
Test status
Simulation time 8835912037 ps
CPU time 15.62 seconds
Started Jul 24 05:18:06 PM PDT 24
Finished Jul 24 05:18:22 PM PDT 24
Peak memory 211480 kb
Host smart-b28bd68f-97b4-4e25-ac5e-cd962a0fa9fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3341762748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3341762748
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3023014995
Short name T124
Test name
Test status
Simulation time 3081799724 ps
CPU time 26.32 seconds
Started Jul 24 05:18:13 PM PDT 24
Finished Jul 24 05:18:40 PM PDT 24
Peak memory 213544 kb
Host smart-2137873e-e1d4-426d-829c-c5bfa27f34ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023014995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3023014995
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.314028156
Short name T178
Test name
Test status
Simulation time 4169785737 ps
CPU time 43.5 seconds
Started Jul 24 05:18:07 PM PDT 24
Finished Jul 24 05:18:51 PM PDT 24
Peak memory 215120 kb
Host smart-2c118006-feef-4694-85cd-c368b9b3aa5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314028156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.314028156
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.884300002
Short name T214
Test name
Test status
Simulation time 1156299967 ps
CPU time 11.06 seconds
Started Jul 24 05:18:29 PM PDT 24
Finished Jul 24 05:18:40 PM PDT 24
Peak memory 211320 kb
Host smart-3a1c9268-88df-4598-a83d-70a3a4294f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884300002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.884300002
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.595537972
Short name T5
Test name
Test status
Simulation time 38619967379 ps
CPU time 147.67 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 05:21:02 PM PDT 24
Peak memory 228604 kb
Host smart-da0418b5-f4b0-45a0-a57c-9d93552cd490
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595537972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.595537972
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.817703666
Short name T241
Test name
Test status
Simulation time 7870508096 ps
CPU time 21.26 seconds
Started Jul 24 05:18:31 PM PDT 24
Finished Jul 24 05:18:52 PM PDT 24
Peak memory 212704 kb
Host smart-24cd68e5-1f6f-4df4-96e2-546f98c49102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817703666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.817703666
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1131526347
Short name T132
Test name
Test status
Simulation time 2816059810 ps
CPU time 15.48 seconds
Started Jul 24 05:18:44 PM PDT 24
Finished Jul 24 05:19:00 PM PDT 24
Peak memory 211376 kb
Host smart-f8196407-bc81-45d4-8f61-08b797218dbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131526347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1131526347
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2846589393
Short name T256
Test name
Test status
Simulation time 778588868 ps
CPU time 9.79 seconds
Started Jul 24 05:18:47 PM PDT 24
Finished Jul 24 05:18:57 PM PDT 24
Peak memory 213924 kb
Host smart-27a0fcae-ff90-4d1e-9d3f-cce6477fb579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846589393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2846589393
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2704373905
Short name T272
Test name
Test status
Simulation time 2599066805 ps
CPU time 22.14 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:18:55 PM PDT 24
Peak memory 216444 kb
Host smart-ec087cf5-8e3b-4f34-8629-232c7cf743e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704373905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2704373905
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1883484346
Short name T337
Test name
Test status
Simulation time 55517154268 ps
CPU time 2270.11 seconds
Started Jul 24 05:18:36 PM PDT 24
Finished Jul 24 05:56:26 PM PDT 24
Peak memory 244112 kb
Host smart-80e10ab3-a504-456e-9f8a-5c61b6a6aad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883484346 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1883484346
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3598043053
Short name T287
Test name
Test status
Simulation time 6275325753 ps
CPU time 16.34 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:18:48 PM PDT 24
Peak memory 211352 kb
Host smart-b70d6b8d-a198-4d72-b388-6804592e0d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598043053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3598043053
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1647007092
Short name T148
Test name
Test status
Simulation time 48055364751 ps
CPU time 293.95 seconds
Started Jul 24 05:18:50 PM PDT 24
Finished Jul 24 05:23:44 PM PDT 24
Peak memory 228508 kb
Host smart-40762ec3-386d-44b9-8fbd-e73f38f09dde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647007092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1647007092
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2350631203
Short name T221
Test name
Test status
Simulation time 6773492729 ps
CPU time 29.53 seconds
Started Jul 24 05:18:36 PM PDT 24
Finished Jul 24 05:19:06 PM PDT 24
Peak memory 212428 kb
Host smart-347c35ef-e8b3-478c-8b26-6705fd7f7a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350631203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2350631203
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.551998360
Short name T296
Test name
Test status
Simulation time 100050011 ps
CPU time 5.59 seconds
Started Jul 24 05:18:40 PM PDT 24
Finished Jul 24 05:18:46 PM PDT 24
Peak memory 211256 kb
Host smart-64ae7916-2819-4bbf-9c2c-d38e4ba9eccc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551998360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.551998360
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1899173439
Short name T316
Test name
Test status
Simulation time 760923575 ps
CPU time 9.69 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:18:42 PM PDT 24
Peak memory 213080 kb
Host smart-37fda8d5-1452-49b8-ac19-0c4089d57a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899173439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1899173439
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4199234612
Short name T351
Test name
Test status
Simulation time 7085533836 ps
CPU time 66.02 seconds
Started Jul 24 05:18:40 PM PDT 24
Finished Jul 24 05:19:47 PM PDT 24
Peak memory 216184 kb
Host smart-85724c5e-7d7e-4993-917d-38f1795d126c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199234612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4199234612
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1206355723
Short name T335
Test name
Test status
Simulation time 35849198467 ps
CPU time 5597.04 seconds
Started Jul 24 05:18:46 PM PDT 24
Finished Jul 24 06:52:04 PM PDT 24
Peak memory 235840 kb
Host smart-1cea0ce1-7eb9-4d5a-a106-8b9d349506f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206355723 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1206355723
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2609496350
Short name T238
Test name
Test status
Simulation time 8625146620 ps
CPU time 17.02 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:18:49 PM PDT 24
Peak memory 211388 kb
Host smart-57864d02-a224-46b5-ad19-73d4af3b29fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609496350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2609496350
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.203925689
Short name T43
Test name
Test status
Simulation time 109882532131 ps
CPU time 263.26 seconds
Started Jul 24 05:18:41 PM PDT 24
Finished Jul 24 05:23:04 PM PDT 24
Peak memory 224968 kb
Host smart-e5e23944-2c2f-40f0-b4e4-a6e9c0bfb7bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203925689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.203925689
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1563298526
Short name T297
Test name
Test status
Simulation time 2381790559 ps
CPU time 23.16 seconds
Started Jul 24 05:18:41 PM PDT 24
Finished Jul 24 05:19:04 PM PDT 24
Peak memory 212252 kb
Host smart-eb14a6f3-6cf8-469e-9c24-48dd75d53e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563298526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1563298526
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.772062426
Short name T31
Test name
Test status
Simulation time 239292899 ps
CPU time 5.75 seconds
Started Jul 24 05:18:40 PM PDT 24
Finished Jul 24 05:18:46 PM PDT 24
Peak memory 211408 kb
Host smart-328081eb-7aaa-4bb7-b7e2-ae7ef0fd76b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772062426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.772062426
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2931629556
Short name T170
Test name
Test status
Simulation time 952272723 ps
CPU time 15.66 seconds
Started Jul 24 05:18:47 PM PDT 24
Finished Jul 24 05:19:03 PM PDT 24
Peak memory 213128 kb
Host smart-2b9753b9-fb8f-4703-ad24-20d7a3a5d636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931629556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2931629556
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4266864395
Short name T229
Test name
Test status
Simulation time 30271527515 ps
CPU time 50.52 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:19:28 PM PDT 24
Peak memory 219364 kb
Host smart-2a107342-145d-4d42-be4d-0d1d10fb315d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266864395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4266864395
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3955091116
Short name T19
Test name
Test status
Simulation time 2125256410 ps
CPU time 15.54 seconds
Started Jul 24 05:18:44 PM PDT 24
Finished Jul 24 05:19:00 PM PDT 24
Peak memory 211288 kb
Host smart-2cc606a0-d05c-4922-8087-dc989a4d7aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955091116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3955091116
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.519209729
Short name T210
Test name
Test status
Simulation time 9795511574 ps
CPU time 147.73 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:21:01 PM PDT 24
Peak memory 225716 kb
Host smart-d92fbb51-ac59-45b5-90e8-3bdf0e2a5d93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519209729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.519209729
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1806503420
Short name T242
Test name
Test status
Simulation time 16426896747 ps
CPU time 25.36 seconds
Started Jul 24 05:18:41 PM PDT 24
Finished Jul 24 05:19:11 PM PDT 24
Peak memory 212428 kb
Host smart-bb5675c7-9149-417a-bc98-d7067fa3987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806503420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1806503420
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.938794235
Short name T361
Test name
Test status
Simulation time 7556613303 ps
CPU time 13.7 seconds
Started Jul 24 05:18:38 PM PDT 24
Finished Jul 24 05:18:52 PM PDT 24
Peak memory 211456 kb
Host smart-03d1a401-78ab-4876-9880-a036f4735993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938794235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.938794235
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2004358006
Short name T53
Test name
Test status
Simulation time 2230205054 ps
CPU time 22.38 seconds
Started Jul 24 05:18:32 PM PDT 24
Finished Jul 24 05:18:55 PM PDT 24
Peak memory 213648 kb
Host smart-8980c50f-2347-41d1-b43d-8cc2df3229bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004358006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2004358006
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4171342109
Short name T365
Test name
Test status
Simulation time 3727819329 ps
CPU time 44.3 seconds
Started Jul 24 05:18:35 PM PDT 24
Finished Jul 24 05:19:19 PM PDT 24
Peak memory 215812 kb
Host smart-16ad3fc4-5d5d-4f56-ae29-ec21f10f8200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171342109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4171342109
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.163026076
Short name T60
Test name
Test status
Simulation time 1643286634 ps
CPU time 13.64 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 05:18:48 PM PDT 24
Peak memory 211312 kb
Host smart-6e0b3e79-26e7-4c32-8237-b1e693973567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163026076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.163026076
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3998603892
Short name T232
Test name
Test status
Simulation time 2529677129 ps
CPU time 23.54 seconds
Started Jul 24 05:18:34 PM PDT 24
Finished Jul 24 05:18:58 PM PDT 24
Peak memory 211948 kb
Host smart-96d2c411-3095-4fcf-b178-6e66b8c73210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998603892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3998603892
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2362255034
Short name T234
Test name
Test status
Simulation time 134631741 ps
CPU time 5.82 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:18:40 PM PDT 24
Peak memory 211412 kb
Host smart-744cc50e-96f1-4ebd-b76f-144a4d4801e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362255034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2362255034
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3555753622
Short name T244
Test name
Test status
Simulation time 2661472197 ps
CPU time 13 seconds
Started Jul 24 05:18:35 PM PDT 24
Finished Jul 24 05:18:48 PM PDT 24
Peak memory 213864 kb
Host smart-3702747d-6841-47eb-97cc-636d08803acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555753622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3555753622
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.910416956
Short name T344
Test name
Test status
Simulation time 4923548938 ps
CPU time 40.83 seconds
Started Jul 24 05:18:44 PM PDT 24
Finished Jul 24 05:19:25 PM PDT 24
Peak memory 213696 kb
Host smart-a5b7bb63-a887-4589-9ac6-3cc9716b1d49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910416956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.910416956
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3238643876
Short name T356
Test name
Test status
Simulation time 172487722 ps
CPU time 5.57 seconds
Started Jul 24 05:18:40 PM PDT 24
Finished Jul 24 05:18:45 PM PDT 24
Peak memory 211300 kb
Host smart-b8e9f9d9-dfa0-4630-abb3-5a43690b5156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238643876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3238643876
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1551427291
Short name T347
Test name
Test status
Simulation time 51249468279 ps
CPU time 256.97 seconds
Started Jul 24 05:18:40 PM PDT 24
Finished Jul 24 05:22:57 PM PDT 24
Peak memory 237864 kb
Host smart-9c536bc8-2ac7-4a6a-9442-8cf67ea075f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551427291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1551427291
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3996547984
Short name T279
Test name
Test status
Simulation time 4398096290 ps
CPU time 28.08 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:19:06 PM PDT 24
Peak memory 212732 kb
Host smart-d199ac5d-b273-4289-9987-88219d30afb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996547984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3996547984
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1892329308
Short name T327
Test name
Test status
Simulation time 187185824 ps
CPU time 5.49 seconds
Started Jul 24 05:18:38 PM PDT 24
Finished Jul 24 05:18:43 PM PDT 24
Peak memory 211396 kb
Host smart-23024b39-1809-4e54-80cf-47b57e8c9469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892329308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1892329308
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3307248951
Short name T155
Test name
Test status
Simulation time 863172985 ps
CPU time 10.12 seconds
Started Jul 24 05:18:52 PM PDT 24
Finished Jul 24 05:19:02 PM PDT 24
Peak memory 213796 kb
Host smart-9c608be6-a1b2-4e0d-8932-b8c40e20736f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307248951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3307248951
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2897477794
Short name T305
Test name
Test status
Simulation time 2288032560 ps
CPU time 24.84 seconds
Started Jul 24 05:18:52 PM PDT 24
Finished Jul 24 05:19:17 PM PDT 24
Peak memory 214176 kb
Host smart-2904fe40-48fb-4f3d-a891-bb73604d6d95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897477794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2897477794
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1266480758
Short name T322
Test name
Test status
Simulation time 1372807303 ps
CPU time 5.82 seconds
Started Jul 24 05:18:46 PM PDT 24
Finished Jul 24 05:18:52 PM PDT 24
Peak memory 211232 kb
Host smart-33ecc905-5c20-4885-8645-8d2ed1773ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266480758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1266480758
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1861317063
Short name T196
Test name
Test status
Simulation time 2041852773 ps
CPU time 130.89 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:20:54 PM PDT 24
Peak memory 237816 kb
Host smart-18867695-f6ba-4750-a52d-9c29f790a64d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861317063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1861317063
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.25650960
Short name T219
Test name
Test status
Simulation time 4094720338 ps
CPU time 15.76 seconds
Started Jul 24 05:18:36 PM PDT 24
Finished Jul 24 05:18:52 PM PDT 24
Peak memory 212284 kb
Host smart-edb04928-e40e-4120-bee5-2f178176ca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25650960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.25650960
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3872579141
Short name T9
Test name
Test status
Simulation time 4634565245 ps
CPU time 11.84 seconds
Started Jul 24 05:18:33 PM PDT 24
Finished Jul 24 05:18:45 PM PDT 24
Peak memory 211476 kb
Host smart-e4d6b5a3-725e-4ace-a4fd-6bafc8eaeb4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872579141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3872579141
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2758663953
Short name T283
Test name
Test status
Simulation time 6722550732 ps
CPU time 29.6 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:19:07 PM PDT 24
Peak memory 213116 kb
Host smart-4bf8560e-7722-44d5-8574-563e69b89b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758663953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2758663953
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2876925734
Short name T158
Test name
Test status
Simulation time 11770022953 ps
CPU time 31.98 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:19:16 PM PDT 24
Peak memory 214048 kb
Host smart-0851975f-5712-48b0-95ec-cea315bcba31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876925734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2876925734
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.972636226
Short name T156
Test name
Test status
Simulation time 1379945999 ps
CPU time 6.68 seconds
Started Jul 24 05:18:44 PM PDT 24
Finished Jul 24 05:18:51 PM PDT 24
Peak memory 211308 kb
Host smart-f0d204d9-8b22-4314-a95e-e888a6d2b4fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972636226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.972636226
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2998207703
Short name T44
Test name
Test status
Simulation time 38428614622 ps
CPU time 189.74 seconds
Started Jul 24 05:18:51 PM PDT 24
Finished Jul 24 05:22:01 PM PDT 24
Peak memory 237072 kb
Host smart-58661b95-e49a-4f52-8942-2985217e4ae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998207703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2998207703
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3498001227
Short name T24
Test name
Test status
Simulation time 2070154806 ps
CPU time 22.11 seconds
Started Jul 24 05:18:38 PM PDT 24
Finished Jul 24 05:19:00 PM PDT 24
Peak memory 211824 kb
Host smart-8428c811-0454-4e5e-bed3-aa06435fec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498001227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3498001227
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4190641316
Short name T213
Test name
Test status
Simulation time 8367184704 ps
CPU time 16.94 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:18:54 PM PDT 24
Peak memory 211444 kb
Host smart-86228d31-7a50-443a-a075-1670d0000d3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190641316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4190641316
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2465320136
Short name T288
Test name
Test status
Simulation time 25574115856 ps
CPU time 25.71 seconds
Started Jul 24 05:18:35 PM PDT 24
Finished Jul 24 05:19:01 PM PDT 24
Peak memory 213448 kb
Host smart-e77b7fb8-2fca-43cb-9bec-dca433e6a2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465320136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2465320136
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.795834509
Short name T200
Test name
Test status
Simulation time 77819476817 ps
CPU time 122.23 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:20:39 PM PDT 24
Peak memory 219400 kb
Host smart-a939ce5f-2035-4a40-ad0f-382d3992cecb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795834509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.795834509
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2525286423
Short name T136
Test name
Test status
Simulation time 2135665588 ps
CPU time 10.05 seconds
Started Jul 24 05:18:49 PM PDT 24
Finished Jul 24 05:18:59 PM PDT 24
Peak memory 211400 kb
Host smart-6d028df8-f14e-4cda-a9a6-fcf6ee7e342d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525286423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2525286423
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2848986138
Short name T319
Test name
Test status
Simulation time 19641447699 ps
CPU time 201.23 seconds
Started Jul 24 05:18:54 PM PDT 24
Finished Jul 24 05:22:15 PM PDT 24
Peak memory 237856 kb
Host smart-8ad40b79-13a2-4628-bf41-d7a984af49ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848986138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2848986138
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.423969623
Short name T362
Test name
Test status
Simulation time 3300307273 ps
CPU time 29.05 seconds
Started Jul 24 05:18:50 PM PDT 24
Finished Jul 24 05:19:19 PM PDT 24
Peak memory 211900 kb
Host smart-028eddde-d707-4c65-a5ab-15ec04a0000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423969623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.423969623
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.597151605
Short name T311
Test name
Test status
Simulation time 13831423489 ps
CPU time 15.69 seconds
Started Jul 24 05:18:41 PM PDT 24
Finished Jul 24 05:18:57 PM PDT 24
Peak memory 211492 kb
Host smart-b4a141e6-24a3-4655-bfaf-4bae9b7848b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=597151605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.597151605
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3203174397
Short name T141
Test name
Test status
Simulation time 2022273352 ps
CPU time 23.6 seconds
Started Jul 24 05:18:53 PM PDT 24
Finished Jul 24 05:19:17 PM PDT 24
Peak memory 211468 kb
Host smart-59e99344-943e-4fba-aa6a-4230c7178895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203174397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3203174397
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.968833213
Short name T122
Test name
Test status
Simulation time 82524919471 ps
CPU time 70.37 seconds
Started Jul 24 05:18:43 PM PDT 24
Finished Jul 24 05:19:53 PM PDT 24
Peak memory 219460 kb
Host smart-d3344076-acf0-4f79-909a-9997f32bdd05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968833213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.968833213
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2833309481
Short name T292
Test name
Test status
Simulation time 8402820999 ps
CPU time 15.11 seconds
Started Jul 24 05:18:39 PM PDT 24
Finished Jul 24 05:18:54 PM PDT 24
Peak memory 211312 kb
Host smart-2f9c55b8-e01e-4e42-9513-bec3c99b8494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833309481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2833309481
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2982214484
Short name T97
Test name
Test status
Simulation time 34706069478 ps
CPU time 178.67 seconds
Started Jul 24 05:18:42 PM PDT 24
Finished Jul 24 05:21:41 PM PDT 24
Peak memory 237816 kb
Host smart-b20dd7c1-7298-4dfc-8f15-a177cd4493a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982214484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2982214484
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.978607825
Short name T226
Test name
Test status
Simulation time 11278389738 ps
CPU time 25.31 seconds
Started Jul 24 05:18:52 PM PDT 24
Finished Jul 24 05:19:18 PM PDT 24
Peak memory 212184 kb
Host smart-a02b40ec-e71e-43bd-82c1-0c0e937127ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978607825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.978607825
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4038516524
Short name T205
Test name
Test status
Simulation time 5607862449 ps
CPU time 12.39 seconds
Started Jul 24 05:18:46 PM PDT 24
Finished Jul 24 05:18:59 PM PDT 24
Peak memory 211392 kb
Host smart-d9a25b0f-8c96-4b51-bb44-98c547b53416
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038516524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4038516524
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1634250298
Short name T218
Test name
Test status
Simulation time 7377516459 ps
CPU time 26.58 seconds
Started Jul 24 05:18:47 PM PDT 24
Finished Jul 24 05:19:14 PM PDT 24
Peak memory 214024 kb
Host smart-ed588156-a558-4a56-8592-9ff2fab7ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634250298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1634250298
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.649265092
Short name T262
Test name
Test status
Simulation time 9899572588 ps
CPU time 89.06 seconds
Started Jul 24 05:18:51 PM PDT 24
Finished Jul 24 05:20:20 PM PDT 24
Peak memory 217372 kb
Host smart-7339d81d-e737-4e47-8663-12f4aad359dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649265092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.649265092
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3161560885
Short name T50
Test name
Test status
Simulation time 41718517425 ps
CPU time 400.86 seconds
Started Jul 24 05:18:37 PM PDT 24
Finished Jul 24 05:25:18 PM PDT 24
Peak memory 225980 kb
Host smart-0dfd831c-0ccf-48fd-a0a8-757633764d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161560885 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3161560885
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.172626009
Short name T310
Test name
Test status
Simulation time 12670896680 ps
CPU time 15.97 seconds
Started Jul 24 05:18:12 PM PDT 24
Finished Jul 24 05:18:28 PM PDT 24
Peak memory 211400 kb
Host smart-768fc0b2-6425-4f91-97c8-c3b56c945bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172626009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.172626009
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3156549656
Short name T271
Test name
Test status
Simulation time 17007473993 ps
CPU time 129.53 seconds
Started Jul 24 05:18:00 PM PDT 24
Finished Jul 24 05:20:10 PM PDT 24
Peak memory 225404 kb
Host smart-e4bed946-c979-4e89-8ade-717aca837161
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156549656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3156549656
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3730628524
Short name T333
Test name
Test status
Simulation time 2429439251 ps
CPU time 22.25 seconds
Started Jul 24 05:18:12 PM PDT 24
Finished Jul 24 05:18:35 PM PDT 24
Peak memory 211888 kb
Host smart-c84bf5aa-0cc8-4abd-b79e-aaf2885e7413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730628524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3730628524
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.872948484
Short name T176
Test name
Test status
Simulation time 97161044 ps
CPU time 5.44 seconds
Started Jul 24 05:18:04 PM PDT 24
Finished Jul 24 05:18:09 PM PDT 24
Peak memory 211356 kb
Host smart-1fc6d986-e459-47a5-9ff8-af142b205b31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872948484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.872948484
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1631838695
Short name T261
Test name
Test status
Simulation time 512991352 ps
CPU time 14.73 seconds
Started Jul 24 05:18:13 PM PDT 24
Finished Jul 24 05:18:28 PM PDT 24
Peak memory 212284 kb
Host smart-72a0a76b-80c9-4833-9ac7-2a999f8b7b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631838695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1631838695
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4046267427
Short name T266
Test name
Test status
Simulation time 6359619942 ps
CPU time 32.05 seconds
Started Jul 24 05:18:05 PM PDT 24
Finished Jul 24 05:18:37 PM PDT 24
Peak memory 217472 kb
Host smart-0d6fab15-48b0-47ed-be04-d5f76e8d63ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046267427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4046267427
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.569654252
Short name T143
Test name
Test status
Simulation time 3420616371 ps
CPU time 13.96 seconds
Started Jul 24 05:18:11 PM PDT 24
Finished Jul 24 05:18:25 PM PDT 24
Peak memory 211368 kb
Host smart-bffb99c2-a9b9-455a-8b3d-4d62ee306bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569654252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.569654252
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3565760852
Short name T258
Test name
Test status
Simulation time 2543578178 ps
CPU time 149.46 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:20:38 PM PDT 24
Peak memory 228344 kb
Host smart-82dd706b-ba75-4924-b6ab-fd8587801d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565760852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3565760852
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2728976566
Short name T188
Test name
Test status
Simulation time 16081891950 ps
CPU time 31.51 seconds
Started Jul 24 05:18:11 PM PDT 24
Finished Jul 24 05:18:43 PM PDT 24
Peak memory 211472 kb
Host smart-d6a48e11-c276-4b4b-8625-5931ace37793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728976566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2728976566
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.317336800
Short name T360
Test name
Test status
Simulation time 761738708 ps
CPU time 5.45 seconds
Started Jul 24 05:18:15 PM PDT 24
Finished Jul 24 05:18:21 PM PDT 24
Peak memory 211392 kb
Host smart-44a3e04e-709c-4441-9ffd-5154bbb10d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317336800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.317336800
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2098659545
Short name T259
Test name
Test status
Simulation time 3938803925 ps
CPU time 33.29 seconds
Started Jul 24 05:18:02 PM PDT 24
Finished Jul 24 05:18:36 PM PDT 24
Peak memory 213380 kb
Host smart-65597c11-372d-4134-8ab4-17202bf1be0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098659545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2098659545
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.599653205
Short name T191
Test name
Test status
Simulation time 11912394777 ps
CPU time 52.75 seconds
Started Jul 24 05:18:19 PM PDT 24
Finished Jul 24 05:19:12 PM PDT 24
Peak memory 215560 kb
Host smart-df406ccc-942d-4359-9c37-1f4296206918
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599653205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.599653205
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3691337436
Short name T273
Test name
Test status
Simulation time 1943573758 ps
CPU time 15.91 seconds
Started Jul 24 05:18:10 PM PDT 24
Finished Jul 24 05:18:26 PM PDT 24
Peak memory 211304 kb
Host smart-816bb54e-11c2-4b81-a2f2-3b6e05f018c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691337436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3691337436
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3528409969
Short name T13
Test name
Test status
Simulation time 9172487024 ps
CPU time 121.28 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:20:10 PM PDT 24
Peak memory 233864 kb
Host smart-1ed7c318-2bec-40ff-9db3-ec70abbfb840
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528409969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3528409969
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.707448689
Short name T198
Test name
Test status
Simulation time 5894134548 ps
CPU time 19.45 seconds
Started Jul 24 05:18:14 PM PDT 24
Finished Jul 24 05:18:34 PM PDT 24
Peak memory 212484 kb
Host smart-6ca10c3f-13e6-4e0d-ba8f-c771ea2374e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707448689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.707448689
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2537311130
Short name T91
Test name
Test status
Simulation time 97238551 ps
CPU time 5.26 seconds
Started Jul 24 05:18:16 PM PDT 24
Finished Jul 24 05:18:22 PM PDT 24
Peak memory 211392 kb
Host smart-c5e966a7-3d53-4a31-8cf1-f12c4716c37e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2537311130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2537311130
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4022661435
Short name T233
Test name
Test status
Simulation time 2243543784 ps
CPU time 18.75 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:27 PM PDT 24
Peak memory 213256 kb
Host smart-6943b8b4-20bb-4828-b1da-d7d9ce542b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022661435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4022661435
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3915901853
Short name T142
Test name
Test status
Simulation time 2899369893 ps
CPU time 31.06 seconds
Started Jul 24 05:18:05 PM PDT 24
Finished Jul 24 05:18:36 PM PDT 24
Peak memory 213592 kb
Host smart-85e13490-bc39-465b-bee2-fa679fb46d8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915901853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3915901853
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3711371151
Short name T260
Test name
Test status
Simulation time 1932399085 ps
CPU time 15.36 seconds
Started Jul 24 05:18:12 PM PDT 24
Finished Jul 24 05:18:28 PM PDT 24
Peak memory 211344 kb
Host smart-f832e50d-8d3d-44f5-94ff-568feca1214c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711371151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3711371151
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1917062151
Short name T18
Test name
Test status
Simulation time 59323202229 ps
CPU time 183.16 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:21:12 PM PDT 24
Peak memory 228588 kb
Host smart-b2bbcc96-b275-448b-af0b-3d9b5a965ff6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917062151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1917062151
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3106261048
Short name T318
Test name
Test status
Simulation time 1008589403 ps
CPU time 12.16 seconds
Started Jul 24 05:18:22 PM PDT 24
Finished Jul 24 05:18:34 PM PDT 24
Peak memory 212012 kb
Host smart-82890ac6-4382-48cf-8c4d-8c4b622bbc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106261048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3106261048
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3315486549
Short name T294
Test name
Test status
Simulation time 7229275438 ps
CPU time 15.39 seconds
Started Jul 24 05:18:23 PM PDT 24
Finished Jul 24 05:18:38 PM PDT 24
Peak memory 211452 kb
Host smart-62f17d15-dbb8-4816-8b71-af3fc4c8771c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3315486549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3315486549
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2781457943
Short name T220
Test name
Test status
Simulation time 17729195824 ps
CPU time 33.73 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 05:18:52 PM PDT 24
Peak memory 214120 kb
Host smart-523e8c35-26c8-4477-8392-72187461f34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781457943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2781457943
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3299514987
Short name T345
Test name
Test status
Simulation time 1793832656 ps
CPU time 17.91 seconds
Started Jul 24 05:18:04 PM PDT 24
Finished Jul 24 05:18:22 PM PDT 24
Peak memory 215052 kb
Host smart-0cc2b5ad-1ab7-43b4-b17f-3c22933c206d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299514987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3299514987
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3572664630
Short name T350
Test name
Test status
Simulation time 1616941822 ps
CPU time 13.52 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:22 PM PDT 24
Peak memory 211336 kb
Host smart-edfbdec8-7225-45b3-a815-7224cc4b62f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572664630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3572664630
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.336039558
Short name T321
Test name
Test status
Simulation time 6114769732 ps
CPU time 99.43 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 05:19:57 PM PDT 24
Peak memory 233804 kb
Host smart-bef6391b-5877-4223-ab51-a5c9c8974449
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336039558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.336039558
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2910288991
Short name T123
Test name
Test status
Simulation time 3025420342 ps
CPU time 27.9 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:36 PM PDT 24
Peak memory 211984 kb
Host smart-2c4c6b33-0ff3-4823-b530-2e56900f7e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910288991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2910288991
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2437644938
Short name T300
Test name
Test status
Simulation time 482722324 ps
CPU time 5.3 seconds
Started Jul 24 05:18:09 PM PDT 24
Finished Jul 24 05:18:14 PM PDT 24
Peak memory 211320 kb
Host smart-77124620-1357-4e33-9774-87980a2c2801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437644938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2437644938
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2071178176
Short name T353
Test name
Test status
Simulation time 1377724945 ps
CPU time 18.58 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:27 PM PDT 24
Peak memory 212088 kb
Host smart-344588ba-a88d-428f-ac87-d89c5b660cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071178176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2071178176
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4076092507
Short name T153
Test name
Test status
Simulation time 5555521211 ps
CPU time 49.56 seconds
Started Jul 24 05:18:12 PM PDT 24
Finished Jul 24 05:19:02 PM PDT 24
Peak memory 213600 kb
Host smart-2c0c7d6c-e4d8-46d9-9534-fd03a318fc59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076092507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4076092507
Directory /workspace/9.rom_ctrl_stress_all/latest
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