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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.30 96.89 91.99 97.67 100.00 98.28 97.45 98.83


Total test records in report: 478
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T298 /workspace/coverage/default/21.rom_ctrl_stress_all.966862453 Jul 25 05:53:09 PM PDT 24 Jul 25 05:53:17 PM PDT 24 133256354 ps
T299 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1669794404 Jul 25 05:53:26 PM PDT 24 Jul 25 05:54:25 PM PDT 24 920148139 ps
T300 /workspace/coverage/default/47.rom_ctrl_smoke.917867064 Jul 25 05:53:55 PM PDT 24 Jul 25 05:54:08 PM PDT 24 642921715 ps
T301 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2790391813 Jul 25 05:52:53 PM PDT 24 Jul 25 05:54:14 PM PDT 24 22187113254 ps
T302 /workspace/coverage/default/28.rom_ctrl_stress_all.2893910015 Jul 25 05:53:16 PM PDT 24 Jul 25 05:53:26 PM PDT 24 242423404 ps
T303 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2377300368 Jul 25 05:52:58 PM PDT 24 Jul 25 05:53:07 PM PDT 24 172039098 ps
T304 /workspace/coverage/default/18.rom_ctrl_stress_all.1949662226 Jul 25 05:52:58 PM PDT 24 Jul 25 05:53:09 PM PDT 24 399106647 ps
T305 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2967086250 Jul 25 05:53:52 PM PDT 24 Jul 25 06:49:07 PM PDT 24 90832969656 ps
T306 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3400517173 Jul 25 05:53:15 PM PDT 24 Jul 25 05:54:59 PM PDT 24 6872597672 ps
T307 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1136127364 Jul 25 05:53:09 PM PDT 24 Jul 25 06:00:14 PM PDT 24 21228818664 ps
T308 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3791916795 Jul 25 05:53:32 PM PDT 24 Jul 25 05:53:41 PM PDT 24 665647402 ps
T309 /workspace/coverage/default/13.rom_ctrl_stress_all.2056315705 Jul 25 05:53:05 PM PDT 24 Jul 25 05:53:25 PM PDT 24 692505380 ps
T310 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1183587485 Jul 25 05:53:25 PM PDT 24 Jul 25 05:53:32 PM PDT 24 144868152 ps
T311 /workspace/coverage/default/18.rom_ctrl_alert_test.3311855217 Jul 25 05:53:06 PM PDT 24 Jul 25 05:53:11 PM PDT 24 261558670 ps
T312 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3294207294 Jul 25 05:53:25 PM PDT 24 Jul 25 05:55:21 PM PDT 24 7427903960 ps
T313 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.973350632 Jul 25 05:53:07 PM PDT 24 Jul 25 06:32:42 PM PDT 24 63048808538 ps
T314 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.854155401 Jul 25 05:53:41 PM PDT 24 Jul 25 06:12:24 PM PDT 24 56519656159 ps
T315 /workspace/coverage/default/2.rom_ctrl_smoke.524412253 Jul 25 05:52:37 PM PDT 24 Jul 25 05:52:47 PM PDT 24 377679665 ps
T316 /workspace/coverage/default/27.rom_ctrl_stress_all.3442002776 Jul 25 05:53:16 PM PDT 24 Jul 25 05:53:43 PM PDT 24 1762092337 ps
T317 /workspace/coverage/default/41.rom_ctrl_smoke.4120514955 Jul 25 05:53:40 PM PDT 24 Jul 25 05:53:52 PM PDT 24 276577289 ps
T102 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3100215761 Jul 25 05:53:54 PM PDT 24 Jul 25 05:54:00 PM PDT 24 275649343 ps
T318 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2719177430 Jul 25 05:53:54 PM PDT 24 Jul 25 06:13:52 PM PDT 24 65038318717 ps
T319 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3313685900 Jul 25 05:53:26 PM PDT 24 Jul 25 05:55:43 PM PDT 24 8465052899 ps
T320 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2084517653 Jul 25 05:53:48 PM PDT 24 Jul 25 05:54:05 PM PDT 24 2096841056 ps
T321 /workspace/coverage/default/29.rom_ctrl_smoke.2406433111 Jul 25 05:53:25 PM PDT 24 Jul 25 05:53:35 PM PDT 24 182043660 ps
T322 /workspace/coverage/default/19.rom_ctrl_stress_all.614243098 Jul 25 05:53:07 PM PDT 24 Jul 25 05:53:18 PM PDT 24 797949529 ps
T323 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2827913909 Jul 25 05:53:09 PM PDT 24 Jul 25 05:53:21 PM PDT 24 262776743 ps
T324 /workspace/coverage/default/3.rom_ctrl_stress_all.2295190600 Jul 25 05:52:50 PM PDT 24 Jul 25 05:53:09 PM PDT 24 1583720965 ps
T325 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4204876349 Jul 25 05:53:55 PM PDT 24 Jul 25 07:23:39 PM PDT 24 127885095584 ps
T326 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2223709477 Jul 25 05:53:50 PM PDT 24 Jul 25 05:53:56 PM PDT 24 187967010 ps
T327 /workspace/coverage/default/8.rom_ctrl_alert_test.1451413347 Jul 25 05:52:52 PM PDT 24 Jul 25 05:53:00 PM PDT 24 500073061 ps
T328 /workspace/coverage/default/28.rom_ctrl_alert_test.2333911021 Jul 25 05:53:26 PM PDT 24 Jul 25 05:53:31 PM PDT 24 305601029 ps
T329 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.740729634 Jul 25 05:52:59 PM PDT 24 Jul 25 05:55:51 PM PDT 24 58021890196 ps
T330 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2098545402 Jul 25 05:53:25 PM PDT 24 Jul 25 05:53:31 PM PDT 24 392202916 ps
T16 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2446800264 Jul 25 05:52:58 PM PDT 24 Jul 25 06:24:31 PM PDT 24 98512906287 ps
T331 /workspace/coverage/default/0.rom_ctrl_smoke.760899026 Jul 25 05:52:37 PM PDT 24 Jul 25 05:52:47 PM PDT 24 721101188 ps
T332 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1096104204 Jul 25 05:53:25 PM PDT 24 Jul 25 05:53:31 PM PDT 24 762486215 ps
T333 /workspace/coverage/default/23.rom_ctrl_alert_test.3625049882 Jul 25 05:53:09 PM PDT 24 Jul 25 05:53:13 PM PDT 24 110395453 ps
T334 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1415727759 Jul 25 05:57:22 PM PDT 24 Jul 25 05:57:29 PM PDT 24 560533019 ps
T335 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3650183775 Jul 25 05:53:17 PM PDT 24 Jul 25 05:53:23 PM PDT 24 379001966 ps
T336 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2890890824 Jul 25 05:52:58 PM PDT 24 Jul 25 05:53:04 PM PDT 24 523505098 ps
T337 /workspace/coverage/default/36.rom_ctrl_smoke.753270410 Jul 25 05:53:33 PM PDT 24 Jul 25 05:53:44 PM PDT 24 188511826 ps
T338 /workspace/coverage/default/41.rom_ctrl_stress_all.1422418441 Jul 25 05:53:42 PM PDT 24 Jul 25 05:54:02 PM PDT 24 2461682241 ps
T339 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.788010025 Jul 25 05:52:49 PM PDT 24 Jul 25 06:00:13 PM PDT 24 46683773686 ps
T340 /workspace/coverage/default/4.rom_ctrl_alert_test.3501414975 Jul 25 05:52:48 PM PDT 24 Jul 25 05:52:53 PM PDT 24 537869010 ps
T341 /workspace/coverage/default/10.rom_ctrl_smoke.303707489 Jul 25 05:52:51 PM PDT 24 Jul 25 05:53:03 PM PDT 24 1319327072 ps
T342 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1680077367 Jul 25 05:53:09 PM PDT 24 Jul 25 05:53:18 PM PDT 24 504171816 ps
T343 /workspace/coverage/default/5.rom_ctrl_stress_all.3670585234 Jul 25 05:52:49 PM PDT 24 Jul 25 05:53:20 PM PDT 24 564943375 ps
T344 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2873911878 Jul 25 05:52:48 PM PDT 24 Jul 25 05:52:57 PM PDT 24 341818186 ps
T345 /workspace/coverage/default/29.rom_ctrl_stress_all.3002751630 Jul 25 05:53:24 PM PDT 24 Jul 25 05:53:51 PM PDT 24 914404576 ps
T346 /workspace/coverage/default/40.rom_ctrl_alert_test.2022029512 Jul 25 05:53:42 PM PDT 24 Jul 25 05:53:47 PM PDT 24 784942964 ps
T347 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2549301974 Jul 25 05:53:26 PM PDT 24 Jul 25 06:22:58 PM PDT 24 92677999536 ps
T348 /workspace/coverage/default/35.rom_ctrl_stress_all.3084117352 Jul 25 05:53:34 PM PDT 24 Jul 25 05:53:57 PM PDT 24 377706608 ps
T349 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1951994500 Jul 25 05:53:17 PM PDT 24 Jul 25 05:53:24 PM PDT 24 138213026 ps
T350 /workspace/coverage/default/39.rom_ctrl_stress_all.653282610 Jul 25 05:53:44 PM PDT 24 Jul 25 05:53:58 PM PDT 24 381118849 ps
T351 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1505693869 Jul 25 05:52:40 PM PDT 24 Jul 25 05:52:51 PM PDT 24 482139470 ps
T352 /workspace/coverage/default/3.rom_ctrl_alert_test.2999582074 Jul 25 05:52:47 PM PDT 24 Jul 25 05:52:52 PM PDT 24 884012802 ps
T353 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1023549538 Jul 25 05:52:50 PM PDT 24 Jul 25 05:54:02 PM PDT 24 1225761510 ps
T354 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3903336035 Jul 25 05:53:04 PM PDT 24 Jul 25 05:54:26 PM PDT 24 5223706095 ps
T355 /workspace/coverage/default/27.rom_ctrl_alert_test.3413504673 Jul 25 05:53:17 PM PDT 24 Jul 25 05:53:22 PM PDT 24 129135254 ps
T356 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1653042911 Jul 25 05:53:44 PM PDT 24 Jul 25 06:04:10 PM PDT 24 163534947355 ps
T357 /workspace/coverage/default/34.rom_ctrl_alert_test.2093145467 Jul 25 05:53:32 PM PDT 24 Jul 25 05:53:38 PM PDT 24 499786764 ps
T358 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1438222388 Jul 25 05:53:16 PM PDT 24 Jul 25 05:53:28 PM PDT 24 500600618 ps
T359 /workspace/coverage/default/6.rom_ctrl_stress_all.3099296400 Jul 25 05:52:58 PM PDT 24 Jul 25 05:53:05 PM PDT 24 224430678 ps
T360 /workspace/coverage/default/7.rom_ctrl_smoke.1276698840 Jul 25 05:52:45 PM PDT 24 Jul 25 05:52:57 PM PDT 24 276548753 ps
T361 /workspace/coverage/default/21.rom_ctrl_smoke.2246396547 Jul 25 05:53:06 PM PDT 24 Jul 25 05:53:17 PM PDT 24 718062558 ps
T362 /workspace/coverage/default/43.rom_ctrl_stress_all.4127671410 Jul 25 05:53:43 PM PDT 24 Jul 25 05:54:21 PM PDT 24 635556951 ps
T363 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2182514581 Jul 25 05:54:12 PM PDT 24 Jul 25 05:54:23 PM PDT 24 956396970 ps
T364 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2965467856 Jul 25 05:53:00 PM PDT 24 Jul 25 05:53:07 PM PDT 24 143975161 ps
T365 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2590052980 Jul 25 05:53:42 PM PDT 24 Jul 25 05:53:49 PM PDT 24 97249980 ps
T366 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4242219953 Jul 25 05:52:58 PM PDT 24 Jul 25 05:53:08 PM PDT 24 340803223 ps
T367 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1876434176 Jul 25 05:52:57 PM PDT 24 Jul 25 05:53:04 PM PDT 24 278016569 ps
T368 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2728538294 Jul 25 05:52:36 PM PDT 24 Jul 25 05:52:42 PM PDT 24 394381116 ps
T369 /workspace/coverage/default/25.rom_ctrl_alert_test.983492723 Jul 25 05:53:15 PM PDT 24 Jul 25 05:53:21 PM PDT 24 134749724 ps
T370 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.39569814 Jul 25 05:53:44 PM PDT 24 Jul 25 05:53:56 PM PDT 24 1039362779 ps
T371 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3963403276 Jul 25 05:52:56 PM PDT 24 Jul 25 05:54:05 PM PDT 24 1093978755 ps
T372 /workspace/coverage/default/14.rom_ctrl_stress_all.452943762 Jul 25 05:53:04 PM PDT 24 Jul 25 05:53:12 PM PDT 24 479140795 ps
T373 /workspace/coverage/default/41.rom_ctrl_alert_test.766160774 Jul 25 05:53:45 PM PDT 24 Jul 25 05:53:51 PM PDT 24 132393637 ps
T374 /workspace/coverage/default/1.rom_ctrl_stress_all.1621063133 Jul 25 05:52:37 PM PDT 24 Jul 25 05:52:56 PM PDT 24 805459463 ps
T375 /workspace/coverage/default/14.rom_ctrl_smoke.667014315 Jul 25 05:52:58 PM PDT 24 Jul 25 05:53:10 PM PDT 24 1109053484 ps
T376 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.629028303 Jul 25 05:52:49 PM PDT 24 Jul 25 05:52:55 PM PDT 24 98347777 ps
T377 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.20964794 Jul 25 05:53:52 PM PDT 24 Jul 25 05:54:02 PM PDT 24 722448107 ps
T378 /workspace/coverage/default/46.rom_ctrl_stress_all.1022366186 Jul 25 05:53:52 PM PDT 24 Jul 25 05:53:58 PM PDT 24 108101736 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3526502058 Jul 25 05:51:58 PM PDT 24 Jul 25 05:52:09 PM PDT 24 215934891 ps
T52 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.932511880 Jul 25 05:52:00 PM PDT 24 Jul 25 05:52:08 PM PDT 24 1702701739 ps
T49 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1527480556 Jul 25 05:52:11 PM PDT 24 Jul 25 05:52:51 PM PDT 24 1264105982 ps
T53 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2021667427 Jul 25 05:52:13 PM PDT 24 Jul 25 05:52:18 PM PDT 24 544027847 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2901775652 Jul 25 05:52:06 PM PDT 24 Jul 25 05:52:12 PM PDT 24 130144793 ps
T64 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3062001295 Jul 25 05:52:20 PM PDT 24 Jul 25 05:52:28 PM PDT 24 263611170 ps
T65 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2755290566 Jul 25 05:52:09 PM PDT 24 Jul 25 05:52:14 PM PDT 24 131887613 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2907896698 Jul 25 05:52:22 PM PDT 24 Jul 25 05:52:31 PM PDT 24 347275775 ps
T381 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.298562472 Jul 25 05:52:22 PM PDT 24 Jul 25 05:52:30 PM PDT 24 854438886 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3720410341 Jul 25 05:52:37 PM PDT 24 Jul 25 05:52:44 PM PDT 24 137487595 ps
T383 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1104344620 Jul 25 05:52:23 PM PDT 24 Jul 25 05:52:35 PM PDT 24 1909952749 ps
T50 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1688693309 Jul 25 05:52:21 PM PDT 24 Jul 25 05:53:29 PM PDT 24 967097793 ps
T384 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1590018227 Jul 25 05:52:36 PM PDT 24 Jul 25 05:52:47 PM PDT 24 170142408 ps
T66 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3253988304 Jul 25 05:51:57 PM PDT 24 Jul 25 05:52:02 PM PDT 24 501715400 ps
T104 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4042442143 Jul 25 05:52:36 PM PDT 24 Jul 25 05:52:58 PM PDT 24 2174751652 ps
T105 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.604644453 Jul 25 05:52:25 PM PDT 24 Jul 25 05:52:48 PM PDT 24 527930419 ps
T385 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3060353402 Jul 25 05:52:25 PM PDT 24 Jul 25 05:52:30 PM PDT 24 115324029 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3659865080 Jul 25 05:51:59 PM PDT 24 Jul 25 05:52:05 PM PDT 24 1292877268 ps
T106 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.747961842 Jul 25 05:52:24 PM PDT 24 Jul 25 05:52:29 PM PDT 24 522565974 ps
T51 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3368274449 Jul 25 05:52:09 PM PDT 24 Jul 25 05:52:45 PM PDT 24 228054365 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2745523498 Jul 25 05:52:22 PM PDT 24 Jul 25 05:52:27 PM PDT 24 91182673 ps
T116 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1537982767 Jul 25 05:52:21 PM PDT 24 Jul 25 05:53:00 PM PDT 24 386332391 ps
T67 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.914103948 Jul 25 05:52:23 PM PDT 24 Jul 25 05:52:28 PM PDT 24 541310932 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2001914622 Jul 25 05:52:06 PM PDT 24 Jul 25 05:52:16 PM PDT 24 521814217 ps
T68 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2498214368 Jul 25 05:52:34 PM PDT 24 Jul 25 05:52:52 PM PDT 24 1500643098 ps
T69 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1711832478 Jul 25 05:52:22 PM PDT 24 Jul 25 05:53:09 PM PDT 24 13603382847 ps
T389 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2876590539 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:16 PM PDT 24 561513049 ps
T70 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2858562638 Jul 25 05:52:23 PM PDT 24 Jul 25 05:52:30 PM PDT 24 540028096 ps
T71 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2935126598 Jul 25 05:52:36 PM PDT 24 Jul 25 05:52:41 PM PDT 24 729098764 ps
T390 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.339127339 Jul 25 05:52:37 PM PDT 24 Jul 25 05:52:44 PM PDT 24 133641180 ps
T391 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1820888190 Jul 25 05:52:23 PM PDT 24 Jul 25 05:52:33 PM PDT 24 657318060 ps
T392 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1147020768 Jul 25 05:52:22 PM PDT 24 Jul 25 05:52:45 PM PDT 24 533406952 ps
T393 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3056413730 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:26 PM PDT 24 376589311 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3732188261 Jul 25 05:52:07 PM PDT 24 Jul 25 05:52:12 PM PDT 24 1451434654 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2213708629 Jul 25 05:51:58 PM PDT 24 Jul 25 05:52:02 PM PDT 24 1394046970 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3767155591 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:21 PM PDT 24 511782278 ps
T79 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4114213487 Jul 25 05:52:10 PM PDT 24 Jul 25 05:52:29 PM PDT 24 365178495 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4038490706 Jul 25 05:52:00 PM PDT 24 Jul 25 05:52:22 PM PDT 24 1050249822 ps
T97 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.704182403 Jul 25 05:52:38 PM PDT 24 Jul 25 05:52:43 PM PDT 24 728036801 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4140159109 Jul 25 05:52:23 PM PDT 24 Jul 25 05:52:28 PM PDT 24 93137281 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3223293963 Jul 25 05:52:38 PM PDT 24 Jul 25 05:52:43 PM PDT 24 1378274398 ps
T400 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1964415428 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:16 PM PDT 24 378470826 ps
T98 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1213554130 Jul 25 05:52:38 PM PDT 24 Jul 25 05:52:43 PM PDT 24 466054077 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1874170599 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:13 PM PDT 24 310048202 ps
T81 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3703211679 Jul 25 05:52:37 PM PDT 24 Jul 25 05:52:43 PM PDT 24 138445875 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3656804108 Jul 25 05:52:24 PM PDT 24 Jul 25 05:52:33 PM PDT 24 204183514 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1856496715 Jul 25 05:52:00 PM PDT 24 Jul 25 05:52:05 PM PDT 24 95751082 ps
T403 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3280843100 Jul 25 05:52:23 PM PDT 24 Jul 25 05:52:30 PM PDT 24 1036049663 ps
T99 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.784618806 Jul 25 05:52:24 PM PDT 24 Jul 25 05:52:30 PM PDT 24 380024023 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1220932964 Jul 25 05:51:58 PM PDT 24 Jul 25 05:52:06 PM PDT 24 139699765 ps
T100 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.329049731 Jul 25 05:52:07 PM PDT 24 Jul 25 05:52:12 PM PDT 24 399867855 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2204397269 Jul 25 05:52:00 PM PDT 24 Jul 25 05:52:04 PM PDT 24 346668821 ps
T125 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.125926711 Jul 25 05:52:36 PM PDT 24 Jul 25 05:53:46 PM PDT 24 576449878 ps
T117 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2784070062 Jul 25 05:52:37 PM PDT 24 Jul 25 05:53:45 PM PDT 24 284093112 ps
T406 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3053226007 Jul 25 05:52:25 PM PDT 24 Jul 25 05:52:35 PM PDT 24 1039151199 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2392161151 Jul 25 05:52:11 PM PDT 24 Jul 25 05:52:20 PM PDT 24 543803814 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1077750542 Jul 25 05:52:05 PM PDT 24 Jul 25 05:52:11 PM PDT 24 261175579 ps
T409 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3508321254 Jul 25 05:52:09 PM PDT 24 Jul 25 05:52:18 PM PDT 24 842970612 ps
T410 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2472017964 Jul 25 05:52:23 PM PDT 24 Jul 25 05:52:30 PM PDT 24 145360584 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1277905068 Jul 25 05:52:13 PM PDT 24 Jul 25 05:52:21 PM PDT 24 135629267 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2095667419 Jul 25 05:51:58 PM PDT 24 Jul 25 05:52:04 PM PDT 24 341635250 ps
T120 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3173234275 Jul 25 05:52:21 PM PDT 24 Jul 25 05:53:30 PM PDT 24 835438731 ps
T118 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2003816105 Jul 25 05:52:35 PM PDT 24 Jul 25 05:53:44 PM PDT 24 275638594 ps
T413 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.951849353 Jul 25 05:52:35 PM PDT 24 Jul 25 05:52:41 PM PDT 24 118456275 ps
T414 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4066552954 Jul 25 05:52:34 PM PDT 24 Jul 25 05:53:02 PM PDT 24 3847001300 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.154452172 Jul 25 05:52:10 PM PDT 24 Jul 25 05:52:18 PM PDT 24 1240539489 ps
T416 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2040320326 Jul 25 05:51:57 PM PDT 24 Jul 25 05:52:34 PM PDT 24 1552906887 ps
T417 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.637743735 Jul 25 05:52:20 PM PDT 24 Jul 25 05:52:25 PM PDT 24 128172091 ps
T82 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3912025967 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:13 PM PDT 24 515476056 ps
T418 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.10364042 Jul 25 05:52:38 PM PDT 24 Jul 25 05:52:45 PM PDT 24 362320191 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.348425824 Jul 25 05:51:59 PM PDT 24 Jul 25 05:52:05 PM PDT 24 500155489 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.800316352 Jul 25 05:52:39 PM PDT 24 Jul 25 05:52:45 PM PDT 24 139425726 ps
T83 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2497160582 Jul 25 05:52:21 PM PDT 24 Jul 25 05:52:27 PM PDT 24 263237173 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1719741782 Jul 25 05:52:10 PM PDT 24 Jul 25 05:52:20 PM PDT 24 503500815 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3881943989 Jul 25 05:51:58 PM PDT 24 Jul 25 05:52:03 PM PDT 24 520561599 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2539911581 Jul 25 05:52:10 PM PDT 24 Jul 25 05:52:15 PM PDT 24 129694809 ps
T126 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2002392790 Jul 25 05:52:01 PM PDT 24 Jul 25 05:53:10 PM PDT 24 279159879 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3955698849 Jul 25 05:52:21 PM PDT 24 Jul 25 05:52:40 PM PDT 24 1643612131 ps
T84 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1389973370 Jul 25 05:52:22 PM PDT 24 Jul 25 05:52:50 PM PDT 24 1866543794 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3896948450 Jul 25 05:52:06 PM PDT 24 Jul 25 05:52:13 PM PDT 24 1612150823 ps
T86 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3626571682 Jul 25 05:52:38 PM PDT 24 Jul 25 05:53:01 PM PDT 24 538551618 ps
T426 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2495144485 Jul 25 05:52:07 PM PDT 24 Jul 25 05:52:14 PM PDT 24 106056671 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3866380778 Jul 25 05:52:09 PM PDT 24 Jul 25 05:52:14 PM PDT 24 127798549 ps
T428 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.711006587 Jul 25 05:52:24 PM PDT 24 Jul 25 05:52:28 PM PDT 24 101809228 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.630943013 Jul 25 05:52:07 PM PDT 24 Jul 25 05:52:11 PM PDT 24 86413365 ps
T429 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3168663595 Jul 25 05:52:11 PM PDT 24 Jul 25 05:52:15 PM PDT 24 348099017 ps
T430 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2422780431 Jul 25 05:52:24 PM PDT 24 Jul 25 05:53:00 PM PDT 24 491744582 ps
T431 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1718598328 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:13 PM PDT 24 135364413 ps
T432 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4230357682 Jul 25 05:52:01 PM PDT 24 Jul 25 05:52:05 PM PDT 24 334465182 ps
T433 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3636984950 Jul 25 05:52:09 PM PDT 24 Jul 25 05:53:17 PM PDT 24 216122294 ps
T127 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3417873953 Jul 25 05:52:24 PM PDT 24 Jul 25 05:53:01 PM PDT 24 394907690 ps
T434 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1977867278 Jul 25 05:52:39 PM PDT 24 Jul 25 05:52:45 PM PDT 24 140651789 ps
T88 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.423534362 Jul 25 05:52:25 PM PDT 24 Jul 25 05:52:47 PM PDT 24 1087626282 ps
T119 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2696132925 Jul 25 05:52:13 PM PDT 24 Jul 25 05:52:51 PM PDT 24 231099615 ps
T435 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4146412515 Jul 25 05:52:13 PM PDT 24 Jul 25 05:52:45 PM PDT 24 818191015 ps
T123 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.104311062 Jul 25 05:52:10 PM PDT 24 Jul 25 05:52:48 PM PDT 24 419256078 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4161116252 Jul 25 05:51:59 PM PDT 24 Jul 25 05:52:07 PM PDT 24 508837579 ps
T437 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3586826909 Jul 25 05:52:21 PM PDT 24 Jul 25 05:52:48 PM PDT 24 2269441445 ps
T121 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.516710408 Jul 25 05:52:24 PM PDT 24 Jul 25 05:53:35 PM PDT 24 312988444 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2401409203 Jul 25 05:52:06 PM PDT 24 Jul 25 05:52:13 PM PDT 24 1518602308 ps
T439 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2311968035 Jul 25 05:52:22 PM PDT 24 Jul 25 05:52:27 PM PDT 24 359243746 ps
T440 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1158593612 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:16 PM PDT 24 1867305520 ps
T441 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1985110229 Jul 25 05:52:37 PM PDT 24 Jul 25 05:52:41 PM PDT 24 173121090 ps
T442 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.376517320 Jul 25 05:52:22 PM PDT 24 Jul 25 05:52:27 PM PDT 24 958728027 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4283627759 Jul 25 05:52:00 PM PDT 24 Jul 25 05:52:28 PM PDT 24 1543911630 ps
T122 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2276391007 Jul 25 05:52:21 PM PDT 24 Jul 25 05:53:30 PM PDT 24 232764807 ps
T443 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.189897156 Jul 25 05:52:22 PM PDT 24 Jul 25 05:52:29 PM PDT 24 88767170 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.586035412 Jul 25 05:52:23 PM PDT 24 Jul 25 05:52:28 PM PDT 24 441916760 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1244441231 Jul 25 05:52:24 PM PDT 24 Jul 25 05:52:30 PM PDT 24 1021178438 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1705125727 Jul 25 05:52:00 PM PDT 24 Jul 25 05:52:05 PM PDT 24 130502139 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.365189014 Jul 25 05:52:09 PM PDT 24 Jul 25 05:52:16 PM PDT 24 136397329 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.524714352 Jul 25 05:52:35 PM PDT 24 Jul 25 05:52:39 PM PDT 24 349133279 ps
T449 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2406746554 Jul 25 05:52:12 PM PDT 24 Jul 25 05:52:17 PM PDT 24 87609738 ps
T450 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1551840954 Jul 25 05:52:37 PM PDT 24 Jul 25 05:52:41 PM PDT 24 922465928 ps
T124 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3426895898 Jul 25 05:52:35 PM PDT 24 Jul 25 05:53:47 PM PDT 24 326466561 ps
T451 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3355573027 Jul 25 05:52:25 PM PDT 24 Jul 25 05:52:31 PM PDT 24 1183020430 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2729001023 Jul 25 05:52:09 PM PDT 24 Jul 25 05:52:14 PM PDT 24 2464748772 ps
T453 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3197457828 Jul 25 05:52:10 PM PDT 24 Jul 25 05:52:15 PM PDT 24 660652106 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1461673419 Jul 25 05:52:10 PM PDT 24 Jul 25 05:52:18 PM PDT 24 132690194 ps
T455 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.749685656 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:15 PM PDT 24 298352876 ps
T456 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1735994919 Jul 25 05:52:26 PM PDT 24 Jul 25 05:52:30 PM PDT 24 168113932 ps
T457 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2871437292 Jul 25 05:52:35 PM PDT 24 Jul 25 05:52:41 PM PDT 24 500021478 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1895900104 Jul 25 05:51:58 PM PDT 24 Jul 25 05:52:09 PM PDT 24 172938104 ps
T87 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.975886318 Jul 25 05:52:37 PM PDT 24 Jul 25 05:52:42 PM PDT 24 252660617 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1235773090 Jul 25 05:51:57 PM PDT 24 Jul 25 05:52:05 PM PDT 24 512395375 ps
T460 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2390350791 Jul 25 05:52:23 PM PDT 24 Jul 25 05:52:45 PM PDT 24 1502889165 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1317124652 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:27 PM PDT 24 1483253928 ps
T462 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3561923673 Jul 25 05:52:22 PM PDT 24 Jul 25 05:52:29 PM PDT 24 130787908 ps
T463 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1288076206 Jul 25 05:52:35 PM PDT 24 Jul 25 05:52:41 PM PDT 24 100792791 ps
T464 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1430666887 Jul 25 05:52:22 PM PDT 24 Jul 25 05:52:29 PM PDT 24 148236285 ps
T465 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1696998837 Jul 25 05:52:26 PM PDT 24 Jul 25 05:52:31 PM PDT 24 132335034 ps
T466 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4258153397 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:13 PM PDT 24 132855404 ps
T467 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3493875330 Jul 25 05:52:10 PM PDT 24 Jul 25 05:52:16 PM PDT 24 268886306 ps
T468 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1212833124 Jul 25 05:52:37 PM PDT 24 Jul 25 05:52:41 PM PDT 24 112561870 ps
T469 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2809454192 Jul 25 05:52:21 PM PDT 24 Jul 25 05:52:27 PM PDT 24 535661004 ps
T470 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3094380087 Jul 25 05:51:59 PM PDT 24 Jul 25 05:52:17 PM PDT 24 369893678 ps
T471 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4098300776 Jul 25 05:52:20 PM PDT 24 Jul 25 05:52:24 PM PDT 24 161766061 ps
T472 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1689704044 Jul 25 05:52:36 PM PDT 24 Jul 25 05:53:46 PM PDT 24 341658703 ps
T473 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.86038057 Jul 25 05:52:02 PM PDT 24 Jul 25 05:52:07 PM PDT 24 114980829 ps
T90 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4091338116 Jul 25 05:52:07 PM PDT 24 Jul 25 05:52:29 PM PDT 24 2183794180 ps
T474 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2858671562 Jul 25 05:51:58 PM PDT 24 Jul 25 05:52:03 PM PDT 24 85757515 ps
T475 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.785619003 Jul 25 05:52:22 PM PDT 24 Jul 25 05:53:00 PM PDT 24 2291550445 ps
T476 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1895377162 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:13 PM PDT 24 140179068 ps
T477 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.274189182 Jul 25 05:52:39 PM PDT 24 Jul 25 05:52:44 PM PDT 24 96981505 ps
T478 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4026909763 Jul 25 05:52:08 PM PDT 24 Jul 25 05:52:13 PM PDT 24 131305127 ps

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1731579459
Short name T7
Test name
Test status
Simulation time 55085851174 ps
CPU time 5352.78 seconds
Started Jul 25 05:53:31 PM PDT 24
Finished Jul 25 07:22:44 PM PDT 24
Peak memory 236388 kb
Host smart-89f329ea-bfe4-482d-ab9e-4ec17bbf220a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731579459 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1731579459
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2975129768
Short name T8
Test name
Test status
Simulation time 4044672811 ps
CPU time 101.19 seconds
Started Jul 25 05:53:35 PM PDT 24
Finished Jul 25 05:55:16 PM PDT 24
Peak memory 225724 kb
Host smart-06fc5d87-2063-4d6e-943c-7da7deaf10c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975129768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2975129768
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3562392917
Short name T216
Test name
Test status
Simulation time 3656603303 ps
CPU time 176.48 seconds
Started Jul 25 05:52:50 PM PDT 24
Finished Jul 25 05:55:47 PM PDT 24
Peak memory 234824 kb
Host smart-4fcef1c4-2541-4954-8c31-7a3b7f1d6dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562392917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3562392917
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3117535554
Short name T12
Test name
Test status
Simulation time 20218962515 ps
CPU time 939.28 seconds
Started Jul 25 05:53:52 PM PDT 24
Finished Jul 25 06:09:31 PM PDT 24
Peak memory 233132 kb
Host smart-68d0061f-cbd7-4fd1-9813-b7835e5c17b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117535554 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3117535554
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1688693309
Short name T50
Test name
Test status
Simulation time 967097793 ps
CPU time 68.35 seconds
Started Jul 25 05:52:21 PM PDT 24
Finished Jul 25 05:53:29 PM PDT 24
Peak memory 218848 kb
Host smart-594f329d-b729-4def-bcbf-83ae414d4610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688693309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1688693309
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1662991799
Short name T11
Test name
Test status
Simulation time 762986502 ps
CPU time 99.97 seconds
Started Jul 25 05:52:38 PM PDT 24
Finished Jul 25 05:54:19 PM PDT 24
Peak memory 236704 kb
Host smart-a0b831ab-3efa-4450-8103-228d05d4dd32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662991799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1662991799
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2498214368
Short name T68
Test name
Test status
Simulation time 1500643098 ps
CPU time 18.39 seconds
Started Jul 25 05:52:34 PM PDT 24
Finished Jul 25 05:52:52 PM PDT 24
Peak memory 210632 kb
Host smart-6c514d32-1629-4147-a6ca-75fc0dd800d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498214368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2498214368
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1364857552
Short name T5
Test name
Test status
Simulation time 333376680 ps
CPU time 4.38 seconds
Started Jul 25 05:53:41 PM PDT 24
Finished Jul 25 05:53:46 PM PDT 24
Peak memory 211840 kb
Host smart-d9990cc6-8f8f-4a6d-837f-d64345b60381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364857552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1364857552
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2002392790
Short name T126
Test name
Test status
Simulation time 279159879 ps
CPU time 69.08 seconds
Started Jul 25 05:52:01 PM PDT 24
Finished Jul 25 05:53:10 PM PDT 24
Peak memory 213192 kb
Host smart-de800fa0-1cdf-4d21-b8a7-64f62e323a13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002392790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2002392790
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3144857780
Short name T129
Test name
Test status
Simulation time 74167173081 ps
CPU time 1447.48 seconds
Started Jul 25 05:53:03 PM PDT 24
Finished Jul 25 06:17:11 PM PDT 24
Peak memory 236360 kb
Host smart-dee72239-8f5c-4b95-a22c-d68dc9550fc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144857780 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3144857780
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3902208088
Short name T133
Test name
Test status
Simulation time 1665637008 ps
CPU time 11.46 seconds
Started Jul 25 05:53:08 PM PDT 24
Finished Jul 25 05:53:20 PM PDT 24
Peak memory 212652 kb
Host smart-a91d162c-c14b-401b-b3f4-55ae40a38070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902208088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3902208088
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2377300368
Short name T303
Test name
Test status
Simulation time 172039098 ps
CPU time 9.5 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:07 PM PDT 24
Peak memory 212628 kb
Host smart-3bc32e7f-2405-459e-8aed-5e7ca9c4f9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377300368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2377300368
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2784070062
Short name T117
Test name
Test status
Simulation time 284093112 ps
CPU time 68.4 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:53:45 PM PDT 24
Peak memory 212292 kb
Host smart-4cf1a1b2-ab9c-4c51-a6a3-7592a3b58494
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784070062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2784070062
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3913423070
Short name T107
Test name
Test status
Simulation time 134594100 ps
CPU time 6.1 seconds
Started Jul 25 05:52:36 PM PDT 24
Finished Jul 25 05:52:42 PM PDT 24
Peak memory 211960 kb
Host smart-eab8a8cf-fdcb-4fe5-92a5-ea94f6af9457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913423070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3913423070
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.914103948
Short name T67
Test name
Test status
Simulation time 541310932 ps
CPU time 5.15 seconds
Started Jul 25 05:52:23 PM PDT 24
Finished Jul 25 05:52:28 PM PDT 24
Peak memory 218852 kb
Host smart-022160a9-369e-40d4-ad25-6f3b6f94cd5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914103948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.914103948
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1219195665
Short name T152
Test name
Test status
Simulation time 5377627789 ps
CPU time 88.52 seconds
Started Jul 25 05:52:39 PM PDT 24
Finished Jul 25 05:54:07 PM PDT 24
Peak memory 238228 kb
Host smart-500f4847-b49b-4087-9e34-98e2f46d4908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219195665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1219195665
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3173234275
Short name T120
Test name
Test status
Simulation time 835438731 ps
CPU time 68.86 seconds
Started Jul 25 05:52:21 PM PDT 24
Finished Jul 25 05:53:30 PM PDT 24
Peak memory 212520 kb
Host smart-e792bb00-2979-4451-a889-b1b928b41034
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173234275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3173234275
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3368274449
Short name T51
Test name
Test status
Simulation time 228054365 ps
CPU time 36.76 seconds
Started Jul 25 05:52:09 PM PDT 24
Finished Jul 25 05:52:45 PM PDT 24
Peak memory 211328 kb
Host smart-e74e5d01-fe7c-4a19-b3f0-2b2e02750575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368274449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3368274449
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1770458770
Short name T44
Test name
Test status
Simulation time 108243677888 ps
CPU time 5993.47 seconds
Started Jul 25 05:52:57 PM PDT 24
Finished Jul 25 07:32:52 PM PDT 24
Peak memory 236368 kb
Host smart-ef656e45-6869-456d-a5ea-030c99814875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770458770 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1770458770
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3778855189
Short name T91
Test name
Test status
Simulation time 2153779376 ps
CPU time 11.78 seconds
Started Jul 25 05:52:57 PM PDT 24
Finished Jul 25 05:53:08 PM PDT 24
Peak memory 214144 kb
Host smart-355ad802-2106-4093-b1cb-0d03d5ad6fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778855189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3778855189
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1491669977
Short name T78
Test name
Test status
Simulation time 2627135930 ps
CPU time 31.19 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:53:08 PM PDT 24
Peak memory 217380 kb
Host smart-e2b4efea-ad60-4383-a7e6-d4e37b63e655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491669977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1491669977
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2446800264
Short name T16
Test name
Test status
Simulation time 98512906287 ps
CPU time 1892.73 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 06:24:31 PM PDT 24
Peak memory 237052 kb
Host smart-5795c7ba-e652-41d4-bb3a-7e3678ff0d0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446800264 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2446800264
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3881943989
Short name T422
Test name
Test status
Simulation time 520561599 ps
CPU time 4.94 seconds
Started Jul 25 05:51:58 PM PDT 24
Finished Jul 25 05:52:03 PM PDT 24
Peak memory 210576 kb
Host smart-81d3bba5-8e4d-45a9-8658-d7d137d9a560
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881943989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3881943989
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1705125727
Short name T446
Test name
Test status
Simulation time 130502139 ps
CPU time 5.47 seconds
Started Jul 25 05:52:00 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 210644 kb
Host smart-bb5127c5-dd09-4872-ae72-9bd4860c324e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705125727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1705125727
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2095667419
Short name T412
Test name
Test status
Simulation time 341635250 ps
CPU time 5.77 seconds
Started Jul 25 05:51:58 PM PDT 24
Finished Jul 25 05:52:04 PM PDT 24
Peak memory 210584 kb
Host smart-e70d1de7-1b41-4d47-8060-26fbc07a0a05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095667419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2095667419
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4161116252
Short name T436
Test name
Test status
Simulation time 508837579 ps
CPU time 7.67 seconds
Started Jul 25 05:51:59 PM PDT 24
Finished Jul 25 05:52:07 PM PDT 24
Peak memory 218920 kb
Host smart-9a47138f-2258-4216-8b65-24a09ba03eab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161116252 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4161116252
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.932511880
Short name T52
Test name
Test status
Simulation time 1702701739 ps
CPU time 7.51 seconds
Started Jul 25 05:52:00 PM PDT 24
Finished Jul 25 05:52:08 PM PDT 24
Peak memory 210584 kb
Host smart-79e12304-a926-4b1d-a720-39a00d81e6a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932511880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.932511880
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.348425824
Short name T419
Test name
Test status
Simulation time 500155489 ps
CPU time 5.14 seconds
Started Jul 25 05:51:59 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 210428 kb
Host smart-c644ca9c-c00e-4b20-85d3-810d40ea1d48
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348425824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.348425824
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2213708629
Short name T395
Test name
Test status
Simulation time 1394046970 ps
CPU time 4.15 seconds
Started Jul 25 05:51:58 PM PDT 24
Finished Jul 25 05:52:02 PM PDT 24
Peak memory 210484 kb
Host smart-7d4d1a05-7d95-4ce6-8660-78bc4a6ece28
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213708629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2213708629
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4283627759
Short name T89
Test name
Test status
Simulation time 1543911630 ps
CPU time 27.24 seconds
Started Jul 25 05:52:00 PM PDT 24
Finished Jul 25 05:52:28 PM PDT 24
Peak memory 210656 kb
Host smart-7ab44d6f-6e18-4842-8b82-4c0e55420e64
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283627759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4283627759
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1235773090
Short name T459
Test name
Test status
Simulation time 512395375 ps
CPU time 7.62 seconds
Started Jul 25 05:51:57 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 210692 kb
Host smart-3e36dd59-1930-4c31-b2e6-6db72b095908
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235773090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1235773090
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3526502058
Short name T379
Test name
Test status
Simulation time 215934891 ps
CPU time 10.8 seconds
Started Jul 25 05:51:58 PM PDT 24
Finished Jul 25 05:52:09 PM PDT 24
Peak memory 215816 kb
Host smart-dfe515bc-3c8e-414a-af61-638afc6daffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526502058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3526502058
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1856496715
Short name T402
Test name
Test status
Simulation time 95751082 ps
CPU time 4.33 seconds
Started Jul 25 05:52:00 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 210624 kb
Host smart-a6991e15-7174-4565-9609-2006d56eb859
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856496715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1856496715
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.86038057
Short name T473
Test name
Test status
Simulation time 114980829 ps
CPU time 4.76 seconds
Started Jul 25 05:52:02 PM PDT 24
Finished Jul 25 05:52:07 PM PDT 24
Peak memory 210644 kb
Host smart-775679d0-5000-4424-98db-191fe1ea8637
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86038057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_ba
sh.86038057
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1220932964
Short name T404
Test name
Test status
Simulation time 139699765 ps
CPU time 8.31 seconds
Started Jul 25 05:51:58 PM PDT 24
Finished Jul 25 05:52:06 PM PDT 24
Peak memory 210624 kb
Host smart-417c37d0-2c12-4c30-a4c6-165477818152
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220932964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1220932964
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3659865080
Short name T386
Test name
Test status
Simulation time 1292877268 ps
CPU time 6.07 seconds
Started Jul 25 05:51:59 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 214780 kb
Host smart-cefb47ef-4398-4589-8fcf-2561bfb9e4a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659865080 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3659865080
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3253988304
Short name T66
Test name
Test status
Simulation time 501715400 ps
CPU time 5.1 seconds
Started Jul 25 05:51:57 PM PDT 24
Finished Jul 25 05:52:02 PM PDT 24
Peak memory 210572 kb
Host smart-48de1d44-27d4-4b43-9cdd-ae79da46368d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253988304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3253988304
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2204397269
Short name T405
Test name
Test status
Simulation time 346668821 ps
CPU time 4.24 seconds
Started Jul 25 05:52:00 PM PDT 24
Finished Jul 25 05:52:04 PM PDT 24
Peak memory 210444 kb
Host smart-64495b80-d57a-43e3-b2fd-6ff789ec37d6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204397269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2204397269
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4230357682
Short name T432
Test name
Test status
Simulation time 334465182 ps
CPU time 4.2 seconds
Started Jul 25 05:52:01 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 210468 kb
Host smart-323f0b87-b127-4a0c-a72e-4159428377f3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230357682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4230357682
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3094380087
Short name T470
Test name
Test status
Simulation time 369893678 ps
CPU time 18.56 seconds
Started Jul 25 05:51:59 PM PDT 24
Finished Jul 25 05:52:17 PM PDT 24
Peak memory 210632 kb
Host smart-32c60ec1-5402-4b8f-96a8-5becc42e5da3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094380087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3094380087
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2858671562
Short name T474
Test name
Test status
Simulation time 85757515 ps
CPU time 4.58 seconds
Started Jul 25 05:51:58 PM PDT 24
Finished Jul 25 05:52:03 PM PDT 24
Peak memory 210668 kb
Host smart-5c2feb85-de21-4e3a-b44f-1f4ba6ad93a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858671562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2858671562
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1895900104
Short name T458
Test name
Test status
Simulation time 172938104 ps
CPU time 11.07 seconds
Started Jul 25 05:51:58 PM PDT 24
Finished Jul 25 05:52:09 PM PDT 24
Peak memory 214416 kb
Host smart-e6d0cfc4-eac0-4156-852a-36afd868f3c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895900104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1895900104
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2040320326
Short name T416
Test name
Test status
Simulation time 1552906887 ps
CPU time 37.1 seconds
Started Jul 25 05:51:57 PM PDT 24
Finished Jul 25 05:52:34 PM PDT 24
Peak memory 211204 kb
Host smart-33a5dddf-98ad-4bd4-9007-31e4cb9c89f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040320326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2040320326
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2745523498
Short name T387
Test name
Test status
Simulation time 91182673 ps
CPU time 4.63 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:52:27 PM PDT 24
Peak memory 218868 kb
Host smart-3e9ed844-166b-49e6-a4d2-ed3f95f7594f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745523498 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2745523498
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.637743735
Short name T417
Test name
Test status
Simulation time 128172091 ps
CPU time 5.12 seconds
Started Jul 25 05:52:20 PM PDT 24
Finished Jul 25 05:52:25 PM PDT 24
Peak memory 217488 kb
Host smart-835d1dde-c7ef-4ce6-97d9-c78ced0fb0f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637743735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.637743735
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3586826909
Short name T437
Test name
Test status
Simulation time 2269441445 ps
CPU time 26.38 seconds
Started Jul 25 05:52:21 PM PDT 24
Finished Jul 25 05:52:48 PM PDT 24
Peak memory 210712 kb
Host smart-d11eb8aa-890d-42c9-9df6-e1a2dec78131
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586826909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3586826909
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3280843100
Short name T403
Test name
Test status
Simulation time 1036049663 ps
CPU time 7.53 seconds
Started Jul 25 05:52:23 PM PDT 24
Finished Jul 25 05:52:30 PM PDT 24
Peak memory 218856 kb
Host smart-33a0dcfb-c0b5-46cf-8b23-d79488a93e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280843100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3280843100
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2809454192
Short name T469
Test name
Test status
Simulation time 535661004 ps
CPU time 5.81 seconds
Started Jul 25 05:52:21 PM PDT 24
Finished Jul 25 05:52:27 PM PDT 24
Peak memory 218924 kb
Host smart-dfc37392-b1e2-44da-b69b-2b3fde247c36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809454192 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2809454192
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.376517320
Short name T442
Test name
Test status
Simulation time 958728027 ps
CPU time 4.91 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:52:27 PM PDT 24
Peak memory 210532 kb
Host smart-0d7e3544-545f-4250-b167-62af6e7553f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376517320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.376517320
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.604644453
Short name T105
Test name
Test status
Simulation time 527930419 ps
CPU time 22.49 seconds
Started Jul 25 05:52:25 PM PDT 24
Finished Jul 25 05:52:48 PM PDT 24
Peak memory 210744 kb
Host smart-0497133c-c497-457e-ba83-6720e678c89e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604644453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.604644453
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3062001295
Short name T64
Test name
Test status
Simulation time 263611170 ps
CPU time 6.98 seconds
Started Jul 25 05:52:20 PM PDT 24
Finished Jul 25 05:52:28 PM PDT 24
Peak memory 210852 kb
Host smart-6c4d4441-caa6-40ee-b7d1-3557a95d1c1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062001295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3062001295
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.298562472
Short name T381
Test name
Test status
Simulation time 854438886 ps
CPU time 7.12 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:52:30 PM PDT 24
Peak memory 218848 kb
Host smart-c7164be7-d97a-43b9-9372-65a94556fbfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298562472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.298562472
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1537982767
Short name T116
Test name
Test status
Simulation time 386332391 ps
CPU time 38.48 seconds
Started Jul 25 05:52:21 PM PDT 24
Finished Jul 25 05:53:00 PM PDT 24
Peak memory 218848 kb
Host smart-176590bf-10da-4f3f-8e99-64da592d40a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537982767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1537982767
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2311968035
Short name T439
Test name
Test status
Simulation time 359243746 ps
CPU time 4.86 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:52:27 PM PDT 24
Peak memory 218952 kb
Host smart-e6cc161c-1aef-4243-ac54-9c9ecdb20098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311968035 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2311968035
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3223293963
Short name T399
Test name
Test status
Simulation time 1378274398 ps
CPU time 5 seconds
Started Jul 25 05:52:38 PM PDT 24
Finished Jul 25 05:52:43 PM PDT 24
Peak memory 218760 kb
Host smart-7732bc53-f3db-4aab-b761-5041d89a4fa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223293963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3223293963
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2390350791
Short name T460
Test name
Test status
Simulation time 1502889165 ps
CPU time 21.98 seconds
Started Jul 25 05:52:23 PM PDT 24
Finished Jul 25 05:52:45 PM PDT 24
Peak memory 210688 kb
Host smart-d39b51bd-8858-4284-aabb-80409a238a6d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390350791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2390350791
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3053226007
Short name T406
Test name
Test status
Simulation time 1039151199 ps
CPU time 9.74 seconds
Started Jul 25 05:52:25 PM PDT 24
Finished Jul 25 05:52:35 PM PDT 24
Peak memory 210736 kb
Host smart-2d9b49f1-e10f-4dab-b1f7-b9a7e570912c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053226007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3053226007
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1104344620
Short name T383
Test name
Test status
Simulation time 1909952749 ps
CPU time 11.83 seconds
Started Jul 25 05:52:23 PM PDT 24
Finished Jul 25 05:52:35 PM PDT 24
Peak memory 218892 kb
Host smart-0143fd74-db4b-4da9-bb50-748d32c5a10a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104344620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1104344620
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2422780431
Short name T430
Test name
Test status
Simulation time 491744582 ps
CPU time 35.8 seconds
Started Jul 25 05:52:24 PM PDT 24
Finished Jul 25 05:53:00 PM PDT 24
Peak memory 211276 kb
Host smart-ddf7239c-be08-455e-a606-8ac6a382ffad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422780431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2422780431
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1430666887
Short name T464
Test name
Test status
Simulation time 148236285 ps
CPU time 5.96 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:52:29 PM PDT 24
Peak memory 218888 kb
Host smart-8e7ac27e-2b2e-4b8a-b77b-ba411bdcf378
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430666887 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1430666887
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.711006587
Short name T428
Test name
Test status
Simulation time 101809228 ps
CPU time 4.29 seconds
Started Jul 25 05:52:24 PM PDT 24
Finished Jul 25 05:52:28 PM PDT 24
Peak memory 217252 kb
Host smart-7ee4bd30-e345-4903-a2c2-3790cfb07fe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711006587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.711006587
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1389973370
Short name T84
Test name
Test status
Simulation time 1866543794 ps
CPU time 27.76 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:52:50 PM PDT 24
Peak memory 210644 kb
Host smart-d4050267-d5be-480e-a5cb-fe9927cdd7c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389973370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1389973370
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.784618806
Short name T99
Test name
Test status
Simulation time 380024023 ps
CPU time 5.94 seconds
Started Jul 25 05:52:24 PM PDT 24
Finished Jul 25 05:52:30 PM PDT 24
Peak memory 210888 kb
Host smart-293b3793-df9c-408d-829f-55cfafd649c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784618806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.784618806
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1820888190
Short name T391
Test name
Test status
Simulation time 657318060 ps
CPU time 10.23 seconds
Started Jul 25 05:52:23 PM PDT 24
Finished Jul 25 05:52:33 PM PDT 24
Peak memory 218892 kb
Host smart-3bcfc676-4561-4958-8a2a-ab2e9dd4b06f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820888190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1820888190
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3355573027
Short name T451
Test name
Test status
Simulation time 1183020430 ps
CPU time 5.55 seconds
Started Jul 25 05:52:25 PM PDT 24
Finished Jul 25 05:52:31 PM PDT 24
Peak memory 218808 kb
Host smart-9e8854eb-4cfd-44ec-ac39-1c7b36822ab3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355573027 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3355573027
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1696998837
Short name T465
Test name
Test status
Simulation time 132335034 ps
CPU time 5 seconds
Started Jul 25 05:52:26 PM PDT 24
Finished Jul 25 05:52:31 PM PDT 24
Peak memory 210592 kb
Host smart-be6a51e9-566c-464d-8306-88b3598303f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696998837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1696998837
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1711832478
Short name T69
Test name
Test status
Simulation time 13603382847 ps
CPU time 46.84 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:53:09 PM PDT 24
Peak memory 210800 kb
Host smart-0424d91f-3acf-4c0d-9ebb-3062773e9f1d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711832478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1711832478
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.586035412
Short name T444
Test name
Test status
Simulation time 441916760 ps
CPU time 5.31 seconds
Started Jul 25 05:52:23 PM PDT 24
Finished Jul 25 05:52:28 PM PDT 24
Peak memory 210660 kb
Host smart-1bd9d9bc-878d-4bbd-9d8c-4f6b4637a48b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586035412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.586035412
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2907896698
Short name T380
Test name
Test status
Simulation time 347275775 ps
CPU time 8.95 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:52:31 PM PDT 24
Peak memory 214884 kb
Host smart-4d669ce0-55ca-42c7-9a6e-876abc0b03f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907896698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2907896698
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.785619003
Short name T475
Test name
Test status
Simulation time 2291550445 ps
CPU time 37.87 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:53:00 PM PDT 24
Peak memory 218848 kb
Host smart-fafe308c-24bc-402b-b625-c0d589cada1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785619003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.785619003
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1977867278
Short name T434
Test name
Test status
Simulation time 140651789 ps
CPU time 6.7 seconds
Started Jul 25 05:52:39 PM PDT 24
Finished Jul 25 05:52:45 PM PDT 24
Peak memory 215848 kb
Host smart-eb6135d2-5b2b-4ce7-abe2-2f31722ccb6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977867278 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1977867278
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1985110229
Short name T441
Test name
Test status
Simulation time 173121090 ps
CPU time 4.27 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:41 PM PDT 24
Peak memory 210636 kb
Host smart-8b4bf3dc-e1fa-48aa-adb6-924b195d6faf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985110229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1985110229
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.423534362
Short name T88
Test name
Test status
Simulation time 1087626282 ps
CPU time 21.96 seconds
Started Jul 25 05:52:25 PM PDT 24
Finished Jul 25 05:52:47 PM PDT 24
Peak memory 210680 kb
Host smart-4668cd1d-5a5d-4582-a8e1-896105c4b991
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423534362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.423534362
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.524714352
Short name T448
Test name
Test status
Simulation time 349133279 ps
CPU time 4.3 seconds
Started Jul 25 05:52:35 PM PDT 24
Finished Jul 25 05:52:39 PM PDT 24
Peak memory 210576 kb
Host smart-b9d497dc-2be7-48d4-b92f-55a5be5b74b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524714352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.524714352
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3656804108
Short name T401
Test name
Test status
Simulation time 204183514 ps
CPU time 8.94 seconds
Started Jul 25 05:52:24 PM PDT 24
Finished Jul 25 05:52:33 PM PDT 24
Peak memory 216052 kb
Host smart-cf29f66f-5c93-44ad-a72d-0ac18c2baa05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656804108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3656804108
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.951849353
Short name T413
Test name
Test status
Simulation time 118456275 ps
CPU time 5.35 seconds
Started Jul 25 05:52:35 PM PDT 24
Finished Jul 25 05:52:41 PM PDT 24
Peak memory 215536 kb
Host smart-6345d688-6df5-4d36-ac19-d2ffba85b40f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951849353 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.951849353
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.975886318
Short name T87
Test name
Test status
Simulation time 252660617 ps
CPU time 5.1 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:42 PM PDT 24
Peak memory 218668 kb
Host smart-08f79b14-3744-43b9-ad72-1650a24465a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975886318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.975886318
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4042442143
Short name T104
Test name
Test status
Simulation time 2174751652 ps
CPU time 22 seconds
Started Jul 25 05:52:36 PM PDT 24
Finished Jul 25 05:52:58 PM PDT 24
Peak memory 210756 kb
Host smart-ae410545-e351-45f1-88f0-140c1cf5bb6c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042442143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4042442143
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2871437292
Short name T457
Test name
Test status
Simulation time 500021478 ps
CPU time 5.15 seconds
Started Jul 25 05:52:35 PM PDT 24
Finished Jul 25 05:52:41 PM PDT 24
Peak memory 210676 kb
Host smart-ef0eb918-0d62-447d-b37a-0e3d2dcda1e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871437292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2871437292
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3720410341
Short name T382
Test name
Test status
Simulation time 137487595 ps
CPU time 6.97 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:44 PM PDT 24
Peak memory 218828 kb
Host smart-181c1836-fbd3-4453-8b61-722273543931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720410341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3720410341
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1689704044
Short name T472
Test name
Test status
Simulation time 341658703 ps
CPU time 69.7 seconds
Started Jul 25 05:52:36 PM PDT 24
Finished Jul 25 05:53:46 PM PDT 24
Peak memory 212344 kb
Host smart-02d8c595-b9bd-41ee-834b-c5fc27813250
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689704044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1689704044
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.274189182
Short name T477
Test name
Test status
Simulation time 96981505 ps
CPU time 4.78 seconds
Started Jul 25 05:52:39 PM PDT 24
Finished Jul 25 05:52:44 PM PDT 24
Peak memory 214300 kb
Host smart-59dd268e-d52a-4e28-b0b1-a4e0f2136318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274189182 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.274189182
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3703211679
Short name T81
Test name
Test status
Simulation time 138445875 ps
CPU time 5.07 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:43 PM PDT 24
Peak memory 218780 kb
Host smart-293e2206-fac5-4a8c-ba51-b7935b9a27eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703211679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3703211679
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1213554130
Short name T98
Test name
Test status
Simulation time 466054077 ps
CPU time 5.15 seconds
Started Jul 25 05:52:38 PM PDT 24
Finished Jul 25 05:52:43 PM PDT 24
Peak memory 210708 kb
Host smart-83265978-ff03-45d0-9747-746f6b7e6948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213554130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1213554130
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.339127339
Short name T390
Test name
Test status
Simulation time 133641180 ps
CPU time 7.05 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:44 PM PDT 24
Peak memory 218892 kb
Host smart-56356fc2-9e35-40ba-8181-f22b60977431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339127339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.339127339
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3426895898
Short name T124
Test name
Test status
Simulation time 326466561 ps
CPU time 71.48 seconds
Started Jul 25 05:52:35 PM PDT 24
Finished Jul 25 05:53:47 PM PDT 24
Peak memory 212460 kb
Host smart-ab87a6d5-8c5f-4430-a9ee-df1f1db860ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426895898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3426895898
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.800316352
Short name T420
Test name
Test status
Simulation time 139425726 ps
CPU time 6.13 seconds
Started Jul 25 05:52:39 PM PDT 24
Finished Jul 25 05:52:45 PM PDT 24
Peak memory 216228 kb
Host smart-6f6bf828-93ad-42e4-8a31-b91d74d4503f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800316352 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.800316352
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2935126598
Short name T71
Test name
Test status
Simulation time 729098764 ps
CPU time 4.93 seconds
Started Jul 25 05:52:36 PM PDT 24
Finished Jul 25 05:52:41 PM PDT 24
Peak memory 210636 kb
Host smart-bea81dd6-7a18-4296-be45-8baba37227e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935126598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2935126598
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3626571682
Short name T86
Test name
Test status
Simulation time 538551618 ps
CPU time 22.19 seconds
Started Jul 25 05:52:38 PM PDT 24
Finished Jul 25 05:53:01 PM PDT 24
Peak memory 210688 kb
Host smart-9b9c76ed-2aec-4841-a57b-ec191bcb71a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626571682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3626571682
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1212833124
Short name T468
Test name
Test status
Simulation time 112561870 ps
CPU time 4.33 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:41 PM PDT 24
Peak memory 218232 kb
Host smart-4fc4230a-bd74-4c13-b5e7-2357335317a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212833124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1212833124
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.10364042
Short name T418
Test name
Test status
Simulation time 362320191 ps
CPU time 6.45 seconds
Started Jul 25 05:52:38 PM PDT 24
Finished Jul 25 05:52:45 PM PDT 24
Peak memory 215496 kb
Host smart-c0924a9a-d93c-477e-a8ca-0d7465883905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10364042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.10364042
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2003816105
Short name T118
Test name
Test status
Simulation time 275638594 ps
CPU time 69.11 seconds
Started Jul 25 05:52:35 PM PDT 24
Finished Jul 25 05:53:44 PM PDT 24
Peak memory 218824 kb
Host smart-dc172ce9-6c0b-4fd8-a866-eaa3cf4c34ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003816105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2003816105
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1288076206
Short name T463
Test name
Test status
Simulation time 100792791 ps
CPU time 5.56 seconds
Started Jul 25 05:52:35 PM PDT 24
Finished Jul 25 05:52:41 PM PDT 24
Peak memory 215964 kb
Host smart-2c427783-8f93-4334-82c2-d0e948db0621
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288076206 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1288076206
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1551840954
Short name T450
Test name
Test status
Simulation time 922465928 ps
CPU time 4.12 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:41 PM PDT 24
Peak memory 218772 kb
Host smart-00523ff4-d282-47d2-89bb-2aa5165aa437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551840954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1551840954
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4066552954
Short name T414
Test name
Test status
Simulation time 3847001300 ps
CPU time 28.05 seconds
Started Jul 25 05:52:34 PM PDT 24
Finished Jul 25 05:53:02 PM PDT 24
Peak memory 211192 kb
Host smart-6ef992ee-f993-4ac3-837a-2d9ca1d3ad23
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066552954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4066552954
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.704182403
Short name T97
Test name
Test status
Simulation time 728036801 ps
CPU time 5.14 seconds
Started Jul 25 05:52:38 PM PDT 24
Finished Jul 25 05:52:43 PM PDT 24
Peak memory 218836 kb
Host smart-49934efe-8c2a-4415-b536-78b01dcd1808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704182403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.704182403
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1590018227
Short name T384
Test name
Test status
Simulation time 170142408 ps
CPU time 10.89 seconds
Started Jul 25 05:52:36 PM PDT 24
Finished Jul 25 05:52:47 PM PDT 24
Peak memory 215868 kb
Host smart-387b1a8f-612c-4c1f-bdb2-3b29f91703b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590018227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1590018227
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.125926711
Short name T125
Test name
Test status
Simulation time 576449878 ps
CPU time 69.66 seconds
Started Jul 25 05:52:36 PM PDT 24
Finished Jul 25 05:53:46 PM PDT 24
Peak memory 212392 kb
Host smart-43427f3a-26a7-430e-ab47-658903d8a140
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125926711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.125926711
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.630943013
Short name T85
Test name
Test status
Simulation time 86413365 ps
CPU time 4.42 seconds
Started Jul 25 05:52:07 PM PDT 24
Finished Jul 25 05:52:11 PM PDT 24
Peak memory 210636 kb
Host smart-d233e785-d846-4bca-a22a-89dde37feba2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630943013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.630943013
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2901775652
Short name T103
Test name
Test status
Simulation time 130144793 ps
CPU time 5.11 seconds
Started Jul 25 05:52:06 PM PDT 24
Finished Jul 25 05:52:12 PM PDT 24
Peak memory 210636 kb
Host smart-a376a7a9-03f9-4089-b061-b89f9ce1158e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901775652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2901775652
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1461673419
Short name T454
Test name
Test status
Simulation time 132690194 ps
CPU time 8.15 seconds
Started Jul 25 05:52:10 PM PDT 24
Finished Jul 25 05:52:18 PM PDT 24
Peak memory 218792 kb
Host smart-893b33fb-2c37-4ad3-8e57-737c2be224e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461673419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1461673419
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3732188261
Short name T394
Test name
Test status
Simulation time 1451434654 ps
CPU time 4.38 seconds
Started Jul 25 05:52:07 PM PDT 24
Finished Jul 25 05:52:12 PM PDT 24
Peak memory 218824 kb
Host smart-83a78425-9aa7-4fcc-93d0-ad9468705874
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732188261 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3732188261
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1874170599
Short name T80
Test name
Test status
Simulation time 310048202 ps
CPU time 4.17 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 210572 kb
Host smart-0429bc9e-5d95-4e7e-9064-e6ea1b622190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874170599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1874170599
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4026909763
Short name T478
Test name
Test status
Simulation time 131305127 ps
CPU time 4.85 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 210496 kb
Host smart-0962b5f9-95c0-41b8-988e-a6eb114f3529
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026909763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4026909763
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4258153397
Short name T466
Test name
Test status
Simulation time 132855404 ps
CPU time 5.02 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 210404 kb
Host smart-8afba580-9025-4176-84c9-d782786cd131
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258153397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4258153397
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4038490706
Short name T397
Test name
Test status
Simulation time 1050249822 ps
CPU time 22.06 seconds
Started Jul 25 05:52:00 PM PDT 24
Finished Jul 25 05:52:22 PM PDT 24
Peak memory 210632 kb
Host smart-e45d8dd4-98d9-4c91-b692-f9c2999d07d0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038490706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4038490706
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3197457828
Short name T453
Test name
Test status
Simulation time 660652106 ps
CPU time 5.27 seconds
Started Jul 25 05:52:10 PM PDT 24
Finished Jul 25 05:52:15 PM PDT 24
Peak memory 210592 kb
Host smart-d6aa3bc9-8b04-4952-b31e-86473e1ca2e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197457828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3197457828
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2001914622
Short name T388
Test name
Test status
Simulation time 521814217 ps
CPU time 9.68 seconds
Started Jul 25 05:52:06 PM PDT 24
Finished Jul 25 05:52:16 PM PDT 24
Peak memory 215952 kb
Host smart-76aa9cbf-7610-4dbf-81b9-347ccb94a7be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001914622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2001914622
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1527480556
Short name T49
Test name
Test status
Simulation time 1264105982 ps
CPU time 39.36 seconds
Started Jul 25 05:52:11 PM PDT 24
Finished Jul 25 05:52:51 PM PDT 24
Peak memory 218852 kb
Host smart-e65a0fdf-0440-4532-995d-351e16133760
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527480556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1527480556
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2021667427
Short name T53
Test name
Test status
Simulation time 544027847 ps
CPU time 5 seconds
Started Jul 25 05:52:13 PM PDT 24
Finished Jul 25 05:52:18 PM PDT 24
Peak memory 210632 kb
Host smart-5e19399b-4d9f-4165-9177-5d506d1f3a39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021667427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2021667427
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3493875330
Short name T467
Test name
Test status
Simulation time 268886306 ps
CPU time 5.27 seconds
Started Jul 25 05:52:10 PM PDT 24
Finished Jul 25 05:52:16 PM PDT 24
Peak memory 218788 kb
Host smart-80782675-35f4-4e2b-b568-a21b4b66789b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493875330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3493875330
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1277905068
Short name T411
Test name
Test status
Simulation time 135629267 ps
CPU time 8.11 seconds
Started Jul 25 05:52:13 PM PDT 24
Finished Jul 25 05:52:21 PM PDT 24
Peak memory 218616 kb
Host smart-e996643f-8e2f-448a-95fe-bb31602f86dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277905068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1277905068
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2495144485
Short name T426
Test name
Test status
Simulation time 106056671 ps
CPU time 6.57 seconds
Started Jul 25 05:52:07 PM PDT 24
Finished Jul 25 05:52:14 PM PDT 24
Peak memory 216272 kb
Host smart-b4eaa609-e130-465b-8cf7-d6218e49bb51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495144485 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2495144485
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2755290566
Short name T65
Test name
Test status
Simulation time 131887613 ps
CPU time 5.12 seconds
Started Jul 25 05:52:09 PM PDT 24
Finished Jul 25 05:52:14 PM PDT 24
Peak memory 210560 kb
Host smart-38f1d545-49d3-4224-8769-607bde9c214f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755290566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2755290566
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1895377162
Short name T476
Test name
Test status
Simulation time 140179068 ps
CPU time 5.15 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 210476 kb
Host smart-e8521c2d-1e2b-4a3d-bfb9-d722772d6840
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895377162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1895377162
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2539911581
Short name T423
Test name
Test status
Simulation time 129694809 ps
CPU time 4.91 seconds
Started Jul 25 05:52:10 PM PDT 24
Finished Jul 25 05:52:15 PM PDT 24
Peak memory 210480 kb
Host smart-6fa7d539-e937-4cea-a8b7-d888ff0f9f27
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539911581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2539911581
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4146412515
Short name T435
Test name
Test status
Simulation time 818191015 ps
CPU time 32.06 seconds
Started Jul 25 05:52:13 PM PDT 24
Finished Jul 25 05:52:45 PM PDT 24
Peak memory 210588 kb
Host smart-17bf4045-2cdf-4727-adac-405e1253d203
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146412515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.4146412515
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2401409203
Short name T438
Test name
Test status
Simulation time 1518602308 ps
CPU time 6.2 seconds
Started Jul 25 05:52:06 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 210696 kb
Host smart-346d8745-8535-474d-9406-33352f759ec0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401409203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2401409203
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1719741782
Short name T421
Test name
Test status
Simulation time 503500815 ps
CPU time 9.6 seconds
Started Jul 25 05:52:10 PM PDT 24
Finished Jul 25 05:52:20 PM PDT 24
Peak memory 218908 kb
Host smart-e5b871fa-71e1-4a20-b63d-0c1d612832c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719741782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1719741782
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3866380778
Short name T427
Test name
Test status
Simulation time 127798549 ps
CPU time 5.07 seconds
Started Jul 25 05:52:09 PM PDT 24
Finished Jul 25 05:52:14 PM PDT 24
Peak memory 210492 kb
Host smart-fb59a509-38e7-497b-8236-faae7e6469b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866380778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3866380778
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2729001023
Short name T452
Test name
Test status
Simulation time 2464748772 ps
CPU time 5.37 seconds
Started Jul 25 05:52:09 PM PDT 24
Finished Jul 25 05:52:14 PM PDT 24
Peak memory 218852 kb
Host smart-b68a1e89-73fb-47d3-a903-82d4ebc1449a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729001023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2729001023
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2392161151
Short name T407
Test name
Test status
Simulation time 543803814 ps
CPU time 8.23 seconds
Started Jul 25 05:52:11 PM PDT 24
Finished Jul 25 05:52:20 PM PDT 24
Peak memory 210524 kb
Host smart-5a470549-5c5d-40fc-bbbf-b716e485a44d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392161151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2392161151
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3896948450
Short name T425
Test name
Test status
Simulation time 1612150823 ps
CPU time 6.12 seconds
Started Jul 25 05:52:06 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 218916 kb
Host smart-3f005f01-8a8b-47a1-abf8-f74ab8d6e4bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896948450 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3896948450
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3912025967
Short name T82
Test name
Test status
Simulation time 515476056 ps
CPU time 4.86 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 210560 kb
Host smart-18588421-8e92-4a4b-9c5d-56683171d910
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912025967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3912025967
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1077750542
Short name T408
Test name
Test status
Simulation time 261175579 ps
CPU time 5.01 seconds
Started Jul 25 05:52:05 PM PDT 24
Finished Jul 25 05:52:11 PM PDT 24
Peak memory 210408 kb
Host smart-bbe55142-16ab-4e18-8081-687fab0d24da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077750542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1077750542
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3168663595
Short name T429
Test name
Test status
Simulation time 348099017 ps
CPU time 4.08 seconds
Started Jul 25 05:52:11 PM PDT 24
Finished Jul 25 05:52:15 PM PDT 24
Peak memory 210452 kb
Host smart-6d06ebea-cd64-44d2-ad76-b3e9785897ea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168663595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3168663595
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1317124652
Short name T461
Test name
Test status
Simulation time 1483253928 ps
CPU time 18.1 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:27 PM PDT 24
Peak memory 210728 kb
Host smart-bc2908ae-fb75-4d4c-9c71-ebe9b3972aef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317124652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1317124652
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.365189014
Short name T447
Test name
Test status
Simulation time 136397329 ps
CPU time 6.88 seconds
Started Jul 25 05:52:09 PM PDT 24
Finished Jul 25 05:52:16 PM PDT 24
Peak memory 210940 kb
Host smart-b7206f9e-3f3a-43c0-ac89-b9af4ef16635
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365189014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.365189014
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.154452172
Short name T415
Test name
Test status
Simulation time 1240539489 ps
CPU time 7.78 seconds
Started Jul 25 05:52:10 PM PDT 24
Finished Jul 25 05:52:18 PM PDT 24
Peak memory 215624 kb
Host smart-588fe901-35da-4eb7-b069-ee53a444d623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154452172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.154452172
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.104311062
Short name T123
Test name
Test status
Simulation time 419256078 ps
CPU time 37.81 seconds
Started Jul 25 05:52:10 PM PDT 24
Finished Jul 25 05:52:48 PM PDT 24
Peak memory 212352 kb
Host smart-e6e8fb5b-b98d-41fb-a4aa-6145d07f77c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104311062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.104311062
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.749685656
Short name T455
Test name
Test status
Simulation time 298352876 ps
CPU time 6.31 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:15 PM PDT 24
Peak memory 215652 kb
Host smart-21459be9-d928-4124-a582-1a8d1a2af9c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749685656 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.749685656
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.329049731
Short name T100
Test name
Test status
Simulation time 399867855 ps
CPU time 4.2 seconds
Started Jul 25 05:52:07 PM PDT 24
Finished Jul 25 05:52:12 PM PDT 24
Peak memory 217932 kb
Host smart-19b2d5e7-a6b6-4406-890d-fec008d804d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329049731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.329049731
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4091338116
Short name T90
Test name
Test status
Simulation time 2183794180 ps
CPU time 22.07 seconds
Started Jul 25 05:52:07 PM PDT 24
Finished Jul 25 05:52:29 PM PDT 24
Peak memory 210656 kb
Host smart-68cb50f3-68d2-4713-a4ee-6e90a6b3a505
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091338116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4091338116
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2406746554
Short name T449
Test name
Test status
Simulation time 87609738 ps
CPU time 4.52 seconds
Started Jul 25 05:52:12 PM PDT 24
Finished Jul 25 05:52:17 PM PDT 24
Peak memory 210728 kb
Host smart-4efc54de-3632-43b5-9719-bb514b6f3691
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406746554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2406746554
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2876590539
Short name T389
Test name
Test status
Simulation time 561513049 ps
CPU time 7.29 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:16 PM PDT 24
Peak memory 218880 kb
Host smart-dabaf11a-438b-4591-b4d5-0a8ccae855ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876590539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2876590539
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2696132925
Short name T119
Test name
Test status
Simulation time 231099615 ps
CPU time 38.06 seconds
Started Jul 25 05:52:13 PM PDT 24
Finished Jul 25 05:52:51 PM PDT 24
Peak memory 213476 kb
Host smart-151844a2-7eab-435f-80f4-0618f319d04b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696132925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2696132925
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1158593612
Short name T440
Test name
Test status
Simulation time 1867305520 ps
CPU time 7.8 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:16 PM PDT 24
Peak memory 213764 kb
Host smart-54b8f30d-3d88-4663-b7e6-788daa3de517
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158593612 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1158593612
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1718598328
Short name T431
Test name
Test status
Simulation time 135364413 ps
CPU time 4.99 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 210480 kb
Host smart-662ab241-341a-4e73-a6a2-563178acc044
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718598328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1718598328
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3056413730
Short name T393
Test name
Test status
Simulation time 376589311 ps
CPU time 18.36 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:26 PM PDT 24
Peak memory 210740 kb
Host smart-918d6936-e287-4070-a3bd-accb802fcd58
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056413730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3056413730
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3508321254
Short name T409
Test name
Test status
Simulation time 842970612 ps
CPU time 8.94 seconds
Started Jul 25 05:52:09 PM PDT 24
Finished Jul 25 05:52:18 PM PDT 24
Peak memory 210748 kb
Host smart-84128d9f-16c4-42e0-aa9a-46f2c942bf0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508321254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3508321254
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3767155591
Short name T396
Test name
Test status
Simulation time 511782278 ps
CPU time 13.14 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:21 PM PDT 24
Peak memory 218836 kb
Host smart-ca380b53-be02-4ae9-8b10-2a9a09cf20db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767155591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3767155591
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3636984950
Short name T433
Test name
Test status
Simulation time 216122294 ps
CPU time 67.61 seconds
Started Jul 25 05:52:09 PM PDT 24
Finished Jul 25 05:53:17 PM PDT 24
Peak memory 218848 kb
Host smart-8c174c0e-94de-4dfe-b7e2-4839aff4c693
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636984950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3636984950
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1244441231
Short name T445
Test name
Test status
Simulation time 1021178438 ps
CPU time 5.32 seconds
Started Jul 25 05:52:24 PM PDT 24
Finished Jul 25 05:52:30 PM PDT 24
Peak memory 218948 kb
Host smart-d8ef5bab-4054-404e-ab05-7e1e74e4bb90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244441231 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1244441231
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.747961842
Short name T106
Test name
Test status
Simulation time 522565974 ps
CPU time 5.12 seconds
Started Jul 25 05:52:24 PM PDT 24
Finished Jul 25 05:52:29 PM PDT 24
Peak memory 218724 kb
Host smart-a2604347-b83b-4751-98b1-479818a82206
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747961842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.747961842
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4114213487
Short name T79
Test name
Test status
Simulation time 365178495 ps
CPU time 18.71 seconds
Started Jul 25 05:52:10 PM PDT 24
Finished Jul 25 05:52:29 PM PDT 24
Peak memory 210740 kb
Host smart-8667cd95-d53e-49c7-9eeb-e774d12147d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114213487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.4114213487
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3561923673
Short name T462
Test name
Test status
Simulation time 130787908 ps
CPU time 6.79 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:52:29 PM PDT 24
Peak memory 210908 kb
Host smart-ec93780c-b012-450f-8023-b59336a459c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561923673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3561923673
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1964415428
Short name T400
Test name
Test status
Simulation time 378470826 ps
CPU time 7.5 seconds
Started Jul 25 05:52:08 PM PDT 24
Finished Jul 25 05:52:16 PM PDT 24
Peak memory 218888 kb
Host smart-c875dc8e-33a7-418b-95ad-c25d7d0726c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964415428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1964415428
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3417873953
Short name T127
Test name
Test status
Simulation time 394907690 ps
CPU time 37.15 seconds
Started Jul 25 05:52:24 PM PDT 24
Finished Jul 25 05:53:01 PM PDT 24
Peak memory 211340 kb
Host smart-94f0fbb8-3561-4fd9-adac-0fdb8fb80a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417873953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3417873953
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4140159109
Short name T398
Test name
Test status
Simulation time 93137281 ps
CPU time 4.61 seconds
Started Jul 25 05:52:23 PM PDT 24
Finished Jul 25 05:52:28 PM PDT 24
Peak memory 218844 kb
Host smart-1d58e866-3455-4cbb-aac6-5be3eb39afbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140159109 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4140159109
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4098300776
Short name T471
Test name
Test status
Simulation time 161766061 ps
CPU time 4.1 seconds
Started Jul 25 05:52:20 PM PDT 24
Finished Jul 25 05:52:24 PM PDT 24
Peak memory 218792 kb
Host smart-6bc1afc7-812f-4f18-8158-0dacbd533d78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098300776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4098300776
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3955698849
Short name T424
Test name
Test status
Simulation time 1643612131 ps
CPU time 18.85 seconds
Started Jul 25 05:52:21 PM PDT 24
Finished Jul 25 05:52:40 PM PDT 24
Peak memory 210740 kb
Host smart-6d682a21-bf09-4292-b2fd-e319316a3e1c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955698849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3955698849
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1735994919
Short name T456
Test name
Test status
Simulation time 168113932 ps
CPU time 4.29 seconds
Started Jul 25 05:52:26 PM PDT 24
Finished Jul 25 05:52:30 PM PDT 24
Peak memory 218264 kb
Host smart-8841f646-86e0-48f5-95d9-87fff2625e8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735994919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1735994919
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2472017964
Short name T410
Test name
Test status
Simulation time 145360584 ps
CPU time 6.98 seconds
Started Jul 25 05:52:23 PM PDT 24
Finished Jul 25 05:52:30 PM PDT 24
Peak memory 214396 kb
Host smart-e0fb8f15-0e3b-4431-b7db-11e72900b0fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472017964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2472017964
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2276391007
Short name T122
Test name
Test status
Simulation time 232764807 ps
CPU time 67.99 seconds
Started Jul 25 05:52:21 PM PDT 24
Finished Jul 25 05:53:30 PM PDT 24
Peak memory 212524 kb
Host smart-07cbba43-7f39-486e-b28d-c95a55dd2ef5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276391007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2276391007
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3060353402
Short name T385
Test name
Test status
Simulation time 115324029 ps
CPU time 4.91 seconds
Started Jul 25 05:52:25 PM PDT 24
Finished Jul 25 05:52:30 PM PDT 24
Peak memory 215352 kb
Host smart-eda6fbe6-8e1e-4f0e-bd39-aede95494bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060353402 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3060353402
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2497160582
Short name T83
Test name
Test status
Simulation time 263237173 ps
CPU time 5.15 seconds
Started Jul 25 05:52:21 PM PDT 24
Finished Jul 25 05:52:27 PM PDT 24
Peak memory 210572 kb
Host smart-9e718fbf-888b-473a-8476-83aaa7da633e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497160582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2497160582
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1147020768
Short name T392
Test name
Test status
Simulation time 533406952 ps
CPU time 22.46 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:52:45 PM PDT 24
Peak memory 210632 kb
Host smart-5999524b-11ed-4600-bf19-a63e214eaf98
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147020768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1147020768
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2858562638
Short name T70
Test name
Test status
Simulation time 540028096 ps
CPU time 6.76 seconds
Started Jul 25 05:52:23 PM PDT 24
Finished Jul 25 05:52:30 PM PDT 24
Peak memory 211028 kb
Host smart-caddddce-9721-4375-8e31-68c221a0dbc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858562638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2858562638
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.189897156
Short name T443
Test name
Test status
Simulation time 88767170 ps
CPU time 6.87 seconds
Started Jul 25 05:52:22 PM PDT 24
Finished Jul 25 05:52:29 PM PDT 24
Peak memory 215612 kb
Host smart-0059369f-ea58-4575-a6b4-bebc8efe5b29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189897156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.189897156
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.516710408
Short name T121
Test name
Test status
Simulation time 312988444 ps
CPU time 71.01 seconds
Started Jul 25 05:52:24 PM PDT 24
Finished Jul 25 05:53:35 PM PDT 24
Peak memory 213368 kb
Host smart-7a837451-bbbb-4c5a-96d8-8ca9255a1016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516710408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.516710408
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2733867761
Short name T176
Test name
Test status
Simulation time 336007438 ps
CPU time 4.35 seconds
Started Jul 25 05:52:40 PM PDT 24
Finished Jul 25 05:52:45 PM PDT 24
Peak memory 211792 kb
Host smart-c5acca80-088b-4d28-a23e-d56ee0a87a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733867761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2733867761
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1505693869
Short name T351
Test name
Test status
Simulation time 482139470 ps
CPU time 11.83 seconds
Started Jul 25 05:52:40 PM PDT 24
Finished Jul 25 05:52:51 PM PDT 24
Peak memory 212652 kb
Host smart-a5e5c63b-350a-4124-9631-74b2c06335c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505693869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1505693869
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.422163411
Short name T94
Test name
Test status
Simulation time 398961702 ps
CPU time 5.73 seconds
Started Jul 25 05:52:39 PM PDT 24
Finished Jul 25 05:52:44 PM PDT 24
Peak memory 211908 kb
Host smart-692f1ba2-c2b8-4ba7-90d1-33962ba835a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422163411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.422163411
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3173838787
Short name T22
Test name
Test status
Simulation time 307637956 ps
CPU time 102.7 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:54:20 PM PDT 24
Peak memory 237148 kb
Host smart-9b4612ec-00d6-427e-8a4c-48155a81d1a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173838787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3173838787
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.760899026
Short name T331
Test name
Test status
Simulation time 721101188 ps
CPU time 9.87 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:47 PM PDT 24
Peak memory 212724 kb
Host smart-88b24931-bb74-4c29-a249-d19e122b967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760899026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.760899026
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3400995831
Short name T238
Test name
Test status
Simulation time 407026900 ps
CPU time 8.37 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:46 PM PDT 24
Peak memory 211812 kb
Host smart-02003131-20c1-44fa-a741-7695652644c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400995831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3400995831
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3265412786
Short name T217
Test name
Test status
Simulation time 249849995 ps
CPU time 5.22 seconds
Started Jul 25 05:52:38 PM PDT 24
Finished Jul 25 05:52:43 PM PDT 24
Peak memory 211804 kb
Host smart-a443f316-00b8-4c98-bbb2-ce03a70609d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265412786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3265412786
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3116290011
Short name T267
Test name
Test status
Simulation time 8494767211 ps
CPU time 146.82 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:55:04 PM PDT 24
Peak memory 239332 kb
Host smart-0cae805b-690b-43b2-876a-9e95b0a36776
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116290011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3116290011
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3235128395
Short name T191
Test name
Test status
Simulation time 729349806 ps
CPU time 9.69 seconds
Started Jul 25 05:52:40 PM PDT 24
Finished Jul 25 05:52:50 PM PDT 24
Peak memory 212604 kb
Host smart-bf486b6a-499c-4fdd-92cb-80e50c107add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235128395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3235128395
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2067626257
Short name T289
Test name
Test status
Simulation time 19692960193 ps
CPU time 16.79 seconds
Started Jul 25 05:52:39 PM PDT 24
Finished Jul 25 05:52:56 PM PDT 24
Peak memory 214752 kb
Host smart-d3854096-bfef-470d-a5aa-3f24b92f8862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067626257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2067626257
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1621063133
Short name T374
Test name
Test status
Simulation time 805459463 ps
CPU time 18.93 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:56 PM PDT 24
Peak memory 216336 kb
Host smart-52e40c69-c270-405e-a3ca-4d50d7dd4c38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621063133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1621063133
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.765520466
Short name T193
Test name
Test status
Simulation time 733204294 ps
CPU time 4.99 seconds
Started Jul 25 05:52:59 PM PDT 24
Finished Jul 25 05:53:04 PM PDT 24
Peak memory 211828 kb
Host smart-a24593f2-b01e-4a10-9fc9-145394146d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765520466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.765520466
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1023549538
Short name T353
Test name
Test status
Simulation time 1225761510 ps
CPU time 71.58 seconds
Started Jul 25 05:52:50 PM PDT 24
Finished Jul 25 05:54:02 PM PDT 24
Peak memory 213044 kb
Host smart-5635ebe9-dae9-4040-bb92-104b78f0284f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023549538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1023549538
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.297809831
Short name T296
Test name
Test status
Simulation time 542312455 ps
CPU time 11.37 seconds
Started Jul 25 05:52:59 PM PDT 24
Finished Jul 25 05:53:10 PM PDT 24
Peak memory 212700 kb
Host smart-e2af3410-afd9-46a3-910c-65585e0aeb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297809831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.297809831
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2119850346
Short name T169
Test name
Test status
Simulation time 602859131 ps
CPU time 6.81 seconds
Started Jul 25 05:52:49 PM PDT 24
Finished Jul 25 05:52:55 PM PDT 24
Peak memory 211928 kb
Host smart-618b6ffb-8687-4d6b-8426-9a1c6dbc2089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119850346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2119850346
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.303707489
Short name T341
Test name
Test status
Simulation time 1319327072 ps
CPU time 11.92 seconds
Started Jul 25 05:52:51 PM PDT 24
Finished Jul 25 05:53:03 PM PDT 24
Peak memory 214548 kb
Host smart-f893af0d-1947-40da-83d1-d899455db88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303707489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.303707489
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.482545449
Short name T203
Test name
Test status
Simulation time 783353168 ps
CPU time 35.53 seconds
Started Jul 25 05:52:52 PM PDT 24
Finished Jul 25 05:53:27 PM PDT 24
Peak memory 216364 kb
Host smart-af14b100-5554-4475-83c3-5fd18afe1383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482545449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.482545449
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3986121819
Short name T140
Test name
Test status
Simulation time 250342709 ps
CPU time 5.16 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:03 PM PDT 24
Peak memory 211784 kb
Host smart-b068d820-da8e-4334-9c99-157fc62904e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986121819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3986121819
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.800650731
Short name T162
Test name
Test status
Simulation time 12269740475 ps
CPU time 131.61 seconds
Started Jul 25 05:52:55 PM PDT 24
Finished Jul 25 05:55:07 PM PDT 24
Peak memory 238296 kb
Host smart-5f8161e7-968d-4e95-9f21-31860b74d354
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800650731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.800650731
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4228509406
Short name T271
Test name
Test status
Simulation time 335972903 ps
CPU time 9.68 seconds
Started Jul 25 05:52:56 PM PDT 24
Finished Jul 25 05:53:06 PM PDT 24
Peak memory 212620 kb
Host smart-bdeda2cc-a849-4d14-9149-eb82663c319d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228509406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4228509406
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2075904556
Short name T236
Test name
Test status
Simulation time 141926205 ps
CPU time 6.8 seconds
Started Jul 25 05:52:57 PM PDT 24
Finished Jul 25 05:53:04 PM PDT 24
Peak memory 211900 kb
Host smart-0a4a0de1-0b68-4795-a381-5c3277a9c445
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075904556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2075904556
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.368380940
Short name T204
Test name
Test status
Simulation time 538299515 ps
CPU time 11.84 seconds
Started Jul 25 05:53:04 PM PDT 24
Finished Jul 25 05:53:16 PM PDT 24
Peak memory 214584 kb
Host smart-a0f380a4-edd4-46d7-a36d-98c53a458b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368380940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.368380940
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1418747293
Short name T273
Test name
Test status
Simulation time 281880946 ps
CPU time 18.12 seconds
Started Jul 25 05:52:57 PM PDT 24
Finished Jul 25 05:53:15 PM PDT 24
Peak memory 214156 kb
Host smart-11d4aec4-7588-4d06-9b5e-1a01d8935981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418747293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1418747293
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1167012934
Short name T156
Test name
Test status
Simulation time 273315483 ps
CPU time 5 seconds
Started Jul 25 05:53:03 PM PDT 24
Finished Jul 25 05:53:09 PM PDT 24
Peak memory 211812 kb
Host smart-08e55bbf-0dee-4c69-b203-ecc4426ca32c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167012934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1167012934
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.740729634
Short name T329
Test name
Test status
Simulation time 58021890196 ps
CPU time 172.18 seconds
Started Jul 25 05:52:59 PM PDT 24
Finished Jul 25 05:55:51 PM PDT 24
Peak memory 234368 kb
Host smart-ff119bab-ff60-4ad0-9af0-6028b0479c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740729634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.740729634
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1011904868
Short name T208
Test name
Test status
Simulation time 253225183 ps
CPU time 11.06 seconds
Started Jul 25 05:53:03 PM PDT 24
Finished Jul 25 05:53:15 PM PDT 24
Peak memory 212588 kb
Host smart-8ae218b8-ce1a-429b-aaeb-aa9115943838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011904868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1011904868
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.884806888
Short name T269
Test name
Test status
Simulation time 617839168 ps
CPU time 6.93 seconds
Started Jul 25 05:52:57 PM PDT 24
Finished Jul 25 05:53:04 PM PDT 24
Peak memory 211992 kb
Host smart-5686a7ea-716e-4042-8d08-99374d88e81b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884806888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.884806888
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.984953574
Short name T175
Test name
Test status
Simulation time 301440636 ps
CPU time 17.71 seconds
Started Jul 25 05:52:56 PM PDT 24
Finished Jul 25 05:53:14 PM PDT 24
Peak memory 213736 kb
Host smart-de473f87-ea4d-40f5-8609-d25a705be6a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984953574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.984953574
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3714936979
Short name T54
Test name
Test status
Simulation time 167946207 ps
CPU time 4.38 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:03 PM PDT 24
Peak memory 211756 kb
Host smart-7f2c653c-844f-42be-8c4d-9c17564245a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714936979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3714936979
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3401996387
Short name T276
Test name
Test status
Simulation time 6731296145 ps
CPU time 111.7 seconds
Started Jul 25 05:52:57 PM PDT 24
Finished Jul 25 05:54:48 PM PDT 24
Peak memory 214156 kb
Host smart-bf17af2f-a29c-4566-b2b0-111afdebb8f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401996387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3401996387
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4280883038
Short name T101
Test name
Test status
Simulation time 100121467 ps
CPU time 5.65 seconds
Started Jul 25 05:53:00 PM PDT 24
Finished Jul 25 05:53:06 PM PDT 24
Peak memory 212004 kb
Host smart-e2b1d1c0-e294-4824-96c2-51c3a6410839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280883038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4280883038
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.564436952
Short name T148
Test name
Test status
Simulation time 553813951 ps
CPU time 12.05 seconds
Started Jul 25 05:52:55 PM PDT 24
Finished Jul 25 05:53:07 PM PDT 24
Peak memory 214284 kb
Host smart-2d3ef493-cc06-4f86-869d-7426dbc51d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564436952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.564436952
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2056315705
Short name T309
Test name
Test status
Simulation time 692505380 ps
CPU time 20.61 seconds
Started Jul 25 05:53:05 PM PDT 24
Finished Jul 25 05:53:25 PM PDT 24
Peak memory 215080 kb
Host smart-6adb7526-81ca-4298-8ae9-a4c9cfabdb9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056315705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2056315705
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3126785999
Short name T181
Test name
Test status
Simulation time 170423405500 ps
CPU time 841.6 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 06:07:00 PM PDT 24
Peak memory 231304 kb
Host smart-4aa90db3-3be7-4f68-8e3b-3310dba36f4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126785999 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3126785999
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3771105653
Short name T142
Test name
Test status
Simulation time 568573894 ps
CPU time 4.83 seconds
Started Jul 25 05:53:09 PM PDT 24
Finished Jul 25 05:53:14 PM PDT 24
Peak memory 211664 kb
Host smart-8dd9179c-2784-457f-b351-62a9976be319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771105653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3771105653
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2892281591
Short name T221
Test name
Test status
Simulation time 8743788939 ps
CPU time 139.33 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:55:18 PM PDT 24
Peak memory 238880 kb
Host smart-81b67d56-ea9c-46df-83ca-d29f2e514e95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892281591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2892281591
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4242219953
Short name T366
Test name
Test status
Simulation time 340803223 ps
CPU time 9.51 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:08 PM PDT 24
Peak memory 212664 kb
Host smart-c049acbd-ddd8-49a7-9487-b4a2d0ba31a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242219953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4242219953
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1876434176
Short name T367
Test name
Test status
Simulation time 278016569 ps
CPU time 6.58 seconds
Started Jul 25 05:52:57 PM PDT 24
Finished Jul 25 05:53:04 PM PDT 24
Peak memory 211876 kb
Host smart-f7a566eb-c4d3-42a3-bf6a-45ac06d751f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876434176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1876434176
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.667014315
Short name T375
Test name
Test status
Simulation time 1109053484 ps
CPU time 11.93 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:10 PM PDT 24
Peak memory 214636 kb
Host smart-0e2d2d93-85be-4dfd-8d60-673a20acc72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667014315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.667014315
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.452943762
Short name T372
Test name
Test status
Simulation time 479140795 ps
CPU time 7.55 seconds
Started Jul 25 05:53:04 PM PDT 24
Finished Jul 25 05:53:12 PM PDT 24
Peak memory 211864 kb
Host smart-a3c13d8c-facd-48d5-afca-af99681ac0d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452943762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.452943762
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1563021198
Short name T245
Test name
Test status
Simulation time 132412134 ps
CPU time 4.9 seconds
Started Jul 25 05:53:09 PM PDT 24
Finished Jul 25 05:53:14 PM PDT 24
Peak memory 211684 kb
Host smart-74dd1260-1c08-4ca2-9321-14be9aac204a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563021198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1563021198
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.797534678
Short name T266
Test name
Test status
Simulation time 9348474878 ps
CPU time 190.01 seconds
Started Jul 25 05:53:00 PM PDT 24
Finished Jul 25 05:56:11 PM PDT 24
Peak memory 226196 kb
Host smart-d7949a26-d86f-412b-a4fc-18c065c6ef88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797534678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.797534678
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.775526102
Short name T137
Test name
Test status
Simulation time 251129714 ps
CPU time 11.43 seconds
Started Jul 25 05:52:57 PM PDT 24
Finished Jul 25 05:53:09 PM PDT 24
Peak memory 212916 kb
Host smart-5c88da48-699b-45a2-b6d1-95a36c84bf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775526102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.775526102
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.824077290
Short name T225
Test name
Test status
Simulation time 991940753 ps
CPU time 5.4 seconds
Started Jul 25 05:53:01 PM PDT 24
Finished Jul 25 05:53:06 PM PDT 24
Peak memory 212016 kb
Host smart-a656e20b-80a9-415c-9ebb-310c0049a6c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824077290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.824077290
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.730599975
Short name T199
Test name
Test status
Simulation time 699998146 ps
CPU time 10.34 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:53:53 PM PDT 24
Peak memory 214224 kb
Host smart-d7890e08-a6e3-4fb7-90a9-03844ac4172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730599975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.730599975
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1836873979
Short name T257
Test name
Test status
Simulation time 1592475538 ps
CPU time 36.83 seconds
Started Jul 25 05:52:57 PM PDT 24
Finished Jul 25 05:53:34 PM PDT 24
Peak memory 215544 kb
Host smart-751cc0ca-d7a6-4435-8a3d-3b63611f9919
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836873979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1836873979
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3433733673
Short name T45
Test name
Test status
Simulation time 13843990285 ps
CPU time 4164.58 seconds
Started Jul 25 05:53:04 PM PDT 24
Finished Jul 25 07:02:29 PM PDT 24
Peak memory 233536 kb
Host smart-7ddc87ba-8afa-4c1e-9177-7a81d300f10e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433733673 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3433733673
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4072633333
Short name T200
Test name
Test status
Simulation time 300036390 ps
CPU time 4.23 seconds
Started Jul 25 05:53:05 PM PDT 24
Finished Jul 25 05:53:09 PM PDT 24
Peak memory 211720 kb
Host smart-52588523-e814-4d53-a85a-a2f4a4294413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072633333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4072633333
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4013166600
Short name T256
Test name
Test status
Simulation time 7218709464 ps
CPU time 87.46 seconds
Started Jul 25 05:52:57 PM PDT 24
Finished Jul 25 05:54:25 PM PDT 24
Peak memory 239000 kb
Host smart-20b49e05-c526-45d1-a782-a36c3be464a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013166600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4013166600
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2867262655
Short name T255
Test name
Test status
Simulation time 340594062 ps
CPU time 9.25 seconds
Started Jul 25 05:53:09 PM PDT 24
Finished Jul 25 05:53:18 PM PDT 24
Peak memory 211964 kb
Host smart-ddfabe14-5a2b-4f2d-8847-67652bf3e237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867262655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2867262655
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.829980307
Short name T59
Test name
Test status
Simulation time 197314180 ps
CPU time 5.67 seconds
Started Jul 25 05:52:56 PM PDT 24
Finished Jul 25 05:53:02 PM PDT 24
Peak memory 211916 kb
Host smart-9ada4fba-c2d8-4cbe-8558-e901d2e39252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829980307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.829980307
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3649656135
Short name T213
Test name
Test status
Simulation time 392684635 ps
CPU time 11.74 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:10 PM PDT 24
Peak memory 214200 kb
Host smart-0767ba3c-0c45-43b4-9b2c-1357f5b99dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649656135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3649656135
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3937031801
Short name T30
Test name
Test status
Simulation time 605634679 ps
CPU time 10.87 seconds
Started Jul 25 05:53:09 PM PDT 24
Finished Jul 25 05:53:20 PM PDT 24
Peak memory 211656 kb
Host smart-d6d895d6-e0e9-4139-b794-f54de01e5fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937031801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3937031801
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1136127364
Short name T307
Test name
Test status
Simulation time 21228818664 ps
CPU time 425.43 seconds
Started Jul 25 05:53:09 PM PDT 24
Finished Jul 25 06:00:14 PM PDT 24
Peak memory 235416 kb
Host smart-3321f229-2439-4521-a627-ab37dc96917f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136127364 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1136127364
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4119016287
Short name T28
Test name
Test status
Simulation time 694705240 ps
CPU time 5.38 seconds
Started Jul 25 05:53:00 PM PDT 24
Finished Jul 25 05:53:06 PM PDT 24
Peak memory 211800 kb
Host smart-73c2b196-cbcf-4f72-9a77-4d8f48af1c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119016287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4119016287
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3903336035
Short name T354
Test name
Test status
Simulation time 5223706095 ps
CPU time 81.84 seconds
Started Jul 25 05:53:04 PM PDT 24
Finished Jul 25 05:54:26 PM PDT 24
Peak memory 238264 kb
Host smart-4fb00d45-c9d3-486d-8d6b-aca61064d433
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903336035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3903336035
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3565102178
Short name T39
Test name
Test status
Simulation time 498754780 ps
CPU time 11.36 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:10 PM PDT 24
Peak memory 212692 kb
Host smart-f2c36892-8760-4fe2-8afa-8263ba3e9fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565102178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3565102178
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2965467856
Short name T364
Test name
Test status
Simulation time 143975161 ps
CPU time 6.56 seconds
Started Jul 25 05:53:00 PM PDT 24
Finished Jul 25 05:53:07 PM PDT 24
Peak memory 211896 kb
Host smart-b43dea46-79d9-409f-9503-63cd7d7bd7a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965467856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2965467856
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3991061148
Short name T268
Test name
Test status
Simulation time 369366778 ps
CPU time 9.8 seconds
Started Jul 25 05:53:10 PM PDT 24
Finished Jul 25 05:53:20 PM PDT 24
Peak memory 214020 kb
Host smart-680f0680-d88d-4b99-87c4-5e8f3480e643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991061148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3991061148
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2886132950
Short name T160
Test name
Test status
Simulation time 1069633391 ps
CPU time 18.59 seconds
Started Jul 25 05:53:09 PM PDT 24
Finished Jul 25 05:53:28 PM PDT 24
Peak memory 214472 kb
Host smart-501241cf-e0a0-451d-8a05-64d386783dea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886132950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2886132950
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3311855217
Short name T311
Test name
Test status
Simulation time 261558670 ps
CPU time 5.23 seconds
Started Jul 25 05:53:06 PM PDT 24
Finished Jul 25 05:53:11 PM PDT 24
Peak memory 211836 kb
Host smart-f4e771aa-089a-46a7-91c0-b122e60313b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311855217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3311855217
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1596271264
Short name T33
Test name
Test status
Simulation time 7104702688 ps
CPU time 107.15 seconds
Started Jul 25 05:53:04 PM PDT 24
Finished Jul 25 05:54:51 PM PDT 24
Peak memory 238264 kb
Host smart-43e3cdb8-6617-4615-8af7-bc3164cf5901
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596271264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1596271264
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2890890824
Short name T336
Test name
Test status
Simulation time 523505098 ps
CPU time 6.35 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:04 PM PDT 24
Peak memory 211852 kb
Host smart-22bd4844-9632-409f-954c-2368ce878d07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890890824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2890890824
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.997398863
Short name T251
Test name
Test status
Simulation time 1035689482 ps
CPU time 11.75 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:10 PM PDT 24
Peak memory 214100 kb
Host smart-de53dce7-b92e-4b80-9196-c969199ea350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997398863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.997398863
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1949662226
Short name T304
Test name
Test status
Simulation time 399106647 ps
CPU time 10.42 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:09 PM PDT 24
Peak memory 214980 kb
Host smart-0ac267a4-574d-4ffb-9685-ed58323ef3d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949662226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1949662226
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1093105378
Short name T247
Test name
Test status
Simulation time 828478784 ps
CPU time 5.18 seconds
Started Jul 25 05:53:05 PM PDT 24
Finished Jul 25 05:53:10 PM PDT 24
Peak memory 211808 kb
Host smart-52d26894-7487-41a8-aba4-c472f86ce4a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093105378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1093105378
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2535332097
Short name T224
Test name
Test status
Simulation time 15578781306 ps
CPU time 139.97 seconds
Started Jul 25 05:53:08 PM PDT 24
Finished Jul 25 05:55:28 PM PDT 24
Peak memory 236312 kb
Host smart-32b8a170-5fd2-4fb8-8d6e-5df1ed4dc007
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535332097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2535332097
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2363627468
Short name T241
Test name
Test status
Simulation time 931513314 ps
CPU time 9.63 seconds
Started Jul 25 05:53:08 PM PDT 24
Finished Jul 25 05:53:18 PM PDT 24
Peak memory 212420 kb
Host smart-78a1c7b9-fed3-4f73-a552-10de0834e7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363627468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2363627468
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.761297627
Short name T147
Test name
Test status
Simulation time 141641304 ps
CPU time 6.5 seconds
Started Jul 25 05:53:04 PM PDT 24
Finished Jul 25 05:53:11 PM PDT 24
Peak memory 211956 kb
Host smart-9fe1071b-fd98-4eab-96b4-5ff0b0bb27af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761297627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.761297627
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3489411878
Short name T166
Test name
Test status
Simulation time 1013112292 ps
CPU time 11.78 seconds
Started Jul 25 05:53:11 PM PDT 24
Finished Jul 25 05:53:23 PM PDT 24
Peak memory 213464 kb
Host smart-a35a87d2-b7cd-47ba-a060-2440fb802864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489411878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3489411878
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.614243098
Short name T322
Test name
Test status
Simulation time 797949529 ps
CPU time 10.86 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:53:18 PM PDT 24
Peak memory 215284 kb
Host smart-25a56713-de4f-4d2f-b40e-70e6aed4b903
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614243098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.614243098
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2604815401
Short name T149
Test name
Test status
Simulation time 501809558 ps
CPU time 5.19 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:42 PM PDT 24
Peak memory 211804 kb
Host smart-0b1dd629-2d1e-4118-89c0-30fece7f34fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604815401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2604815401
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2706944881
Short name T186
Test name
Test status
Simulation time 14128824935 ps
CPU time 99.11 seconds
Started Jul 25 05:52:39 PM PDT 24
Finished Jul 25 05:54:18 PM PDT 24
Peak memory 213224 kb
Host smart-e0e8efeb-6911-4c61-8c22-059d617acbfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706944881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2706944881
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3051806909
Short name T23
Test name
Test status
Simulation time 262007486 ps
CPU time 11.22 seconds
Started Jul 25 05:52:38 PM PDT 24
Finished Jul 25 05:52:50 PM PDT 24
Peak memory 212600 kb
Host smart-35ab36ec-096e-4b1b-811e-a7e981133fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051806909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3051806909
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2728538294
Short name T368
Test name
Test status
Simulation time 394381116 ps
CPU time 5.68 seconds
Started Jul 25 05:52:36 PM PDT 24
Finished Jul 25 05:52:42 PM PDT 24
Peak memory 211892 kb
Host smart-34bdaf53-7222-4915-b728-d534d9fd972d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728538294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2728538294
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2437545638
Short name T21
Test name
Test status
Simulation time 757581936 ps
CPU time 52.4 seconds
Started Jul 25 05:52:38 PM PDT 24
Finished Jul 25 05:53:31 PM PDT 24
Peak memory 238112 kb
Host smart-4ecd450d-2d24-48bd-950a-f01d5ce420e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437545638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2437545638
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.524412253
Short name T315
Test name
Test status
Simulation time 377679665 ps
CPU time 10.06 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 05:52:47 PM PDT 24
Peak memory 214388 kb
Host smart-d696cf4f-a1fc-4dd5-aca7-d023b1c9a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524412253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.524412253
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1773290376
Short name T40
Test name
Test status
Simulation time 86846986920 ps
CPU time 5417.75 seconds
Started Jul 25 05:52:37 PM PDT 24
Finished Jul 25 07:22:56 PM PDT 24
Peak memory 229556 kb
Host smart-bc723d19-5fbd-4dc1-88d1-67fe84bd8d06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773290376 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1773290376
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3632854073
Short name T58
Test name
Test status
Simulation time 2040368758 ps
CPU time 7.72 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:53:15 PM PDT 24
Peak memory 211740 kb
Host smart-b183361b-56db-4b10-980e-8d976eea0b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632854073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3632854073
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2274678051
Short name T290
Test name
Test status
Simulation time 2199253920 ps
CPU time 111.85 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:54:59 PM PDT 24
Peak memory 237384 kb
Host smart-35e675f8-0ac5-49db-bcf8-6b1f545172b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274678051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2274678051
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2412871741
Short name T130
Test name
Test status
Simulation time 323045056 ps
CPU time 9.59 seconds
Started Jul 25 05:53:06 PM PDT 24
Finished Jul 25 05:53:16 PM PDT 24
Peak memory 212628 kb
Host smart-f02cf5b2-2f88-4664-8652-8d4eb36214f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412871741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2412871741
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3247213016
Short name T93
Test name
Test status
Simulation time 141378311 ps
CPU time 6.37 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:53:13 PM PDT 24
Peak memory 211948 kb
Host smart-2f8fccf1-d5e3-4038-911e-dd0eed686d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247213016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3247213016
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.710616465
Short name T258
Test name
Test status
Simulation time 276175767 ps
CPU time 11.73 seconds
Started Jul 25 05:53:06 PM PDT 24
Finished Jul 25 05:53:18 PM PDT 24
Peak memory 212612 kb
Host smart-6d23b89f-946f-4416-b014-1b153e5f1832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710616465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.710616465
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3750815656
Short name T232
Test name
Test status
Simulation time 724787392 ps
CPU time 30.4 seconds
Started Jul 25 05:53:06 PM PDT 24
Finished Jul 25 05:53:37 PM PDT 24
Peak memory 214876 kb
Host smart-68ff7094-2042-454d-9406-2b2a0a6037a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750815656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3750815656
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.299764290
Short name T274
Test name
Test status
Simulation time 25763900236 ps
CPU time 1095.66 seconds
Started Jul 25 05:53:08 PM PDT 24
Finished Jul 25 06:11:23 PM PDT 24
Peak memory 230412 kb
Host smart-9469477a-0ecb-44d3-89ac-837701d42cce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299764290 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.299764290
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2324340659
Short name T218
Test name
Test status
Simulation time 500642639 ps
CPU time 5.01 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:53:12 PM PDT 24
Peak memory 211720 kb
Host smart-4dcbd2ec-2fae-49f1-b401-60181f1f67a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324340659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2324340659
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2940795462
Short name T146
Test name
Test status
Simulation time 7153860739 ps
CPU time 95.37 seconds
Started Jul 25 05:53:08 PM PDT 24
Finished Jul 25 05:54:44 PM PDT 24
Peak memory 213084 kb
Host smart-01baec45-b4d5-49fc-bf49-85d832dbd0a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940795462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2940795462
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4267889774
Short name T254
Test name
Test status
Simulation time 544936207 ps
CPU time 11.14 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:53:18 PM PDT 24
Peak memory 212704 kb
Host smart-1583551f-311d-49e2-bfd6-3de563d5e247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267889774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4267889774
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1680077367
Short name T342
Test name
Test status
Simulation time 504171816 ps
CPU time 8.87 seconds
Started Jul 25 05:53:09 PM PDT 24
Finished Jul 25 05:53:18 PM PDT 24
Peak memory 211860 kb
Host smart-8e419d6f-8843-4961-bdde-f7073f81614b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1680077367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1680077367
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2246396547
Short name T361
Test name
Test status
Simulation time 718062558 ps
CPU time 10.2 seconds
Started Jul 25 05:53:06 PM PDT 24
Finished Jul 25 05:53:17 PM PDT 24
Peak memory 214568 kb
Host smart-7d48931c-5845-4c67-9a83-0222f6c99838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246396547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2246396547
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.966862453
Short name T298
Test name
Test status
Simulation time 133256354 ps
CPU time 7.72 seconds
Started Jul 25 05:53:09 PM PDT 24
Finished Jul 25 05:53:17 PM PDT 24
Peak memory 211808 kb
Host smart-ea6c2731-33d7-43b9-87b7-666368ba5f77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966862453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.966862453
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2743395492
Short name T150
Test name
Test status
Simulation time 1830240209 ps
CPU time 7.82 seconds
Started Jul 25 05:53:06 PM PDT 24
Finished Jul 25 05:53:14 PM PDT 24
Peak memory 211816 kb
Host smart-8fcfa4b4-04d4-4e57-8d68-40a75e527f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743395492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2743395492
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3365806934
Short name T223
Test name
Test status
Simulation time 7046203154 ps
CPU time 90.83 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:54:38 PM PDT 24
Peak memory 234220 kb
Host smart-43d207a6-ccf4-4da0-93ae-97f49d75f909
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365806934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3365806934
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3389920386
Short name T297
Test name
Test status
Simulation time 760816524 ps
CPU time 9.58 seconds
Started Jul 25 05:53:10 PM PDT 24
Finished Jul 25 05:53:20 PM PDT 24
Peak memory 212764 kb
Host smart-4e6d4081-a24c-40fa-a545-61a1b45643ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389920386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3389920386
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2622427143
Short name T62
Test name
Test status
Simulation time 374230942 ps
CPU time 5.48 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:53:13 PM PDT 24
Peak memory 211932 kb
Host smart-ab7b79be-d6c1-4281-9c28-d1e0c26595e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622427143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2622427143
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.861399722
Short name T201
Test name
Test status
Simulation time 279254087 ps
CPU time 12.2 seconds
Started Jul 25 05:53:06 PM PDT 24
Finished Jul 25 05:53:19 PM PDT 24
Peak memory 214520 kb
Host smart-553b36e9-272b-4242-a877-21220d5a1fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861399722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.861399722
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2590978195
Short name T230
Test name
Test status
Simulation time 8455683360 ps
CPU time 18.61 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:53:26 PM PDT 24
Peak memory 217648 kb
Host smart-4e3e25e3-2d4f-4764-887b-c0bbdd3735a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590978195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2590978195
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1722549463
Short name T15
Test name
Test status
Simulation time 204142492261 ps
CPU time 1954.26 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 06:25:41 PM PDT 24
Peak memory 236376 kb
Host smart-fc8cc1f0-4c43-4365-8857-7e73105978b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722549463 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1722549463
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3625049882
Short name T333
Test name
Test status
Simulation time 110395453 ps
CPU time 4.49 seconds
Started Jul 25 05:53:09 PM PDT 24
Finished Jul 25 05:53:13 PM PDT 24
Peak memory 211784 kb
Host smart-be99c8c3-550d-4f99-b96c-611e28b50724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625049882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3625049882
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2702952408
Short name T163
Test name
Test status
Simulation time 1229755614 ps
CPU time 89.48 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:54:36 PM PDT 24
Peak memory 238236 kb
Host smart-701d8756-624e-4459-8077-4659692e701b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702952408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2702952408
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2827913909
Short name T323
Test name
Test status
Simulation time 262776743 ps
CPU time 11.32 seconds
Started Jul 25 05:53:09 PM PDT 24
Finished Jul 25 05:53:21 PM PDT 24
Peak memory 212768 kb
Host smart-ec2869b5-bd0f-4e0d-a84c-af0a2a742dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827913909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2827913909
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1647188714
Short name T231
Test name
Test status
Simulation time 135267923 ps
CPU time 6.27 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:53:14 PM PDT 24
Peak memory 211884 kb
Host smart-f00e4167-32fe-4c8a-b824-150139295581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647188714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1647188714
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.525569860
Short name T138
Test name
Test status
Simulation time 362262036 ps
CPU time 9.98 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 05:53:17 PM PDT 24
Peak memory 213944 kb
Host smart-17e21e8c-733c-4b86-a26f-95ab2d74450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525569860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.525569860
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3452790996
Short name T261
Test name
Test status
Simulation time 858411340 ps
CPU time 11.01 seconds
Started Jul 25 05:53:06 PM PDT 24
Finished Jul 25 05:53:17 PM PDT 24
Peak memory 211796 kb
Host smart-baf43cb7-5601-4502-a03b-16df64e195a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452790996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3452790996
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.973350632
Short name T313
Test name
Test status
Simulation time 63048808538 ps
CPU time 2374.85 seconds
Started Jul 25 05:53:07 PM PDT 24
Finished Jul 25 06:32:42 PM PDT 24
Peak memory 236728 kb
Host smart-2544e180-6da0-47bf-896d-0a79476e70cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973350632 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.973350632
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1849498409
Short name T154
Test name
Test status
Simulation time 336771803 ps
CPU time 4.26 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:53:21 PM PDT 24
Peak memory 211780 kb
Host smart-ad963a63-827f-4be7-ab1e-bf885d2994cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849498409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1849498409
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4113211545
Short name T34
Test name
Test status
Simulation time 9404898512 ps
CPU time 109.23 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:55:06 PM PDT 24
Peak memory 213360 kb
Host smart-a2457b8d-ea67-490c-ad74-52087580c870
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113211545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4113211545
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1438222388
Short name T358
Test name
Test status
Simulation time 500600618 ps
CPU time 11.25 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:53:28 PM PDT 24
Peak memory 212600 kb
Host smart-c5bad7ac-cb2c-4fe4-8efa-60e308bd4b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438222388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1438222388
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2271730391
Short name T226
Test name
Test status
Simulation time 99767610 ps
CPU time 5.52 seconds
Started Jul 25 05:53:14 PM PDT 24
Finished Jul 25 05:53:20 PM PDT 24
Peak memory 211908 kb
Host smart-3eac1a86-8fdd-46f0-974f-6038daeff39d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2271730391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2271730391
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3828166226
Short name T76
Test name
Test status
Simulation time 561901786 ps
CPU time 11.99 seconds
Started Jul 25 05:53:05 PM PDT 24
Finished Jul 25 05:53:17 PM PDT 24
Peak memory 214644 kb
Host smart-9e3f2abd-61ed-4fe8-b80f-d6ee7dab6ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828166226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3828166226
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.899185854
Short name T294
Test name
Test status
Simulation time 645162794 ps
CPU time 9.31 seconds
Started Jul 25 05:53:10 PM PDT 24
Finished Jul 25 05:53:20 PM PDT 24
Peak memory 211836 kb
Host smart-bf5e1a5f-13d3-42cb-a67a-566859c18353
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899185854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.899185854
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.983492723
Short name T369
Test name
Test status
Simulation time 134749724 ps
CPU time 5.09 seconds
Started Jul 25 05:53:15 PM PDT 24
Finished Jul 25 05:53:21 PM PDT 24
Peak memory 211788 kb
Host smart-06c2bca8-4850-40a4-ab78-268ec62c9c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983492723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.983492723
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2448808481
Short name T136
Test name
Test status
Simulation time 5241769596 ps
CPU time 73.98 seconds
Started Jul 25 05:53:17 PM PDT 24
Finished Jul 25 05:54:31 PM PDT 24
Peak memory 235252 kb
Host smart-06b2affc-a395-45ee-9bd6-7d7ef88f379d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448808481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2448808481
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2567804010
Short name T177
Test name
Test status
Simulation time 336395035 ps
CPU time 9.43 seconds
Started Jul 25 05:53:17 PM PDT 24
Finished Jul 25 05:53:26 PM PDT 24
Peak memory 212644 kb
Host smart-fa3ec47f-d9b5-44e7-94bf-d2ace7e8a815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567804010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2567804010
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1858014860
Short name T153
Test name
Test status
Simulation time 275648237 ps
CPU time 6.59 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:53:23 PM PDT 24
Peak memory 211896 kb
Host smart-2952badd-511b-40f9-9cd8-0f3a9705802a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858014860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1858014860
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4050510847
Short name T284
Test name
Test status
Simulation time 178370542 ps
CPU time 10.7 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:53:27 PM PDT 24
Peak memory 213252 kb
Host smart-0f781d48-5511-463b-b2ba-f667e41d7092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050510847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4050510847
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1772367567
Short name T192
Test name
Test status
Simulation time 167413965 ps
CPU time 10.05 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:53:27 PM PDT 24
Peak memory 211900 kb
Host smart-b8e7dcd7-1f12-479f-a6fa-085c583207fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772367567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1772367567
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2386375280
Short name T207
Test name
Test status
Simulation time 174899313 ps
CPU time 4.27 seconds
Started Jul 25 05:53:20 PM PDT 24
Finished Jul 25 05:53:24 PM PDT 24
Peak memory 211824 kb
Host smart-f2d208ce-82af-49fa-9499-05dadf77f508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386375280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2386375280
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2340098984
Short name T239
Test name
Test status
Simulation time 4121382100 ps
CPU time 121 seconds
Started Jul 25 05:53:17 PM PDT 24
Finished Jul 25 05:55:18 PM PDT 24
Peak memory 238156 kb
Host smart-66beedf6-b240-406d-aa74-5b0252ff238f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340098984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2340098984
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4556021
Short name T151
Test name
Test status
Simulation time 3348080778 ps
CPU time 9.69 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:53:25 PM PDT 24
Peak memory 212744 kb
Host smart-5e3c7511-0843-4d41-b37b-040896e16db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4556021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4556021
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1951994500
Short name T349
Test name
Test status
Simulation time 138213026 ps
CPU time 6.51 seconds
Started Jul 25 05:53:17 PM PDT 24
Finished Jul 25 05:53:24 PM PDT 24
Peak memory 211896 kb
Host smart-4dadb595-45bc-433f-ab22-49127f7be233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951994500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1951994500
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.4139340906
Short name T171
Test name
Test status
Simulation time 183871298 ps
CPU time 10.15 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:53:26 PM PDT 24
Peak memory 213588 kb
Host smart-206b2423-9202-4220-90b7-fb97124f6166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139340906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.4139340906
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1111166236
Short name T250
Test name
Test status
Simulation time 295869828 ps
CPU time 19.12 seconds
Started Jul 25 05:53:15 PM PDT 24
Finished Jul 25 05:53:35 PM PDT 24
Peak memory 216872 kb
Host smart-66cebec7-3a03-4359-9973-c59740631720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111166236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1111166236
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1862654684
Short name T48
Test name
Test status
Simulation time 103181565110 ps
CPU time 940.02 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 06:08:56 PM PDT 24
Peak memory 236412 kb
Host smart-83e09517-4fa7-425f-8909-0fc3e2d0a1f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862654684 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1862654684
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3413504673
Short name T355
Test name
Test status
Simulation time 129135254 ps
CPU time 5.22 seconds
Started Jul 25 05:53:17 PM PDT 24
Finished Jul 25 05:53:22 PM PDT 24
Peak memory 211768 kb
Host smart-c53a64e0-d84f-452b-a461-aafe1b27b62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413504673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3413504673
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.536125715
Short name T32
Test name
Test status
Simulation time 21327046280 ps
CPU time 211.15 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:56:48 PM PDT 24
Peak memory 239312 kb
Host smart-dcee60f5-0686-4d6c-905c-59c8c4380854
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536125715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.536125715
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4213819425
Short name T275
Test name
Test status
Simulation time 258239466 ps
CPU time 11.15 seconds
Started Jul 25 05:53:15 PM PDT 24
Finished Jul 25 05:53:26 PM PDT 24
Peak memory 213112 kb
Host smart-f75f170a-6010-41a4-b982-6feea904ce57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213819425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4213819425
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4264782708
Short name T210
Test name
Test status
Simulation time 533160349 ps
CPU time 6.56 seconds
Started Jul 25 05:53:18 PM PDT 24
Finished Jul 25 05:53:25 PM PDT 24
Peak memory 211960 kb
Host smart-f824595a-4254-47bb-b895-c4049b5da267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264782708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4264782708
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1209861977
Short name T280
Test name
Test status
Simulation time 185897302 ps
CPU time 10.59 seconds
Started Jul 25 05:53:19 PM PDT 24
Finished Jul 25 05:53:30 PM PDT 24
Peak memory 214012 kb
Host smart-aa85a5e7-a1a1-46c2-85dd-25f5e8d5a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209861977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1209861977
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3442002776
Short name T316
Test name
Test status
Simulation time 1762092337 ps
CPU time 26.12 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:53:43 PM PDT 24
Peak memory 215124 kb
Host smart-4aea8d77-b5bd-44a1-8cf6-90f7255dcd07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442002776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3442002776
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1830659767
Short name T41
Test name
Test status
Simulation time 139377242398 ps
CPU time 5264.56 seconds
Started Jul 25 05:53:17 PM PDT 24
Finished Jul 25 07:21:02 PM PDT 24
Peak memory 253984 kb
Host smart-e5f22440-4ad1-4f9b-95a6-f26fe5165675
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830659767 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1830659767
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2333911021
Short name T328
Test name
Test status
Simulation time 305601029 ps
CPU time 5.13 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:53:31 PM PDT 24
Peak memory 211812 kb
Host smart-c52ebee0-1437-40c6-a702-5972c4def652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333911021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2333911021
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3400517173
Short name T306
Test name
Test status
Simulation time 6872597672 ps
CPU time 103.29 seconds
Started Jul 25 05:53:15 PM PDT 24
Finished Jul 25 05:54:59 PM PDT 24
Peak memory 213148 kb
Host smart-69e28dc5-74da-4f6e-9554-f607e3f51753
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400517173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3400517173
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2962080465
Short name T263
Test name
Test status
Simulation time 172803668 ps
CPU time 9.6 seconds
Started Jul 25 05:53:28 PM PDT 24
Finished Jul 25 05:53:37 PM PDT 24
Peak memory 212572 kb
Host smart-cf2d3b6e-335b-4403-a626-85e28930276b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962080465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2962080465
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3650183775
Short name T335
Test name
Test status
Simulation time 379001966 ps
CPU time 5.89 seconds
Started Jul 25 05:53:17 PM PDT 24
Finished Jul 25 05:53:23 PM PDT 24
Peak memory 211912 kb
Host smart-e8a80460-4ac7-4bdf-9300-fbf4ca0ee6a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650183775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3650183775
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2306881117
Short name T9
Test name
Test status
Simulation time 183852634 ps
CPU time 10.09 seconds
Started Jul 25 05:53:17 PM PDT 24
Finished Jul 25 05:53:28 PM PDT 24
Peak memory 213708 kb
Host smart-550a8f17-7581-4cbb-a7a4-78f7cf4d123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306881117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2306881117
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2893910015
Short name T302
Test name
Test status
Simulation time 242423404 ps
CPU time 9.61 seconds
Started Jul 25 05:53:16 PM PDT 24
Finished Jul 25 05:53:26 PM PDT 24
Peak memory 212132 kb
Host smart-45b61a04-04fd-4459-a4a4-9f8f9e6379f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893910015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2893910015
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1828021361
Short name T1
Test name
Test status
Simulation time 126157673 ps
CPU time 5.19 seconds
Started Jul 25 05:53:32 PM PDT 24
Finished Jul 25 05:53:37 PM PDT 24
Peak memory 211824 kb
Host smart-00e8f1ea-5abe-4050-b0c0-7266a6959960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828021361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1828021361
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1669794404
Short name T299
Test name
Test status
Simulation time 920148139 ps
CPU time 59.34 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:54:25 PM PDT 24
Peak memory 237100 kb
Host smart-92da0e09-df36-4d51-9e55-de1efbf498b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669794404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1669794404
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3791916795
Short name T308
Test name
Test status
Simulation time 665647402 ps
CPU time 9.23 seconds
Started Jul 25 05:53:32 PM PDT 24
Finished Jul 25 05:53:41 PM PDT 24
Peak memory 212628 kb
Host smart-01035ffa-8472-4870-bf05-7654ada85e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791916795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3791916795
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1183587485
Short name T310
Test name
Test status
Simulation time 144868152 ps
CPU time 6.52 seconds
Started Jul 25 05:53:25 PM PDT 24
Finished Jul 25 05:53:32 PM PDT 24
Peak memory 211936 kb
Host smart-5f8d7d6f-6cc1-4981-a5f4-6243cb08c601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183587485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1183587485
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2406433111
Short name T321
Test name
Test status
Simulation time 182043660 ps
CPU time 9.95 seconds
Started Jul 25 05:53:25 PM PDT 24
Finished Jul 25 05:53:35 PM PDT 24
Peak memory 213132 kb
Host smart-be380ecf-e565-435e-a15a-9e6491e9081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406433111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2406433111
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3002751630
Short name T345
Test name
Test status
Simulation time 914404576 ps
CPU time 27.07 seconds
Started Jul 25 05:53:24 PM PDT 24
Finished Jul 25 05:53:51 PM PDT 24
Peak memory 215020 kb
Host smart-e9768b28-c0bb-4526-9781-9274957a6c53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002751630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3002751630
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2549301974
Short name T347
Test name
Test status
Simulation time 92677999536 ps
CPU time 1770.97 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 06:22:58 PM PDT 24
Peak memory 236492 kb
Host smart-9b551500-df57-46f2-9428-0833e4ccaa11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549301974 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2549301974
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2999582074
Short name T352
Test name
Test status
Simulation time 884012802 ps
CPU time 5.03 seconds
Started Jul 25 05:52:47 PM PDT 24
Finished Jul 25 05:52:52 PM PDT 24
Peak memory 211828 kb
Host smart-b695b41e-e60a-4483-9b66-cee5d30fb896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999582074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2999582074
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3963403276
Short name T371
Test name
Test status
Simulation time 1093978755 ps
CPU time 68.6 seconds
Started Jul 25 05:52:56 PM PDT 24
Finished Jul 25 05:54:05 PM PDT 24
Peak memory 229016 kb
Host smart-e919d150-3978-43db-a8f1-e594540fc4c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963403276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3963403276
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.342702406
Short name T131
Test name
Test status
Simulation time 700863204 ps
CPU time 9.55 seconds
Started Jul 25 05:52:50 PM PDT 24
Finished Jul 25 05:53:00 PM PDT 24
Peak memory 212804 kb
Host smart-852e859a-9de2-44fe-803e-36635865d5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342702406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.342702406
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3417701809
Short name T168
Test name
Test status
Simulation time 154616833 ps
CPU time 5.65 seconds
Started Jul 25 05:52:46 PM PDT 24
Finished Jul 25 05:52:51 PM PDT 24
Peak memory 211928 kb
Host smart-1daf6bb3-80ab-4349-ae49-d70a79f3e95b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417701809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3417701809
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4001812320
Short name T27
Test name
Test status
Simulation time 724463404 ps
CPU time 52.41 seconds
Started Jul 25 05:52:47 PM PDT 24
Finished Jul 25 05:53:39 PM PDT 24
Peak memory 236476 kb
Host smart-6d0a9895-fa2b-461f-ab5e-5e8070541b5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001812320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4001812320
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3876991875
Short name T112
Test name
Test status
Simulation time 185308691 ps
CPU time 10.25 seconds
Started Jul 25 05:52:49 PM PDT 24
Finished Jul 25 05:52:59 PM PDT 24
Peak memory 214324 kb
Host smart-bb361cd6-e3fa-4ffd-8f76-fc70332f9b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876991875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3876991875
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2295190600
Short name T324
Test name
Test status
Simulation time 1583720965 ps
CPU time 19.15 seconds
Started Jul 25 05:52:50 PM PDT 24
Finished Jul 25 05:53:09 PM PDT 24
Peak memory 216140 kb
Host smart-b522759c-e4c1-42d6-8324-a234c44bd862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295190600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2295190600
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3819234448
Short name T139
Test name
Test status
Simulation time 333020801 ps
CPU time 4.31 seconds
Started Jul 25 05:53:27 PM PDT 24
Finished Jul 25 05:53:32 PM PDT 24
Peak memory 211760 kb
Host smart-580689a1-5cca-487a-af68-1aaecbcf0b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819234448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3819234448
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1538353374
Short name T4
Test name
Test status
Simulation time 9794860662 ps
CPU time 124.79 seconds
Started Jul 25 05:53:28 PM PDT 24
Finished Jul 25 05:55:33 PM PDT 24
Peak memory 238156 kb
Host smart-849f0ecb-808c-4570-a923-65651153fdc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538353374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1538353374
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.473357021
Short name T55
Test name
Test status
Simulation time 265017115 ps
CPU time 11.65 seconds
Started Jul 25 05:53:25 PM PDT 24
Finished Jul 25 05:53:37 PM PDT 24
Peak memory 212716 kb
Host smart-bd7c9e41-b77b-42ea-a545-87c794121018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473357021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.473357021
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3625030028
Short name T3
Test name
Test status
Simulation time 136456636 ps
CPU time 6.3 seconds
Started Jul 25 05:53:23 PM PDT 24
Finished Jul 25 05:53:30 PM PDT 24
Peak memory 211852 kb
Host smart-08f70d22-2520-483a-8f57-7d8011a24d01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625030028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3625030028
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.656766422
Short name T293
Test name
Test status
Simulation time 1596327218 ps
CPU time 12.83 seconds
Started Jul 25 05:53:25 PM PDT 24
Finished Jul 25 05:53:38 PM PDT 24
Peak memory 214284 kb
Host smart-a8c895ef-c52d-44f6-abf6-366a723039d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656766422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.656766422
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3391139199
Short name T246
Test name
Test status
Simulation time 600531782 ps
CPU time 17.64 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:53:44 PM PDT 24
Peak memory 215828 kb
Host smart-247469eb-c839-44d4-8012-573bf85ccaa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391139199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3391139199
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2435312296
Short name T14
Test name
Test status
Simulation time 86607415047 ps
CPU time 841.77 seconds
Started Jul 25 05:53:30 PM PDT 24
Finished Jul 25 06:07:33 PM PDT 24
Peak memory 236400 kb
Host smart-a8105f8b-e419-4555-bf9e-5be8c4a37b19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435312296 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2435312296
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2659610904
Short name T61
Test name
Test status
Simulation time 570594919 ps
CPU time 5.07 seconds
Started Jul 25 05:53:27 PM PDT 24
Finished Jul 25 05:53:33 PM PDT 24
Peak memory 211768 kb
Host smart-d1ceb972-f999-4214-a9bd-567ecfd679db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659610904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2659610904
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1066262481
Short name T43
Test name
Test status
Simulation time 8855703532 ps
CPU time 83.81 seconds
Started Jul 25 05:53:28 PM PDT 24
Finished Jul 25 05:54:52 PM PDT 24
Peak memory 238192 kb
Host smart-92df5c6b-fa38-4757-97c6-bc3c578836ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066262481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1066262481
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.864916625
Short name T182
Test name
Test status
Simulation time 2266678704 ps
CPU time 11.25 seconds
Started Jul 25 05:53:28 PM PDT 24
Finished Jul 25 05:53:39 PM PDT 24
Peak memory 212668 kb
Host smart-d7a18152-08aa-409e-b9a8-239be9287648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864916625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.864916625
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2583404557
Short name T18
Test name
Test status
Simulation time 170486767 ps
CPU time 6.34 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:53:32 PM PDT 24
Peak memory 211896 kb
Host smart-150e32a7-deaf-420a-a061-0197ccf740e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583404557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2583404557
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2233247361
Short name T145
Test name
Test status
Simulation time 1059126773 ps
CPU time 11.86 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:53:38 PM PDT 24
Peak memory 212540 kb
Host smart-d7697cb9-081b-4161-ad1b-beecae9e3539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233247361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2233247361
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.337666766
Short name T244
Test name
Test status
Simulation time 8492853299 ps
CPU time 27.46 seconds
Started Jul 25 05:53:30 PM PDT 24
Finished Jul 25 05:53:58 PM PDT 24
Peak memory 215472 kb
Host smart-51f3e9f4-eaa0-45c9-877e-9d249c67f540
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337666766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.337666766
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2292103186
Short name T29
Test name
Test status
Simulation time 201945080 ps
CPU time 4.36 seconds
Started Jul 25 05:53:28 PM PDT 24
Finished Jul 25 05:53:32 PM PDT 24
Peak memory 211844 kb
Host smart-24c43c9d-695c-4133-8705-0a3baf684f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292103186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2292103186
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3294207294
Short name T312
Test name
Test status
Simulation time 7427903960 ps
CPU time 115.42 seconds
Started Jul 25 05:53:25 PM PDT 24
Finished Jul 25 05:55:21 PM PDT 24
Peak memory 239284 kb
Host smart-23740424-c53a-4099-b7c2-0fe0d132bf69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294207294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3294207294
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3821411850
Short name T95
Test name
Test status
Simulation time 667898597 ps
CPU time 9.83 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:53:36 PM PDT 24
Peak memory 212608 kb
Host smart-25c21c28-af90-4ecd-9845-55370baee7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821411850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3821411850
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3377624182
Short name T249
Test name
Test status
Simulation time 97329483 ps
CPU time 5.88 seconds
Started Jul 25 05:53:27 PM PDT 24
Finished Jul 25 05:53:33 PM PDT 24
Peak memory 211908 kb
Host smart-03b227e6-13e1-41b7-931b-ae58ef59f90e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377624182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3377624182
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.462044183
Short name T222
Test name
Test status
Simulation time 394265122 ps
CPU time 10.24 seconds
Started Jul 25 05:53:24 PM PDT 24
Finished Jul 25 05:53:34 PM PDT 24
Peak memory 213932 kb
Host smart-be35597b-6e5c-4d07-b97e-05398fa8da7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462044183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.462044183
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1542787567
Short name T77
Test name
Test status
Simulation time 2012826426 ps
CPU time 26.3 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:53:53 PM PDT 24
Peak memory 214768 kb
Host smart-589c170d-00e4-4240-a76c-2568df5df558
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542787567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1542787567
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.119516703
Short name T2
Test name
Test status
Simulation time 521051456 ps
CPU time 5.22 seconds
Started Jul 25 05:53:25 PM PDT 24
Finished Jul 25 05:53:30 PM PDT 24
Peak memory 211812 kb
Host smart-36154b1c-1be4-4cbf-8638-b8f6aab677b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119516703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.119516703
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1982142534
Short name T20
Test name
Test status
Simulation time 2563073654 ps
CPU time 139.91 seconds
Started Jul 25 05:53:32 PM PDT 24
Finished Jul 25 05:55:52 PM PDT 24
Peak memory 213156 kb
Host smart-f4dd9b32-5dbf-454f-bbee-de5cab23daa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982142534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1982142534
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.742997863
Short name T194
Test name
Test status
Simulation time 617232900 ps
CPU time 9.42 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:53:36 PM PDT 24
Peak memory 212560 kb
Host smart-9509b766-7bd7-43a9-9081-3764096b916a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742997863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.742997863
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1096104204
Short name T332
Test name
Test status
Simulation time 762486215 ps
CPU time 5.49 seconds
Started Jul 25 05:53:25 PM PDT 24
Finished Jul 25 05:53:31 PM PDT 24
Peak memory 211932 kb
Host smart-b3f5440e-566f-4a38-8adb-c03f4aac5381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096104204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1096104204
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3133458641
Short name T75
Test name
Test status
Simulation time 2150736388 ps
CPU time 12.41 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:53:39 PM PDT 24
Peak memory 214068 kb
Host smart-849c2377-c5ff-4bc2-afba-c011bf670352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133458641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3133458641
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2765756105
Short name T10
Test name
Test status
Simulation time 1451183880 ps
CPU time 19.02 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:53:46 PM PDT 24
Peak memory 215848 kb
Host smart-306cca09-e88a-4834-9511-ad4b688e3d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765756105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2765756105
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.733960971
Short name T220
Test name
Test status
Simulation time 37863382564 ps
CPU time 8207.04 seconds
Started Jul 25 05:53:27 PM PDT 24
Finished Jul 25 08:10:15 PM PDT 24
Peak memory 228160 kb
Host smart-541661be-59e7-424b-87c4-f41bad28c175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733960971 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.733960971
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2093145467
Short name T357
Test name
Test status
Simulation time 499786764 ps
CPU time 5.15 seconds
Started Jul 25 05:53:32 PM PDT 24
Finished Jul 25 05:53:38 PM PDT 24
Peak memory 211836 kb
Host smart-7748e4ba-441e-4a4c-8d62-66e39ec18878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093145467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2093145467
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3313685900
Short name T319
Test name
Test status
Simulation time 8465052899 ps
CPU time 136.69 seconds
Started Jul 25 05:53:26 PM PDT 24
Finished Jul 25 05:55:43 PM PDT 24
Peak memory 213048 kb
Host smart-ae260063-cfcd-450a-a800-ffdce9d303c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313685900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3313685900
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3032364928
Short name T174
Test name
Test status
Simulation time 262164946 ps
CPU time 11.37 seconds
Started Jul 25 05:53:32 PM PDT 24
Finished Jul 25 05:53:44 PM PDT 24
Peak memory 212776 kb
Host smart-ddd3cb12-ad7e-451e-8bd9-16e6629e0f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032364928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3032364928
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2098545402
Short name T330
Test name
Test status
Simulation time 392202916 ps
CPU time 5.9 seconds
Started Jul 25 05:53:25 PM PDT 24
Finished Jul 25 05:53:31 PM PDT 24
Peak memory 211928 kb
Host smart-ca27f884-2248-4fe0-85f2-9199aa43291d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098545402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2098545402
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2869257099
Short name T178
Test name
Test status
Simulation time 272412264 ps
CPU time 11.95 seconds
Started Jul 25 05:53:28 PM PDT 24
Finished Jul 25 05:53:40 PM PDT 24
Peak memory 213088 kb
Host smart-4e0dafd0-0ffd-4b28-8b38-8b51d393a268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869257099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2869257099
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2424744303
Short name T286
Test name
Test status
Simulation time 1920453937 ps
CPU time 12.73 seconds
Started Jul 25 05:53:23 PM PDT 24
Finished Jul 25 05:53:36 PM PDT 24
Peak memory 211808 kb
Host smart-0ffae6dd-188e-496d-a045-bc5f62ce3b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424744303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2424744303
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3052387570
Short name T113
Test name
Test status
Simulation time 27290908710 ps
CPU time 1124 seconds
Started Jul 25 05:53:35 PM PDT 24
Finished Jul 25 06:12:19 PM PDT 24
Peak memory 236360 kb
Host smart-1fdcb90f-df0d-4238-90f3-5d2983070bae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052387570 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3052387570
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.337530900
Short name T6
Test name
Test status
Simulation time 211575792 ps
CPU time 4.27 seconds
Started Jul 25 05:53:32 PM PDT 24
Finished Jul 25 05:53:37 PM PDT 24
Peak memory 211764 kb
Host smart-0d6f2c83-b8da-466b-960d-ff7c9cdec33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337530900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.337530900
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4155193995
Short name T183
Test name
Test status
Simulation time 3154577111 ps
CPU time 126.94 seconds
Started Jul 25 05:53:34 PM PDT 24
Finished Jul 25 05:55:41 PM PDT 24
Peak memory 213156 kb
Host smart-ed8cfb0d-b106-4d15-8698-40e1d21d33b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155193995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4155193995
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3639873129
Short name T38
Test name
Test status
Simulation time 174047899 ps
CPU time 9.55 seconds
Started Jul 25 05:53:32 PM PDT 24
Finished Jul 25 05:53:42 PM PDT 24
Peak memory 212700 kb
Host smart-5e0aca08-a896-4934-a85a-b77cac51483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639873129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3639873129
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1787082981
Short name T60
Test name
Test status
Simulation time 540402100 ps
CPU time 6.66 seconds
Started Jul 25 05:53:31 PM PDT 24
Finished Jul 25 05:53:38 PM PDT 24
Peak memory 211924 kb
Host smart-7ad47c0f-0cc6-458e-8d52-9d6d6584308b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787082981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1787082981
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3256713368
Short name T158
Test name
Test status
Simulation time 1056077715 ps
CPU time 11.75 seconds
Started Jul 25 05:53:54 PM PDT 24
Finished Jul 25 05:54:06 PM PDT 24
Peak memory 214280 kb
Host smart-cdf681cc-5dca-41f4-9bc7-770a1394936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256713368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3256713368
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3084117352
Short name T348
Test name
Test status
Simulation time 377706608 ps
CPU time 22.42 seconds
Started Jul 25 05:53:34 PM PDT 24
Finished Jul 25 05:53:57 PM PDT 24
Peak memory 216576 kb
Host smart-be9a4980-6e82-4083-8655-55df21572001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084117352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3084117352
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1077673678
Short name T135
Test name
Test status
Simulation time 86580773 ps
CPU time 4.3 seconds
Started Jul 25 05:53:31 PM PDT 24
Finished Jul 25 05:53:35 PM PDT 24
Peak memory 211796 kb
Host smart-f4cbf08a-6424-4f0a-8be5-806b8976979d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077673678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1077673678
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2591234324
Short name T36
Test name
Test status
Simulation time 3423692191 ps
CPU time 90.73 seconds
Started Jul 25 05:53:33 PM PDT 24
Finished Jul 25 05:55:04 PM PDT 24
Peak memory 229068 kb
Host smart-46872e98-90c5-4aae-859d-bda7ab8b4158
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591234324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2591234324
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1705742583
Short name T24
Test name
Test status
Simulation time 921592084 ps
CPU time 11.22 seconds
Started Jul 25 05:53:32 PM PDT 24
Finished Jul 25 05:53:43 PM PDT 24
Peak memory 212632 kb
Host smart-0308074f-fa00-43e5-aaf1-1cf293c3480c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705742583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1705742583
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.613101123
Short name T184
Test name
Test status
Simulation time 103693878 ps
CPU time 5.62 seconds
Started Jul 25 05:53:31 PM PDT 24
Finished Jul 25 05:53:37 PM PDT 24
Peak memory 211876 kb
Host smart-ad121a03-bff9-46bf-8a60-325ff44977a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613101123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.613101123
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.753270410
Short name T337
Test name
Test status
Simulation time 188511826 ps
CPU time 10.28 seconds
Started Jul 25 05:53:33 PM PDT 24
Finished Jul 25 05:53:44 PM PDT 24
Peak memory 214484 kb
Host smart-5b23e4e1-263d-4cd4-bd26-419df3c89349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753270410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.753270410
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2736871079
Short name T240
Test name
Test status
Simulation time 289165598 ps
CPU time 13.76 seconds
Started Jul 25 05:53:36 PM PDT 24
Finished Jul 25 05:53:50 PM PDT 24
Peak memory 214340 kb
Host smart-3103b503-26a3-4326-90d4-0ec1b514837a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736871079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2736871079
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2719177430
Short name T318
Test name
Test status
Simulation time 65038318717 ps
CPU time 1197.71 seconds
Started Jul 25 05:53:54 PM PDT 24
Finished Jul 25 06:13:52 PM PDT 24
Peak memory 236232 kb
Host smart-451beead-1d0a-4fbc-810f-0a83acc20b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719177430 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2719177430
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1069536459
Short name T253
Test name
Test status
Simulation time 619642492 ps
CPU time 5.1 seconds
Started Jul 25 05:53:32 PM PDT 24
Finished Jul 25 05:53:37 PM PDT 24
Peak memory 211800 kb
Host smart-197ab3cf-b543-41f8-8286-0dc82a046d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069536459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1069536459
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3343614299
Short name T132
Test name
Test status
Simulation time 169529708 ps
CPU time 9.46 seconds
Started Jul 25 05:53:34 PM PDT 24
Finished Jul 25 05:53:44 PM PDT 24
Peak memory 212748 kb
Host smart-030a48d2-8eae-4a67-a987-79047b6716b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343614299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3343614299
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2636978661
Short name T215
Test name
Test status
Simulation time 144043560 ps
CPU time 6.43 seconds
Started Jul 25 05:53:36 PM PDT 24
Finished Jul 25 05:53:43 PM PDT 24
Peak memory 211932 kb
Host smart-8ba08e2c-5bcc-464b-bdd6-cc859f06133f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2636978661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2636978661
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3771632488
Short name T211
Test name
Test status
Simulation time 1015800276 ps
CPU time 10.06 seconds
Started Jul 25 05:53:54 PM PDT 24
Finished Jul 25 05:54:04 PM PDT 24
Peak memory 214008 kb
Host smart-063ea872-cf72-45e3-a410-45b99b39cf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771632488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3771632488
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1372371713
Short name T282
Test name
Test status
Simulation time 462363880 ps
CPU time 5.87 seconds
Started Jul 25 05:53:32 PM PDT 24
Finished Jul 25 05:53:38 PM PDT 24
Peak memory 211860 kb
Host smart-e366e9e4-39f1-45bf-a8ad-cd112d6735a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372371713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1372371713
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2251068028
Short name T144
Test name
Test status
Simulation time 1130392163 ps
CPU time 5.22 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:53:48 PM PDT 24
Peak memory 211744 kb
Host smart-fa069b79-7328-4509-bf78-05782951d535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251068028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2251068028
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1776868161
Short name T35
Test name
Test status
Simulation time 14843423544 ps
CPU time 163.71 seconds
Started Jul 25 05:53:45 PM PDT 24
Finished Jul 25 05:56:29 PM PDT 24
Peak memory 214080 kb
Host smart-03ec928f-dd3f-4ea0-8f3d-fd6558dd659f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776868161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1776868161
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1371265582
Short name T37
Test name
Test status
Simulation time 696652012 ps
CPU time 9.37 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:53:52 PM PDT 24
Peak memory 212700 kb
Host smart-56894578-f452-42b5-9c76-1b03eba15392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371265582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1371265582
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1599167062
Short name T209
Test name
Test status
Simulation time 182231202 ps
CPU time 5.35 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:53:49 PM PDT 24
Peak memory 211928 kb
Host smart-a30af9ae-23de-47d6-b088-b9e0eec9a04f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599167062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1599167062
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.374118838
Short name T295
Test name
Test status
Simulation time 697908579 ps
CPU time 9.85 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:53:53 PM PDT 24
Peak memory 214492 kb
Host smart-e3ddfed6-fcc1-4d3f-aac7-f88994ee533b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374118838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.374118838
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1074569156
Short name T235
Test name
Test status
Simulation time 2232364588 ps
CPU time 22.76 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:54:06 PM PDT 24
Peak memory 216256 kb
Host smart-d08576db-5ceb-4797-ba24-d9110424aa68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074569156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1074569156
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1653042911
Short name T356
Test name
Test status
Simulation time 163534947355 ps
CPU time 626.46 seconds
Started Jul 25 05:53:44 PM PDT 24
Finished Jul 25 06:04:10 PM PDT 24
Peak memory 236404 kb
Host smart-6c4952fe-e9ba-443f-8dfe-8511c01f074f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653042911 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1653042911
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4116306584
Short name T243
Test name
Test status
Simulation time 350015749 ps
CPU time 4.33 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:53:47 PM PDT 24
Peak memory 211812 kb
Host smart-f5e08472-3ab6-4239-9399-20ae8506899d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116306584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4116306584
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2289940597
Short name T288
Test name
Test status
Simulation time 7797908347 ps
CPU time 137.88 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:56:01 PM PDT 24
Peak memory 238264 kb
Host smart-fa62e44b-7154-4e76-ac16-4b9122c47632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289940597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2289940597
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2084517653
Short name T320
Test name
Test status
Simulation time 2096841056 ps
CPU time 17 seconds
Started Jul 25 05:53:48 PM PDT 24
Finished Jul 25 05:54:05 PM PDT 24
Peak memory 212656 kb
Host smart-7204f5b9-cbe5-4175-9a5f-8c482a19be2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084517653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2084517653
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3300356956
Short name T110
Test name
Test status
Simulation time 370711782 ps
CPU time 5.4 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:53:48 PM PDT 24
Peak memory 211932 kb
Host smart-f4888ed4-df56-4764-b645-fb0251c2183f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300356956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3300356956
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1695496470
Short name T73
Test name
Test status
Simulation time 550568648 ps
CPU time 12.22 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:53:55 PM PDT 24
Peak memory 214564 kb
Host smart-259d0d2c-a0e9-4083-b77d-630d61133223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695496470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1695496470
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.653282610
Short name T350
Test name
Test status
Simulation time 381118849 ps
CPU time 14.37 seconds
Started Jul 25 05:53:44 PM PDT 24
Finished Jul 25 05:53:58 PM PDT 24
Peak memory 213120 kb
Host smart-14d7bb55-c8d8-4bc5-96b6-3b245e59394e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653282610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.653282610
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3501414975
Short name T340
Test name
Test status
Simulation time 537869010 ps
CPU time 5.1 seconds
Started Jul 25 05:52:48 PM PDT 24
Finished Jul 25 05:52:53 PM PDT 24
Peak memory 211804 kb
Host smart-6cb38c5d-4953-42b9-b74f-74db19c4356b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501414975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3501414975
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2731931791
Short name T285
Test name
Test status
Simulation time 8808049413 ps
CPU time 126.09 seconds
Started Jul 25 05:52:47 PM PDT 24
Finished Jul 25 05:54:53 PM PDT 24
Peak memory 238252 kb
Host smart-d02e0f8f-5fb9-4f29-a229-5c10b0214a04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731931791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2731931791
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.65282784
Short name T25
Test name
Test status
Simulation time 1132937006 ps
CPU time 11.4 seconds
Started Jul 25 05:52:47 PM PDT 24
Finished Jul 25 05:52:59 PM PDT 24
Peak memory 212800 kb
Host smart-579c3e0c-457b-4413-b014-e74fd2987109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65282784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.65282784
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.560311551
Short name T292
Test name
Test status
Simulation time 288396331 ps
CPU time 6.62 seconds
Started Jul 25 05:52:52 PM PDT 24
Finished Jul 25 05:52:59 PM PDT 24
Peak memory 211932 kb
Host smart-7dde3125-8715-44d5-a6d2-7b3e0d067695
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=560311551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.560311551
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2302879141
Short name T26
Test name
Test status
Simulation time 301622551 ps
CPU time 51.53 seconds
Started Jul 25 05:52:47 PM PDT 24
Finished Jul 25 05:53:38 PM PDT 24
Peak memory 237216 kb
Host smart-7cd63896-2966-4de3-99b2-bd321c823581
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302879141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2302879141
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.971914209
Short name T164
Test name
Test status
Simulation time 1056122070 ps
CPU time 10.21 seconds
Started Jul 25 05:52:49 PM PDT 24
Finished Jul 25 05:53:00 PM PDT 24
Peak memory 214768 kb
Host smart-a2f71939-8599-44cf-b7f5-8239d5be159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971914209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.971914209
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3627815689
Short name T189
Test name
Test status
Simulation time 411103309 ps
CPU time 23.57 seconds
Started Jul 25 05:52:47 PM PDT 24
Finished Jul 25 05:53:10 PM PDT 24
Peak memory 215672 kb
Host smart-dfdda1fa-a78b-4065-8854-76c17e0d323e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627815689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3627815689
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2022029512
Short name T346
Test name
Test status
Simulation time 784942964 ps
CPU time 5.08 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:53:47 PM PDT 24
Peak memory 211816 kb
Host smart-c9606ced-5d8e-4d73-9ef6-eea6ccb60ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022029512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2022029512
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4039076558
Short name T157
Test name
Test status
Simulation time 1472477180 ps
CPU time 99.97 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:55:23 PM PDT 24
Peak memory 237208 kb
Host smart-ee75bb77-d344-4e0d-b309-9d7fbb7a55e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039076558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4039076558
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.678558271
Short name T234
Test name
Test status
Simulation time 621646250 ps
CPU time 11.11 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:53:54 PM PDT 24
Peak memory 212740 kb
Host smart-c33263fb-53a1-4ea4-8f12-8a37496faa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678558271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.678558271
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2999438191
Short name T227
Test name
Test status
Simulation time 323550193 ps
CPU time 6.35 seconds
Started Jul 25 05:53:47 PM PDT 24
Finished Jul 25 05:53:53 PM PDT 24
Peak memory 211860 kb
Host smart-b73f8512-e33f-462d-953f-992f03ef7df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999438191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2999438191
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1069917216
Short name T72
Test name
Test status
Simulation time 1632048305 ps
CPU time 10.2 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:53:52 PM PDT 24
Peak memory 214356 kb
Host smart-0b390f59-2f46-4f58-aabf-4d4eb9f0d099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069917216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1069917216
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1498419414
Short name T278
Test name
Test status
Simulation time 1406795493 ps
CPU time 21.91 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:54:05 PM PDT 24
Peak memory 214928 kb
Host smart-4d1c62da-1d15-46e1-89e1-c583a0dbfa56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498419414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1498419414
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.854155401
Short name T314
Test name
Test status
Simulation time 56519656159 ps
CPU time 1122.07 seconds
Started Jul 25 05:53:41 PM PDT 24
Finished Jul 25 06:12:24 PM PDT 24
Peak memory 236300 kb
Host smart-3b1f06f3-0fab-4718-bb1d-8ca2026e0af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854155401 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.854155401
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.766160774
Short name T373
Test name
Test status
Simulation time 132393637 ps
CPU time 5.22 seconds
Started Jul 25 05:53:45 PM PDT 24
Finished Jul 25 05:53:51 PM PDT 24
Peak memory 211808 kb
Host smart-2180f12e-e9f0-46ca-ab14-1e1e4314f60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766160774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.766160774
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2080158356
Short name T270
Test name
Test status
Simulation time 1706671823 ps
CPU time 101.76 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:55:25 PM PDT 24
Peak memory 228468 kb
Host smart-5e44e738-5ca1-41a8-aa81-2dcd4bce808c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080158356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2080158356
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.39569814
Short name T370
Test name
Test status
Simulation time 1039362779 ps
CPU time 11.58 seconds
Started Jul 25 05:53:44 PM PDT 24
Finished Jul 25 05:53:56 PM PDT 24
Peak memory 212620 kb
Host smart-04e2604b-1492-4265-9112-ca5562bccb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39569814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.39569814
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3166712711
Short name T202
Test name
Test status
Simulation time 1342773381 ps
CPU time 6.56 seconds
Started Jul 25 05:53:45 PM PDT 24
Finished Jul 25 05:53:52 PM PDT 24
Peak memory 211860 kb
Host smart-89b2a106-05fd-4bdc-80ae-a649d2a8b405
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166712711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3166712711
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4120514955
Short name T317
Test name
Test status
Simulation time 276577289 ps
CPU time 11.73 seconds
Started Jul 25 05:53:40 PM PDT 24
Finished Jul 25 05:53:52 PM PDT 24
Peak memory 213864 kb
Host smart-69972b74-f6f0-4075-880d-28912d7d183a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120514955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4120514955
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1422418441
Short name T338
Test name
Test status
Simulation time 2461682241 ps
CPU time 19.93 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:54:02 PM PDT 24
Peak memory 214512 kb
Host smart-62ef2ad8-d8f0-42ca-9976-c1f754ad017a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422418441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1422418441
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.193073219
Short name T279
Test name
Test status
Simulation time 13090165192 ps
CPU time 153.22 seconds
Started Jul 25 05:53:44 PM PDT 24
Finished Jul 25 05:56:17 PM PDT 24
Peak memory 235332 kb
Host smart-b167954b-73c5-4944-bddc-d41e38801b3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193073219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.193073219
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1816848925
Short name T229
Test name
Test status
Simulation time 994119898 ps
CPU time 11.47 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:53:54 PM PDT 24
Peak memory 212748 kb
Host smart-e673411c-16d0-457a-bb04-cadcf529d9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816848925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1816848925
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.718673522
Short name T187
Test name
Test status
Simulation time 790749020 ps
CPU time 5.85 seconds
Started Jul 25 05:53:45 PM PDT 24
Finished Jul 25 05:53:51 PM PDT 24
Peak memory 211904 kb
Host smart-e458334f-b8fc-48d1-9af1-be78a9110b86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=718673522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.718673522
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.294415578
Short name T42
Test name
Test status
Simulation time 3676627003 ps
CPU time 11.71 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:53:55 PM PDT 24
Peak memory 214776 kb
Host smart-1e9dfdd4-fa57-4b42-b424-612e58e8da35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294415578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.294415578
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1620745395
Short name T141
Test name
Test status
Simulation time 1181591868 ps
CPU time 12.19 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:53:55 PM PDT 24
Peak memory 214636 kb
Host smart-00189687-8f5d-41e3-9a7d-a68860bde328
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620745395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1620745395
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3713430255
Short name T114
Test name
Test status
Simulation time 26966455454 ps
CPU time 1121.94 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 06:12:24 PM PDT 24
Peak memory 236376 kb
Host smart-06eed09a-9217-4302-8f12-cbdec0a2a1ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713430255 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3713430255
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2969680894
Short name T291
Test name
Test status
Simulation time 2069625778 ps
CPU time 5.22 seconds
Started Jul 25 05:53:59 PM PDT 24
Finished Jul 25 05:54:05 PM PDT 24
Peak memory 211776 kb
Host smart-2fbf6784-49fa-4acd-b9b9-d99c2473aeff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969680894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2969680894
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.358228725
Short name T242
Test name
Test status
Simulation time 4610562497 ps
CPU time 109.44 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:55:32 PM PDT 24
Peak memory 225868 kb
Host smart-57c64867-8087-457d-aebf-e1db46509fbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358228725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.358228725
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1834952081
Short name T134
Test name
Test status
Simulation time 480832725 ps
CPU time 11.5 seconds
Started Jul 25 05:53:54 PM PDT 24
Finished Jul 25 05:54:05 PM PDT 24
Peak memory 212780 kb
Host smart-09036c6e-6b5e-4964-b5f8-8fa0ef86885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834952081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1834952081
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2590052980
Short name T365
Test name
Test status
Simulation time 97249980 ps
CPU time 5.81 seconds
Started Jul 25 05:53:42 PM PDT 24
Finished Jul 25 05:53:49 PM PDT 24
Peak memory 211920 kb
Host smart-fb2ec9a9-757d-4d81-9937-8375b69acf5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2590052980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2590052980
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4108675566
Short name T63
Test name
Test status
Simulation time 1094590171 ps
CPU time 11.97 seconds
Started Jul 25 05:53:41 PM PDT 24
Finished Jul 25 05:53:53 PM PDT 24
Peak memory 214132 kb
Host smart-4b06a336-adeb-4af8-bd61-9e85daaa7e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108675566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4108675566
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4127671410
Short name T362
Test name
Test status
Simulation time 635556951 ps
CPU time 37.66 seconds
Started Jul 25 05:53:43 PM PDT 24
Finished Jul 25 05:54:21 PM PDT 24
Peak memory 215852 kb
Host smart-952cb138-25d1-4238-b463-6e9d11673002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127671410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4127671410
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2967086250
Short name T305
Test name
Test status
Simulation time 90832969656 ps
CPU time 3314.69 seconds
Started Jul 25 05:53:52 PM PDT 24
Finished Jul 25 06:49:07 PM PDT 24
Peak memory 244056 kb
Host smart-001d59e5-a4ef-417c-a608-1268e241f185
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967086250 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2967086250
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1946809453
Short name T219
Test name
Test status
Simulation time 555002429 ps
CPU time 4.11 seconds
Started Jul 25 05:53:53 PM PDT 24
Finished Jul 25 05:53:57 PM PDT 24
Peak memory 211804 kb
Host smart-4b1b2d8a-9874-4666-a2fd-8a23ba5aed74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946809453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1946809453
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1159727235
Short name T161
Test name
Test status
Simulation time 3719975448 ps
CPU time 87.8 seconds
Started Jul 25 05:53:52 PM PDT 24
Finished Jul 25 05:55:19 PM PDT 24
Peak memory 225804 kb
Host smart-e6a66aa0-9c2a-4fe1-8505-4afa33dddfae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159727235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1159727235
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.756746873
Short name T195
Test name
Test status
Simulation time 463515309 ps
CPU time 9.5 seconds
Started Jul 25 05:53:53 PM PDT 24
Finished Jul 25 05:54:03 PM PDT 24
Peak memory 212608 kb
Host smart-a3ef4ec4-2e55-470a-aef1-a37dc9c23c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756746873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.756746873
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3100215761
Short name T102
Test name
Test status
Simulation time 275649343 ps
CPU time 6.69 seconds
Started Jul 25 05:53:54 PM PDT 24
Finished Jul 25 05:54:00 PM PDT 24
Peak memory 211856 kb
Host smart-63a9fa0a-f024-4688-af12-00e8a3c50677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100215761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3100215761
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.708379512
Short name T205
Test name
Test status
Simulation time 542379887 ps
CPU time 11.94 seconds
Started Jul 25 05:53:59 PM PDT 24
Finished Jul 25 05:54:11 PM PDT 24
Peak memory 212940 kb
Host smart-5c33a89e-f1e1-4a70-b4ec-93ede213a880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708379512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.708379512
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1584871782
Short name T281
Test name
Test status
Simulation time 4086836051 ps
CPU time 33.27 seconds
Started Jul 25 05:53:54 PM PDT 24
Finished Jul 25 05:54:28 PM PDT 24
Peak memory 216116 kb
Host smart-e8e5fe13-b79f-4aa3-bace-b6594a185267
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584871782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1584871782
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1709083190
Short name T111
Test name
Test status
Simulation time 132434298 ps
CPU time 5.06 seconds
Started Jul 25 05:53:51 PM PDT 24
Finished Jul 25 05:53:56 PM PDT 24
Peak memory 211824 kb
Host smart-2b269337-88e3-43dd-9db6-300826f747ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709083190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1709083190
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2398570413
Short name T265
Test name
Test status
Simulation time 13357270212 ps
CPU time 196.17 seconds
Started Jul 25 05:53:50 PM PDT 24
Finished Jul 25 05:57:07 PM PDT 24
Peak memory 235352 kb
Host smart-ba2ef77b-2b18-4b0b-8991-93dbb8918eca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398570413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2398570413
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2182514581
Short name T363
Test name
Test status
Simulation time 956396970 ps
CPU time 11.01 seconds
Started Jul 25 05:54:12 PM PDT 24
Finished Jul 25 05:54:23 PM PDT 24
Peak memory 212648 kb
Host smart-7fda586c-483b-4b50-893e-ebf4dcde5e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182514581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2182514581
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2223709477
Short name T326
Test name
Test status
Simulation time 187967010 ps
CPU time 6.58 seconds
Started Jul 25 05:53:50 PM PDT 24
Finished Jul 25 05:53:56 PM PDT 24
Peak memory 211880 kb
Host smart-72ac3270-d8c3-4844-ad12-d2ae19dd797f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223709477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2223709477
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2509114573
Short name T190
Test name
Test status
Simulation time 1175793283 ps
CPU time 11.92 seconds
Started Jul 25 05:53:51 PM PDT 24
Finished Jul 25 05:54:03 PM PDT 24
Peak memory 213892 kb
Host smart-55d569b9-5b01-435c-b599-660156e940c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509114573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2509114573
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4264463086
Short name T262
Test name
Test status
Simulation time 3002040330 ps
CPU time 34.78 seconds
Started Jul 25 05:53:55 PM PDT 24
Finished Jul 25 05:54:30 PM PDT 24
Peak memory 216308 kb
Host smart-baee5407-6449-405c-8683-77c0aaa7404c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264463086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4264463086
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1260781654
Short name T233
Test name
Test status
Simulation time 504907829 ps
CPU time 7.37 seconds
Started Jul 25 05:53:51 PM PDT 24
Finished Jul 25 05:53:58 PM PDT 24
Peak memory 211808 kb
Host smart-62e834da-33ba-48c6-9d89-cec5f9ccba42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260781654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1260781654
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4146882691
Short name T173
Test name
Test status
Simulation time 2107789009 ps
CPU time 93.25 seconds
Started Jul 25 05:53:53 PM PDT 24
Finished Jul 25 05:55:27 PM PDT 24
Peak memory 212972 kb
Host smart-be4f85ef-2f8e-43f3-86c6-2929aef1cbb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146882691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4146882691
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3640937032
Short name T170
Test name
Test status
Simulation time 261714978 ps
CPU time 11.66 seconds
Started Jul 25 05:53:51 PM PDT 24
Finished Jul 25 05:54:03 PM PDT 24
Peak memory 212604 kb
Host smart-355e9024-ad34-485e-b2e3-fa7122cdf4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640937032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3640937032
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2270065468
Short name T264
Test name
Test status
Simulation time 336371552 ps
CPU time 5.66 seconds
Started Jul 25 05:53:54 PM PDT 24
Finished Jul 25 05:53:59 PM PDT 24
Peak memory 211948 kb
Host smart-48e39833-4a74-4b23-8918-00132ebdc919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270065468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2270065468
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.572278190
Short name T260
Test name
Test status
Simulation time 806835901 ps
CPU time 12.12 seconds
Started Jul 25 05:53:53 PM PDT 24
Finished Jul 25 05:54:05 PM PDT 24
Peak memory 214364 kb
Host smart-b4db610e-2630-49ca-8028-a27c428e8b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572278190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.572278190
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1022366186
Short name T378
Test name
Test status
Simulation time 108101736 ps
CPU time 6.02 seconds
Started Jul 25 05:53:52 PM PDT 24
Finished Jul 25 05:53:58 PM PDT 24
Peak memory 211856 kb
Host smart-6853143f-1d74-41d2-91b2-bd8c0261b6d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022366186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1022366186
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4165838729
Short name T115
Test name
Test status
Simulation time 113426152165 ps
CPU time 2380.48 seconds
Started Jul 25 05:53:54 PM PDT 24
Finished Jul 25 06:33:35 PM PDT 24
Peak memory 244520 kb
Host smart-e80ab2ec-0ff9-44ef-9de2-d9da725bb4f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165838729 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.4165838729
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.515319874
Short name T287
Test name
Test status
Simulation time 544515890 ps
CPU time 5.08 seconds
Started Jul 25 05:53:55 PM PDT 24
Finished Jul 25 05:54:00 PM PDT 24
Peak memory 211824 kb
Host smart-0c5de3ba-3f3b-4e02-bf8f-6f3c12791a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515319874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.515319874
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2824269023
Short name T188
Test name
Test status
Simulation time 2020546479 ps
CPU time 90.25 seconds
Started Jul 25 05:53:53 PM PDT 24
Finished Jul 25 05:55:23 PM PDT 24
Peak memory 237200 kb
Host smart-aaa82fb1-45c8-4e94-8336-a286dd1a2e73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824269023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2824269023
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.20964794
Short name T377
Test name
Test status
Simulation time 722448107 ps
CPU time 9.66 seconds
Started Jul 25 05:53:52 PM PDT 24
Finished Jul 25 05:54:02 PM PDT 24
Peak memory 212652 kb
Host smart-38d4a0e4-7533-4fb7-9661-8c4a3f30a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20964794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.20964794
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3158699649
Short name T198
Test name
Test status
Simulation time 96132379 ps
CPU time 5.35 seconds
Started Jul 25 05:53:52 PM PDT 24
Finished Jul 25 05:53:58 PM PDT 24
Peak memory 211908 kb
Host smart-8242fb1f-1dc6-4135-a68d-df17a5d73f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158699649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3158699649
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.917867064
Short name T300
Test name
Test status
Simulation time 642921715 ps
CPU time 12.11 seconds
Started Jul 25 05:53:55 PM PDT 24
Finished Jul 25 05:54:08 PM PDT 24
Peak memory 213908 kb
Host smart-779a30ce-9ab0-4b79-8b67-ff869170d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917867064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.917867064
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.958617061
Short name T180
Test name
Test status
Simulation time 621216680 ps
CPU time 17.89 seconds
Started Jul 25 05:53:51 PM PDT 24
Finished Jul 25 05:54:09 PM PDT 24
Peak memory 214864 kb
Host smart-67d55b13-7cb3-4c09-ae7b-7f97a272d412
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958617061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.958617061
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4204876349
Short name T325
Test name
Test status
Simulation time 127885095584 ps
CPU time 5383.53 seconds
Started Jul 25 05:53:55 PM PDT 24
Finished Jul 25 07:23:39 PM PDT 24
Peak memory 236312 kb
Host smart-fda28938-f47c-4857-b0fb-26b032998d32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204876349 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.4204876349
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1185754131
Short name T31
Test name
Test status
Simulation time 262820716 ps
CPU time 5.12 seconds
Started Jul 25 05:53:56 PM PDT 24
Finished Jul 25 05:54:01 PM PDT 24
Peak memory 211816 kb
Host smart-8f6c9cd8-13c4-4701-85f2-df964b9d293a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185754131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1185754131
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3362877065
Short name T128
Test name
Test status
Simulation time 14619152252 ps
CPU time 187.64 seconds
Started Jul 25 05:53:56 PM PDT 24
Finished Jul 25 05:57:04 PM PDT 24
Peak memory 238260 kb
Host smart-773e4304-0343-42e2-b79a-43397a0f9e61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362877065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3362877065
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1128985709
Short name T248
Test name
Test status
Simulation time 781329208 ps
CPU time 11.47 seconds
Started Jul 25 05:53:53 PM PDT 24
Finished Jul 25 05:54:05 PM PDT 24
Peak memory 212728 kb
Host smart-8eac4e3c-5101-418d-95be-9ffe3d7a9f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128985709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1128985709
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1415727759
Short name T334
Test name
Test status
Simulation time 560533019 ps
CPU time 6.63 seconds
Started Jul 25 05:57:22 PM PDT 24
Finished Jul 25 05:57:29 PM PDT 24
Peak memory 211908 kb
Host smart-56b3583f-83f7-43c2-9132-ad4c1b22238c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415727759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1415727759
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3741660662
Short name T277
Test name
Test status
Simulation time 277587172 ps
CPU time 11.84 seconds
Started Jul 25 05:53:53 PM PDT 24
Finished Jul 25 05:54:05 PM PDT 24
Peak memory 213000 kb
Host smart-80905cb7-e954-426b-96cb-4930bcd1c937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741660662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3741660662
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1912019751
Short name T155
Test name
Test status
Simulation time 560748174 ps
CPU time 18.14 seconds
Started Jul 25 05:53:53 PM PDT 24
Finished Jul 25 05:54:12 PM PDT 24
Peak memory 214576 kb
Host smart-a3c97ac3-5ac1-401f-9d26-6049cd018239
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912019751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1912019751
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3344271323
Short name T283
Test name
Test status
Simulation time 132663998 ps
CPU time 5.26 seconds
Started Jul 25 05:53:51 PM PDT 24
Finished Jul 25 05:53:57 PM PDT 24
Peak memory 211796 kb
Host smart-babb91b2-336c-4be7-a910-317b9c648c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344271323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3344271323
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1228466447
Short name T228
Test name
Test status
Simulation time 15047698597 ps
CPU time 90.35 seconds
Started Jul 25 05:53:55 PM PDT 24
Finished Jul 25 05:55:26 PM PDT 24
Peak memory 212832 kb
Host smart-3bf72fc8-f77d-4fea-8f26-90c48b144431
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228466447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1228466447
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.720779428
Short name T159
Test name
Test status
Simulation time 2778316685 ps
CPU time 9.36 seconds
Started Jul 25 05:53:55 PM PDT 24
Finished Jul 25 05:54:04 PM PDT 24
Peak memory 212760 kb
Host smart-fc70180e-9b53-4d75-852e-44b26c9b2ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720779428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.720779428
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.500269249
Short name T206
Test name
Test status
Simulation time 201930343 ps
CPU time 6.64 seconds
Started Jul 25 05:53:52 PM PDT 24
Finished Jul 25 05:53:59 PM PDT 24
Peak memory 211940 kb
Host smart-c243c9ed-822f-4007-9348-1e666eaf97bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500269249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.500269249
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.928946056
Short name T179
Test name
Test status
Simulation time 5084000702 ps
CPU time 11.16 seconds
Started Jul 25 05:53:56 PM PDT 24
Finished Jul 25 05:54:07 PM PDT 24
Peak memory 213596 kb
Host smart-853db6b0-0a08-482e-8842-3dc7cb422284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928946056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.928946056
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1485536828
Short name T172
Test name
Test status
Simulation time 130311019 ps
CPU time 6.13 seconds
Started Jul 25 05:54:10 PM PDT 24
Finished Jul 25 05:54:16 PM PDT 24
Peak memory 211728 kb
Host smart-55aab96e-bdf2-4680-aff4-7ebab6434380
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485536828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1485536828
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.721572452
Short name T272
Test name
Test status
Simulation time 88381524 ps
CPU time 4.34 seconds
Started Jul 25 05:52:52 PM PDT 24
Finished Jul 25 05:52:56 PM PDT 24
Peak memory 211780 kb
Host smart-ce840b36-fd0a-4008-b2a4-8829bffbb4e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721572452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.721572452
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2790391813
Short name T301
Test name
Test status
Simulation time 22187113254 ps
CPU time 80.84 seconds
Started Jul 25 05:52:53 PM PDT 24
Finished Jul 25 05:54:14 PM PDT 24
Peak memory 216892 kb
Host smart-d5c6166c-b726-42a6-84fc-ff326357950a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790391813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2790391813
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2873911878
Short name T344
Test name
Test status
Simulation time 341818186 ps
CPU time 9.43 seconds
Started Jul 25 05:52:48 PM PDT 24
Finished Jul 25 05:52:57 PM PDT 24
Peak memory 212632 kb
Host smart-1b8183a8-bd5c-490b-9f89-0791d72bf7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873911878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2873911878
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.629028303
Short name T376
Test name
Test status
Simulation time 98347777 ps
CPU time 5.46 seconds
Started Jul 25 05:52:49 PM PDT 24
Finished Jul 25 05:52:55 PM PDT 24
Peak memory 211936 kb
Host smart-b714526f-edda-4bea-855b-6c92d73c67c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=629028303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.629028303
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3915739597
Short name T185
Test name
Test status
Simulation time 277202305 ps
CPU time 11.98 seconds
Started Jul 25 05:52:50 PM PDT 24
Finished Jul 25 05:53:02 PM PDT 24
Peak memory 214156 kb
Host smart-0e841a5e-c96a-4a99-a27e-7d5afa5c5134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915739597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3915739597
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3670585234
Short name T343
Test name
Test status
Simulation time 564943375 ps
CPU time 30.75 seconds
Started Jul 25 05:52:49 PM PDT 24
Finished Jul 25 05:53:20 PM PDT 24
Peak memory 217492 kb
Host smart-f8034f91-5ae5-4e76-8bf4-562a8599a483
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670585234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3670585234
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1777890350
Short name T143
Test name
Test status
Simulation time 379484361 ps
CPU time 4.24 seconds
Started Jul 25 05:52:46 PM PDT 24
Finished Jul 25 05:52:50 PM PDT 24
Peak memory 211800 kb
Host smart-58531fa8-0fe0-4fcc-bdcb-f39fdf4b2f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777890350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1777890350
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3376232857
Short name T19
Test name
Test status
Simulation time 1839553328 ps
CPU time 84.81 seconds
Started Jul 25 05:52:49 PM PDT 24
Finished Jul 25 05:54:14 PM PDT 24
Peak memory 213056 kb
Host smart-a7a535ab-54d9-4337-a134-a8190d5a598b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376232857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3376232857
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.479593548
Short name T96
Test name
Test status
Simulation time 1038139658 ps
CPU time 11.28 seconds
Started Jul 25 05:52:51 PM PDT 24
Finished Jul 25 05:53:02 PM PDT 24
Peak memory 212732 kb
Host smart-7798ebc0-7bbf-4708-a8cc-7e344e303c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479593548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.479593548
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1113044756
Short name T252
Test name
Test status
Simulation time 273067484 ps
CPU time 6.98 seconds
Started Jul 25 05:52:56 PM PDT 24
Finished Jul 25 05:53:03 PM PDT 24
Peak memory 211908 kb
Host smart-82d10935-02b0-4df3-937e-f8be9d43a99c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113044756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1113044756
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.996139573
Short name T74
Test name
Test status
Simulation time 1050293888 ps
CPU time 12.62 seconds
Started Jul 25 05:52:52 PM PDT 24
Finished Jul 25 05:53:05 PM PDT 24
Peak memory 213844 kb
Host smart-ff13c1a5-290d-46a9-bf41-d6a73874a98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996139573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.996139573
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3099296400
Short name T359
Test name
Test status
Simulation time 224430678 ps
CPU time 6.95 seconds
Started Jul 25 05:52:58 PM PDT 24
Finished Jul 25 05:53:05 PM PDT 24
Peak memory 211764 kb
Host smart-5543682e-d261-42a4-8004-a47a9afb3730
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099296400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3099296400
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.788010025
Short name T339
Test name
Test status
Simulation time 46683773686 ps
CPU time 443.9 seconds
Started Jul 25 05:52:49 PM PDT 24
Finished Jul 25 06:00:13 PM PDT 24
Peak memory 236388 kb
Host smart-9c7c6acf-33b2-457b-854f-ce907786302d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788010025 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.788010025
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1364425711
Short name T214
Test name
Test status
Simulation time 132528808 ps
CPU time 5.13 seconds
Started Jul 25 05:52:52 PM PDT 24
Finished Jul 25 05:52:57 PM PDT 24
Peak memory 211804 kb
Host smart-78140419-a2ca-45de-9e06-05c27d7bbf03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364425711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1364425711
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2837360232
Short name T92
Test name
Test status
Simulation time 260723261 ps
CPU time 11.51 seconds
Started Jul 25 05:52:50 PM PDT 24
Finished Jul 25 05:53:01 PM PDT 24
Peak memory 212700 kb
Host smart-b7b05a5a-6142-4b33-b458-e6820386c10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837360232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2837360232
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3716986335
Short name T108
Test name
Test status
Simulation time 273234936 ps
CPU time 6.23 seconds
Started Jul 25 05:52:50 PM PDT 24
Finished Jul 25 05:52:57 PM PDT 24
Peak memory 211908 kb
Host smart-db7e8f38-a8ce-4940-aae1-d409d77e24ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716986335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3716986335
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1276698840
Short name T360
Test name
Test status
Simulation time 276548753 ps
CPU time 11.63 seconds
Started Jul 25 05:52:45 PM PDT 24
Finished Jul 25 05:52:57 PM PDT 24
Peak memory 214540 kb
Host smart-c93bcb7b-b1d6-4417-b35b-6dd6a494a407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276698840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1276698840
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.91212501
Short name T109
Test name
Test status
Simulation time 10878844380 ps
CPU time 29.07 seconds
Started Jul 25 05:52:51 PM PDT 24
Finished Jul 25 05:53:21 PM PDT 24
Peak memory 218076 kb
Host smart-ac34c8cd-b68f-4d7d-b1a7-99233452acbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91212501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.rom_ctrl_stress_all.91212501
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.717983273
Short name T47
Test name
Test status
Simulation time 270092943078 ps
CPU time 767.72 seconds
Started Jul 25 05:52:50 PM PDT 24
Finished Jul 25 06:05:38 PM PDT 24
Peak memory 230864 kb
Host smart-c716c2e8-7e03-454d-a0cb-147befe6d6d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717983273 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.717983273
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1451413347
Short name T327
Test name
Test status
Simulation time 500073061 ps
CPU time 7.73 seconds
Started Jul 25 05:52:52 PM PDT 24
Finished Jul 25 05:53:00 PM PDT 24
Peak memory 211772 kb
Host smart-70ae511e-04d2-4711-a9fb-1cc50aef1488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451413347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1451413347
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1714828208
Short name T212
Test name
Test status
Simulation time 8133271716 ps
CPU time 96.64 seconds
Started Jul 25 05:52:47 PM PDT 24
Finished Jul 25 05:54:24 PM PDT 24
Peak memory 238304 kb
Host smart-31f5ceb4-7f74-4e1c-a828-bb25cff61538
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714828208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1714828208
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3822931751
Short name T197
Test name
Test status
Simulation time 334850111 ps
CPU time 9.35 seconds
Started Jul 25 05:52:47 PM PDT 24
Finished Jul 25 05:52:57 PM PDT 24
Peak memory 212804 kb
Host smart-aecbc2f3-7ee9-4cc9-a04e-8cc0fb6c1120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822931751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3822931751
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1068198374
Short name T165
Test name
Test status
Simulation time 527153626 ps
CPU time 8.79 seconds
Started Jul 25 05:52:53 PM PDT 24
Finished Jul 25 05:53:02 PM PDT 24
Peak memory 211928 kb
Host smart-5cd8bfd8-38dc-4444-b4de-eb7f38f45aad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068198374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1068198374
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4032512915
Short name T259
Test name
Test status
Simulation time 188154698 ps
CPU time 10.46 seconds
Started Jul 25 05:52:52 PM PDT 24
Finished Jul 25 05:53:02 PM PDT 24
Peak memory 213964 kb
Host smart-253673f4-a9d5-4ff7-83bb-bd820273510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032512915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4032512915
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3429957123
Short name T57
Test name
Test status
Simulation time 581841184 ps
CPU time 19.79 seconds
Started Jul 25 05:52:47 PM PDT 24
Finished Jul 25 05:53:07 PM PDT 24
Peak memory 214784 kb
Host smart-aec80a5f-eeac-485d-9f1f-317950935971
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429957123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3429957123
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3766270834
Short name T196
Test name
Test status
Simulation time 320416611 ps
CPU time 4.47 seconds
Started Jul 25 05:52:48 PM PDT 24
Finished Jul 25 05:52:53 PM PDT 24
Peak memory 211744 kb
Host smart-a2ecc30b-39e4-41ac-b2bc-8af4c3fda10c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766270834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3766270834
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4240599131
Short name T167
Test name
Test status
Simulation time 8652869010 ps
CPU time 132.93 seconds
Started Jul 25 05:52:51 PM PDT 24
Finished Jul 25 05:55:04 PM PDT 24
Peak memory 235508 kb
Host smart-5e303685-81b7-4c0c-a570-3be02fc7cb7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240599131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4240599131
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2328970157
Short name T237
Test name
Test status
Simulation time 513162309 ps
CPU time 11.14 seconds
Started Jul 25 05:52:46 PM PDT 24
Finished Jul 25 05:52:57 PM PDT 24
Peak memory 212672 kb
Host smart-26efcdf1-19d6-4a4c-86ae-a8e2125abcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328970157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2328970157
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.802071391
Short name T13
Test name
Test status
Simulation time 96395550 ps
CPU time 5.41 seconds
Started Jul 25 05:52:50 PM PDT 24
Finished Jul 25 05:52:55 PM PDT 24
Peak memory 211860 kb
Host smart-1847a02b-62c1-4361-a920-a0eb039cf4d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=802071391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.802071391
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3723168238
Short name T17
Test name
Test status
Simulation time 3992389331 ps
CPU time 16.55 seconds
Started Jul 25 05:52:53 PM PDT 24
Finished Jul 25 05:53:09 PM PDT 24
Peak memory 214004 kb
Host smart-f4080e14-f175-494a-a5ec-d730b0037fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723168238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3723168238
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.522914558
Short name T56
Test name
Test status
Simulation time 286586451 ps
CPU time 19.55 seconds
Started Jul 25 05:52:46 PM PDT 24
Finished Jul 25 05:53:06 PM PDT 24
Peak memory 214260 kb
Host smart-b6d933d2-b7e1-4804-923a-a32138d7d128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522914558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.522914558
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.409568785
Short name T46
Test name
Test status
Simulation time 15950441281 ps
CPU time 632.32 seconds
Started Jul 25 05:52:50 PM PDT 24
Finished Jul 25 06:03:22 PM PDT 24
Peak memory 228752 kb
Host smart-0846d435-3ad0-4217-a5c4-986bae60ffa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409568785 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.409568785
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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