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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.67 100.00 98.28 97.30 98.37


Total test records in report: 481
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T298 /workspace/coverage/default/43.rom_ctrl_alert_test.1978441625 Jul 26 05:37:44 PM PDT 24 Jul 26 05:37:49 PM PDT 24 334081997 ps
T299 /workspace/coverage/default/33.rom_ctrl_alert_test.241622199 Jul 26 05:37:28 PM PDT 24 Jul 26 05:37:32 PM PDT 24 553627753 ps
T300 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4023327154 Jul 26 05:37:44 PM PDT 24 Jul 26 05:40:09 PM PDT 24 11495616019 ps
T301 /workspace/coverage/default/34.rom_ctrl_smoke.3459576086 Jul 26 05:37:29 PM PDT 24 Jul 26 05:37:40 PM PDT 24 187508702 ps
T302 /workspace/coverage/default/19.rom_ctrl_stress_all.3413501221 Jul 26 05:37:09 PM PDT 24 Jul 26 05:37:36 PM PDT 24 1162539637 ps
T303 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.4131433620 Jul 26 05:36:50 PM PDT 24 Jul 26 06:09:30 PM PDT 24 202710166273 ps
T304 /workspace/coverage/default/46.rom_ctrl_alert_test.3406724020 Jul 26 05:37:44 PM PDT 24 Jul 26 05:37:50 PM PDT 24 134462607 ps
T305 /workspace/coverage/default/2.rom_ctrl_alert_test.1578172876 Jul 26 05:36:36 PM PDT 24 Jul 26 05:36:41 PM PDT 24 133670462 ps
T306 /workspace/coverage/default/34.rom_ctrl_stress_all.538197090 Jul 26 05:37:32 PM PDT 24 Jul 26 05:38:10 PM PDT 24 3388583183 ps
T307 /workspace/coverage/default/28.rom_ctrl_smoke.2390606245 Jul 26 05:37:25 PM PDT 24 Jul 26 05:37:38 PM PDT 24 553066479 ps
T308 /workspace/coverage/default/40.rom_ctrl_stress_all.1300616047 Jul 26 05:37:43 PM PDT 24 Jul 26 05:38:03 PM PDT 24 2525243582 ps
T309 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2936234325 Jul 26 05:37:49 PM PDT 24 Jul 26 05:38:01 PM PDT 24 1455935324 ps
T310 /workspace/coverage/default/27.rom_ctrl_smoke.3210385061 Jul 26 05:37:29 PM PDT 24 Jul 26 05:37:46 PM PDT 24 996984861 ps
T311 /workspace/coverage/default/19.rom_ctrl_smoke.130120738 Jul 26 05:36:58 PM PDT 24 Jul 26 05:37:16 PM PDT 24 1001572877 ps
T312 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4214480578 Jul 26 05:37:10 PM PDT 24 Jul 26 05:37:26 PM PDT 24 2048085659 ps
T313 /workspace/coverage/default/6.rom_ctrl_smoke.3507743060 Jul 26 05:36:34 PM PDT 24 Jul 26 05:36:52 PM PDT 24 1998058210 ps
T314 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2061971680 Jul 26 05:37:29 PM PDT 24 Jul 26 08:31:15 PM PDT 24 27445027131 ps
T315 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.349127414 Jul 26 05:36:48 PM PDT 24 Jul 26 05:36:54 PM PDT 24 140253818 ps
T316 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1560186108 Jul 26 05:36:57 PM PDT 24 Jul 26 05:37:07 PM PDT 24 169759609 ps
T317 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1276449913 Jul 26 05:37:32 PM PDT 24 Jul 26 05:37:43 PM PDT 24 254903413 ps
T318 /workspace/coverage/default/39.rom_ctrl_alert_test.3067590357 Jul 26 05:37:41 PM PDT 24 Jul 26 05:37:45 PM PDT 24 171641171 ps
T319 /workspace/coverage/default/32.rom_ctrl_alert_test.3419642477 Jul 26 05:37:27 PM PDT 24 Jul 26 05:37:31 PM PDT 24 521018750 ps
T320 /workspace/coverage/default/33.rom_ctrl_smoke.1627394484 Jul 26 05:37:28 PM PDT 24 Jul 26 05:37:40 PM PDT 24 277256795 ps
T321 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1458378080 Jul 26 05:36:39 PM PDT 24 Jul 26 05:37:43 PM PDT 24 1398402146 ps
T322 /workspace/coverage/default/11.rom_ctrl_alert_test.224591135 Jul 26 05:36:41 PM PDT 24 Jul 26 05:36:46 PM PDT 24 175340796 ps
T323 /workspace/coverage/default/32.rom_ctrl_smoke.1014087234 Jul 26 05:37:30 PM PDT 24 Jul 26 05:37:42 PM PDT 24 1029046982 ps
T324 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3568747755 Jul 26 05:36:37 PM PDT 24 Jul 26 05:38:36 PM PDT 24 2140124999 ps
T325 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.926026674 Jul 26 05:37:28 PM PDT 24 Jul 26 05:39:51 PM PDT 24 5049881196 ps
T326 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2625455001 Jul 26 05:36:58 PM PDT 24 Jul 26 05:39:04 PM PDT 24 2106009867 ps
T327 /workspace/coverage/default/25.rom_ctrl_alert_test.2160500622 Jul 26 05:37:26 PM PDT 24 Jul 26 05:37:31 PM PDT 24 518558240 ps
T328 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.629042155 Jul 26 05:37:34 PM PDT 24 Jul 26 05:39:40 PM PDT 24 9349839738 ps
T329 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2079491791 Jul 26 05:36:35 PM PDT 24 Jul 26 05:48:11 PM PDT 24 18171495494 ps
T330 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1024345835 Jul 26 05:37:44 PM PDT 24 Jul 26 05:37:54 PM PDT 24 183138708 ps
T331 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.412304521 Jul 26 05:37:32 PM PDT 24 Jul 26 05:49:28 PM PDT 24 17170065953 ps
T332 /workspace/coverage/default/26.rom_ctrl_alert_test.3909482478 Jul 26 05:37:25 PM PDT 24 Jul 26 05:37:31 PM PDT 24 133010075 ps
T333 /workspace/coverage/default/31.rom_ctrl_alert_test.1676350747 Jul 26 05:37:30 PM PDT 24 Jul 26 05:37:35 PM PDT 24 1249411231 ps
T26 /workspace/coverage/default/0.rom_ctrl_sec_cm.3265394778 Jul 26 05:36:39 PM PDT 24 Jul 26 05:37:32 PM PDT 24 163688049 ps
T334 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3815190634 Jul 26 05:36:34 PM PDT 24 Jul 26 05:38:28 PM PDT 24 3862627658 ps
T335 /workspace/coverage/default/21.rom_ctrl_smoke.3036704441 Jul 26 05:37:17 PM PDT 24 Jul 26 05:37:29 PM PDT 24 1202824712 ps
T336 /workspace/coverage/default/39.rom_ctrl_smoke.110589307 Jul 26 05:37:41 PM PDT 24 Jul 26 05:37:52 PM PDT 24 849700223 ps
T337 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3940573106 Jul 26 05:36:39 PM PDT 24 Jul 26 05:36:51 PM PDT 24 997665426 ps
T338 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1370882531 Jul 26 05:36:39 PM PDT 24 Jul 26 05:38:23 PM PDT 24 4426013602 ps
T339 /workspace/coverage/default/31.rom_ctrl_stress_all.615284943 Jul 26 05:37:28 PM PDT 24 Jul 26 05:37:40 PM PDT 24 871184631 ps
T340 /workspace/coverage/default/47.rom_ctrl_smoke.242754250 Jul 26 05:37:47 PM PDT 24 Jul 26 05:37:57 PM PDT 24 357240542 ps
T341 /workspace/coverage/default/23.rom_ctrl_stress_all.961377020 Jul 26 05:37:12 PM PDT 24 Jul 26 05:37:27 PM PDT 24 399047157 ps
T342 /workspace/coverage/default/14.rom_ctrl_stress_all.1779058959 Jul 26 05:36:49 PM PDT 24 Jul 26 05:37:23 PM PDT 24 1166897710 ps
T343 /workspace/coverage/default/44.rom_ctrl_smoke.1921403212 Jul 26 05:37:42 PM PDT 24 Jul 26 05:37:54 PM PDT 24 296195851 ps
T344 /workspace/coverage/default/12.rom_ctrl_alert_test.487238255 Jul 26 05:36:47 PM PDT 24 Jul 26 05:36:51 PM PDT 24 346461252 ps
T345 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3200762196 Jul 26 05:37:42 PM PDT 24 Jul 26 05:39:07 PM PDT 24 1824792267 ps
T346 /workspace/coverage/default/17.rom_ctrl_alert_test.1946430421 Jul 26 05:36:52 PM PDT 24 Jul 26 05:36:56 PM PDT 24 85528959 ps
T347 /workspace/coverage/default/29.rom_ctrl_stress_all.116317962 Jul 26 05:37:29 PM PDT 24 Jul 26 05:37:57 PM PDT 24 562278775 ps
T348 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2078224136 Jul 26 05:37:29 PM PDT 24 Jul 26 05:37:40 PM PDT 24 1044459819 ps
T349 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3179300381 Jul 26 05:36:35 PM PDT 24 Jul 26 05:38:49 PM PDT 24 1930826229 ps
T350 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3048208868 Jul 26 05:37:31 PM PDT 24 Jul 26 05:37:42 PM PDT 24 1083488623 ps
T351 /workspace/coverage/default/24.rom_ctrl_alert_test.1963071464 Jul 26 05:37:14 PM PDT 24 Jul 26 05:37:19 PM PDT 24 128670247 ps
T352 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1732075844 Jul 26 05:36:44 PM PDT 24 Jul 26 05:38:59 PM PDT 24 5515522506 ps
T353 /workspace/coverage/default/35.rom_ctrl_alert_test.3825091503 Jul 26 05:37:26 PM PDT 24 Jul 26 05:37:31 PM PDT 24 127317906 ps
T354 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1103267967 Jul 26 05:36:47 PM PDT 24 Jul 26 06:08:20 PM PDT 24 47768041442 ps
T355 /workspace/coverage/default/28.rom_ctrl_alert_test.569289388 Jul 26 05:37:25 PM PDT 24 Jul 26 05:37:29 PM PDT 24 333977769 ps
T356 /workspace/coverage/default/36.rom_ctrl_alert_test.2257405191 Jul 26 05:37:26 PM PDT 24 Jul 26 05:37:31 PM PDT 24 137452177 ps
T357 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3401785677 Jul 26 05:37:28 PM PDT 24 Jul 26 05:37:39 PM PDT 24 1040117900 ps
T358 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1305003614 Jul 26 05:37:23 PM PDT 24 Jul 26 05:37:34 PM PDT 24 342763723 ps
T359 /workspace/coverage/default/49.rom_ctrl_smoke.3052949722 Jul 26 05:37:44 PM PDT 24 Jul 26 05:37:56 PM PDT 24 276111406 ps
T360 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4113733940 Jul 26 05:37:25 PM PDT 24 Jul 26 05:37:31 PM PDT 24 193256807 ps
T361 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2102510777 Jul 26 05:37:40 PM PDT 24 Jul 26 05:37:49 PM PDT 24 334833156 ps
T362 /workspace/coverage/default/32.rom_ctrl_stress_all.227547648 Jul 26 05:37:29 PM PDT 24 Jul 26 05:37:49 PM PDT 24 421090610 ps
T363 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3110380664 Jul 26 05:37:02 PM PDT 24 Jul 26 05:37:09 PM PDT 24 141867899 ps
T364 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1535111690 Jul 26 05:36:41 PM PDT 24 Jul 26 05:38:04 PM PDT 24 1352991985 ps
T365 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1064994831 Jul 26 05:37:23 PM PDT 24 Jul 26 05:37:40 PM PDT 24 1968255513 ps
T366 /workspace/coverage/default/15.rom_ctrl_smoke.1572135196 Jul 26 05:36:49 PM PDT 24 Jul 26 05:37:01 PM PDT 24 269455312 ps
T367 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.260983118 Jul 26 05:36:47 PM PDT 24 Jul 26 05:38:56 PM PDT 24 10822206618 ps
T368 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1486802127 Jul 26 05:37:24 PM PDT 24 Jul 26 06:18:54 PM PDT 24 58466674152 ps
T369 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.27645542 Jul 26 05:36:36 PM PDT 24 Jul 26 05:36:47 PM PDT 24 312072931 ps
T370 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1396972979 Jul 26 05:37:00 PM PDT 24 Jul 26 05:37:07 PM PDT 24 167590042 ps
T371 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2515815560 Jul 26 05:36:57 PM PDT 24 Jul 26 05:37:09 PM PDT 24 960615770 ps
T372 /workspace/coverage/default/6.rom_ctrl_alert_test.3709831801 Jul 26 05:36:38 PM PDT 24 Jul 26 05:36:43 PM PDT 24 569085676 ps
T373 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2752862164 Jul 26 05:36:44 PM PDT 24 Jul 26 05:36:54 PM PDT 24 168998709 ps
T374 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3906892920 Jul 26 05:36:50 PM PDT 24 Jul 26 05:53:32 PM PDT 24 88796983475 ps
T375 /workspace/coverage/default/7.rom_ctrl_stress_all.872791135 Jul 26 05:36:39 PM PDT 24 Jul 26 05:37:00 PM PDT 24 1525873138 ps
T376 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4195535887 Jul 26 05:36:55 PM PDT 24 Jul 26 05:37:04 PM PDT 24 355863623 ps
T377 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.983205688 Jul 26 05:37:26 PM PDT 24 Jul 26 05:46:48 PM PDT 24 19330841118 ps
T378 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.36063259 Jul 26 05:36:52 PM PDT 24 Jul 26 05:37:02 PM PDT 24 666326019 ps
T379 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3499390017 Jul 26 05:37:26 PM PDT 24 Jul 26 05:37:37 PM PDT 24 1127529746 ps
T380 /workspace/coverage/default/40.rom_ctrl_alert_test.2243479229 Jul 26 05:37:40 PM PDT 24 Jul 26 05:37:46 PM PDT 24 133048337 ps
T381 /workspace/coverage/default/37.rom_ctrl_smoke.458671918 Jul 26 05:37:30 PM PDT 24 Jul 26 05:37:43 PM PDT 24 516118622 ps
T382 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1699254010 Jul 26 05:37:25 PM PDT 24 Jul 26 05:37:35 PM PDT 24 1394644309 ps
T59 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3689789575 Jul 26 05:36:04 PM PDT 24 Jul 26 05:36:12 PM PDT 24 349160005 ps
T60 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3277855454 Jul 26 05:36:34 PM PDT 24 Jul 26 05:36:39 PM PDT 24 130335420 ps
T61 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.334246725 Jul 26 05:36:40 PM PDT 24 Jul 26 05:37:01 PM PDT 24 2086206817 ps
T62 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1763962685 Jul 26 05:36:33 PM PDT 24 Jul 26 05:36:38 PM PDT 24 287380452 ps
T56 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2109844938 Jul 26 05:36:30 PM PDT 24 Jul 26 05:37:40 PM PDT 24 1921709599 ps
T63 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.312151924 Jul 26 05:36:33 PM PDT 24 Jul 26 05:36:38 PM PDT 24 518142798 ps
T83 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3020604319 Jul 26 05:36:37 PM PDT 24 Jul 26 05:36:45 PM PDT 24 491651325 ps
T64 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.599120006 Jul 26 05:36:41 PM PDT 24 Jul 26 05:37:00 PM PDT 24 446621605 ps
T383 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2197013650 Jul 26 05:36:30 PM PDT 24 Jul 26 05:36:37 PM PDT 24 421993525 ps
T384 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.589644164 Jul 26 05:36:34 PM PDT 24 Jul 26 05:36:42 PM PDT 24 168971991 ps
T88 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3031885117 Jul 26 05:36:25 PM PDT 24 Jul 26 05:36:32 PM PDT 24 506100931 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1780210354 Jul 26 05:36:19 PM PDT 24 Jul 26 05:36:26 PM PDT 24 548882760 ps
T385 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.40630059 Jul 26 05:36:20 PM PDT 24 Jul 26 05:36:28 PM PDT 24 110013762 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1570832293 Jul 26 05:36:38 PM PDT 24 Jul 26 05:36:44 PM PDT 24 98392403 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3382086057 Jul 26 05:36:19 PM PDT 24 Jul 26 05:36:24 PM PDT 24 302640380 ps
T65 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1800887174 Jul 26 05:36:29 PM PDT 24 Jul 26 05:36:36 PM PDT 24 268838975 ps
T84 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3824332697 Jul 26 05:36:37 PM PDT 24 Jul 26 05:36:42 PM PDT 24 755700597 ps
T57 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.377801054 Jul 26 05:36:31 PM PDT 24 Jul 26 05:37:42 PM PDT 24 339785724 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3797702676 Jul 26 05:36:19 PM PDT 24 Jul 26 05:36:25 PM PDT 24 495907034 ps
T66 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1518868077 Jul 26 05:36:34 PM PDT 24 Jul 26 05:36:40 PM PDT 24 532406065 ps
T85 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2286803082 Jul 26 05:36:21 PM PDT 24 Jul 26 05:36:39 PM PDT 24 2734173944 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.531612181 Jul 26 05:36:25 PM PDT 24 Jul 26 05:36:30 PM PDT 24 152182886 ps
T58 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2165089982 Jul 26 05:36:33 PM PDT 24 Jul 26 05:37:40 PM PDT 24 1512137557 ps
T97 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2662051161 Jul 26 05:36:37 PM PDT 24 Jul 26 05:37:47 PM PDT 24 226005134 ps
T98 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1037928973 Jul 26 05:36:20 PM PDT 24 Jul 26 05:37:30 PM PDT 24 660306763 ps
T390 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1771390940 Jul 26 05:36:34 PM PDT 24 Jul 26 05:37:12 PM PDT 24 230671453 ps
T67 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3763811856 Jul 26 05:36:28 PM PDT 24 Jul 26 05:36:50 PM PDT 24 530270496 ps
T68 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2055168338 Jul 26 05:36:35 PM PDT 24 Jul 26 05:37:19 PM PDT 24 3123412774 ps
T391 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.427735713 Jul 26 05:36:30 PM PDT 24 Jul 26 05:36:39 PM PDT 24 131398185 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2726444936 Jul 26 05:36:18 PM PDT 24 Jul 26 05:36:25 PM PDT 24 142217324 ps
T99 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3196093937 Jul 26 05:36:29 PM PDT 24 Jul 26 05:37:35 PM PDT 24 841682765 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3551299557 Jul 26 05:36:27 PM PDT 24 Jul 26 05:36:31 PM PDT 24 347050536 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.173280146 Jul 26 05:36:26 PM PDT 24 Jul 26 05:36:32 PM PDT 24 133126968 ps
T69 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.742739733 Jul 26 05:36:32 PM PDT 24 Jul 26 05:36:37 PM PDT 24 86649112 ps
T100 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3075725756 Jul 26 05:36:38 PM PDT 24 Jul 26 05:37:14 PM PDT 24 616024070 ps
T70 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2833035142 Jul 26 05:36:30 PM PDT 24 Jul 26 05:36:35 PM PDT 24 85411040 ps
T393 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1588019377 Jul 26 05:36:31 PM PDT 24 Jul 26 05:36:37 PM PDT 24 127757074 ps
T394 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.663679730 Jul 26 05:35:52 PM PDT 24 Jul 26 05:35:56 PM PDT 24 350194566 ps
T395 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.438151264 Jul 26 05:36:36 PM PDT 24 Jul 26 05:36:41 PM PDT 24 347799259 ps
T396 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.648332774 Jul 26 05:36:33 PM PDT 24 Jul 26 05:36:38 PM PDT 24 492298308 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2225470504 Jul 26 05:36:30 PM PDT 24 Jul 26 05:36:36 PM PDT 24 111407417 ps
T101 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2956830521 Jul 26 05:36:20 PM PDT 24 Jul 26 05:36:57 PM PDT 24 810311854 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.690504300 Jul 26 05:36:20 PM PDT 24 Jul 26 05:36:26 PM PDT 24 132490831 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4049787028 Jul 26 05:36:25 PM PDT 24 Jul 26 05:36:47 PM PDT 24 7458867657 ps
T399 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1425418509 Jul 26 05:36:29 PM PDT 24 Jul 26 05:36:37 PM PDT 24 346418784 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1397888147 Jul 26 05:36:22 PM PDT 24 Jul 26 05:36:27 PM PDT 24 132804220 ps
T401 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2475175379 Jul 26 05:36:28 PM PDT 24 Jul 26 05:36:36 PM PDT 24 2045175775 ps
T402 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3730196918 Jul 26 05:36:42 PM PDT 24 Jul 26 05:36:47 PM PDT 24 256420158 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.968636326 Jul 26 05:36:44 PM PDT 24 Jul 26 05:36:48 PM PDT 24 594177379 ps
T72 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3521333493 Jul 26 05:36:17 PM PDT 24 Jul 26 05:36:23 PM PDT 24 519282054 ps
T73 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1436085142 Jul 26 05:36:34 PM PDT 24 Jul 26 05:37:02 PM PDT 24 4928073141 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3900307336 Jul 26 05:35:52 PM PDT 24 Jul 26 05:36:00 PM PDT 24 1968000565 ps
T405 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.29354045 Jul 26 05:36:37 PM PDT 24 Jul 26 05:37:05 PM PDT 24 572743000 ps
T406 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2674869124 Jul 26 05:36:19 PM PDT 24 Jul 26 05:36:24 PM PDT 24 87327318 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1339085934 Jul 26 05:36:31 PM PDT 24 Jul 26 05:36:36 PM PDT 24 516312748 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2781640737 Jul 26 05:36:35 PM PDT 24 Jul 26 05:36:40 PM PDT 24 1561509672 ps
T74 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2972447055 Jul 26 05:36:19 PM PDT 24 Jul 26 05:36:52 PM PDT 24 853791234 ps
T79 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1747127185 Jul 26 05:36:20 PM PDT 24 Jul 26 05:36:52 PM PDT 24 781066254 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1858817766 Jul 26 05:36:36 PM PDT 24 Jul 26 05:36:42 PM PDT 24 747944500 ps
T410 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.878551461 Jul 26 05:36:29 PM PDT 24 Jul 26 05:37:15 PM PDT 24 13012764797 ps
T411 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1933906093 Jul 26 05:36:40 PM PDT 24 Jul 26 05:36:46 PM PDT 24 555529187 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3946717959 Jul 26 05:36:04 PM PDT 24 Jul 26 05:36:23 PM PDT 24 1507472769 ps
T413 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1822549185 Jul 26 05:36:17 PM PDT 24 Jul 26 05:36:22 PM PDT 24 568401882 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.20598138 Jul 26 05:36:38 PM PDT 24 Jul 26 05:36:45 PM PDT 24 542276824 ps
T415 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.259591360 Jul 26 05:36:18 PM PDT 24 Jul 26 05:36:23 PM PDT 24 100395294 ps
T416 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1309889248 Jul 26 05:36:32 PM PDT 24 Jul 26 05:36:38 PM PDT 24 146163696 ps
T417 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1762464570 Jul 26 05:36:26 PM PDT 24 Jul 26 05:36:37 PM PDT 24 675538320 ps
T418 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.134462161 Jul 26 05:36:42 PM PDT 24 Jul 26 05:36:50 PM PDT 24 500075618 ps
T103 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.567018829 Jul 26 05:36:32 PM PDT 24 Jul 26 05:37:42 PM PDT 24 353961987 ps
T419 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.781717016 Jul 26 05:36:31 PM PDT 24 Jul 26 05:36:50 PM PDT 24 1319162924 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2245733449 Jul 26 05:36:36 PM PDT 24 Jul 26 05:36:42 PM PDT 24 442355692 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2753555380 Jul 26 05:36:30 PM PDT 24 Jul 26 05:36:34 PM PDT 24 201527556 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3757111376 Jul 26 05:36:05 PM PDT 24 Jul 26 05:36:10 PM PDT 24 132351169 ps
T423 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2757375588 Jul 26 05:36:40 PM PDT 24 Jul 26 05:36:48 PM PDT 24 146907168 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3739410924 Jul 26 05:35:57 PM PDT 24 Jul 26 05:36:01 PM PDT 24 168427940 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1412968660 Jul 26 05:36:07 PM PDT 24 Jul 26 05:36:43 PM PDT 24 182479678 ps
T106 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1671684222 Jul 26 05:36:30 PM PDT 24 Jul 26 05:37:07 PM PDT 24 790280163 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1307107829 Jul 26 05:36:29 PM PDT 24 Jul 26 05:36:38 PM PDT 24 97645634 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2851681628 Jul 26 05:36:28 PM PDT 24 Jul 26 05:36:32 PM PDT 24 169969347 ps
T80 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.699564334 Jul 26 05:36:37 PM PDT 24 Jul 26 05:36:59 PM PDT 24 2077280319 ps
T105 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1257001326 Jul 26 05:36:19 PM PDT 24 Jul 26 05:37:33 PM PDT 24 888849416 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.265180070 Jul 26 05:36:19 PM PDT 24 Jul 26 05:36:24 PM PDT 24 132964729 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3279412916 Jul 26 05:36:28 PM PDT 24 Jul 26 05:36:33 PM PDT 24 336395781 ps
T429 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2766191550 Jul 26 05:36:27 PM PDT 24 Jul 26 05:36:32 PM PDT 24 348768634 ps
T430 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.118360684 Jul 26 05:36:05 PM PDT 24 Jul 26 05:36:09 PM PDT 24 322220101 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2110952320 Jul 26 05:36:31 PM PDT 24 Jul 26 05:36:41 PM PDT 24 2093518086 ps
T107 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1637160776 Jul 26 05:36:18 PM PDT 24 Jul 26 05:37:26 PM PDT 24 254245572 ps
T432 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.996826030 Jul 26 05:36:30 PM PDT 24 Jul 26 05:37:42 PM PDT 24 374286291 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4177821556 Jul 26 05:36:32 PM PDT 24 Jul 26 05:36:37 PM PDT 24 361368584 ps
T81 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2723831435 Jul 26 05:36:39 PM PDT 24 Jul 26 05:37:01 PM PDT 24 1868950797 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4140477296 Jul 26 05:36:33 PM PDT 24 Jul 26 05:36:38 PM PDT 24 260823619 ps
T435 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1110180926 Jul 26 05:36:38 PM PDT 24 Jul 26 05:36:43 PM PDT 24 175283130 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1944830989 Jul 26 05:36:24 PM PDT 24 Jul 26 05:36:32 PM PDT 24 543780112 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2714679086 Jul 26 05:36:39 PM PDT 24 Jul 26 05:36:45 PM PDT 24 517960419 ps
T438 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1508931279 Jul 26 05:36:40 PM PDT 24 Jul 26 05:36:44 PM PDT 24 88329766 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3837106959 Jul 26 05:35:53 PM PDT 24 Jul 26 05:35:58 PM PDT 24 125950067 ps
T75 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3245414720 Jul 26 05:36:28 PM PDT 24 Jul 26 05:36:33 PM PDT 24 131335420 ps
T82 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.384487269 Jul 26 05:36:36 PM PDT 24 Jul 26 05:36:55 PM PDT 24 755005936 ps
T440 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2439924669 Jul 26 05:36:30 PM PDT 24 Jul 26 05:37:09 PM PDT 24 815677718 ps
T441 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2129771711 Jul 26 05:36:42 PM PDT 24 Jul 26 05:36:48 PM PDT 24 400698173 ps
T442 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2241241289 Jul 26 05:36:30 PM PDT 24 Jul 26 05:36:35 PM PDT 24 1244372077 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.405832854 Jul 26 05:36:19 PM PDT 24 Jul 26 05:36:24 PM PDT 24 89745032 ps
T444 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4230006797 Jul 26 05:36:33 PM PDT 24 Jul 26 05:36:54 PM PDT 24 2264011665 ps
T445 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3250907742 Jul 26 05:36:35 PM PDT 24 Jul 26 05:36:41 PM PDT 24 559801046 ps
T446 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3243651763 Jul 26 05:36:39 PM PDT 24 Jul 26 05:36:44 PM PDT 24 337110746 ps
T76 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1934269110 Jul 26 05:36:18 PM PDT 24 Jul 26 05:36:23 PM PDT 24 173034210 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2519212185 Jul 26 05:36:34 PM PDT 24 Jul 26 05:36:42 PM PDT 24 262797426 ps
T448 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.387433237 Jul 26 05:36:30 PM PDT 24 Jul 26 05:36:38 PM PDT 24 130259414 ps
T449 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.875355856 Jul 26 05:36:32 PM PDT 24 Jul 26 05:36:38 PM PDT 24 559180379 ps
T450 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2416693800 Jul 26 05:36:30 PM PDT 24 Jul 26 05:36:38 PM PDT 24 144901766 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.534846601 Jul 26 05:36:17 PM PDT 24 Jul 26 05:36:22 PM PDT 24 260258987 ps
T77 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3908397005 Jul 26 05:36:39 PM PDT 24 Jul 26 05:36:44 PM PDT 24 2457743650 ps
T452 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3952875952 Jul 26 05:36:31 PM PDT 24 Jul 26 05:36:36 PM PDT 24 88394271 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3780949487 Jul 26 05:36:26 PM PDT 24 Jul 26 05:36:31 PM PDT 24 126995163 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.86715969 Jul 26 05:36:20 PM PDT 24 Jul 26 05:36:25 PM PDT 24 131456635 ps
T454 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3688855645 Jul 26 05:36:31 PM PDT 24 Jul 26 05:37:04 PM PDT 24 792056698 ps
T455 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.892476585 Jul 26 05:36:28 PM PDT 24 Jul 26 05:36:37 PM PDT 24 129814354 ps
T456 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3880707261 Jul 26 05:36:33 PM PDT 24 Jul 26 05:36:41 PM PDT 24 127383933 ps
T457 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.186358365 Jul 26 05:36:35 PM PDT 24 Jul 26 05:36:46 PM PDT 24 164226121 ps
T458 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1791701705 Jul 26 05:36:17 PM PDT 24 Jul 26 05:36:21 PM PDT 24 333715312 ps
T459 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2893612603 Jul 26 05:36:18 PM PDT 24 Jul 26 05:36:22 PM PDT 24 338032673 ps
T460 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1767009783 Jul 26 05:36:17 PM PDT 24 Jul 26 05:36:24 PM PDT 24 146495545 ps
T461 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2279490450 Jul 26 05:36:30 PM PDT 24 Jul 26 05:36:34 PM PDT 24 173372981 ps
T462 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3248562288 Jul 26 05:36:33 PM PDT 24 Jul 26 05:36:42 PM PDT 24 565107250 ps
T102 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.923227215 Jul 26 05:36:38 PM PDT 24 Jul 26 05:37:55 PM PDT 24 1146428889 ps
T463 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3462496840 Jul 26 05:36:20 PM PDT 24 Jul 26 05:36:29 PM PDT 24 543632122 ps
T464 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3082557846 Jul 26 05:36:28 PM PDT 24 Jul 26 05:36:35 PM PDT 24 85411894 ps
T465 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1243139005 Jul 26 05:36:33 PM PDT 24 Jul 26 05:36:37 PM PDT 24 219984999 ps
T466 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2423730041 Jul 26 05:36:37 PM PDT 24 Jul 26 05:37:47 PM PDT 24 1149850866 ps
T467 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2221144342 Jul 26 05:36:32 PM PDT 24 Jul 26 05:36:54 PM PDT 24 550263256 ps
T468 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4134502008 Jul 26 05:36:04 PM PDT 24 Jul 26 05:36:14 PM PDT 24 785833447 ps
T469 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3122295622 Jul 26 05:36:16 PM PDT 24 Jul 26 05:36:23 PM PDT 24 88890568 ps
T470 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3924518171 Jul 26 05:36:17 PM PDT 24 Jul 26 05:36:39 PM PDT 24 2180157033 ps
T471 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1064787434 Jul 26 05:36:18 PM PDT 24 Jul 26 05:36:23 PM PDT 24 181185004 ps
T472 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4139944576 Jul 26 05:36:32 PM PDT 24 Jul 26 05:36:37 PM PDT 24 521260583 ps
T473 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.916952844 Jul 26 05:36:27 PM PDT 24 Jul 26 05:36:32 PM PDT 24 104363984 ps
T108 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1101707239 Jul 26 05:36:30 PM PDT 24 Jul 26 05:37:07 PM PDT 24 185922961 ps
T474 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3881132488 Jul 26 05:36:34 PM PDT 24 Jul 26 05:36:39 PM PDT 24 254124576 ps
T475 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.825883410 Jul 26 05:36:34 PM PDT 24 Jul 26 05:36:39 PM PDT 24 883559697 ps
T476 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.741909095 Jul 26 05:36:33 PM PDT 24 Jul 26 05:36:39 PM PDT 24 304510252 ps
T477 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1708305078 Jul 26 05:36:17 PM PDT 24 Jul 26 05:37:24 PM PDT 24 1215610372 ps
T478 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1691399012 Jul 26 05:36:29 PM PDT 24 Jul 26 05:36:34 PM PDT 24 102115972 ps
T479 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.915581660 Jul 26 05:36:38 PM PDT 24 Jul 26 05:36:43 PM PDT 24 260877812 ps
T480 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1869368994 Jul 26 05:36:40 PM PDT 24 Jul 26 05:36:44 PM PDT 24 86321536 ps
T481 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3787801718 Jul 26 05:36:28 PM PDT 24 Jul 26 05:36:33 PM PDT 24 96798031 ps

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.525041211
Short name T1
Test name
Test status
Simulation time 158479019641 ps
CPU time 2437.75 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 06:18:27 PM PDT 24
Peak memory 239292 kb
Host smart-fbd6f4ba-128f-464e-99ef-fd2ae14aab1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525041211 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.525041211
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1475547309
Short name T18
Test name
Test status
Simulation time 25372506426 ps
CPU time 141.58 seconds
Started Jul 26 05:36:31 PM PDT 24
Finished Jul 26 05:38:53 PM PDT 24
Peak memory 238412 kb
Host smart-39916bc2-3263-4db1-8deb-9f7b05bfbd2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475547309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1475547309
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3062012303
Short name T12
Test name
Test status
Simulation time 54106175017 ps
CPU time 1048.9 seconds
Started Jul 26 05:37:12 PM PDT 24
Finished Jul 26 05:54:41 PM PDT 24
Peak memory 236336 kb
Host smart-06503b39-74c2-4309-84be-064cb1053426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062012303 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3062012303
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3152100580
Short name T39
Test name
Test status
Simulation time 12778265042 ps
CPU time 271.1 seconds
Started Jul 26 05:37:30 PM PDT 24
Finished Jul 26 05:42:01 PM PDT 24
Peak memory 236168 kb
Host smart-0441ff0c-2f1a-4375-8cc8-c0a04d6ce502
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152100580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3152100580
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2109844938
Short name T56
Test name
Test status
Simulation time 1921709599 ps
CPU time 69.71 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:37:40 PM PDT 24
Peak memory 218692 kb
Host smart-9ad0926b-9919-4032-8003-17339e2133cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109844938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2109844938
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1789372163
Short name T21
Test name
Test status
Simulation time 248901632 ps
CPU time 99.76 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:38:15 PM PDT 24
Peak memory 237228 kb
Host smart-c0a88b6f-d929-47c6-bbec-86c3fe12450b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789372163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1789372163
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.334246725
Short name T61
Test name
Test status
Simulation time 2086206817 ps
CPU time 21.51 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:37:01 PM PDT 24
Peak memory 210660 kb
Host smart-92c85e65-c479-4cd6-b351-10fc1f0c1f82
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334246725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.334246725
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.807269032
Short name T7
Test name
Test status
Simulation time 521336143 ps
CPU time 4.84 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:37:55 PM PDT 24
Peak memory 211716 kb
Host smart-09beafc6-fb2d-4f3c-85c2-d13074ccc0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807269032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.807269032
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.408301389
Short name T8
Test name
Test status
Simulation time 270150944 ps
CPU time 9.6 seconds
Started Jul 26 05:37:48 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 212828 kb
Host smart-7e99c91a-a582-49ed-9ea6-675f52681e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408301389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.408301389
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1412968660
Short name T104
Test name
Test status
Simulation time 182479678 ps
CPU time 36.22 seconds
Started Jul 26 05:36:07 PM PDT 24
Finished Jul 26 05:36:43 PM PDT 24
Peak memory 212308 kb
Host smart-6de86a7e-9063-4e28-8361-fe25e99e6d65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412968660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1412968660
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1495812781
Short name T46
Test name
Test status
Simulation time 1079353946 ps
CPU time 29.5 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:37:06 PM PDT 24
Peak memory 216272 kb
Host smart-73e00361-b74e-49fa-833f-a90300b1c159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495812781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1495812781
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2463460154
Short name T109
Test name
Test status
Simulation time 1137592521 ps
CPU time 11.32 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:36:52 PM PDT 24
Peak memory 212652 kb
Host smart-be8221df-7a73-4f6a-8e2c-7423e3f32825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463460154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2463460154
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1637160776
Short name T107
Test name
Test status
Simulation time 254245572 ps
CPU time 67.86 seconds
Started Jul 26 05:36:18 PM PDT 24
Finished Jul 26 05:37:26 PM PDT 24
Peak memory 218728 kb
Host smart-f14315b5-ff2e-419b-9be0-87502add76cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637160776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1637160776
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3924518171
Short name T470
Test name
Test status
Simulation time 2180157033 ps
CPU time 21.84 seconds
Started Jul 26 05:36:17 PM PDT 24
Finished Jul 26 05:36:39 PM PDT 24
Peak memory 210644 kb
Host smart-213882ec-9924-4709-a686-8a9897510a66
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924518171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3924518171
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1037928973
Short name T98
Test name
Test status
Simulation time 660306763 ps
CPU time 69.97 seconds
Started Jul 26 05:36:20 PM PDT 24
Finished Jul 26 05:37:30 PM PDT 24
Peak memory 213252 kb
Host smart-c730b874-7b29-42ae-bf4f-275ce2574d64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037928973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1037928973
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1257001326
Short name T105
Test name
Test status
Simulation time 888849416 ps
CPU time 73.37 seconds
Started Jul 26 05:36:19 PM PDT 24
Finished Jul 26 05:37:33 PM PDT 24
Peak memory 212620 kb
Host smart-2083c097-c986-45e4-a803-800c4b24a494
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257001326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1257001326
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.663679730
Short name T394
Test name
Test status
Simulation time 350194566 ps
CPU time 4.19 seconds
Started Jul 26 05:35:52 PM PDT 24
Finished Jul 26 05:35:56 PM PDT 24
Peak memory 217340 kb
Host smart-6a1e0fe8-23fb-440d-88b5-6850426e2303
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663679730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.663679730
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3837106959
Short name T439
Test name
Test status
Simulation time 125950067 ps
CPU time 5.21 seconds
Started Jul 26 05:35:53 PM PDT 24
Finished Jul 26 05:35:58 PM PDT 24
Peak memory 210568 kb
Host smart-aea300f2-0b38-46f7-911a-b8fcff79e2b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837106959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3837106959
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3689789575
Short name T59
Test name
Test status
Simulation time 349160005 ps
CPU time 7.53 seconds
Started Jul 26 05:36:04 PM PDT 24
Finished Jul 26 05:36:12 PM PDT 24
Peak memory 210576 kb
Host smart-610662b3-58cb-46da-9aa9-1bc8fe1e1d3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689789575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3689789575
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.20598138
Short name T414
Test name
Test status
Simulation time 542276824 ps
CPU time 5.94 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:36:45 PM PDT 24
Peak memory 218860 kb
Host smart-310ddb37-deab-4afe-914e-5ed62d7e9214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20598138 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.20598138
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3900307336
Short name T404
Test name
Test status
Simulation time 1968000565 ps
CPU time 7.37 seconds
Started Jul 26 05:35:52 PM PDT 24
Finished Jul 26 05:36:00 PM PDT 24
Peak memory 210552 kb
Host smart-855cd645-c4e2-4e62-ba64-e84af34adf87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900307336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3900307336
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3757111376
Short name T422
Test name
Test status
Simulation time 132351169 ps
CPU time 5.02 seconds
Started Jul 26 05:36:05 PM PDT 24
Finished Jul 26 05:36:10 PM PDT 24
Peak memory 210432 kb
Host smart-1311bf5a-3f3a-428c-88cc-d67b23119368
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757111376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3757111376
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.118360684
Short name T430
Test name
Test status
Simulation time 322220101 ps
CPU time 4.03 seconds
Started Jul 26 05:36:05 PM PDT 24
Finished Jul 26 05:36:09 PM PDT 24
Peak memory 210460 kb
Host smart-cd0f04ee-e264-49e6-8b11-7dd9a79f5235
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118360684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
118360684
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3946717959
Short name T412
Test name
Test status
Simulation time 1507472769 ps
CPU time 18.64 seconds
Started Jul 26 05:36:04 PM PDT 24
Finished Jul 26 05:36:23 PM PDT 24
Peak memory 210628 kb
Host smart-a568f3a2-89f1-4d50-87c8-f84e1c0339c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946717959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3946717959
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3739410924
Short name T424
Test name
Test status
Simulation time 168427940 ps
CPU time 4.16 seconds
Started Jul 26 05:35:57 PM PDT 24
Finished Jul 26 05:36:01 PM PDT 24
Peak memory 210612 kb
Host smart-c949150b-7ba8-4dc4-aea0-4222a26a0009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739410924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3739410924
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4134502008
Short name T468
Test name
Test status
Simulation time 785833447 ps
CPU time 9.82 seconds
Started Jul 26 05:36:04 PM PDT 24
Finished Jul 26 05:36:14 PM PDT 24
Peak memory 215792 kb
Host smart-a3329601-eeba-43d4-80c6-cb359345cee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134502008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4134502008
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.86715969
Short name T78
Test name
Test status
Simulation time 131456635 ps
CPU time 5.1 seconds
Started Jul 26 05:36:20 PM PDT 24
Finished Jul 26 05:36:25 PM PDT 24
Peak memory 210544 kb
Host smart-57b3a96c-fa95-4229-9e1c-1a341dea5655
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86715969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasi
ng.86715969
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.531612181
Short name T389
Test name
Test status
Simulation time 152182886 ps
CPU time 5.41 seconds
Started Jul 26 05:36:25 PM PDT 24
Finished Jul 26 05:36:30 PM PDT 24
Peak memory 218680 kb
Host smart-124613c9-0295-4068-a155-51e6c48e4237
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531612181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.531612181
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1780210354
Short name T89
Test name
Test status
Simulation time 548882760 ps
CPU time 6.59 seconds
Started Jul 26 05:36:19 PM PDT 24
Finished Jul 26 05:36:26 PM PDT 24
Peak memory 218748 kb
Host smart-4fc5c57d-4dbe-4239-8748-c309bd104ebc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780210354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1780210354
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1064787434
Short name T471
Test name
Test status
Simulation time 181185004 ps
CPU time 4.82 seconds
Started Jul 26 05:36:18 PM PDT 24
Finished Jul 26 05:36:23 PM PDT 24
Peak memory 215244 kb
Host smart-54d05789-10c7-415c-9acd-8be498f88b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064787434 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1064787434
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.915581660
Short name T479
Test name
Test status
Simulation time 260877812 ps
CPU time 4.96 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:36:43 PM PDT 24
Peak memory 210376 kb
Host smart-1105eeca-27b0-4908-9a94-6e1231474eba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915581660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.915581660
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.534846601
Short name T451
Test name
Test status
Simulation time 260258987 ps
CPU time 5.03 seconds
Started Jul 26 05:36:17 PM PDT 24
Finished Jul 26 05:36:22 PM PDT 24
Peak memory 210384 kb
Host smart-6052c45f-5f85-4edd-88e3-0daf3b533726
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534846601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.534846601
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1339085934
Short name T407
Test name
Test status
Simulation time 516312748 ps
CPU time 4.87 seconds
Started Jul 26 05:36:31 PM PDT 24
Finished Jul 26 05:36:36 PM PDT 24
Peak memory 210324 kb
Host smart-88dd230b-1d8a-419d-9218-35492d4c67bc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339085934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1339085934
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3780949487
Short name T453
Test name
Test status
Simulation time 126995163 ps
CPU time 5.34 seconds
Started Jul 26 05:36:26 PM PDT 24
Finished Jul 26 05:36:31 PM PDT 24
Peak memory 210676 kb
Host smart-08918c7c-101c-4ec9-af2d-34e49a9e7af5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780949487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3780949487
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3122295622
Short name T469
Test name
Test status
Simulation time 88890568 ps
CPU time 6.78 seconds
Started Jul 26 05:36:16 PM PDT 24
Finished Jul 26 05:36:23 PM PDT 24
Peak memory 218744 kb
Host smart-08d9d35c-d087-4b3f-be97-3d02d902a52c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122295622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3122295622
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1708305078
Short name T477
Test name
Test status
Simulation time 1215610372 ps
CPU time 67.05 seconds
Started Jul 26 05:36:17 PM PDT 24
Finished Jul 26 05:37:24 PM PDT 24
Peak memory 212368 kb
Host smart-53f373d6-26a9-49b0-873c-f6dabdf566a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708305078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1708305078
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3250907742
Short name T445
Test name
Test status
Simulation time 559801046 ps
CPU time 6.08 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:36:41 PM PDT 24
Peak memory 215712 kb
Host smart-8325787c-698a-4e3b-a84d-1665133ae2e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250907742 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3250907742
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2893612603
Short name T459
Test name
Test status
Simulation time 338032673 ps
CPU time 4.1 seconds
Started Jul 26 05:36:18 PM PDT 24
Finished Jul 26 05:36:22 PM PDT 24
Peak memory 210480 kb
Host smart-90527db1-e88b-4966-91e5-29c09be72a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893612603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2893612603
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1822549185
Short name T413
Test name
Test status
Simulation time 568401882 ps
CPU time 5.14 seconds
Started Jul 26 05:36:17 PM PDT 24
Finished Jul 26 05:36:22 PM PDT 24
Peak memory 210560 kb
Host smart-57e2b478-87fa-460c-9d5b-e711685d1604
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822549185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1822549185
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1425418509
Short name T399
Test name
Test status
Simulation time 346418784 ps
CPU time 8.02 seconds
Started Jul 26 05:36:29 PM PDT 24
Finished Jul 26 05:36:37 PM PDT 24
Peak memory 215772 kb
Host smart-91d0926d-a4f1-4c12-90c5-d9572e89f62a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425418509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1425418509
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.259591360
Short name T415
Test name
Test status
Simulation time 100395294 ps
CPU time 4.94 seconds
Started Jul 26 05:36:18 PM PDT 24
Finished Jul 26 05:36:23 PM PDT 24
Peak memory 215204 kb
Host smart-890cb32b-8ec8-4f3b-b8eb-9a4e8de5f82d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259591360 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.259591360
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2674869124
Short name T406
Test name
Test status
Simulation time 87327318 ps
CPU time 4.3 seconds
Started Jul 26 05:36:19 PM PDT 24
Finished Jul 26 05:36:24 PM PDT 24
Peak memory 217668 kb
Host smart-05ec3136-f9e3-4ae2-9699-c408581969d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674869124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2674869124
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2286803082
Short name T85
Test name
Test status
Simulation time 2734173944 ps
CPU time 17.87 seconds
Started Jul 26 05:36:21 PM PDT 24
Finished Jul 26 05:36:39 PM PDT 24
Peak memory 210676 kb
Host smart-2f056c83-9da4-40ec-8d74-9d41485ebb46
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286803082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2286803082
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2475175379
Short name T401
Test name
Test status
Simulation time 2045175775 ps
CPU time 7.68 seconds
Started Jul 26 05:36:28 PM PDT 24
Finished Jul 26 05:36:36 PM PDT 24
Peak memory 218692 kb
Host smart-afed4445-8da7-4e87-a571-6e6a2e3a47da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475175379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2475175379
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.40630059
Short name T385
Test name
Test status
Simulation time 110013762 ps
CPU time 7.95 seconds
Started Jul 26 05:36:20 PM PDT 24
Finished Jul 26 05:36:28 PM PDT 24
Peak memory 215844 kb
Host smart-d20ced21-91da-4dcf-bd25-fcaf274f346b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40630059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.40630059
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3787801718
Short name T481
Test name
Test status
Simulation time 96798031 ps
CPU time 4.68 seconds
Started Jul 26 05:36:28 PM PDT 24
Finished Jul 26 05:36:33 PM PDT 24
Peak memory 214776 kb
Host smart-f91b4c13-d5a2-4853-819f-dd1b3103164c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787801718 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3787801718
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2766191550
Short name T429
Test name
Test status
Simulation time 348768634 ps
CPU time 4.02 seconds
Started Jul 26 05:36:27 PM PDT 24
Finished Jul 26 05:36:32 PM PDT 24
Peak memory 217776 kb
Host smart-ba6f7e32-e029-4465-ab3d-0fa8a7d48e4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766191550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2766191550
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2055168338
Short name T68
Test name
Test status
Simulation time 3123412774 ps
CPU time 44 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:37:19 PM PDT 24
Peak memory 210672 kb
Host smart-897636d9-bb8e-4f78-8e78-0a8c863525a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055168338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2055168338
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3824332697
Short name T84
Test name
Test status
Simulation time 755700597 ps
CPU time 4.33 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:36:42 PM PDT 24
Peak memory 210660 kb
Host smart-2fc8fece-b52f-4056-96ca-0d04457e33dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824332697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3824332697
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1762464570
Short name T417
Test name
Test status
Simulation time 675538320 ps
CPU time 10.34 seconds
Started Jul 26 05:36:26 PM PDT 24
Finished Jul 26 05:36:37 PM PDT 24
Peak memory 218752 kb
Host smart-1b18f9ec-8c90-443e-8ae1-2dc4a69134fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762464570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1762464570
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2225470504
Short name T397
Test name
Test status
Simulation time 111407417 ps
CPU time 5.24 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:36:36 PM PDT 24
Peak memory 215416 kb
Host smart-d00c7c3f-b6fb-4566-9be3-b8dade1b1cf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225470504 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2225470504
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.825883410
Short name T475
Test name
Test status
Simulation time 883559697 ps
CPU time 4.86 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:36:39 PM PDT 24
Peak memory 218536 kb
Host smart-02ee4580-9a74-4a8e-89a5-e86f1f8a5296
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825883410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.825883410
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3763811856
Short name T67
Test name
Test status
Simulation time 530270496 ps
CPU time 21.66 seconds
Started Jul 26 05:36:28 PM PDT 24
Finished Jul 26 05:36:50 PM PDT 24
Peak memory 210644 kb
Host smart-446cebe8-7ff1-4728-8873-88ce77bc095f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763811856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3763811856
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2110952320
Short name T431
Test name
Test status
Simulation time 2093518086 ps
CPU time 9.73 seconds
Started Jul 26 05:36:31 PM PDT 24
Finished Jul 26 05:36:41 PM PDT 24
Peak memory 210684 kb
Host smart-d5b23272-5592-4647-9dbd-324246058b16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110952320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2110952320
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.892476585
Short name T455
Test name
Test status
Simulation time 129814354 ps
CPU time 8.88 seconds
Started Jul 26 05:36:28 PM PDT 24
Finished Jul 26 05:36:37 PM PDT 24
Peak memory 214476 kb
Host smart-31e9e722-2e42-444b-bda8-a2292e2751f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892476585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.892476585
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.996826030
Short name T432
Test name
Test status
Simulation time 374286291 ps
CPU time 71.15 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:37:42 PM PDT 24
Peak memory 212272 kb
Host smart-dd4b7724-6801-4cdb-9b07-f61c441e0645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996826030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.996826030
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1858817766
Short name T409
Test name
Test status
Simulation time 747944500 ps
CPU time 5.56 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:36:42 PM PDT 24
Peak memory 214464 kb
Host smart-96271dd4-dbe7-48ab-b2c6-e2869b80561a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858817766 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1858817766
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2279490450
Short name T461
Test name
Test status
Simulation time 173372981 ps
CPU time 4.07 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:36:34 PM PDT 24
Peak memory 217276 kb
Host smart-4a3a9cd7-a0ea-45f9-8e5f-dc5a25be0cb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279490450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2279490450
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3688855645
Short name T454
Test name
Test status
Simulation time 792056698 ps
CPU time 32.51 seconds
Started Jul 26 05:36:31 PM PDT 24
Finished Jul 26 05:37:04 PM PDT 24
Peak memory 210524 kb
Host smart-c4935e95-05fe-441d-af32-ddff34bf198f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688855645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3688855645
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1243139005
Short name T465
Test name
Test status
Simulation time 219984999 ps
CPU time 4.24 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:36:37 PM PDT 24
Peak memory 210636 kb
Host smart-59913bed-dfa2-46bf-ab2d-ef59d4c5f16b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243139005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1243139005
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.387433237
Short name T448
Test name
Test status
Simulation time 130259414 ps
CPU time 7.41 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 218820 kb
Host smart-fd819a95-b306-476b-a4b0-552e3850c2de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387433237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.387433237
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3196093937
Short name T99
Test name
Test status
Simulation time 841682765 ps
CPU time 65.4 seconds
Started Jul 26 05:36:29 PM PDT 24
Finished Jul 26 05:37:35 PM PDT 24
Peak memory 218780 kb
Host smart-7561c77e-8cb1-4f96-b9bb-327e074112b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196093937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3196093937
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.438151264
Short name T395
Test name
Test status
Simulation time 347799259 ps
CPU time 4.72 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:36:41 PM PDT 24
Peak memory 218828 kb
Host smart-d65d4d37-b5bc-4bbd-9814-3cae1612599f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438151264 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.438151264
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1508931279
Short name T438
Test name
Test status
Simulation time 88329766 ps
CPU time 4.05 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:36:44 PM PDT 24
Peak memory 210496 kb
Host smart-47068789-308e-43e8-9727-cea436631cab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508931279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1508931279
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1436085142
Short name T73
Test name
Test status
Simulation time 4928073141 ps
CPU time 27.32 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:37:02 PM PDT 24
Peak memory 210580 kb
Host smart-4758fe85-a2ac-402a-ad19-2304617ab08d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436085142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1436085142
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3730196918
Short name T402
Test name
Test status
Simulation time 256420158 ps
CPU time 5.05 seconds
Started Jul 26 05:36:42 PM PDT 24
Finished Jul 26 05:36:47 PM PDT 24
Peak memory 210492 kb
Host smart-3b0dfc2a-4fd5-48dd-9ead-7e1947bb19a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730196918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3730196918
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2519212185
Short name T447
Test name
Test status
Simulation time 262797426 ps
CPU time 7.35 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:36:42 PM PDT 24
Peak memory 215500 kb
Host smart-d1a48905-7270-4e5a-ad0c-5acd2d09c40a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519212185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2519212185
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2439924669
Short name T440
Test name
Test status
Simulation time 815677718 ps
CPU time 38.24 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:37:09 PM PDT 24
Peak memory 218780 kb
Host smart-a44abddb-d756-4b43-9136-612b56006e80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439924669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2439924669
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2129771711
Short name T441
Test name
Test status
Simulation time 400698173 ps
CPU time 4.76 seconds
Started Jul 26 05:36:42 PM PDT 24
Finished Jul 26 05:36:48 PM PDT 24
Peak memory 218596 kb
Host smart-e47879f3-6cbc-4925-825a-e9768c20a573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129771711 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2129771711
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1763962685
Short name T62
Test name
Test status
Simulation time 287380452 ps
CPU time 4.18 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 218720 kb
Host smart-3948c8ef-c760-40c0-a24b-ede4a3b45c8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763962685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1763962685
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2723831435
Short name T81
Test name
Test status
Simulation time 1868950797 ps
CPU time 21.83 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:37:01 PM PDT 24
Peak memory 210560 kb
Host smart-c25e4f02-0e02-4cfc-87a0-ee11f4a978c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723831435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2723831435
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2781640737
Short name T408
Test name
Test status
Simulation time 1561509672 ps
CPU time 4.99 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:36:40 PM PDT 24
Peak memory 218776 kb
Host smart-dccedadd-9336-4a88-86e7-7f9a94e88fa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781640737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2781640737
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.134462161
Short name T418
Test name
Test status
Simulation time 500075618 ps
CPU time 7.4 seconds
Started Jul 26 05:36:42 PM PDT 24
Finished Jul 26 05:36:50 PM PDT 24
Peak memory 218628 kb
Host smart-dac0b3c6-887f-41d1-8be0-edcbeac604a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134462161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.134462161
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3075725756
Short name T100
Test name
Test status
Simulation time 616024070 ps
CPU time 36.09 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:37:14 PM PDT 24
Peak memory 218636 kb
Host smart-42c6ed3f-c0df-41a1-8ca6-920b4b2ef228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075725756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3075725756
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1309889248
Short name T416
Test name
Test status
Simulation time 146163696 ps
CPU time 6.56 seconds
Started Jul 26 05:36:32 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 216000 kb
Host smart-a826cc4a-509e-4425-9646-72b1a761f59f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309889248 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1309889248
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3243651763
Short name T446
Test name
Test status
Simulation time 337110746 ps
CPU time 4.34 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:36:44 PM PDT 24
Peak memory 210436 kb
Host smart-fedf7dce-0a5e-4ec3-832e-e88141c1a7ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243651763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3243651763
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.599120006
Short name T64
Test name
Test status
Simulation time 446621605 ps
CPU time 18.49 seconds
Started Jul 26 05:36:41 PM PDT 24
Finished Jul 26 05:37:00 PM PDT 24
Peak memory 210612 kb
Host smart-8e3b92cb-1527-4c94-9491-492544f77297
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599120006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.599120006
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3881132488
Short name T474
Test name
Test status
Simulation time 254124576 ps
CPU time 5.2 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:36:39 PM PDT 24
Peak memory 218760 kb
Host smart-597610af-a050-437c-a590-19b74b06b496
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881132488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3881132488
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3248562288
Short name T462
Test name
Test status
Simulation time 565107250 ps
CPU time 8.78 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:36:42 PM PDT 24
Peak memory 215956 kb
Host smart-211ee8fa-673a-42d2-8b99-b87e07a9b062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248562288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3248562288
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.377801054
Short name T57
Test name
Test status
Simulation time 339785724 ps
CPU time 70.28 seconds
Started Jul 26 05:36:31 PM PDT 24
Finished Jul 26 05:37:42 PM PDT 24
Peak memory 212132 kb
Host smart-46edf1c9-3283-4fe1-835f-52e39da0ba30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377801054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.377801054
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2245733449
Short name T420
Test name
Test status
Simulation time 442355692 ps
CPU time 5.4 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:36:42 PM PDT 24
Peak memory 215888 kb
Host smart-61744835-e927-4a4a-b0bc-5492c4ff339e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245733449 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2245733449
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.742739733
Short name T69
Test name
Test status
Simulation time 86649112 ps
CPU time 4.21 seconds
Started Jul 26 05:36:32 PM PDT 24
Finished Jul 26 05:36:37 PM PDT 24
Peak memory 210560 kb
Host smart-6ca016e1-218d-443b-aa38-c1f3d6ecffd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742739733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.742739733
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.384487269
Short name T82
Test name
Test status
Simulation time 755005936 ps
CPU time 18.51 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:36:55 PM PDT 24
Peak memory 210636 kb
Host smart-056ec61f-8e05-4a83-9b7e-13a03f453f3b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384487269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.384487269
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3020604319
Short name T83
Test name
Test status
Simulation time 491651325 ps
CPU time 7.67 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:36:45 PM PDT 24
Peak memory 218748 kb
Host smart-b42cf5c3-e600-4667-94ab-9a448d4f26cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020604319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3020604319
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2757375588
Short name T423
Test name
Test status
Simulation time 146907168 ps
CPU time 7.4 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:36:48 PM PDT 24
Peak memory 215776 kb
Host smart-cd096cd1-5c8e-44da-a193-15ca4e2082d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757375588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2757375588
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1771390940
Short name T390
Test name
Test status
Simulation time 230671453 ps
CPU time 37.89 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:37:12 PM PDT 24
Peak memory 210924 kb
Host smart-ecda7ace-3a8c-4075-9b96-ff7252352d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771390940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1771390940
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1570832293
Short name T386
Test name
Test status
Simulation time 98392403 ps
CPU time 5.05 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:36:44 PM PDT 24
Peak memory 215816 kb
Host smart-016ce3a2-45ee-4d7f-81a2-d4f2cb8e0f0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570832293 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1570832293
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3277855454
Short name T60
Test name
Test status
Simulation time 130335420 ps
CPU time 5.21 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:36:39 PM PDT 24
Peak memory 218720 kb
Host smart-1204b00e-ffe8-4688-80da-fc82cae42287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277855454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3277855454
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.699564334
Short name T80
Test name
Test status
Simulation time 2077280319 ps
CPU time 21.29 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:36:59 PM PDT 24
Peak memory 210656 kb
Host smart-c9583260-bc17-426c-8199-e743e13c54c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699564334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.699564334
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1518868077
Short name T66
Test name
Test status
Simulation time 532406065 ps
CPU time 6.65 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:36:40 PM PDT 24
Peak memory 218784 kb
Host smart-aade4bb7-b015-48f1-b587-bc56a22b8f5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518868077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1518868077
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.589644164
Short name T384
Test name
Test status
Simulation time 168971991 ps
CPU time 7.43 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:36:42 PM PDT 24
Peak memory 218840 kb
Host smart-c03461f5-4da5-46df-b817-73ec585601ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589644164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.589644164
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.405832854
Short name T443
Test name
Test status
Simulation time 89745032 ps
CPU time 4.23 seconds
Started Jul 26 05:36:19 PM PDT 24
Finished Jul 26 05:36:24 PM PDT 24
Peak memory 210548 kb
Host smart-4b54c606-6c38-4d0d-887d-b7a59989fe04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405832854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.405832854
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3797702676
Short name T388
Test name
Test status
Simulation time 495907034 ps
CPU time 5.29 seconds
Started Jul 26 05:36:19 PM PDT 24
Finished Jul 26 05:36:25 PM PDT 24
Peak memory 210568 kb
Host smart-63368594-8aa9-4de4-a857-75f0546d2962
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797702676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3797702676
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1767009783
Short name T460
Test name
Test status
Simulation time 146495545 ps
CPU time 6.78 seconds
Started Jul 26 05:36:17 PM PDT 24
Finished Jul 26 05:36:24 PM PDT 24
Peak memory 210556 kb
Host smart-43b07071-529c-4d37-9a25-91ef6fed7d8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767009783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1767009783
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4177821556
Short name T433
Test name
Test status
Simulation time 361368584 ps
CPU time 4.39 seconds
Started Jul 26 05:36:32 PM PDT 24
Finished Jul 26 05:36:37 PM PDT 24
Peak memory 218736 kb
Host smart-ccda8bad-d181-45f6-9db0-d7148c6b9204
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177821556 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4177821556
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3521333493
Short name T72
Test name
Test status
Simulation time 519282054 ps
CPU time 5.17 seconds
Started Jul 26 05:36:17 PM PDT 24
Finished Jul 26 05:36:23 PM PDT 24
Peak memory 210592 kb
Host smart-8fedc9b1-fe75-421a-aad6-67f5e9f866c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521333493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3521333493
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4140477296
Short name T434
Test name
Test status
Simulation time 260823619 ps
CPU time 4.86 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 210448 kb
Host smart-fc8e6390-10e6-4590-8170-c5df38f327ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140477296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4140477296
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2714679086
Short name T437
Test name
Test status
Simulation time 517960419 ps
CPU time 4.85 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:36:45 PM PDT 24
Peak memory 210364 kb
Host smart-f405550e-997f-4c38-938e-e6c38160a37f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714679086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2714679086
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2972447055
Short name T74
Test name
Test status
Simulation time 853791234 ps
CPU time 31.92 seconds
Started Jul 26 05:36:19 PM PDT 24
Finished Jul 26 05:36:52 PM PDT 24
Peak memory 210572 kb
Host smart-1dfa2427-37f2-4088-8a7e-79298ca42ba3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972447055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2972447055
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2726444936
Short name T86
Test name
Test status
Simulation time 142217324 ps
CPU time 6.9 seconds
Started Jul 26 05:36:18 PM PDT 24
Finished Jul 26 05:36:25 PM PDT 24
Peak memory 218740 kb
Host smart-d2313543-f664-43f7-ad98-a0d72785e7e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726444936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2726444936
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1307107829
Short name T425
Test name
Test status
Simulation time 97645634 ps
CPU time 8.52 seconds
Started Jul 26 05:36:29 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 218840 kb
Host smart-06310ee5-d0f7-4aa5-8599-c064d2b23d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307107829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1307107829
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2662051161
Short name T97
Test name
Test status
Simulation time 226005134 ps
CPU time 69.34 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:37:47 PM PDT 24
Peak memory 212320 kb
Host smart-bac1ab12-5471-47e6-a100-83ea9f44f8f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662051161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2662051161
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1934269110
Short name T76
Test name
Test status
Simulation time 173034210 ps
CPU time 4.42 seconds
Started Jul 26 05:36:18 PM PDT 24
Finished Jul 26 05:36:23 PM PDT 24
Peak memory 217144 kb
Host smart-10fea81c-c61f-4ded-b1c8-2a9a2446a3ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934269110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1934269110
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1791701705
Short name T458
Test name
Test status
Simulation time 333715312 ps
CPU time 4.46 seconds
Started Jul 26 05:36:17 PM PDT 24
Finished Jul 26 05:36:21 PM PDT 24
Peak memory 210592 kb
Host smart-3f4c7837-efb3-4664-9405-ce242e8ac348
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791701705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1791701705
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3031885117
Short name T88
Test name
Test status
Simulation time 506100931 ps
CPU time 6.4 seconds
Started Jul 26 05:36:25 PM PDT 24
Finished Jul 26 05:36:32 PM PDT 24
Peak memory 218676 kb
Host smart-df53ea88-3e7f-4f8f-adfe-c2410623f2d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031885117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3031885117
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3382086057
Short name T387
Test name
Test status
Simulation time 302640380 ps
CPU time 4.33 seconds
Started Jul 26 05:36:19 PM PDT 24
Finished Jul 26 05:36:24 PM PDT 24
Peak memory 218724 kb
Host smart-233da3f4-117c-4f30-b554-7581eb3bf206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382086057 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3382086057
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3908397005
Short name T77
Test name
Test status
Simulation time 2457743650 ps
CPU time 5.05 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:36:44 PM PDT 24
Peak memory 218776 kb
Host smart-16b65a1d-6660-44ff-8d73-d383cb120206
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908397005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3908397005
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1397888147
Short name T400
Test name
Test status
Simulation time 132804220 ps
CPU time 5.05 seconds
Started Jul 26 05:36:22 PM PDT 24
Finished Jul 26 05:36:27 PM PDT 24
Peak memory 210500 kb
Host smart-ed2d752f-6cb5-4217-a023-eb05b9f1c36a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397888147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1397888147
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.265180070
Short name T427
Test name
Test status
Simulation time 132964729 ps
CPU time 5.07 seconds
Started Jul 26 05:36:19 PM PDT 24
Finished Jul 26 05:36:24 PM PDT 24
Peak memory 210432 kb
Host smart-b83010b0-dcb3-41ab-9050-bc420b928bd7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265180070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
265180070
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4230006797
Short name T444
Test name
Test status
Simulation time 2264011665 ps
CPU time 20.81 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:36:54 PM PDT 24
Peak memory 210712 kb
Host smart-33e82bb7-a903-4e1c-8170-a917d0c5a0df
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230006797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.4230006797
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3279412916
Short name T428
Test name
Test status
Simulation time 336395781 ps
CPU time 4.35 seconds
Started Jul 26 05:36:28 PM PDT 24
Finished Jul 26 05:36:33 PM PDT 24
Peak memory 210624 kb
Host smart-8e3343ef-ccae-4ded-88e7-b3fb9da61fca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279412916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3279412916
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1944830989
Short name T436
Test name
Test status
Simulation time 543780112 ps
CPU time 7.58 seconds
Started Jul 26 05:36:24 PM PDT 24
Finished Jul 26 05:36:32 PM PDT 24
Peak memory 218840 kb
Host smart-43bbfd69-237c-48d2-82f1-cdfdb091f8e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944830989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1944830989
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2956830521
Short name T101
Test name
Test status
Simulation time 810311854 ps
CPU time 36.99 seconds
Started Jul 26 05:36:20 PM PDT 24
Finished Jul 26 05:36:57 PM PDT 24
Peak memory 212980 kb
Host smart-0db3f00b-8ec8-47d9-9ed9-21a58b149079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956830521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2956830521
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2851681628
Short name T426
Test name
Test status
Simulation time 169969347 ps
CPU time 4.17 seconds
Started Jul 26 05:36:28 PM PDT 24
Finished Jul 26 05:36:32 PM PDT 24
Peak memory 217280 kb
Host smart-151c3ea4-f65c-4127-9e77-b57d26363ce9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851681628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2851681628
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.690504300
Short name T398
Test name
Test status
Simulation time 132490831 ps
CPU time 5.5 seconds
Started Jul 26 05:36:20 PM PDT 24
Finished Jul 26 05:36:26 PM PDT 24
Peak memory 218956 kb
Host smart-e58ad8b4-77c5-4667-94ca-4bd78cb74932
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690504300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.690504300
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1800887174
Short name T65
Test name
Test status
Simulation time 268838975 ps
CPU time 6.56 seconds
Started Jul 26 05:36:29 PM PDT 24
Finished Jul 26 05:36:36 PM PDT 24
Peak memory 210588 kb
Host smart-343acd34-52d1-43e6-b664-23365263d443
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800887174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1800887174
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1933906093
Short name T411
Test name
Test status
Simulation time 555529187 ps
CPU time 5.77 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:36:46 PM PDT 24
Peak memory 218864 kb
Host smart-45c7e04d-f7d4-4143-bcf9-7a3509402139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933906093 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1933906093
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2753555380
Short name T421
Test name
Test status
Simulation time 201527556 ps
CPU time 4.19 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:36:34 PM PDT 24
Peak memory 210588 kb
Host smart-026dbec2-b668-4b0f-881a-7b16129608b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753555380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2753555380
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.173280146
Short name T392
Test name
Test status
Simulation time 133126968 ps
CPU time 4.97 seconds
Started Jul 26 05:36:26 PM PDT 24
Finished Jul 26 05:36:32 PM PDT 24
Peak memory 210324 kb
Host smart-228a49e6-54a7-42d2-b8cc-1523eb87dd87
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173280146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.173280146
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1869368994
Short name T480
Test name
Test status
Simulation time 86321536 ps
CPU time 4.1 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:36:44 PM PDT 24
Peak memory 210432 kb
Host smart-2a22aa43-6e5b-411f-9346-93c694326414
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869368994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1869368994
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1747127185
Short name T79
Test name
Test status
Simulation time 781066254 ps
CPU time 31.26 seconds
Started Jul 26 05:36:20 PM PDT 24
Finished Jul 26 05:36:52 PM PDT 24
Peak memory 210556 kb
Host smart-8f91e24c-cfb2-4589-bdd7-3cdf1833194f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747127185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1747127185
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3551299557
Short name T87
Test name
Test status
Simulation time 347050536 ps
CPU time 4.18 seconds
Started Jul 26 05:36:27 PM PDT 24
Finished Jul 26 05:36:31 PM PDT 24
Peak memory 210612 kb
Host smart-df6a6c58-af5f-4c84-bca4-a4b096ff7a34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551299557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3551299557
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3462496840
Short name T463
Test name
Test status
Simulation time 543632122 ps
CPU time 8.8 seconds
Started Jul 26 05:36:20 PM PDT 24
Finished Jul 26 05:36:29 PM PDT 24
Peak memory 215716 kb
Host smart-4fb4e420-06aa-4975-9993-7c3829450406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462496840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3462496840
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2423730041
Short name T466
Test name
Test status
Simulation time 1149850866 ps
CPU time 70.6 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:37:47 PM PDT 24
Peak memory 212364 kb
Host smart-eedcf725-ebea-43df-88ee-5e5769038892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423730041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2423730041
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.916952844
Short name T473
Test name
Test status
Simulation time 104363984 ps
CPU time 5.65 seconds
Started Jul 26 05:36:27 PM PDT 24
Finished Jul 26 05:36:32 PM PDT 24
Peak memory 218792 kb
Host smart-aa29ffd0-6bf1-42c6-a9c2-763b165dd11f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916952844 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.916952844
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3245414720
Short name T75
Test name
Test status
Simulation time 131335420 ps
CPU time 5.05 seconds
Started Jul 26 05:36:28 PM PDT 24
Finished Jul 26 05:36:33 PM PDT 24
Peak memory 218712 kb
Host smart-3d447847-e25c-4c23-95f3-9dc867994d0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245414720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3245414720
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4049787028
Short name T94
Test name
Test status
Simulation time 7458867657 ps
CPU time 21.68 seconds
Started Jul 26 05:36:25 PM PDT 24
Finished Jul 26 05:36:47 PM PDT 24
Peak memory 210672 kb
Host smart-ca18711f-958f-4db4-bc3f-c04003b08c80
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049787028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4049787028
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3952875952
Short name T452
Test name
Test status
Simulation time 88394271 ps
CPU time 4.35 seconds
Started Jul 26 05:36:31 PM PDT 24
Finished Jul 26 05:36:36 PM PDT 24
Peak memory 210496 kb
Host smart-25e50a7a-3364-4094-9242-8c53f6947d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952875952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3952875952
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3082557846
Short name T464
Test name
Test status
Simulation time 85411894 ps
CPU time 7.3 seconds
Started Jul 26 05:36:28 PM PDT 24
Finished Jul 26 05:36:35 PM PDT 24
Peak memory 218816 kb
Host smart-b3349192-a6e2-4b70-a974-fbb90bdd5fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082557846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3082557846
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1101707239
Short name T108
Test name
Test status
Simulation time 185922961 ps
CPU time 36.8 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:37:07 PM PDT 24
Peak memory 211304 kb
Host smart-e5a429a3-2667-4237-ba36-3f402939c81a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101707239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1101707239
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1691399012
Short name T478
Test name
Test status
Simulation time 102115972 ps
CPU time 5.28 seconds
Started Jul 26 05:36:29 PM PDT 24
Finished Jul 26 05:36:34 PM PDT 24
Peak memory 215844 kb
Host smart-45489591-5ea7-42f2-bd82-d28d8da489f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691399012 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1691399012
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4139944576
Short name T472
Test name
Test status
Simulation time 521260583 ps
CPU time 4.93 seconds
Started Jul 26 05:36:32 PM PDT 24
Finished Jul 26 05:36:37 PM PDT 24
Peak memory 218600 kb
Host smart-05d3a6c7-0ee3-40f0-b80c-1ce2b8132939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139944576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4139944576
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.878551461
Short name T410
Test name
Test status
Simulation time 13012764797 ps
CPU time 46.12 seconds
Started Jul 26 05:36:29 PM PDT 24
Finished Jul 26 05:37:15 PM PDT 24
Peak memory 210636 kb
Host smart-1109199c-2182-4531-aacc-dd85f30b5f03
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878551461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.878551461
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2241241289
Short name T442
Test name
Test status
Simulation time 1244372077 ps
CPU time 4.76 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:36:35 PM PDT 24
Peak memory 218772 kb
Host smart-655ef3c3-f031-4090-b221-10a405c7570a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241241289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2241241289
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.427735713
Short name T391
Test name
Test status
Simulation time 131398185 ps
CPU time 8.63 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:36:39 PM PDT 24
Peak memory 218820 kb
Host smart-0f378572-0984-413d-b202-ee3779f613cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427735713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.427735713
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1671684222
Short name T106
Test name
Test status
Simulation time 790280163 ps
CPU time 36.53 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:37:07 PM PDT 24
Peak memory 218748 kb
Host smart-f52153b2-e702-4133-a2d4-01b617f612cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671684222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1671684222
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2197013650
Short name T383
Test name
Test status
Simulation time 421993525 ps
CPU time 6.44 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:36:37 PM PDT 24
Peak memory 218772 kb
Host smart-aca7991a-26ba-4d07-be2a-51aaefb1582d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197013650 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2197013650
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1588019377
Short name T393
Test name
Test status
Simulation time 127757074 ps
CPU time 5.03 seconds
Started Jul 26 05:36:31 PM PDT 24
Finished Jul 26 05:36:37 PM PDT 24
Peak memory 218536 kb
Host smart-f3aa5f36-c03c-4fc3-a99d-8d7b2db46554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588019377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1588019377
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.781717016
Short name T419
Test name
Test status
Simulation time 1319162924 ps
CPU time 18.19 seconds
Started Jul 26 05:36:31 PM PDT 24
Finished Jul 26 05:36:50 PM PDT 24
Peak memory 210544 kb
Host smart-4a03309f-50f5-4cb8-9c8e-8e38a9c0a8a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781717016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.781717016
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2833035142
Short name T70
Test name
Test status
Simulation time 85411040 ps
CPU time 4.33 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:36:35 PM PDT 24
Peak memory 210604 kb
Host smart-ae37ab9c-ce3a-4d9c-89b5-26100615349a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833035142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2833035142
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2416693800
Short name T450
Test name
Test status
Simulation time 144901766 ps
CPU time 7.57 seconds
Started Jul 26 05:36:30 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 218832 kb
Host smart-b48616aa-a6a8-4e05-99ce-4dc47a2a3b7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416693800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2416693800
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.567018829
Short name T103
Test name
Test status
Simulation time 353961987 ps
CPU time 69.79 seconds
Started Jul 26 05:36:32 PM PDT 24
Finished Jul 26 05:37:42 PM PDT 24
Peak memory 213120 kb
Host smart-9e27dcfd-4e9f-40e4-9033-092c14462156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567018829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.567018829
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.741909095
Short name T476
Test name
Test status
Simulation time 304510252 ps
CPU time 5.94 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:36:39 PM PDT 24
Peak memory 218788 kb
Host smart-832eda87-7c86-4b70-98a1-3b7775a1d554
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741909095 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.741909095
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.312151924
Short name T63
Test name
Test status
Simulation time 518142798 ps
CPU time 4.88 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 210536 kb
Host smart-2603b170-f7fe-4d56-9ce0-81379875cc0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312151924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.312151924
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2221144342
Short name T467
Test name
Test status
Simulation time 550263256 ps
CPU time 21.78 seconds
Started Jul 26 05:36:32 PM PDT 24
Finished Jul 26 05:36:54 PM PDT 24
Peak memory 210548 kb
Host smart-25cc7647-16b1-4e2b-a38a-216d301dd1d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221144342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2221144342
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.968636326
Short name T403
Test name
Test status
Simulation time 594177379 ps
CPU time 4.14 seconds
Started Jul 26 05:36:44 PM PDT 24
Finished Jul 26 05:36:48 PM PDT 24
Peak memory 210640 kb
Host smart-1353f071-59cb-430b-87dc-9550d29d62b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968636326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.968636326
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.186358365
Short name T457
Test name
Test status
Simulation time 164226121 ps
CPU time 9.81 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:36:46 PM PDT 24
Peak memory 215736 kb
Host smart-6729ad78-53c7-4e48-8f1f-8803ce4d5b70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186358365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.186358365
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2165089982
Short name T58
Test name
Test status
Simulation time 1512137557 ps
CPU time 66.6 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:37:40 PM PDT 24
Peak memory 212364 kb
Host smart-b8f3b3da-6243-4b5f-93c4-86e6c6e2c332
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165089982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2165089982
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.875355856
Short name T449
Test name
Test status
Simulation time 559180379 ps
CPU time 5.69 seconds
Started Jul 26 05:36:32 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 214744 kb
Host smart-15ad1ef1-2416-4e0f-9b4e-677f8f13d996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875355856 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.875355856
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1110180926
Short name T435
Test name
Test status
Simulation time 175283130 ps
CPU time 4.07 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:36:43 PM PDT 24
Peak memory 210576 kb
Host smart-d4169254-9744-4027-9241-6fe9c6ab1684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110180926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1110180926
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.29354045
Short name T405
Test name
Test status
Simulation time 572743000 ps
CPU time 27.79 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:37:05 PM PDT 24
Peak memory 210636 kb
Host smart-46ede853-a3b8-4721-bc9b-546ca4690e60
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29354045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pass
thru_mem_tl_intg_err.29354045
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.648332774
Short name T396
Test name
Test status
Simulation time 492298308 ps
CPU time 4.47 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:36:38 PM PDT 24
Peak memory 210660 kb
Host smart-69221961-fa3b-404a-9af7-9575fbd7cc00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648332774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.648332774
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3880707261
Short name T456
Test name
Test status
Simulation time 127383933 ps
CPU time 8.21 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:36:41 PM PDT 24
Peak memory 215544 kb
Host smart-fb38e8b2-524b-4d8f-b087-1ddc4887748f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880707261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3880707261
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.923227215
Short name T102
Test name
Test status
Simulation time 1146428889 ps
CPU time 77.18 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:37:55 PM PDT 24
Peak memory 218780 kb
Host smart-bb12e32c-406c-4a85-8878-35420d45699a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923227215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.923227215
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3074903150
Short name T166
Test name
Test status
Simulation time 348473588 ps
CPU time 4.22 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:36:39 PM PDT 24
Peak memory 211700 kb
Host smart-cda0d465-43b1-4599-98d0-7b21f9e0cb2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074903150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3074903150
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3179300381
Short name T349
Test name
Test status
Simulation time 1930826229 ps
CPU time 134.12 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 237536 kb
Host smart-a6968334-6897-4129-8b4b-46fce125e3a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179300381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3179300381
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.27645542
Short name T369
Test name
Test status
Simulation time 312072931 ps
CPU time 10.88 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:36:47 PM PDT 24
Peak memory 212524 kb
Host smart-d970dd1b-8a1c-4ffc-98ef-b29bf7d77c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27645542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.27645542
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.213369597
Short name T147
Test name
Test status
Simulation time 95707059 ps
CPU time 5.44 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:36:43 PM PDT 24
Peak memory 211840 kb
Host smart-9ccb0ff8-7931-4418-96d9-fb1ac6a000f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213369597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.213369597
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3265394778
Short name T26
Test name
Test status
Simulation time 163688049 ps
CPU time 52.4 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:37:32 PM PDT 24
Peak memory 237144 kb
Host smart-ee709a4f-4451-4073-b4be-62c838c9bebb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265394778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3265394778
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2737819600
Short name T233
Test name
Test status
Simulation time 270006017 ps
CPU time 12.1 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:36:49 PM PDT 24
Peak memory 212764 kb
Host smart-b8569bc2-f9ab-476e-8520-8c33b224e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737819600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2737819600
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2709272513
Short name T213
Test name
Test status
Simulation time 2691929472 ps
CPU time 13.45 seconds
Started Jul 26 05:36:33 PM PDT 24
Finished Jul 26 05:36:47 PM PDT 24
Peak memory 215672 kb
Host smart-8f2941e5-7270-4aa0-b535-8ebb9aa17382
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709272513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2709272513
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1636819638
Short name T4
Test name
Test status
Simulation time 15369769614 ps
CPU time 302.66 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:41:41 PM PDT 24
Peak memory 223028 kb
Host smart-85d55f5f-b350-46b6-868b-7d9f55326710
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636819638 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1636819638
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4094874834
Short name T211
Test name
Test status
Simulation time 520805346 ps
CPU time 5.11 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:36:39 PM PDT 24
Peak memory 211692 kb
Host smart-be372f7e-5044-4de7-821b-aac6f467fa44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094874834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4094874834
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1458378080
Short name T321
Test name
Test status
Simulation time 1398402146 ps
CPU time 63.66 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:37:43 PM PDT 24
Peak memory 213008 kb
Host smart-51f19353-9f09-4515-8d0c-f83b6a87d7cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458378080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1458378080
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2862561531
Short name T254
Test name
Test status
Simulation time 267212491 ps
CPU time 6.28 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:36:45 PM PDT 24
Peak memory 211828 kb
Host smart-65bbd27b-7767-477a-9bd7-3959ce9b0bfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862561531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2862561531
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3382380742
Short name T25
Test name
Test status
Simulation time 328316439 ps
CPU time 57.92 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:37:33 PM PDT 24
Peak memory 240668 kb
Host smart-458f5112-7295-4a47-b735-e30074f2ceb4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382380742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3382380742
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1156471476
Short name T113
Test name
Test status
Simulation time 976551173 ps
CPU time 11.91 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:36:52 PM PDT 24
Peak memory 214548 kb
Host smart-0ca60f37-daba-4ce7-aa29-24e107cedb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156471476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1156471476
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1704042224
Short name T229
Test name
Test status
Simulation time 2832582720 ps
CPU time 29.76 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:37:06 PM PDT 24
Peak memory 217032 kb
Host smart-5d4431c5-71cb-4f72-9777-9711b3a9a6e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704042224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1704042224
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.450143030
Short name T266
Test name
Test status
Simulation time 161160213636 ps
CPU time 3008.1 seconds
Started Jul 26 05:36:44 PM PDT 24
Finished Jul 26 06:26:53 PM PDT 24
Peak memory 244704 kb
Host smart-2864902a-5bd3-4a92-8921-ca7dd4344a56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450143030 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.450143030
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4276488069
Short name T41
Test name
Test status
Simulation time 143460174 ps
CPU time 5.07 seconds
Started Jul 26 05:36:47 PM PDT 24
Finished Jul 26 05:36:52 PM PDT 24
Peak memory 211768 kb
Host smart-b41ca553-2619-47a2-b027-a4d5493512cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276488069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4276488069
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.260983118
Short name T367
Test name
Test status
Simulation time 10822206618 ps
CPU time 128.9 seconds
Started Jul 26 05:36:47 PM PDT 24
Finished Jul 26 05:38:56 PM PDT 24
Peak memory 238208 kb
Host smart-6a0e2c33-7e5c-49e9-bc9a-ea6145050f91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260983118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.260983118
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.381735670
Short name T214
Test name
Test status
Simulation time 998039152 ps
CPU time 11.45 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:36:51 PM PDT 24
Peak memory 212612 kb
Host smart-ce4452b3-8003-4fd2-bd20-4e895a7a414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381735670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.381735670
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1673965900
Short name T196
Test name
Test status
Simulation time 373584063 ps
CPU time 5.64 seconds
Started Jul 26 05:36:47 PM PDT 24
Finished Jul 26 05:36:53 PM PDT 24
Peak memory 211900 kb
Host smart-e9f9e811-f2c1-4266-b957-ec9914f90e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673965900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1673965900
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.690907910
Short name T10
Test name
Test status
Simulation time 189038406 ps
CPU time 10.27 seconds
Started Jul 26 05:36:46 PM PDT 24
Finished Jul 26 05:36:57 PM PDT 24
Peak memory 213820 kb
Host smart-759e01f5-4cac-4c98-9018-94c2890a363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690907910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.690907910
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3552235681
Short name T281
Test name
Test status
Simulation time 107002719 ps
CPU time 8.51 seconds
Started Jul 26 05:36:48 PM PDT 24
Finished Jul 26 05:36:56 PM PDT 24
Peak memory 211760 kb
Host smart-b4ce3273-dbb8-4aa3-81a9-14508d581c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552235681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3552235681
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1103267967
Short name T354
Test name
Test status
Simulation time 47768041442 ps
CPU time 1893.08 seconds
Started Jul 26 05:36:47 PM PDT 24
Finished Jul 26 06:08:20 PM PDT 24
Peak memory 236060 kb
Host smart-c9cc8a25-b145-4723-8b16-cb3e79fbafc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103267967 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1103267967
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.224591135
Short name T322
Test name
Test status
Simulation time 175340796 ps
CPU time 4.3 seconds
Started Jul 26 05:36:41 PM PDT 24
Finished Jul 26 05:36:46 PM PDT 24
Peak memory 211716 kb
Host smart-dcde020b-a0b9-4892-8788-4d1da7dd337a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224591135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.224591135
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4284384672
Short name T131
Test name
Test status
Simulation time 1535086385 ps
CPU time 86.17 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:38:06 PM PDT 24
Peak memory 228704 kb
Host smart-d69b8726-5602-4cad-a999-732c14cc5883
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284384672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4284384672
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2571541566
Short name T9
Test name
Test status
Simulation time 1039264552 ps
CPU time 11.24 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:36:51 PM PDT 24
Peak memory 212752 kb
Host smart-bc753cb5-667b-4f2e-91b2-50f63f0e0ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571541566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2571541566
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.349127414
Short name T315
Test name
Test status
Simulation time 140253818 ps
CPU time 6.62 seconds
Started Jul 26 05:36:48 PM PDT 24
Finished Jul 26 05:36:54 PM PDT 24
Peak memory 211900 kb
Host smart-29319688-1204-472c-aafd-17b78601e82c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349127414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.349127414
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3492314226
Short name T188
Test name
Test status
Simulation time 1094408385 ps
CPU time 12.2 seconds
Started Jul 26 05:36:47 PM PDT 24
Finished Jul 26 05:36:59 PM PDT 24
Peak memory 212908 kb
Host smart-68802a27-60cb-4ec5-a4ad-a6d70d0f3a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492314226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3492314226
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2577760927
Short name T152
Test name
Test status
Simulation time 841050484 ps
CPU time 12.47 seconds
Started Jul 26 05:36:46 PM PDT 24
Finished Jul 26 05:36:59 PM PDT 24
Peak memory 214108 kb
Host smart-91254edc-7c54-4956-8dda-745ac42f3bb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577760927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2577760927
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.487238255
Short name T344
Test name
Test status
Simulation time 346461252 ps
CPU time 4.28 seconds
Started Jul 26 05:36:47 PM PDT 24
Finished Jul 26 05:36:51 PM PDT 24
Peak memory 211772 kb
Host smart-268c5b65-01f8-4ff2-8c62-587126775447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487238255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.487238255
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1535111690
Short name T364
Test name
Test status
Simulation time 1352991985 ps
CPU time 83.49 seconds
Started Jul 26 05:36:41 PM PDT 24
Finished Jul 26 05:38:04 PM PDT 24
Peak memory 238140 kb
Host smart-7212028c-6306-4ddf-8194-9fc86af69113
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535111690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1535111690
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1067333314
Short name T191
Test name
Test status
Simulation time 838542910 ps
CPU time 9.25 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:36:49 PM PDT 24
Peak memory 212576 kb
Host smart-ed98c6b4-0136-4baf-bc65-2501d31b69bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067333314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1067333314
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2266347510
Short name T156
Test name
Test status
Simulation time 284309099 ps
CPU time 6.48 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:36:47 PM PDT 24
Peak memory 212048 kb
Host smart-b6cca803-51f1-4af5-b372-8e396f109099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266347510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2266347510
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2608788149
Short name T235
Test name
Test status
Simulation time 345403977 ps
CPU time 9.91 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:36:47 PM PDT 24
Peak memory 214756 kb
Host smart-0d1026aa-8a9c-4e5c-9a05-e1e9af1e9c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608788149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2608788149
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3550819271
Short name T15
Test name
Test status
Simulation time 2705993778 ps
CPU time 30.79 seconds
Started Jul 26 05:36:47 PM PDT 24
Finished Jul 26 05:37:18 PM PDT 24
Peak memory 217140 kb
Host smart-efbb091c-c639-40a5-9a6a-b5f674d24d9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550819271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3550819271
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2704684526
Short name T271
Test name
Test status
Simulation time 33476271892 ps
CPU time 994.47 seconds
Started Jul 26 05:36:48 PM PDT 24
Finished Jul 26 05:53:23 PM PDT 24
Peak memory 236360 kb
Host smart-db05d3b3-ad0c-402a-a6cc-e758efd1970f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704684526 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2704684526
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4121257354
Short name T194
Test name
Test status
Simulation time 85538187 ps
CPU time 4.31 seconds
Started Jul 26 05:36:51 PM PDT 24
Finished Jul 26 05:36:55 PM PDT 24
Peak memory 211740 kb
Host smart-71108803-7d64-486a-8aca-a6b5f30ac701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121257354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4121257354
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3104278590
Short name T127
Test name
Test status
Simulation time 1560095272 ps
CPU time 84.89 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:38:04 PM PDT 24
Peak memory 237680 kb
Host smart-39faa348-66a2-402e-adb2-edca3484a618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104278590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3104278590
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3565998661
Short name T288
Test name
Test status
Simulation time 259083554 ps
CPU time 11.04 seconds
Started Jul 26 05:36:47 PM PDT 24
Finished Jul 26 05:36:58 PM PDT 24
Peak memory 212308 kb
Host smart-8e68c939-243f-4298-ba4d-e5df30b4f045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565998661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3565998661
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3964713327
Short name T173
Test name
Test status
Simulation time 552003189 ps
CPU time 6.09 seconds
Started Jul 26 05:36:47 PM PDT 24
Finished Jul 26 05:36:53 PM PDT 24
Peak memory 211896 kb
Host smart-bccc0117-167a-47a8-9294-c87f28213f54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964713327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3964713327
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.484036131
Short name T129
Test name
Test status
Simulation time 501487870 ps
CPU time 10.33 seconds
Started Jul 26 05:36:41 PM PDT 24
Finished Jul 26 05:36:52 PM PDT 24
Peak memory 214340 kb
Host smart-70aa689f-dbb1-4e79-8ed7-8cc925b05e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484036131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.484036131
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2423628138
Short name T205
Test name
Test status
Simulation time 964978191 ps
CPU time 40.38 seconds
Started Jul 26 05:36:42 PM PDT 24
Finished Jul 26 05:37:23 PM PDT 24
Peak memory 219744 kb
Host smart-247603a9-c349-49ec-8f9b-450706dba00b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423628138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2423628138
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3906892920
Short name T374
Test name
Test status
Simulation time 88796983475 ps
CPU time 1001.51 seconds
Started Jul 26 05:36:50 PM PDT 24
Finished Jul 26 05:53:32 PM PDT 24
Peak memory 236344 kb
Host smart-457f03ca-6e64-4b22-b5f1-b0559eb3b724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906892920 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3906892920
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.612433729
Short name T3
Test name
Test status
Simulation time 431363227 ps
CPU time 5.04 seconds
Started Jul 26 05:36:55 PM PDT 24
Finished Jul 26 05:37:00 PM PDT 24
Peak memory 211932 kb
Host smart-43547e43-527e-4df6-a466-25f0b27eeaf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612433729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.612433729
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3937188313
Short name T265
Test name
Test status
Simulation time 13354352548 ps
CPU time 169.76 seconds
Started Jul 26 05:36:50 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 234108 kb
Host smart-8e2e8a87-c3d6-4a87-ae05-6bd01c28fad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937188313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3937188313
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.296491154
Short name T176
Test name
Test status
Simulation time 261840319 ps
CPU time 11.28 seconds
Started Jul 26 05:36:53 PM PDT 24
Finished Jul 26 05:37:05 PM PDT 24
Peak memory 212460 kb
Host smart-a2ccf469-07aa-4cba-9f2d-0692c6763063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296491154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.296491154
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.389754464
Short name T243
Test name
Test status
Simulation time 637468681 ps
CPU time 6.68 seconds
Started Jul 26 05:36:48 PM PDT 24
Finished Jul 26 05:36:55 PM PDT 24
Peak memory 211840 kb
Host smart-51358caf-d7d6-4a3c-9c7d-8f7b7551dde7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389754464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.389754464
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4154779934
Short name T150
Test name
Test status
Simulation time 196538851 ps
CPU time 10.5 seconds
Started Jul 26 05:36:50 PM PDT 24
Finished Jul 26 05:37:01 PM PDT 24
Peak memory 214116 kb
Host smart-d94c2d6b-5361-4bb2-9874-6fd69b99cf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154779934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4154779934
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1779058959
Short name T342
Test name
Test status
Simulation time 1166897710 ps
CPU time 33.79 seconds
Started Jul 26 05:36:49 PM PDT 24
Finished Jul 26 05:37:23 PM PDT 24
Peak memory 217936 kb
Host smart-fc84fbd3-d0a0-450a-b234-6122ee7776cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779058959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1779058959
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.243782614
Short name T297
Test name
Test status
Simulation time 22448979821 ps
CPU time 3318.2 seconds
Started Jul 26 05:36:50 PM PDT 24
Finished Jul 26 06:32:09 PM PDT 24
Peak memory 232488 kb
Host smart-d3f73bda-1008-4c41-8eb0-f42b39be4cef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243782614 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.243782614
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.193652800
Short name T248
Test name
Test status
Simulation time 126952225 ps
CPU time 5.14 seconds
Started Jul 26 05:36:50 PM PDT 24
Finished Jul 26 05:36:55 PM PDT 24
Peak memory 211756 kb
Host smart-594e7b9f-9732-4bf6-97ec-1c0d74e9f16d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193652800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.193652800
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2260170625
Short name T262
Test name
Test status
Simulation time 1630273767 ps
CPU time 99.72 seconds
Started Jul 26 05:36:50 PM PDT 24
Finished Jul 26 05:38:30 PM PDT 24
Peak memory 238156 kb
Host smart-4be3e2c0-85b4-48d8-968c-fe47abcf6c5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260170625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2260170625
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.36063259
Short name T378
Test name
Test status
Simulation time 666326019 ps
CPU time 9.76 seconds
Started Jul 26 05:36:52 PM PDT 24
Finished Jul 26 05:37:02 PM PDT 24
Peak memory 212656 kb
Host smart-ff45793a-81fa-4372-8c16-01d36287dc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36063259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.36063259
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.883615587
Short name T252
Test name
Test status
Simulation time 527240741 ps
CPU time 6.19 seconds
Started Jul 26 05:36:50 PM PDT 24
Finished Jul 26 05:36:56 PM PDT 24
Peak memory 211900 kb
Host smart-52135e84-cab9-485d-b964-002439bc6f75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883615587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.883615587
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1572135196
Short name T366
Test name
Test status
Simulation time 269455312 ps
CPU time 12.1 seconds
Started Jul 26 05:36:49 PM PDT 24
Finished Jul 26 05:37:01 PM PDT 24
Peak memory 214392 kb
Host smart-c242a027-d986-46de-b1a0-cdf47f9bb4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572135196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1572135196
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1815082915
Short name T202
Test name
Test status
Simulation time 11686666990 ps
CPU time 26.75 seconds
Started Jul 26 05:36:48 PM PDT 24
Finished Jul 26 05:37:15 PM PDT 24
Peak memory 218084 kb
Host smart-794c14c2-5c1a-4b8e-a287-8b2f785f406e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815082915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1815082915
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3638691995
Short name T208
Test name
Test status
Simulation time 21006253766 ps
CPU time 7758.74 seconds
Started Jul 26 05:36:51 PM PDT 24
Finished Jul 26 07:46:11 PM PDT 24
Peak memory 234644 kb
Host smart-b17bb23a-ca9e-4255-bbbd-3a0fccd3b423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638691995 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3638691995
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1159747938
Short name T240
Test name
Test status
Simulation time 772648620 ps
CPU time 5.23 seconds
Started Jul 26 05:36:51 PM PDT 24
Finished Jul 26 05:36:56 PM PDT 24
Peak memory 211784 kb
Host smart-01a14dfd-df32-4c51-87e4-1529f5410e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159747938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1159747938
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1270782261
Short name T40
Test name
Test status
Simulation time 7833938249 ps
CPU time 96.02 seconds
Started Jul 26 05:36:50 PM PDT 24
Finished Jul 26 05:38:26 PM PDT 24
Peak memory 226064 kb
Host smart-8d04eba2-8621-40fa-a5da-ede7b3069c07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270782261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1270782261
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4195535887
Short name T376
Test name
Test status
Simulation time 355863623 ps
CPU time 9.53 seconds
Started Jul 26 05:36:55 PM PDT 24
Finished Jul 26 05:37:04 PM PDT 24
Peak memory 212992 kb
Host smart-dc70c263-26fb-48ea-ad87-2c64fe72ca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195535887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4195535887
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.239761666
Short name T206
Test name
Test status
Simulation time 485692496 ps
CPU time 5.53 seconds
Started Jul 26 05:36:51 PM PDT 24
Finished Jul 26 05:36:57 PM PDT 24
Peak memory 211904 kb
Host smart-ddaec79c-4477-46e0-9887-0c5b04916389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239761666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.239761666
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1589047032
Short name T157
Test name
Test status
Simulation time 271137891 ps
CPU time 13.02 seconds
Started Jul 26 05:36:51 PM PDT 24
Finished Jul 26 05:37:04 PM PDT 24
Peak memory 212900 kb
Host smart-76b90281-a355-4378-9762-9d58b1d27b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589047032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1589047032
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.39249549
Short name T280
Test name
Test status
Simulation time 690798914 ps
CPU time 27.81 seconds
Started Jul 26 05:36:53 PM PDT 24
Finished Jul 26 05:37:21 PM PDT 24
Peak memory 217988 kb
Host smart-c0983999-243a-4f1e-8317-cada145d03c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39249549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.rom_ctrl_stress_all.39249549
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1946430421
Short name T346
Test name
Test status
Simulation time 85528959 ps
CPU time 4.3 seconds
Started Jul 26 05:36:52 PM PDT 24
Finished Jul 26 05:36:56 PM PDT 24
Peak memory 211724 kb
Host smart-2056be2d-6b50-4572-9b87-7e56663bf0de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946430421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1946430421
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3396718320
Short name T50
Test name
Test status
Simulation time 2474261978 ps
CPU time 175.13 seconds
Started Jul 26 05:36:52 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 229004 kb
Host smart-190d8ac7-4259-4740-86d4-5ac62e31297c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396718320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3396718320
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2632347284
Short name T224
Test name
Test status
Simulation time 1038144217 ps
CPU time 11.41 seconds
Started Jul 26 05:36:55 PM PDT 24
Finished Jul 26 05:37:07 PM PDT 24
Peak memory 212832 kb
Host smart-9ecb91a5-5032-43de-a9b8-315001dae3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632347284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2632347284
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3161932
Short name T231
Test name
Test status
Simulation time 97656256 ps
CPU time 5.3 seconds
Started Jul 26 05:36:52 PM PDT 24
Finished Jul 26 05:36:57 PM PDT 24
Peak memory 211888 kb
Host smart-56bc0d10-606a-4a89-8377-9b3f6de73ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3161932
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2215700097
Short name T236
Test name
Test status
Simulation time 274225215 ps
CPU time 10.4 seconds
Started Jul 26 05:36:52 PM PDT 24
Finished Jul 26 05:37:02 PM PDT 24
Peak memory 214468 kb
Host smart-2d11f04f-1633-4178-894b-ddde06489564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215700097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2215700097
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2599824231
Short name T33
Test name
Test status
Simulation time 696120971 ps
CPU time 10.33 seconds
Started Jul 26 05:36:52 PM PDT 24
Finished Jul 26 05:37:03 PM PDT 24
Peak memory 215096 kb
Host smart-3a915680-e8de-45e4-8a18-d9cef9870c4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599824231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2599824231
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.4131433620
Short name T303
Test name
Test status
Simulation time 202710166273 ps
CPU time 1959.69 seconds
Started Jul 26 05:36:50 PM PDT 24
Finished Jul 26 06:09:30 PM PDT 24
Peak memory 237432 kb
Host smart-93c52975-6b4c-4810-9a29-266cb7390103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131433620 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.4131433620
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1467196794
Short name T286
Test name
Test status
Simulation time 1140417196 ps
CPU time 5.31 seconds
Started Jul 26 05:36:56 PM PDT 24
Finished Jul 26 05:37:01 PM PDT 24
Peak memory 211680 kb
Host smart-09eebcc9-4485-4390-8c73-8f69e22ebe0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467196794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1467196794
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2625455001
Short name T326
Test name
Test status
Simulation time 2106009867 ps
CPU time 125.24 seconds
Started Jul 26 05:36:58 PM PDT 24
Finished Jul 26 05:39:04 PM PDT 24
Peak memory 228580 kb
Host smart-da7cfc39-17b4-4003-bb63-b6ecbd433fc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625455001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2625455001
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2515815560
Short name T371
Test name
Test status
Simulation time 960615770 ps
CPU time 11.22 seconds
Started Jul 26 05:36:57 PM PDT 24
Finished Jul 26 05:37:09 PM PDT 24
Peak memory 211840 kb
Host smart-31883a7b-0bb7-4e34-8f82-e2584450c5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515815560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2515815560
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3110380664
Short name T363
Test name
Test status
Simulation time 141867899 ps
CPU time 6.62 seconds
Started Jul 26 05:37:02 PM PDT 24
Finished Jul 26 05:37:09 PM PDT 24
Peak memory 211788 kb
Host smart-8a6aaab7-4d4b-4b6d-ab05-ec1b67fa1563
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110380664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3110380664
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.402859362
Short name T163
Test name
Test status
Simulation time 193485847 ps
CPU time 9.78 seconds
Started Jul 26 05:36:53 PM PDT 24
Finished Jul 26 05:37:03 PM PDT 24
Peak memory 214044 kb
Host smart-62e7634b-776a-4d39-9f2c-ea443a165ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402859362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.402859362
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2721566919
Short name T118
Test name
Test status
Simulation time 623893831 ps
CPU time 17.79 seconds
Started Jul 26 05:36:53 PM PDT 24
Finished Jul 26 05:37:11 PM PDT 24
Peak memory 214828 kb
Host smart-05450eea-cf78-42f3-9738-9ee50a403de2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721566919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2721566919
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.256068998
Short name T186
Test name
Test status
Simulation time 11708411498 ps
CPU time 3469.28 seconds
Started Jul 26 05:36:58 PM PDT 24
Finished Jul 26 06:34:48 PM PDT 24
Peak memory 224320 kb
Host smart-8fc258c3-a269-4b97-aea3-7d2a7c8933ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256068998 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.256068998
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1206640730
Short name T174
Test name
Test status
Simulation time 88108797 ps
CPU time 4.57 seconds
Started Jul 26 05:36:59 PM PDT 24
Finished Jul 26 05:37:04 PM PDT 24
Peak memory 211772 kb
Host smart-20aa56aa-473d-41f2-a2d3-c91102025acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206640730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1206640730
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3423589602
Short name T272
Test name
Test status
Simulation time 4207788566 ps
CPU time 92.28 seconds
Started Jul 26 05:37:01 PM PDT 24
Finished Jul 26 05:38:33 PM PDT 24
Peak memory 238280 kb
Host smart-d70f9ba3-47de-43c3-8f44-a54cb893f969
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423589602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3423589602
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1560186108
Short name T316
Test name
Test status
Simulation time 169759609 ps
CPU time 9.84 seconds
Started Jul 26 05:36:57 PM PDT 24
Finished Jul 26 05:37:07 PM PDT 24
Peak memory 212600 kb
Host smart-910ec452-d5ab-4a50-a4ba-0b267cb30fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560186108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1560186108
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1396972979
Short name T370
Test name
Test status
Simulation time 167590042 ps
CPU time 7.09 seconds
Started Jul 26 05:37:00 PM PDT 24
Finished Jul 26 05:37:07 PM PDT 24
Peak memory 211904 kb
Host smart-c601a5ca-4997-49b8-bc8d-221e4aa4e095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396972979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1396972979
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.130120738
Short name T311
Test name
Test status
Simulation time 1001572877 ps
CPU time 17.76 seconds
Started Jul 26 05:36:58 PM PDT 24
Finished Jul 26 05:37:16 PM PDT 24
Peak memory 214164 kb
Host smart-618d38ab-6e2f-4af8-ac3b-a5f9b2f76e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130120738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.130120738
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3413501221
Short name T302
Test name
Test status
Simulation time 1162539637 ps
CPU time 26.15 seconds
Started Jul 26 05:37:09 PM PDT 24
Finished Jul 26 05:37:36 PM PDT 24
Peak memory 216612 kb
Host smart-e328c275-ab50-4656-8139-8a95463abff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413501221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3413501221
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1578172876
Short name T305
Test name
Test status
Simulation time 133670462 ps
CPU time 5.03 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:36:41 PM PDT 24
Peak memory 211700 kb
Host smart-afa7b95a-47ab-43d3-bb68-6656b51a1ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578172876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1578172876
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3797702307
Short name T290
Test name
Test status
Simulation time 10836249433 ps
CPU time 98.34 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:38:17 PM PDT 24
Peak memory 234328 kb
Host smart-35cf712f-1024-4f59-a2e2-5ab128d8a99e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797702307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3797702307
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3940573106
Short name T337
Test name
Test status
Simulation time 997665426 ps
CPU time 11.31 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:36:51 PM PDT 24
Peak memory 212608 kb
Host smart-384d03e9-d66a-40b3-ba48-a34976409b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940573106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3940573106
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2460123315
Short name T228
Test name
Test status
Simulation time 1326916091 ps
CPU time 6.75 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:36:45 PM PDT 24
Peak memory 211828 kb
Host smart-3d7be076-1e90-41d0-af94-824869becdf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460123315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2460123315
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3738298087
Short name T23
Test name
Test status
Simulation time 1090071709 ps
CPU time 97.18 seconds
Started Jul 26 05:36:42 PM PDT 24
Finished Jul 26 05:38:20 PM PDT 24
Peak memory 237080 kb
Host smart-3e74914d-a931-4f1e-b2e1-9601d62ca4e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738298087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3738298087
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2382610582
Short name T255
Test name
Test status
Simulation time 2362314906 ps
CPU time 11.72 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:36:52 PM PDT 24
Peak memory 214524 kb
Host smart-9f957b09-d9cf-4bbd-b756-9c6b05fb0cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382610582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2382610582
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1030277884
Short name T130
Test name
Test status
Simulation time 2630357315 ps
CPU time 32.08 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:37:06 PM PDT 24
Peak memory 216512 kb
Host smart-fb399ca9-aaa2-4d62-a418-2340bcc27bd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030277884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1030277884
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.642063758
Short name T54
Test name
Test status
Simulation time 31603276746 ps
CPU time 1228.05 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:57:06 PM PDT 24
Peak memory 236252 kb
Host smart-d5a67840-8ae1-4e7f-833c-7807eaa701d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642063758 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.642063758
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2524114979
Short name T123
Test name
Test status
Simulation time 278412773 ps
CPU time 5.28 seconds
Started Jul 26 05:37:13 PM PDT 24
Finished Jul 26 05:37:18 PM PDT 24
Peak memory 211752 kb
Host smart-b308c0de-0682-4923-bacf-70e6305194f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524114979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2524114979
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3108447881
Short name T36
Test name
Test status
Simulation time 4848746145 ps
CPU time 128.89 seconds
Started Jul 26 05:37:08 PM PDT 24
Finished Jul 26 05:39:17 PM PDT 24
Peak memory 238320 kb
Host smart-3425ae5a-de17-41e2-826c-b237afc62ba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108447881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3108447881
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2358654100
Short name T28
Test name
Test status
Simulation time 1035643867 ps
CPU time 15.93 seconds
Started Jul 26 05:36:58 PM PDT 24
Finished Jul 26 05:37:14 PM PDT 24
Peak memory 212744 kb
Host smart-52b2bac5-41e2-4aa7-87d2-86e1166a86fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358654100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2358654100
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.392628342
Short name T204
Test name
Test status
Simulation time 141622519 ps
CPU time 6.58 seconds
Started Jul 26 05:36:58 PM PDT 24
Finished Jul 26 05:37:05 PM PDT 24
Peak memory 211808 kb
Host smart-329bae86-2da7-47fd-933f-2e502fce0d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=392628342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.392628342
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.78251015
Short name T251
Test name
Test status
Simulation time 272428378 ps
CPU time 11.41 seconds
Started Jul 26 05:36:57 PM PDT 24
Finished Jul 26 05:37:08 PM PDT 24
Peak memory 213624 kb
Host smart-bcd99dcc-e069-4f2d-ad3c-17a3cd1ac4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78251015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.78251015
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3557799426
Short name T182
Test name
Test status
Simulation time 9516316266 ps
CPU time 27.95 seconds
Started Jul 26 05:36:58 PM PDT 24
Finished Jul 26 05:37:26 PM PDT 24
Peak memory 219808 kb
Host smart-025e7793-ae09-49b7-8756-3b37864b7b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557799426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3557799426
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1190572118
Short name T51
Test name
Test status
Simulation time 99730988113 ps
CPU time 4909.66 seconds
Started Jul 26 05:36:57 PM PDT 24
Finished Jul 26 06:58:48 PM PDT 24
Peak memory 236356 kb
Host smart-02ee5ab9-2106-4ed3-8da5-6f4d0fce71d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190572118 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1190572118
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3583800209
Short name T169
Test name
Test status
Simulation time 87646308 ps
CPU time 4.65 seconds
Started Jul 26 05:37:14 PM PDT 24
Finished Jul 26 05:37:19 PM PDT 24
Peak memory 211744 kb
Host smart-d642efe7-c183-4369-8f20-b988869ac26e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583800209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3583800209
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3108346214
Short name T38
Test name
Test status
Simulation time 9861179837 ps
CPU time 110.39 seconds
Started Jul 26 05:37:22 PM PDT 24
Finished Jul 26 05:39:12 PM PDT 24
Peak memory 213008 kb
Host smart-5ce00f3a-0b8a-4fc6-9e08-33fe0d5d6d24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108346214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3108346214
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4214480578
Short name T312
Test name
Test status
Simulation time 2048085659 ps
CPU time 16 seconds
Started Jul 26 05:37:10 PM PDT 24
Finished Jul 26 05:37:26 PM PDT 24
Peak memory 213428 kb
Host smart-751f35b6-709d-41ff-b763-99f959bb6f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214480578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4214480578
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3858931724
Short name T90
Test name
Test status
Simulation time 875198476 ps
CPU time 6.18 seconds
Started Jul 26 05:37:13 PM PDT 24
Finished Jul 26 05:37:19 PM PDT 24
Peak memory 211896 kb
Host smart-c054274c-15b1-47fd-ac07-a46f8a095525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3858931724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3858931724
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3036704441
Short name T335
Test name
Test status
Simulation time 1202824712 ps
CPU time 11.81 seconds
Started Jul 26 05:37:17 PM PDT 24
Finished Jul 26 05:37:29 PM PDT 24
Peak memory 214608 kb
Host smart-9dc562cb-303f-4dc2-881c-82ca0573ba9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036704441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3036704441
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1510120159
Short name T132
Test name
Test status
Simulation time 864104579 ps
CPU time 9.15 seconds
Started Jul 26 05:37:11 PM PDT 24
Finished Jul 26 05:37:20 PM PDT 24
Peak memory 211728 kb
Host smart-dcbc08a1-83b0-4407-9d4e-f8ff6ea99927
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510120159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1510120159
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2447797302
Short name T198
Test name
Test status
Simulation time 260098687 ps
CPU time 5.06 seconds
Started Jul 26 05:37:22 PM PDT 24
Finished Jul 26 05:37:27 PM PDT 24
Peak memory 212008 kb
Host smart-40d8b714-9d7a-4b27-8464-6ae96e331672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447797302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2447797302
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4081222386
Short name T291
Test name
Test status
Simulation time 1625458426 ps
CPU time 92.69 seconds
Started Jul 26 05:37:21 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 212984 kb
Host smart-353b0f69-92d8-4881-a06a-b803a3b12797
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081222386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4081222386
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1305003614
Short name T358
Test name
Test status
Simulation time 342763723 ps
CPU time 11.03 seconds
Started Jul 26 05:37:23 PM PDT 24
Finished Jul 26 05:37:34 PM PDT 24
Peak memory 212692 kb
Host smart-63da8dfd-1209-47df-bd74-c52007857291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305003614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1305003614
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3179612301
Short name T122
Test name
Test status
Simulation time 556840396 ps
CPU time 6.66 seconds
Started Jul 26 05:37:13 PM PDT 24
Finished Jul 26 05:37:20 PM PDT 24
Peak memory 211812 kb
Host smart-5e23cb9e-6116-4540-b866-e227a638d59e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179612301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3179612301
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.39439260
Short name T212
Test name
Test status
Simulation time 754973205 ps
CPU time 10.46 seconds
Started Jul 26 05:37:10 PM PDT 24
Finished Jul 26 05:37:21 PM PDT 24
Peak memory 214796 kb
Host smart-86ed7ed0-3fac-4477-9947-f3c1872343fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39439260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.39439260
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.862589022
Short name T117
Test name
Test status
Simulation time 1633374321 ps
CPU time 15.52 seconds
Started Jul 26 05:37:15 PM PDT 24
Finished Jul 26 05:37:31 PM PDT 24
Peak memory 213956 kb
Host smart-9fab05bb-16fe-481c-acfb-8ebaa2685bf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862589022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.862589022
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3108593497
Short name T6
Test name
Test status
Simulation time 556352989 ps
CPU time 4.34 seconds
Started Jul 26 05:37:11 PM PDT 24
Finished Jul 26 05:37:15 PM PDT 24
Peak memory 211752 kb
Host smart-88d406a6-dfab-489f-9726-af6edda37828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108593497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3108593497
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3617810175
Short name T162
Test name
Test status
Simulation time 1981491765 ps
CPU time 99.47 seconds
Started Jul 26 05:37:12 PM PDT 24
Finished Jul 26 05:38:51 PM PDT 24
Peak memory 212948 kb
Host smart-64ff6da9-cb79-436d-8f99-b0ee9d454892
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617810175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3617810175
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3118603028
Short name T172
Test name
Test status
Simulation time 169027202 ps
CPU time 9.37 seconds
Started Jul 26 05:37:21 PM PDT 24
Finished Jul 26 05:37:30 PM PDT 24
Peak memory 212836 kb
Host smart-2ce0b9f5-8f9c-49d5-859b-f7dfa8cebaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118603028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3118603028
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2047742554
Short name T195
Test name
Test status
Simulation time 182729078 ps
CPU time 5.83 seconds
Started Jul 26 05:37:15 PM PDT 24
Finished Jul 26 05:37:21 PM PDT 24
Peak memory 211860 kb
Host smart-fcf1e031-ff1e-4deb-8542-20cdbe1868cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2047742554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2047742554
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4022902678
Short name T261
Test name
Test status
Simulation time 542272529 ps
CPU time 10.06 seconds
Started Jul 26 05:37:12 PM PDT 24
Finished Jul 26 05:37:23 PM PDT 24
Peak memory 214292 kb
Host smart-0a59440f-0e64-470a-a351-7e10d4c325c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022902678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4022902678
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.961377020
Short name T341
Test name
Test status
Simulation time 399047157 ps
CPU time 14.24 seconds
Started Jul 26 05:37:12 PM PDT 24
Finished Jul 26 05:37:27 PM PDT 24
Peak memory 216036 kb
Host smart-752b6a18-5823-4a52-a288-d08856989757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961377020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.961377020
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3915628608
Short name T52
Test name
Test status
Simulation time 454648203443 ps
CPU time 7933.76 seconds
Started Jul 26 05:37:11 PM PDT 24
Finished Jul 26 07:49:25 PM PDT 24
Peak memory 236288 kb
Host smart-5ee101c0-d188-49b6-a100-e20f02cc46e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915628608 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3915628608
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1963071464
Short name T351
Test name
Test status
Simulation time 128670247 ps
CPU time 5.23 seconds
Started Jul 26 05:37:14 PM PDT 24
Finished Jul 26 05:37:19 PM PDT 24
Peak memory 211732 kb
Host smart-21962648-f480-42c2-bd6d-7da0af270a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963071464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1963071464
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1896056889
Short name T227
Test name
Test status
Simulation time 3864832022 ps
CPU time 124.18 seconds
Started Jul 26 05:37:13 PM PDT 24
Finished Jul 26 05:39:17 PM PDT 24
Peak memory 225796 kb
Host smart-3a918a96-b2f4-4971-8175-f6b9751e5ef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896056889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1896056889
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3680761529
Short name T273
Test name
Test status
Simulation time 1034083146 ps
CPU time 11.03 seconds
Started Jul 26 05:37:11 PM PDT 24
Finished Jul 26 05:37:22 PM PDT 24
Peak memory 212796 kb
Host smart-6fe47868-8f5f-49f6-9c31-70e224c1c950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680761529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3680761529
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1057842693
Short name T192
Test name
Test status
Simulation time 277239940 ps
CPU time 6.52 seconds
Started Jul 26 05:37:14 PM PDT 24
Finished Jul 26 05:37:21 PM PDT 24
Peak memory 211896 kb
Host smart-0b1a3b76-f3be-4e74-b3ca-0904d9de8224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057842693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1057842693
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1188088751
Short name T264
Test name
Test status
Simulation time 263364780 ps
CPU time 12.03 seconds
Started Jul 26 05:37:15 PM PDT 24
Finished Jul 26 05:37:27 PM PDT 24
Peak memory 212912 kb
Host smart-107a804d-5d6c-4d90-8f1c-212f4c869d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188088751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1188088751
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1070634945
Short name T71
Test name
Test status
Simulation time 2764945399 ps
CPU time 33.09 seconds
Started Jul 26 05:37:12 PM PDT 24
Finished Jul 26 05:37:45 PM PDT 24
Peak memory 216916 kb
Host smart-53e0e0d7-2223-4ff4-b802-874178b44749
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070634945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1070634945
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1205827282
Short name T275
Test name
Test status
Simulation time 27326644806 ps
CPU time 975.24 seconds
Started Jul 26 05:37:21 PM PDT 24
Finished Jul 26 05:53:37 PM PDT 24
Peak memory 230752 kb
Host smart-094c0290-f75e-40ec-8c5b-f3e7f764f6a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205827282 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1205827282
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2160500622
Short name T327
Test name
Test status
Simulation time 518558240 ps
CPU time 5.1 seconds
Started Jul 26 05:37:26 PM PDT 24
Finished Jul 26 05:37:31 PM PDT 24
Peak memory 211692 kb
Host smart-a7ade153-c518-4f66-a84f-46b874b4fd3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160500622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2160500622
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1026835397
Short name T175
Test name
Test status
Simulation time 1130331479 ps
CPU time 53.43 seconds
Started Jul 26 05:37:25 PM PDT 24
Finished Jul 26 05:38:19 PM PDT 24
Peak memory 213040 kb
Host smart-56775ec5-deea-44c4-ac7c-ab67bdb2b756
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026835397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1026835397
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3048208868
Short name T350
Test name
Test status
Simulation time 1083488623 ps
CPU time 10.92 seconds
Started Jul 26 05:37:31 PM PDT 24
Finished Jul 26 05:37:42 PM PDT 24
Peak memory 212628 kb
Host smart-52a5f8ac-aa85-4bd7-a1e3-0ffab236bea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048208868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3048208868
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3816746883
Short name T140
Test name
Test status
Simulation time 98757641 ps
CPU time 6.09 seconds
Started Jul 26 05:37:13 PM PDT 24
Finished Jul 26 05:37:19 PM PDT 24
Peak memory 211840 kb
Host smart-d7e53e59-65cc-4cde-860e-ecc6f3f861f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816746883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3816746883
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3758490517
Short name T167
Test name
Test status
Simulation time 1620474832 ps
CPU time 11.78 seconds
Started Jul 26 05:37:23 PM PDT 24
Finished Jul 26 05:37:35 PM PDT 24
Peak memory 214712 kb
Host smart-998213ed-38de-443f-a6e2-adbdccb72559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758490517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3758490517
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4239512784
Short name T238
Test name
Test status
Simulation time 398794756 ps
CPU time 22.66 seconds
Started Jul 26 05:37:15 PM PDT 24
Finished Jul 26 05:37:38 PM PDT 24
Peak memory 214792 kb
Host smart-37a19679-766e-4109-85a2-ad9462dc3e86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239512784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4239512784
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1640447703
Short name T13
Test name
Test status
Simulation time 84704942939 ps
CPU time 3262.1 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 06:31:51 PM PDT 24
Peak memory 252692 kb
Host smart-a9830a57-7982-495a-8405-ab629e215bf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640447703 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1640447703
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3909482478
Short name T332
Test name
Test status
Simulation time 133010075 ps
CPU time 5.01 seconds
Started Jul 26 05:37:25 PM PDT 24
Finished Jul 26 05:37:31 PM PDT 24
Peak memory 211632 kb
Host smart-f6ac1515-638b-46c4-bd19-add4a8b60bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909482478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3909482478
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2747238185
Short name T269
Test name
Test status
Simulation time 1890223244 ps
CPU time 50.97 seconds
Started Jul 26 05:37:27 PM PDT 24
Finished Jul 26 05:38:18 PM PDT 24
Peak memory 228132 kb
Host smart-7be1a4a5-ed23-415b-8b3a-d395e36a947f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747238185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2747238185
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3499390017
Short name T379
Test name
Test status
Simulation time 1127529746 ps
CPU time 11.03 seconds
Started Jul 26 05:37:26 PM PDT 24
Finished Jul 26 05:37:37 PM PDT 24
Peak memory 212604 kb
Host smart-6619c573-72bc-4887-abd0-156e356c0b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499390017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3499390017
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1013180908
Short name T153
Test name
Test status
Simulation time 278043892 ps
CPU time 6.14 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:35 PM PDT 24
Peak memory 211548 kb
Host smart-1f64ac8f-e11c-4382-840c-c4dfe32cccd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1013180908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1013180908
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2870676505
Short name T139
Test name
Test status
Simulation time 1616707181 ps
CPU time 12.44 seconds
Started Jul 26 05:37:27 PM PDT 24
Finished Jul 26 05:37:40 PM PDT 24
Peak memory 214036 kb
Host smart-7162e6bc-a6b4-4fc1-aa58-42cb38dc7d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870676505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2870676505
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1934644456
Short name T294
Test name
Test status
Simulation time 127156791 ps
CPU time 6.5 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:34 PM PDT 24
Peak memory 211812 kb
Host smart-fd053c26-e80e-493e-a4e5-8b48d254c481
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934644456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1934644456
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2061971680
Short name T314
Test name
Test status
Simulation time 27445027131 ps
CPU time 10425.3 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 08:31:15 PM PDT 24
Peak memory 236280 kb
Host smart-d57cdb49-9db0-4533-9bb9-f2568f7f433e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061971680 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2061971680
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3515641096
Short name T128
Test name
Test status
Simulation time 176678626 ps
CPU time 4.06 seconds
Started Jul 26 05:37:24 PM PDT 24
Finished Jul 26 05:37:28 PM PDT 24
Peak memory 211744 kb
Host smart-3adae729-242a-4f18-ae01-84259d424a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515641096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3515641096
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2111989882
Short name T279
Test name
Test status
Simulation time 4018851505 ps
CPU time 144.42 seconds
Started Jul 26 05:37:30 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 214108 kb
Host smart-8c2031b4-2ccc-4ef0-8f8f-2eae86fb1fae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111989882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2111989882
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2078224136
Short name T348
Test name
Test status
Simulation time 1044459819 ps
CPU time 11.46 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:40 PM PDT 24
Peak memory 213180 kb
Host smart-260314ba-7fc4-4f37-bb06-f032dcdc1471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078224136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2078224136
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1758177234
Short name T199
Test name
Test status
Simulation time 728200681 ps
CPU time 5.68 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:34 PM PDT 24
Peak memory 211772 kb
Host smart-b569557a-1e70-4a08-bf1e-a999455b7230
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1758177234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1758177234
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3210385061
Short name T310
Test name
Test status
Simulation time 996984861 ps
CPU time 17.4 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:46 PM PDT 24
Peak memory 213600 kb
Host smart-933ee241-bbe2-4121-a1ad-0213d1d0b00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210385061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3210385061
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3351783457
Short name T193
Test name
Test status
Simulation time 1766999420 ps
CPU time 20.14 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:48 PM PDT 24
Peak memory 216932 kb
Host smart-33975aed-8218-420f-978f-f066c3f4a312
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351783457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3351783457
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2318331106
Short name T158
Test name
Test status
Simulation time 17062380248 ps
CPU time 687.38 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:48:55 PM PDT 24
Peak memory 236352 kb
Host smart-1cb792bb-b834-4851-b542-f5771f28a38e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318331106 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2318331106
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.569289388
Short name T355
Test name
Test status
Simulation time 333977769 ps
CPU time 4.09 seconds
Started Jul 26 05:37:25 PM PDT 24
Finished Jul 26 05:37:29 PM PDT 24
Peak memory 211716 kb
Host smart-f6e735dd-86c9-4079-9553-755a1e06b940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569289388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.569289388
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3142036956
Short name T241
Test name
Test status
Simulation time 11033372374 ps
CPU time 56.56 seconds
Started Jul 26 05:37:26 PM PDT 24
Finished Jul 26 05:38:23 PM PDT 24
Peak memory 234244 kb
Host smart-1635a254-5eea-4a63-bbd3-ae5b84afbba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142036956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3142036956
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1699254010
Short name T382
Test name
Test status
Simulation time 1394644309 ps
CPU time 9.54 seconds
Started Jul 26 05:37:25 PM PDT 24
Finished Jul 26 05:37:35 PM PDT 24
Peak memory 212524 kb
Host smart-cf387a58-5a4b-4db4-8a8c-ce59c7db1483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699254010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1699254010
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1541230972
Short name T296
Test name
Test status
Simulation time 268658901 ps
CPU time 6.39 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:34 PM PDT 24
Peak memory 211788 kb
Host smart-388ec53c-a588-47f2-878d-76e62a122ca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541230972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1541230972
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2390606245
Short name T307
Test name
Test status
Simulation time 553066479 ps
CPU time 12.59 seconds
Started Jul 26 05:37:25 PM PDT 24
Finished Jul 26 05:37:38 PM PDT 24
Peak memory 214268 kb
Host smart-e46825b0-4def-4ad8-a784-54ac05d419be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390606245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2390606245
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3308869920
Short name T185
Test name
Test status
Simulation time 508517111 ps
CPU time 26.43 seconds
Started Jul 26 05:37:26 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 213120 kb
Host smart-22d9bd3d-89d0-4ef6-8bef-dcb9acb7df25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308869920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3308869920
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1443254340
Short name T155
Test name
Test status
Simulation time 1978681633 ps
CPU time 7.44 seconds
Started Jul 26 05:37:24 PM PDT 24
Finished Jul 26 05:37:31 PM PDT 24
Peak memory 211784 kb
Host smart-9d21525d-8fb8-41ce-ab98-c1dba33eb0f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443254340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1443254340
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3712375548
Short name T170
Test name
Test status
Simulation time 1784770533 ps
CPU time 100.6 seconds
Started Jul 26 05:37:25 PM PDT 24
Finished Jul 26 05:39:06 PM PDT 24
Peak memory 233088 kb
Host smart-72fc27a1-0b0e-49cd-b265-d04f54903a0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712375548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3712375548
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1064994831
Short name T365
Test name
Test status
Simulation time 1968255513 ps
CPU time 16.25 seconds
Started Jul 26 05:37:23 PM PDT 24
Finished Jul 26 05:37:40 PM PDT 24
Peak memory 212628 kb
Host smart-95baa581-7049-4339-94a2-5b71e64b9b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064994831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1064994831
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.946785761
Short name T242
Test name
Test status
Simulation time 987815223 ps
CPU time 9.03 seconds
Started Jul 26 05:37:31 PM PDT 24
Finished Jul 26 05:37:41 PM PDT 24
Peak memory 211900 kb
Host smart-c4135e86-b136-4aa4-8d28-572803c5e0a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946785761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.946785761
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1394578834
Short name T244
Test name
Test status
Simulation time 757568627 ps
CPU time 9.74 seconds
Started Jul 26 05:37:25 PM PDT 24
Finished Jul 26 05:37:35 PM PDT 24
Peak memory 214260 kb
Host smart-31903230-4363-4299-aafc-6dd2d56b317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394578834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1394578834
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.116317962
Short name T347
Test name
Test status
Simulation time 562278775 ps
CPU time 27.39 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 216664 kb
Host smart-f32d5c62-a781-4d7d-9e99-9935eb61ec8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116317962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.116317962
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1486802127
Short name T368
Test name
Test status
Simulation time 58466674152 ps
CPU time 2489.97 seconds
Started Jul 26 05:37:24 PM PDT 24
Finished Jul 26 06:18:54 PM PDT 24
Peak memory 244568 kb
Host smart-cfcdc4f5-25ef-4489-8261-2cd400a53f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486802127 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1486802127
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3949996705
Short name T168
Test name
Test status
Simulation time 519194267 ps
CPU time 5.14 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:36:43 PM PDT 24
Peak memory 211720 kb
Host smart-8eb1dc58-53de-43a5-b129-861def877f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949996705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3949996705
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3568747755
Short name T324
Test name
Test status
Simulation time 2140124999 ps
CPU time 119.09 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:38:36 PM PDT 24
Peak memory 233728 kb
Host smart-acceca78-7082-4ac5-9fb6-c3a73fe24a44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568747755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3568747755
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3427021086
Short name T274
Test name
Test status
Simulation time 1387806513 ps
CPU time 9.64 seconds
Started Jul 26 05:36:31 PM PDT 24
Finished Jul 26 05:36:41 PM PDT 24
Peak memory 212892 kb
Host smart-97de6339-5a32-4db5-a6a8-bdc027a104e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427021086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3427021086
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1295126679
Short name T112
Test name
Test status
Simulation time 233167498 ps
CPU time 5.19 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:36:45 PM PDT 24
Peak memory 211900 kb
Host smart-9bbc5d33-5a9b-465d-8da6-16a48584d7ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295126679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1295126679
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2839665539
Short name T278
Test name
Test status
Simulation time 1099379226 ps
CPU time 11.99 seconds
Started Jul 26 05:36:44 PM PDT 24
Finished Jul 26 05:36:56 PM PDT 24
Peak memory 213256 kb
Host smart-0e2fc2df-031e-4130-9f43-437810f49257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839665539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2839665539
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3166743012
Short name T219
Test name
Test status
Simulation time 248912529 ps
CPU time 5.15 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:34 PM PDT 24
Peak memory 211776 kb
Host smart-606428db-8794-44a2-ba21-bf3ffc5b3f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166743012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3166743012
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1677394468
Short name T124
Test name
Test status
Simulation time 3140691626 ps
CPU time 86.45 seconds
Started Jul 26 05:37:27 PM PDT 24
Finished Jul 26 05:38:53 PM PDT 24
Peak memory 226144 kb
Host smart-14b5fc2a-8d23-490b-8362-e90c50113f18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677394468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1677394468
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3401785677
Short name T357
Test name
Test status
Simulation time 1040117900 ps
CPU time 10.94 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:39 PM PDT 24
Peak memory 212628 kb
Host smart-9a33a788-7c0e-4658-a54f-cc1e451e0fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401785677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3401785677
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2861148345
Short name T292
Test name
Test status
Simulation time 148906927 ps
CPU time 5.55 seconds
Started Jul 26 05:37:31 PM PDT 24
Finished Jul 26 05:37:37 PM PDT 24
Peak memory 211900 kb
Host smart-3d47307b-d96e-4192-b7ce-e29522a6259d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861148345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2861148345
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.218795533
Short name T151
Test name
Test status
Simulation time 272287329 ps
CPU time 12.28 seconds
Started Jul 26 05:37:31 PM PDT 24
Finished Jul 26 05:37:44 PM PDT 24
Peak memory 214104 kb
Host smart-c12fc011-7c77-4817-a6b1-b5a05e2c4490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218795533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.218795533
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4276127404
Short name T237
Test name
Test status
Simulation time 202930361 ps
CPU time 13.5 seconds
Started Jul 26 05:37:24 PM PDT 24
Finished Jul 26 05:37:38 PM PDT 24
Peak memory 214436 kb
Host smart-7247d61a-5ac9-44ba-8e5e-aaa09ae191bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276127404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4276127404
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1676350747
Short name T333
Test name
Test status
Simulation time 1249411231 ps
CPU time 4.96 seconds
Started Jul 26 05:37:30 PM PDT 24
Finished Jul 26 05:37:35 PM PDT 24
Peak memory 211768 kb
Host smart-d481fd16-981d-43ad-84e2-8423eca08b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676350747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1676350747
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.926026674
Short name T325
Test name
Test status
Simulation time 5049881196 ps
CPU time 142.46 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:39:51 PM PDT 24
Peak memory 235148 kb
Host smart-69dec249-ceaf-4f52-a8c0-356e783537be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926026674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.926026674
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2222957253
Short name T143
Test name
Test status
Simulation time 926119372 ps
CPU time 10.94 seconds
Started Jul 26 05:37:30 PM PDT 24
Finished Jul 26 05:37:41 PM PDT 24
Peak memory 212708 kb
Host smart-ff8c6724-b460-4f96-a7d4-8366a1a97441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222957253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2222957253
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2851235059
Short name T220
Test name
Test status
Simulation time 143608809 ps
CPU time 6.47 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:36 PM PDT 24
Peak memory 211836 kb
Host smart-78c94a1f-a0b9-4060-8d06-ceb59b060497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851235059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2851235059
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3673595433
Short name T217
Test name
Test status
Simulation time 357608407 ps
CPU time 10.01 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:38 PM PDT 24
Peak memory 214124 kb
Host smart-26b8c6d3-3dd8-4c76-b60b-4ebedc10fa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673595433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3673595433
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.615284943
Short name T339
Test name
Test status
Simulation time 871184631 ps
CPU time 12.44 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:40 PM PDT 24
Peak memory 214652 kb
Host smart-b5d9f75d-d8c4-49f8-8420-f121f6b866bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615284943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.615284943
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3419642477
Short name T319
Test name
Test status
Simulation time 521018750 ps
CPU time 4.36 seconds
Started Jul 26 05:37:27 PM PDT 24
Finished Jul 26 05:37:31 PM PDT 24
Peak memory 211764 kb
Host smart-f6bda7db-1dfb-4644-bd82-2864f5a8aa23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419642477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3419642477
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1078085123
Short name T253
Test name
Test status
Simulation time 8240483483 ps
CPU time 106.95 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:39:16 PM PDT 24
Peak memory 225908 kb
Host smart-ffdd09d0-1561-4059-9431-658aa88ef0e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078085123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1078085123
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1678885871
Short name T29
Test name
Test status
Simulation time 513581049 ps
CPU time 11.15 seconds
Started Jul 26 05:37:32 PM PDT 24
Finished Jul 26 05:37:43 PM PDT 24
Peak memory 212652 kb
Host smart-98c3c8b4-f771-46ea-9a9d-8ec2059b03f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678885871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1678885871
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1671791509
Short name T201
Test name
Test status
Simulation time 704953621 ps
CPU time 6.46 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:35 PM PDT 24
Peak memory 211872 kb
Host smart-3933309e-6e99-4626-8fa5-c1320186d8b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671791509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1671791509
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1014087234
Short name T323
Test name
Test status
Simulation time 1029046982 ps
CPU time 11.8 seconds
Started Jul 26 05:37:30 PM PDT 24
Finished Jul 26 05:37:42 PM PDT 24
Peak memory 211824 kb
Host smart-de25e8b7-7dcf-4eb3-a6f7-632e416e57c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014087234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1014087234
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.227547648
Short name T362
Test name
Test status
Simulation time 421090610 ps
CPU time 20.08 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:49 PM PDT 24
Peak memory 214056 kb
Host smart-bc889ca3-b4b0-48f0-a58c-c07b695aae18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227547648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.227547648
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1037752885
Short name T96
Test name
Test status
Simulation time 215116017405 ps
CPU time 1012.04 seconds
Started Jul 26 05:37:30 PM PDT 24
Finished Jul 26 05:54:23 PM PDT 24
Peak memory 234564 kb
Host smart-2e5fc54b-de3f-4bca-9b53-24f7f35ebfda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037752885 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1037752885
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.241622199
Short name T299
Test name
Test status
Simulation time 553627753 ps
CPU time 4.24 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:32 PM PDT 24
Peak memory 211812 kb
Host smart-a6384392-341f-4f30-83c6-de9929e62021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241622199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.241622199
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4082407625
Short name T37
Test name
Test status
Simulation time 1839991833 ps
CPU time 86.03 seconds
Started Jul 26 05:37:31 PM PDT 24
Finished Jul 26 05:38:58 PM PDT 24
Peak memory 225004 kb
Host smart-e6a82dc6-0e74-4524-96e1-f67686070f12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082407625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4082407625
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.150599381
Short name T134
Test name
Test status
Simulation time 727581257 ps
CPU time 9.58 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:39 PM PDT 24
Peak memory 212804 kb
Host smart-c80a4d86-c939-4627-ac4a-a3733c5d2cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150599381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.150599381
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1330544884
Short name T180
Test name
Test status
Simulation time 193852002 ps
CPU time 5.28 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:34 PM PDT 24
Peak memory 211820 kb
Host smart-e96859bb-3766-4c0c-ab5f-8ed12a48257d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330544884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1330544884
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1627394484
Short name T320
Test name
Test status
Simulation time 277256795 ps
CPU time 11.95 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:40 PM PDT 24
Peak memory 212712 kb
Host smart-5feee3b6-703d-41de-aab6-eb401b55e1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627394484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1627394484
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1558570366
Short name T257
Test name
Test status
Simulation time 1012147406 ps
CPU time 12.92 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:42 PM PDT 24
Peak memory 214556 kb
Host smart-cece4e4a-8128-46bb-926d-98bf6e644c36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558570366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1558570366
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.983205688
Short name T377
Test name
Test status
Simulation time 19330841118 ps
CPU time 561.29 seconds
Started Jul 26 05:37:26 PM PDT 24
Finished Jul 26 05:46:48 PM PDT 24
Peak memory 222628 kb
Host smart-127b0b4c-c926-4ce4-9fbe-cdc2f710777d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983205688 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.983205688
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2600046209
Short name T184
Test name
Test status
Simulation time 257225490 ps
CPU time 5.15 seconds
Started Jul 26 05:37:39 PM PDT 24
Finished Jul 26 05:37:44 PM PDT 24
Peak memory 211740 kb
Host smart-80b5fdc0-6d7c-4e35-9eb6-ebbf6646b2af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600046209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2600046209
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4196786844
Short name T203
Test name
Test status
Simulation time 2846963012 ps
CPU time 128.74 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:39:37 PM PDT 24
Peak memory 213080 kb
Host smart-684cb304-e6e4-4183-b6ac-f0cdfc8a00f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196786844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4196786844
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1276449913
Short name T317
Test name
Test status
Simulation time 254903413 ps
CPU time 11.07 seconds
Started Jul 26 05:37:32 PM PDT 24
Finished Jul 26 05:37:43 PM PDT 24
Peak memory 212540 kb
Host smart-0f7e9a72-bd95-44db-bf65-db19d6a53109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276449913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1276449913
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3246947653
Short name T225
Test name
Test status
Simulation time 141736357 ps
CPU time 6.58 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 211860 kb
Host smart-f2cd4178-3bca-44bc-bf5a-1ed3e81cf8ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3246947653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3246947653
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3459576086
Short name T301
Test name
Test status
Simulation time 187508702 ps
CPU time 10.47 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:40 PM PDT 24
Peak memory 214228 kb
Host smart-dd303a56-9f02-468f-b208-4e2743b4c84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459576086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3459576086
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.538197090
Short name T306
Test name
Test status
Simulation time 3388583183 ps
CPU time 38.72 seconds
Started Jul 26 05:37:32 PM PDT 24
Finished Jul 26 05:38:10 PM PDT 24
Peak memory 216704 kb
Host smart-e0f3ea42-d378-44ae-b7eb-c5c3d34457c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538197090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.538197090
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.412304521
Short name T331
Test name
Test status
Simulation time 17170065953 ps
CPU time 715.9 seconds
Started Jul 26 05:37:32 PM PDT 24
Finished Jul 26 05:49:28 PM PDT 24
Peak memory 228156 kb
Host smart-49d47810-d46b-4ac1-b805-e9877babdd97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412304521 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.412304521
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3825091503
Short name T353
Test name
Test status
Simulation time 127317906 ps
CPU time 5.25 seconds
Started Jul 26 05:37:26 PM PDT 24
Finished Jul 26 05:37:31 PM PDT 24
Peak memory 211764 kb
Host smart-4a7f09b3-4c94-44b9-a7c4-9a19bd7a3045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825091503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3825091503
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2207392501
Short name T30
Test name
Test status
Simulation time 252029296 ps
CPU time 11.4 seconds
Started Jul 26 05:37:43 PM PDT 24
Finished Jul 26 05:37:54 PM PDT 24
Peak memory 212456 kb
Host smart-e9d3b825-6a34-4964-a7e7-db50cdab9e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207392501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2207392501
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.488760711
Short name T234
Test name
Test status
Simulation time 99531318 ps
CPU time 5.6 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:35 PM PDT 24
Peak memory 211872 kb
Host smart-b58f535d-5c64-486a-ae3f-5cf4bccc8262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488760711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.488760711
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3508711997
Short name T126
Test name
Test status
Simulation time 528226106 ps
CPU time 11.78 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:41 PM PDT 24
Peak memory 214244 kb
Host smart-e50df86b-9f28-436e-8495-dc6aaf9b701a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508711997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3508711997
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4278696475
Short name T31
Test name
Test status
Simulation time 231297847 ps
CPU time 7.19 seconds
Started Jul 26 05:37:32 PM PDT 24
Finished Jul 26 05:37:39 PM PDT 24
Peak memory 211812 kb
Host smart-82055155-93b0-4944-b51f-fad59ca06912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278696475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4278696475
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2962000113
Short name T250
Test name
Test status
Simulation time 11249996054 ps
CPU time 2940.75 seconds
Started Jul 26 05:37:30 PM PDT 24
Finished Jul 26 06:26:31 PM PDT 24
Peak memory 228136 kb
Host smart-318a4b1e-3d8e-4f64-9ebd-19740e421de8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962000113 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2962000113
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2257405191
Short name T356
Test name
Test status
Simulation time 137452177 ps
CPU time 5 seconds
Started Jul 26 05:37:26 PM PDT 24
Finished Jul 26 05:37:31 PM PDT 24
Peak memory 211664 kb
Host smart-17a21e0d-53e6-450c-914f-6f6701bdbd25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257405191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2257405191
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.542034837
Short name T258
Test name
Test status
Simulation time 20545604489 ps
CPU time 105.74 seconds
Started Jul 26 05:37:27 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 234140 kb
Host smart-800f1c33-d0dc-448c-8742-a68a5ded86a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542034837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.542034837
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1387637796
Short name T277
Test name
Test status
Simulation time 925083855 ps
CPU time 9.39 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:38 PM PDT 24
Peak memory 212624 kb
Host smart-d252d27d-6d91-4cc8-87c8-4c5af563561e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387637796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1387637796
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2720685292
Short name T136
Test name
Test status
Simulation time 408273393 ps
CPU time 5.7 seconds
Started Jul 26 05:37:24 PM PDT 24
Finished Jul 26 05:37:30 PM PDT 24
Peak memory 211916 kb
Host smart-619bcf5b-b60c-4955-8902-7bbd65814482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720685292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2720685292
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2312716442
Short name T284
Test name
Test status
Simulation time 393429796 ps
CPU time 11.64 seconds
Started Jul 26 05:37:24 PM PDT 24
Finished Jul 26 05:37:36 PM PDT 24
Peak memory 214108 kb
Host smart-fa1d56bb-e817-42c4-a321-c0020cf3da0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312716442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2312716442
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3875106039
Short name T247
Test name
Test status
Simulation time 382155297 ps
CPU time 10.07 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 05:37:39 PM PDT 24
Peak memory 215484 kb
Host smart-5ad776aa-065a-40d1-8a72-d37e14c70564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875106039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3875106039
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1725218808
Short name T95
Test name
Test status
Simulation time 218620412408 ps
CPU time 2127.83 seconds
Started Jul 26 05:37:29 PM PDT 24
Finished Jul 26 06:12:58 PM PDT 24
Peak memory 244536 kb
Host smart-c8199463-3f92-485e-ba46-6a8740a556ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725218808 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1725218808
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3437857199
Short name T138
Test name
Test status
Simulation time 175531111 ps
CPU time 4.39 seconds
Started Jul 26 05:37:25 PM PDT 24
Finished Jul 26 05:37:30 PM PDT 24
Peak memory 211680 kb
Host smart-43d41bd3-afb1-40d9-b0c9-7f5654726f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437857199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3437857199
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.212497466
Short name T216
Test name
Test status
Simulation time 4111016943 ps
CPU time 131.41 seconds
Started Jul 26 05:37:25 PM PDT 24
Finished Jul 26 05:39:36 PM PDT 24
Peak memory 238244 kb
Host smart-e7b07f61-2d9e-459d-a94e-9ed7bba3109c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212497466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.212497466
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.917828100
Short name T210
Test name
Test status
Simulation time 261594329 ps
CPU time 9.53 seconds
Started Jul 26 05:37:28 PM PDT 24
Finished Jul 26 05:37:38 PM PDT 24
Peak memory 212680 kb
Host smart-27399128-26d9-429f-8ea2-80ea2580f2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917828100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.917828100
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4113733940
Short name T360
Test name
Test status
Simulation time 193256807 ps
CPU time 5.49 seconds
Started Jul 26 05:37:25 PM PDT 24
Finished Jul 26 05:37:31 PM PDT 24
Peak memory 211880 kb
Host smart-79a971a0-155a-46d9-b8be-afeb9fc6463e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113733940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4113733940
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.458671918
Short name T381
Test name
Test status
Simulation time 516118622 ps
CPU time 11.92 seconds
Started Jul 26 05:37:30 PM PDT 24
Finished Jul 26 05:37:43 PM PDT 24
Peak memory 213464 kb
Host smart-4bd49284-7b45-47fe-85e7-c31713bfb874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458671918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.458671918
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1620812111
Short name T142
Test name
Test status
Simulation time 460833774 ps
CPU time 20.52 seconds
Started Jul 26 05:37:22 PM PDT 24
Finished Jul 26 05:37:42 PM PDT 24
Peak memory 215800 kb
Host smart-32e0cd71-824e-405b-9421-b41abc1bb003
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620812111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1620812111
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1194936382
Short name T120
Test name
Test status
Simulation time 498477755 ps
CPU time 5.11 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:37:47 PM PDT 24
Peak memory 211676 kb
Host smart-ada92477-75a4-41a3-b822-a0b1a68fd2a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194936382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1194936382
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3200762196
Short name T345
Test name
Test status
Simulation time 1824792267 ps
CPU time 85.24 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:39:07 PM PDT 24
Peak memory 237136 kb
Host smart-46d993dc-d393-4105-9d92-36e62eac48d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200762196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3200762196
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3718847335
Short name T177
Test name
Test status
Simulation time 172315434 ps
CPU time 9.43 seconds
Started Jul 26 05:37:34 PM PDT 24
Finished Jul 26 05:37:44 PM PDT 24
Peak memory 213040 kb
Host smart-6b6ff8f1-a51c-41ff-ace8-d6b870f018f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718847335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3718847335
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3797426965
Short name T148
Test name
Test status
Simulation time 193768864 ps
CPU time 5.56 seconds
Started Jul 26 05:37:39 PM PDT 24
Finished Jul 26 05:37:45 PM PDT 24
Peak memory 211880 kb
Host smart-a2eb49a3-d5f8-4756-a36a-3cc4a5819703
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797426965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3797426965
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.578258396
Short name T164
Test name
Test status
Simulation time 295936443 ps
CPU time 11.53 seconds
Started Jul 26 05:37:26 PM PDT 24
Finished Jul 26 05:37:38 PM PDT 24
Peak memory 214624 kb
Host smart-f094b79a-0653-4225-bc26-3de1cd22feb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578258396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.578258396
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.729739664
Short name T2
Test name
Test status
Simulation time 1595013873 ps
CPU time 28.66 seconds
Started Jul 26 05:37:24 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 216740 kb
Host smart-4e483f09-fa9e-4c7c-8ab3-fb0ba3ed4c5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729739664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.729739664
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3067590357
Short name T318
Test name
Test status
Simulation time 171641171 ps
CPU time 4.22 seconds
Started Jul 26 05:37:41 PM PDT 24
Finished Jul 26 05:37:45 PM PDT 24
Peak memory 211788 kb
Host smart-3a1aa574-8de0-4d89-b813-43b577a08b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067590357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3067590357
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4212951504
Short name T20
Test name
Test status
Simulation time 1459691400 ps
CPU time 85.46 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:39:08 PM PDT 24
Peak memory 237840 kb
Host smart-ced98670-e7c0-454d-aa84-828abc82dc93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212951504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4212951504
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1432826032
Short name T47
Test name
Test status
Simulation time 1040177262 ps
CPU time 9.32 seconds
Started Jul 26 05:37:45 PM PDT 24
Finished Jul 26 05:37:54 PM PDT 24
Peak memory 212588 kb
Host smart-7d2a15e8-6785-43bb-9c7c-acad20203e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432826032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1432826032
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2272524677
Short name T161
Test name
Test status
Simulation time 99184463 ps
CPU time 5.72 seconds
Started Jul 26 05:37:48 PM PDT 24
Finished Jul 26 05:37:54 PM PDT 24
Peak memory 211900 kb
Host smart-66b08cda-5675-4619-be6d-23adaedc2262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272524677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2272524677
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.110589307
Short name T336
Test name
Test status
Simulation time 849700223 ps
CPU time 9.94 seconds
Started Jul 26 05:37:41 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 214536 kb
Host smart-81d7736f-eedf-4439-97fc-daf2633c2f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110589307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.110589307
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2953928101
Short name T215
Test name
Test status
Simulation time 397577893 ps
CPU time 25.1 seconds
Started Jul 26 05:37:43 PM PDT 24
Finished Jul 26 05:38:09 PM PDT 24
Peak memory 216068 kb
Host smart-461accf3-2b48-403e-8955-bec2f86c66b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953928101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2953928101
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.528370836
Short name T187
Test name
Test status
Simulation time 220073731 ps
CPU time 4.21 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:36:45 PM PDT 24
Peak memory 211728 kb
Host smart-938c64f9-3957-4aa0-afed-a2166aaae2d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528370836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.528370836
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2215246485
Short name T230
Test name
Test status
Simulation time 416759866 ps
CPU time 10.87 seconds
Started Jul 26 05:36:44 PM PDT 24
Finished Jul 26 05:36:55 PM PDT 24
Peak memory 212648 kb
Host smart-07132dff-50b7-4c61-8b01-106171dc408b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215246485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2215246485
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3239097604
Short name T137
Test name
Test status
Simulation time 377398915 ps
CPU time 5.43 seconds
Started Jul 26 05:36:27 PM PDT 24
Finished Jul 26 05:36:33 PM PDT 24
Peak memory 211784 kb
Host smart-1488c87b-2402-47bc-8cce-89eeb3c82878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239097604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3239097604
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2638234785
Short name T22
Test name
Test status
Simulation time 377914758 ps
CPU time 102.17 seconds
Started Jul 26 05:36:42 PM PDT 24
Finished Jul 26 05:38:25 PM PDT 24
Peak memory 238584 kb
Host smart-b7e90ba2-1cc3-4cc9-a724-7bfc395e3a7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638234785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2638234785
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1502472066
Short name T32
Test name
Test status
Simulation time 271015050 ps
CPU time 11.73 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:36:46 PM PDT 24
Peak memory 212700 kb
Host smart-e825329e-eb7a-49b1-8ae2-1d3f6bf7b473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502472066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1502472066
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2432087106
Short name T5
Test name
Test status
Simulation time 181314638 ps
CPU time 7.36 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:36:43 PM PDT 24
Peak memory 211764 kb
Host smart-4fab8a8e-e55e-40a6-9d44-ecfcd2bfc633
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432087106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2432087106
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2243479229
Short name T380
Test name
Test status
Simulation time 133048337 ps
CPU time 5.36 seconds
Started Jul 26 05:37:40 PM PDT 24
Finished Jul 26 05:37:46 PM PDT 24
Peak memory 212004 kb
Host smart-be357b42-11e0-4aea-9687-b9ba4ef82fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243479229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2243479229
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4011932050
Short name T289
Test name
Test status
Simulation time 2671600146 ps
CPU time 143.94 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:40:06 PM PDT 24
Peak memory 228988 kb
Host smart-8d08b35c-9bd8-4e44-bfc9-32be1c1a49f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011932050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4011932050
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3678820151
Short name T121
Test name
Test status
Simulation time 4133482749 ps
CPU time 11.29 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 212520 kb
Host smart-e1db4e93-b7bc-4088-8017-be19b4e001c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678820151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3678820151
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3030538464
Short name T222
Test name
Test status
Simulation time 380941171 ps
CPU time 5.7 seconds
Started Jul 26 05:37:40 PM PDT 24
Finished Jul 26 05:37:46 PM PDT 24
Peak memory 211848 kb
Host smart-902e0cd7-dde3-4a11-8a92-29ca6c8540d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030538464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3030538464
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3811780550
Short name T270
Test name
Test status
Simulation time 1093748418 ps
CPU time 11.5 seconds
Started Jul 26 05:37:46 PM PDT 24
Finished Jul 26 05:37:58 PM PDT 24
Peak memory 213960 kb
Host smart-80243cd2-0b2a-464d-9f88-0189bfa6e312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811780550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3811780550
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1300616047
Short name T308
Test name
Test status
Simulation time 2525243582 ps
CPU time 19.97 seconds
Started Jul 26 05:37:43 PM PDT 24
Finished Jul 26 05:38:03 PM PDT 24
Peak memory 216052 kb
Host smart-f1dac2dc-fa36-4988-8b99-504c5f6f3f27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300616047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1300616047
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3481218165
Short name T114
Test name
Test status
Simulation time 639796799 ps
CPU time 4.18 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:37:47 PM PDT 24
Peak memory 211764 kb
Host smart-14d2d1eb-5039-4a17-8977-90c489f77a7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481218165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3481218165
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.629042155
Short name T328
Test name
Test status
Simulation time 9349839738 ps
CPU time 125.09 seconds
Started Jul 26 05:37:34 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 237172 kb
Host smart-03db2556-446e-40ba-a772-79ef051a8134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629042155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.629042155
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.95995815
Short name T133
Test name
Test status
Simulation time 220479615 ps
CPU time 9.58 seconds
Started Jul 26 05:37:43 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 212688 kb
Host smart-cb706c4d-2093-462d-a6b2-98a7f45d0a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95995815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.95995815
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1551177902
Short name T287
Test name
Test status
Simulation time 166643894 ps
CPU time 6.37 seconds
Started Jul 26 05:37:41 PM PDT 24
Finished Jul 26 05:37:48 PM PDT 24
Peak memory 211852 kb
Host smart-32fb637d-6647-4d9c-b775-2d97bb858f88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1551177902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1551177902
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2168252900
Short name T293
Test name
Test status
Simulation time 189525005 ps
CPU time 10.03 seconds
Started Jul 26 05:37:43 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 214156 kb
Host smart-e3d1d0ec-71dc-475e-ae21-0d1d17cfc48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168252900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2168252900
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.540782397
Short name T263
Test name
Test status
Simulation time 216595483 ps
CPU time 14.36 seconds
Started Jul 26 05:37:35 PM PDT 24
Finished Jul 26 05:37:49 PM PDT 24
Peak memory 212848 kb
Host smart-1a456f1a-573e-4e45-b7e2-09c0921546ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540782397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.540782397
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4117880112
Short name T160
Test name
Test status
Simulation time 2905051466 ps
CPU time 7.56 seconds
Started Jul 26 05:37:41 PM PDT 24
Finished Jul 26 05:37:49 PM PDT 24
Peak memory 211816 kb
Host smart-967208ec-629e-40ae-8d76-317c34d35919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117880112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4117880112
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2353897125
Short name T135
Test name
Test status
Simulation time 13154478077 ps
CPU time 180.96 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:40:44 PM PDT 24
Peak memory 214056 kb
Host smart-932b0097-a916-4ecc-9944-bdd07f1cfdbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353897125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2353897125
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2102510777
Short name T361
Test name
Test status
Simulation time 334833156 ps
CPU time 9.45 seconds
Started Jul 26 05:37:40 PM PDT 24
Finished Jul 26 05:37:49 PM PDT 24
Peak memory 212556 kb
Host smart-5a0bb988-5752-43f1-a02e-116876ea348c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102510777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2102510777
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3887130923
Short name T159
Test name
Test status
Simulation time 146940705 ps
CPU time 5.77 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:50 PM PDT 24
Peak memory 211744 kb
Host smart-20bebe6d-b8ed-4145-b26c-42fa7528920c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887130923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3887130923
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2081463016
Short name T45
Test name
Test status
Simulation time 268190812 ps
CPU time 12.05 seconds
Started Jul 26 05:37:39 PM PDT 24
Finished Jul 26 05:37:51 PM PDT 24
Peak memory 214308 kb
Host smart-03c1b184-5e8a-4e50-8147-a6d1f32cd4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081463016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2081463016
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1966155899
Short name T34
Test name
Test status
Simulation time 667599139 ps
CPU time 11.55 seconds
Started Jul 26 05:37:40 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 214680 kb
Host smart-f379d899-2412-47d7-a60f-12963e444f07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966155899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1966155899
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1978441625
Short name T298
Test name
Test status
Simulation time 334081997 ps
CPU time 4.34 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:49 PM PDT 24
Peak memory 211748 kb
Host smart-b8a912c3-b0ba-4082-b539-314428b4c0de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978441625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1978441625
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1731347028
Short name T283
Test name
Test status
Simulation time 1592822885 ps
CPU time 93.21 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:39:15 PM PDT 24
Peak memory 237192 kb
Host smart-dae27c4c-7106-4d2d-be3d-6e7948b3360c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731347028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1731347028
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2852723752
Short name T141
Test name
Test status
Simulation time 1126485439 ps
CPU time 10.98 seconds
Started Jul 26 05:37:45 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 212668 kb
Host smart-f18c5395-620d-42a4-9cb6-1513fd533ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852723752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2852723752
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3778189834
Short name T91
Test name
Test status
Simulation time 140666821 ps
CPU time 6.34 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:50 PM PDT 24
Peak memory 211880 kb
Host smart-30031d87-29af-4c6e-b532-f9c1be0e516e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778189834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3778189834
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3028236415
Short name T44
Test name
Test status
Simulation time 178229065 ps
CPU time 10.57 seconds
Started Jul 26 05:37:47 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 214196 kb
Host smart-8b68fc1f-f10e-4b44-a7b1-5db49b718042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028236415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3028236415
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3983508176
Short name T154
Test name
Test status
Simulation time 290990342 ps
CPU time 15.33 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:37:58 PM PDT 24
Peak memory 214680 kb
Host smart-189a709f-8f12-42fa-8143-06f172ab3f08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983508176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3983508176
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1314901363
Short name T110
Test name
Test status
Simulation time 159846675 ps
CPU time 5.12 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:37:47 PM PDT 24
Peak memory 211788 kb
Host smart-58873b3f-111f-49de-8636-092af50ee391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314901363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1314901363
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2813960198
Short name T149
Test name
Test status
Simulation time 7971421006 ps
CPU time 110.5 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:39:35 PM PDT 24
Peak memory 238196 kb
Host smart-cbfe479b-ca28-477b-8174-bca953dd5b1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813960198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2813960198
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4183013075
Short name T92
Test name
Test status
Simulation time 554942874 ps
CPU time 6.28 seconds
Started Jul 26 05:37:45 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 211860 kb
Host smart-9b74af7d-2662-448a-8da0-89dff8833300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183013075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4183013075
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1921403212
Short name T343
Test name
Test status
Simulation time 296195851 ps
CPU time 11.95 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:37:54 PM PDT 24
Peak memory 211916 kb
Host smart-70484158-984a-4e91-b1ef-61a44d0a6dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921403212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1921403212
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4097064954
Short name T259
Test name
Test status
Simulation time 628781243 ps
CPU time 24.73 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:38:09 PM PDT 24
Peak memory 216996 kb
Host smart-965a9ad8-c82b-44e3-bcd5-74f664f3a0e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097064954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4097064954
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1643616803
Short name T14
Test name
Test status
Simulation time 76099242037 ps
CPU time 1160.09 seconds
Started Jul 26 05:37:42 PM PDT 24
Finished Jul 26 05:57:02 PM PDT 24
Peak memory 236340 kb
Host smart-67e66855-7947-44bf-87c7-63e40a1ad80f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643616803 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1643616803
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2934652585
Short name T245
Test name
Test status
Simulation time 85605002 ps
CPU time 4.23 seconds
Started Jul 26 05:37:43 PM PDT 24
Finished Jul 26 05:37:47 PM PDT 24
Peak memory 211632 kb
Host smart-4f72dd34-484f-4053-b6f9-aa4d70c75aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934652585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2934652585
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4023327154
Short name T300
Test name
Test status
Simulation time 11495616019 ps
CPU time 145 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:40:09 PM PDT 24
Peak memory 238192 kb
Host smart-76693420-3623-4181-a19e-96755c4cef74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023327154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4023327154
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1024345835
Short name T330
Test name
Test status
Simulation time 183138708 ps
CPU time 9.64 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:54 PM PDT 24
Peak memory 212644 kb
Host smart-3a6083df-3881-4336-b36e-f5a0da102266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024345835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1024345835
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1891447352
Short name T200
Test name
Test status
Simulation time 95903236 ps
CPU time 5.55 seconds
Started Jul 26 05:37:48 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 211900 kb
Host smart-79582fc5-1914-40f2-9594-28e05ec0b808
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1891447352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1891447352
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1099965840
Short name T267
Test name
Test status
Simulation time 350177269 ps
CPU time 9.75 seconds
Started Jul 26 05:37:43 PM PDT 24
Finished Jul 26 05:37:53 PM PDT 24
Peak memory 213728 kb
Host smart-e0cf6ede-3943-476d-8a2f-7f97dcc95abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099965840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1099965840
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1471584374
Short name T165
Test name
Test status
Simulation time 1074887626 ps
CPU time 23.21 seconds
Started Jul 26 05:37:45 PM PDT 24
Finished Jul 26 05:38:08 PM PDT 24
Peak memory 215216 kb
Host smart-d2fdc0fc-1c44-4f4d-aa33-bc91755b9068
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471584374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1471584374
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3406724020
Short name T304
Test name
Test status
Simulation time 134462607 ps
CPU time 5.3 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:50 PM PDT 24
Peak memory 211740 kb
Host smart-01afea64-5b75-4d9e-80ad-458595be3224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406724020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3406724020
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4213670357
Short name T246
Test name
Test status
Simulation time 2398032661 ps
CPU time 124.64 seconds
Started Jul 26 05:37:45 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 238200 kb
Host smart-7a15784c-8163-48fd-b0ca-49f7d011191a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213670357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4213670357
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2581288968
Short name T119
Test name
Test status
Simulation time 342553037 ps
CPU time 9.67 seconds
Started Jul 26 05:37:41 PM PDT 24
Finished Jul 26 05:37:51 PM PDT 24
Peak memory 212776 kb
Host smart-7a496007-8059-41d6-9e95-d47b65d102d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581288968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2581288968
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.424957440
Short name T197
Test name
Test status
Simulation time 1992386263 ps
CPU time 8.53 seconds
Started Jul 26 05:37:43 PM PDT 24
Finished Jul 26 05:37:52 PM PDT 24
Peak memory 211892 kb
Host smart-5572b620-2d18-41d7-9d86-35358057bbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424957440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.424957440
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3920400696
Short name T145
Test name
Test status
Simulation time 574449499 ps
CPU time 11.9 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 214672 kb
Host smart-bfedd2e0-56d8-4962-8fde-907c6227ab74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920400696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3920400696
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.513726938
Short name T27
Test name
Test status
Simulation time 1837910404 ps
CPU time 19.76 seconds
Started Jul 26 05:37:45 PM PDT 24
Finished Jul 26 05:38:05 PM PDT 24
Peak memory 216696 kb
Host smart-63693127-9c03-4c00-995c-00c286376acf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513726938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.513726938
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4025102670
Short name T53
Test name
Test status
Simulation time 33473461983 ps
CPU time 612.1 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:48:01 PM PDT 24
Peak memory 234464 kb
Host smart-de74c0ef-e831-4e3e-94b0-bfd31c6e8ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025102670 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.4025102670
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.916541404
Short name T183
Test name
Test status
Simulation time 781967366 ps
CPU time 5.14 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:37:55 PM PDT 24
Peak memory 211656 kb
Host smart-9cbc808d-4a23-4c04-8a38-9fdd5c2623f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916541404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.916541404
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1330365393
Short name T239
Test name
Test status
Simulation time 3741792800 ps
CPU time 89.55 seconds
Started Jul 26 05:37:52 PM PDT 24
Finished Jul 26 05:39:21 PM PDT 24
Peak memory 233460 kb
Host smart-5e1d8198-e0f6-4326-8167-cab12a9dc03f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330365393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1330365393
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2936234325
Short name T309
Test name
Test status
Simulation time 1455935324 ps
CPU time 10.97 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:38:01 PM PDT 24
Peak memory 212660 kb
Host smart-216de232-b3fa-4af3-a772-2009faf97528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936234325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2936234325
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2990122862
Short name T189
Test name
Test status
Simulation time 113832601 ps
CPU time 5.23 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:37:55 PM PDT 24
Peak memory 211844 kb
Host smart-5556eab1-3a23-4cc3-a045-98c14ce298fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990122862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2990122862
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.242754250
Short name T340
Test name
Test status
Simulation time 357240542 ps
CPU time 9.64 seconds
Started Jul 26 05:37:47 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 214608 kb
Host smart-dcf2224d-ab1b-4c91-b6c8-730a057478e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242754250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.242754250
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3338688736
Short name T256
Test name
Test status
Simulation time 794996380 ps
CPU time 11.83 seconds
Started Jul 26 05:37:46 PM PDT 24
Finished Jul 26 05:37:58 PM PDT 24
Peak memory 213900 kb
Host smart-ae178843-4b4c-48a6-97ff-c141dc4564d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338688736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3338688736
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1636364542
Short name T19
Test name
Test status
Simulation time 20359885655 ps
CPU time 3273.58 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 06:32:24 PM PDT 24
Peak memory 235900 kb
Host smart-12e5362d-518c-496f-bbaf-628eb176f016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636364542 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1636364542
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.543237701
Short name T35
Test name
Test status
Simulation time 2039154662 ps
CPU time 96.12 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:39:26 PM PDT 24
Peak memory 212924 kb
Host smart-3fbea188-5579-4708-ae0b-22c01089930a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543237701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.543237701
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4046584449
Short name T178
Test name
Test status
Simulation time 333952841 ps
CPU time 9.46 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:37:59 PM PDT 24
Peak memory 212708 kb
Host smart-0090bad9-8403-4e76-b537-be0c993a6b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046584449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4046584449
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4078739853
Short name T226
Test name
Test status
Simulation time 159845580 ps
CPU time 6.38 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:37:57 PM PDT 24
Peak memory 211852 kb
Host smart-f95fa381-4e6f-4d9a-85c0-640a4bb31ccb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078739853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4078739853
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1330954643
Short name T179
Test name
Test status
Simulation time 264821974 ps
CPU time 11.5 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 212592 kb
Host smart-7e75d5dc-cd85-430d-a914-e4ad03ac8986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330954643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1330954643
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4186593028
Short name T190
Test name
Test status
Simulation time 702194389 ps
CPU time 6.8 seconds
Started Jul 26 05:37:47 PM PDT 24
Finished Jul 26 05:37:54 PM PDT 24
Peak memory 211988 kb
Host smart-ee9de2a9-60bc-48d4-a95a-b1c2ed7decb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186593028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4186593028
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.317129182
Short name T116
Test name
Test status
Simulation time 88414815 ps
CPU time 4.3 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:37:54 PM PDT 24
Peak memory 211776 kb
Host smart-4309e513-ebf6-48e0-b5b8-c391dc7df422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317129182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.317129182
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2187592967
Short name T17
Test name
Test status
Simulation time 1183895801 ps
CPU time 83.8 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 238216 kb
Host smart-74210a5a-1664-479b-8a3a-75ae4a305b01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187592967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2187592967
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2078139509
Short name T223
Test name
Test status
Simulation time 176022544 ps
CPU time 9.61 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:37:59 PM PDT 24
Peak memory 212700 kb
Host smart-114448b3-c7c1-421a-9cff-85ed479e5882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078139509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2078139509
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2940668031
Short name T146
Test name
Test status
Simulation time 99132269 ps
CPU time 5.8 seconds
Started Jul 26 05:37:50 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 211784 kb
Host smart-09fc8283-7cef-4910-8210-045eebfe111e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2940668031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2940668031
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3052949722
Short name T359
Test name
Test status
Simulation time 276111406 ps
CPU time 11.56 seconds
Started Jul 26 05:37:44 PM PDT 24
Finished Jul 26 05:37:56 PM PDT 24
Peak memory 212772 kb
Host smart-3c7da1fc-2212-4b79-8c3c-bcd7df055a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052949722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3052949722
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3549736835
Short name T42
Test name
Test status
Simulation time 2028021144 ps
CPU time 25.2 seconds
Started Jul 26 05:37:43 PM PDT 24
Finished Jul 26 05:38:08 PM PDT 24
Peak memory 216184 kb
Host smart-0d39b36c-b547-491c-95db-b469fb9f21d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549736835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3549736835
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.715616003
Short name T55
Test name
Test status
Simulation time 29233197404 ps
CPU time 1313.63 seconds
Started Jul 26 05:37:49 PM PDT 24
Finished Jul 26 05:59:43 PM PDT 24
Peak memory 236340 kb
Host smart-87924316-252e-4be7-bc0c-16b6701a45c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715616003 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.715616003
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3030338135
Short name T171
Test name
Test status
Simulation time 490013011 ps
CPU time 4.36 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:36:42 PM PDT 24
Peak memory 211752 kb
Host smart-7bc9a196-3eee-4a9d-94a1-2581d32a4543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030338135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3030338135
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3815190634
Short name T334
Test name
Test status
Simulation time 3862627658 ps
CPU time 113.78 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:38:28 PM PDT 24
Peak memory 234676 kb
Host smart-7ea85b99-9f5c-4f37-a535-4fd2ad87140e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815190634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3815190634
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3451591438
Short name T24
Test name
Test status
Simulation time 267436380 ps
CPU time 10.99 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:36:48 PM PDT 24
Peak memory 212884 kb
Host smart-30fee8ab-1bf5-4b8b-95c0-8510460d2c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451591438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3451591438
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.330636281
Short name T93
Test name
Test status
Simulation time 359966002 ps
CPU time 6.77 seconds
Started Jul 26 05:36:37 PM PDT 24
Finished Jul 26 05:36:45 PM PDT 24
Peak memory 211884 kb
Host smart-dd3487b8-6f3c-454f-ab71-e87485e6aee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330636281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.330636281
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.526051316
Short name T16
Test name
Test status
Simulation time 192777565 ps
CPU time 9.95 seconds
Started Jul 26 05:36:41 PM PDT 24
Finished Jul 26 05:36:51 PM PDT 24
Peak memory 213704 kb
Host smart-fd293f3e-290d-44e1-aca2-7e437b4154be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526051316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.526051316
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2865408923
Short name T125
Test name
Test status
Simulation time 4471094284 ps
CPU time 24.04 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:37:03 PM PDT 24
Peak memory 216824 kb
Host smart-48617ff3-0eaf-4b26-b188-f93b942a4354
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865408923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2865408923
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.593576081
Short name T268
Test name
Test status
Simulation time 16264079170 ps
CPU time 621.37 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:47:01 PM PDT 24
Peak memory 236336 kb
Host smart-8b434ce8-eb00-4ea4-a1c2-8506bb3ce5d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593576081 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.593576081
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3709831801
Short name T372
Test name
Test status
Simulation time 569085676 ps
CPU time 5.01 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:36:43 PM PDT 24
Peak memory 211772 kb
Host smart-377ef843-721b-4129-8149-8e06c5daab76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709831801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3709831801
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1370882531
Short name T338
Test name
Test status
Simulation time 4426013602 ps
CPU time 104.28 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:38:23 PM PDT 24
Peak memory 238004 kb
Host smart-f0a21dc5-442a-4e69-abc7-10482ebade81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370882531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1370882531
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2813071018
Short name T221
Test name
Test status
Simulation time 250964153 ps
CPU time 10.77 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:36:47 PM PDT 24
Peak memory 212620 kb
Host smart-803175d6-242c-4b15-a40e-f531abb573bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813071018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2813071018
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2006562899
Short name T144
Test name
Test status
Simulation time 99782202 ps
CPU time 5.68 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:36:40 PM PDT 24
Peak memory 211896 kb
Host smart-e31494f8-29d1-417a-ab40-829e912ffff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006562899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2006562899
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3507743060
Short name T313
Test name
Test status
Simulation time 1998058210 ps
CPU time 17.46 seconds
Started Jul 26 05:36:34 PM PDT 24
Finished Jul 26 05:36:52 PM PDT 24
Peak memory 214232 kb
Host smart-a5123782-19e3-4df1-ab06-5a388f5a2c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507743060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3507743060
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1681528706
Short name T285
Test name
Test status
Simulation time 3303390015 ps
CPU time 25.93 seconds
Started Jul 26 05:36:31 PM PDT 24
Finished Jul 26 05:36:57 PM PDT 24
Peak memory 217320 kb
Host smart-34acde83-8c55-4d4f-bd25-a0ce0bedd395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681528706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1681528706
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1918617012
Short name T43
Test name
Test status
Simulation time 694986537 ps
CPU time 4.2 seconds
Started Jul 26 05:36:40 PM PDT 24
Finished Jul 26 05:36:45 PM PDT 24
Peak memory 211768 kb
Host smart-1f2f38c4-122f-47f5-81a6-b022f0f6b02e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918617012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1918617012
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1732075844
Short name T352
Test name
Test status
Simulation time 5515522506 ps
CPU time 135.03 seconds
Started Jul 26 05:36:44 PM PDT 24
Finished Jul 26 05:38:59 PM PDT 24
Peak memory 238124 kb
Host smart-a91e4464-34aa-4fd9-a130-db599d883754
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732075844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1732075844
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2752862164
Short name T373
Test name
Test status
Simulation time 168998709 ps
CPU time 9.48 seconds
Started Jul 26 05:36:44 PM PDT 24
Finished Jul 26 05:36:54 PM PDT 24
Peak memory 212592 kb
Host smart-8d3adce2-c4bc-4683-b2fd-676934ae6073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752862164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2752862164
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2483951149
Short name T207
Test name
Test status
Simulation time 377007581 ps
CPU time 5.18 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:36:40 PM PDT 24
Peak memory 211856 kb
Host smart-ce8cc977-39c1-40fd-82d2-1f34598b8635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483951149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2483951149
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.674343120
Short name T232
Test name
Test status
Simulation time 728480250 ps
CPU time 10.18 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:36:50 PM PDT 24
Peak memory 213596 kb
Host smart-e56fc66b-33bb-400d-ae45-257da5c10f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674343120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.674343120
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.872791135
Short name T375
Test name
Test status
Simulation time 1525873138 ps
CPU time 19.97 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:37:00 PM PDT 24
Peak memory 216052 kb
Host smart-ae6bdd8a-55f9-46e5-8af0-a81b92469e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872791135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.872791135
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2079491791
Short name T329
Test name
Test status
Simulation time 18171495494 ps
CPU time 695.52 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:48:11 PM PDT 24
Peak memory 227248 kb
Host smart-7e32a23b-cfcf-40af-9b40-3e9d7c804088
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079491791 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2079491791
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.845990240
Short name T49
Test name
Test status
Simulation time 519372042 ps
CPU time 7.53 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:36:46 PM PDT 24
Peak memory 211776 kb
Host smart-ac00ca53-d955-48ff-8a3b-7e4bb5676f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845990240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.845990240
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2617615895
Short name T276
Test name
Test status
Simulation time 2714912808 ps
CPU time 129.94 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:38:47 PM PDT 24
Peak memory 234172 kb
Host smart-9d769a8d-5b29-4bba-9130-0723fd375cf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617615895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2617615895
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.89660690
Short name T48
Test name
Test status
Simulation time 639608695 ps
CPU time 9.49 seconds
Started Jul 26 05:36:44 PM PDT 24
Finished Jul 26 05:36:54 PM PDT 24
Peak memory 212544 kb
Host smart-1ef7c875-db9d-4412-bff9-fcbd0a01c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89660690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.89660690
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.456139162
Short name T260
Test name
Test status
Simulation time 138588335 ps
CPU time 5.99 seconds
Started Jul 26 05:36:35 PM PDT 24
Finished Jul 26 05:36:41 PM PDT 24
Peak memory 211856 kb
Host smart-eed394f6-e043-4f37-b65e-41bf74491c66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456139162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.456139162
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1963591460
Short name T115
Test name
Test status
Simulation time 370291941 ps
CPU time 9.81 seconds
Started Jul 26 05:36:36 PM PDT 24
Finished Jul 26 05:36:46 PM PDT 24
Peak memory 214200 kb
Host smart-01b4674f-2811-4326-a170-ccfcfcfc079a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963591460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1963591460
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1215148223
Short name T181
Test name
Test status
Simulation time 6131613459 ps
CPU time 29.22 seconds
Started Jul 26 05:36:39 PM PDT 24
Finished Jul 26 05:37:09 PM PDT 24
Peak memory 216120 kb
Host smart-7ff21ef6-793e-42a2-b748-ff5e3f800756
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215148223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1215148223
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2991111286
Short name T218
Test name
Test status
Simulation time 225840670 ps
CPU time 4.97 seconds
Started Jul 26 05:36:46 PM PDT 24
Finished Jul 26 05:36:51 PM PDT 24
Peak memory 211748 kb
Host smart-efd82132-826f-46e2-b19c-5a6f3e9c576b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991111286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2991111286
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4249497719
Short name T282
Test name
Test status
Simulation time 1384015372 ps
CPU time 95.37 seconds
Started Jul 26 05:36:42 PM PDT 24
Finished Jul 26 05:38:18 PM PDT 24
Peak memory 233340 kb
Host smart-8f8cb56c-f5fb-4e2d-b2cd-8bdaa8f03010
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249497719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4249497719
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2240453030
Short name T111
Test name
Test status
Simulation time 1115499465 ps
CPU time 9.39 seconds
Started Jul 26 05:36:48 PM PDT 24
Finished Jul 26 05:36:57 PM PDT 24
Peak memory 212748 kb
Host smart-419e8f5d-48f4-4742-92f1-27c5a42d0b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240453030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2240453030
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1834529238
Short name T249
Test name
Test status
Simulation time 266669524 ps
CPU time 6.12 seconds
Started Jul 26 05:36:42 PM PDT 24
Finished Jul 26 05:36:49 PM PDT 24
Peak memory 211764 kb
Host smart-35bcfdc9-ab25-4ce7-bd50-324261a2e66d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1834529238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1834529238
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1298117690
Short name T209
Test name
Test status
Simulation time 281043902 ps
CPU time 11.84 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:36:51 PM PDT 24
Peak memory 213108 kb
Host smart-757f3809-d719-434f-9f23-d40a4cc775a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298117690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1298117690
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2140468802
Short name T295
Test name
Test status
Simulation time 251398422 ps
CPU time 10.34 seconds
Started Jul 26 05:36:38 PM PDT 24
Finished Jul 26 05:36:49 PM PDT 24
Peak memory 211764 kb
Host smart-16d1fbd7-def6-422c-b05c-a09954b086c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140468802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2140468802
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2856798867
Short name T11
Test name
Test status
Simulation time 48861271736 ps
CPU time 1037.28 seconds
Started Jul 26 05:36:47 PM PDT 24
Finished Jul 26 05:54:04 PM PDT 24
Peak memory 234516 kb
Host smart-3f7f5e80-813d-4aa7-b69d-7e92f2769b35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856798867 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2856798867
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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